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[HC32] Add HC32F4A2/HC32F467 BSP support 

- Add chip macro for driver
 - Modify 'IDLE_THREAD_STACK_SIZE' to 512
 - Modify 'HWTIMER' to 'CLOCK_TIMER'
 - Use 'clang-format' format driver and BSP code
 - Fix SPI clock division configuration
This commit is contained in:
Leeto1970 2026-07-07 10:34:04 +08:00 committed by Rbb666
parent f8a65e4092
commit d513da02db
429 changed files with 66445 additions and 25702 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
.github/ALL_BSP_COMPILE.json vendored
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@ -53,12 +53,14 @@
"at32/at32f457-start",
"at32/at32m412-start",
"at32/at32m416-start",
"hc32/ev_hc32f4a0_lqfp176",
"hc32/ev_hc32f4a8_lqfp176",
"hc32/ev_hc32f334_lqfp64",
"hc32/ev_hc32f448_lqfp80",
"hc32/ev_hc32f460_lqfp100_v2",
"hc32/ev_hc32f467_lqfp144",
"hc32/ev_hc32f472_lqfp100",
"hc32/ev_hc32f4a0_lqfp176",
"hc32/ev_hc32f4a2_lqfp176",
"hc32/ev_hc32f4a8_lqfp176",
"hc32/lckfb-hc32f4a0-lqfp100",
"hc32l196",
"hc32l136",

2
bsp/hc32/docs/HC32系列BSP制作教程.md
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@ -227,7 +227,7 @@ HC32 BSP 的制作规范主要分为 3 个方面：工程配置，ENV 配置和
- 系统心跳统一设置为 1000（宏：RT_TICK_PER_SECOND）
- BSP 中需要打开调试选项中的断言（宏：RT_DEBUG）
- 系统空闲线程栈大小统一设置为 256（宏：IDLE_THREAD_STACK_SIZE）
- 系统空闲线程栈大小统一设置为 512（宏：IDLE_THREAD_STACK_SIZE）
- 开启组件自动初始化（宏：RT_USING_COMPONENTS_INIT）
- 需要开启 user main 选项（宏：RT_USING_USER_MAIN）
- FinSH 默认只使用 MSH 模式（宏：FINSH_USING_MSH_ONLY）

2
bsp/hc32/docs/HC32系列驱动介绍.md
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@ -40,7 +40,7 @@
| 8 | [ADC](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/adc/adc) | 测量管脚上的模拟量 |
| 9 | [DAC](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/dac/dac) | 通过管脚输出模拟量 |
| 10 | [CAN](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/can/can) | 通过 CAN 收发数据 |
| 11 | [HWTIMER](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/hwtimer/hwtimer) | 通过硬件定时器计时 |
| 11 | [CLOCK_TIMER](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/clock_timer/clock_timer) | 通过硬件定时器计时 |
| 12 | [PWM](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/pwm/pwm) | 在特定的管脚输出 PWM 波形 |
| 13 | [RTC](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/rtc/rtc) | 设置和读取时间 |
| 14 | [WDT](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/watchdog/watchdog) | 看门狗驱动 |

4
bsp/hc32/ev_hc32f334_lqfp64/.ci/attachconfig/ci.attachconfig.yml
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@ -24,9 +24,9 @@ devices.flash:
devices.gpio:
kconfig:
- CONFIG_BSP_USING_GPIO=y
devices.hwtimer:
devices.clock_timer:
kconfig:
- CONFIG_BSP_USING_HWTIMER=y
- CONFIG_BSP_USING_CLOCK_TIMER=y
- CONFIG_BSP_USING_TMRA_1=y
devices.i2c:
kconfig:

2
bsp/hc32/ev_hc32f334_lqfp64/.config
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@ -125,7 +125,7 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y
# CONFIG_RT_USING_HOOKLIST is not set
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
CONFIG_IDLE_THREAD_STACK_SIZE=512
# CONFIG_RT_USING_TIMER_SOFT is not set
# CONFIG_RT_USING_CPU_USAGE_TRACER is not set

2
bsp/hc32/ev_hc32f334_lqfp64/README.md
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@ -46,7 +46,7 @@ EV_F334_LQ64 开发板常用 **板载资源** 如下：
| DAC | 支持 | |
| FLASH | 支持 | |
| GPIO | 支持 | PA0，PA1...PF3 ---> PIN：0，1...68 |
| HwTimer | 支持 | |
| CLOCK_TIMER | 支持 | |
| I2C | 支持 | 软件、硬件 I2C |
| InputCapture | 支持 | |
| MCAN | 支持 | |

2
bsp/hc32/ev_hc32f334_lqfp64/applications/main.c
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@ -13,7 +13,7 @@
#include <board.h>
/* defined the LED_BLUE pin: PC13 */
#define LED_BLUE_PIN GET_PIN(C, 13)
#define LED_BLUE_PIN GET_PIN(C, 13)
int main(void)
{

16
bsp/hc32/ev_hc32f334_lqfp64/applications/xtal32_fcm.c
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@ -18,8 +18,8 @@
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
#define XTAL32_FCM_THREAD_STACK_SIZE (1024)
#define XTAL32_FCM_UNIT (CM_FCM)
#define XTAL32_FCM_THREAD_STACK_SIZE (1024)
#define XTAL32_FCM_UNIT (CM_FCM)
/**
* @brief This thread is used to monitor whether XTAL32 is stable.
@ -36,13 +36,13 @@ void xtal32_fcm_thread_entry(void *parameter)
/* FCM config */
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE);
(void)FCM_StructInit(&stcFcmInit);
stcFcmInit.u32RefClock = FCM_REF_CLK_MRC;
stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */
stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING;
stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32;
stcFcmInit.u32RefClock = FCM_REF_CLK_MRC;
stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */
stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING;
stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32;
stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1;
stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
(void)FCM_Init(XTAL32_FCM_UNIT, &stcFcmInit);
/* Enable FCM, to ensure xtal32 stable */
FCM_Cmd(XTAL32_FCM_UNIT, ENABLE);

12
bsp/hc32/ev_hc32f334_lqfp64/board/Kconfig
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@ -528,24 +528,24 @@ menu "On-chip Peripheral Drivers"
endif
menuconfig BSP_USING_CLOCK_TIMER
bool "Enable Hw Timer"
bool "Enable Clock Timer"
default n
select RT_USING_CLOCK_TIME
if BSP_USING_CLOCK_TIMER
config BSP_USING_TMRA_1
bool "Use Timer_a1 As The Hw Timer"
bool "Use Timer_a1 As The Clock Timer"
default n
config BSP_USING_TMRA_2
bool "Use Timer_a2 As The Hw Timer"
bool "Use Timer_a2 As The Clock Timer"
default n
config BSP_USING_TMRA_3
bool "Use Timer_a3 As The Hw Timer"
bool "Use Timer_a3 As The Clock Timer"
default n
config BSP_USING_TMRA_4
bool "Use Timer_a4 As The Hw Timer"
bool "Use Timer_a4 As The Clock Timer"
default n
config BSP_USING_TMRA_5
bool "Use Timer_a5 As The Hw Timer"
bool "Use Timer_a5 As The Clock Timer"
default n
endif

16
bsp/hc32/ev_hc32f334_lqfp64/board/board.c
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@ -12,9 +12,9 @@
#include "board_config.h"
/* unlock/lock peripheral */
#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD)
#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM)
#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD)
#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM)
/** System Base Configuration
*/
@ -54,9 +54,9 @@ void SystemClock_Config(void)
GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE);
(void)CLK_XtalStructInit(&stcXtalInit);
/* Config Xtal and enable Xtal */
stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW;
stcXtalInit.u8State = CLK_XTAL_ON;
stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW;
stcXtalInit.u8State = CLK_XTAL_ON;
stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
(void)CLK_XtalInit(&stcXtalInit);
@ -82,8 +82,8 @@ void SystemClock_Config(void)
/* Xtal32 config */
GPIO_AnalogCmd(XTAL32_PORT, XTAL32_PIN, ENABLE);
(void)CLK_Xtal32StructInit(&stcXtal32Init);
stcXtal32Init.u8State = CLK_XTAL32_ON;
stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH;
stcXtal32Init.u8State = CLK_XTAL32_ON;
stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH;
stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD;
(void)CLK_Xtal32Init(&stcXtal32Init);
#endif

24
bsp/hc32/ev_hc32f334_lqfp64/board/board.h
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@ -19,27 +19,27 @@
extern "C" {
#endif
#define HC32_FLASH_ERASE_GRANULARITY (4 * 1024)
#define HC32_FLASH_WRITE_GRANULARITY (4)
#define HC32_FLASH_SIZE (128 * 1024)
#define HC32_FLASH_START_ADDRESS (0)
#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
#define HC32_FLASH_ERASE_GRANULARITY (4 * 1024)
#define HC32_FLASH_WRITE_GRANULARITY (4)
#define HC32_FLASH_SIZE (128 * 1024)
#define HC32_FLASH_START_ADDRESS (0)
#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
#define HC32_SRAM_SIZE (32)
#define HC32_SRAM_END (0x1FFFC000 + HC32_SRAM_SIZE * 1024)
#define HC32_SRAM_SIZE (32)
#define HC32_SRAM_END (0x1FFFC000 + HC32_SRAM_SIZE * 1024)
#ifdef __ARMCC_VERSION
extern int Image$$RW_IRAM2$$ZI$$Limit;
#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit)
#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit)
#elif __ICCARM__
#pragma section="HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#pragma section = "HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#else
extern int __bss_end;
#define HEAP_BEGIN (&__bss_end)
#define HEAP_BEGIN (&__bss_end)
#endif
#define HEAP_END HC32_SRAM_END
#define HEAP_END HC32_SRAM_END
void PeripheralRegister_Unlock(void);
void PeripheralClock_Config(void);

18
bsp/hc32/ev_hc32f334_lqfp64/board/board_config.c
View File

@ -141,13 +141,13 @@ void CanPhyEnable(void)
#if defined(BSP_USING_MCAN1)
GPIO_StructInit(&stcGpioInit);
stcGpioInit.u16PinState = PIN_STAT_RST;
stcGpioInit.u16PinDir = PIN_DIR_OUT;
stcGpioInit.u16PinDir = PIN_DIR_OUT;
GPIO_Init(MCAN1_PHY_STBY_PORT, MCAN1_PHY_STBY_PIN, &stcGpioInit);
#endif
#if defined(BSP_USING_MCAN2)
GPIO_StructInit(&stcGpioInit);
stcGpioInit.u16PinState = PIN_STAT_RST;
stcGpioInit.u16PinDir = PIN_DIR_OUT;
stcGpioInit.u16PinDir = PIN_DIR_OUT;
GPIO_Init(MCAN2_PHY_STBY_PORT, MCAN2_PHY_STBY_PIN, &stcGpioInit);
#endif
}
@ -179,7 +179,7 @@ rt_err_t rt_hw_board_mcan_init(CM_MCAN_TypeDef *MCANx)
}
#endif
#if defined (RT_USING_SPI)
#if defined(RT_USING_SPI)
rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx)
{
rt_err_t result = RT_EOK;
@ -194,10 +194,10 @@ rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx)
(void)GPIO_StructInit(&stcGpioInit);
stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS;
(void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit);
(void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit);
(void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit);
(void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit);
GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC);
GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC);
GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC);
GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC);
break;
@ -311,24 +311,24 @@ rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x)
#endif
#endif
#if defined (BSP_USING_INPUT_CAPTURE)
#if defined(BSP_USING_INPUT_CAPTURE)
rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance)
{
rt_err_t result = RT_EOK;
switch ((rt_uint32_t)tmr_instance)
{
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1)
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1)
case (rt_uint32_t)CM_TMR6_1:
GPIO_SetFunc(INPUT_CAPTURE_TMR6_1_PORT, INPUT_CAPTURE_TMR6_1_PIN, INPUT_CAPTURE_TMR6_FUNC);
break;
#endif
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2)
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2)
case (rt_uint32_t)CM_TMR6_2:
GPIO_SetFunc(INPUT_CAPTURE_TMR6_2_PORT, INPUT_CAPTURE_TMR6_2_PIN, INPUT_CAPTURE_TMR6_FUNC);
break;
#endif
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3)
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3)
case (rt_uint32_t)CM_TMR6_3:
GPIO_SetFunc(INPUT_CAPTURE_TMR6_3_PORT, INPUT_CAPTURE_TMR6_3_PIN, INPUT_CAPTURE_TMR6_FUNC);
break;

346
bsp/hc32/ev_hc32f334_lqfp64/board/board_config.h
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@ -18,248 +18,248 @@
/************************* XTAL port **********************/
#define XTAL_PORT (GPIO_PORT_F)
#define XTAL_IN_PIN (GPIO_PIN_00)
#define XTAL_OUT_PIN (GPIO_PIN_01)
#define XTAL_PORT (GPIO_PORT_F)
#define XTAL_IN_PIN (GPIO_PIN_00)
#define XTAL_OUT_PIN (GPIO_PIN_01)
/************************ USART port **********************/
#if defined(BSP_USING_UART1)
#define USART1_RX_PORT (GPIO_PORT_B)
#define USART1_RX_PIN (GPIO_PIN_06)
#define USART1_RX_FUNC (GPIO_FUNC_33)
#define USART1_RX_PORT (GPIO_PORT_B)
#define USART1_RX_PIN (GPIO_PIN_06)
#define USART1_RX_FUNC (GPIO_FUNC_33)
#define USART1_TX_PORT (GPIO_PORT_B)
#define USART1_TX_PIN (GPIO_PIN_07)
#define USART1_TX_FUNC (GPIO_FUNC_32)
#define USART1_TX_PORT (GPIO_PORT_B)
#define USART1_TX_PIN (GPIO_PIN_07)
#define USART1_TX_FUNC (GPIO_FUNC_32)
#endif
#if defined(BSP_USING_UART2)
#define USART2_RX_PORT (GPIO_PORT_C)
#define USART2_RX_PIN (GPIO_PIN_04)
#define USART2_RX_FUNC (GPIO_FUNC_37)
#define USART2_RX_PORT (GPIO_PORT_C)
#define USART2_RX_PIN (GPIO_PIN_04)
#define USART2_RX_FUNC (GPIO_FUNC_37)
#define USART2_TX_PORT (GPIO_PORT_C)
#define USART2_TX_PIN (GPIO_PIN_10)
#define USART2_TX_FUNC (GPIO_FUNC_36)
#define USART2_TX_PORT (GPIO_PORT_C)
#define USART2_TX_PIN (GPIO_PIN_10)
#define USART2_TX_FUNC (GPIO_FUNC_36)
#endif
/************************ I2C port **********************/
#if defined(BSP_USING_I2C1)
#define I2C1_SDA_PORT (GPIO_PORT_B)
#define I2C1_SDA_PIN (GPIO_PIN_06)
#define I2C1_SDA_FUNC (GPIO_FUNC_52)
#define I2C1_SDA_PORT (GPIO_PORT_B)
#define I2C1_SDA_PIN (GPIO_PIN_06)
#define I2C1_SDA_FUNC (GPIO_FUNC_52)
#define I2C1_SCL_PORT (GPIO_PORT_B)
#define I2C1_SCL_PIN (GPIO_PIN_07)
#define I2C1_SCL_FUNC (GPIO_FUNC_53)
#define I2C1_SCL_PORT (GPIO_PORT_B)
#define I2C1_SCL_PIN (GPIO_PIN_07)
#define I2C1_SCL_FUNC (GPIO_FUNC_53)
#endif
/*********** ADC configure *********/
#if defined(BSP_USING_ADC1)
#define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC12_IN10 */
#define ADC1_CH_PIN (GPIO_PIN_00)
#define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC12_IN10 */
#define ADC1_CH_PIN (GPIO_PIN_00)
#endif
#if defined(BSP_USING_ADC2)
#define ADC2_CH_PORT (GPIO_PORT_A) /* Default ADC12_IN4 */
#define ADC2_CH_PIN (GPIO_PIN_04)
#define ADC2_CH_PORT (GPIO_PORT_A) /* Default ADC12_IN4 */
#define ADC2_CH_PIN (GPIO_PIN_04)
#endif
#if defined(BSP_USING_ADC3)
#define ADC3_CH_PORT (GPIO_PORT_B) /* Default ADC3_IN1 */
#define ADC3_CH_PIN (GPIO_PIN_13)
#define ADC3_CH_PORT (GPIO_PORT_B) /* Default ADC3_IN1 */
#define ADC3_CH_PIN (GPIO_PIN_13)
#endif
/*********** DAC configure *********/
#if defined(BSP_USING_DAC1)
#define DAC1_CH1_PORT (GPIO_PORT_A)
#define DAC1_CH1_PIN (GPIO_PIN_04)
#define DAC1_CH2_PORT (GPIO_PORT_A)
#define DAC1_CH2_PIN (GPIO_PIN_05)
#define DAC1_CH1_PORT (GPIO_PORT_A)
#define DAC1_CH1_PIN (GPIO_PIN_04)
#define DAC1_CH2_PORT (GPIO_PORT_A)
#define DAC1_CH2_PIN (GPIO_PIN_05)
#endif
#if defined(BSP_USING_DAC2)
#define DAC2_CH1_PORT (GPIO_PORT_A)
#define DAC2_CH1_PIN (GPIO_PIN_06)
#define DAC2_CH1_PORT (GPIO_PORT_A)
#define DAC2_CH1_PIN (GPIO_PIN_06)
#endif
/*********** CAN configure *********/
#if defined(BSP_USING_MCAN1)
#define MCAN1_TX_PORT (GPIO_PORT_A)
#define MCAN1_TX_PIN (GPIO_PIN_02)
#define MCAN1_TX_PIN_FUNC (GPIO_FUNC_54)
#define MCAN1_TX_PORT (GPIO_PORT_A)
#define MCAN1_TX_PIN (GPIO_PIN_02)
#define MCAN1_TX_PIN_FUNC (GPIO_FUNC_54)
#define MCAN1_RX_PORT (GPIO_PORT_C)
#define MCAN1_RX_PIN (GPIO_PIN_05)
#define MCAN1_RX_PIN_FUNC (GPIO_FUNC_55)
#define MCAN1_RX_PORT (GPIO_PORT_C)
#define MCAN1_RX_PIN (GPIO_PIN_05)
#define MCAN1_RX_PIN_FUNC (GPIO_FUNC_55)
#define MCAN1_PHY_STBY_PORT (GPIO_PORT_B)
#define MCAN1_PHY_STBY_PIN (GPIO_PIN_01)
#define MCAN1_PHY_STBY_PORT (GPIO_PORT_B)
#define MCAN1_PHY_STBY_PIN (GPIO_PIN_01)
#endif
#if defined(BSP_USING_MCAN2)
#define MCAN2_TX_PORT (GPIO_PORT_B)
#define MCAN2_TX_PIN (GPIO_PIN_11)
#define MCAN2_TX_PIN_FUNC (GPIO_FUNC_56)
#define MCAN2_TX_PORT (GPIO_PORT_B)
#define MCAN2_TX_PIN (GPIO_PIN_11)
#define MCAN2_TX_PIN_FUNC (GPIO_FUNC_56)
#define MCAN2_RX_PORT (GPIO_PORT_B)
#define MCAN2_RX_PIN (GPIO_PIN_10)
#define MCAN2_RX_PIN_FUNC (GPIO_FUNC_57)
#define MCAN2_RX_PORT (GPIO_PORT_B)
#define MCAN2_RX_PIN (GPIO_PIN_10)
#define MCAN2_RX_PIN_FUNC (GPIO_FUNC_57)
#define MCAN2_PHY_STBY_PORT (GPIO_PORT_B)
#define MCAN2_PHY_STBY_PIN (GPIO_PIN_02)
#define MCAN2_PHY_STBY_PORT (GPIO_PORT_B)
#define MCAN2_PHY_STBY_PIN (GPIO_PIN_02)
#endif
/************************* SPI port ***********************/
#if defined(BSP_USING_SPI1)
#define SPI1_CS_PORT (GPIO_PORT_C)
#define SPI1_CS_PIN (GPIO_PIN_01)
#define SPI1_CS_PORT (GPIO_PORT_C)
#define SPI1_CS_PIN (GPIO_PIN_01)
#define SPI1_SCK_PORT (GPIO_PORT_B)
#define SPI1_SCK_PIN (GPIO_PIN_05)
#define SPI1_SCK_FUNC (GPIO_FUNC_49)
#define SPI1_SCK_PORT (GPIO_PORT_B)
#define SPI1_SCK_PIN (GPIO_PIN_05)
#define SPI1_SCK_FUNC (GPIO_FUNC_49)
#define SPI1_MOSI_PORT (GPIO_PORT_A)
#define SPI1_MOSI_PIN (GPIO_PIN_00)
#define SPI1_MOSI_FUNC (GPIO_FUNC_50)
#define SPI1_MOSI_PORT (GPIO_PORT_A)
#define SPI1_MOSI_PIN (GPIO_PIN_00)
#define SPI1_MOSI_FUNC (GPIO_FUNC_50)
#define SPI1_MISO_PORT (GPIO_PORT_A)
#define SPI1_MISO_PIN (GPIO_PIN_01)
#define SPI1_MISO_FUNC (GPIO_FUNC_51)
#define SPI1_MISO_PORT (GPIO_PORT_A)
#define SPI1_MISO_PIN (GPIO_PIN_01)
#define SPI1_MISO_FUNC (GPIO_FUNC_51)
#endif
/************************ RTC/PM *****************************/
#if defined(BSP_USING_RTC) || defined(RT_USING_PM)
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
#define XTAL32_PORT (GPIO_PORT_C)
#define XTAL32_PIN (GPIO_PIN_14 | GPIO_PIN_15)
#endif
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
#define XTAL32_PORT (GPIO_PORT_C)
#define XTAL32_PIN (GPIO_PIN_14 | GPIO_PIN_15)
#endif
#endif
#if defined(RT_USING_PWM)
/*********** PWM_TMRA configure *********/
#if defined(BSP_USING_PWM_TMRA_1)
#if defined(BSP_USING_PWM_TMRA_1_CH1)
#define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH1_PIN (GPIO_PIN_00)
#define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_15)
#endif
#if defined(BSP_USING_PWM_TMRA_1_CH2)
#define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH2_PIN (GPIO_PIN_01)
#define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_15)
#endif
#if defined(BSP_USING_PWM_TMRA_1_CH3)
#define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH3_PIN (GPIO_PIN_02)
#define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_15)
#endif
#if defined(BSP_USING_PWM_TMRA_1_CH4)
#define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH4_PIN (GPIO_PIN_03)
#define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_15)
#endif
#endif
#if defined(BSP_USING_PWM_TMRA_1)
#if defined(BSP_USING_PWM_TMRA_1_CH1)
#define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH1_PIN (GPIO_PIN_00)
#define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_15)
#endif
#if defined(BSP_USING_PWM_TMRA_1_CH2)
#define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH2_PIN (GPIO_PIN_01)
#define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_15)
#endif
#if defined(BSP_USING_PWM_TMRA_1_CH3)
#define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH3_PIN (GPIO_PIN_02)
#define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_15)
#endif
#if defined(BSP_USING_PWM_TMRA_1_CH4)
#define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH4_PIN (GPIO_PIN_03)
#define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_15)
#endif
#endif
/*********** PWM_TMR4 configure *********/
#if defined(BSP_USING_PWM_TMR4_1)
#if defined(BSP_USING_PWM_TMR4_1_OUH)
#define PWM_TMR4_1_OUH_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OUH_PIN (GPIO_PIN_02)
#define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_20)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OUL)
#define PWM_TMR4_1_OUL_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OUL_PIN (GPIO_PIN_01)
#define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_20)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OVH)
#define PWM_TMR4_1_OVH_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OVH_PIN (GPIO_PIN_06)
#define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_20)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OVL)
#define PWM_TMR4_1_OVL_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OVL_PIN (GPIO_PIN_04)
#define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_20)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OWH)
#define PWM_TMR4_1_OWH_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OWH_PIN (GPIO_PIN_07)
#define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_20)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OWL)
#define PWM_TMR4_1_OWL_PORT (GPIO_PORT_B)
#define PWM_TMR4_1_OWL_PIN (GPIO_PIN_02)
#define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_20)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OXH)
#define PWM_TMR4_1_OXH_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OXH_PIN (GPIO_PIN_01)
#define PWM_TMR4_1_OXH_PIN_FUNC (GPIO_FUNC_23)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OXL)
#define PWM_TMR4_1_OXL_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OXL_PIN (GPIO_PIN_00)
#define PWM_TMR4_1_OXL_PIN_FUNC (GPIO_FUNC_23)
#endif
#endif
#if defined(BSP_USING_PWM_TMR4_1)
#if defined(BSP_USING_PWM_TMR4_1_OUH)
#define PWM_TMR4_1_OUH_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OUH_PIN (GPIO_PIN_02)
#define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_20)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OUL)
#define PWM_TMR4_1_OUL_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OUL_PIN (GPIO_PIN_01)
#define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_20)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OVH)
#define PWM_TMR4_1_OVH_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OVH_PIN (GPIO_PIN_06)
#define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_20)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OVL)
#define PWM_TMR4_1_OVL_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OVL_PIN (GPIO_PIN_04)
#define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_20)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OWH)
#define PWM_TMR4_1_OWH_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OWH_PIN (GPIO_PIN_07)
#define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_20)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OWL)
#define PWM_TMR4_1_OWL_PORT (GPIO_PORT_B)
#define PWM_TMR4_1_OWL_PIN (GPIO_PIN_02)
#define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_20)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OXH)
#define PWM_TMR4_1_OXH_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OXH_PIN (GPIO_PIN_01)
#define PWM_TMR4_1_OXH_PIN_FUNC (GPIO_FUNC_23)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OXL)
#define PWM_TMR4_1_OXL_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OXL_PIN (GPIO_PIN_00)
#define PWM_TMR4_1_OXL_PIN_FUNC (GPIO_FUNC_23)
#endif
#endif
/*********** PWM_TMR6 configure *********/
#if defined(BSP_USING_PWM_TMR6_1)
#if defined(BSP_USING_PWM_TMR6_1_A)
#define PWM_TMR6_1_A_PORT (GPIO_PORT_C)
#define PWM_TMR6_1_A_PIN (GPIO_PIN_00)
#define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_12)
#endif
#if defined(BSP_USING_PWM_TMR6_1_B)
#define PWM_TMR6_1_B_PORT (GPIO_PORT_A)
#define PWM_TMR6_1_B_PIN (GPIO_PIN_00)
#define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_12)
#endif
#endif
#if defined(BSP_USING_PWM_TMR6_1)
#if defined(BSP_USING_PWM_TMR6_1_A)
#define PWM_TMR6_1_A_PORT (GPIO_PORT_C)
#define PWM_TMR6_1_A_PIN (GPIO_PIN_00)
#define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_12)
#endif
#if defined(BSP_USING_PWM_TMR6_1_B)
#define PWM_TMR6_1_B_PORT (GPIO_PORT_A)
#define PWM_TMR6_1_B_PIN (GPIO_PIN_00)
#define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_12)
#endif
#endif
#endif
#if defined(BSP_USING_INPUT_CAPTURE)
#define INPUT_CAPTURE_TMR6_FUNC (GPIO_FUNC_14)
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1)
#define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_C)
#define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_06)
#endif
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2)
#define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_C)
#define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_07)
#endif
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3)
#define INPUT_CAPTURE_TMR6_3_PORT (GPIO_PORT_B)
#define INPUT_CAPTURE_TMR6_3_PIN (GPIO_PIN_02)
#endif
#define INPUT_CAPTURE_TMR6_FUNC (GPIO_FUNC_14)
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1)
#define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_C)
#define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_06)
#endif
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2)
#define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_C)
#define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_07)
#endif
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3)
#define INPUT_CAPTURE_TMR6_3_PORT (GPIO_PORT_B)
#define INPUT_CAPTURE_TMR6_3_PIN (GPIO_PIN_02)
#endif
#endif
/*********** TMRA_PULSE_ENCODER configure *********/
#if defined(RT_USING_PULSE_ENCODER)
#if defined(BSP_USING_TMRA_PULSE_ENCODER)
#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
#define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A)
#define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08)
#define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4)
#define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A)
#define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09)
#define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4)
#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
#endif /* BSP_USING_TMRA_PULSE_ENCODER */
#if defined(BSP_USING_TMRA_PULSE_ENCODER)
#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
#define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A)
#define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08)
#define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4)
#define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A)
#define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09)
#define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4)
#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
#endif /* BSP_USING_TMRA_PULSE_ENCODER */
#if defined(BSP_USING_TMR6_PULSE_ENCODER)
#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
#define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B)
#define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_05)
#define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3)
#define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B)
#define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_13)
#define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3)
#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
#endif /* BSP_USING_TMR6_PULSE_ENCODER */
#if defined(BSP_USING_TMR6_PULSE_ENCODER)
#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
#define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B)
#define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_05)
#define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3)
#define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B)
#define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_13)
#define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3)
#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
#endif /* BSP_USING_TMR6_PULSE_ENCODER */
#endif /* RT_USING_PULSE_ENCODER */
#endif

189
bsp/hc32/ev_hc32f334_lqfp64/board/config/adc_config.h
View File

@ -20,42 +20,41 @@ extern "C" {
#ifdef BSP_USING_ADC1
#ifndef ADC1_INIT_PARAMS
#define ADC1_INIT_PARAMS \
{ \
.name = "adc1", \
.vref = 3300, \
.resolution = ADC_RESOLUTION_12BIT, \
.data_align = ADC_DATAALIGN_RIGHT, \
.eoc_poll_time_max = 100, \
.hard_trig_enable = RT_FALSE, \
.hard_trig_src = ADC_HARDTRIG_EVT0, \
.internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
.internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_TMR0_1_CMP_A, \
.continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \
#define ADC1_INIT_PARAMS \
{ \
.name = "adc1", \
.vref = 3300, \
.resolution = ADC_RESOLUTION_12BIT, \
.data_align = ADC_DATAALIGN_RIGHT, \
.eoc_poll_time_max = 100, \
.hard_trig_enable = RT_FALSE, \
.hard_trig_src = ADC_HARDTRIG_EVT0, \
.internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
.internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_TMR0_1_CMP_A, \
.continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \
}
#endif /* ADC1_INIT_PARAMS */
#if defined (BSP_ADC1_USING_DMA)
#if defined(BSP_ADC1_USING_DMA)
#ifndef ADC1_EOCA_DMA_CONFIG
#define ADC1_EOCA_DMA_CONFIG \
{ \
.Instance = ADC1_EOCA_DMA_INSTANCE, \
.channel = ADC1_EOCA_DMA_CHANNEL, \
.clock = ADC1_EOCA_DMA_CLOCK, \
.trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_ADC1_EOCA, \
.flag = ADC1_EOCA_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = ADC1_EOCA_DMA_IRQn, \
.irq_prio = ADC1_EOCA_DMA_INT_PRIO, \
.int_src = ADC1_EOCA_DMA_INT_SRC, \
}, \
#define ADC1_EOCA_DMA_CONFIG \
{ \
.Instance = ADC1_EOCA_DMA_INSTANCE, \
.channel = ADC1_EOCA_DMA_CHANNEL, \
.clock = ADC1_EOCA_DMA_CLOCK, \
.trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_ADC1_EOCA, \
.flag = ADC1_EOCA_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = ADC1_EOCA_DMA_IRQn, \
.irq_prio = ADC1_EOCA_DMA_INT_PRIO, \
.int_src = ADC1_EOCA_DMA_INT_SRC, \
}, \
}
#endif /* ADC1_EOCA_DMA_CONFIG */
#endif /* BSP_ADC1_USING_DMA */
@ -63,42 +62,41 @@ extern "C" {
#ifdef BSP_USING_ADC2
#ifndef ADC2_INIT_PARAMS
#define ADC2_INIT_PARAMS \
{ \
.name = "adc2", \
.vref = 3300, \
.resolution = ADC_RESOLUTION_12BIT, \
.data_align = ADC_DATAALIGN_RIGHT, \
.eoc_poll_time_max = 100, \
.hard_trig_enable = RT_FALSE, \
.hard_trig_src = ADC_HARDTRIG_EVT0, \
.internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
.internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_TMR0_1_CMP_A, \
.continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \
#define ADC2_INIT_PARAMS \
{ \
.name = "adc2", \
.vref = 3300, \
.resolution = ADC_RESOLUTION_12BIT, \
.data_align = ADC_DATAALIGN_RIGHT, \
.eoc_poll_time_max = 100, \
.hard_trig_enable = RT_FALSE, \
.hard_trig_src = ADC_HARDTRIG_EVT0, \
.internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
.internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_TMR0_1_CMP_A, \
.continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \
}
#endif /* ADC2_INIT_PARAMS */
#if defined (BSP_ADC2_USING_DMA)
#if defined(BSP_ADC2_USING_DMA)
#ifndef ADC2_EOCA_DMA_CONFIG
#define ADC2_EOCA_DMA_CONFIG \
{ \
.Instance = ADC2_EOCA_DMA_INSTANCE, \
.channel = ADC2_EOCA_DMA_CHANNEL, \
.clock = ADC2_EOCA_DMA_CLOCK, \
.trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_ADC2_EOCA, \
.flag = ADC2_EOCA_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = ADC2_EOCA_DMA_IRQn, \
.irq_prio = ADC2_EOCA_DMA_INT_PRIO, \
.int_src = ADC2_EOCA_DMA_INT_SRC, \
}, \
#define ADC2_EOCA_DMA_CONFIG \
{ \
.Instance = ADC2_EOCA_DMA_INSTANCE, \
.channel = ADC2_EOCA_DMA_CHANNEL, \
.clock = ADC2_EOCA_DMA_CLOCK, \
.trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_ADC2_EOCA, \
.flag = ADC2_EOCA_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = ADC2_EOCA_DMA_IRQn, \
.irq_prio = ADC2_EOCA_DMA_INT_PRIO, \
.int_src = ADC2_EOCA_DMA_INT_SRC, \
}, \
}
#endif /* ADC2_EOCA_DMA_CONFIG */
#endif /* BSP_ADC2_USING_DMA */
@ -106,42 +104,41 @@ extern "C" {
#ifdef BSP_USING_ADC3
#ifndef ADC3_INIT_PARAMS
#define ADC3_INIT_PARAMS \
{ \
.name = "adc3", \
.vref = 3300, \
.resolution = ADC_RESOLUTION_12BIT, \
.data_align = ADC_DATAALIGN_RIGHT, \
.eoc_poll_time_max = 100, \
.hard_trig_enable = RT_FALSE, \
.hard_trig_src = ADC_HARDTRIG_EVT0, \
.internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
.internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_TMR0_1_CMP_A, \
.continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \
#define ADC3_INIT_PARAMS \
{ \
.name = "adc3", \
.vref = 3300, \
.resolution = ADC_RESOLUTION_12BIT, \
.data_align = ADC_DATAALIGN_RIGHT, \
.eoc_poll_time_max = 100, \
.hard_trig_enable = RT_FALSE, \
.hard_trig_src = ADC_HARDTRIG_EVT0, \
.internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
.internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_TMR0_1_CMP_A, \
.continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \
}
#endif /* ADC3_INIT_PARAMS */
#if defined (BSP_ADC3_USING_DMA)
#if defined(BSP_ADC3_USING_DMA)
#ifndef ADC3_EOCA_DMA_CONFIG
#define ADC3_EOCA_DMA_CONFIG \
{ \
.Instance = ADC3_EOCA_DMA_INSTANCE, \
.channel = ADC3_EOCA_DMA_CHANNEL, \
.clock = ADC3_EOCA_DMA_CLOCK, \
.trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_ADC3_EOCA, \
.flag = ADC3_EOCA_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = ADC3_EOCA_DMA_IRQn, \
.irq_prio = ADC3_EOCA_DMA_INT_PRIO, \
.int_src = ADC3_EOCA_DMA_INT_SRC, \
}, \
#define ADC3_EOCA_DMA_CONFIG \
{ \
.Instance = ADC3_EOCA_DMA_INSTANCE, \
.channel = ADC3_EOCA_DMA_CHANNEL, \
.clock = ADC3_EOCA_DMA_CLOCK, \
.trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_ADC3_EOCA, \
.flag = ADC3_EOCA_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = ADC3_EOCA_DMA_IRQn, \
.irq_prio = ADC3_EOCA_DMA_INT_PRIO, \
.int_src = ADC3_EOCA_DMA_INT_SRC, \
}, \
}
#endif /* ADC3_EOCA_DMA_CONFIG */
#endif /* BSP_ADC3_USING_DMA */

36
bsp/hc32/ev_hc32f334_lqfp64/board/config/dac_config.h
View File

@ -19,30 +19,30 @@ extern "C" {
#ifdef BSP_USING_DAC1
#ifndef DAC1_INIT_PARAMS
#define DAC1_INIT_PARAMS \
{ \
.name = "dac1", \
.vref = 3300, \
.dac_adp_enable = RT_FALSE, \
.dac_adp_sel = DAC_ADP_SEL_ALL, \
.ch1_output_enable = RT_TRUE, \
.ch2_output_enable = RT_TRUE, \
.ch1_amp_enable = RT_TRUE, \
.ch2_amp_enable = RT_TRUE, \
#define DAC1_INIT_PARAMS \
{ \
.name = "dac1", \
.vref = 3300, \
.dac_adp_enable = RT_FALSE, \
.dac_adp_sel = DAC_ADP_SEL_ALL, \
.ch1_output_enable = RT_TRUE, \
.ch2_output_enable = RT_TRUE, \
.ch1_amp_enable = RT_TRUE, \
.ch2_amp_enable = RT_TRUE, \
}
#endif /* DAC1_INIT_PARAMS */
#endif /* BSP_USING_DAC1 */
#ifdef BSP_USING_DAC2
#ifndef DAC2_INIT_PARAMS
#define DAC2_INIT_PARAMS \
{ \
.name = "dac2", \
.vref = 3300, \
.dac_adp_enable = RT_FALSE, \
.dac_adp_sel = DAC_ADP_SEL_ALL, \
.ch1_output_enable = RT_TRUE, \
.ch1_amp_enable = RT_TRUE, \
#define DAC2_INIT_PARAMS \
{ \
.name = "dac2", \
.vref = 3300, \
.dac_adp_enable = RT_FALSE, \
.dac_adp_sel = DAC_ADP_SEL_ALL, \
.ch1_output_enable = RT_TRUE, \
.ch1_amp_enable = RT_TRUE, \
}
#endif /* DAC2_INIT_PARAMS */
#endif /* BSP_USING_DAC2 */

240
bsp/hc32/ev_hc32f334_lqfp64/board/config/dma_config.h
View File

@ -20,168 +20,168 @@ extern "C" {
/* DMA1 ch0 */
#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
#define UART1_TX_DMA_INSTANCE CM_DMA
#define UART1_TX_DMA_CHANNEL DMA_CH0
#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define UART1_TX_DMA_TRIG_SELECT AOS_DMA_0
#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define UART1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
#define UART1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
#define UART1_TX_DMA_INT_SRC INT_SRC_DMA_TC0
#define UART1_TX_DMA_INSTANCE CM_DMA
#define UART1_TX_DMA_CHANNEL DMA_CH0
#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define UART1_TX_DMA_TRIG_SELECT AOS_DMA_0
#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define UART1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
#define UART1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
#define UART1_TX_DMA_INT_SRC INT_SRC_DMA_TC0
#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
#define SPI1_TX_DMA_INSTANCE CM_DMA
#define SPI1_TX_DMA_CHANNEL DMA_CH0
#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA_0
#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define SPI1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA_TC0
#define SPI1_TX_DMA_INSTANCE CM_DMA
#define SPI1_TX_DMA_CHANNEL DMA_CH0
#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA_0
#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define SPI1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA_TC0
#endif
/* DMA1 ch1 */
#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
#define UART1_RX_DMA_INSTANCE CM_DMA
#define UART1_RX_DMA_CHANNEL DMA_CH1
#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define UART1_RX_DMA_TRIG_SELECT AOS_DMA_1
#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define UART1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
#define UART1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
#define UART1_RX_DMA_INT_SRC INT_SRC_DMA_TC1
#define UART1_RX_DMA_INSTANCE CM_DMA
#define UART1_RX_DMA_CHANNEL DMA_CH1
#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define UART1_RX_DMA_TRIG_SELECT AOS_DMA_1
#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define UART1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
#define UART1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
#define UART1_RX_DMA_INT_SRC INT_SRC_DMA_TC1
#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
#define SPI1_RX_DMA_INSTANCE CM_DMA
#define SPI1_RX_DMA_CHANNEL DMA_CH1
#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA_1
#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define SPI1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA_TC1
#define SPI1_RX_DMA_INSTANCE CM_DMA
#define SPI1_RX_DMA_CHANNEL DMA_CH1
#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA_1
#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define SPI1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA_TC1
#endif
/* DMA1 ch2 */
#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
#define UART2_TX_DMA_INSTANCE CM_DMA
#define UART2_TX_DMA_CHANNEL DMA_CH2
#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define UART2_TX_DMA_TRIG_SELECT AOS_DMA_2
#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define UART2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
#define UART2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
#define UART2_TX_DMA_INT_SRC INT_SRC_DMA_TC2
#define UART2_TX_DMA_INSTANCE CM_DMA
#define UART2_TX_DMA_CHANNEL DMA_CH2
#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define UART2_TX_DMA_TRIG_SELECT AOS_DMA_2
#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define UART2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
#define UART2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
#define UART2_TX_DMA_INT_SRC INT_SRC_DMA_TC2
#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE)
#define I2C1_TX_DMA_INSTANCE CM_DMA
#define I2C1_TX_DMA_CHANNEL DMA_CH2
#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA_2
#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define I2C1_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA_TC2
#define I2C1_TX_DMA_INSTANCE CM_DMA
#define I2C1_TX_DMA_CHANNEL DMA_CH2
#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA_2
#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define I2C1_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA_TC2
#endif
/* DMA1 ch3 */
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
#define UART2_RX_DMA_INSTANCE CM_DMA
#define UART2_RX_DMA_CHANNEL DMA_CH3
#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define UART2_RX_DMA_TRIG_SELECT AOS_DMA_3
#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define UART2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
#define UART2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
#define UART2_RX_DMA_INT_SRC INT_SRC_DMA_TC3
#define UART2_RX_DMA_INSTANCE CM_DMA
#define UART2_RX_DMA_CHANNEL DMA_CH3
#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define UART2_RX_DMA_TRIG_SELECT AOS_DMA_3
#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define UART2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
#define UART2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
#define UART2_RX_DMA_INT_SRC INT_SRC_DMA_TC3
#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE)
#define I2C1_RX_DMA_INSTANCE CM_DMA
#define I2C1_RX_DMA_CHANNEL DMA_CH3
#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA_3
#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define I2C1_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA_TC3
#define I2C1_RX_DMA_INSTANCE CM_DMA
#define I2C1_RX_DMA_CHANNEL DMA_CH3
#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA_3
#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define I2C1_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA_TC3
#endif
/* DMA1 ch4 */
#if defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
#define UART3_TX_DMA_INSTANCE CM_DMA
#define UART3_TX_DMA_CHANNEL DMA_CH4
#define UART3_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define UART3_TX_DMA_TRIG_SELECT AOS_DMA_4
#define UART3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
#define UART3_TX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
#define UART3_TX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
#define UART3_TX_DMA_INT_SRC INT_SRC_DMA_TC4
#define UART3_TX_DMA_INSTANCE CM_DMA
#define UART3_TX_DMA_CHANNEL DMA_CH4
#define UART3_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define UART3_TX_DMA_TRIG_SELECT AOS_DMA_4
#define UART3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
#define UART3_TX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
#define UART3_TX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
#define UART3_TX_DMA_INT_SRC INT_SRC_DMA_TC4
#elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE)
#define ADC1_EOCA_DMA_INSTANCE CM_DMA
#define ADC1_EOCA_DMA_CHANNEL DMA_CH4
#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA_4
#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA_TC4
#define ADC1_EOCA_DMA_INSTANCE CM_DMA
#define ADC1_EOCA_DMA_CHANNEL DMA_CH4
#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA_4
#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA_TC4
#endif
/* DMA1 ch5 */
#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
#define UART3_RX_DMA_INSTANCE CM_DMA
#define UART3_RX_DMA_CHANNEL DMA_CH5
#define UART3_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define UART3_RX_DMA_TRIG_SELECT AOS_DMA_5
#define UART3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
#define UART3_RX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
#define UART3_RX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
#define UART3_RX_DMA_INT_SRC INT_SRC_DMA_TC5
#define UART3_RX_DMA_INSTANCE CM_DMA
#define UART3_RX_DMA_CHANNEL DMA_CH5
#define UART3_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define UART3_RX_DMA_TRIG_SELECT AOS_DMA_5
#define UART3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
#define UART3_RX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
#define UART3_RX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
#define UART3_RX_DMA_INT_SRC INT_SRC_DMA_TC5
#elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE)
#define ADC2_EOCA_DMA_INSTANCE CM_DMA
#define ADC2_EOCA_DMA_CHANNEL DMA_CH5
#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA_5
#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA_TC5
#define ADC2_EOCA_DMA_INSTANCE CM_DMA
#define ADC2_EOCA_DMA_CHANNEL DMA_CH5
#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA_5
#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA_TC5
#endif
/* DMA1 ch6 */
#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
#define UART4_TX_DMA_INSTANCE CM_DMA
#define UART4_TX_DMA_CHANNEL DMA_CH6
#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define UART4_TX_DMA_TRIG_SELECT AOS_DMA_6
#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6
#define UART4_TX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM
#define UART4_TX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO
#define UART4_TX_DMA_INT_SRC INT_SRC_DMA_TC6
#define UART4_TX_DMA_INSTANCE CM_DMA
#define UART4_TX_DMA_CHANNEL DMA_CH6
#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define UART4_TX_DMA_TRIG_SELECT AOS_DMA_6
#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6
#define UART4_TX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM
#define UART4_TX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO
#define UART4_TX_DMA_INT_SRC INT_SRC_DMA_TC6
#elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE)
#define ADC3_EOCA_DMA_INSTANCE CM_DMA
#define ADC3_EOCA_DMA_CHANNEL DMA_CH6
#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA_6
#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH6
#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM
#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO
#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA_TC6
#define ADC3_EOCA_DMA_INSTANCE CM_DMA
#define ADC3_EOCA_DMA_CHANNEL DMA_CH6
#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA_6
#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH6
#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM
#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO
#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA_TC6
#endif
/* DMA1 ch7 */
#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
#define UART4_RX_DMA_INSTANCE CM_DMA
#define UART4_RX_DMA_CHANNEL DMA_CH7
#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define UART4_RX_DMA_TRIG_SELECT AOS_DMA_7
#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7
#define UART4_RX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM
#define UART4_RX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO
#define UART4_RX_DMA_INT_SRC INT_SRC_DMA_TC7
#define UART4_RX_DMA_INSTANCE CM_DMA
#define UART4_RX_DMA_CHANNEL DMA_CH7
#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define UART4_RX_DMA_TRIG_SELECT AOS_DMA_7
#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7
#define UART4_RX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM
#define UART4_RX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO
#define UART4_RX_DMA_INT_SRC INT_SRC_DMA_TC7
#endif
#ifdef __cplusplus

160
bsp/hc32/ev_hc32f334_lqfp64/board/config/gpio_config.h
View File

@ -22,146 +22,146 @@ extern "C" {
#if defined(RT_USING_PIN)
#ifndef EXTINT0_IRQ_CONFIG
#define EXTINT0_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT0_IRQ_NUM, \
.irq_prio = BSP_EXTINT0_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ0, \
#define EXTINT0_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT0_IRQ_NUM, \
.irq_prio = BSP_EXTINT0_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ0, \
}
#endif /* EXTINT1_IRQ_CONFIG */
#ifndef EXTINT1_IRQ_CONFIG
#define EXTINT1_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT1_IRQ_NUM, \
.irq_prio = BSP_EXTINT1_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ1, \
#define EXTINT1_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT1_IRQ_NUM, \
.irq_prio = BSP_EXTINT1_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ1, \
}
#endif /* EXTINT1_IRQ_CONFIG */
#ifndef EXTINT2_IRQ_CONFIG
#define EXTINT2_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT2_IRQ_NUM, \
.irq_prio = BSP_EXTINT2_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ2, \
#define EXTINT2_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT2_IRQ_NUM, \
.irq_prio = BSP_EXTINT2_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ2, \
}
#endif /* EXTINT2_IRQ_CONFIG */
#ifndef EXTINT3_IRQ_CONFIG
#define EXTINT3_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT3_IRQ_NUM, \
.irq_prio = BSP_EXTINT3_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ3, \
#define EXTINT3_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT3_IRQ_NUM, \
.irq_prio = BSP_EXTINT3_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ3, \
}
#endif /* EXTINT3_IRQ_CONFIG */
#ifndef EXTINT4_IRQ_CONFIG
#define EXTINT4_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT4_IRQ_NUM, \
.irq_prio = BSP_EXTINT4_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ4, \
#define EXTINT4_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT4_IRQ_NUM, \
.irq_prio = BSP_EXTINT4_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ4, \
}
#endif /* EXTINT4_IRQ_CONFIG */
#ifndef EXTINT5_IRQ_CONFIG
#define EXTINT5_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT5_IRQ_NUM, \
.irq_prio = BSP_EXTINT5_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ5, \
#define EXTINT5_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT5_IRQ_NUM, \
.irq_prio = BSP_EXTINT5_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ5, \
}
#endif /* EXTINT5_IRQ_CONFIG */
#ifndef EXTINT6_IRQ_CONFIG
#define EXTINT6_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT6_IRQ_NUM, \
.irq_prio = BSP_EXTINT6_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ6, \
#define EXTINT6_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT6_IRQ_NUM, \
.irq_prio = BSP_EXTINT6_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ6, \
}
#endif /* EXTINT6_IRQ_CONFIG */
#ifndef EXTINT7_IRQ_CONFIG
#define EXTINT7_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT7_IRQ_NUM, \
.irq_prio = BSP_EXTINT7_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ7, \
#define EXTINT7_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT7_IRQ_NUM, \
.irq_prio = BSP_EXTINT7_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ7, \
}
#endif /* EXTINT7_IRQ_CONFIG */
#ifndef EXTINT8_IRQ_CONFIG
#define EXTINT8_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT8_IRQ_NUM, \
.irq_prio = BSP_EXTINT8_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ8, \
#define EXTINT8_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT8_IRQ_NUM, \
.irq_prio = BSP_EXTINT8_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ8, \
}
#endif /* EXTINT8_IRQ_CONFIG */
#ifndef EXTINT9_IRQ_CONFIG
#define EXTINT9_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT9_IRQ_NUM, \
.irq_prio = BSP_EXTINT9_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ9, \
#define EXTINT9_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT9_IRQ_NUM, \
.irq_prio = BSP_EXTINT9_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ9, \
}
#endif /* EXTINT9_IRQ_CONFIG */
#ifndef EXTINT10_IRQ_CONFIG
#define EXTINT10_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT10_IRQ_NUM, \
.irq_prio = BSP_EXTINT10_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ10, \
#define EXTINT10_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT10_IRQ_NUM, \
.irq_prio = BSP_EXTINT10_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ10, \
}
#endif /* EXTINT10_IRQ_CONFIG */
#ifndef EXTINT11_IRQ_CONFIG
#define EXTINT11_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT11_IRQ_NUM, \
.irq_prio = BSP_EXTINT11_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ11, \
#define EXTINT11_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT11_IRQ_NUM, \
.irq_prio = BSP_EXTINT11_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ11, \
}
#endif /* EXTINT11_IRQ_CONFIG */
#ifndef EXTINT12_IRQ_CONFIG
#define EXTINT12_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT12_IRQ_NUM, \
.irq_prio = BSP_EXTINT12_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ12, \
#define EXTINT12_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT12_IRQ_NUM, \
.irq_prio = BSP_EXTINT12_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ12, \
}
#endif /* EXTINT12_IRQ_CONFIG */
#ifndef EXTINT13_IRQ_CONFIG
#define EXTINT13_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT13_IRQ_NUM, \
.irq_prio = BSP_EXTINT13_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ13, \
#define EXTINT13_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT13_IRQ_NUM, \
.irq_prio = BSP_EXTINT13_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ13, \
}
#endif /* EXTINT13_IRQ_CONFIG */
#ifndef EXTINT14_IRQ_CONFIG
#define EXTINT14_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT14_IRQ_NUM, \
.irq_prio = BSP_EXTINT14_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ14, \
#define EXTINT14_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT14_IRQ_NUM, \
.irq_prio = BSP_EXTINT14_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ14, \
}
#endif /* EXTINT14_IRQ_CONFIG */
#ifndef EXTINT15_IRQ_CONFIG
#define EXTINT15_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT15_IRQ_NUM, \
.irq_prio = BSP_EXTINT15_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ15, \
#define EXTINT15_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT15_IRQ_NUM, \
.irq_prio = BSP_EXTINT15_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ15, \
}
#endif /* EXTINT15_IRQ_CONFIG */

68
bsp/hc32/ev_hc32f334_lqfp64/board/config/i2c_config.h
View File

@ -20,51 +20,49 @@ extern "C" {
#if defined(BSP_USING_I2C1)
#ifndef I2C1_CONFIG
#define I2C1_CONFIG \
{ \
.name = "i2c1", \
.Instance = CM_I2C, \
.clock = FCG1_PERIPH_I2C, \
.baudrate = 100000UL, \
.timeout = 10000UL, \
#define I2C1_CONFIG \
{ \
.name = "i2c1", \
.Instance = CM_I2C, \
.clock = FCG1_PERIPH_I2C, \
.baudrate = 100000UL, \
.timeout = 10000UL, \
}
#endif /* I2C1_CONFIG */
#endif
#if defined(BSP_I2C1_USING_DMA)
#ifndef I2C1_TX_DMA_CONFIG
#define I2C1_TX_DMA_CONFIG \
{ \
.Instance = I2C1_TX_DMA_INSTANCE, \
.channel = I2C1_TX_DMA_CHANNEL, \
.clock = I2C1_TX_DMA_CLOCK, \
.trigger_select = I2C1_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C_TEI, \
.flag = I2C1_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = I2C1_TX_DMA_IRQn, \
.irq_prio = I2C1_TX_DMA_INT_PRIO, \
.int_src = I2C1_TX_DMA_INT_SRC, \
}, \
#define I2C1_TX_DMA_CONFIG \
{ \
.Instance = I2C1_TX_DMA_INSTANCE, \
.channel = I2C1_TX_DMA_CHANNEL, \
.clock = I2C1_TX_DMA_CLOCK, \
.trigger_select = I2C1_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C_TEI, \
.flag = I2C1_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = I2C1_TX_DMA_IRQn, \
.irq_prio = I2C1_TX_DMA_INT_PRIO, \
.int_src = I2C1_TX_DMA_INT_SRC, \
}, \
}
#endif /* I2C1_TX_DMA_CONFIG */
#ifndef I2C1_RX_DMA_CONFIG
#define I2C1_RX_DMA_CONFIG \
{ \
.Instance = I2C1_RX_DMA_INSTANCE, \
.channel = I2C1_RX_DMA_CHANNEL, \
.clock = I2C1_RX_DMA_CLOCK, \
.trigger_select = I2C1_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C_RXI, \
.flag = I2C1_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = I2C1_RX_DMA_IRQn, \
.irq_prio = I2C1_RX_DMA_INT_PRIO, \
.int_src = I2C1_RX_DMA_INT_SRC, \
}, \
#define I2C1_RX_DMA_CONFIG \
{ \
.Instance = I2C1_RX_DMA_INSTANCE, \
.channel = I2C1_RX_DMA_CHANNEL, \
.clock = I2C1_RX_DMA_CLOCK, \
.trigger_select = I2C1_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C_RXI, \
.flag = I2C1_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = I2C1_RX_DMA_IRQn, \
.irq_prio = I2C1_RX_DMA_INT_PRIO, \
.int_src = I2C1_RX_DMA_INT_SRC, \
}, \
}
#endif /* I2C1_RX_DMA_CONFIG */
#endif /* BSP_I2C1_USING_DMA */

258
bsp/hc32/ev_hc32f334_lqfp64/board/config/irq_config.h
View File

@ -17,222 +17,222 @@
extern "C" {
#endif
#define BSP_EXTINT0_IRQ_NUM EXTINT_PORT_EIRQ0_IRQn
#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT1_IRQ_NUM EXTINT_PORT_EIRQ1_IRQn
#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT2_IRQ_NUM EXTINT_PORT_EIRQ2_IRQn
#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT3_IRQ_NUM EXTINT_PORT_EIRQ3_IRQn
#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT4_IRQ_NUM EXTINT_PORT_EIRQ4_IRQn
#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT5_IRQ_NUM EXTINT_PORT_EIRQ5_IRQn
#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT6_IRQ_NUM EXTINT_PORT_EIRQ6_IRQn
#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT7_IRQ_NUM EXTINT_PORT_EIRQ7_IRQn
#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT8_IRQ_NUM EXTINT_PORT_EIRQ8_IRQn
#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT9_IRQ_NUM EXTINT_PORT_EIRQ9_IRQn
#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT10_IRQ_NUM EXTINT_PORT_EIRQ10_IRQn
#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT11_IRQ_NUM EXTINT_PORT_EIRQ11_IRQn
#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT12_IRQ_NUM EXTINT_PORT_EIRQ12_IRQn
#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT13_IRQ_NUM EXTINT_PORT_EIRQ13_IRQn
#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT14_IRQ_NUM EXTINT_PORT_EIRQ14_IRQn
#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT15_IRQ_NUM EXTINT_PORT_EIRQ15_IRQn
#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT0_IRQ_NUM EXTINT_PORT_EIRQ0_IRQn
#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT1_IRQ_NUM EXTINT_PORT_EIRQ1_IRQn
#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT2_IRQ_NUM EXTINT_PORT_EIRQ2_IRQn
#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT3_IRQ_NUM EXTINT_PORT_EIRQ3_IRQn
#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT4_IRQ_NUM EXTINT_PORT_EIRQ4_IRQn
#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT5_IRQ_NUM EXTINT_PORT_EIRQ5_IRQn
#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT6_IRQ_NUM EXTINT_PORT_EIRQ6_IRQn
#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT7_IRQ_NUM EXTINT_PORT_EIRQ7_IRQn
#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT8_IRQ_NUM EXTINT_PORT_EIRQ8_IRQn
#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT9_IRQ_NUM EXTINT_PORT_EIRQ9_IRQn
#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT10_IRQ_NUM EXTINT_PORT_EIRQ10_IRQn
#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT11_IRQ_NUM EXTINT_PORT_EIRQ11_IRQn
#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT12_IRQ_NUM EXTINT_PORT_EIRQ12_IRQn
#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT13_IRQ_NUM EXTINT_PORT_EIRQ13_IRQn
#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT14_IRQ_NUM EXTINT_PORT_EIRQ14_IRQn
#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT15_IRQ_NUM EXTINT_PORT_EIRQ15_IRQn
#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch0 */
#define BSP_DMA1_CH0_IRQ_NUM INT000_IRQn
#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA1_CH0_IRQ_NUM INT000_IRQn
#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch1 */
#define BSP_DMA1_CH1_IRQ_NUM INT001_IRQn
#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA1_CH1_IRQ_NUM INT001_IRQn
#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch2 */
#define BSP_DMA1_CH2_IRQ_NUM INT002_IRQn
#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA1_CH2_IRQ_NUM INT002_IRQn
#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch3 */
#define BSP_DMA1_CH3_IRQ_NUM INT003_IRQn
#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA1_CH3_IRQ_NUM INT003_IRQn
#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch4 */
#define BSP_DMA1_CH4_IRQ_NUM INT004_IRQn
#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA1_CH4_IRQ_NUM INT004_IRQn
#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch5 */
#define BSP_DMA1_CH5_IRQ_NUM INT005_IRQn
#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA1_CH5_IRQ_NUM INT005_IRQn
#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch6 */
#define BSP_DMA1_CH6_IRQ_NUM INT006_IRQn
#define BSP_DMA1_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA1_CH6_IRQ_NUM INT006_IRQn
#define BSP_DMA1_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch7 */
#define BSP_DMA1_CH7_IRQ_NUM INT007_IRQn
#define BSP_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA1_CH7_IRQ_NUM INT007_IRQn
#define BSP_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if defined(BSP_USING_UART1)
#define BSP_UART1_IRQ_NUM USART1_IRQn
#define BSP_UART1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART1_IRQ_NUM USART1_IRQn
#define BSP_UART1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)) || \
defined(RT_USING_SERIAL_V2)
#define BSP_UART1_TX_CPLT_IRQ_NUM USART1_TCI_IRQn
#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART1_TX_CPLT_IRQ_NUM USART1_TCI_IRQn
#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#endif /* BSP_USING_UART1 */
#if defined(BSP_USING_UART2)
#define BSP_UART2_IRQ_NUM USART2_IRQn
#define BSP_UART2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART2_IRQ_NUM USART2_IRQn
#define BSP_UART2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)) || \
defined(RT_USING_SERIAL_V2)
#define BSP_UART2_TX_CPLT_IRQ_NUM USART2_TCI_IRQn
#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART2_TX_CPLT_IRQ_NUM USART2_TCI_IRQn
#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#endif /* BSP_USING_UART2 */
#if defined(BSP_USING_UART3)
#define BSP_UART3_IRQ_NUM USART3_IRQn
#define BSP_UART3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART3_IRQ_NUM USART3_IRQn
#define BSP_UART3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART3_TX_USING_DMA)) || \
defined(RT_USING_SERIAL_V2)
#define BSP_UART3_TX_CPLT_IRQ_NUM USART3_TCI_IRQn
#define BSP_UART3_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART3_TX_CPLT_IRQ_NUM USART3_TCI_IRQn
#define BSP_UART3_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#endif /* BSP_USING_UART3 */
#if defined(BSP_USING_UART4)
#define BSP_UART4_IRQ_NUM USART4_IRQn
#define BSP_UART4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART4_IRQ_NUM USART4_IRQn
#define BSP_UART4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)) || \
defined(RT_USING_SERIAL_V2)
#define BSP_UART4_TX_CPLT_IRQ_NUM USART4_TCI_IRQn
#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART4_TX_CPLT_IRQ_NUM USART4_TCI_IRQn
#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#endif /* BSP_USING_UART4 */
#if defined(BSP_USING_SPI1)
#define BSP_SPI1_ERR_IRQ_NUM SPI_IRQn
#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_SPI1_ERR_IRQ_NUM SPI_IRQn
#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#if defined (BSP_USING_QSPI)
#define BSP_QSPI_ERR_IRQ_NUM QSPI_IRQn
#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if defined(BSP_USING_QSPI)
#define BSP_QSPI_ERR_IRQ_NUM QSPI_IRQn
#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif /* BSP_USING_QSPI */
#if defined(BSP_USING_TMRA_1)
#define BSP_USING_TMRA_1_IRQ_NUM TMRA_1_OVF_UDF_IRQn
#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_USING_TMRA_1_IRQ_NUM TMRA_1_OVF_UDF_IRQn
#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_1 */
#if defined(BSP_USING_TMRA_2)
#define BSP_USING_TMRA_2_IRQ_NUM TMRA_2_OVF_UDF_IRQn
#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_USING_TMRA_2_IRQ_NUM TMRA_2_OVF_UDF_IRQn
#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_2 */
#if defined(BSP_USING_TMRA_3)
#define BSP_USING_TMRA_3_IRQ_NUM TMRA_3_OVF_UDF_IRQn
#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_USING_TMRA_3_IRQ_NUM TMRA_3_OVF_UDF_IRQn
#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_3 */
#if defined(BSP_USING_TMRA_4)
#define BSP_USING_TMRA_4_IRQ_NUM TMRA_4_OVF_UDF_IRQn
#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_USING_TMRA_4_IRQ_NUM TMRA_4_OVF_UDF_IRQn
#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_4 */
#if defined(BSP_USING_TMRA_5)
#define BSP_USING_TMRA_5_IRQ_NUM TMRA_5_OVF_UDF_IRQn
#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_USING_TMRA_5_IRQ_NUM TMRA_5_OVF_UDF_IRQn
#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_5 */
#if defined(BSP_USING_MCAN1)
#define BSP_MCAN1_INT0_IRQ_NUM MCAN1_INT0_IRQn
#define BSP_MCAN1_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_MCAN1_INT0_IRQ_NUM MCAN1_INT0_IRQn
#define BSP_MCAN1_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_MCAN1 */
#if defined(BSP_USING_MCAN2)
#define BSP_MCAN2_INT0_IRQ_NUM MCAN2_INT0_IRQn
#define BSP_MCAN2_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_MCAN2_INT0_IRQ_NUM MCAN2_INT0_IRQn
#define BSP_MCAN2_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_MCAN2 */
#if defined(RT_USING_ALARM)
#define BSP_RTC_ALARM_IRQ_NUM RTC_IRQn
#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_RTC_ALARM_IRQ_NUM RTC_IRQn
#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* RT_USING_ALARM */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM TMRA_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM TMRA_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM TMRA_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM TMRA_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_2)
#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM TMRA_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM TMRA_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM TMRA_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM TMRA_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_3)
#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM TMRA_3_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM TMRA_3_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM TMRA_3_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM TMRA_3_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_4)
#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM TMRA_4_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM TMRA_4_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM TMRA_4_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM TMRA_4_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_5)
#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM TMRA_5_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM TMRA_5_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM TMRA_5_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM TMRA_5_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */
#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM TMR6_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM TMR6_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM TMR6_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM TMR6_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */
#if defined(BSP_USING_PULSE_ENCODER_TMR6_2)
#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM TMR6_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM TMR6_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM TMR6_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM TMR6_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */
#if defined(BSP_USING_INPUT_CAPTURE)
#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT008_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT009_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT008_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT009_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT010_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT011_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT010_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT011_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM (INT012_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM (INT013_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM (INT012_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM (INT013_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_NUM (INT014_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_NUM (INT015_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_NUM (INT014_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_NUM (INT015_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#endif/* BSP_USING_INPUT_CAPTURE */
#ifdef __cplusplus

464
bsp/hc32/ev_hc32f334_lqfp64/board/config/mcan_config.h
View File

@ -30,56 +30,56 @@ extern "C" {
*/
#ifdef RT_CAN_USING_CANFD
#define MCAN_FD_SEL MCAN_FD_ISO_FD_BRS
#define MCAN_TOTAL_FILTER_NUM (26U)
#define MCAN_STD_FILTER_NUM (13U) /* Each standard filter element size is 4 bytes */
#define MCAN_EXT_FILTER_NUM (13U) /* Each extended filter element size is 8 bytes */
#define MCAN_TX_FIFO_NUM (6U)
#define MCAN_RX_FIFO_NUM (6U)
#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_64BYTE) /* Each FIFO element size is 64+8 bytes */
#define MCAN_FD_SEL MCAN_FD_ISO_FD_BRS
#define MCAN_TOTAL_FILTER_NUM (26U)
#define MCAN_STD_FILTER_NUM (13U) /* Each standard filter element size is 4 bytes */
#define MCAN_EXT_FILTER_NUM (13U) /* Each extended filter element size is 8 bytes */
#define MCAN_TX_FIFO_NUM (6U)
#define MCAN_RX_FIFO_NUM (6U)
#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_64BYTE) /* Each FIFO element size is 64+8 bytes */
#else
#define MCAN_FD_SEL MCAN_FD_CLASSICAL
#define MCAN_TOTAL_FILTER_NUM (32U)
#define MCAN_STD_FILTER_NUM (16U) /* Each standard filter element size is 4 bytes */
#define MCAN_EXT_FILTER_NUM (16U) /* Each extended filter element size is 8 bytes */
#define MCAN_TX_FIFO_NUM (26U)
#define MCAN_RX_FIFO_NUM (26U)
#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_8BYTE) /* Each FIFO element size is 8+8 bytes */
#define MCAN_FD_SEL MCAN_FD_CLASSICAL
#define MCAN_TOTAL_FILTER_NUM (32U)
#define MCAN_STD_FILTER_NUM (16U) /* Each standard filter element size is 4 bytes */
#define MCAN_EXT_FILTER_NUM (16U) /* Each extended filter element size is 8 bytes */
#define MCAN_TX_FIFO_NUM (26U)
#define MCAN_RX_FIFO_NUM (26U)
#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_8BYTE) /* Each FIFO element size is 8+8 bytes */
#endif
#ifdef BSP_USING_MCAN1
#define MCAN1_NAME ("mcan1")
#define MCAN1_WORK_MODE (RT_CAN_MODE_NORMAL)
#define MCAN1_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */
#define MCAN1_NAME ("mcan1")
#define MCAN1_WORK_MODE (RT_CAN_MODE_NORMAL)
#define MCAN1_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */
#define MCAN1_FD_SEL MCAN_FD_SEL
#define MCAN1_FD_SEL MCAN_FD_SEL
#define MCAN1_STD_FILTER_NUM MCAN_STD_FILTER_NUM
#define MCAN1_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM
#define MCAN1_STD_FILTER_NUM MCAN_STD_FILTER_NUM
#define MCAN1_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM
#define MCAN1_RX_FIFO0_NUM MCAN_RX_FIFO_NUM
#define MCAN1_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
#define MCAN1_RX_FIFO0_NUM MCAN_RX_FIFO_NUM
#define MCAN1_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
#define MCAN1_TX_FIFO_NUM MCAN_TX_FIFO_NUM
#define MCAN1_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
#define MCAN1_TX_NOTIFICATION_BUF ((1UL << MCAN1_TX_FIFO_NUM) - 1U)
#define MCAN1_TX_FIFO_NUM MCAN_TX_FIFO_NUM
#define MCAN1_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
#define MCAN1_TX_NOTIFICATION_BUF ((1UL << MCAN1_TX_FIFO_NUM) - 1U)
#endif /* BSP_USING_MCAN1 */
#ifdef BSP_USING_MCAN2
#define MCAN2_NAME ("mcan2")
#define MCAN2_WORK_MODE (RT_CAN_MODE_NORMAL)
#define MCAN2_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */
#define MCAN2_NAME ("mcan2")
#define MCAN2_WORK_MODE (RT_CAN_MODE_NORMAL)
#define MCAN2_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */
#define MCAN2_FD_SEL MCAN_FD_SEL
#define MCAN2_STD_FILTER_NUM MCAN_STD_FILTER_NUM
#define MCAN2_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM
#define MCAN2_FD_SEL MCAN_FD_SEL
#define MCAN2_STD_FILTER_NUM MCAN_STD_FILTER_NUM
#define MCAN2_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM
#define MCAN2_RX_FIFO0_NUM MCAN_RX_FIFO_NUM
#define MCAN2_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
#define MCAN2_RX_FIFO0_NUM MCAN_RX_FIFO_NUM
#define MCAN2_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
#define MCAN2_TX_FIFO_NUM MCAN_TX_FIFO_NUM
#define MCAN2_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
#define MCAN2_TX_NOTIFICATION_BUF ((1UL << MCAN2_TX_FIFO_NUM) - 1U)
#define MCAN2_TX_FIFO_NUM MCAN_TX_FIFO_NUM
#define MCAN2_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
#define MCAN2_TX_NOTIFICATION_BUF ((1UL << MCAN2_TX_FIFO_NUM) - 1U)
#endif /* BSP_USING_MCAN2 */
/***********************************************************************************************/
@ -100,154 +100,154 @@ extern "C" {
2. For the corresponding function of u32TdcFilter, please refer to the reference manual for details(TDCR.TDCF).
The u32TdcFilter can be get from PSR.TDCV.
*/
#define MCAN_FD_CFG_500K_1M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 64, \
.u32NominalTimeSeg2 = 16, \
.u32NominalSyncJumpWidth = 16, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 32, \
.u32DataTimeSeg2 = 8, \
.u32DataSyncJumpWidth = 8, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 32, \
.u32TdcFilter = 32 + 1, \
#define MCAN_FD_CFG_500K_1M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 64, \
.u32NominalTimeSeg2 = 16, \
.u32NominalSyncJumpWidth = 16, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 32, \
.u32DataTimeSeg2 = 8, \
.u32DataSyncJumpWidth = 8, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 32, \
.u32TdcFilter = 32 + 1, \
}
#define MCAN_FD_CFG_500K_2M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 64, \
.u32NominalTimeSeg2 = 16, \
.u32NominalSyncJumpWidth = 16, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 16, \
.u32DataTimeSeg2 = 4, \
.u32DataSyncJumpWidth = 4, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 16, \
.u32TdcFilter = 16 + 1, \
#define MCAN_FD_CFG_500K_2M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 64, \
.u32NominalTimeSeg2 = 16, \
.u32NominalSyncJumpWidth = 16, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 16, \
.u32DataTimeSeg2 = 4, \
.u32DataSyncJumpWidth = 4, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 16, \
.u32TdcFilter = 16 + 1, \
}
#define MCAN_FD_CFG_500K_4M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 64, \
.u32NominalTimeSeg2 = 16, \
.u32NominalSyncJumpWidth = 16, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 8, \
.u32DataTimeSeg2 = 2, \
.u32DataSyncJumpWidth = 2, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 8, \
.u32TdcFilter = 8 + 1, \
#define MCAN_FD_CFG_500K_4M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 64, \
.u32NominalTimeSeg2 = 16, \
.u32NominalSyncJumpWidth = 16, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 8, \
.u32DataTimeSeg2 = 2, \
.u32DataSyncJumpWidth = 2, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 8, \
.u32TdcFilter = 8 + 1, \
}
#define MCAN_FD_CFG_500K_5M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 64, \
.u32NominalTimeSeg2 = 16, \
.u32NominalSyncJumpWidth = 16, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 6, \
.u32DataTimeSeg2 = 2, \
.u32DataSyncJumpWidth = 2, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 6, \
.u32TdcFilter = 6 + 1, \
#define MCAN_FD_CFG_500K_5M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 64, \
.u32NominalTimeSeg2 = 16, \
.u32NominalSyncJumpWidth = 16, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 6, \
.u32DataTimeSeg2 = 2, \
.u32DataSyncJumpWidth = 2, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 6, \
.u32TdcFilter = 6 + 1, \
}
#define MCAN_FD_CFG_500K_8M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 64, \
.u32NominalTimeSeg2 = 16, \
.u32NominalSyncJumpWidth = 16, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 4, \
.u32DataTimeSeg2 = 1, \
.u32DataSyncJumpWidth = 1, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 4, \
.u32TdcFilter = 4 + 1, \
#define MCAN_FD_CFG_500K_8M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 64, \
.u32NominalTimeSeg2 = 16, \
.u32NominalSyncJumpWidth = 16, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 4, \
.u32DataTimeSeg2 = 1, \
.u32DataSyncJumpWidth = 1, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 4, \
.u32TdcFilter = 4 + 1, \
}
#define MCAN_FD_CFG_1M_1M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 32, \
.u32DataTimeSeg2 = 8, \
.u32DataSyncJumpWidth = 8, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 2*32, \
.u32TdcFilter = 2*32 + 1, \
#define MCAN_FD_CFG_1M_1M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 32, \
.u32DataTimeSeg2 = 8, \
.u32DataSyncJumpWidth = 8, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 2 * 32, \
.u32TdcFilter = 2 * 32 + 1, \
}
#define MCAN_FD_CFG_1M_2M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 16, \
.u32DataTimeSeg2 = 4, \
.u32DataSyncJumpWidth = 4, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 16, \
.u32TdcFilter = 16 + 1, \
#define MCAN_FD_CFG_1M_2M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 16, \
.u32DataTimeSeg2 = 4, \
.u32DataSyncJumpWidth = 4, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 16, \
.u32TdcFilter = 16 + 1, \
}
#define MCAN_FD_CFG_1M_4M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 8, \
.u32DataTimeSeg2 = 2, \
.u32DataSyncJumpWidth = 2, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 8, \
.u32TdcFilter = 8 + 1, \
#define MCAN_FD_CFG_1M_4M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 8, \
.u32DataTimeSeg2 = 2, \
.u32DataSyncJumpWidth = 2, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 8, \
.u32TdcFilter = 8 + 1, \
}
#define MCAN_FD_CFG_1M_5M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 6, \
.u32DataTimeSeg2 = 2, \
.u32DataSyncJumpWidth = 2, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 6, \
.u32TdcFilter = 6 + 1, \
#define MCAN_FD_CFG_1M_5M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 6, \
.u32DataTimeSeg2 = 2, \
.u32DataSyncJumpWidth = 2, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 6, \
.u32TdcFilter = 6 + 1, \
}
#define MCAN_FD_CFG_1M_8M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 4, \
.u32DataTimeSeg2 = 1, \
.u32DataSyncJumpWidth = 1, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 4, \
.u32TdcFilter = 4 + 1, \
#define MCAN_FD_CFG_1M_8M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 4, \
.u32DataTimeSeg2 = 1, \
.u32DataSyncJumpWidth = 1, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 4, \
.u32TdcFilter = 4 + 1, \
}
/*
@ -259,95 +259,95 @@ extern "C" {
SamplePoint(%) = 16 / (16 + 4) = 80%
The following bit rate configurations are based on the max MCAN Clock(40MHz).
*/
#define MCAN_CC_CFG_1M \
{ \
.u32NominalPrescaler = 2, \
.u32NominalTimeSeg1 = 16, \
.u32NominalTimeSeg2 = 4, \
.u32NominalSyncJumpWidth = 4, \
#define MCAN_CC_CFG_1M \
{ \
.u32NominalPrescaler = 2, \
.u32NominalTimeSeg1 = 16, \
.u32NominalTimeSeg2 = 4, \
.u32NominalSyncJumpWidth = 4, \
}
#define MCAN_CC_CFG_800K \
{ \
.u32NominalPrescaler = 2, \
.u32NominalTimeSeg1 = 20, \
.u32NominalTimeSeg2 = 5, \
.u32NominalSyncJumpWidth = 5, \
#define MCAN_CC_CFG_800K \
{ \
.u32NominalPrescaler = 2, \
.u32NominalTimeSeg1 = 20, \
.u32NominalTimeSeg2 = 5, \
.u32NominalSyncJumpWidth = 5, \
}
#define MCAN_CC_CFG_500K \
{ \
.u32NominalPrescaler = 4, \
.u32NominalTimeSeg1 = 16, \
.u32NominalTimeSeg2 = 4, \
.u32NominalSyncJumpWidth = 4, \
#define MCAN_CC_CFG_500K \
{ \
.u32NominalPrescaler = 4, \
.u32NominalTimeSeg1 = 16, \
.u32NominalTimeSeg2 = 4, \
.u32NominalSyncJumpWidth = 4, \
}
#define MCAN_CC_CFG_250K \
{ \
.u32NominalPrescaler = 4, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
#define MCAN_CC_CFG_250K \
{ \
.u32NominalPrescaler = 4, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
}
#define MCAN_CC_CFG_125K \
{ \
.u32NominalPrescaler = 8, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
#define MCAN_CC_CFG_125K \
{ \
.u32NominalPrescaler = 8, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
}
#define MCAN_CC_CFG_100K \
{ \
.u32NominalPrescaler = 10, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
#define MCAN_CC_CFG_100K \
{ \
.u32NominalPrescaler = 10, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
}
#define MCAN_CC_CFG_50K \
{ \
.u32NominalPrescaler = 20, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
#define MCAN_CC_CFG_50K \
{ \
.u32NominalPrescaler = 20, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
}
#define MCAN_CC_CFG_20K \
{ \
.u32NominalPrescaler = 50, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
#define MCAN_CC_CFG_20K \
{ \
.u32NominalPrescaler = 50, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
}
#define MCAN_CC_CFG_10K \
{ \
.u32NominalPrescaler = 100, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
#define MCAN_CC_CFG_10K \
{ \
.u32NominalPrescaler = 100, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
}
#ifdef RT_CAN_USING_CANFD
#define MCAN1_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M
#define MCAN1_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M
#define MCAN1_DATA_BAUD_RATE CANFD_DATA_BAUD_4M
#define MCAN1_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M
#define MCAN1_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M
#define MCAN1_DATA_BAUD_RATE CANFD_DATA_BAUD_4M
#define MCAN2_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M
#define MCAN2_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M
#define MCAN2_DATA_BAUD_RATE CANFD_DATA_BAUD_4M
#define MCAN2_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M
#define MCAN2_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M
#define MCAN2_DATA_BAUD_RATE CANFD_DATA_BAUD_4M
#else
#define MCAN1_BAUD_RATE_CFG MCAN_CC_CFG_1M
#define MCAN1_NOMINAL_BAUD_RATE CAN1MBaud
#define MCAN1_DATA_BAUD_RATE 0
#define MCAN1_BAUD_RATE_CFG MCAN_CC_CFG_1M
#define MCAN1_NOMINAL_BAUD_RATE CAN1MBaud
#define MCAN1_DATA_BAUD_RATE 0
#define MCAN2_BAUD_RATE_CFG MCAN_CC_CFG_1M
#define MCAN2_NOMINAL_BAUD_RATE CAN1MBaud
#define MCAN2_DATA_BAUD_RATE 0
#define MCAN2_BAUD_RATE_CFG MCAN_CC_CFG_1M
#define MCAN2_NOMINAL_BAUD_RATE CAN1MBaud
#define MCAN2_DATA_BAUD_RATE 0
#endif /* #ifdef RT_CAN_USING_CANFD */

64
bsp/hc32/ev_hc32f334_lqfp64/board/config/pm_config.h
View File

@ -21,18 +21,18 @@ extern "C" {
extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
#ifndef PM_TICKLESS_TIMER_ENABLE_MASK
#define PM_TICKLESS_TIMER_ENABLE_MASK \
( (1UL << PM_SLEEP_MODE_IDLE) | \
(1UL << PM_SLEEP_MODE_DEEP))
#define PM_TICKLESS_TIMER_ENABLE_MASK \
((1UL << PM_SLEEP_MODE_IDLE) | \
(1UL << PM_SLEEP_MODE_DEEP))
#endif
/**
* @brief run mode config @ref pm_run_mode_config structure
*/
#ifndef PM_RUN_MODE_CFG
#define PM_RUN_MODE_CFG \
{ \
.sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \
#define PM_RUN_MODE_CFG \
{ \
.sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \
}
#endif /* PM_RUN_MODE_CFG */
@ -40,50 +40,50 @@ extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
* @brief sleep idle config @ref pm_sleep_mode_idle_config structure
*/
#ifndef PM_SLEEP_IDLE_CFG
#define PM_SLEEP_IDLE_CFG \
{ \
.pwc_sleep_type = PWC_SLEEP_WFE_INT, \
}
#define PM_SLEEP_IDLE_CFG \
{ \
.pwc_sleep_type = PWC_SLEEP_WFE_INT, \
}
#endif /*PM_SLEEP_IDLE_CFG*/
/**
* @brief sleep deep config @ref pm_sleep_mode_deep_config structure
*/
#ifndef PM_SLEEP_DEEP_CFG
#define PM_SLEEP_DEEP_CFG \
{ \
{ \
.u16Clock = PWC_STOP_CLK_KEEP, \
.u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \
}, \
.pwc_stop_type = PWC_STOP_WFE_INT, \
}
#define PM_SLEEP_DEEP_CFG \
{ \
{ \
.u16Clock = PWC_STOP_CLK_KEEP, \
.u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \
}, \
.pwc_stop_type = PWC_STOP_WFE_INT, \
}
#endif /*PM_SLEEP_DEEP_CFG*/
/**
* @brief sleep standby config @ref pm_sleep_mode_standby_config structure
*/
#ifndef PM_SLEEP_STANDBY_CFG
#define PM_SLEEP_STANDBY_CFG \
{ \
{ \
.u8Mode = PWC_PD_MD1, \
.u8IOState = PWC_PD_IO_KEEP1, \
}, \
}
#define PM_SLEEP_STANDBY_CFG \
{ \
{ \
.u8Mode = PWC_PD_MD1, \
.u8IOState = PWC_PD_IO_KEEP1, \
}, \
}
#endif /*PM_SLEEP_STANDBY_CFG*/
/**
* @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure
*/
#ifndef PM_SLEEP_SHUTDOWN_CFG
#define PM_SLEEP_SHUTDOWN_CFG \
{ \
{ \
.u8Mode = PWC_PD_MD3, \
.u8IOState = PWC_PD_IO_KEEP1, \
}, \
}
#define PM_SLEEP_SHUTDOWN_CFG \
{ \
{ \
.u8Mode = PWC_PD_MD3, \
.u8IOState = PWC_PD_IO_KEEP1, \
}, \
}
#endif /*PM_SLEEP_SHUTDOWN_CFG*/
#endif /* BSP_USING_PM */

266
bsp/hc32/ev_hc32f334_lqfp64/board/config/pulse_encoder_config.h
View File

@ -21,182 +21,168 @@ extern "C" {
#ifdef BSP_USING_PULSE_ENCODER_TMRA_1
#ifndef PULSE_ENCODER_TMRA_1_CONFIG
#define PULSE_ENCODER_TMRA_1_CONFIG \
{ \
.tmr_handler = CM_TMRA_1, \
.u32PeriphClock = FCG2_PERIPH_TMRA_1, \
.hw_count = \
{ \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = \
{ \
.enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a1" \
#define PULSE_ENCODER_TMRA_1_CONFIG \
{ \
.tmr_handler = CM_TMRA_1, \
.u32PeriphClock = FCG2_PERIPH_TMRA_1, \
.hw_count = { \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = { \
.enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a1" \
}
#endif /* PULSE_ENCODER_TMRA_1_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
#ifdef BSP_USING_PULSE_ENCODER_TMRA_2
#ifndef PULSE_ENCODER_TMRA_2_CONFIG
#define PULSE_ENCODER_TMRA_2_CONFIG \
{ \
.tmr_handler = CM_TMRA_2, \
.u32PeriphClock = FCG2_PERIPH_TMRA_2, \
.hw_count = \
{ \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = \
{ \
.enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a2" \
#define PULSE_ENCODER_TMRA_2_CONFIG \
{ \
.tmr_handler = CM_TMRA_2, \
.u32PeriphClock = FCG2_PERIPH_TMRA_2, \
.hw_count = { \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = { \
.enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a2" \
}
#endif /* PULSE_ENCODER_TMRA_2_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */
#ifdef BSP_USING_PULSE_ENCODER_TMRA_3
#ifndef PULSE_ENCODER_TMRA_3_CONFIG
#define PULSE_ENCODER_TMRA_3_CONFIG \
{ \
.tmr_handler = CM_TMRA_3, \
.u32PeriphClock = FCG2_PERIPH_TMRA_3, \
.hw_count = \
{ \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = \
{ \
.enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a3" \
#define PULSE_ENCODER_TMRA_3_CONFIG \
{ \
.tmr_handler = CM_TMRA_3, \
.u32PeriphClock = FCG2_PERIPH_TMRA_3, \
.hw_count = { \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = { \
.enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a3" \
}
#endif /* PULSE_ENCODER_TMRA_3_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */
#ifdef BSP_USING_PULSE_ENCODER_TMRA_4
#ifndef PULSE_ENCODER_TMRA_4_CONFIG
#define PULSE_ENCODER_TMRA_4_CONFIG \
{ \
.tmr_handler = CM_TMRA_4, \
.u32PeriphClock = FCG2_PERIPH_TMRA_4, \
.hw_count = \
{ \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = \
{ \
.enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a4" \
#define PULSE_ENCODER_TMRA_4_CONFIG \
{ \
.tmr_handler = CM_TMRA_4, \
.u32PeriphClock = FCG2_PERIPH_TMRA_4, \
.hw_count = { \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = { \
.enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a4" \
}
#endif /* PULSE_ENCODER_TMRA_4_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */
#ifdef BSP_USING_PULSE_ENCODER_TMRA_5
#ifndef PULSE_ENCODER_TMRA_5_CONFIG
#define PULSE_ENCODER_TMRA_5_CONFIG \
{ \
.tmr_handler = CM_TMRA_5, \
.u32PeriphClock = FCG2_PERIPH_TMRA_5, \
.hw_count = \
{ \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = \
{ \
.enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a5" \
#define PULSE_ENCODER_TMRA_5_CONFIG \
{ \
.tmr_handler = CM_TMRA_5, \
.u32PeriphClock = FCG2_PERIPH_TMRA_5, \
.hw_count = { \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = { \
.enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a5" \
}
#endif /* PULSE_ENCODER_TMRA_5_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */
#ifdef BSP_USING_PULSE_ENCODER_TMR6_1
#ifndef PULSE_ENCODER_TMR6_1_CONFIG
#define PULSE_ENCODER_TMR6_1_CONFIG \
{ \
.tmr_handler = CM_TMR6_1, \
.u32PeriphClock = FCG2_PERIPH_TMR6_1, \
.hw_count = \
{ \
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
}, \
.isr = \
{ \
.enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_61" \
#define PULSE_ENCODER_TMR6_1_CONFIG \
{ \
.tmr_handler = CM_TMR6_1, \
.u32PeriphClock = FCG2_PERIPH_TMR6_1, \
.hw_count = { \
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
}, \
.isr = { \
.enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_61" \
}
#endif /* PULSE_ENCODER_TMR6_1_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
#ifdef BSP_USING_PULSE_ENCODER_TMR6_2
#ifndef PULSE_ENCODER_TMR6_2_CONFIG
#define PULSE_ENCODER_TMR6_2_CONFIG \
{ \
.tmr_handler = CM_TMR6_2, \
.u32PeriphClock = FCG2_PERIPH_TMR6_2, \
.hw_count = \
{ \
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
}, \
.isr = \
{ \
.enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_62" \
#define PULSE_ENCODER_TMR6_2_CONFIG \
{ \
.tmr_handler = CM_TMR6_2, \
.u32PeriphClock = FCG2_PERIPH_TMR6_2, \
.hw_count = { \
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
}, \
.isr = { \
.enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_62" \
}
#endif /* PULSE_ENCODER_TMR6_2_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */

595
bsp/hc32/ev_hc32f334_lqfp64/board/config/pwm_tmr_config.h
View File

@ -21,155 +21,135 @@ extern "C" {
#ifdef BSP_USING_PWM_TMRA_1
#ifndef PWM_TMRA_1_CONFIG
#define PWM_TMRA_1_CONFIG \
{ \
.name = "pwm_a1", \
.instance = CM_TMRA_1, \
.channel = 0, \
.stcTmraInit = \
{ \
.u8CountSrc = TMRA_CNT_SRC_SW, \
.u32PeriodValue = 0xFFFF, \
.sw_count = \
{ \
.u8ClockDiv = TMRA_CLK_DIV1, \
.u8CountMode = TMRA_MD_SAWTOOTH, \
.u8CountDir = TMRA_DIR_DOWN, \
}, \
.u8CountReload = TMRA_CNT_RELOAD_ENABLE\
}, \
.stcPwmInit = \
{ \
.u32CompareValue = 0x0000, \
.u16StartPolarity = TMRA_PWM_LOW, \
.u16StopPolarity = TMRA_PWM_LOW, \
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
}, \
#define PWM_TMRA_1_CONFIG \
{ \
.name = "pwm_a1", \
.instance = CM_TMRA_1, \
.channel = 0, \
.stcTmraInit = { \
.u8CountSrc = TMRA_CNT_SRC_SW, \
.u32PeriodValue = 0xFFFF, \
.sw_count = { \
.u8ClockDiv = TMRA_CLK_DIV1, \
.u8CountMode = TMRA_MD_SAWTOOTH, \
.u8CountDir = TMRA_DIR_DOWN, \
}, \
.u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \
.stcPwmInit = { \
.u32CompareValue = 0x0000, \
.u16StartPolarity = TMRA_PWM_LOW, \
.u16StopPolarity = TMRA_PWM_LOW, \
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
}, \
}
#endif /* PWM_TMRA_1_CONFIG */
#endif /* BSP_USING_PWM_TMRA_1 */
#ifdef BSP_USING_PWM_TMRA_2
#ifndef PWM_TMRA_2_CONFIG
#define PWM_TMRA_2_CONFIG \
{ \
.name = "pwm_a2", \
.instance = CM_TMRA_2, \
.channel = 0, \
.stcTmraInit = \
{ \
.u8CountSrc = TMRA_CNT_SRC_SW, \
.u32PeriodValue = 0xFFFF, \
.sw_count = \
{ \
.u8ClockDiv = TMRA_CLK_DIV1, \
.u8CountMode = TMRA_MD_SAWTOOTH, \
.u8CountDir = TMRA_DIR_DOWN, \
}, \
.u8CountReload = TMRA_CNT_RELOAD_ENABLE\
}, \
.stcPwmInit = \
{ \
.u32CompareValue = 0x0000, \
.u16StartPolarity = TMRA_PWM_LOW, \
.u16StopPolarity = TMRA_PWM_LOW, \
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
}, \
#define PWM_TMRA_2_CONFIG \
{ \
.name = "pwm_a2", \
.instance = CM_TMRA_2, \
.channel = 0, \
.stcTmraInit = { \
.u8CountSrc = TMRA_CNT_SRC_SW, \
.u32PeriodValue = 0xFFFF, \
.sw_count = { \
.u8ClockDiv = TMRA_CLK_DIV1, \
.u8CountMode = TMRA_MD_SAWTOOTH, \
.u8CountDir = TMRA_DIR_DOWN, \
}, \
.u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \
.stcPwmInit = { \
.u32CompareValue = 0x0000, \
.u16StartPolarity = TMRA_PWM_LOW, \
.u16StopPolarity = TMRA_PWM_LOW, \
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
}, \
}
#endif /* PWM_TMRA_2_CONFIG */
#endif /* BSP_USING_PWM_TMRA_2 */
#ifdef BSP_USING_PWM_TMRA_3
#ifndef PWM_TMRA_3_CONFIG
#define PWM_TMRA_3_CONFIG \
{ \
.name = "pwm_a3", \
.instance = CM_TMRA_3, \
.channel = 0, \
.stcTmraInit = \
{ \
.u8CountSrc = TMRA_CNT_SRC_SW, \
.u32PeriodValue = 0xFFFF, \
.sw_count = \
{ \
.u8ClockDiv = TMRA_CLK_DIV1, \
.u8CountMode = TMRA_MD_SAWTOOTH, \
.u8CountDir = TMRA_DIR_DOWN, \
}, \
.u8CountReload = TMRA_CNT_RELOAD_ENABLE\
}, \
.stcPwmInit = \
{ \
.u32CompareValue = 0x0000, \
.u16StartPolarity = TMRA_PWM_LOW, \
.u16StopPolarity = TMRA_PWM_LOW, \
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
}, \
#define PWM_TMRA_3_CONFIG \
{ \
.name = "pwm_a3", \
.instance = CM_TMRA_3, \
.channel = 0, \
.stcTmraInit = { \
.u8CountSrc = TMRA_CNT_SRC_SW, \
.u32PeriodValue = 0xFFFF, \
.sw_count = { \
.u8ClockDiv = TMRA_CLK_DIV1, \
.u8CountMode = TMRA_MD_SAWTOOTH, \
.u8CountDir = TMRA_DIR_DOWN, \
}, \
.u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \
.stcPwmInit = { \
.u32CompareValue = 0x0000, \
.u16StartPolarity = TMRA_PWM_LOW, \
.u16StopPolarity = TMRA_PWM_LOW, \
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
}, \
}
#endif /* PWM_TMRA_3_CONFIG */
#endif /* BSP_USING_PWM_TMRA_3 */
#ifdef BSP_USING_PWM_TMRA_4
#ifndef PWM_TMRA_4_CONFIG
#define PWM_TMRA_4_CONFIG \
{ \
.name = "pwm_a4", \
.instance = CM_TMRA_4, \
.channel = 0, \
.stcTmraInit = \
{ \
.u8CountSrc = TMRA_CNT_SRC_SW, \
.u32PeriodValue = 0xFFFF, \
.sw_count = \
{ \
.u8ClockDiv = TMRA_CLK_DIV1, \
.u8CountMode = TMRA_MD_SAWTOOTH, \
.u8CountDir = TMRA_DIR_DOWN, \
}, \
.u8CountReload = TMRA_CNT_RELOAD_ENABLE\
}, \
.stcPwmInit = \
{ \
.u32CompareValue = 0x0000, \
.u16StartPolarity = TMRA_PWM_LOW, \
.u16StopPolarity = TMRA_PWM_LOW, \
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
}, \
#define PWM_TMRA_4_CONFIG \
{ \
.name = "pwm_a4", \
.instance = CM_TMRA_4, \
.channel = 0, \
.stcTmraInit = { \
.u8CountSrc = TMRA_CNT_SRC_SW, \
.u32PeriodValue = 0xFFFF, \
.sw_count = { \
.u8ClockDiv = TMRA_CLK_DIV1, \
.u8CountMode = TMRA_MD_SAWTOOTH, \
.u8CountDir = TMRA_DIR_DOWN, \
}, \
.u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \
.stcPwmInit = { \
.u32CompareValue = 0x0000, \
.u16StartPolarity = TMRA_PWM_LOW, \
.u16StopPolarity = TMRA_PWM_LOW, \
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
}, \
}
#endif /* PWM_TMRA_4_CONFIG */
#endif /* BSP_USING_PWM_TMRA_4 */
#ifdef BSP_USING_PWM_TMRA_5
#ifndef PWM_TMRA_5_CONFIG
#define PWM_TMRA_5_CONFIG \
{ \
.name = "pwm_a5", \
.instance = CM_TMRA_5, \
.channel = 0, \
.stcTmraInit = \
{ \
.u8CountSrc = TMRA_CNT_SRC_SW, \
.u32PeriodValue = 0xFFFF, \
.sw_count = \
{ \
.u8ClockDiv = TMRA_CLK_DIV1, \
.u8CountMode = TMRA_MD_SAWTOOTH, \
.u8CountDir = TMRA_DIR_DOWN, \
}, \
.u8CountReload = TMRA_CNT_RELOAD_ENABLE\
}, \
.stcPwmInit = \
{ \
.u32CompareValue = 0x0000, \
.u16StartPolarity = TMRA_PWM_LOW, \
.u16StopPolarity = TMRA_PWM_LOW, \
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
}, \
#define PWM_TMRA_5_CONFIG \
{ \
.name = "pwm_a5", \
.instance = CM_TMRA_5, \
.channel = 0, \
.stcTmraInit = { \
.u8CountSrc = TMRA_CNT_SRC_SW, \
.u32PeriodValue = 0xFFFF, \
.sw_count = { \
.u8ClockDiv = TMRA_CLK_DIV1, \
.u8CountMode = TMRA_MD_SAWTOOTH, \
.u8CountDir = TMRA_DIR_DOWN, \
}, \
.u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \
.stcPwmInit = { \
.u32CompareValue = 0x0000, \
.u16StartPolarity = TMRA_PWM_LOW, \
.u16StopPolarity = TMRA_PWM_LOW, \
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
}, \
}
#endif /* PWM_TMRA_5_CONFIG */
#endif /* BSP_USING_PWM_TMRA_5 */
@ -179,32 +159,29 @@ extern "C" {
#ifdef BSP_USING_PWM_TMR4_1
#ifndef PWM_TMR4_1_CONFIG
#define PWM_TMR4_1_CONFIG \
{ \
.name = "pwm_t41", \
.instance = CM_TMR4, \
.channel = 0, \
.stcTmr4Init = \
{ \
.u16ClockDiv = TMR4_CLK_DIV1, \
.u16PeriodValue = 0xFFFFU, \
.u16CountMode = TMR4_MD_SAWTOOTH, \
.u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\
}, \
.stcTmr4OcInit = \
{ \
.u16CompareValue = 0x0000, \
.u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \
.u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\
.u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \
.u16BufLinkTransObject = 0U, \
}, \
.stcTmr4PwmInit = \
{ \
.u16Mode = TMR4_PWM_MD_THROUGH, \
.u16ClockDiv = TMR4_PWM_CLK_DIV1, \
.u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\
}, \
#define PWM_TMR4_1_CONFIG \
{ \
.name = "pwm_t41", \
.instance = CM_TMR4, \
.channel = 0, \
.stcTmr4Init = { \
.u16ClockDiv = TMR4_CLK_DIV1, \
.u16PeriodValue = 0xFFFFU, \
.u16CountMode = TMR4_MD_SAWTOOTH, \
.u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \
}, \
.stcTmr4OcInit = { \
.u16CompareValue = 0x0000, \
.u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \
.u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \
.u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \
.u16BufLinkTransObject = 0U, \
}, \
.stcTmr4PwmInit = { \
.u16Mode = TMR4_PWM_MD_THROUGH, \
.u16ClockDiv = TMR4_PWM_CLK_DIV1, \
.u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \
}, \
}
#endif /* PWM_TMR4_1_CONFIG */
#endif /* BSP_USING_PWM_TMR4_1 */
@ -215,189 +192,169 @@ extern "C" {
#ifdef BSP_USING_PWM_TMR6_1
#ifndef PWM_TMR6_1_CONFIG
#define PWM_TMR6_1_CONFIG \
{ \
.name = "pwm_t61", \
.instance = CM_TMR6_1, \
.channel = 0, \
.stcTmr6Init = \
{ \
.u8CountSrc = TMR6_CNT_SRC_SW, \
.sw_count = \
{ \
.u32ClockDiv = TMR6_CLK_DIV1, \
.u32CountMode = TMR6_MD_SAWTOOTH, \
.u32CountDir = TMR6_CNT_DOWN, \
}, \
.u32PeriodValue = 0xFFFF, \
.u32CountReload = TMR6_CNT_RELOAD_ON, \
}, \
.stcPwmInit = \
{ \
{ \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_LOW, \
.u32StopPolarity = TMR6_PWM_LOW, \
.u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \
.u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \
.u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \
.u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
.u32UdfPolarity = TMR6_PWM_LOW, \
.u32OvfPolarity = TMR6_PWM_LOW, \
}, \
{ \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_LOW, \
.u32StopPolarity = TMR6_PWM_LOW, \
.u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \
.u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
.u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \
.u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \
.u32UdfPolarity = TMR6_PWM_LOW, \
.u32OvfPolarity = TMR6_PWM_LOW, \
} \
}, \
#define PWM_TMR6_1_CONFIG \
{ \
.name = "pwm_t61", \
.instance = CM_TMR6_1, \
.channel = 0, \
.stcTmr6Init = { \
.u8CountSrc = TMR6_CNT_SRC_SW, \
.sw_count = { \
.u32ClockDiv = TMR6_CLK_DIV1, \
.u32CountMode = TMR6_MD_SAWTOOTH, \
.u32CountDir = TMR6_CNT_DOWN, \
}, \
.u32PeriodValue = 0xFFFF, \
.u32CountReload = TMR6_CNT_RELOAD_ON, \
}, \
.stcPwmInit = { { \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_LOW, \
.u32StopPolarity = TMR6_PWM_LOW, \
.u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \
.u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \
.u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \
.u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
.u32UdfPolarity = TMR6_PWM_LOW, \
.u32OvfPolarity = TMR6_PWM_LOW, \
}, \
{ \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_LOW, \
.u32StopPolarity = TMR6_PWM_LOW, \
.u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \
.u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
.u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \
.u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \
.u32UdfPolarity = TMR6_PWM_LOW, \
.u32OvfPolarity = TMR6_PWM_LOW, \
} }, \
}
#endif /* PWM_TMR6_1_CONFIG */
#endif /* BSP_USING_PWM_TMR6_1 */
#ifdef BSP_USING_PWM_TMR6_2
#ifndef PWM_TMR6_2_CONFIG
#define PWM_TMR6_2_CONFIG \
{ \
.name = "pwm_t62", \
.instance = CM_TMR6_2, \
.channel = 0, \
.stcTmr6Init = \
{ \
.u8CountSrc = TMR6_CNT_SRC_SW, \
.sw_count = \
{ \
.u32ClockDiv = TMR6_CLK_DIV1, \
.u32CountMode = TMR6_MD_SAWTOOTH, \
.u32CountDir = TMR6_CNT_DOWN, \
}, \
.u32PeriodValue = 0xFFFF, \
.u32CountReload = TMR6_CNT_RELOAD_ON, \
}, \
.stcPwmInit = \
{ \
{ \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_LOW, \
.u32StopPolarity = TMR6_PWM_LOW, \
.u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \
.u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \
.u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \
.u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
.u32UdfPolarity = TMR6_PWM_LOW, \
.u32OvfPolarity = TMR6_PWM_LOW, \
}, \
{ \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_LOW, \
.u32StopPolarity = TMR6_PWM_LOW, \
.u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \
.u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
.u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \
.u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \
.u32UdfPolarity = TMR6_PWM_LOW, \
.u32OvfPolarity = TMR6_PWM_LOW, \
} \
}, \
#define PWM_TMR6_2_CONFIG \
{ \
.name = "pwm_t62", \
.instance = CM_TMR6_2, \
.channel = 0, \
.stcTmr6Init = { \
.u8CountSrc = TMR6_CNT_SRC_SW, \
.sw_count = { \
.u32ClockDiv = TMR6_CLK_DIV1, \
.u32CountMode = TMR6_MD_SAWTOOTH, \
.u32CountDir = TMR6_CNT_DOWN, \
}, \
.u32PeriodValue = 0xFFFF, \
.u32CountReload = TMR6_CNT_RELOAD_ON, \
}, \
.stcPwmInit = { { \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_LOW, \
.u32StopPolarity = TMR6_PWM_LOW, \
.u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \
.u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \
.u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \
.u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
.u32UdfPolarity = TMR6_PWM_LOW, \
.u32OvfPolarity = TMR6_PWM_LOW, \
}, \
{ \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_LOW, \
.u32StopPolarity = TMR6_PWM_LOW, \
.u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \
.u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
.u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \
.u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \
.u32UdfPolarity = TMR6_PWM_LOW, \
.u32OvfPolarity = TMR6_PWM_LOW, \
} }, \
}
#endif /* PWM_TMR6_2_CONFIG */
#endif /* BSP_USING_PWM_TMR6_2 */
#ifdef BSP_USING_PWM_TMR6_3
#ifndef PWM_TMR6_3_CONFIG
#define PWM_TMR6_3_CONFIG \
{ \
.name = "pwm_t63", \
.instance = CM_TMR6_3, \
.channel = 0, \
.stcTmr6Init = \
{ \
.u8CountSrc = TMR6_CNT_SRC_SW, \
.sw_count = \
{ \
.u32ClockDiv = TMR6_CLK_DIV1, \
.u32CountMode = TMR6_MD_SAWTOOTH, \
.u32CountDir = TMR6_CNT_DOWN, \
}, \
.u32PeriodValue = 0xFFFF, \
.u32CountReload = TMR6_CNT_RELOAD_ON, \
}, \
.stcPwmInit = \
{ \
{ \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_LOW, \
.u32StopPolarity = TMR6_PWM_LOW, \
.u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \
.u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \
.u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \
.u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
.u32UdfPolarity = TMR6_PWM_LOW, \
.u32OvfPolarity = TMR6_PWM_LOW, \
}, \
{ \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_LOW, \
.u32StopPolarity = TMR6_PWM_LOW, \
.u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \
.u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
.u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \
.u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \
.u32UdfPolarity = TMR6_PWM_LOW, \
.u32OvfPolarity = TMR6_PWM_LOW, \
} \
}, \
#define PWM_TMR6_3_CONFIG \
{ \
.name = "pwm_t63", \
.instance = CM_TMR6_3, \
.channel = 0, \
.stcTmr6Init = { \
.u8CountSrc = TMR6_CNT_SRC_SW, \
.sw_count = { \
.u32ClockDiv = TMR6_CLK_DIV1, \
.u32CountMode = TMR6_MD_SAWTOOTH, \
.u32CountDir = TMR6_CNT_DOWN, \
}, \
.u32PeriodValue = 0xFFFF, \
.u32CountReload = TMR6_CNT_RELOAD_ON, \
}, \
.stcPwmInit = { { \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_LOW, \
.u32StopPolarity = TMR6_PWM_LOW, \
.u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \
.u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \
.u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \
.u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
.u32UdfPolarity = TMR6_PWM_LOW, \
.u32OvfPolarity = TMR6_PWM_LOW, \
}, \
{ \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_LOW, \
.u32StopPolarity = TMR6_PWM_LOW, \
.u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \
.u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
.u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \
.u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \
.u32UdfPolarity = TMR6_PWM_LOW, \
.u32OvfPolarity = TMR6_PWM_LOW, \
} }, \
}
#endif /* PWM_TMR6_3_CONFIG */
#endif /* BSP_USING_PWM_TMR6_3 */
#ifdef BSP_USING_PWM_TMR6_4
#ifndef PWM_TMR6_4_CONFIG
#define PWM_TMR6_4_CONFIG \
{ \
.name = "pwm_t64", \
.instance = CM_TMR6_4, \
.channel = 0, \
.stcTmr6Init = \
{ \
.u8CountSrc = TMR6_CNT_SRC_SW, \
.sw_count = \
{ \
.u32ClockDiv = TMR6_CLK_DIV1, \
.u32CountMode = TMR6_MD_SAWTOOTH, \
.u32CountDir = TMR6_CNT_DOWN, \
}, \
.u32PeriodValue = 0xFFFF, \
.u32CountReload = TMR6_CNT_RELOAD_ON, \
}, \
.stcPwmInit = \
{ \
{ \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_LOW, \
.u32StopPolarity = TMR6_PWM_LOW, \
.u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \
.u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \
.u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \
.u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
.u32UdfPolarity = TMR6_PWM_LOW, \
.u32OvfPolarity = TMR6_PWM_LOW, \
}, \
{ \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_LOW, \
.u32StopPolarity = TMR6_PWM_LOW, \
.u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \
.u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
.u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \
.u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \
.u32UdfPolarity = TMR6_PWM_LOW, \
.u32OvfPolarity = TMR6_PWM_LOW, \
} \
}, \
#define PWM_TMR6_4_CONFIG \
{ \
.name = "pwm_t64", \
.instance = CM_TMR6_4, \
.channel = 0, \
.stcTmr6Init = { \
.u8CountSrc = TMR6_CNT_SRC_SW, \
.sw_count = { \
.u32ClockDiv = TMR6_CLK_DIV1, \
.u32CountMode = TMR6_MD_SAWTOOTH, \
.u32CountDir = TMR6_CNT_DOWN, \
}, \
.u32PeriodValue = 0xFFFF, \
.u32CountReload = TMR6_CNT_RELOAD_ON, \
}, \
.stcPwmInit = { { \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_LOW, \
.u32StopPolarity = TMR6_PWM_LOW, \
.u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \
.u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \
.u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \
.u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
.u32UdfPolarity = TMR6_PWM_LOW, \
.u32OvfPolarity = TMR6_PWM_LOW, \
}, \
{ \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_LOW, \
.u32StopPolarity = TMR6_PWM_LOW, \
.u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \
.u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
.u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \
.u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \
.u32UdfPolarity = TMR6_PWM_LOW, \
.u32OvfPolarity = TMR6_PWM_LOW, \
} }, \
}
#endif /* PWM_TMR6_4_CONFIG */
#endif /* BSP_USING_PWM_TMR6_4 */

77
bsp/hc32/ev_hc32f334_lqfp64/board/config/spi_config.h
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@ -21,58 +21,55 @@ extern "C" {
#ifdef BSP_USING_SPI1
#ifndef SPI1_BUS_CONFIG
#define SPI1_BUS_CONFIG \
{ \
.Instance = CM_SPI, \
.bus_name = "spi1", \
.clock = FCG1_PERIPH_SPI, \
.timeout = 5000UL, \
.err_irq.irq_config = \
{ \
.irq_num = BSP_SPI1_ERR_IRQ_NUM, \
.irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \
.int_src = INT_SRC_SPI_SPEI, \
}, \
#define SPI1_BUS_CONFIG \
{ \
.Instance = CM_SPI, \
.bus_name = "spi1", \
.clock = FCG1_PERIPH_SPI, \
.timeout = 5000UL, \
.err_irq.irq_config = { \
.irq_num = BSP_SPI1_ERR_IRQ_NUM, \
.irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \
.int_src = INT_SRC_SPI_SPEI, \
}, \
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
{ \
.Instance = SPI1_TX_DMA_INSTANCE, \
.channel = SPI1_TX_DMA_CHANNEL, \
.clock = SPI1_TX_DMA_CLOCK, \
.trigger_select = SPI1_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI_SPTI, \
.flag = SPI1_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = SPI1_TX_DMA_IRQn, \
.irq_prio = SPI1_TX_DMA_INT_PRIO, \
.int_src = SPI1_TX_DMA_INT_SRC, \
} \
#define SPI1_TX_DMA_CONFIG \
{ \
.Instance = SPI1_TX_DMA_INSTANCE, \
.channel = SPI1_TX_DMA_CHANNEL, \
.clock = SPI1_TX_DMA_CLOCK, \
.trigger_select = SPI1_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI_SPTI, \
.flag = SPI1_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = SPI1_TX_DMA_IRQn, \
.irq_prio = SPI1_TX_DMA_INT_PRIO, \
.int_src = SPI1_TX_DMA_INT_SRC, \
} \
}
#endif /* SPI1_TX_DMA_CONFIG */
#endif /* BSP_SPI1_TX_USING_DMA */
#ifdef BSP_SPI1_RX_USING_DMA
#ifndef SPI1_RX_DMA_CONFIG
#define SPI1_RX_DMA_CONFIG \
{ \
.Instance = SPI1_RX_DMA_INSTANCE, \
.channel = SPI1_RX_DMA_CHANNEL, \
.clock = SPI1_RX_DMA_CLOCK, \
.trigger_select = SPI1_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI_SPRI, \
.flag = SPI1_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = SPI1_RX_DMA_IRQn, \
.irq_prio = SPI1_RX_DMA_INT_PRIO, \
.int_src = SPI1_RX_DMA_INT_SRC, \
} \
#define SPI1_RX_DMA_CONFIG \
{ \
.Instance = SPI1_RX_DMA_INSTANCE, \
.channel = SPI1_RX_DMA_CHANNEL, \
.clock = SPI1_RX_DMA_CLOCK, \
.trigger_select = SPI1_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI_SPRI, \
.flag = SPI1_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = SPI1_RX_DMA_IRQn, \
.irq_prio = SPI1_RX_DMA_INT_PRIO, \
.int_src = SPI1_RX_DMA_INT_SRC, \
} \
}
#endif /* SPI1_RX_DMA_CONFIG */
#endif /* BSP_SPI1_RX_USING_DMA */

125
bsp/hc32/ev_hc32f334_lqfp64/board/config/timer_config.h
View File

@ -19,95 +19,90 @@ extern "C" {
#ifdef BSP_USING_TMRA_1
#ifndef TMRA_1_CONFIG
#define TMRA_1_CONFIG \
{ \
.tmr_handle = CM_TMRA_1, \
.clock_source = CLK_BUS_PCLK0, \
.clock = FCG2_PERIPH_TMRA_1, \
.flag = TMRA_FLAG_OVF, \
.isr = \
{ \
.enIntSrc = INT_SRC_TMRA_1_OVF, \
.enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \
}, \
.name = "tmra_1" \
#define TMRA_1_CONFIG \
{ \
.tmr_handle = CM_TMRA_1, \
.clock_source = CLK_BUS_PCLK0, \
.clock = FCG2_PERIPH_TMRA_1, \
.flag = TMRA_FLAG_OVF, \
.isr = { \
.enIntSrc = INT_SRC_TMRA_1_OVF, \
.enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \
}, \
.name = "tmra_1" \
}
#endif /* TMRA_1_CONFIG */
#endif /* BSP_USING_TMRA_1 */
#ifdef BSP_USING_TMRA_2
#ifndef TMRA_2_CONFIG
#define TMRA_2_CONFIG \
{ \
.tmr_handle = CM_TMRA_2, \
.clock_source = CLK_BUS_PCLK0, \
.clock = FCG2_PERIPH_TMRA_2, \
.flag = TMRA_FLAG_OVF, \
.isr = \
{ \
.enIntSrc = INT_SRC_TMRA_2_OVF, \
.enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \
}, \
.name = "tmra_2" \
#define TMRA_2_CONFIG \
{ \
.tmr_handle = CM_TMRA_2, \
.clock_source = CLK_BUS_PCLK0, \
.clock = FCG2_PERIPH_TMRA_2, \
.flag = TMRA_FLAG_OVF, \
.isr = { \
.enIntSrc = INT_SRC_TMRA_2_OVF, \
.enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \
}, \
.name = "tmra_2" \
}
#endif /* TMRA_2_CONFIG */
#endif /* BSP_USING_TMRA_2 */
#ifdef BSP_USING_TMRA_3
#ifndef TMRA_3_CONFIG
#define TMRA_3_CONFIG \
{ \
.tmr_handle = CM_TMRA_3, \
.clock_source = CLK_BUS_PCLK0, \
.clock = FCG2_PERIPH_TMRA_3, \
.flag = TMRA_FLAG_OVF, \
.isr = \
{ \
.enIntSrc = INT_SRC_TMRA_3_OVF, \
.enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \
}, \
.name = "tmra_3" \
#define TMRA_3_CONFIG \
{ \
.tmr_handle = CM_TMRA_3, \
.clock_source = CLK_BUS_PCLK0, \
.clock = FCG2_PERIPH_TMRA_3, \
.flag = TMRA_FLAG_OVF, \
.isr = { \
.enIntSrc = INT_SRC_TMRA_3_OVF, \
.enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \
}, \
.name = "tmra_3" \
}
#endif /* TMRA_3_CONFIG */
#endif /* BSP_USING_TMRA_3 */
#ifdef BSP_USING_TMRA_4
#ifndef TMRA_4_CONFIG
#define TMRA_4_CONFIG \
{ \
.tmr_handle = CM_TMRA_4, \
.clock_source = CLK_BUS_PCLK0, \
.clock = FCG2_PERIPH_TMRA_4, \
.flag = TMRA_FLAG_OVF, \
.isr = \
{ \
.enIntSrc = INT_SRC_TMRA_4_OVF, \
.enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \
}, \
.name = "tmra_4" \
#define TMRA_4_CONFIG \
{ \
.tmr_handle = CM_TMRA_4, \
.clock_source = CLK_BUS_PCLK0, \
.clock = FCG2_PERIPH_TMRA_4, \
.flag = TMRA_FLAG_OVF, \
.isr = { \
.enIntSrc = INT_SRC_TMRA_4_OVF, \
.enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \
}, \
.name = "tmra_4" \
}
#endif /* TMRA_4_CONFIG */
#endif /* BSP_USING_TMRA_4 */
#ifdef BSP_USING_TMRA_5
#ifndef TMRA_5_CONFIG
#define TMRA_5_CONFIG \
{ \
.tmr_handle = CM_TMRA_5, \
.clock_source = CLK_BUS_PCLK1, \
.clock = FCG2_PERIPH_TMRA_5, \
.flag = TMRA_FLAG_OVF, \
.isr = \
{ \
.enIntSrc = INT_SRC_TMRA_5_OVF, \
.enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \
}, \
.name = "tmra_5" \
#define TMRA_5_CONFIG \
{ \
.tmr_handle = CM_TMRA_5, \
.clock_source = CLK_BUS_PCLK1, \
.clock = FCG2_PERIPH_TMRA_5, \
.flag = TMRA_FLAG_OVF, \
.isr = { \
.enIntSrc = INT_SRC_TMRA_5_OVF, \
.enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \
}, \
.name = "tmra_5" \
}
#endif /* TMRA_5_CONFIG */
#endif /* BSP_USING_TMRA_5 */

96
bsp/hc32/ev_hc32f334_lqfp64/board/config/tmr_capture_config.h
View File

@ -17,64 +17,64 @@
extern "C" {
#endif
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1)
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1)
#define IC1_NAME "ic1"
#define INPUT_CAPTURE_CFG_TMR6_1 \
{ \
.name = IC1_NAME, \
.ch = TMR6_CH_A, \
.clk_div = TMR6_CLK_DIV32, \
.first_edge = TMR6_CAPT_COND_PWMA_RISING, \
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \
}
#define INPUT_CAPTURE_CFG_TMR6_1 \
{ \
.name = IC1_NAME, \
.ch = TMR6_CH_A, \
.clk_div = TMR6_CLK_DIV32, \
.first_edge = TMR6_CAPT_COND_PWMA_RISING, \
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \
}
#endif
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2)
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2)
#define IC2_NAME "ic2"
#define INPUT_CAPTURE_CFG_TMR6_2 \
{ \
.name = IC2_NAME, \
.ch = TMR6_CH_A, \
.clk_div = TMR6_CLK_DIV32, \
.first_edge = TMR6_CAPT_COND_PWMA_RISING, \
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \
}
#define INPUT_CAPTURE_CFG_TMR6_2 \
{ \
.name = IC2_NAME, \
.ch = TMR6_CH_A, \
.clk_div = TMR6_CLK_DIV32, \
.first_edge = TMR6_CAPT_COND_PWMA_RISING, \
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \
}
#endif
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3)
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3)
#define IC3_NAME "ic3"
#define INPUT_CAPTURE_CFG_TMR6_3 \
{ \
.name = IC3_NAME, \
.ch = TMR6_CH_B, \
.clk_div = TMR6_CLK_DIV16, \
.first_edge = TMR6_CAPT_COND_TRIGD_RISING, \
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM, \
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO, \
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM, \
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO, \
}
#define INPUT_CAPTURE_CFG_TMR6_3 \
{ \
.name = IC3_NAME, \
.ch = TMR6_CH_B, \
.clk_div = TMR6_CLK_DIV16, \
.first_edge = TMR6_CAPT_COND_TRIGD_RISING, \
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM, \
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO, \
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM, \
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO, \
}
#endif
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_4)
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_4)
#define IC4_NAME "ic4"
#define INPUT_CAPTURE_CFG_TMR6_4 \
{ \
.name = IC4_NAME, \
.ch = TMR6_CH_B, \
.clk_div = TMR6_CLK_DIV16, \
.first_edge = TMR6_CAPT_COND_PWMA_RISING, \
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_NUM, \
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_PRIO, \
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_NUM, \
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_PRIO, \
}
#define INPUT_CAPTURE_CFG_TMR6_4 \
{ \
.name = IC4_NAME, \
.ch = TMR6_CH_B, \
.clk_div = TMR6_CLK_DIV16, \
.first_edge = TMR6_CAPT_COND_PWMA_RISING, \
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_NUM, \
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_PRIO, \
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_NUM, \
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_PRIO, \
}
#endif
#ifdef __cplusplus

456
bsp/hc32/ev_hc32f334_lqfp64/board/config/uart_config.h
View File

@ -21,90 +21,86 @@ extern "C" {
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = CM_USART1, \
.clock = FCG3_PERIPH_USART1, \
.irq_num = BSP_UART1_IRQ_NUM, \
.rxerr_int_src = INT_SRC_USART1_EI, \
.rx_int_src = INT_SRC_USART1_RI, \
.tx_int_src = INT_SRC_USART1_TI, \
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = CM_USART1, \
.clock = FCG3_PERIPH_USART1, \
.irq_num = BSP_UART1_IRQ_NUM, \
.rxerr_int_src = INT_SRC_USART1_EI, \
.rx_int_src = INT_SRC_USART1_RI, \
.tx_int_src = INT_SRC_USART1_TI, \
}
#endif /* UART1_CONFIG */
#if defined(BSP_UART1_RX_USING_DMA)
#ifndef UART1_DMA_RX_CONFIG
#define UART1_DMA_RX_CONFIG \
{ \
.Instance = UART1_RX_DMA_INSTANCE, \
.channel = UART1_RX_DMA_CHANNEL, \
.clock = UART1_RX_DMA_CLOCK, \
.trigger_select = UART1_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART1_RI, \
.flag = UART1_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = UART1_RX_DMA_IRQn, \
.irq_prio = UART1_RX_DMA_INT_PRIO, \
.int_src = UART1_RX_DMA_INT_SRC, \
}, \
#define UART1_DMA_RX_CONFIG \
{ \
.Instance = UART1_RX_DMA_INSTANCE, \
.channel = UART1_RX_DMA_CHANNEL, \
.clock = UART1_RX_DMA_CLOCK, \
.trigger_select = UART1_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART1_RI, \
.flag = UART1_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = UART1_RX_DMA_IRQn, \
.irq_prio = UART1_RX_DMA_INT_PRIO, \
.int_src = UART1_RX_DMA_INT_SRC, \
}, \
}
#endif /* UART1_DMA_RX_CONFIG */
#ifndef UART1_RXTO_CONFIG
#define UART1_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_1, \
.channel = TMR0_CH_A, \
.clock = FCG2_PERIPH_TMR0_1, \
.timeout_bits = 20UL, \
#define UART1_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_1, \
.channel = TMR0_CH_A, \
.clock = FCG2_PERIPH_TMR0_1, \
.timeout_bits = 20UL, \
}
#endif /* UART1_RXTO_CONFIG */
#endif /* BSP_UART1_RX_USING_DMA */
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)
#ifndef UART1_TX_CPLT_CONFIG
#define UART1_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART1_TCI, \
}, \
#define UART1_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART1_TCI, \
}, \
}
#endif
#elif defined(RT_USING_SERIAL_V2)
#ifndef UART1_TX_CPLT_CONFIG
#define UART1_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART1_TCI, \
}, \
#define UART1_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART1_TCI, \
}, \
}
#endif
#endif /* UART1_TX_CPLT_CONFIG */
#if defined(BSP_UART1_TX_USING_DMA)
#ifndef UART1_DMA_TX_CONFIG
#define UART1_DMA_TX_CONFIG \
{ \
.Instance = UART1_TX_DMA_INSTANCE, \
.channel = UART1_TX_DMA_CHANNEL, \
.clock = UART1_TX_DMA_CLOCK, \
.trigger_select = UART1_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART1_TI, \
.flag = UART1_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = UART1_TX_DMA_IRQn, \
.irq_prio = UART1_TX_DMA_INT_PRIO, \
.int_src = UART1_TX_DMA_INT_SRC, \
}, \
#define UART1_DMA_TX_CONFIG \
{ \
.Instance = UART1_TX_DMA_INSTANCE, \
.channel = UART1_TX_DMA_CHANNEL, \
.clock = UART1_TX_DMA_CLOCK, \
.trigger_select = UART1_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART1_TI, \
.flag = UART1_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = UART1_TX_DMA_IRQn, \
.irq_prio = UART1_TX_DMA_INT_PRIO, \
.int_src = UART1_TX_DMA_INT_SRC, \
}, \
}
#endif /* UART1_DMA_TX_CONFIG */
#endif /* BSP_UART1_TX_USING_DMA */
@ -112,90 +108,86 @@ extern "C" {
#if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = CM_USART2, \
.clock = FCG3_PERIPH_USART2, \
.irq_num = BSP_UART2_IRQ_NUM, \
.rxerr_int_src = INT_SRC_USART2_EI, \
.rx_int_src = INT_SRC_USART2_RI, \
.tx_int_src = INT_SRC_USART2_TI, \
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = CM_USART2, \
.clock = FCG3_PERIPH_USART2, \
.irq_num = BSP_UART2_IRQ_NUM, \
.rxerr_int_src = INT_SRC_USART2_EI, \
.rx_int_src = INT_SRC_USART2_RI, \
.tx_int_src = INT_SRC_USART2_TI, \
}
#endif /* UART2_CONFIG */
#if defined(BSP_UART2_RX_USING_DMA)
#ifndef UART2_DMA_RX_CONFIG
#define UART2_DMA_RX_CONFIG \
{ \
.Instance = UART2_RX_DMA_INSTANCE, \
.channel = UART2_RX_DMA_CHANNEL, \
.clock = UART2_RX_DMA_CLOCK, \
.trigger_select = UART2_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART2_RI, \
.flag = UART2_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = UART2_RX_DMA_IRQn, \
.irq_prio = UART2_RX_DMA_INT_PRIO, \
.int_src = UART2_RX_DMA_INT_SRC, \
}, \
#define UART2_DMA_RX_CONFIG \
{ \
.Instance = UART2_RX_DMA_INSTANCE, \
.channel = UART2_RX_DMA_CHANNEL, \
.clock = UART2_RX_DMA_CLOCK, \
.trigger_select = UART2_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART2_RI, \
.flag = UART2_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = UART2_RX_DMA_IRQn, \
.irq_prio = UART2_RX_DMA_INT_PRIO, \
.int_src = UART2_RX_DMA_INT_SRC, \
}, \
}
#endif /* UART2_DMA_RX_CONFIG */
#ifndef UART2_RXTO_CONFIG
#define UART2_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_1, \
.channel = TMR0_CH_B, \
.clock = FCG2_PERIPH_TMR0_1, \
.timeout_bits = 20UL, \
#define UART2_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_1, \
.channel = TMR0_CH_B, \
.clock = FCG2_PERIPH_TMR0_1, \
.timeout_bits = 20UL, \
}
#endif /* UART2_RXTO_CONFIG */
#endif /* BSP_UART2_RX_USING_DMA */
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)
#ifndef UART2_TX_CPLT_CONFIG
#define UART2_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART2_TCI, \
}, \
#define UART2_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART2_TCI, \
}, \
}
#endif
#elif defined(RT_USING_SERIAL_V2)
#ifndef UART2_TX_CPLT_CONFIG
#define UART2_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART2_TCI, \
}, \
#define UART2_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART2_TCI, \
}, \
}
#endif
#endif /* UART2_TX_CPLT_CONFIG */
#if defined(BSP_UART2_TX_USING_DMA)
#ifndef UART2_DMA_TX_CONFIG
#define UART2_DMA_TX_CONFIG \
{ \
.Instance = UART2_TX_DMA_INSTANCE, \
.channel = UART2_TX_DMA_CHANNEL, \
.clock = UART2_TX_DMA_CLOCK, \
.trigger_select = UART2_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART2_TI, \
.flag = UART2_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = UART2_TX_DMA_IRQn, \
.irq_prio = UART2_TX_DMA_INT_PRIO, \
.int_src = UART2_TX_DMA_INT_SRC, \
}, \
#define UART2_DMA_TX_CONFIG \
{ \
.Instance = UART2_TX_DMA_INSTANCE, \
.channel = UART2_TX_DMA_CHANNEL, \
.clock = UART2_TX_DMA_CLOCK, \
.trigger_select = UART2_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART2_TI, \
.flag = UART2_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = UART2_TX_DMA_IRQn, \
.irq_prio = UART2_TX_DMA_INT_PRIO, \
.int_src = UART2_TX_DMA_INT_SRC, \
}, \
}
#endif /* UART2_DMA_TX_CONFIG */
#endif /* BSP_UART2_TX_USING_DMA */
@ -203,90 +195,86 @@ extern "C" {
#if defined(BSP_USING_UART3)
#ifndef UART3_CONFIG
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = CM_USART3, \
.clock = FCG3_PERIPH_USART3, \
.irq_num = BSP_UART3_IRQ_NUM, \
.rxerr_int_src = INT_SRC_USART3_EI, \
.rx_int_src = INT_SRC_USART3_RI, \
.tx_int_src = INT_SRC_USART3_TI, \
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = CM_USART3, \
.clock = FCG3_PERIPH_USART3, \
.irq_num = BSP_UART3_IRQ_NUM, \
.rxerr_int_src = INT_SRC_USART3_EI, \
.rx_int_src = INT_SRC_USART3_RI, \
.tx_int_src = INT_SRC_USART3_TI, \
}
#endif /* UART3_CONFIG */
#if defined(BSP_UART3_RX_USING_DMA)
#ifndef UART3_DMA_RX_CONFIG
#define UART3_DMA_RX_CONFIG \
{ \
.Instance = UART3_RX_DMA_INSTANCE, \
.channel = UART3_RX_DMA_CHANNEL, \
.clock = UART3_RX_DMA_CLOCK, \
.trigger_select = UART3_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART3_RI, \
.flag = UART3_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = UART3_RX_DMA_IRQn, \
.irq_prio = UART3_RX_DMA_INT_PRIO, \
.int_src = UART3_RX_DMA_INT_SRC, \
}, \
#define UART3_DMA_RX_CONFIG \
{ \
.Instance = UART3_RX_DMA_INSTANCE, \
.channel = UART3_RX_DMA_CHANNEL, \
.clock = UART3_RX_DMA_CLOCK, \
.trigger_select = UART3_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART3_RI, \
.flag = UART3_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = UART3_RX_DMA_IRQn, \
.irq_prio = UART3_RX_DMA_INT_PRIO, \
.int_src = UART3_RX_DMA_INT_SRC, \
}, \
}
#endif /* UART3_DMA_RX_CONFIG */
#ifndef UART3_RXTO_CONFIG
#define UART3_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_2, \
.channel = TMR0_CH_B, \
.clock = FCG2_PERIPH_TMR0_2, \
.timeout_bits = 20UL, \
#define UART3_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_2, \
.channel = TMR0_CH_B, \
.clock = FCG2_PERIPH_TMR0_2, \
.timeout_bits = 20UL, \
}
#endif /* UART3_RXTO_CONFIG */
#endif /* BSP_UART3_RX_USING_DMA */
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART3_TX_USING_DMA)
#ifndef UART3_TX_CPLT_CONFIG
#define UART3_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART3_TCI, \
}, \
#define UART3_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART3_TCI, \
}, \
}
#endif
#elif defined(RT_USING_SERIAL_V2)
#ifndef UART3_TX_CPLT_CONFIG
#define UART3_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART3_TCI, \
}, \
#define UART3_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART3_TCI, \
}, \
}
#endif
#endif /* UART3_TX_CPLT_CONFIG */
#if defined(BSP_UART3_TX_USING_DMA)
#ifndef UART3_DMA_TX_CONFIG
#define UART3_DMA_TX_CONFIG \
{ \
.Instance = UART3_TX_DMA_INSTANCE, \
.channel = UART3_TX_DMA_CHANNEL, \
.clock = UART3_TX_DMA_CLOCK, \
.trigger_select = UART3_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART3_TI, \
.flag = UART3_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = UART3_TX_DMA_IRQn, \
.irq_prio = UART3_TX_DMA_INT_PRIO, \
.int_src = UART3_TX_DMA_INT_SRC, \
}, \
#define UART3_DMA_TX_CONFIG \
{ \
.Instance = UART3_TX_DMA_INSTANCE, \
.channel = UART3_TX_DMA_CHANNEL, \
.clock = UART3_TX_DMA_CLOCK, \
.trigger_select = UART3_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART3_TI, \
.flag = UART3_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = UART3_TX_DMA_IRQn, \
.irq_prio = UART3_TX_DMA_INT_PRIO, \
.int_src = UART3_TX_DMA_INT_SRC, \
}, \
}
#endif /* UART3_DMA_TX_CONFIG */
#endif /* BSP_UART3_TX_USING_DMA */
@ -294,90 +282,86 @@ extern "C" {
#if defined(BSP_USING_UART4)
#ifndef UART4_CONFIG
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = CM_USART4, \
.clock = FCG3_PERIPH_USART4, \
.irq_num = BSP_UART4_IRQ_NUM, \
.rxerr_int_src = INT_SRC_USART4_EI, \
.rx_int_src = INT_SRC_USART4_RI, \
.tx_int_src = INT_SRC_USART4_TI, \
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = CM_USART4, \
.clock = FCG3_PERIPH_USART4, \
.irq_num = BSP_UART4_IRQ_NUM, \
.rxerr_int_src = INT_SRC_USART4_EI, \
.rx_int_src = INT_SRC_USART4_RI, \
.tx_int_src = INT_SRC_USART4_TI, \
}
#endif /* UART4_CONFIG */
#if defined(BSP_UART4_RX_USING_DMA)
#ifndef UART4_DMA_RX_CONFIG
#define UART4_DMA_RX_CONFIG \
{ \
.Instance = UART4_RX_DMA_INSTANCE, \
.channel = UART4_RX_DMA_CHANNEL, \
.clock = UART4_RX_DMA_CLOCK, \
.trigger_select = UART4_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART4_RI, \
.flag = UART4_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = UART4_RX_DMA_IRQn, \
.irq_prio = UART4_RX_DMA_INT_PRIO, \
.int_src = UART4_RX_DMA_INT_SRC, \
}, \
#define UART4_DMA_RX_CONFIG \
{ \
.Instance = UART4_RX_DMA_INSTANCE, \
.channel = UART4_RX_DMA_CHANNEL, \
.clock = UART4_RX_DMA_CLOCK, \
.trigger_select = UART4_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART4_RI, \
.flag = UART4_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = UART4_RX_DMA_IRQn, \
.irq_prio = UART4_RX_DMA_INT_PRIO, \
.int_src = UART4_RX_DMA_INT_SRC, \
}, \
}
#endif /* UART4_DMA_RX_CONFIG */
#ifndef UART4_RXTO_CONFIG
#define UART4_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_2, \
.channel = TMR0_CH_B, \
.clock = FCG2_PERIPH_TMR0_2, \
.timeout_bits = 20UL, \
#define UART4_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_2, \
.channel = TMR0_CH_B, \
.clock = FCG2_PERIPH_TMR0_2, \
.timeout_bits = 20UL, \
}
#endif /* UART4_RXTO_CONFIG */
#endif /* BSP_UART4_RX_USING_DMA */
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)
#ifndef UART4_TX_CPLT_CONFIG
#define UART4_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART4_TCI, \
}, \
#define UART4_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART4_TCI, \
}, \
}
#endif
#elif defined(RT_USING_SERIAL_V2)
#ifndef UART4_TX_CPLT_CONFIG
#define UART4_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART4_TCI, \
}, \
#define UART4_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART4_TCI, \
}, \
}
#endif
#endif /* UART4_TX_CPLT_CONFIG */
#if defined(BSP_UART4_TX_USING_DMA)
#ifndef UART4_DMA_TX_CONFIG
#define UART4_DMA_TX_CONFIG \
{ \
.Instance = UART4_TX_DMA_INSTANCE, \
.channel = UART4_TX_DMA_CHANNEL, \
.clock = UART4_TX_DMA_CLOCK, \
.trigger_select = UART4_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART4_TI, \
.flag = UART4_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = UART4_TX_DMA_IRQn, \
.irq_prio = UART4_TX_DMA_INT_PRIO, \
.int_src = UART4_TX_DMA_INT_SRC, \
}, \
#define UART4_DMA_TX_CONFIG \
{ \
.Instance = UART4_TX_DMA_INSTANCE, \
.channel = UART4_TX_DMA_CHANNEL, \
.clock = UART4_TX_DMA_CLOCK, \
.trigger_select = UART4_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART4_TI, \
.flag = UART4_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = UART4_TX_DMA_IRQn, \
.irq_prio = UART4_TX_DMA_INT_PRIO, \
.int_src = UART4_TX_DMA_INT_SRC, \
}, \
}
#endif /* UART4_DMA_TX_CONFIG */
#endif /* BSP_UART4_TX_USING_DMA */

85
bsp/hc32/ev_hc32f334_lqfp64/board/hc32f3xx_conf.h
View File

@ -27,8 +27,7 @@
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
extern "C" {
#endif
/*******************************************************************************
@ -48,48 +47,48 @@ extern "C"
* Library.
* @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function.
*/
#define LL_ICG_ENABLE (DDL_ON)
#define LL_UTILITY_ENABLE (DDL_ON)
#define LL_PRINT_ENABLE (DDL_OFF)
#define LL_ICG_ENABLE (DDL_ON)
#define LL_UTILITY_ENABLE (DDL_ON)
#define LL_PRINT_ENABLE (DDL_OFF)
#define LL_ADC_ENABLE (DDL_ON)
#define LL_AOS_ENABLE (DDL_ON)
#define LL_CLK_ENABLE (DDL_ON)
#define LL_CMP_ENABLE (DDL_ON)
#define LL_CRC_ENABLE (DDL_ON)
#define LL_CTC_ENABLE (DDL_ON)
#define LL_DAC_ENABLE (DDL_ON)
#define LL_DBGC_ENABLE (DDL_OFF)
#define LL_DMA_ENABLE (DDL_ON)
#define LL_EFM_ENABLE (DDL_ON)
#define LL_EMB_ENABLE (DDL_ON)
#define LL_EVENT_PORT_ENABLE (DDL_OFF)
#define LL_FCG_ENABLE (DDL_ON)
#define LL_FCM_ENABLE (DDL_ON)
#define LL_HRPWM_ENABLE (DDL_ON)
#define LL_GPIO_ENABLE (DDL_ON)
#define LL_I2C_ENABLE (DDL_ON)
#define LL_INTERRUPTS_ENABLE (DDL_ON)
#define LL_MCAN_ENABLE (DDL_ON)
#define LL_MPU_ENABLE (DDL_ON)
#define LL_PLA_ENABLE (DDL_ON)
#define LL_PWC_ENABLE (DDL_ON)
#define LL_RMU_ENABLE (DDL_ON)
#define LL_RTC_ENABLE (DDL_ON)
#define LL_SPI_ENABLE (DDL_ON)
#define LL_SRAM_ENABLE (DDL_ON)
#define LL_SWDT_ENABLE (DDL_ON)
#define LL_TMR0_ENABLE (DDL_ON)
#define LL_TMR4_ENABLE (DDL_ON)
#define LL_TMR6_ENABLE (DDL_ON)
#define LL_TMRA_ENABLE (DDL_ON)
#define LL_USART_ENABLE (DDL_ON)
#define LL_WDT_ENABLE (DDL_ON)
#define LL_ADC_ENABLE (DDL_ON)
#define LL_AOS_ENABLE (DDL_ON)
#define LL_CLK_ENABLE (DDL_ON)
#define LL_CMP_ENABLE (DDL_ON)
#define LL_CRC_ENABLE (DDL_ON)
#define LL_CTC_ENABLE (DDL_ON)
#define LL_DAC_ENABLE (DDL_ON)
#define LL_DBGC_ENABLE (DDL_OFF)
#define LL_DMA_ENABLE (DDL_ON)
#define LL_EFM_ENABLE (DDL_ON)
#define LL_EMB_ENABLE (DDL_ON)
#define LL_EVENT_PORT_ENABLE (DDL_OFF)
#define LL_FCG_ENABLE (DDL_ON)
#define LL_FCM_ENABLE (DDL_ON)
#define LL_HRPWM_ENABLE (DDL_ON)
#define LL_GPIO_ENABLE (DDL_ON)
#define LL_I2C_ENABLE (DDL_ON)
#define LL_INTERRUPTS_ENABLE (DDL_ON)
#define LL_MCAN_ENABLE (DDL_ON)
#define LL_MPU_ENABLE (DDL_ON)
#define LL_PLA_ENABLE (DDL_ON)
#define LL_PWC_ENABLE (DDL_ON)
#define LL_RMU_ENABLE (DDL_ON)
#define LL_RTC_ENABLE (DDL_ON)
#define LL_SPI_ENABLE (DDL_ON)
#define LL_SRAM_ENABLE (DDL_ON)
#define LL_SWDT_ENABLE (DDL_ON)
#define LL_TMR0_ENABLE (DDL_ON)
#define LL_TMR4_ENABLE (DDL_ON)
#define LL_TMR6_ENABLE (DDL_ON)
#define LL_TMRA_ENABLE (DDL_ON)
#define LL_USART_ENABLE (DDL_ON)
#define LL_WDT_ENABLE (DDL_ON)
/**
* @brief The following is a list of currently supported BSP boards.
*/
#define BSP_EV_HC32F334_LQFP64 (1U)
#define BSP_EV_HC32F334_LQFP64 (1U)
/**
* @brief The macro BSP_EV_HC32F3XX is used to specify the BSP board currently
@ -98,15 +97,15 @@ extern "C"
* @note If there is no supported BSP board or the BSP function is not used,
* the value needs to be set to 0U.
*/
#define BSP_EV_HC32F3XX (0U)
#define BSP_EV_HC32F3XX (0U)
/**
* @brief This is the list of BSP components to be used.
* Select the components you need to use to DDL_ON.
*/
#define BSP_24CXX_ENABLE (DDL_OFF)
#define BSP_W25QXX_ENABLE (DDL_OFF)
#define BSP_INT_KEY_ENABLE (DDL_OFF)
#define BSP_24CXX_ENABLE (DDL_OFF)
#define BSP_W25QXX_ENABLE (DDL_OFF)
#define BSP_INT_KEY_ENABLE (DDL_OFF)
/*******************************************************************************
* Global variable definitions ('extern')

20
bsp/hc32/ev_hc32f334_lqfp64/board/ports/fal_cfg.h
View File

@ -23,20 +23,20 @@ extern const struct fal_flash_dev hc32_onchip_flash;
extern struct fal_flash_dev ext_nor_flash0;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&hc32_onchip_flash, \
&ext_nor_flash0, \
}
#define FAL_FLASH_DEV_TABLE \
{ \
&hc32_onchip_flash, \
&ext_nor_flash0, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 128 * 1024, 0}, \
{FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0}, \
}
#define FAL_PART_TABLE \
{ \
{ FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 128 * 1024, 0 }, \
{ FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0 }, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#endif /* _FAL_CFG_H_ */

10
bsp/hc32/ev_hc32f334_lqfp64/rtconfig.h
View File

@ -72,7 +72,7 @@
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
#define IDLE_THREAD_STACK_SIZE 512
/* kservice options */
@ -326,14 +326,6 @@
/* GD32 Drivers */
/* end of GD32 Drivers */
/* HPMicro SDK */
/* end of HPMicro SDK */
/* FT32 HAL & SDK Drivers */
/* end of FT32 HAL & SDK Drivers */
/* end of HAL & SDK Drivers */
/* sensors drivers */

8
bsp/hc32/ev_hc32f448_lqfp80/.ci/attachconfig/ci.attachconfig.yml
View File

@ -22,11 +22,11 @@ devices.flash:
- CONFIG_RT_USING_SPI=y
- CONFIG_RT_USING_SFUD=y
devices.gpio:
kconfig:
- CONFIG_BSP_USING_GPIO=y
devices.hwtimer:
kconfig:
- CONFIG_BSP_USING_HWTIMER=y
- CONFIG_BSP_USING_GPIO=y
devices.clock_timer:
kconfig:
- CONFIG_BSP_USING_CLOCK_TIMER=y
- CONFIG_BSP_USING_TMRA_1=y
devices.i2c:
kconfig:

2
bsp/hc32/ev_hc32f448_lqfp80/.config
View File

@ -125,7 +125,7 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y
# CONFIG_RT_USING_HOOKLIST is not set
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
CONFIG_IDLE_THREAD_STACK_SIZE=512
# CONFIG_RT_USING_TIMER_SOFT is not set
# CONFIG_RT_USING_CPU_USAGE_TRACER is not set

2
bsp/hc32/ev_hc32f448_lqfp80/README.md
View File

@ -47,7 +47,7 @@ EV_F448_LQ80 开发板常用 **板载资源** 如下：
| DAC | 支持 | |
| FLASH | 支持 | |
| GPIO | 支持 | PA0，PA1...PH2 ---> PIN：0，1...82 |
| HwTimer | 支持 | |
| CLOCK_TIMER | 支持 | |
| I2C | 支持 | 软件、硬件 I2C |
| InputCapture | 支持 | |
| MCAN | 支持 | |

14
bsp/hc32/ev_hc32f448_lqfp80/applications/xtal32_fcm.c
View File

@ -19,7 +19,7 @@
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
#define XTAL32_FCM_THREAD_STACK_SIZE (1024)
#define XTAL32_FCM_THREAD_STACK_SIZE (1024)
/**
* @brief This thread is used to monitor whether XTAL32 is stable.
@ -36,13 +36,13 @@ void xtal32_fcm_thread_entry(void *parameter)
/* FCM config */
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE);
(void)FCM_StructInit(&stcFcmInit);
stcFcmInit.u32RefClock = FCM_REF_CLK_MRC;
stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */
stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING;
stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32;
stcFcmInit.u32RefClock = FCM_REF_CLK_MRC;
stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */
stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING;
stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32;
stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1;
stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
(void)FCM_Init(&stcFcmInit);
/* Enable FCM, to ensure xtal32 stable */
FCM_Cmd(ENABLE);

12
bsp/hc32/ev_hc32f448_lqfp80/board/Kconfig
View File

@ -641,24 +641,24 @@ menu "On-chip Peripheral Drivers"
endif
menuconfig BSP_USING_CLOCK_TIMER
bool "Enable Hw Timer"
bool "Enable Clock Timer"
default n
select RT_USING_CLOCK_TIME
if BSP_USING_CLOCK_TIMER
config BSP_USING_TMRA_1
bool "Use Timer_a1 As The Hw Timer"
bool "Use Timer_a1 As The Clock Timer"
default n
config BSP_USING_TMRA_2
bool "Use Timer_a2 As The Hw Timer"
bool "Use Timer_a2 As The Clock Timer"
default n
config BSP_USING_TMRA_3
bool "Use Timer_a3 As The Hw Timer"
bool "Use Timer_a3 As The Clock Timer"
default n
config BSP_USING_TMRA_4
bool "Use Timer_a4 As The Hw Timer"
bool "Use Timer_a4 As The Clock Timer"
default n
config BSP_USING_TMRA_5
bool "Use Timer_a5 As The Hw Timer"
bool "Use Timer_a5 As The Clock Timer"
default n
endif

16
bsp/hc32/ev_hc32f448_lqfp80/board/board.c
View File

@ -14,9 +14,9 @@
#include "board_config.h"
/* unlock/lock peripheral */
#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD)
#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM)
#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD)
#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM)
/** System Base Configuration
*/
@ -58,9 +58,9 @@ void SystemClock_Config(void)
GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE);
(void)CLK_XtalStructInit(&stcXtalInit);
/* Config Xtal and enable Xtal */
stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW;
stcXtalInit.u8State = CLK_XTAL_ON;
stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW;
stcXtalInit.u8State = CLK_XTAL_ON;
stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
(void)CLK_XtalInit(&stcXtalInit);
@ -86,8 +86,8 @@ void SystemClock_Config(void)
/* Xtal32 config */
GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE);
(void)CLK_Xtal32StructInit(&stcXtal32Init);
stcXtal32Init.u8State = CLK_XTAL32_ON;
stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH;
stcXtal32Init.u8State = CLK_XTAL32_ON;
stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH;
stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD;
(void)CLK_Xtal32Init(&stcXtal32Init);
#endif

24
bsp/hc32/ev_hc32f448_lqfp80/board/board.h
View File

@ -20,27 +20,27 @@
extern "C" {
#endif
#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024)
#define HC32_FLASH_WRITE_GRANULARITY (4)
#define HC32_FLASH_SIZE (256 * 1024)
#define HC32_FLASH_START_ADDRESS (0)
#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024)
#define HC32_FLASH_WRITE_GRANULARITY (4)
#define HC32_FLASH_SIZE (256 * 1024)
#define HC32_FLASH_START_ADDRESS (0)
#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
#define HC32_SRAM_SIZE (64)
#define HC32_SRAM_END (0x1FFF8000 + HC32_SRAM_SIZE * 1024)
#define HC32_SRAM_SIZE (64)
#define HC32_SRAM_END (0x1FFF8000 + HC32_SRAM_SIZE * 1024)
#ifdef __ARMCC_VERSION
extern int Image$$RW_IRAM2$$ZI$$Limit;
#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit)
#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit)
#elif __ICCARM__
#pragma section="HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#pragma section = "HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#else
extern int __bss_end;
#define HEAP_BEGIN (&__bss_end)
#define HEAP_BEGIN (&__bss_end)
#endif
#define HEAP_END HC32_SRAM_END
#define HEAP_END HC32_SRAM_END
void PeripheralRegister_Unlock(void);
void PeripheralClock_Config(void);

20
bsp/hc32/ev_hc32f448_lqfp80/board/board_config.c
View File

@ -184,7 +184,7 @@ rt_err_t rt_hw_board_mcan_init(CM_MCAN_TypeDef *MCANx)
}
#endif
#if defined (RT_USING_SPI)
#if defined(RT_USING_SPI)
rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx)
{
rt_err_t result = RT_EOK;
@ -198,17 +198,17 @@ rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx)
case (rt_uint32_t)CM_SPI1:
GPIO_StructInit(&stcGpioInit);
stcGpioInit.u16PinState = PIN_STAT_SET;
stcGpioInit.u16PinDir = PIN_DIR_OUT;
stcGpioInit.u16PinDir = PIN_DIR_OUT;
GPIO_Init(SPI1_WP_PORT, SPI1_WP_PIN, &stcGpioInit);
GPIO_Init(SPI1_HOLD_PORT, SPI1_HOLD_PIN, &stcGpioInit);
(void)GPIO_StructInit(&stcGpioInit);
stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS;
(void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit);
(void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit);
(void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit);
(void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit);
GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC);
GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC);
GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC);
GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC);
break;
@ -332,19 +332,19 @@ rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x)
#endif
#endif
#if defined (BSP_USING_INPUT_CAPTURE)
#if defined(BSP_USING_INPUT_CAPTURE)
rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance)
{
rt_err_t result = RT_EOK;
switch ((rt_uint32_t)tmr_instance)
{
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1)
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1)
case (rt_uint32_t)CM_TMR6_1:
GPIO_SetFunc(INPUT_CAPTURE_TMR6_1_PORT, INPUT_CAPTURE_TMR6_1_PIN, INPUT_CAPTURE_TMR6_1_FUNC);
break;
#endif
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2)
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2)
case (rt_uint32_t)CM_TMR6_2:
GPIO_SetFunc(INPUT_CAPTURE_TMR6_2_PORT, INPUT_CAPTURE_TMR6_2_PIN, INPUT_CAPTURE_TMR6_2_FUNC);
break;
@ -358,7 +358,7 @@ rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance)
#endif
#ifdef RT_USING_PM
#define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS)
#define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS)
void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode)
{
switch (run_mode)
@ -385,8 +385,8 @@ rt_err_t rt_hw_qspi_board_init(void)
(void)GPIO_StructInit(&stcGpioInit);
stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
#ifndef BSP_QSPI_USING_SOFT_CS
(void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit);
GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC);
(void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit);
GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC);
#endif
(void)GPIO_Init(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, &stcGpioInit);
(void)GPIO_Init(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, &stcGpioInit);

426
bsp/hc32/ev_hc32f448_lqfp80/board/board_config.h
View File

@ -19,304 +19,304 @@
/************************* XTAL port **********************/
#define XTAL_PORT (GPIO_PORT_H)
#define XTAL_IN_PIN (GPIO_PIN_00)
#define XTAL_OUT_PIN (GPIO_PIN_01)
#define XTAL_PORT (GPIO_PORT_H)
#define XTAL_IN_PIN (GPIO_PIN_00)
#define XTAL_OUT_PIN (GPIO_PIN_01)
/************************ USART port **********************/
#if defined(BSP_USING_UART1)
#define USART1_RX_PORT (GPIO_PORT_A)
#define USART1_RX_PIN (GPIO_PIN_10)
#define USART1_RX_FUNC (GPIO_FUNC_33)
#define USART1_RX_PORT (GPIO_PORT_A)
#define USART1_RX_PIN (GPIO_PIN_10)
#define USART1_RX_FUNC (GPIO_FUNC_33)
#define USART1_TX_PORT (GPIO_PORT_A)
#define USART1_TX_PIN (GPIO_PIN_09)
#define USART1_TX_FUNC (GPIO_FUNC_32)
#define USART1_TX_PORT (GPIO_PORT_A)
#define USART1_TX_PIN (GPIO_PIN_09)
#define USART1_TX_FUNC (GPIO_FUNC_32)
#endif
#if defined(BSP_USING_UART2)
#define USART2_RX_PORT (GPIO_PORT_C)
#define USART2_RX_PIN (GPIO_PIN_11)
#define USART2_RX_FUNC (GPIO_FUNC_37)
#define USART2_RX_PORT (GPIO_PORT_C)
#define USART2_RX_PIN (GPIO_PIN_11)
#define USART2_RX_FUNC (GPIO_FUNC_37)
#define USART2_TX_PORT (GPIO_PORT_C)
#define USART2_TX_PIN (GPIO_PIN_10)
#define USART2_TX_FUNC (GPIO_FUNC_36)
#define USART2_TX_PORT (GPIO_PORT_C)
#define USART2_TX_PIN (GPIO_PIN_10)
#define USART2_TX_FUNC (GPIO_FUNC_36)
#endif
#if defined(BSP_USING_UART6)
#define USART6_RX_PORT (GPIO_PORT_D)
#define USART6_RX_PIN (GPIO_PIN_01)
#define USART6_RX_FUNC (GPIO_FUNC_55)
#define USART6_RX_PORT (GPIO_PORT_D)
#define USART6_RX_PIN (GPIO_PIN_01)
#define USART6_RX_FUNC (GPIO_FUNC_55)
#define USART6_TX_PORT (GPIO_PORT_D)
#define USART6_TX_PIN (GPIO_PIN_02)
#define USART6_TX_FUNC (GPIO_FUNC_54)
#define USART6_TX_PORT (GPIO_PORT_D)
#define USART6_TX_PIN (GPIO_PIN_02)
#define USART6_TX_FUNC (GPIO_FUNC_54)
#endif
/************************ I2C port **********************/
#if defined(BSP_USING_I2C1)
#define I2C1_SDA_PORT (GPIO_PORT_E)
#define I2C1_SDA_PIN (GPIO_PIN_00)
#define I2C1_SDA_FUNC (GPIO_FUNC_48)
#define I2C1_SDA_PORT (GPIO_PORT_E)
#define I2C1_SDA_PIN (GPIO_PIN_00)
#define I2C1_SDA_FUNC (GPIO_FUNC_48)
#define I2C1_SCL_PORT (GPIO_PORT_E)
#define I2C1_SCL_PIN (GPIO_PIN_01)
#define I2C1_SCL_FUNC (GPIO_FUNC_49)
#define I2C1_SCL_PORT (GPIO_PORT_E)
#define I2C1_SCL_PIN (GPIO_PIN_01)
#define I2C1_SCL_FUNC (GPIO_FUNC_49)
#endif
#if defined(BSP_USING_I2C2) // TODO, ch2 for test only
#define I2C2_SDA_PORT (GPIO_PORT_A)
#define I2C2_SDA_PIN (GPIO_PIN_09)
#define I2C2_SDA_FUNC (GPIO_FUNC_50)
#define I2C2_SDA_PORT (GPIO_PORT_A)
#define I2C2_SDA_PIN (GPIO_PIN_09)
#define I2C2_SDA_FUNC (GPIO_FUNC_50)
#define I2C2_SCL_PORT (GPIO_PORT_A)
#define I2C2_SCL_PIN (GPIO_PIN_10)
#define I2C2_SCL_FUNC (GPIO_FUNC_51)
#define I2C2_SCL_PORT (GPIO_PORT_A)
#define I2C2_SCL_PIN (GPIO_PIN_10)
#define I2C2_SCL_FUNC (GPIO_FUNC_51)
#endif
/*********** ADC configure *********/
#if defined(BSP_USING_ADC1)
#define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC12_IN10 */
#define ADC1_CH_PIN (GPIO_PIN_00)
#define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC12_IN10 */
#define ADC1_CH_PIN (GPIO_PIN_00)
#endif
#if defined(BSP_USING_ADC2)
#define ADC2_CH_PORT (GPIO_PORT_A) /* Default ADC12_IN4 */
#define ADC2_CH_PIN (GPIO_PIN_04)
#define ADC2_CH_PORT (GPIO_PORT_A) /* Default ADC12_IN4 */
#define ADC2_CH_PIN (GPIO_PIN_04)
#endif
#if defined(BSP_USING_ADC3)
#define ADC3_CH_PORT (GPIO_PORT_E) /* Default ADC3_IN1 */
#define ADC3_CH_PIN (GPIO_PIN_03)
#define ADC3_CH_PORT (GPIO_PORT_E) /* Default ADC3_IN1 */
#define ADC3_CH_PIN (GPIO_PIN_03)
#endif
/*********** DAC configure *********/
#if defined(BSP_USING_DAC1)
#define DAC1_CH1_PORT (GPIO_PORT_A)
#define DAC1_CH1_PIN (GPIO_PIN_04)
#define DAC1_CH2_PORT (GPIO_PORT_A)
#define DAC1_CH2_PIN (GPIO_PIN_05)
#define DAC1_CH1_PORT (GPIO_PORT_A)
#define DAC1_CH1_PIN (GPIO_PIN_04)
#define DAC1_CH2_PORT (GPIO_PORT_A)
#define DAC1_CH2_PIN (GPIO_PIN_05)
#endif
/*********** CAN configure *********/
#if defined(BSP_USING_MCAN1)
#define MCAN1_TX_PORT (GPIO_PORT_C)
#define MCAN1_TX_PIN (GPIO_PIN_12)
#define MCAN1_TX_PIN_FUNC (GPIO_FUNC_56)
#define MCAN1_TX_PORT (GPIO_PORT_C)
#define MCAN1_TX_PIN (GPIO_PIN_12)
#define MCAN1_TX_PIN_FUNC (GPIO_FUNC_56)
#define MCAN1_RX_PORT (GPIO_PORT_D)
#define MCAN1_RX_PIN (GPIO_PIN_00)
#define MCAN1_RX_PIN_FUNC (GPIO_FUNC_57)
#define MCAN1_RX_PORT (GPIO_PORT_D)
#define MCAN1_RX_PIN (GPIO_PIN_00)
#define MCAN1_RX_PIN_FUNC (GPIO_FUNC_57)
#endif
#if defined(BSP_USING_MCAN2)
#define MCAN2_TX_PORT (GPIO_PORT_H)
#define MCAN2_TX_PIN (GPIO_PIN_02)
#define MCAN2_TX_PIN_FUNC (GPIO_FUNC_56)
#define MCAN2_TX_PORT (GPIO_PORT_H)
#define MCAN2_TX_PIN (GPIO_PIN_02)
#define MCAN2_TX_PIN_FUNC (GPIO_FUNC_56)
#define MCAN2_RX_PORT (GPIO_PORT_E)
#define MCAN2_RX_PIN (GPIO_PIN_04)
#define MCAN2_RX_PIN_FUNC (GPIO_FUNC_57)
#define MCAN2_RX_PORT (GPIO_PORT_E)
#define MCAN2_RX_PIN (GPIO_PIN_04)
#define MCAN2_RX_PIN_FUNC (GPIO_FUNC_57)
#endif
/************************* SPI port ***********************/
#if defined(BSP_USING_SPI1)
#define SPI1_CS_PORT (GPIO_PORT_C)
#define SPI1_CS_PIN (GPIO_PIN_07)
#define SPI1_CS_PORT (GPIO_PORT_C)
#define SPI1_CS_PIN (GPIO_PIN_07)
#define SPI1_SCK_PORT (GPIO_PORT_B)
#define SPI1_SCK_PIN (GPIO_PIN_14)
#define SPI1_SCK_FUNC (GPIO_FUNC_47)
#define SPI1_SCK_PORT (GPIO_PORT_B)
#define SPI1_SCK_PIN (GPIO_PIN_14)
#define SPI1_SCK_FUNC (GPIO_FUNC_47)
#define SPI1_MOSI_PORT (GPIO_PORT_B)
#define SPI1_MOSI_PIN (GPIO_PIN_13)
#define SPI1_MOSI_FUNC (GPIO_FUNC_44)
#define SPI1_MOSI_PORT (GPIO_PORT_B)
#define SPI1_MOSI_PIN (GPIO_PIN_13)
#define SPI1_MOSI_FUNC (GPIO_FUNC_44)
#define SPI1_MISO_PORT (GPIO_PORT_D)
#define SPI1_MISO_PIN (GPIO_PIN_09)
#define SPI1_MISO_FUNC (GPIO_FUNC_45)
#define SPI1_MISO_PORT (GPIO_PORT_D)
#define SPI1_MISO_PIN (GPIO_PIN_09)
#define SPI1_MISO_FUNC (GPIO_FUNC_45)
#define SPI1_WP_PORT (GPIO_PORT_D)
#define SPI1_WP_PIN (GPIO_PIN_10)
#define SPI1_WP_PORT (GPIO_PORT_D)
#define SPI1_WP_PIN (GPIO_PIN_10)
#define SPI1_HOLD_PORT (GPIO_PORT_D)
#define SPI1_HOLD_PIN (GPIO_PIN_11)
#define SPI1_HOLD_PORT (GPIO_PORT_D)
#define SPI1_HOLD_PIN (GPIO_PIN_11)
#endif
/************************ RTC/PM *****************************/
#if defined(BSP_USING_RTC) || defined(RT_USING_PM)
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
#define XTAL32_PORT (GPIO_PORT_C)
#define XTAL32_IN_PIN (GPIO_PIN_14)
#define XTAL32_OUT_PIN (GPIO_PIN_15)
#endif
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
#define XTAL32_PORT (GPIO_PORT_C)
#define XTAL32_IN_PIN (GPIO_PIN_14)
#define XTAL32_OUT_PIN (GPIO_PIN_15)
#endif
#endif
#if defined(RT_USING_PWM)
/*********** PWM_TMRA configure *********/
#if defined(BSP_USING_PWM_TMRA_1)
#if defined(BSP_USING_PWM_TMRA_1_CH1)
#define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08)
#define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4)
#endif
#if defined(BSP_USING_PWM_TMRA_1_CH2)
#define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09)
#define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4)
#endif
#if defined(BSP_USING_PWM_TMRA_1_CH3)
#define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10)
#define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4)
#endif
#if defined(BSP_USING_PWM_TMRA_1_CH4)
#define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11)
#define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4)
#endif
#endif
#if defined(BSP_USING_PWM_TMRA_1)
#if defined(BSP_USING_PWM_TMRA_1_CH1)
#define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08)
#define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4)
#endif
#if defined(BSP_USING_PWM_TMRA_1_CH2)
#define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09)
#define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4)
#endif
#if defined(BSP_USING_PWM_TMRA_1_CH3)
#define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10)
#define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4)
#endif
#if defined(BSP_USING_PWM_TMRA_1_CH4)
#define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11)
#define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4)
#endif
#endif
#if defined(BSP_USING_PWM_TMRA_2)
#if defined(BSP_USING_PWM_TMRA_2_CH1)
#define PWM_TMRA_2_CH1_PORT (GPIO_PORT_A)
#define PWM_TMRA_2_CH1_PIN (GPIO_PIN_00)
#define PWM_TMRA_2_CH1_PIN_FUNC (GPIO_FUNC_4)
#endif
#if defined(BSP_USING_PWM_TMRA_2_CH2)
#define PWM_TMRA_2_CH2_PORT (GPIO_PORT_A)
#define PWM_TMRA_2_CH2_PIN (GPIO_PIN_01)
#define PWM_TMRA_2_CH2_PIN_FUNC (GPIO_FUNC_4)
#endif
#if defined(BSP_USING_PWM_TMRA_2_CH3)
#define PWM_TMRA_2_CH3_PORT (GPIO_PORT_A)
#define PWM_TMRA_2_CH3_PIN (GPIO_PIN_02)
#define PWM_TMRA_2_CH3_PIN_FUNC (GPIO_FUNC_4)
#endif
#if defined(BSP_USING_PWM_TMRA_2_CH4)
#define PWM_TMRA_2_CH4_PORT (GPIO_PORT_A)
#define PWM_TMRA_2_CH4_PIN (GPIO_PIN_03)
#define PWM_TMRA_2_CH4_PIN_FUNC (GPIO_FUNC_4)
#endif
#endif
#if defined(BSP_USING_PWM_TMRA_2)
#if defined(BSP_USING_PWM_TMRA_2_CH1)
#define PWM_TMRA_2_CH1_PORT (GPIO_PORT_A)
#define PWM_TMRA_2_CH1_PIN (GPIO_PIN_00)
#define PWM_TMRA_2_CH1_PIN_FUNC (GPIO_FUNC_4)
#endif
#if defined(BSP_USING_PWM_TMRA_2_CH2)
#define PWM_TMRA_2_CH2_PORT (GPIO_PORT_A)
#define PWM_TMRA_2_CH2_PIN (GPIO_PIN_01)
#define PWM_TMRA_2_CH2_PIN_FUNC (GPIO_FUNC_4)
#endif
#if defined(BSP_USING_PWM_TMRA_2_CH3)
#define PWM_TMRA_2_CH3_PORT (GPIO_PORT_A)
#define PWM_TMRA_2_CH3_PIN (GPIO_PIN_02)
#define PWM_TMRA_2_CH3_PIN_FUNC (GPIO_FUNC_4)
#endif
#if defined(BSP_USING_PWM_TMRA_2_CH4)
#define PWM_TMRA_2_CH4_PORT (GPIO_PORT_A)
#define PWM_TMRA_2_CH4_PIN (GPIO_PIN_03)
#define PWM_TMRA_2_CH4_PIN_FUNC (GPIO_FUNC_4)
#endif
#endif
/*********** PWM_TMR4 configure *********/
#if defined(BSP_USING_PWM_TMR4_1)
#if defined(BSP_USING_PWM_TMR4_1_OUH)
#define PWM_TMR4_1_OUH_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OUH_PIN (GPIO_PIN_08)
#define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OUL)
#define PWM_TMR4_1_OUL_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OUL_PIN (GPIO_PIN_07)
#define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OVH)
#define PWM_TMR4_1_OVH_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OVH_PIN (GPIO_PIN_09)
#define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OVL)
#define PWM_TMR4_1_OVL_PORT (GPIO_PORT_B)
#define PWM_TMR4_1_OVL_PIN (GPIO_PIN_00)
#define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OWH)
#define PWM_TMR4_1_OWH_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OWH_PIN (GPIO_PIN_10)
#define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OWL)
#define PWM_TMR4_1_OWL_PORT (GPIO_PORT_B)
#define PWM_TMR4_1_OWL_PIN (GPIO_PIN_01)
#define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2)
#endif
#endif
#if defined(BSP_USING_PWM_TMR4_1)
#if defined(BSP_USING_PWM_TMR4_1_OUH)
#define PWM_TMR4_1_OUH_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OUH_PIN (GPIO_PIN_08)
#define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OUL)
#define PWM_TMR4_1_OUL_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OUL_PIN (GPIO_PIN_07)
#define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OVH)
#define PWM_TMR4_1_OVH_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OVH_PIN (GPIO_PIN_09)
#define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OVL)
#define PWM_TMR4_1_OVL_PORT (GPIO_PORT_B)
#define PWM_TMR4_1_OVL_PIN (GPIO_PIN_00)
#define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OWH)
#define PWM_TMR4_1_OWH_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OWH_PIN (GPIO_PIN_10)
#define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OWL)
#define PWM_TMR4_1_OWL_PORT (GPIO_PORT_B)
#define PWM_TMR4_1_OWL_PIN (GPIO_PIN_01)
#define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2)
#endif
#endif
/*********** PWM_TMR6 configure *********/
#if defined(BSP_USING_PWM_TMR6_1)
#if defined(BSP_USING_PWM_TMR6_1_A)
#define PWM_TMR6_1_A_PORT (GPIO_PORT_A)
#define PWM_TMR6_1_A_PIN (GPIO_PIN_08)
#define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3)
#endif
#if defined(BSP_USING_PWM_TMR6_1_B)
#define PWM_TMR6_1_B_PORT (GPIO_PORT_A)
#define PWM_TMR6_1_B_PIN (GPIO_PIN_07)
#define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3)
#endif
#endif
#if defined(BSP_USING_PWM_TMR6_1)
#if defined(BSP_USING_PWM_TMR6_1_A)
#define PWM_TMR6_1_A_PORT (GPIO_PORT_A)
#define PWM_TMR6_1_A_PIN (GPIO_PIN_08)
#define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3)
#endif
#if defined(BSP_USING_PWM_TMR6_1_B)
#define PWM_TMR6_1_B_PORT (GPIO_PORT_A)
#define PWM_TMR6_1_B_PIN (GPIO_PIN_07)
#define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3)
#endif
#endif
#endif
#if defined(BSP_USING_INPUT_CAPTURE)
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1)
#define INPUT_CAPTURE_TMR6_1_FUNC (GPIO_FUNC_3)
#define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_A)
#define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_08)
#endif
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2)
#define INPUT_CAPTURE_TMR6_2_FUNC (GPIO_FUNC_3)
#define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_B)
#define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_02)
#endif
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1)
#define INPUT_CAPTURE_TMR6_1_FUNC (GPIO_FUNC_3)
#define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_A)
#define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_08)
#endif
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2)
#define INPUT_CAPTURE_TMR6_2_FUNC (GPIO_FUNC_3)
#define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_B)
#define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_02)
#endif
#endif
#if defined(BSP_USING_QSPI)
#ifndef BSP_QSPI_USING_SOFT_CS
#ifndef BSP_QSPI_USING_SOFT_CS
/* QSSN */
#define QSPI_FLASH_CS_PORT (GPIO_PORT_C)
#define QSPI_FLASH_CS_PIN (GPIO_PIN_07)
#define QSPI_FLASH_CS_FUNC (GPIO_FUNC_7)
#endif
#define QSPI_FLASH_CS_PORT (GPIO_PORT_C)
#define QSPI_FLASH_CS_PIN (GPIO_PIN_07)
#define QSPI_FLASH_CS_FUNC (GPIO_FUNC_7)
#endif
/* QSCK */
#define QSPI_FLASH_SCK_PORT (GPIO_PORT_B)
#define QSPI_FLASH_SCK_PIN (GPIO_PIN_14)
#define QSPI_FLASH_SCK_FUNC (GPIO_FUNC_7)
#define QSPI_FLASH_SCK_PORT (GPIO_PORT_B)
#define QSPI_FLASH_SCK_PIN (GPIO_PIN_14)
#define QSPI_FLASH_SCK_FUNC (GPIO_FUNC_7)
/* QSIO0 */
#define QSPI_FLASH_IO0_PORT (GPIO_PORT_B)
#define QSPI_FLASH_IO0_PIN (GPIO_PIN_13)
#define QSPI_FLASH_IO0_FUNC (GPIO_FUNC_7)
#define QSPI_FLASH_IO0_PORT (GPIO_PORT_B)
#define QSPI_FLASH_IO0_PIN (GPIO_PIN_13)
#define QSPI_FLASH_IO0_FUNC (GPIO_FUNC_7)
/* QSIO1 */
#define QSPI_FLASH_IO1_PORT (GPIO_PORT_D)
#define QSPI_FLASH_IO1_PIN (GPIO_PIN_09)
#define QSPI_FLASH_IO1_FUNC (GPIO_FUNC_7)
#define QSPI_FLASH_IO1_PORT (GPIO_PORT_D)
#define QSPI_FLASH_IO1_PIN (GPIO_PIN_09)
#define QSPI_FLASH_IO1_FUNC (GPIO_FUNC_7)
/* QSIO2 */
#define QSPI_FLASH_IO2_PORT (GPIO_PORT_D)
#define QSPI_FLASH_IO2_PIN (GPIO_PIN_10)
#define QSPI_FLASH_IO2_FUNC (GPIO_FUNC_7)
#define QSPI_FLASH_IO2_PORT (GPIO_PORT_D)
#define QSPI_FLASH_IO2_PIN (GPIO_PIN_10)
#define QSPI_FLASH_IO2_FUNC (GPIO_FUNC_7)
/* QSIO3 */
#define QSPI_FLASH_IO3_PORT (GPIO_PORT_D)
#define QSPI_FLASH_IO3_PIN (GPIO_PIN_11)
#define QSPI_FLASH_IO3_FUNC (GPIO_FUNC_7)
#define QSPI_FLASH_IO3_PORT (GPIO_PORT_D)
#define QSPI_FLASH_IO3_PIN (GPIO_PIN_11)
#define QSPI_FLASH_IO3_FUNC (GPIO_FUNC_7)
#endif
/*********** TMRA_PULSE_ENCODER configure *********/
#if defined(RT_USING_PULSE_ENCODER)
#if defined(BSP_USING_TMRA_PULSE_ENCODER)
#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
#define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A)
#define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08)
#define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4)
#define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A)
#define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09)
#define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4)
#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
#endif /* BSP_USING_TMRA_PULSE_ENCODER */
#if defined(BSP_USING_TMRA_PULSE_ENCODER)
#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
#define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A)
#define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08)
#define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4)
#define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A)
#define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09)
#define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4)
#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
#endif /* BSP_USING_TMRA_PULSE_ENCODER */
#if defined(BSP_USING_TMR6_PULSE_ENCODER)
#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
#define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B)
#define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_05)
#define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3)
#define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B)
#define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_13)
#define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3)
#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
#endif /* BSP_USING_TMR6_PULSE_ENCODER */
#if defined(BSP_USING_TMR6_PULSE_ENCODER)
#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
#define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B)
#define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_05)
#define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3)
#define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B)
#define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_13)
#define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3)
#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
#endif /* BSP_USING_TMR6_PULSE_ENCODER */
#endif /* RT_USING_PULSE_ENCODER */
#endif

189
bsp/hc32/ev_hc32f448_lqfp80/board/config/adc_config.h
View File

@ -20,42 +20,41 @@ extern "C" {
#ifdef BSP_USING_ADC1
#ifndef ADC1_INIT_PARAMS
#define ADC1_INIT_PARAMS \
{ \
.name = "adc1", \
.vref = 3300, \
.resolution = ADC_RESOLUTION_12BIT, \
.data_align = ADC_DATAALIGN_RIGHT, \
.eoc_poll_time_max = 100, \
.hard_trig_enable = RT_FALSE, \
.hard_trig_src = ADC_HARDTRIG_EVT0, \
.internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
.internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_MAX, \
.continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \
#define ADC1_INIT_PARAMS \
{ \
.name = "adc1", \
.vref = 3300, \
.resolution = ADC_RESOLUTION_12BIT, \
.data_align = ADC_DATAALIGN_RIGHT, \
.eoc_poll_time_max = 100, \
.hard_trig_enable = RT_FALSE, \
.hard_trig_src = ADC_HARDTRIG_EVT0, \
.internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
.internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_MAX, \
.continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \
}
#endif /* ADC1_INIT_PARAMS */
#if defined (BSP_ADC1_USING_DMA)
#if defined(BSP_ADC1_USING_DMA)
#ifndef ADC1_EOCA_DMA_CONFIG
#define ADC1_EOCA_DMA_CONFIG \
{ \
.Instance = ADC1_EOCA_DMA_INSTANCE, \
.channel = ADC1_EOCA_DMA_CHANNEL, \
.clock = ADC1_EOCA_DMA_CLOCK, \
.trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_ADC1_EOCA, \
.flag = ADC1_EOCA_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = ADC1_EOCA_DMA_IRQn, \
.irq_prio = ADC1_EOCA_DMA_INT_PRIO, \
.int_src = ADC1_EOCA_DMA_INT_SRC, \
}, \
#define ADC1_EOCA_DMA_CONFIG \
{ \
.Instance = ADC1_EOCA_DMA_INSTANCE, \
.channel = ADC1_EOCA_DMA_CHANNEL, \
.clock = ADC1_EOCA_DMA_CLOCK, \
.trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_ADC1_EOCA, \
.flag = ADC1_EOCA_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = ADC1_EOCA_DMA_IRQn, \
.irq_prio = ADC1_EOCA_DMA_INT_PRIO, \
.int_src = ADC1_EOCA_DMA_INT_SRC, \
}, \
}
#endif /* ADC1_EOCA_DMA_CONFIG */
#endif /* BSP_ADC1_USING_DMA */
@ -63,42 +62,41 @@ extern "C" {
#ifdef BSP_USING_ADC2
#ifndef ADC2_INIT_PARAMS
#define ADC2_INIT_PARAMS \
{ \
.name = "adc2", \
.vref = 3300, \
.resolution = ADC_RESOLUTION_12BIT, \
.data_align = ADC_DATAALIGN_RIGHT, \
.eoc_poll_time_max = 100, \
.hard_trig_enable = RT_FALSE, \
.hard_trig_src = ADC_HARDTRIG_EVT0, \
.internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
.internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_MAX, \
.continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \
#define ADC2_INIT_PARAMS \
{ \
.name = "adc2", \
.vref = 3300, \
.resolution = ADC_RESOLUTION_12BIT, \
.data_align = ADC_DATAALIGN_RIGHT, \
.eoc_poll_time_max = 100, \
.hard_trig_enable = RT_FALSE, \
.hard_trig_src = ADC_HARDTRIG_EVT0, \
.internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
.internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_MAX, \
.continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \
}
#endif /* ADC2_INIT_PARAMS */
#if defined (BSP_ADC2_USING_DMA)
#if defined(BSP_ADC2_USING_DMA)
#ifndef ADC2_EOCA_DMA_CONFIG
#define ADC2_EOCA_DMA_CONFIG \
{ \
.Instance = ADC2_EOCA_DMA_INSTANCE, \
.channel = ADC2_EOCA_DMA_CHANNEL, \
.clock = ADC2_EOCA_DMA_CLOCK, \
.trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_ADC2_EOCA, \
.flag = ADC2_EOCA_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = ADC2_EOCA_DMA_IRQn, \
.irq_prio = ADC2_EOCA_DMA_INT_PRIO, \
.int_src = ADC2_EOCA_DMA_INT_SRC, \
}, \
#define ADC2_EOCA_DMA_CONFIG \
{ \
.Instance = ADC2_EOCA_DMA_INSTANCE, \
.channel = ADC2_EOCA_DMA_CHANNEL, \
.clock = ADC2_EOCA_DMA_CLOCK, \
.trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_ADC2_EOCA, \
.flag = ADC2_EOCA_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = ADC2_EOCA_DMA_IRQn, \
.irq_prio = ADC2_EOCA_DMA_INT_PRIO, \
.int_src = ADC2_EOCA_DMA_INT_SRC, \
}, \
}
#endif /* ADC2_EOCA_DMA_CONFIG */
#endif /* BSP_ADC2_USING_DMA */
@ -106,42 +104,41 @@ extern "C" {
#ifdef BSP_USING_ADC3
#ifndef ADC3_INIT_PARAMS
#define ADC3_INIT_PARAMS \
{ \
.name = "adc3", \
.vref = 3300, \
.resolution = ADC_RESOLUTION_12BIT, \
.data_align = ADC_DATAALIGN_RIGHT, \
.eoc_poll_time_max = 100, \
.hard_trig_enable = RT_FALSE, \
.hard_trig_src = ADC_HARDTRIG_EVT0, \
.internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
.internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_MAX, \
.continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \
#define ADC3_INIT_PARAMS \
{ \
.name = "adc3", \
.vref = 3300, \
.resolution = ADC_RESOLUTION_12BIT, \
.data_align = ADC_DATAALIGN_RIGHT, \
.eoc_poll_time_max = 100, \
.hard_trig_enable = RT_FALSE, \
.hard_trig_src = ADC_HARDTRIG_EVT0, \
.internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
.internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_MAX, \
.continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \
}
#endif /* ADC3_INIT_PARAMS */
#if defined (BSP_ADC3_USING_DMA)
#if defined(BSP_ADC3_USING_DMA)
#ifndef ADC3_EOCA_DMA_CONFIG
#define ADC3_EOCA_DMA_CONFIG \
{ \
.Instance = ADC3_EOCA_DMA_INSTANCE, \
.channel = ADC3_EOCA_DMA_CHANNEL, \
.clock = ADC3_EOCA_DMA_CLOCK, \
.trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_ADC3_EOCA, \
.flag = ADC3_EOCA_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = ADC3_EOCA_DMA_IRQn, \
.irq_prio = ADC3_EOCA_DMA_INT_PRIO, \
.int_src = ADC3_EOCA_DMA_INT_SRC, \
}, \
#define ADC3_EOCA_DMA_CONFIG \
{ \
.Instance = ADC3_EOCA_DMA_INSTANCE, \
.channel = ADC3_EOCA_DMA_CHANNEL, \
.clock = ADC3_EOCA_DMA_CLOCK, \
.trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_ADC3_EOCA, \
.flag = ADC3_EOCA_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = ADC3_EOCA_DMA_IRQn, \
.irq_prio = ADC3_EOCA_DMA_INT_PRIO, \
.int_src = ADC3_EOCA_DMA_INT_SRC, \
}, \
}
#endif /* ADC3_EOCA_DMA_CONFIG */
#endif /* BSP_ADC3_USING_DMA */

24
bsp/hc32/ev_hc32f448_lqfp80/board/config/dac_config.h
View File

@ -19,18 +19,18 @@ extern "C" {
#ifdef BSP_USING_DAC1
#ifndef DAC1_INIT_PARAMS
#define DAC1_INIT_PARAMS \
{ \
.name = "dac1", \
.vref = 3300, \
.dac_adp_enable = RT_FALSE, \
.dac_adp_sel = DAC_ADP_SEL_ALL, \
.ch1_output_enable = RT_TRUE, \
.ch2_output_enable = RT_TRUE, \
.ch1_data_src = DAC_DATA_SRC_DATAREG, \
.ch2_data_src = DAC_DATA_SRC_DATAREG, \
.ch1_amp_enable = RT_TRUE, \
.ch2_amp_enable = RT_TRUE, \
#define DAC1_INIT_PARAMS \
{ \
.name = "dac1", \
.vref = 3300, \
.dac_adp_enable = RT_FALSE, \
.dac_adp_sel = DAC_ADP_SEL_ALL, \
.ch1_output_enable = RT_TRUE, \
.ch2_output_enable = RT_TRUE, \
.ch1_data_src = DAC_DATA_SRC_DATAREG, \
.ch2_data_src = DAC_DATA_SRC_DATAREG, \
.ch1_amp_enable = RT_TRUE, \
.ch2_amp_enable = RT_TRUE, \
}
#endif /* DAC1_INIT_PARAMS */
#endif /* BSP_USING_DAC1 */

352
bsp/hc32/ev_hc32f448_lqfp80/board/config/dma_config.h
View File

@ -21,248 +21,248 @@ extern "C" {
/* DMA1 ch0 */
#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
#define SPI1_RX_DMA_INSTANCE CM_DMA1
#define SPI1_RX_DMA_CHANNEL DMA_CH0
#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0
#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0
#define SPI1_RX_DMA_INSTANCE CM_DMA1
#define SPI1_RX_DMA_CHANNEL DMA_CH0
#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0
#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0
#elif defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
#define SPI3_RX_DMA_INSTANCE CM_DMA1
#define SPI3_RX_DMA_CHANNEL DMA_CH0
#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_0
#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define SPI3_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC0
#define SPI3_RX_DMA_INSTANCE CM_DMA1
#define SPI3_RX_DMA_CHANNEL DMA_CH0
#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_0
#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define SPI3_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC0
#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE)
#define I2C1_TX_DMA_INSTANCE CM_DMA1
#define I2C1_TX_DMA_CHANNEL DMA_CH0
#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0
#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0
#define I2C1_TX_DMA_INSTANCE CM_DMA1
#define I2C1_TX_DMA_CHANNEL DMA_CH0
#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0
#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0
#endif
/* DMA1 ch1 */
#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
#define SPI1_TX_DMA_INSTANCE CM_DMA1
#define SPI1_TX_DMA_CHANNEL DMA_CH1
#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1
#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1
#define SPI1_TX_DMA_INSTANCE CM_DMA1
#define SPI1_TX_DMA_CHANNEL DMA_CH1
#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1
#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1
#elif defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
#define SPI3_TX_DMA_INSTANCE CM_DMA1
#define SPI3_TX_DMA_CHANNEL DMA_CH1
#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_1
#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define SPI3_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC1
#define SPI3_TX_DMA_INSTANCE CM_DMA1
#define SPI3_TX_DMA_CHANNEL DMA_CH1
#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_1
#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define SPI3_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC1
#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE)
#define I2C1_RX_DMA_INSTANCE CM_DMA1
#define I2C1_RX_DMA_CHANNEL DMA_CH1
#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1
#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1
#define I2C1_RX_DMA_INSTANCE CM_DMA1
#define I2C1_RX_DMA_CHANNEL DMA_CH1
#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1
#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1
#endif
/* DMA1 ch2 */
#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
#define SPI2_RX_DMA_INSTANCE CM_DMA1
#define SPI2_RX_DMA_CHANNEL DMA_CH2
#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2
#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2
#define SPI2_RX_DMA_INSTANCE CM_DMA1
#define SPI2_RX_DMA_CHANNEL DMA_CH2
#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2
#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2
#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE)
#define I2C2_TX_DMA_INSTANCE CM_DMA1
#define I2C2_TX_DMA_CHANNEL DMA_CH2
#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2
#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2
#define I2C2_TX_DMA_INSTANCE CM_DMA1
#define I2C2_TX_DMA_CHANNEL DMA_CH2
#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2
#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2
#endif
/* DMA1 ch3 */
#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
#define SPI2_TX_DMA_INSTANCE CM_DMA1
#define SPI2_TX_DMA_CHANNEL DMA_CH3
#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3
#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3
#define SPI2_TX_DMA_INSTANCE CM_DMA1
#define SPI2_TX_DMA_CHANNEL DMA_CH3
#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3
#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3
#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE)
#define I2C2_RX_DMA_INSTANCE CM_DMA1
#define I2C2_RX_DMA_CHANNEL DMA_CH3
#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3
#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3
#define I2C2_RX_DMA_INSTANCE CM_DMA1
#define I2C2_RX_DMA_CHANNEL DMA_CH3
#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3
#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3
#elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE)
#define ADC1_EOCA_DMA_INSTANCE CM_DMA1
#define ADC1_EOCA_DMA_CHANNEL DMA_CH3
#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_3
#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC3
#define ADC1_EOCA_DMA_INSTANCE CM_DMA1
#define ADC1_EOCA_DMA_CHANNEL DMA_CH3
#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_3
#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC3
#endif
/* DMA1 ch4 */
#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
#define UART5_RX_DMA_INSTANCE CM_DMA1
#define UART5_RX_DMA_CHANNEL DMA_CH4
#define UART5_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define UART5_RX_DMA_TRIG_SELECT AOS_DMA1_4
#define UART5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
#define UART5_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
#define UART5_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
#define UART5_RX_DMA_INT_SRC INT_SRC_DMA1_TC4
#define UART5_RX_DMA_INSTANCE CM_DMA1
#define UART5_RX_DMA_CHANNEL DMA_CH4
#define UART5_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define UART5_RX_DMA_TRIG_SELECT AOS_DMA1_4
#define UART5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
#define UART5_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
#define UART5_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
#define UART5_RX_DMA_INT_SRC INT_SRC_DMA1_TC4
#elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE)
#define ADC2_EOCA_DMA_INSTANCE CM_DMA1
#define ADC2_EOCA_DMA_CHANNEL DMA_CH4
#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA1_4
#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC4
#define ADC2_EOCA_DMA_INSTANCE CM_DMA1
#define ADC2_EOCA_DMA_CHANNEL DMA_CH4
#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA1_4
#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC4
#endif
/* DMA1 ch5 */
#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
#define UART5_TX_DMA_INSTANCE CM_DMA1
#define UART5_TX_DMA_CHANNEL DMA_CH5
#define UART5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define UART5_TX_DMA_TRIG_SELECT AOS_DMA1_5
#define UART5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
#define UART5_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
#define UART5_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
#define UART5_TX_DMA_INT_SRC INT_SRC_DMA1_TC5
#define UART5_TX_DMA_INSTANCE CM_DMA1
#define UART5_TX_DMA_CHANNEL DMA_CH5
#define UART5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define UART5_TX_DMA_TRIG_SELECT AOS_DMA1_5
#define UART5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
#define UART5_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
#define UART5_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
#define UART5_TX_DMA_INT_SRC INT_SRC_DMA1_TC5
#elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE)
#define ADC3_EOCA_DMA_INSTANCE CM_DMA1
#define ADC3_EOCA_DMA_CHANNEL DMA_CH5
#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA1_5
#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC5
#define ADC3_EOCA_DMA_INSTANCE CM_DMA1
#define ADC3_EOCA_DMA_CHANNEL DMA_CH5
#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA1_5
#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC5
#endif
/* DMA2 ch0 */
#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
#define UART1_RX_DMA_INSTANCE CM_DMA2
#define UART1_RX_DMA_CHANNEL DMA_CH0
#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0
#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0
#define UART1_RX_DMA_INSTANCE CM_DMA2
#define UART1_RX_DMA_CHANNEL DMA_CH0
#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0
#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0
#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
#define QSPI_DMA_INSTANCE CM_DMA2
#define QSPI_DMA_CHANNEL DMA_CH0
#define QSPI_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define QSPI_DMA_TRIG_SELECT AOS_DMA2_0
#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define QSPI_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
#define QSPI_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
#define QSPI_DMA_INT_SRC INT_SRC_DMA2_TC0
#define QSPI_DMA_INSTANCE CM_DMA2
#define QSPI_DMA_CHANNEL DMA_CH0
#define QSPI_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define QSPI_DMA_TRIG_SELECT AOS_DMA2_0
#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define QSPI_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
#define QSPI_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
#define QSPI_DMA_INT_SRC INT_SRC_DMA2_TC0
#endif
/* DMA2 ch1 */
#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
#define UART1_TX_DMA_INSTANCE CM_DMA2
#define UART1_TX_DMA_CHANNEL DMA_CH1
#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1
#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM
#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO
#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1
#define UART1_TX_DMA_INSTANCE CM_DMA2
#define UART1_TX_DMA_CHANNEL DMA_CH1
#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1
#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM
#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO
#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1
#endif
/* DMA2 ch2 */
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
#define UART2_RX_DMA_INSTANCE CM_DMA2
#define UART2_RX_DMA_CHANNEL DMA_CH2
#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2
#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM
#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO
#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2
#define UART2_RX_DMA_INSTANCE CM_DMA2
#define UART2_RX_DMA_CHANNEL DMA_CH2
#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2
#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM
#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO
#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2
#endif
/* DMA2 ch3 */
#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
#define UART2_TX_DMA_INSTANCE CM_DMA2
#define UART2_TX_DMA_CHANNEL DMA_CH3
#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3
#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM
#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO
#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3
#define UART2_TX_DMA_INSTANCE CM_DMA2
#define UART2_TX_DMA_CHANNEL DMA_CH3
#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3
#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM
#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO
#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3
#endif
/* DMA2 ch4 */
#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
#define UART4_RX_DMA_INSTANCE CM_DMA2
#define UART4_RX_DMA_CHANNEL DMA_CH4
#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART4_RX_DMA_TRIG_SELECT AOS_DMA2_4
#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
#define UART4_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM
#define UART4_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO
#define UART4_RX_DMA_INT_SRC INT_SRC_DMA2_TC4
#define UART4_RX_DMA_INSTANCE CM_DMA2
#define UART4_RX_DMA_CHANNEL DMA_CH4
#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART4_RX_DMA_TRIG_SELECT AOS_DMA2_4
#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
#define UART4_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM
#define UART4_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO
#define UART4_RX_DMA_INT_SRC INT_SRC_DMA2_TC4
#endif
/* DMA2 ch5 */
#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
#define UART4_TX_DMA_INSTANCE CM_DMA2
#define UART4_TX_DMA_CHANNEL DMA_CH5
#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART4_TX_DMA_TRIG_SELECT AOS_DMA2_5
#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
#define UART4_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM
#define UART4_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO
#define UART4_TX_DMA_INT_SRC INT_SRC_DMA2_TC5
#define UART4_TX_DMA_INSTANCE CM_DMA2
#define UART4_TX_DMA_CHANNEL DMA_CH5
#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART4_TX_DMA_TRIG_SELECT AOS_DMA2_5
#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
#define UART4_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM
#define UART4_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO
#define UART4_TX_DMA_INT_SRC INT_SRC_DMA2_TC5
#endif
#ifdef __cplusplus

160
bsp/hc32/ev_hc32f448_lqfp80/board/config/gpio_config.h
View File

@ -23,146 +23,146 @@ extern "C" {
#if defined(RT_USING_PIN)
#ifndef EXTINT0_IRQ_CONFIG
#define EXTINT0_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT0_IRQ_NUM, \
.irq_prio = BSP_EXTINT0_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ0, \
#define EXTINT0_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT0_IRQ_NUM, \
.irq_prio = BSP_EXTINT0_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ0, \
}
#endif /* EXTINT1_IRQ_CONFIG */
#ifndef EXTINT1_IRQ_CONFIG
#define EXTINT1_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT1_IRQ_NUM, \
.irq_prio = BSP_EXTINT1_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ1, \
#define EXTINT1_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT1_IRQ_NUM, \
.irq_prio = BSP_EXTINT1_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ1, \
}
#endif /* EXTINT1_IRQ_CONFIG */
#ifndef EXTINT2_IRQ_CONFIG
#define EXTINT2_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT2_IRQ_NUM, \
.irq_prio = BSP_EXTINT2_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ2, \
#define EXTINT2_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT2_IRQ_NUM, \
.irq_prio = BSP_EXTINT2_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ2, \
}
#endif /* EXTINT2_IRQ_CONFIG */
#ifndef EXTINT3_IRQ_CONFIG
#define EXTINT3_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT3_IRQ_NUM, \
.irq_prio = BSP_EXTINT3_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ3, \
#define EXTINT3_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT3_IRQ_NUM, \
.irq_prio = BSP_EXTINT3_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ3, \
}
#endif /* EXTINT3_IRQ_CONFIG */
#ifndef EXTINT4_IRQ_CONFIG
#define EXTINT4_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT4_IRQ_NUM, \
.irq_prio = BSP_EXTINT4_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ4, \
#define EXTINT4_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT4_IRQ_NUM, \
.irq_prio = BSP_EXTINT4_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ4, \
}
#endif /* EXTINT4_IRQ_CONFIG */
#ifndef EXTINT5_IRQ_CONFIG
#define EXTINT5_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT5_IRQ_NUM, \
.irq_prio = BSP_EXTINT5_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ5, \
#define EXTINT5_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT5_IRQ_NUM, \
.irq_prio = BSP_EXTINT5_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ5, \
}
#endif /* EXTINT5_IRQ_CONFIG */
#ifndef EXTINT6_IRQ_CONFIG
#define EXTINT6_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT6_IRQ_NUM, \
.irq_prio = BSP_EXTINT6_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ6, \
#define EXTINT6_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT6_IRQ_NUM, \
.irq_prio = BSP_EXTINT6_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ6, \
}
#endif /* EXTINT6_IRQ_CONFIG */
#ifndef EXTINT7_IRQ_CONFIG
#define EXTINT7_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT7_IRQ_NUM, \
.irq_prio = BSP_EXTINT7_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ7, \
#define EXTINT7_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT7_IRQ_NUM, \
.irq_prio = BSP_EXTINT7_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ7, \
}
#endif /* EXTINT7_IRQ_CONFIG */
#ifndef EXTINT8_IRQ_CONFIG
#define EXTINT8_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT8_IRQ_NUM, \
.irq_prio = BSP_EXTINT8_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ8, \
#define EXTINT8_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT8_IRQ_NUM, \
.irq_prio = BSP_EXTINT8_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ8, \
}
#endif /* EXTINT8_IRQ_CONFIG */
#ifndef EXTINT9_IRQ_CONFIG
#define EXTINT9_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT9_IRQ_NUM, \
.irq_prio = BSP_EXTINT9_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ9, \
#define EXTINT9_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT9_IRQ_NUM, \
.irq_prio = BSP_EXTINT9_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ9, \
}
#endif /* EXTINT9_IRQ_CONFIG */
#ifndef EXTINT10_IRQ_CONFIG
#define EXTINT10_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT10_IRQ_NUM, \
.irq_prio = BSP_EXTINT10_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ10, \
#define EXTINT10_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT10_IRQ_NUM, \
.irq_prio = BSP_EXTINT10_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ10, \
}
#endif /* EXTINT10_IRQ_CONFIG */
#ifndef EXTINT11_IRQ_CONFIG
#define EXTINT11_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT11_IRQ_NUM, \
.irq_prio = BSP_EXTINT11_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ11, \
#define EXTINT11_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT11_IRQ_NUM, \
.irq_prio = BSP_EXTINT11_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ11, \
}
#endif /* EXTINT11_IRQ_CONFIG */
#ifndef EXTINT12_IRQ_CONFIG
#define EXTINT12_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT12_IRQ_NUM, \
.irq_prio = BSP_EXTINT12_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ12, \
#define EXTINT12_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT12_IRQ_NUM, \
.irq_prio = BSP_EXTINT12_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ12, \
}
#endif /* EXTINT12_IRQ_CONFIG */
#ifndef EXTINT13_IRQ_CONFIG
#define EXTINT13_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT13_IRQ_NUM, \
.irq_prio = BSP_EXTINT13_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ13, \
#define EXTINT13_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT13_IRQ_NUM, \
.irq_prio = BSP_EXTINT13_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ13, \
}
#endif /* EXTINT13_IRQ_CONFIG */
#ifndef EXTINT14_IRQ_CONFIG
#define EXTINT14_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT14_IRQ_NUM, \
.irq_prio = BSP_EXTINT14_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ14, \
#define EXTINT14_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT14_IRQ_NUM, \
.irq_prio = BSP_EXTINT14_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ14, \
}
#endif /* EXTINT14_IRQ_CONFIG */
#ifndef EXTINT15_IRQ_CONFIG
#define EXTINT15_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT15_IRQ_NUM, \
.irq_prio = BSP_EXTINT15_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ15, \
#define EXTINT15_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT15_IRQ_NUM, \
.irq_prio = BSP_EXTINT15_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ15, \
}
#endif /* EXTINT15_IRQ_CONFIG */

408
bsp/hc32/ev_hc32f448_lqfp80/board/config/i2c_config.h
View File

@ -21,101 +21,97 @@ extern "C" {
#if defined(BSP_USING_I2C1)
#ifndef I2C1_CONFIG
#define I2C1_CONFIG \
{ \
.name = "i2c1", \
.Instance = CM_I2C1, \
.clock = FCG1_PERIPH_I2C1, \
.baudrate = 100000UL, \
.timeout = 10000UL, \
#define I2C1_CONFIG \
{ \
.name = "i2c1", \
.Instance = CM_I2C1, \
.clock = FCG1_PERIPH_I2C1, \
.baudrate = 100000UL, \
.timeout = 10000UL, \
}
#endif /* I2C1_CONFIG */
#endif
#if defined(BSP_I2C1_USING_DMA)
#ifndef I2C1_TX_DMA_CONFIG
#define I2C1_TX_DMA_CONFIG \
{ \
.Instance = I2C1_TX_DMA_INSTANCE, \
.channel = I2C1_TX_DMA_CHANNEL, \
.clock = I2C1_TX_DMA_CLOCK, \
.trigger_select = I2C1_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C1_TEI, \
.flag = I2C1_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = I2C1_TX_DMA_IRQn, \
.irq_prio = I2C1_TX_DMA_INT_PRIO, \
.int_src = I2C1_TX_DMA_INT_SRC, \
}, \
#define I2C1_TX_DMA_CONFIG \
{ \
.Instance = I2C1_TX_DMA_INSTANCE, \
.channel = I2C1_TX_DMA_CHANNEL, \
.clock = I2C1_TX_DMA_CLOCK, \
.trigger_select = I2C1_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C1_TEI, \
.flag = I2C1_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = I2C1_TX_DMA_IRQn, \
.irq_prio = I2C1_TX_DMA_INT_PRIO, \
.int_src = I2C1_TX_DMA_INT_SRC, \
}, \
}
#endif /* I2C1_TX_DMA_CONFIG */
#ifndef I2C1_RX_DMA_CONFIG
#define I2C1_RX_DMA_CONFIG \
{ \
.Instance = I2C1_RX_DMA_INSTANCE, \
.channel = I2C1_RX_DMA_CHANNEL, \
.clock = I2C1_RX_DMA_CLOCK, \
.trigger_select = I2C1_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C1_RXI, \
.flag = I2C1_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = I2C1_RX_DMA_IRQn, \
.irq_prio = I2C1_RX_DMA_INT_PRIO, \
.int_src = I2C1_RX_DMA_INT_SRC, \
}, \
#define I2C1_RX_DMA_CONFIG \
{ \
.Instance = I2C1_RX_DMA_INSTANCE, \
.channel = I2C1_RX_DMA_CHANNEL, \
.clock = I2C1_RX_DMA_CLOCK, \
.trigger_select = I2C1_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C1_RXI, \
.flag = I2C1_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = I2C1_RX_DMA_IRQn, \
.irq_prio = I2C1_RX_DMA_INT_PRIO, \
.int_src = I2C1_RX_DMA_INT_SRC, \
}, \
}
#endif /* I2C1_RX_DMA_CONFIG */
#endif /* BSP_I2C1_USING_DMA */
#if defined(BSP_USING_I2C2)
#ifndef I2C2_CONFIG
#define I2C2_CONFIG \
{ \
.name = "i2c2", \
.Instance = CM_I2C2, \
.clock = FCG1_PERIPH_I2C2, \
.baudrate = 100000UL, \
.timeout = 10000UL, \
#define I2C2_CONFIG \
{ \
.name = "i2c2", \
.Instance = CM_I2C2, \
.clock = FCG1_PERIPH_I2C2, \
.baudrate = 100000UL, \
.timeout = 10000UL, \
}
#endif /* I2C2_CONFIG */
#if defined(BSP_I2C2_USING_DMA)
#ifndef I2C2_TX_DMA_CONFIG
#define I2C2_TX_DMA_CONFIG \
{ \
.Instance = I2C2_TX_DMA_INSTANCE, \
.channel = I2C2_TX_DMA_CHANNEL, \
.clock = I2C2_TX_DMA_CLOCK, \
.trigger_select = I2C2_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C2_TEI, \
.flag = I2C2_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = I2C2_TX_DMA_IRQn, \
.irq_prio = I2C2_TX_DMA_INT_PRIO, \
.int_src = I2C2_TX_DMA_INT_SRC, \
}, \
#define I2C2_TX_DMA_CONFIG \
{ \
.Instance = I2C2_TX_DMA_INSTANCE, \
.channel = I2C2_TX_DMA_CHANNEL, \
.clock = I2C2_TX_DMA_CLOCK, \
.trigger_select = I2C2_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C2_TEI, \
.flag = I2C2_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = I2C2_TX_DMA_IRQn, \
.irq_prio = I2C2_TX_DMA_INT_PRIO, \
.int_src = I2C2_TX_DMA_INT_SRC, \
}, \
}
#endif /* I2C2_TX_DMA_CONFIG */
#ifndef I2C2_RX_DMA_CONFIG
#define I2C2_RX_DMA_CONFIG \
{ \
.Instance = I2C2_RX_DMA_INSTANCE, \
.channel = I2C2_RX_DMA_CHANNEL, \
.clock = I2C2_RX_DMA_CLOCK, \
.trigger_select = I2C2_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C2_RXI, \
.flag = I2C2_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = I2C2_RX_DMA_IRQn, \
.irq_prio = I2C2_RX_DMA_INT_PRIO, \
.int_src = I2C2_RX_DMA_INT_SRC, \
}, \
#define I2C2_RX_DMA_CONFIG \
{ \
.Instance = I2C2_RX_DMA_INSTANCE, \
.channel = I2C2_RX_DMA_CHANNEL, \
.clock = I2C2_RX_DMA_CLOCK, \
.trigger_select = I2C2_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C2_RXI, \
.flag = I2C2_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = I2C2_RX_DMA_IRQn, \
.irq_prio = I2C2_RX_DMA_INT_PRIO, \
.int_src = I2C2_RX_DMA_INT_SRC, \
}, \
}
#endif /* I2C2_RX_DMA_CONFIG */
#endif /* BSP_I2C2_USING_DMA */
@ -123,50 +119,48 @@ extern "C" {
#if defined(BSP_USING_I2C3)
#ifndef I2C3_CONFIG
#define I2C3_CONFIG \
{ \
.name = "i2c3", \
.Instance = CM_I2C3, \
.clock = FCG1_PERIPH_I2C3, \
.baudrate = 100000UL, \
.timeout = 10000UL, \
#define I2C3_CONFIG \
{ \
.name = "i2c3", \
.Instance = CM_I2C3, \
.clock = FCG1_PERIPH_I2C3, \
.baudrate = 100000UL, \
.timeout = 10000UL, \
}
#endif /* I2C3_CONFIG */
#if defined(BSP_I2C3_USING_DMA)
#ifndef I2C3_TX_DMA_CONFIG
#define I2C3_TX_DMA_CONFIG \
{ \
.Instance = I2C3_TX_DMA_INSTANCE, \
.channel = I2C3_TX_DMA_CHANNEL, \
.clock = I2C3_TX_DMA_CLOCK, \
.trigger_select = I2C3_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C3_TEI, \
.flag = I2C3_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = I2C3_TX_DMA_IRQn, \
.irq_prio = I2C3_TX_DMA_INT_PRIO, \
.int_src = I2C3_TX_DMA_INT_SRC, \
}, \
#define I2C3_TX_DMA_CONFIG \
{ \
.Instance = I2C3_TX_DMA_INSTANCE, \
.channel = I2C3_TX_DMA_CHANNEL, \
.clock = I2C3_TX_DMA_CLOCK, \
.trigger_select = I2C3_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C3_TEI, \
.flag = I2C3_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = I2C3_TX_DMA_IRQn, \
.irq_prio = I2C3_TX_DMA_INT_PRIO, \
.int_src = I2C3_TX_DMA_INT_SRC, \
}, \
}
#endif /* I2C3_TX_DMA_CONFIG */
#ifndef I2C3_RX_DMA_CONFIG
#define I2C3_RX_DMA_CONFIG \
{ \
.Instance = I2C3_RX_DMA_INSTANCE, \
.channel = I2C3_RX_DMA_CHANNEL, \
.clock = I2C3_RX_DMA_CLOCK, \
.trigger_select = I2C3_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C3_RXI, \
.flag = I2C3_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = I2C3_RX_DMA_IRQn, \
.irq_prio = I2C3_RX_DMA_INT_PRIO, \
.int_src = I2C3_RX_DMA_INT_SRC, \
}, \
#define I2C3_RX_DMA_CONFIG \
{ \
.Instance = I2C3_RX_DMA_INSTANCE, \
.channel = I2C3_RX_DMA_CHANNEL, \
.clock = I2C3_RX_DMA_CLOCK, \
.trigger_select = I2C3_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C3_RXI, \
.flag = I2C3_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = I2C3_RX_DMA_IRQn, \
.irq_prio = I2C3_RX_DMA_INT_PRIO, \
.int_src = I2C3_RX_DMA_INT_SRC, \
}, \
}
#endif /* I2C3_RX_DMA_CONFIG */
#endif /* BSP_I2C3_USING_DMA */
@ -174,50 +168,48 @@ extern "C" {
#if defined(BSP_USING_I2C4)
#ifndef I2C4_CONFIG
#define I2C4_CONFIG \
{ \
.name = "i2c4", \
.Instance = CM_I2C4, \
.clock = FCG1_PERIPH_I2C4, \
.baudrate = 100000UL, \
.timeout = 10000UL, \
#define I2C4_CONFIG \
{ \
.name = "i2c4", \
.Instance = CM_I2C4, \
.clock = FCG1_PERIPH_I2C4, \
.baudrate = 100000UL, \
.timeout = 10000UL, \
}
#endif /* I2C4_CONFIG */
#if defined(BSP_I2C4_USING_DMA)
#ifndef I2C4_TX_DMA_CONFIG
#define I2C4_TX_DMA_CONFIG \
{ \
.Instance = I2C4_TX_DMA_INSTANCE, \
.channel = I2C4_TX_DMA_CHANNEL, \
.clock = I2C4_TX_DMA_CLOCK, \
.trigger_select = I2C4_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C4_TEI, \
.flag = I2C4_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = I2C4_TX_DMA_IRQn, \
.irq_prio = I2C4_TX_DMA_INT_PRIO, \
.int_src = I2C4_TX_DMA_INT_SRC, \
}, \
#define I2C4_TX_DMA_CONFIG \
{ \
.Instance = I2C4_TX_DMA_INSTANCE, \
.channel = I2C4_TX_DMA_CHANNEL, \
.clock = I2C4_TX_DMA_CLOCK, \
.trigger_select = I2C4_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C4_TEI, \
.flag = I2C4_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = I2C4_TX_DMA_IRQn, \
.irq_prio = I2C4_TX_DMA_INT_PRIO, \
.int_src = I2C4_TX_DMA_INT_SRC, \
}, \
}
#endif /* I2C4_TX_DMA_CONFIG */
#ifndef I2C4_RX_DMA_CONFIG
#define I2C4_RX_DMA_CONFIG \
{ \
.Instance = I2C4_RX_DMA_INSTANCE, \
.channel = I2C4_RX_DMA_CHANNEL, \
.clock = I2C4_RX_DMA_CLOCK, \
.trigger_select = I2C4_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C4_RXI, \
.flag = I2C4_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = I2C4_RX_DMA_IRQn, \
.irq_prio = I2C4_RX_DMA_INT_PRIO, \
.int_src = I2C4_RX_DMA_INT_SRC, \
}, \
#define I2C4_RX_DMA_CONFIG \
{ \
.Instance = I2C4_RX_DMA_INSTANCE, \
.channel = I2C4_RX_DMA_CHANNEL, \
.clock = I2C4_RX_DMA_CLOCK, \
.trigger_select = I2C4_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C4_RXI, \
.flag = I2C4_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = I2C4_RX_DMA_IRQn, \
.irq_prio = I2C4_RX_DMA_INT_PRIO, \
.int_src = I2C4_RX_DMA_INT_SRC, \
}, \
}
#endif /* I2C4_RX_DMA_CONFIG */
#endif /* BSP_I2C4_USING_DMA */
@ -225,50 +217,48 @@ extern "C" {
#if defined(BSP_USING_I2C5)
#ifndef I2C5_CONFIG
#define I2C5_CONFIG \
{ \
.name = "i2c5", \
.Instance = CM_I2C5, \
.clock = FCG1_PERIPH_I2C5, \
.baudrate = 100000UL, \
.timeout = 10000UL, \
#define I2C5_CONFIG \
{ \
.name = "i2c5", \
.Instance = CM_I2C5, \
.clock = FCG1_PERIPH_I2C5, \
.baudrate = 100000UL, \
.timeout = 10000UL, \
}
#endif /* I2C5_CONFIG */
#if defined(BSP_I2C5_USING_DMA)
#ifndef I2C5_TX_DMA_CONFIG
#define I2C5_TX_DMA_CONFIG \
{ \
.Instance = I2C5_TX_DMA_INSTANCE, \
.channel = I2C5_TX_DMA_CHANNEL, \
.clock = I2C5_TX_DMA_CLOCK, \
.trigger_select = I2C5_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C5_TEI, \
.flag = I2C5_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = I2C5_TX_DMA_IRQn, \
.irq_prio = I2C5_TX_DMA_INT_PRIO, \
.int_src = I2C5_TX_DMA_INT_SRC, \
}, \
#define I2C5_TX_DMA_CONFIG \
{ \
.Instance = I2C5_TX_DMA_INSTANCE, \
.channel = I2C5_TX_DMA_CHANNEL, \
.clock = I2C5_TX_DMA_CLOCK, \
.trigger_select = I2C5_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C5_TEI, \
.flag = I2C5_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = I2C5_TX_DMA_IRQn, \
.irq_prio = I2C5_TX_DMA_INT_PRIO, \
.int_src = I2C5_TX_DMA_INT_SRC, \
}, \
}
#endif /* I2C5_TX_DMA_CONFIG */
#ifndef I2C5_RX_DMA_CONFIG
#define I2C5_RX_DMA_CONFIG \
{ \
.Instance = I2C5_RX_DMA_INSTANCE, \
.channel = I2C5_RX_DMA_CHANNEL, \
.clock = I2C5_RX_DMA_CLOCK, \
.trigger_select = I2C5_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C5_RXI, \
.flag = I2C5_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = I2C5_RX_DMA_IRQn, \
.irq_prio = I2C5_RX_DMA_INT_PRIO, \
.int_src = I2C5_RX_DMA_INT_SRC, \
}, \
#define I2C5_RX_DMA_CONFIG \
{ \
.Instance = I2C5_RX_DMA_INSTANCE, \
.channel = I2C5_RX_DMA_CHANNEL, \
.clock = I2C5_RX_DMA_CLOCK, \
.trigger_select = I2C5_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C5_RXI, \
.flag = I2C5_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = I2C5_RX_DMA_IRQn, \
.irq_prio = I2C5_RX_DMA_INT_PRIO, \
.int_src = I2C5_RX_DMA_INT_SRC, \
}, \
}
#endif /* I2C5_RX_DMA_CONFIG */
#endif /* BSP_I2C5_USING_DMA */
@ -276,50 +266,48 @@ extern "C" {
#if defined(BSP_USING_I2C6)
#ifndef I2C6_CONFIG
#define I2C6_CONFIG \
{ \
.name = "i2c6", \
.Instance = CM_I2C6, \
.clock = FCG1_PERIPH_I2C6, \
.baudrate = 100000UL, \
.timeout = 10000UL, \
#define I2C6_CONFIG \
{ \
.name = "i2c6", \
.Instance = CM_I2C6, \
.clock = FCG1_PERIPH_I2C6, \
.baudrate = 100000UL, \
.timeout = 10000UL, \
}
#endif /* I2C6_CONFIG */
#if defined(BSP_I2C6_USING_DMA)
#ifndef I2C6_TX_DMA_CONFIG
#define I2C6_TX_DMA_CONFIG \
{ \
.Instance = I2C6_TX_DMA_INSTANCE, \
.channel = I2C6_TX_DMA_CHANNEL, \
.clock = I2C6_TX_DMA_CLOCK, \
.trigger_select = I2C6_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C6_TEI, \
.flag = I2C6_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = I2C6_TX_DMA_IRQn, \
.irq_prio = I2C6_TX_DMA_INT_PRIO, \
.int_src = I2C6_TX_DMA_INT_SRC, \
}, \
#define I2C6_TX_DMA_CONFIG \
{ \
.Instance = I2C6_TX_DMA_INSTANCE, \
.channel = I2C6_TX_DMA_CHANNEL, \
.clock = I2C6_TX_DMA_CLOCK, \
.trigger_select = I2C6_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C6_TEI, \
.flag = I2C6_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = I2C6_TX_DMA_IRQn, \
.irq_prio = I2C6_TX_DMA_INT_PRIO, \
.int_src = I2C6_TX_DMA_INT_SRC, \
}, \
}
#endif /* I2C6_TX_DMA_CONFIG */
#ifndef I2C6_RX_DMA_CONFIG
#define I2C6_RX_DMA_CONFIG \
{ \
.Instance = I2C6_RX_DMA_INSTANCE, \
.channel = I2C6_RX_DMA_CHANNEL, \
.clock = I2C6_RX_DMA_CLOCK, \
.trigger_select = I2C6_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C6_RXI, \
.flag = I2C6_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = I2C6_RX_DMA_IRQn, \
.irq_prio = I2C6_RX_DMA_INT_PRIO, \
.int_src = I2C6_RX_DMA_INT_SRC, \
}, \
#define I2C6_RX_DMA_CONFIG \
{ \
.Instance = I2C6_RX_DMA_INSTANCE, \
.channel = I2C6_RX_DMA_CHANNEL, \
.clock = I2C6_RX_DMA_CLOCK, \
.trigger_select = I2C6_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C6_RXI, \
.flag = I2C6_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = I2C6_RX_DMA_IRQn, \
.irq_prio = I2C6_RX_DMA_INT_PRIO, \
.int_src = I2C6_RX_DMA_INT_SRC, \
}, \
}
#endif /* I2C6_RX_DMA_CONFIG */
#endif /* BSP_I2C6_USING_DMA */

274
bsp/hc32/ev_hc32f448_lqfp80/board/config/irq_config.h
View File

@ -18,245 +18,245 @@
extern "C" {
#endif
#define BSP_EXTINT0_IRQ_NUM EXTINT_PORT_EIRQ0_IRQn
#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT1_IRQ_NUM EXTINT_PORT_EIRQ1_IRQn
#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT2_IRQ_NUM EXTINT_PORT_EIRQ2_IRQn
#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT3_IRQ_NUM EXTINT_PORT_EIRQ3_IRQn
#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT4_IRQ_NUM EXTINT_PORT_EIRQ4_IRQn
#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT5_IRQ_NUM EXTINT_PORT_EIRQ5_IRQn
#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT6_IRQ_NUM EXTINT_PORT_EIRQ6_IRQn
#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT7_IRQ_NUM EXTINT_PORT_EIRQ7_IRQn
#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT8_IRQ_NUM EXTINT_PORT_EIRQ8_IRQn
#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT9_IRQ_NUM EXTINT_PORT_EIRQ9_IRQn
#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT10_IRQ_NUM EXTINT_PORT_EIRQ10_IRQn
#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT11_IRQ_NUM EXTINT_PORT_EIRQ11_IRQn
#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT12_IRQ_NUM EXTINT_PORT_EIRQ12_IRQn
#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT13_IRQ_NUM EXTINT_PORT_EIRQ13_IRQn
#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT14_IRQ_NUM EXTINT_PORT_EIRQ14_IRQn
#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT15_IRQ_NUM EXTINT_PORT_EIRQ15_IRQn
#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT0_IRQ_NUM EXTINT_PORT_EIRQ0_IRQn
#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT1_IRQ_NUM EXTINT_PORT_EIRQ1_IRQn
#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT2_IRQ_NUM EXTINT_PORT_EIRQ2_IRQn
#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT3_IRQ_NUM EXTINT_PORT_EIRQ3_IRQn
#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT4_IRQ_NUM EXTINT_PORT_EIRQ4_IRQn
#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT5_IRQ_NUM EXTINT_PORT_EIRQ5_IRQn
#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT6_IRQ_NUM EXTINT_PORT_EIRQ6_IRQn
#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT7_IRQ_NUM EXTINT_PORT_EIRQ7_IRQn
#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT8_IRQ_NUM EXTINT_PORT_EIRQ8_IRQn
#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT9_IRQ_NUM EXTINT_PORT_EIRQ9_IRQn
#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT10_IRQ_NUM EXTINT_PORT_EIRQ10_IRQn
#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT11_IRQ_NUM EXTINT_PORT_EIRQ11_IRQn
#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT12_IRQ_NUM EXTINT_PORT_EIRQ12_IRQn
#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT13_IRQ_NUM EXTINT_PORT_EIRQ13_IRQn
#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT14_IRQ_NUM EXTINT_PORT_EIRQ14_IRQn
#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT15_IRQ_NUM EXTINT_PORT_EIRQ15_IRQn
#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch0 */
#define BSP_DMA1_CH0_IRQ_NUM INT000_IRQn
#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA1_CH0_IRQ_NUM INT000_IRQn
#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch1 */
#define BSP_DMA1_CH1_IRQ_NUM INT001_IRQn
#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA1_CH1_IRQ_NUM INT001_IRQn
#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch2 */
#define BSP_DMA1_CH2_IRQ_NUM INT002_IRQn
#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA1_CH2_IRQ_NUM INT002_IRQn
#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch3 */
#define BSP_DMA1_CH3_IRQ_NUM INT003_IRQn
#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA1_CH3_IRQ_NUM INT003_IRQn
#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch4 */
#define BSP_DMA1_CH4_IRQ_NUM INT004_IRQn
#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA1_CH4_IRQ_NUM INT004_IRQn
#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch5 */
#define BSP_DMA1_CH5_IRQ_NUM INT005_IRQn
#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA1_CH5_IRQ_NUM INT005_IRQn
#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA2 ch0 */
#define BSP_DMA2_CH0_IRQ_NUM INT006_IRQn
#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA2_CH0_IRQ_NUM INT006_IRQn
#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA2 ch1 */
#define BSP_DMA2_CH1_IRQ_NUM INT007_IRQn
#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA2_CH1_IRQ_NUM INT007_IRQn
#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA2 ch2 */
#define BSP_DMA2_CH2_IRQ_NUM INT008_IRQn
#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA2_CH2_IRQ_NUM INT008_IRQn
#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA2 ch3 */
#define BSP_DMA2_CH3_IRQ_NUM INT009_IRQn
#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA2_CH3_IRQ_NUM INT009_IRQn
#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA2 ch4 */
#define BSP_DMA2_CH4_IRQ_NUM INT010_IRQn
#define BSP_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA2_CH4_IRQ_NUM INT010_IRQn
#define BSP_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA2 ch5 */
#define BSP_DMA2_CH5_IRQ_NUM INT011_IRQn
#define BSP_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA2_CH5_IRQ_NUM INT011_IRQn
#define BSP_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if defined(BSP_USING_UART1)
#define BSP_UART1_IRQ_NUM USART1_IRQn
#define BSP_UART1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART1_IRQ_NUM USART1_IRQn
#define BSP_UART1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)) || \
defined(RT_USING_SERIAL_V2)
#define BSP_UART1_TX_CPLT_IRQ_NUM USART1_TCI_IRQn
#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART1_TX_CPLT_IRQ_NUM USART1_TCI_IRQn
#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#endif /* BSP_USING_UART1 */
#if defined(BSP_USING_UART2)
#define BSP_UART2_IRQ_NUM USART2_IRQn
#define BSP_UART2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART2_IRQ_NUM USART2_IRQn
#define BSP_UART2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)) || \
defined(RT_USING_SERIAL_V2)
#define BSP_UART2_TX_CPLT_IRQ_NUM USART2_TCI_IRQn
#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART2_TX_CPLT_IRQ_NUM USART2_TCI_IRQn
#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#endif /* BSP_USING_UART2 */
#if defined(BSP_USING_UART3)
#define BSP_UART3_IRQ_NUM USART3_IRQn
#define BSP_UART3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART3_IRQ_NUM USART3_IRQn
#define BSP_UART3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif /* BSP_USING_UART3 */
#if defined(BSP_USING_UART4)
#define BSP_UART4_IRQ_NUM USART4_IRQn
#define BSP_UART4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART4_IRQ_NUM USART4_IRQn
#define BSP_UART4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)) || \
defined(RT_USING_SERIAL_V2)
#define BSP_UART4_TX_CPLT_IRQ_NUM USART4_TCI_IRQn
#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART4_TX_CPLT_IRQ_NUM USART4_TCI_IRQn
#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#endif /* BSP_USING_UART4 */
#if defined(BSP_USING_UART5)
#define BSP_UART5_IRQ_NUM USART5_IRQn
#define BSP_UART5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART5_IRQ_NUM USART5_IRQn
#define BSP_UART5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART5_TX_USING_DMA)) || \
defined(RT_USING_SERIAL_V2)
#define BSP_UART5_TX_CPLT_IRQ_NUM USART5_TCI_IRQn
#define BSP_UART5_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART5_TX_CPLT_IRQ_NUM USART5_TCI_IRQn
#define BSP_UART5_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#endif /* BSP_USING_UART5 */
#if defined(BSP_USING_UART6)
#define BSP_UART6_IRQ_NUM USART6_IRQn
#define BSP_UART6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART6_IRQ_NUM USART6_IRQn
#define BSP_UART6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif /* BSP_USING_UART6 */
#if defined(BSP_USING_SPI1)
#define BSP_SPI1_ERR_IRQ_NUM SPI1_IRQn
#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_SPI1_ERR_IRQ_NUM SPI1_IRQn
#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#if defined(BSP_USING_SPI2)
#define BSP_SPI2_ERR_IRQ_NUM SPI2_IRQn
#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_SPI2_ERR_IRQ_NUM SPI2_IRQn
#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#if defined(BSP_USING_SPI3)
#define BSP_SPI3_ERR_IRQ_NUM SPI3_IRQn
#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_SPI3_ERR_IRQ_NUM SPI3_IRQn
#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#if defined (BSP_USING_QSPI)
#define BSP_QSPI_ERR_IRQ_NUM QSPI_IRQn
#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if defined(BSP_USING_QSPI)
#define BSP_QSPI_ERR_IRQ_NUM QSPI_IRQn
#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif /* BSP_USING_QSPI */
#if defined(BSP_USING_TMRA_1)
#define BSP_USING_TMRA_1_IRQ_NUM TMRA_1_OVF_UDF_IRQn
#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_USING_TMRA_1_IRQ_NUM TMRA_1_OVF_UDF_IRQn
#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_1 */
#if defined(BSP_USING_TMRA_2)
#define BSP_USING_TMRA_2_IRQ_NUM TMRA_2_OVF_UDF_IRQn
#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_USING_TMRA_2_IRQ_NUM TMRA_2_OVF_UDF_IRQn
#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_2 */
#if defined(BSP_USING_TMRA_3)
#define BSP_USING_TMRA_3_IRQ_NUM TMRA_3_OVF_UDF_IRQn
#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_USING_TMRA_3_IRQ_NUM TMRA_3_OVF_UDF_IRQn
#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_3 */
#if defined(BSP_USING_TMRA_4)
#define BSP_USING_TMRA_4_IRQ_NUM TMRA_4_OVF_UDF_IRQn
#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_USING_TMRA_4_IRQ_NUM TMRA_4_OVF_UDF_IRQn
#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_4 */
#if defined(BSP_USING_TMRA_5)
#define BSP_USING_TMRA_5_IRQ_NUM TMRA_5_OVF_UDF_IRQn
#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_USING_TMRA_5_IRQ_NUM TMRA_5_OVF_UDF_IRQn
#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_5 */
#if defined(BSP_USING_MCAN1)
#define BSP_MCAN1_INT0_IRQ_NUM MCAN1_INT0_IRQn
#define BSP_MCAN1_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_MCAN1_INT0_IRQ_NUM MCAN1_INT0_IRQn
#define BSP_MCAN1_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_MCAN1 */
#if defined(BSP_USING_MCAN2)
#define BSP_MCAN2_INT0_IRQ_NUM MCAN2_INT0_IRQn
#define BSP_MCAN2_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_MCAN2_INT0_IRQ_NUM MCAN2_INT0_IRQn
#define BSP_MCAN2_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_MCAN2 */
#if defined(RT_USING_ALARM)
#define BSP_RTC_ALARM_IRQ_NUM RTC_IRQn
#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_RTC_ALARM_IRQ_NUM RTC_IRQn
#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* RT_USING_ALARM */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM TMRA_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM TMRA_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM TMRA_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM TMRA_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_2)
#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM TMRA_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM TMRA_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM TMRA_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM TMRA_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_3)
#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM TMRA_3_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM TMRA_3_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM TMRA_3_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM TMRA_3_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_4)
#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM TMRA_4_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM TMRA_4_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM TMRA_4_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM TMRA_4_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_5)
#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM TMRA_5_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM TMRA_5_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM TMRA_5_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM TMRA_5_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */
#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM TMR6_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM TMR6_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM TMR6_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM TMR6_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */
#if defined(BSP_USING_PULSE_ENCODER_TMR6_2)
#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM TMR6_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM TMR6_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM TMR6_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM TMR6_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */
#if defined(BSP_USING_INPUT_CAPTURE)
#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT012_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT013_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT012_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT013_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT014_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT015_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT014_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT015_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#endif
#ifdef __cplusplus

464
bsp/hc32/ev_hc32f448_lqfp80/board/config/mcan_config.h
View File

@ -31,56 +31,56 @@ extern "C" {
*/
#ifdef RT_CAN_USING_CANFD
#define MCAN_FD_SEL MCAN_FD_ISO_FD_BRS
#define MCAN_TOTAL_FILTER_NUM (26U)
#define MCAN_STD_FILTER_NUM (13U) /* Each standard filter element size is 4 bytes */
#define MCAN_EXT_FILTER_NUM (13U) /* Each extended filter element size is 8 bytes */
#define MCAN_TX_FIFO_NUM (6U)
#define MCAN_RX_FIFO_NUM (6U)
#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_64BYTE) /* Each FIFO element size is 64+8 bytes */
#define MCAN_FD_SEL MCAN_FD_ISO_FD_BRS
#define MCAN_TOTAL_FILTER_NUM (26U)
#define MCAN_STD_FILTER_NUM (13U) /* Each standard filter element size is 4 bytes */
#define MCAN_EXT_FILTER_NUM (13U) /* Each extended filter element size is 8 bytes */
#define MCAN_TX_FIFO_NUM (6U)
#define MCAN_RX_FIFO_NUM (6U)
#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_64BYTE) /* Each FIFO element size is 64+8 bytes */
#else
#define MCAN_FD_SEL MCAN_FD_CLASSICAL
#define MCAN_TOTAL_FILTER_NUM (32U)
#define MCAN_STD_FILTER_NUM (16U) /* Each standard filter element size is 4 bytes */
#define MCAN_EXT_FILTER_NUM (16U) /* Each extended filter element size is 8 bytes */
#define MCAN_TX_FIFO_NUM (26U)
#define MCAN_RX_FIFO_NUM (26U)
#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_8BYTE) /* Each FIFO element size is 8+8 bytes */
#define MCAN_FD_SEL MCAN_FD_CLASSICAL
#define MCAN_TOTAL_FILTER_NUM (32U)
#define MCAN_STD_FILTER_NUM (16U) /* Each standard filter element size is 4 bytes */
#define MCAN_EXT_FILTER_NUM (16U) /* Each extended filter element size is 8 bytes */
#define MCAN_TX_FIFO_NUM (26U)
#define MCAN_RX_FIFO_NUM (26U)
#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_8BYTE) /* Each FIFO element size is 8+8 bytes */
#endif
#ifdef BSP_USING_MCAN1
#define MCAN1_NAME ("mcan1")
#define MCAN1_WORK_MODE (RT_CAN_MODE_NORMAL)
#define MCAN1_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */
#define MCAN1_NAME ("mcan1")
#define MCAN1_WORK_MODE (RT_CAN_MODE_NORMAL)
#define MCAN1_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */
#define MCAN1_FD_SEL MCAN_FD_SEL
#define MCAN1_FD_SEL MCAN_FD_SEL
#define MCAN1_STD_FILTER_NUM MCAN_STD_FILTER_NUM
#define MCAN1_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM
#define MCAN1_STD_FILTER_NUM MCAN_STD_FILTER_NUM
#define MCAN1_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM
#define MCAN1_RX_FIFO0_NUM MCAN_RX_FIFO_NUM
#define MCAN1_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
#define MCAN1_RX_FIFO0_NUM MCAN_RX_FIFO_NUM
#define MCAN1_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
#define MCAN1_TX_FIFO_NUM MCAN_TX_FIFO_NUM
#define MCAN1_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
#define MCAN1_TX_NOTIFICATION_BUF ((1UL << MCAN1_TX_FIFO_NUM) - 1U)
#define MCAN1_TX_FIFO_NUM MCAN_TX_FIFO_NUM
#define MCAN1_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
#define MCAN1_TX_NOTIFICATION_BUF ((1UL << MCAN1_TX_FIFO_NUM) - 1U)
#endif /* BSP_USING_MCAN1 */
#ifdef BSP_USING_MCAN2
#define MCAN2_NAME ("mcan2")
#define MCAN2_WORK_MODE (RT_CAN_MODE_NORMAL)
#define MCAN2_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */
#define MCAN2_NAME ("mcan2")
#define MCAN2_WORK_MODE (RT_CAN_MODE_NORMAL)
#define MCAN2_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */
#define MCAN2_FD_SEL MCAN_FD_SEL
#define MCAN2_STD_FILTER_NUM MCAN_STD_FILTER_NUM
#define MCAN2_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM
#define MCAN2_FD_SEL MCAN_FD_SEL
#define MCAN2_STD_FILTER_NUM MCAN_STD_FILTER_NUM
#define MCAN2_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM
#define MCAN2_RX_FIFO0_NUM MCAN_RX_FIFO_NUM
#define MCAN2_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
#define MCAN2_RX_FIFO0_NUM MCAN_RX_FIFO_NUM
#define MCAN2_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
#define MCAN2_TX_FIFO_NUM MCAN_TX_FIFO_NUM
#define MCAN2_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
#define MCAN2_TX_NOTIFICATION_BUF ((1UL << MCAN2_TX_FIFO_NUM) - 1U)
#define MCAN2_TX_FIFO_NUM MCAN_TX_FIFO_NUM
#define MCAN2_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
#define MCAN2_TX_NOTIFICATION_BUF ((1UL << MCAN2_TX_FIFO_NUM) - 1U)
#endif /* BSP_USING_MCAN2 */
/***********************************************************************************************/
@ -101,154 +101,154 @@ extern "C" {
2. For the corresponding function of u32TdcFilter, please refer to the reference manual for details(TDCR.TDCF).
The u32TdcFilter can be get from PSR.TDCV.
*/
#define MCAN_FD_CFG_500K_1M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 64, \
.u32NominalTimeSeg2 = 16, \
.u32NominalSyncJumpWidth = 16, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 32, \
.u32DataTimeSeg2 = 8, \
.u32DataSyncJumpWidth = 8, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 32, \
.u32TdcFilter = 32 + 1, \
#define MCAN_FD_CFG_500K_1M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 64, \
.u32NominalTimeSeg2 = 16, \
.u32NominalSyncJumpWidth = 16, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 32, \
.u32DataTimeSeg2 = 8, \
.u32DataSyncJumpWidth = 8, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 32, \
.u32TdcFilter = 32 + 1, \
}
#define MCAN_FD_CFG_500K_2M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 64, \
.u32NominalTimeSeg2 = 16, \
.u32NominalSyncJumpWidth = 16, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 16, \
.u32DataTimeSeg2 = 4, \
.u32DataSyncJumpWidth = 4, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 16, \
.u32TdcFilter = 16 + 1, \
#define MCAN_FD_CFG_500K_2M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 64, \
.u32NominalTimeSeg2 = 16, \
.u32NominalSyncJumpWidth = 16, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 16, \
.u32DataTimeSeg2 = 4, \
.u32DataSyncJumpWidth = 4, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 16, \
.u32TdcFilter = 16 + 1, \
}
#define MCAN_FD_CFG_500K_4M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 64, \
.u32NominalTimeSeg2 = 16, \
.u32NominalSyncJumpWidth = 16, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 8, \
.u32DataTimeSeg2 = 2, \
.u32DataSyncJumpWidth = 2, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 8, \
.u32TdcFilter = 8 + 1, \
#define MCAN_FD_CFG_500K_4M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 64, \
.u32NominalTimeSeg2 = 16, \
.u32NominalSyncJumpWidth = 16, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 8, \
.u32DataTimeSeg2 = 2, \
.u32DataSyncJumpWidth = 2, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 8, \
.u32TdcFilter = 8 + 1, \
}
#define MCAN_FD_CFG_500K_5M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 64, \
.u32NominalTimeSeg2 = 16, \
.u32NominalSyncJumpWidth = 16, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 6, \
.u32DataTimeSeg2 = 2, \
.u32DataSyncJumpWidth = 2, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 6, \
.u32TdcFilter = 6 + 1, \
#define MCAN_FD_CFG_500K_5M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 64, \
.u32NominalTimeSeg2 = 16, \
.u32NominalSyncJumpWidth = 16, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 6, \
.u32DataTimeSeg2 = 2, \
.u32DataSyncJumpWidth = 2, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 6, \
.u32TdcFilter = 6 + 1, \
}
#define MCAN_FD_CFG_500K_8M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 64, \
.u32NominalTimeSeg2 = 16, \
.u32NominalSyncJumpWidth = 16, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 4, \
.u32DataTimeSeg2 = 1, \
.u32DataSyncJumpWidth = 1, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 4, \
.u32TdcFilter = 4 + 1, \
#define MCAN_FD_CFG_500K_8M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 64, \
.u32NominalTimeSeg2 = 16, \
.u32NominalSyncJumpWidth = 16, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 4, \
.u32DataTimeSeg2 = 1, \
.u32DataSyncJumpWidth = 1, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 4, \
.u32TdcFilter = 4 + 1, \
}
#define MCAN_FD_CFG_1M_1M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 32, \
.u32DataTimeSeg2 = 8, \
.u32DataSyncJumpWidth = 8, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 2*32, \
.u32TdcFilter = 2*32 + 1, \
#define MCAN_FD_CFG_1M_1M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 32, \
.u32DataTimeSeg2 = 8, \
.u32DataSyncJumpWidth = 8, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 2 * 32, \
.u32TdcFilter = 2 * 32 + 1, \
}
#define MCAN_FD_CFG_1M_2M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 16, \
.u32DataTimeSeg2 = 4, \
.u32DataSyncJumpWidth = 4, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 16, \
.u32TdcFilter = 16 + 1, \
#define MCAN_FD_CFG_1M_2M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 16, \
.u32DataTimeSeg2 = 4, \
.u32DataSyncJumpWidth = 4, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 16, \
.u32TdcFilter = 16 + 1, \
}
#define MCAN_FD_CFG_1M_4M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 8, \
.u32DataTimeSeg2 = 2, \
.u32DataSyncJumpWidth = 2, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 8, \
.u32TdcFilter = 8 + 1, \
#define MCAN_FD_CFG_1M_4M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 8, \
.u32DataTimeSeg2 = 2, \
.u32DataSyncJumpWidth = 2, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 8, \
.u32TdcFilter = 8 + 1, \
}
#define MCAN_FD_CFG_1M_5M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 6, \
.u32DataTimeSeg2 = 2, \
.u32DataSyncJumpWidth = 2, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 6, \
.u32TdcFilter = 6 + 1, \
#define MCAN_FD_CFG_1M_5M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 6, \
.u32DataTimeSeg2 = 2, \
.u32DataSyncJumpWidth = 2, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 6, \
.u32TdcFilter = 6 + 1, \
}
#define MCAN_FD_CFG_1M_8M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 4, \
.u32DataTimeSeg2 = 1, \
.u32DataSyncJumpWidth = 1, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 4, \
.u32TdcFilter = 4 + 1, \
#define MCAN_FD_CFG_1M_8M \
{ \
.u32NominalPrescaler = 1, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
.u32DataPrescaler = 1, \
.u32DataTimeSeg1 = 4, \
.u32DataTimeSeg2 = 1, \
.u32DataSyncJumpWidth = 1, \
.u32TDC = MCAN_FD_TDC_ENABLE, \
.u32SspOffset = 4, \
.u32TdcFilter = 4 + 1, \
}
/*
@ -260,95 +260,95 @@ extern "C" {
SamplePoint(%) = 16 / (16 + 4) = 80%
The following bit rate configurations are based on the max MCAN Clock(40MHz).
*/
#define MCAN_CC_CFG_1M \
{ \
.u32NominalPrescaler = 2, \
.u32NominalTimeSeg1 = 16, \
.u32NominalTimeSeg2 = 4, \
.u32NominalSyncJumpWidth = 4, \
#define MCAN_CC_CFG_1M \
{ \
.u32NominalPrescaler = 2, \
.u32NominalTimeSeg1 = 16, \
.u32NominalTimeSeg2 = 4, \
.u32NominalSyncJumpWidth = 4, \
}
#define MCAN_CC_CFG_800K \
{ \
.u32NominalPrescaler = 2, \
.u32NominalTimeSeg1 = 20, \
.u32NominalTimeSeg2 = 5, \
.u32NominalSyncJumpWidth = 5, \
#define MCAN_CC_CFG_800K \
{ \
.u32NominalPrescaler = 2, \
.u32NominalTimeSeg1 = 20, \
.u32NominalTimeSeg2 = 5, \
.u32NominalSyncJumpWidth = 5, \
}
#define MCAN_CC_CFG_500K \
{ \
.u32NominalPrescaler = 4, \
.u32NominalTimeSeg1 = 16, \
.u32NominalTimeSeg2 = 4, \
.u32NominalSyncJumpWidth = 4, \
#define MCAN_CC_CFG_500K \
{ \
.u32NominalPrescaler = 4, \
.u32NominalTimeSeg1 = 16, \
.u32NominalTimeSeg2 = 4, \
.u32NominalSyncJumpWidth = 4, \
}
#define MCAN_CC_CFG_250K \
{ \
.u32NominalPrescaler = 4, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
#define MCAN_CC_CFG_250K \
{ \
.u32NominalPrescaler = 4, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
}
#define MCAN_CC_CFG_125K \
{ \
.u32NominalPrescaler = 8, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
#define MCAN_CC_CFG_125K \
{ \
.u32NominalPrescaler = 8, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
}
#define MCAN_CC_CFG_100K \
{ \
.u32NominalPrescaler = 10, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
#define MCAN_CC_CFG_100K \
{ \
.u32NominalPrescaler = 10, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
}
#define MCAN_CC_CFG_50K \
{ \
.u32NominalPrescaler = 20, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
#define MCAN_CC_CFG_50K \
{ \
.u32NominalPrescaler = 20, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
}
#define MCAN_CC_CFG_20K \
{ \
.u32NominalPrescaler = 50, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
#define MCAN_CC_CFG_20K \
{ \
.u32NominalPrescaler = 50, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
}
#define MCAN_CC_CFG_10K \
{ \
.u32NominalPrescaler = 100, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
#define MCAN_CC_CFG_10K \
{ \
.u32NominalPrescaler = 100, \
.u32NominalTimeSeg1 = 32, \
.u32NominalTimeSeg2 = 8, \
.u32NominalSyncJumpWidth = 8, \
}
#ifdef RT_CAN_USING_CANFD
#define MCAN1_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M
#define MCAN1_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M
#define MCAN1_DATA_BAUD_RATE CANFD_DATA_BAUD_4M
#define MCAN1_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M
#define MCAN1_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M
#define MCAN1_DATA_BAUD_RATE CANFD_DATA_BAUD_4M
#define MCAN2_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M
#define MCAN2_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M
#define MCAN2_DATA_BAUD_RATE CANFD_DATA_BAUD_4M
#define MCAN2_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M
#define MCAN2_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M
#define MCAN2_DATA_BAUD_RATE CANFD_DATA_BAUD_4M
#else
#define MCAN1_BAUD_RATE_CFG MCAN_CC_CFG_1M
#define MCAN1_NOMINAL_BAUD_RATE CAN1MBaud
#define MCAN1_DATA_BAUD_RATE 0
#define MCAN1_BAUD_RATE_CFG MCAN_CC_CFG_1M
#define MCAN1_NOMINAL_BAUD_RATE CAN1MBaud
#define MCAN1_DATA_BAUD_RATE 0
#define MCAN2_BAUD_RATE_CFG MCAN_CC_CFG_1M
#define MCAN2_NOMINAL_BAUD_RATE CAN1MBaud
#define MCAN2_DATA_BAUD_RATE 0
#define MCAN2_BAUD_RATE_CFG MCAN_CC_CFG_1M
#define MCAN2_NOMINAL_BAUD_RATE CAN1MBaud
#define MCAN2_DATA_BAUD_RATE 0
#endif /* #ifdef RT_CAN_USING_CANFD */

72
bsp/hc32/ev_hc32f448_lqfp80/board/config/pm_config.h
View File

@ -22,18 +22,18 @@ extern "C" {
extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
#ifndef PM_TICKLESS_TIMER_ENABLE_MASK
#define PM_TICKLESS_TIMER_ENABLE_MASK \
( (1UL << PM_SLEEP_MODE_IDLE) | \
(1UL << PM_SLEEP_MODE_DEEP))
#define PM_TICKLESS_TIMER_ENABLE_MASK \
((1UL << PM_SLEEP_MODE_IDLE) | \
(1UL << PM_SLEEP_MODE_DEEP))
#endif
/**
* @brief run mode config @ref pm_run_mode_config structure
*/
#ifndef PM_RUN_MODE_CFG
#define PM_RUN_MODE_CFG \
{ \
.sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \
#define PM_RUN_MODE_CFG \
{ \
.sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \
}
#endif /* PM_RUN_MODE_CFG */
@ -41,54 +41,54 @@ extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
* @brief sleep idle config @ref pm_sleep_mode_idle_config structure
*/
#ifndef PM_SLEEP_IDLE_CFG
#define PM_SLEEP_IDLE_CFG \
{ \
.pwc_sleep_type = PWC_SLEEP_WFE_INT, \
}
#define PM_SLEEP_IDLE_CFG \
{ \
.pwc_sleep_type = PWC_SLEEP_WFE_INT, \
}
#endif /*PM_SLEEP_IDLE_CFG*/
/**
* @brief sleep deep config @ref pm_sleep_mode_deep_config structure
*/
#ifndef PM_SLEEP_DEEP_CFG
#define PM_SLEEP_DEEP_CFG \
{ \
{ \
.u16Clock = PWC_STOP_CLK_KEEP, \
.u8StopDrv = PWC_STOP_DRV_HIGH, \
.u16ExBusHold = PWC_STOP_EXBUS_HIZ, \
.u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \
}, \
.pwc_stop_type = PWC_STOP_WFE_INT, \
}
#define PM_SLEEP_DEEP_CFG \
{ \
{ \
.u16Clock = PWC_STOP_CLK_KEEP, \
.u8StopDrv = PWC_STOP_DRV_HIGH, \
.u16ExBusHold = PWC_STOP_EXBUS_HIZ, \
.u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \
}, \
.pwc_stop_type = PWC_STOP_WFE_INT, \
}
#endif /*PM_SLEEP_DEEP_CFG*/
/**
* @brief sleep standby config @ref pm_sleep_mode_standby_config structure
*/
#ifndef PM_SLEEP_STANDBY_CFG
#define PM_SLEEP_STANDBY_CFG \
{ \
{ \
.u8Mode = PWC_PD_MD1, \
.u8IOState = PWC_PD_IO_KEEP1, \
.u8VcapCtrl = PWC_PD_VCAP_0P047UF, \
}, \
}
#define PM_SLEEP_STANDBY_CFG \
{ \
{ \
.u8Mode = PWC_PD_MD1, \
.u8IOState = PWC_PD_IO_KEEP1, \
.u8VcapCtrl = PWC_PD_VCAP_0P047UF, \
}, \
}
#endif /*PM_SLEEP_STANDBY_CFG*/
/**
* @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure
*/
#ifndef PM_SLEEP_SHUTDOWN_CFG
#define PM_SLEEP_SHUTDOWN_CFG \
{ \
{ \
.u8Mode = PWC_PD_MD3, \
.u8IOState = PWC_PD_IO_KEEP1, \
.u8VcapCtrl = PWC_PD_VCAP_0P047UF, \
}, \
}
#define PM_SLEEP_SHUTDOWN_CFG \
{ \
{ \
.u8Mode = PWC_PD_MD3, \
.u8IOState = PWC_PD_IO_KEEP1, \
.u8VcapCtrl = PWC_PD_VCAP_0P047UF, \
}, \
}
#endif /*PM_SLEEP_SHUTDOWN_CFG*/
#endif /* BSP_USING_PM */

266
bsp/hc32/ev_hc32f448_lqfp80/board/config/pulse_encoder_config.h
View File

@ -22,182 +22,168 @@ extern "C" {
#ifdef BSP_USING_PULSE_ENCODER_TMRA_1
#ifndef PULSE_ENCODER_TMRA_1_CONFIG
#define PULSE_ENCODER_TMRA_1_CONFIG \
{ \
.tmr_handler = CM_TMRA_1, \
.u32PeriphClock = FCG2_PERIPH_TMRA_1, \
.hw_count = \
{ \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = \
{ \
.enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a1" \
#define PULSE_ENCODER_TMRA_1_CONFIG \
{ \
.tmr_handler = CM_TMRA_1, \
.u32PeriphClock = FCG2_PERIPH_TMRA_1, \
.hw_count = { \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = { \
.enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a1" \
}
#endif /* PULSE_ENCODER_TMRA_1_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
#ifdef BSP_USING_PULSE_ENCODER_TMRA_2
#ifndef PULSE_ENCODER_TMRA_2_CONFIG
#define PULSE_ENCODER_TMRA_2_CONFIG \
{ \
.tmr_handler = CM_TMRA_2, \
.u32PeriphClock = FCG2_PERIPH_TMRA_2, \
.hw_count = \
{ \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = \
{ \
.enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a2" \
#define PULSE_ENCODER_TMRA_2_CONFIG \
{ \
.tmr_handler = CM_TMRA_2, \
.u32PeriphClock = FCG2_PERIPH_TMRA_2, \
.hw_count = { \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = { \
.enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a2" \
}
#endif /* PULSE_ENCODER_TMRA_2_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */
#ifdef BSP_USING_PULSE_ENCODER_TMRA_3
#ifndef PULSE_ENCODER_TMRA_3_CONFIG
#define PULSE_ENCODER_TMRA_3_CONFIG \
{ \
.tmr_handler = CM_TMRA_3, \
.u32PeriphClock = FCG2_PERIPH_TMRA_3, \
.hw_count = \
{ \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = \
{ \
.enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a3" \
#define PULSE_ENCODER_TMRA_3_CONFIG \
{ \
.tmr_handler = CM_TMRA_3, \
.u32PeriphClock = FCG2_PERIPH_TMRA_3, \
.hw_count = { \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = { \
.enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a3" \
}
#endif /* PULSE_ENCODER_TMRA_3_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */
#ifdef BSP_USING_PULSE_ENCODER_TMRA_4
#ifndef PULSE_ENCODER_TMRA_4_CONFIG
#define PULSE_ENCODER_TMRA_4_CONFIG \
{ \
.tmr_handler = CM_TMRA_4, \
.u32PeriphClock = FCG2_PERIPH_TMRA_4, \
.hw_count = \
{ \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = \
{ \
.enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a4" \
#define PULSE_ENCODER_TMRA_4_CONFIG \
{ \
.tmr_handler = CM_TMRA_4, \
.u32PeriphClock = FCG2_PERIPH_TMRA_4, \
.hw_count = { \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = { \
.enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a4" \
}
#endif /* PULSE_ENCODER_TMRA_4_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */
#ifdef BSP_USING_PULSE_ENCODER_TMRA_5
#ifndef PULSE_ENCODER_TMRA_5_CONFIG
#define PULSE_ENCODER_TMRA_5_CONFIG \
{ \
.tmr_handler = CM_TMRA_5, \
.u32PeriphClock = FCG2_PERIPH_TMRA_5, \
.hw_count = \
{ \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = \
{ \
.enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a5" \
#define PULSE_ENCODER_TMRA_5_CONFIG \
{ \
.tmr_handler = CM_TMRA_5, \
.u32PeriphClock = FCG2_PERIPH_TMRA_5, \
.hw_count = { \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = { \
.enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a5" \
}
#endif /* PULSE_ENCODER_TMRA_5_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */
#ifdef BSP_USING_PULSE_ENCODER_TMR6_1
#ifndef PULSE_ENCODER_TMR6_1_CONFIG
#define PULSE_ENCODER_TMR6_1_CONFIG \
{ \
.tmr_handler = CM_TMR6_1, \
.u32PeriphClock = FCG2_PERIPH_TMR6_1, \
.hw_count = \
{ \
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
}, \
.isr = \
{ \
.enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_61" \
#define PULSE_ENCODER_TMR6_1_CONFIG \
{ \
.tmr_handler = CM_TMR6_1, \
.u32PeriphClock = FCG2_PERIPH_TMR6_1, \
.hw_count = { \
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
}, \
.isr = { \
.enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_61" \
}
#endif /* PULSE_ENCODER_TMR6_1_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
#ifdef BSP_USING_PULSE_ENCODER_TMR6_2
#ifndef PULSE_ENCODER_TMR6_2_CONFIG
#define PULSE_ENCODER_TMR6_2_CONFIG \
{ \
.tmr_handler = CM_TMR6_2, \
.u32PeriphClock = FCG2_PERIPH_TMR6_2, \
.hw_count = \
{ \
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
}, \
.isr = \
{ \
.enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_62" \
#define PULSE_ENCODER_TMR6_2_CONFIG \
{ \
.tmr_handler = CM_TMR6_2, \
.u32PeriphClock = FCG2_PERIPH_TMR6_2, \
.hw_count = { \
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
}, \
.isr = { \
.enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_62" \
}
#endif /* PULSE_ENCODER_TMR6_2_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */

1009
bsp/hc32/ev_hc32f448_lqfp80/board/config/pwm_tmr_config.h
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File diff suppressed because it is too large Load Diff

64
bsp/hc32/ev_hc32f448_lqfp80/board/config/qspi_config.h
View File

@ -21,54 +21,52 @@ extern "C" {
#ifdef BSP_USING_QSPI
#ifndef QSPI_BUS_CONFIG
#define QSPI_BUS_CONFIG \
{ \
.Instance = CM_QSPI, \
.clock = FCG1_PERIPH_QSPI, \
.timeout = 5000UL, \
.err_irq.irq_config = \
{ \
.irq_num = BSP_QSPI_ERR_IRQ_NUM, \
.irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \
.int_src = INT_SRC_QSPI_INTR, \
}, \
#define QSPI_BUS_CONFIG \
{ \
.Instance = CM_QSPI, \
.clock = FCG1_PERIPH_QSPI, \
.timeout = 5000UL, \
.err_irq.irq_config = { \
.irq_num = BSP_QSPI_ERR_IRQ_NUM, \
.irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \
.int_src = INT_SRC_QSPI_INTR, \
}, \
}
#endif /* QSPI_BUS_CONFIG */
#ifndef QSPI_INIT_PARAMS
#define QSPI_INIT_PARAMS \
{ \
.u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \
.u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \
.u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \
.u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \
#define QSPI_INIT_PARAMS \
{ \
.u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \
.u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \
.u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \
.u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \
}
#endif /* QSPI_INIT_PARAMS */
#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH
#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH
#ifdef BSP_QSPI_USING_DMA
#ifndef QSPI_DMA_CONFIG
#define QSPI_DMA_CONFIG \
{ \
.Instance = QSPI_DMA_INSTANCE, \
.channel = QSPI_DMA_CHANNEL, \
.clock = QSPI_DMA_CLOCK, \
.trigger_select = QSPI_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_AOS_STRG, \
.flag = QSPI_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = QSPI_DMA_IRQn, \
.irq_prio = QSPI_DMA_INT_PRIO, \
.int_src = QSPI_DMA_INT_SRC, \
} \
#define QSPI_DMA_CONFIG \
{ \
.Instance = QSPI_DMA_INSTANCE, \
.channel = QSPI_DMA_CHANNEL, \
.clock = QSPI_DMA_CLOCK, \
.trigger_select = QSPI_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_AOS_STRG, \
.flag = QSPI_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = QSPI_DMA_IRQn, \
.irq_prio = QSPI_DMA_INT_PRIO, \
.int_src = QSPI_DMA_INT_SRC, \
} \
}
#endif /* QSPI_DMA_CONFIG */
/* unit: half-word, DMA data width of QSPI transmitting is 16bit */
#ifndef QSPI_DMA_TX_BUFSIZE
#define QSPI_DMA_TX_BUFSIZE 256
#define QSPI_DMA_TX_BUFSIZE 256
#endif /* QSPI_DMA_TX_BUFSIZE */
#endif /* BSP_QSPI_USING_DMA */
#endif /* BSP_USING_QSPI */

231
bsp/hc32/ev_hc32f448_lqfp80/board/config/spi_config.h
View File

@ -22,134 +22,127 @@ extern "C" {
#ifdef BSP_USING_SPI1
#ifndef SPI1_BUS_CONFIG
#define SPI1_BUS_CONFIG \
{ \
.Instance = CM_SPI1, \
.bus_name = "spi1", \
.clock = FCG1_PERIPH_SPI1, \
.timeout = 5000UL, \
.err_irq.irq_config = \
{ \
.irq_num = BSP_SPI1_ERR_IRQ_NUM, \
.irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \
.int_src = INT_SRC_SPI1_SPEI, \
}, \
#define SPI1_BUS_CONFIG \
{ \
.Instance = CM_SPI1, \
.bus_name = "spi1", \
.clock = FCG1_PERIPH_SPI1, \
.timeout = 5000UL, \
.err_irq.irq_config = { \
.irq_num = BSP_SPI1_ERR_IRQ_NUM, \
.irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \
.int_src = INT_SRC_SPI1_SPEI, \
}, \
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
{ \
.Instance = SPI1_TX_DMA_INSTANCE, \
.channel = SPI1_TX_DMA_CHANNEL, \
.clock = SPI1_TX_DMA_CLOCK, \
.trigger_select = SPI1_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI1_SPTI, \
.flag = SPI1_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = SPI1_TX_DMA_IRQn, \
.irq_prio = SPI1_TX_DMA_INT_PRIO, \
.int_src = SPI1_TX_DMA_INT_SRC, \
} \
#define SPI1_TX_DMA_CONFIG \
{ \
.Instance = SPI1_TX_DMA_INSTANCE, \
.channel = SPI1_TX_DMA_CHANNEL, \
.clock = SPI1_TX_DMA_CLOCK, \
.trigger_select = SPI1_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI1_SPTI, \
.flag = SPI1_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = SPI1_TX_DMA_IRQn, \
.irq_prio = SPI1_TX_DMA_INT_PRIO, \
.int_src = SPI1_TX_DMA_INT_SRC, \
} \
}
#endif /* SPI1_TX_DMA_CONFIG */
#endif /* BSP_SPI1_TX_USING_DMA */
#ifdef BSP_SPI1_RX_USING_DMA
#ifndef SPI1_RX_DMA_CONFIG
#define SPI1_RX_DMA_CONFIG \
{ \
.Instance = SPI1_RX_DMA_INSTANCE, \
.channel = SPI1_RX_DMA_CHANNEL, \
.clock = SPI1_RX_DMA_CLOCK, \
.trigger_select = SPI1_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI1_SPRI, \
.flag = SPI1_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = SPI1_RX_DMA_IRQn, \
.irq_prio = SPI1_RX_DMA_INT_PRIO, \
.int_src = SPI1_RX_DMA_INT_SRC, \
} \
#define SPI1_RX_DMA_CONFIG \
{ \
.Instance = SPI1_RX_DMA_INSTANCE, \
.channel = SPI1_RX_DMA_CHANNEL, \
.clock = SPI1_RX_DMA_CLOCK, \
.trigger_select = SPI1_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI1_SPRI, \
.flag = SPI1_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = SPI1_RX_DMA_IRQn, \
.irq_prio = SPI1_RX_DMA_INT_PRIO, \
.int_src = SPI1_RX_DMA_INT_SRC, \
} \
}
#endif /* SPI1_RX_DMA_CONFIG */
#endif /* BSP_SPI1_RX_USING_DMA */
#ifdef BSP_USING_SPI2
#ifndef SPI2_BUS_CONFIG
#define SPI2_BUS_CONFIG \
{ \
.Instance = CM_SPI2, \
.bus_name = "spi2", \
.clock = FCG1_PERIPH_SPI2, \
.timeout = 5000UL, \
.err_irq.irq_config = \
{ \
.irq_num = BSP_SPI2_ERR_IRQ_NUM, \
.irq_prio = BSP_SPI2_ERR_IRQ_PRIO, \
.int_src = INT_SRC_SPI2_SPEI, \
}, \
#define SPI2_BUS_CONFIG \
{ \
.Instance = CM_SPI2, \
.bus_name = "spi2", \
.clock = FCG1_PERIPH_SPI2, \
.timeout = 5000UL, \
.err_irq.irq_config = { \
.irq_num = BSP_SPI2_ERR_IRQ_NUM, \
.irq_prio = BSP_SPI2_ERR_IRQ_PRIO, \
.int_src = INT_SRC_SPI2_SPEI, \
}, \
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#ifdef BSP_SPI2_TX_USING_DMA
#ifndef SPI2_TX_DMA_CONFIG
#define SPI2_TX_DMA_CONFIG \
{ \
.Instance = SPI2_TX_DMA_INSTANCE, \
.channel = SPI2_TX_DMA_CHANNEL, \
.clock = SPI2_TX_DMA_CLOCK, \
.trigger_select = SPI2_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI2_SPTI, \
.flag = SPI2_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = SPI2_TX_DMA_IRQn, \
.irq_prio = SPI2_TX_DMA_INT_PRIO, \
.int_src = SPI2_TX_DMA_INT_SRC, \
} \
#define SPI2_TX_DMA_CONFIG \
{ \
.Instance = SPI2_TX_DMA_INSTANCE, \
.channel = SPI2_TX_DMA_CHANNEL, \
.clock = SPI2_TX_DMA_CLOCK, \
.trigger_select = SPI2_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI2_SPTI, \
.flag = SPI2_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = SPI2_TX_DMA_IRQn, \
.irq_prio = SPI2_TX_DMA_INT_PRIO, \
.int_src = SPI2_TX_DMA_INT_SRC, \
} \
}
#endif /* SPI2_TX_DMA_CONFIG */
#endif /* BSP_SPI2_TX_USING_DMA */
#ifdef BSP_SPI2_RX_USING_DMA
#ifndef SPI2_RX_DMA_CONFIG
#define SPI2_RX_DMA_CONFIG \
{ \
.Instance = SPI2_RX_DMA_INSTANCE, \
.channel = SPI2_RX_DMA_CHANNEL, \
.clock = SPI2_RX_DMA_CLOCK, \
.trigger_select = SPI2_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI2_SPRI, \
.flag = SPI2_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = SPI2_RX_DMA_IRQn, \
.irq_prio = SPI2_RX_DMA_INT_PRIO, \
.int_src = SPI2_RX_DMA_INT_SRC, \
} \
#define SPI2_RX_DMA_CONFIG \
{ \
.Instance = SPI2_RX_DMA_INSTANCE, \
.channel = SPI2_RX_DMA_CHANNEL, \
.clock = SPI2_RX_DMA_CLOCK, \
.trigger_select = SPI2_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI2_SPRI, \
.flag = SPI2_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = SPI2_RX_DMA_IRQn, \
.irq_prio = SPI2_RX_DMA_INT_PRIO, \
.int_src = SPI2_RX_DMA_INT_SRC, \
} \
}
#endif /* SPI2_RX_DMA_CONFIG */
#endif /* BSP_SPI2_RX_USING_DMA */
#ifdef BSP_USING_SPI3
#ifndef SPI3_BUS_CONFIG
#define SPI3_BUS_CONFIG \
{ \
.Instance = CM_SPI3, \
.bus_name = "spi3", \
.clock = FCG1_PERIPH_SPI3, \
.timeout = 5000UL, \
.err_irq.irq_config = \
{ \
.irq_num = BSP_SPI3_ERR_IRQ_NUM, \
.irq_prio = BSP_SPI3_ERR_IRQ_PRIO, \
.int_src = INT_SRC_SPI3_SPEI, \
}, \
#define SPI3_BUS_CONFIG \
{ \
.Instance = CM_SPI3, \
.bus_name = "spi3", \
.clock = FCG1_PERIPH_SPI3, \
.timeout = 5000UL, \
.err_irq.irq_config = { \
.irq_num = BSP_SPI3_ERR_IRQ_NUM, \
.irq_prio = BSP_SPI3_ERR_IRQ_PRIO, \
.int_src = INT_SRC_SPI3_SPEI, \
}, \
}
#endif /* SPI3_BUS_CONFIG */
#endif /* BSP_USING_SPI3 */
@ -157,40 +150,38 @@ extern "C" {
#ifdef BSP_SPI3_TX_USING_DMA
#ifndef SPI3_TX_DMA_CONFIG
#define SPI3_TX_DMA_CONFIG \
{ \
.Instance = SPI3_TX_DMA_INSTANCE, \
.channel = SPI3_TX_DMA_CHANNEL, \
.clock = SPI3_TX_DMA_CLOCK, \
.trigger_select = SPI3_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI3_SPTI, \
.flag = SPI3_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = SPI3_TX_DMA_IRQn, \
.irq_prio = SPI3_TX_DMA_INT_PRIO, \
.int_src = SPI3_TX_DMA_INT_SRC, \
} \
#define SPI3_TX_DMA_CONFIG \
{ \
.Instance = SPI3_TX_DMA_INSTANCE, \
.channel = SPI3_TX_DMA_CHANNEL, \
.clock = SPI3_TX_DMA_CLOCK, \
.trigger_select = SPI3_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI3_SPTI, \
.flag = SPI3_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = SPI3_TX_DMA_IRQn, \
.irq_prio = SPI3_TX_DMA_INT_PRIO, \
.int_src = SPI3_TX_DMA_INT_SRC, \
} \
}
#endif /* SPI3_TX_DMA_CONFIG */
#endif /* BSP_SPI3_TX_USING_DMA */
#ifdef BSP_SPI3_RX_USING_DMA
#ifndef SPI3_RX_DMA_CONFIG
#define SPI3_RX_DMA_CONFIG \
{ \
.Instance = SPI3_RX_DMA_INSTANCE, \
.channel = SPI3_RX_DMA_CHANNEL, \
.clock = SPI3_RX_DMA_CLOCK, \
.trigger_select = SPI3_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI3_SPRI, \
.flag = SPI3_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = SPI3_RX_DMA_IRQn, \
.irq_prio = SPI3_RX_DMA_INT_PRIO, \
.int_src = SPI3_RX_DMA_INT_SRC, \
} \
#define SPI3_RX_DMA_CONFIG \
{ \
.Instance = SPI3_RX_DMA_INSTANCE, \
.channel = SPI3_RX_DMA_CHANNEL, \
.clock = SPI3_RX_DMA_CLOCK, \
.trigger_select = SPI3_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI3_SPRI, \
.flag = SPI3_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = SPI3_RX_DMA_IRQn, \
.irq_prio = SPI3_RX_DMA_INT_PRIO, \
.int_src = SPI3_RX_DMA_INT_SRC, \
} \
}
#endif /* SPI3_RX_DMA_CONFIG */
#endif /* BSP_SPI3_RX_USING_DMA */

125
bsp/hc32/ev_hc32f448_lqfp80/board/config/timer_config.h
View File

@ -20,95 +20,90 @@ extern "C" {
#ifdef BSP_USING_TMRA_1
#ifndef TMRA_1_CONFIG
#define TMRA_1_CONFIG \
{ \
.tmr_handle = CM_TMRA_1, \
.clock_source = CLK_BUS_PCLK0, \
.clock = FCG2_PERIPH_TMRA_1, \
.flag = TMRA_FLAG_OVF, \
.isr = \
{ \
.enIntSrc = INT_SRC_TMRA_1_OVF, \
.enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \
}, \
.name = "tmra_1" \
#define TMRA_1_CONFIG \
{ \
.tmr_handle = CM_TMRA_1, \
.clock_source = CLK_BUS_PCLK0, \
.clock = FCG2_PERIPH_TMRA_1, \
.flag = TMRA_FLAG_OVF, \
.isr = { \
.enIntSrc = INT_SRC_TMRA_1_OVF, \
.enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \
}, \
.name = "tmra_1" \
}
#endif /* TMRA_1_CONFIG */
#endif /* BSP_USING_TMRA_1 */
#ifdef BSP_USING_TMRA_2
#ifndef TMRA_2_CONFIG
#define TMRA_2_CONFIG \
{ \
.tmr_handle = CM_TMRA_2, \
.clock_source = CLK_BUS_PCLK0, \
.clock = FCG2_PERIPH_TMRA_2, \
.flag = TMRA_FLAG_OVF, \
.isr = \
{ \
.enIntSrc = INT_SRC_TMRA_2_OVF, \
.enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \
}, \
.name = "tmra_2" \
#define TMRA_2_CONFIG \
{ \
.tmr_handle = CM_TMRA_2, \
.clock_source = CLK_BUS_PCLK0, \
.clock = FCG2_PERIPH_TMRA_2, \
.flag = TMRA_FLAG_OVF, \
.isr = { \
.enIntSrc = INT_SRC_TMRA_2_OVF, \
.enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \
}, \
.name = "tmra_2" \
}
#endif /* TMRA_2_CONFIG */
#endif /* BSP_USING_TMRA_2 */
#ifdef BSP_USING_TMRA_3
#ifndef TMRA_3_CONFIG
#define TMRA_3_CONFIG \
{ \
.tmr_handle = CM_TMRA_3, \
.clock_source = CLK_BUS_PCLK0, \
.clock = FCG2_PERIPH_TMRA_3, \
.flag = TMRA_FLAG_OVF, \
.isr = \
{ \
.enIntSrc = INT_SRC_TMRA_3_OVF, \
.enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \
}, \
.name = "tmra_3" \
#define TMRA_3_CONFIG \
{ \
.tmr_handle = CM_TMRA_3, \
.clock_source = CLK_BUS_PCLK0, \
.clock = FCG2_PERIPH_TMRA_3, \
.flag = TMRA_FLAG_OVF, \
.isr = { \
.enIntSrc = INT_SRC_TMRA_3_OVF, \
.enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \
}, \
.name = "tmra_3" \
}
#endif /* TMRA_3_CONFIG */
#endif /* BSP_USING_TMRA_3 */
#ifdef BSP_USING_TMRA_4
#ifndef TMRA_4_CONFIG
#define TMRA_4_CONFIG \
{ \
.tmr_handle = CM_TMRA_4, \
.clock_source = CLK_BUS_PCLK0, \
.clock = FCG2_PERIPH_TMRA_4, \
.flag = TMRA_FLAG_OVF, \
.isr = \
{ \
.enIntSrc = INT_SRC_TMRA_4_OVF, \
.enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \
}, \
.name = "tmra_4" \
#define TMRA_4_CONFIG \
{ \
.tmr_handle = CM_TMRA_4, \
.clock_source = CLK_BUS_PCLK0, \
.clock = FCG2_PERIPH_TMRA_4, \
.flag = TMRA_FLAG_OVF, \
.isr = { \
.enIntSrc = INT_SRC_TMRA_4_OVF, \
.enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \
}, \
.name = "tmra_4" \
}
#endif /* TMRA_4_CONFIG */
#endif /* BSP_USING_TMRA_4 */
#ifdef BSP_USING_TMRA_5
#ifndef TMRA_5_CONFIG
#define TMRA_5_CONFIG \
{ \
.tmr_handle = CM_TMRA_5, \
.clock_source = CLK_BUS_PCLK1, \
.clock = FCG2_PERIPH_TMRA_5, \
.flag = TMRA_FLAG_OVF, \
.isr = \
{ \
.enIntSrc = INT_SRC_TMRA_5_OVF, \
.enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \
}, \
.name = "tmra_5" \
#define TMRA_5_CONFIG \
{ \
.tmr_handle = CM_TMRA_5, \
.clock_source = CLK_BUS_PCLK1, \
.clock = FCG2_PERIPH_TMRA_5, \
.flag = TMRA_FLAG_OVF, \
.isr = { \
.enIntSrc = INT_SRC_TMRA_5_OVF, \
.enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \
}, \
.name = "tmra_5" \
}
#endif /* TMRA_5_CONFIG */
#endif /* BSP_USING_TMRA_5 */

48
bsp/hc32/ev_hc32f448_lqfp80/board/config/tmr_capture_config.h
View File

@ -17,34 +17,34 @@
extern "C" {
#endif
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1)
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1)
#define IC1_NAME "ic1"
#define INPUT_CAPTURE_CFG_TMR6_1 \
{ \
.name = IC1_NAME, \
.ch = TMR6_CH_A, \
.clk_div = TMR6_CLK_DIV32, \
.first_edge = TMR6_CAPT_COND_PWMA_RISING, \
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \
}
#define INPUT_CAPTURE_CFG_TMR6_1 \
{ \
.name = IC1_NAME, \
.ch = TMR6_CH_A, \
.clk_div = TMR6_CLK_DIV32, \
.first_edge = TMR6_CAPT_COND_PWMA_RISING, \
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \
}
#endif
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2)
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2)
#define IC2_NAME "ic2"
#define INPUT_CAPTURE_CFG_TMR6_2 \
{ \
.name = IC2_NAME, \
.ch = TMR6_CH_A, \
.clk_div = TMR6_CLK_DIV32, \
.first_edge = TMR6_CAPT_COND_TRIGB_RISING, \
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \
}
#define INPUT_CAPTURE_CFG_TMR6_2 \
{ \
.name = IC2_NAME, \
.ch = TMR6_CH_A, \
.clk_div = TMR6_CLK_DIV32, \
.first_edge = TMR6_CAPT_COND_TRIGB_RISING, \
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \
}
#endif
#ifdef __cplusplus

522
bsp/hc32/ev_hc32f448_lqfp80/board/config/uart_config.h
View File

@ -22,90 +22,86 @@ extern "C" {
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = CM_USART1, \
.clock = FCG3_PERIPH_USART1, \
.irq_num = BSP_UART1_IRQ_NUM, \
.rxerr_int_src = INT_SRC_USART1_EI, \
.rx_int_src = INT_SRC_USART1_RI, \
.tx_int_src = INT_SRC_USART1_TI, \
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = CM_USART1, \
.clock = FCG3_PERIPH_USART1, \
.irq_num = BSP_UART1_IRQ_NUM, \
.rxerr_int_src = INT_SRC_USART1_EI, \
.rx_int_src = INT_SRC_USART1_RI, \
.tx_int_src = INT_SRC_USART1_TI, \
}
#endif /* UART1_CONFIG */
#if defined(BSP_UART1_RX_USING_DMA)
#ifndef UART1_DMA_RX_CONFIG
#define UART1_DMA_RX_CONFIG \
{ \
.Instance = UART1_RX_DMA_INSTANCE, \
.channel = UART1_RX_DMA_CHANNEL, \
.clock = UART1_RX_DMA_CLOCK, \
.trigger_select = UART1_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART1_RI, \
.flag = UART1_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = UART1_RX_DMA_IRQn, \
.irq_prio = UART1_RX_DMA_INT_PRIO, \
.int_src = UART1_RX_DMA_INT_SRC, \
}, \
#define UART1_DMA_RX_CONFIG \
{ \
.Instance = UART1_RX_DMA_INSTANCE, \
.channel = UART1_RX_DMA_CHANNEL, \
.clock = UART1_RX_DMA_CLOCK, \
.trigger_select = UART1_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART1_RI, \
.flag = UART1_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = UART1_RX_DMA_IRQn, \
.irq_prio = UART1_RX_DMA_INT_PRIO, \
.int_src = UART1_RX_DMA_INT_SRC, \
}, \
}
#endif /* UART1_DMA_RX_CONFIG */
#ifndef UART1_RXTO_CONFIG
#define UART1_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_1, \
.channel = TMR0_CH_A, \
.clock = FCG2_PERIPH_TMR0_1, \
.timeout_bits = 20UL, \
#define UART1_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_1, \
.channel = TMR0_CH_A, \
.clock = FCG2_PERIPH_TMR0_1, \
.timeout_bits = 20UL, \
}
#endif /* UART1_RXTO_CONFIG */
#endif /* BSP_UART1_RX_USING_DMA */
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)
#ifndef UART1_TX_CPLT_CONFIG
#define UART1_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART1_TCI, \
}, \
#define UART1_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART1_TCI, \
}, \
}
#endif
#elif defined(RT_USING_SERIAL_V2)
#ifndef UART1_TX_CPLT_CONFIG
#define UART1_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART1_TCI, \
}, \
#define UART1_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART1_TCI, \
}, \
}
#endif
#endif /* UART1_TX_CPLT_CONFIG */
#if defined(BSP_UART1_TX_USING_DMA)
#ifndef UART1_DMA_TX_CONFIG
#define UART1_DMA_TX_CONFIG \
{ \
.Instance = UART1_TX_DMA_INSTANCE, \
.channel = UART1_TX_DMA_CHANNEL, \
.clock = UART1_TX_DMA_CLOCK, \
.trigger_select = UART1_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART1_TI, \
.flag = UART1_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = UART1_TX_DMA_IRQn, \
.irq_prio = UART1_TX_DMA_INT_PRIO, \
.int_src = UART1_TX_DMA_INT_SRC, \
}, \
#define UART1_DMA_TX_CONFIG \
{ \
.Instance = UART1_TX_DMA_INSTANCE, \
.channel = UART1_TX_DMA_CHANNEL, \
.clock = UART1_TX_DMA_CLOCK, \
.trigger_select = UART1_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART1_TI, \
.flag = UART1_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = UART1_TX_DMA_IRQn, \
.irq_prio = UART1_TX_DMA_INT_PRIO, \
.int_src = UART1_TX_DMA_INT_SRC, \
}, \
}
#endif /* UART1_DMA_TX_CONFIG */
#endif /* BSP_UART1_TX_USING_DMA */
@ -113,90 +109,86 @@ extern "C" {
#if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = CM_USART2, \
.clock = FCG3_PERIPH_USART2, \
.irq_num = BSP_UART2_IRQ_NUM, \
.rxerr_int_src = INT_SRC_USART2_EI, \
.rx_int_src = INT_SRC_USART2_RI, \
.tx_int_src = INT_SRC_USART2_TI, \
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = CM_USART2, \
.clock = FCG3_PERIPH_USART2, \
.irq_num = BSP_UART2_IRQ_NUM, \
.rxerr_int_src = INT_SRC_USART2_EI, \
.rx_int_src = INT_SRC_USART2_RI, \
.tx_int_src = INT_SRC_USART2_TI, \
}
#endif /* UART2_CONFIG */
#if defined(BSP_UART2_RX_USING_DMA)
#ifndef UART2_DMA_RX_CONFIG
#define UART2_DMA_RX_CONFIG \
{ \
.Instance = UART2_RX_DMA_INSTANCE, \
.channel = UART2_RX_DMA_CHANNEL, \
.clock = UART2_RX_DMA_CLOCK, \
.trigger_select = UART2_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART2_RI, \
.flag = UART2_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = UART2_RX_DMA_IRQn, \
.irq_prio = UART2_RX_DMA_INT_PRIO, \
.int_src = UART2_RX_DMA_INT_SRC, \
}, \
#define UART2_DMA_RX_CONFIG \
{ \
.Instance = UART2_RX_DMA_INSTANCE, \
.channel = UART2_RX_DMA_CHANNEL, \
.clock = UART2_RX_DMA_CLOCK, \
.trigger_select = UART2_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART2_RI, \
.flag = UART2_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = UART2_RX_DMA_IRQn, \
.irq_prio = UART2_RX_DMA_INT_PRIO, \
.int_src = UART2_RX_DMA_INT_SRC, \
}, \
}
#endif /* UART2_DMA_RX_CONFIG */
#ifndef UART2_RXTO_CONFIG
#define UART2_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_1, \
.channel = TMR0_CH_B, \
.clock = FCG2_PERIPH_TMR0_1, \
.timeout_bits = 20UL, \
#define UART2_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_1, \
.channel = TMR0_CH_B, \
.clock = FCG2_PERIPH_TMR0_1, \
.timeout_bits = 20UL, \
}
#endif /* UART2_RXTO_CONFIG */
#endif /* BSP_UART2_RX_USING_DMA */
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)
#ifndef UART2_TX_CPLT_CONFIG
#define UART2_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART2_TCI, \
}, \
#define UART2_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART2_TCI, \
}, \
}
#endif
#elif defined(RT_USING_SERIAL_V2)
#ifndef UART2_TX_CPLT_CONFIG
#define UART2_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART2_TCI, \
}, \
#define UART2_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART2_TCI, \
}, \
}
#endif
#endif /* UART2_TX_CPLT_CONFIG */
#if defined(BSP_UART2_TX_USING_DMA)
#ifndef UART2_DMA_TX_CONFIG
#define UART2_DMA_TX_CONFIG \
{ \
.Instance = UART2_TX_DMA_INSTANCE, \
.channel = UART2_TX_DMA_CHANNEL, \
.clock = UART2_TX_DMA_CLOCK, \
.trigger_select = UART2_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART2_TI, \
.flag = UART2_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = UART2_TX_DMA_IRQn, \
.irq_prio = UART2_TX_DMA_INT_PRIO, \
.int_src = UART2_TX_DMA_INT_SRC, \
}, \
#define UART2_DMA_TX_CONFIG \
{ \
.Instance = UART2_TX_DMA_INSTANCE, \
.channel = UART2_TX_DMA_CHANNEL, \
.clock = UART2_TX_DMA_CLOCK, \
.trigger_select = UART2_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART2_TI, \
.flag = UART2_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = UART2_TX_DMA_IRQn, \
.irq_prio = UART2_TX_DMA_INT_PRIO, \
.int_src = UART2_TX_DMA_INT_SRC, \
}, \
}
#endif /* UART2_DMA_TX_CONFIG */
#endif /* BSP_UART2_TX_USING_DMA */
@ -204,28 +196,27 @@ extern "C" {
#if defined(BSP_USING_UART3)
#ifndef UART3_CONFIG
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = CM_USART3, \
.clock = FCG3_PERIPH_USART3, \
.irq_num = BSP_UART3_IRQ_NUM, \
.rxerr_int_src = INT_SRC_USART3_EI, \
.rx_int_src = INT_SRC_USART3_RI, \
.tx_int_src = INT_SRC_USART3_TI, \
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = CM_USART3, \
.clock = FCG3_PERIPH_USART3, \
.irq_num = BSP_UART3_IRQ_NUM, \
.rxerr_int_src = INT_SRC_USART3_EI, \
.rx_int_src = INT_SRC_USART3_RI, \
.tx_int_src = INT_SRC_USART3_TI, \
}
#endif /* UART3_CONFIG */
#if defined(RT_USING_SERIAL_V2)
#ifndef UART3_TX_CPLT_CONFIG
#define UART3_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART3_TCI, \
}, \
#define UART3_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART3_TCI, \
}, \
}
#endif
#endif /* UART3_TX_CPLT_CONFIG */
@ -233,90 +224,86 @@ extern "C" {
#if defined(BSP_USING_UART4)
#ifndef UART4_CONFIG
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = CM_USART4, \
.clock = FCG3_PERIPH_USART4, \
.irq_num = BSP_UART4_IRQ_NUM, \
.rxerr_int_src = INT_SRC_USART4_EI, \
.rx_int_src = INT_SRC_USART4_RI, \
.tx_int_src = INT_SRC_USART4_TI, \
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = CM_USART4, \
.clock = FCG3_PERIPH_USART4, \
.irq_num = BSP_UART4_IRQ_NUM, \
.rxerr_int_src = INT_SRC_USART4_EI, \
.rx_int_src = INT_SRC_USART4_RI, \
.tx_int_src = INT_SRC_USART4_TI, \
}
#endif /* UART4_CONFIG */
#if defined(BSP_UART4_RX_USING_DMA)
#ifndef UART4_DMA_RX_CONFIG
#define UART4_DMA_RX_CONFIG \
{ \
.Instance = UART4_RX_DMA_INSTANCE, \
.channel = UART4_RX_DMA_CHANNEL, \
.clock = UART4_RX_DMA_CLOCK, \
.trigger_select = UART4_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART4_RI, \
.flag = UART4_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = UART4_RX_DMA_IRQn, \
.irq_prio = UART4_RX_DMA_INT_PRIO, \
.int_src = UART4_RX_DMA_INT_SRC, \
}, \
#define UART4_DMA_RX_CONFIG \
{ \
.Instance = UART4_RX_DMA_INSTANCE, \
.channel = UART4_RX_DMA_CHANNEL, \
.clock = UART4_RX_DMA_CLOCK, \
.trigger_select = UART4_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART4_RI, \
.flag = UART4_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = UART4_RX_DMA_IRQn, \
.irq_prio = UART4_RX_DMA_INT_PRIO, \
.int_src = UART4_RX_DMA_INT_SRC, \
}, \
}
#endif /* UART4_DMA_RX_CONFIG */
#ifndef UART4_RXTO_CONFIG
#define UART4_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_2, \
.channel = TMR0_CH_A, \
.clock = FCG2_PERIPH_TMR0_2, \
.timeout_bits = 20UL, \
#define UART4_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_2, \
.channel = TMR0_CH_A, \
.clock = FCG2_PERIPH_TMR0_2, \
.timeout_bits = 20UL, \
}
#endif /* UART4_RXTO_CONFIG */
#endif /* BSP_UART4_RX_USING_DMA */
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)
#ifndef UART4_TX_CPLT_CONFIG
#define UART4_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART4_TCI, \
}, \
#define UART4_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART4_TCI, \
}, \
}
#endif
#elif defined(RT_USING_SERIAL_V2)
#ifndef UART4_TX_CPLT_CONFIG
#define UART4_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART4_TCI, \
}, \
#define UART4_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART4_TCI, \
}, \
}
#endif
#endif /* UART4_TX_CPLT_CONFIG */
#if defined(BSP_UART4_TX_USING_DMA)
#ifndef UART4_DMA_TX_CONFIG
#define UART4_DMA_TX_CONFIG \
{ \
.Instance = UART4_TX_DMA_INSTANCE, \
.channel = UART4_TX_DMA_CHANNEL, \
.clock = UART4_TX_DMA_CLOCK, \
.trigger_select = UART4_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART4_TI, \
.flag = UART4_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = UART4_TX_DMA_IRQn, \
.irq_prio = UART4_TX_DMA_INT_PRIO, \
.int_src = UART4_TX_DMA_INT_SRC, \
}, \
#define UART4_DMA_TX_CONFIG \
{ \
.Instance = UART4_TX_DMA_INSTANCE, \
.channel = UART4_TX_DMA_CHANNEL, \
.clock = UART4_TX_DMA_CLOCK, \
.trigger_select = UART4_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART4_TI, \
.flag = UART4_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = UART4_TX_DMA_IRQn, \
.irq_prio = UART4_TX_DMA_INT_PRIO, \
.int_src = UART4_TX_DMA_INT_SRC, \
}, \
}
#endif /* UART4_DMA_TX_CONFIG */
#endif /* BSP_UART4_TX_USING_DMA */
@ -324,90 +311,86 @@ extern "C" {
#if defined(BSP_USING_UART5)
#ifndef UART5_CONFIG
#define UART5_CONFIG \
{ \
.name = "uart5", \
.Instance = CM_USART5, \
.clock = FCG3_PERIPH_USART5, \
.irq_num = BSP_UART5_IRQ_NUM, \
.rxerr_int_src = INT_SRC_USART5_EI, \
.rx_int_src = INT_SRC_USART5_RI, \
.tx_int_src = INT_SRC_USART5_TI, \
#define UART5_CONFIG \
{ \
.name = "uart5", \
.Instance = CM_USART5, \
.clock = FCG3_PERIPH_USART5, \
.irq_num = BSP_UART5_IRQ_NUM, \
.rxerr_int_src = INT_SRC_USART5_EI, \
.rx_int_src = INT_SRC_USART5_RI, \
.tx_int_src = INT_SRC_USART5_TI, \
}
#endif /* UART5_CONFIG */
#if defined(BSP_UART5_RX_USING_DMA)
#ifndef UART5_DMA_RX_CONFIG
#define UART5_DMA_RX_CONFIG \
{ \
.Instance = UART5_RX_DMA_INSTANCE, \
.channel = UART5_RX_DMA_CHANNEL, \
.clock = UART5_RX_DMA_CLOCK, \
.trigger_select = UART5_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART5_RI, \
.flag = UART5_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = UART5_RX_DMA_IRQn, \
.irq_prio = UART5_RX_DMA_INT_PRIO, \
.int_src = UART5_RX_DMA_INT_SRC, \
}, \
#define UART5_DMA_RX_CONFIG \
{ \
.Instance = UART5_RX_DMA_INSTANCE, \
.channel = UART5_RX_DMA_CHANNEL, \
.clock = UART5_RX_DMA_CLOCK, \
.trigger_select = UART5_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART5_RI, \
.flag = UART5_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = UART5_RX_DMA_IRQn, \
.irq_prio = UART5_RX_DMA_INT_PRIO, \
.int_src = UART5_RX_DMA_INT_SRC, \
}, \
}
#endif /* UART5_DMA_RX_CONFIG */
#ifndef UART5_RXTO_CONFIG
#define UART5_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_2, \
.channel = TMR0_CH_B, \
.clock = FCG2_PERIPH_TMR0_2, \
.timeout_bits = 20UL, \
#define UART5_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_2, \
.channel = TMR0_CH_B, \
.clock = FCG2_PERIPH_TMR0_2, \
.timeout_bits = 20UL, \
}
#endif /* UART5_RXTO_CONFIG */
#endif /* BSP_UART5_RX_USING_DMA */
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART5_TX_USING_DMA)
#ifndef UART5_TX_CPLT_CONFIG
#define UART5_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART5_TCI, \
}, \
#define UART5_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART5_TCI, \
}, \
}
#endif
#elif defined(RT_USING_SERIAL_V2)
#ifndef UART5_TX_CPLT_CONFIG
#define UART5_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART5_TCI, \
}, \
#define UART5_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART5_TCI, \
}, \
}
#endif
#endif /* UART5_TX_CPLT_CONFIG */
#if defined(BSP_UART5_TX_USING_DMA)
#ifndef UART5_DMA_TX_CONFIG
#define UART5_DMA_TX_CONFIG \
{ \
.Instance = UART5_TX_DMA_INSTANCE, \
.channel = UART5_TX_DMA_CHANNEL, \
.clock = UART5_TX_DMA_CLOCK, \
.trigger_select = UART5_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART5_TI, \
.flag = UART5_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = UART5_TX_DMA_IRQn, \
.irq_prio = UART5_TX_DMA_INT_PRIO, \
.int_src = UART5_TX_DMA_INT_SRC, \
}, \
#define UART5_DMA_TX_CONFIG \
{ \
.Instance = UART5_TX_DMA_INSTANCE, \
.channel = UART5_TX_DMA_CHANNEL, \
.clock = UART5_TX_DMA_CLOCK, \
.trigger_select = UART5_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART5_TI, \
.flag = UART5_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = UART5_TX_DMA_IRQn, \
.irq_prio = UART5_TX_DMA_INT_PRIO, \
.int_src = UART5_TX_DMA_INT_SRC, \
}, \
}
#endif /* UART5_DMA_TX_CONFIG */
#endif /* BSP_UART5_TX_USING_DMA */
@ -415,28 +398,27 @@ extern "C" {
#if defined(BSP_USING_UART6)
#ifndef UART6_CONFIG
#define UART6_CONFIG \
{ \
.name = "uart6", \
.Instance = CM_USART6, \
.clock = FCG3_PERIPH_USART6, \
.irq_num = BSP_UART6_IRQ_NUM, \
.rxerr_int_src = INT_SRC_USART6_EI, \
.rx_int_src = INT_SRC_USART6_RI, \
.tx_int_src = INT_SRC_USART6_TI, \
#define UART6_CONFIG \
{ \
.name = "uart6", \
.Instance = CM_USART6, \
.clock = FCG3_PERIPH_USART6, \
.irq_num = BSP_UART6_IRQ_NUM, \
.rxerr_int_src = INT_SRC_USART6_EI, \
.rx_int_src = INT_SRC_USART6_RI, \
.tx_int_src = INT_SRC_USART6_TI, \
}
#endif /* UART6_CONFIG */
#if defined(RT_USING_SERIAL_V2)
#ifndef UART6_TX_CPLT_CONFIG
#define UART6_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART6_TCI, \
}, \
#define UART6_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART6_TCI, \
}, \
}
#endif
#endif /* UART6_TX_CPLT_CONFIG */

103
bsp/hc32/ev_hc32f448_lqfp80/board/hc32f4xx_conf.h
View File

@ -27,8 +27,7 @@
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
extern "C" {
#endif
/*******************************************************************************
@ -48,53 +47,53 @@ extern "C"
* Library.
* @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function.
*/
#define LL_ICG_ENABLE (DDL_ON)
#define LL_UTILITY_ENABLE (DDL_ON)
#define LL_PRINT_ENABLE (DDL_OFF)
#define LL_ICG_ENABLE (DDL_ON)
#define LL_UTILITY_ENABLE (DDL_ON)
#define LL_PRINT_ENABLE (DDL_OFF)
#define LL_ADC_ENABLE (DDL_ON)
#define LL_AES_ENABLE (DDL_ON)
#define LL_AOS_ENABLE (DDL_ON)
#define LL_CLK_ENABLE (DDL_ON)
#define LL_CMP_ENABLE (DDL_ON)
#define LL_CRC_ENABLE (DDL_ON)
#define LL_CTC_ENABLE (DDL_ON)
#define LL_DAC_ENABLE (DDL_ON)
#define LL_DBGC_ENABLE (DDL_OFF)
#define LL_DCU_ENABLE (DDL_ON)
#define LL_DMA_ENABLE (DDL_ON)
#define LL_EFM_ENABLE (DDL_ON)
#define LL_EMB_ENABLE (DDL_ON)
#define LL_EVENT_PORT_ENABLE (DDL_OFF)
#define LL_FCG_ENABLE (DDL_ON)
#define LL_FCM_ENABLE (DDL_ON)
#define LL_GPIO_ENABLE (DDL_ON)
#define LL_HASH_ENABLE (DDL_ON)
#define LL_I2C_ENABLE (DDL_ON)
#define LL_INTERRUPTS_ENABLE (DDL_ON)
#define LL_KEYSCAN_ENABLE (DDL_ON)
#define LL_MCAN_ENABLE (DDL_ON)
#define LL_MPU_ENABLE (DDL_ON)
#define LL_PWC_ENABLE (DDL_ON)
#define LL_QSPI_ENABLE (DDL_ON)
#define LL_RMU_ENABLE (DDL_ON)
#define LL_RTC_ENABLE (DDL_ON)
#define LL_SMC_ENABLE (DDL_ON)
#define LL_SPI_ENABLE (DDL_ON)
#define LL_SRAM_ENABLE (DDL_ON)
#define LL_SWDT_ENABLE (DDL_ON)
#define LL_TMR0_ENABLE (DDL_ON)
#define LL_TMR4_ENABLE (DDL_ON)
#define LL_TMR6_ENABLE (DDL_ON)
#define LL_TMRA_ENABLE (DDL_ON)
#define LL_TRNG_ENABLE (DDL_ON)
#define LL_USART_ENABLE (DDL_ON)
#define LL_WDT_ENABLE (DDL_ON)
#define LL_ADC_ENABLE (DDL_ON)
#define LL_AES_ENABLE (DDL_ON)
#define LL_AOS_ENABLE (DDL_ON)
#define LL_CLK_ENABLE (DDL_ON)
#define LL_CMP_ENABLE (DDL_ON)
#define LL_CRC_ENABLE (DDL_ON)
#define LL_CTC_ENABLE (DDL_ON)
#define LL_DAC_ENABLE (DDL_ON)
#define LL_DBGC_ENABLE (DDL_OFF)
#define LL_DCU_ENABLE (DDL_ON)
#define LL_DMA_ENABLE (DDL_ON)
#define LL_EFM_ENABLE (DDL_ON)
#define LL_EMB_ENABLE (DDL_ON)
#define LL_EVENT_PORT_ENABLE (DDL_OFF)
#define LL_FCG_ENABLE (DDL_ON)
#define LL_FCM_ENABLE (DDL_ON)
#define LL_GPIO_ENABLE (DDL_ON)
#define LL_HASH_ENABLE (DDL_ON)
#define LL_I2C_ENABLE (DDL_ON)
#define LL_INTERRUPTS_ENABLE (DDL_ON)
#define LL_KEYSCAN_ENABLE (DDL_ON)
#define LL_MCAN_ENABLE (DDL_ON)
#define LL_MPU_ENABLE (DDL_ON)
#define LL_PWC_ENABLE (DDL_ON)
#define LL_QSPI_ENABLE (DDL_ON)
#define LL_RMU_ENABLE (DDL_ON)
#define LL_RTC_ENABLE (DDL_ON)
#define LL_SMC_ENABLE (DDL_ON)
#define LL_SPI_ENABLE (DDL_ON)
#define LL_SRAM_ENABLE (DDL_ON)
#define LL_SWDT_ENABLE (DDL_ON)
#define LL_TMR0_ENABLE (DDL_ON)
#define LL_TMR4_ENABLE (DDL_ON)
#define LL_TMR6_ENABLE (DDL_ON)
#define LL_TMRA_ENABLE (DDL_ON)
#define LL_TRNG_ENABLE (DDL_ON)
#define LL_USART_ENABLE (DDL_ON)
#define LL_WDT_ENABLE (DDL_ON)
/**
* @brief The following is a list of currently supported BSP boards.
*/
#define BSP_EV_HC32F448_LQFP80 (9U)
#define BSP_EV_HC32F448_LQFP80 (9U)
/**
* @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently
@ -103,19 +102,19 @@ extern "C"
* @note If there is no supported BSP board or the BSP function is not used,
* the value needs to be set to 0U.
*/
#define BSP_EV_HC32F4XX (0U)
#define BSP_EV_HC32F4XX (0U)
/**
* @brief This is the list of BSP components to be used.
* Select the components you need to use to DDL_ON.
*/
#define BSP_24CXX_ENABLE (DDL_OFF)
#define BSP_GT9XX_ENABLE (DDL_OFF)
#define BSP_IS61LV6416_ENABLE (DDL_OFF)
#define BSP_NT35510_ENABLE (DDL_OFF)
#define BSP_TCA9539_ENABLE (DDL_OFF)
#define BSP_W25QXX_ENABLE (DDL_OFF)
#define BSP_INT_KEY_ENABLE (DDL_OFF)
#define BSP_24CXX_ENABLE (DDL_OFF)
#define BSP_GT9XX_ENABLE (DDL_OFF)
#define BSP_IS61LV6416_ENABLE (DDL_OFF)
#define BSP_NT35510_ENABLE (DDL_OFF)
#define BSP_TCA9539_ENABLE (DDL_OFF)
#define BSP_W25QXX_ENABLE (DDL_OFF)
#define BSP_INT_KEY_ENABLE (DDL_OFF)
/*******************************************************************************
* Global variable definitions ('extern')

20
bsp/hc32/ev_hc32f448_lqfp80/board/ports/fal_cfg.h
View File

@ -24,20 +24,20 @@ extern const struct fal_flash_dev hc32_onchip_flash;
extern struct fal_flash_dev ext_nor_flash0;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&hc32_onchip_flash, \
&ext_nor_flash0, \
}
#define FAL_FLASH_DEV_TABLE \
{ \
&hc32_onchip_flash, \
&ext_nor_flash0, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 256 * 1024, 0}, \
{FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0}, \
}
#define FAL_PART_TABLE \
{ \
{ FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 256 * 1024, 0 }, \
{ FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0 }, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#endif /* _FAL_CFG_H_ */

42
bsp/hc32/ev_hc32f448_lqfp80/board/ports/tca9539_port.h
View File

@ -17,18 +17,18 @@
* @defgroup HC32F448_EV_IO_Function_Sel Expand IO function definition
* @{
*/
#define EIO_SCI_CD (TCA9539_IO_PIN1) /* Smart card detect, input */
#define EIO_TOUCH_INT (TCA9539_IO_PIN2) /* Touch screen interrupt, input */
#define EIO_TOUCH_CTRST (TCA9539_IO_PIN5) /* 'Reset' for Cap touch panel, output */
#define EIO_LCD_RST (TCA9539_IO_PIN6) /* LCD panel reset, output */
#define EIO_LCD_BKL (TCA9539_IO_PIN7) /* LCD panel back light, output */
#define EIO_SCI_CD (TCA9539_IO_PIN1) /* Smart card detect, input */
#define EIO_TOUCH_INT (TCA9539_IO_PIN2) /* Touch screen interrupt, input */
#define EIO_TOUCH_CTRST (TCA9539_IO_PIN5) /* 'Reset' for Cap touch panel, output */
#define EIO_LCD_RST (TCA9539_IO_PIN6) /* LCD panel reset, output */
#define EIO_LCD_BKL (TCA9539_IO_PIN7) /* LCD panel back light, output */
#define EIO_LIN_SLEEP (TCA9539_IO_PIN1) /* LIN PHY sleep, output */
#define EIO_CAN1_STB (TCA9539_IO_PIN2) /* CAN1 PHY standby, output */
#define EIO_CAN2_STB (TCA9539_IO_PIN3) /* CAN2 PHY standby, output */
#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */
#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */
#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */
#define EIO_LIN_SLEEP (TCA9539_IO_PIN1) /* LIN PHY sleep, output */
#define EIO_CAN1_STB (TCA9539_IO_PIN2) /* CAN1 PHY standby, output */
#define EIO_CAN2_STB (TCA9539_IO_PIN3) /* CAN2 PHY standby, output */
#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */
#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */
#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */
/**
* @}
*/
@ -37,12 +37,12 @@
* @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition
* @{
*/
#define LED_RED_PORT (TCA9539_IO_PORT1)
#define LED_RED_PIN (EIO_LED_RED)
#define LED_YELLOW_PORT (TCA9539_IO_PORT1)
#define LED_YELLOW_PIN (EIO_LED_YELLOW)
#define LED_BLUE_PORT (TCA9539_IO_PORT1)
#define LED_BLUE_PIN (EIO_LED_BLUE)
#define LED_RED_PORT (TCA9539_IO_PORT1)
#define LED_RED_PIN (EIO_LED_RED)
#define LED_YELLOW_PORT (TCA9539_IO_PORT1)
#define LED_YELLOW_PIN (EIO_LED_YELLOW)
#define LED_BLUE_PORT (TCA9539_IO_PORT1)
#define LED_BLUE_PIN (EIO_LED_BLUE)
/**
* @}
*/
@ -51,10 +51,10 @@
* @defgroup BSP CAN PHY STB port/pin definition
* @{
*/
#define CAN1_STB_PORT (TCA9539_IO_PORT1)
#define CAN1_STB_PIN (EIO_CAN1_STB)
#define CAN2_STB_PORT (TCA9539_IO_PORT1)
#define CAN2_STB_PIN (EIO_CAN2_STB)
#define CAN1_STB_PORT (TCA9539_IO_PORT1)
#define CAN1_STB_PIN (EIO_CAN1_STB)
#define CAN2_STB_PORT (TCA9539_IO_PORT1)
#define CAN2_STB_PIN (EIO_CAN2_STB)
/**
* @}
*/

24
bsp/hc32/ev_hc32f448_lqfp80/rtconfig.h
View File

@ -61,18 +61,18 @@
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 12
#define RT_CPUS_NR 1
#define RT_NAME_MAX 24
#define RT_CPUS_NR 1
#define RT_ALIGN_SIZE 8
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
#define IDLE_THREAD_STACK_SIZE 512
/* kservice options */
@ -100,10 +100,10 @@
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart2"
#define RT_USING_CONSOLE_OUTPUT_CTL
#define RT_VER_NUM 0x50300
#define RT_VER_NUM 0x50300
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
#define RT_USING_HW_ATOMIC
@ -119,12 +119,12 @@
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
@ -145,7 +145,7 @@
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
@ -163,8 +163,8 @@
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */

8
bsp/hc32/ev_hc32f460_lqfp100_v2/.ci/attachconfig/ci.attachconfig.yml
View File

@ -23,11 +23,11 @@ devices.flash:
- CONFIG_RT_USING_SPI=y
- CONFIG_RT_USING_SFUD=y
devices.gpio:
kconfig:
- CONFIG_BSP_USING_GPIO=y
devices.hwtimer:
kconfig:
- CONFIG_BSP_USING_HWTIMER=y
- CONFIG_BSP_USING_GPIO=y
devices.clock_timer:
kconfig:
- CONFIG_BSP_USING_CLOCK_TIMER=y
- CONFIG_BSP_USING_TMRA_1=y
devices.i2c:
kconfig:

2
bsp/hc32/ev_hc32f460_lqfp100_v2/.config
View File

@ -125,7 +125,7 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y
# CONFIG_RT_USING_HOOKLIST is not set
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
CONFIG_IDLE_THREAD_STACK_SIZE=512
# CONFIG_RT_USING_TIMER_SOFT is not set
# CONFIG_RT_USING_CPU_USAGE_TRACER is not set

2
bsp/hc32/ev_hc32f460_lqfp100_v2/README.md
View File

@ -46,7 +46,7 @@ EV_F460_LQ100_V2 开发板常用 **板载资源** 如下：
| Crypto | 支持 | CRC，HASH，RNG |
| FLASH | 支持 | |
| GPIO | 支持 | PA0，PA1... PH2 ---> PIN：0，1...82 |
| HwTimer | 支持 | |
| CLOCK_TIMER | 支持 | |
| I2C | 支持 | 软件、硬件 I2C |
| InputCapture | 支持 | |
| PM | 支持 | |

16
bsp/hc32/ev_hc32f460_lqfp100_v2/applications/xtal32_fcm.c
View File

@ -19,8 +19,8 @@
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
#define XTAL32_FCM_THREAD_STACK_SIZE (1024)
#define XTAL32_FCM_UNIT (CM_FCM)
#define XTAL32_FCM_THREAD_STACK_SIZE (1024)
#define XTAL32_FCM_UNIT (CM_FCM)
/**
* @brief This thread is used to monitor whether XTAL32 is stable.
@ -37,13 +37,13 @@ void xtal32_fcm_thread_entry(void *parameter)
/* FCM config */
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE);
(void)FCM_StructInit(&stcFcmInit);
stcFcmInit.u32RefClock = FCM_REF_CLK_MRC;
stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */
stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING;
stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32;
stcFcmInit.u32RefClock = FCM_REF_CLK_MRC;
stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */
stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING;
stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32;
stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1;
stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
(void)FCM_Init(XTAL32_FCM_UNIT, &stcFcmInit);
/* Enable FCM, to ensure xtal32 stable */
FCM_Cmd(XTAL32_FCM_UNIT, ENABLE);

14
bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig
View File

@ -637,27 +637,27 @@ menu "On-chip Peripheral Drivers"
endif
menuconfig BSP_USING_CLOCK_TIMER
bool "Enable Hw Timer"
bool "Enable Clock Timer"
default n
select RT_USING_CLOCK_TIME
if BSP_USING_CLOCK_TIMER
config BSP_USING_TMRA_1
bool "Use Timer_a1 As The Hw Timer"
bool "Use Timer_a1 As The Clock Timer"
default n
config BSP_USING_TMRA_2
bool "Use Timer_a2 As The Hw Timer"
bool "Use Timer_a2 As The Clock Timer"
default n
config BSP_USING_TMRA_3
bool "Use Timer_a3 As The Hw Timer"
bool "Use Timer_a3 As The Clock Timer"
default n
config BSP_USING_TMRA_4
bool "Use Timer_a4 As The Hw Timer"
bool "Use Timer_a4 As The Clock Timer"
default n
config BSP_USING_TMRA_5
bool "Use Timer_a5 As The Hw Timer"
bool "Use Timer_a5 As The Clock Timer"
default n
config BSP_USING_TMRA_6
bool "Use Timer_a6 As The Hw Timer"
bool "Use Timer_a6 As The Clock Timer"
default n
endif
menuconfig BSP_USING_INPUT_CAPTURE

20
bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.c
View File

@ -13,9 +13,9 @@
#include "board_config.h"
/* unlock/lock peripheral */
#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD)
#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM)
#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD)
#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM)
/** System Base Configuration
*/
@ -30,8 +30,8 @@ void SystemBase_Config(void)
*/
void SystemClock_Config(void)
{
stc_clock_xtal_init_t stcXtalInit;
stc_clock_pll_init_t stcMpllInit;
stc_clock_xtal_init_t stcXtalInit;
stc_clock_pll_init_t stcMpllInit;
#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB)
stc_clock_pllx_init_t stcUpllInit;
#endif
@ -43,14 +43,14 @@ void SystemClock_Config(void)
/* PCLK1, PCLK4 Max 100MHz */
/* PCLK2, PCLK3 Max 50MHz */
/* EX BUS Max 100MHz */
CLK_SetClockDiv(CLK_BUS_CLK_ALL, (CLK_HCLK_DIV1 | CLK_EXCLK_DIV2 | CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | \
CLK_SetClockDiv(CLK_BUS_CLK_ALL, (CLK_HCLK_DIV1 | CLK_EXCLK_DIV2 | CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 |
CLK_PCLK2_DIV4 | CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2));
GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE);
(void)CLK_XtalStructInit(&stcXtalInit);
/* Config Xtal and enable Xtal */
stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW;
stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW;
stcXtalInit.u8State = CLK_XTAL_ON;
stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
(void)CLK_XtalInit(&stcXtalInit);
@ -98,8 +98,8 @@ void SystemClock_Config(void)
/* Xtal32 config */
GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE);
(void)CLK_Xtal32StructInit(&stcXtal32Init);
stcXtal32Init.u8State = CLK_XTAL32_ON;
stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH;
stcXtal32Init.u8State = CLK_XTAL32_ON;
stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH;
stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD;
(void)CLK_Xtal32Init(&stcXtal32Init);
#endif

24
bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.h
View File

@ -20,27 +20,27 @@ extern "C" {
#endif
#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024)
#define HC32_FLASH_WRITE_GRANULARITY (4)
#define HC32_FLASH_SIZE (512 * 1024)
#define HC32_FLASH_START_ADDRESS (0)
#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024)
#define HC32_FLASH_WRITE_GRANULARITY (4)
#define HC32_FLASH_SIZE (512 * 1024)
#define HC32_FLASH_START_ADDRESS (0)
#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
#define HC32_SRAM_SIZE (188)
#define HC32_SRAM_END (0x1FFF8000 + HC32_SRAM_SIZE * 1024)
#define HC32_SRAM_SIZE (188)
#define HC32_SRAM_END (0x1FFF8000 + HC32_SRAM_SIZE * 1024)
#ifdef __ARMCC_VERSION
extern int Image$$RW_IRAM2$$ZI$$Limit;
#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit)
#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit)
#elif __ICCARM__
#pragma section="HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#pragma section = "HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#else
extern int __bss_end;
#define HEAP_BEGIN (&__bss_end)
#define HEAP_BEGIN (&__bss_end)
#endif
#define HEAP_END HC32_SRAM_END
#define HEAP_END HC32_SRAM_END
void PeripheralRegister_Unlock(void);
void PeripheralClock_Config(void);

42
bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.c
View File

@ -127,7 +127,7 @@ rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx)
#endif
#if defined (RT_USING_SPI)
#if defined(RT_USING_SPI)
rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx)
{
rt_err_t result = RT_EOK;
@ -141,16 +141,16 @@ rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx)
case (rt_uint32_t)CM_SPI3:
GPIO_StructInit(&stcGpioInit);
stcGpioInit.u16PinState = PIN_STAT_SET;
stcGpioInit.u16PinDir = PIN_DIR_OUT;
stcGpioInit.u16PinDir = PIN_DIR_OUT;
GPIO_Init(SPI3_WP_PORT, SPI3_WP_PIN, &stcGpioInit);
GPIO_Init(SPI3_HOLD_PORT, SPI3_HOLD_PIN, &stcGpioInit);
(void)GPIO_StructInit(&stcGpioInit);
stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
(void)GPIO_Init(SPI3_SCK_PORT, SPI3_SCK_PIN, &stcGpioInit);
(void)GPIO_Init(SPI3_SCK_PORT, SPI3_SCK_PIN, &stcGpioInit);
(void)GPIO_Init(SPI3_MOSI_PORT, SPI3_MOSI_PIN, &stcGpioInit);
(void)GPIO_Init(SPI3_MISO_PORT, SPI3_MISO_PIN, &stcGpioInit);
GPIO_SetFunc(SPI3_SCK_PORT, SPI3_SCK_PIN, SPI3_SCK_FUNC);
GPIO_SetFunc(SPI3_SCK_PORT, SPI3_SCK_PIN, SPI3_SCK_FUNC);
GPIO_SetFunc(SPI3_MOSI_PORT, SPI3_MOSI_PIN, SPI3_MOSI_FUNC);
GPIO_SetFunc(SPI3_MISO_PORT, SPI3_MISO_PIN, SPI3_MISO_FUNC);
break;
@ -164,7 +164,7 @@ rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx)
}
#endif
#if defined (RT_USING_SDIO)
#if defined(RT_USING_SDIO)
rt_err_t rt_hw_board_sdio_init(CM_SDIOC_TypeDef *SDIOCx)
{
rt_err_t result = RT_EOK;
@ -177,19 +177,19 @@ rt_err_t rt_hw_board_sdio_init(CM_SDIOC_TypeDef *SDIOCx)
/************************* Set pin drive capacity *************************/
(void)GPIO_StructInit(&stcGpioInit);
stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
(void)GPIO_Init(SDIOC1_CK_PORT, SDIOC1_CK_PIN, &stcGpioInit);
(void)GPIO_Init(SDIOC1_CK_PORT, SDIOC1_CK_PIN, &stcGpioInit);
(void)GPIO_Init(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, &stcGpioInit);
(void)GPIO_Init(SDIOC1_D0_PORT, SDIOC1_D0_PIN, &stcGpioInit);
(void)GPIO_Init(SDIOC1_D1_PORT, SDIOC1_D1_PIN, &stcGpioInit);
(void)GPIO_Init(SDIOC1_D2_PORT, SDIOC1_D2_PIN, &stcGpioInit);
(void)GPIO_Init(SDIOC1_D3_PORT, SDIOC1_D3_PIN, &stcGpioInit);
(void)GPIO_Init(SDIOC1_D0_PORT, SDIOC1_D0_PIN, &stcGpioInit);
(void)GPIO_Init(SDIOC1_D1_PORT, SDIOC1_D1_PIN, &stcGpioInit);
(void)GPIO_Init(SDIOC1_D2_PORT, SDIOC1_D2_PIN, &stcGpioInit);
(void)GPIO_Init(SDIOC1_D3_PORT, SDIOC1_D3_PIN, &stcGpioInit);
GPIO_SetFunc(SDIOC1_CK_PORT, SDIOC1_CK_PIN, SDIOC1_CK_FUNC);
GPIO_SetFunc(SDIOC1_CK_PORT, SDIOC1_CK_PIN, SDIOC1_CK_FUNC);
GPIO_SetFunc(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, SDIOC1_CMD_FUNC);
GPIO_SetFunc(SDIOC1_D0_PORT, SDIOC1_D0_PIN, SDIOC1_D0_FUNC);
GPIO_SetFunc(SDIOC1_D1_PORT, SDIOC1_D1_PIN, SDIOC1_D1_FUNC);
GPIO_SetFunc(SDIOC1_D2_PORT, SDIOC1_D2_PIN, SDIOC1_D2_FUNC);
GPIO_SetFunc(SDIOC1_D3_PORT, SDIOC1_D3_PIN, SDIOC1_D3_FUNC);
GPIO_SetFunc(SDIOC1_D0_PORT, SDIOC1_D0_PIN, SDIOC1_D0_FUNC);
GPIO_SetFunc(SDIOC1_D1_PORT, SDIOC1_D1_PIN, SDIOC1_D1_FUNC);
GPIO_SetFunc(SDIOC1_D2_PORT, SDIOC1_D2_PIN, SDIOC1_D2_FUNC);
GPIO_SetFunc(SDIOC1_D3_PORT, SDIOC1_D3_PIN, SDIOC1_D3_FUNC);
break;
#endif
default:
@ -298,24 +298,24 @@ rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x)
#endif
#endif
#if defined (BSP_USING_INPUT_CAPTURE)
#if defined(BSP_USING_INPUT_CAPTURE)
rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance)
{
rt_err_t result = RT_EOK;
switch ((rt_uint32_t)tmr_instance)
{
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1)
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1)
case (rt_uint32_t)CM_TMR6_1:
GPIO_SetFunc(INPUT_CAPTURE_TMR6_1_PORT, INPUT_CAPTURE_TMR6_1_PIN, GPIO_FUNC_3);
break;
#endif
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2)
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2)
case (rt_uint32_t)CM_TMR6_2:
GPIO_SetFunc(INPUT_CAPTURE_TMR6_2_PORT, INPUT_CAPTURE_TMR6_2_PIN, GPIO_FUNC_3);
break;
#endif
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3)
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3)
case (rt_uint32_t)CM_TMR6_3:
GPIO_SetFunc(INPUT_CAPTURE_TMR6_3_PORT, INPUT_CAPTURE_TMR6_3_PIN, GPIO_FUNC_3);
break;
@ -395,8 +395,8 @@ rt_err_t rt_hw_qspi_board_init(void)
(void)GPIO_StructInit(&stcGpioInit);
stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
#ifndef BSP_QSPI_USING_SOFT_CS
(void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit);
GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC);
(void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit);
GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC);
#endif
(void)GPIO_Init(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, &stcGpioInit);
(void)GPIO_Init(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, &stcGpioInit);

430
bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.h
View File

@ -16,309 +16,309 @@
#include "hc32_ll.h"
#include "drv_config.h"
#if defined(RT_USING_CHERRYUSB)
#include "usb_config.h"
#include "usb_config.h"
#endif
/************************* XTAL port **********************/
#define XTAL_PORT (GPIO_PORT_H)
#define XTAL_IN_PIN (GPIO_PIN_01)
#define XTAL_OUT_PIN (GPIO_PIN_00)
#define XTAL_PORT (GPIO_PORT_H)
#define XTAL_IN_PIN (GPIO_PIN_01)
#define XTAL_OUT_PIN (GPIO_PIN_00)
/************************ USART port **********************/
#if defined(BSP_USING_UART2)
#define USART2_RX_PORT (GPIO_PORT_A)
#define USART2_RX_PIN (GPIO_PIN_03)
#define USART2_RX_FUNC (GPIO_FUNC_37)
#define USART2_RX_PORT (GPIO_PORT_A)
#define USART2_RX_PIN (GPIO_PIN_03)
#define USART2_RX_FUNC (GPIO_FUNC_37)
#define USART2_TX_PORT (GPIO_PORT_A)
#define USART2_TX_PIN (GPIO_PIN_02)
#define USART2_TX_FUNC (GPIO_FUNC_36)
#define USART2_TX_PORT (GPIO_PORT_A)
#define USART2_TX_PIN (GPIO_PIN_02)
#define USART2_TX_FUNC (GPIO_FUNC_36)
#endif
#if defined(BSP_USING_UART4)
#define USART4_RX_PORT (GPIO_PORT_B)
#define USART4_RX_PIN (GPIO_PIN_09)
#define USART4_RX_FUNC (GPIO_FUNC_37)
#define USART4_RX_PORT (GPIO_PORT_B)
#define USART4_RX_PIN (GPIO_PIN_09)
#define USART4_RX_FUNC (GPIO_FUNC_37)
#define USART4_TX_PORT (GPIO_PORT_E)
#define USART4_TX_PIN (GPIO_PIN_06)
#define USART4_TX_FUNC (GPIO_FUNC_36)
#define USART4_TX_PORT (GPIO_PORT_E)
#define USART4_TX_PIN (GPIO_PIN_06)
#define USART4_TX_FUNC (GPIO_FUNC_36)
#endif
/************************ I2C port **********************/
#if defined(BSP_USING_I2C1)
#define I2C1_SDA_PORT (GPIO_PORT_A)
#define I2C1_SDA_PIN (GPIO_PIN_07)
#define I2C1_SDA_FUNC (GPIO_FUNC_48)
#define I2C1_SDA_PORT (GPIO_PORT_A)
#define I2C1_SDA_PIN (GPIO_PIN_07)
#define I2C1_SDA_FUNC (GPIO_FUNC_48)
#define I2C1_SCL_PORT (GPIO_PORT_C)
#define I2C1_SCL_PIN (GPIO_PIN_04)
#define I2C1_SCL_FUNC (GPIO_FUNC_49)
#define I2C1_SCL_PORT (GPIO_PORT_C)
#define I2C1_SCL_PIN (GPIO_PIN_04)
#define I2C1_SCL_FUNC (GPIO_FUNC_49)
#endif
#if defined(BSP_USING_I2C3)
#define I2C3_SDA_PORT (GPIO_PORT_B)
#define I2C3_SDA_PIN (GPIO_PIN_05)
#define I2C3_SDA_FUNC (GPIO_FUNC_48)
#define I2C3_SDA_PORT (GPIO_PORT_B)
#define I2C3_SDA_PIN (GPIO_PIN_05)
#define I2C3_SDA_FUNC (GPIO_FUNC_48)
#define I2C3_SCL_PORT (GPIO_PORT_E)
#define I2C3_SCL_PIN (GPIO_PIN_15)
#define I2C3_SCL_FUNC (GPIO_FUNC_49)
#define I2C3_SCL_PORT (GPIO_PORT_E)
#define I2C3_SCL_PIN (GPIO_PIN_15)
#define I2C3_SCL_FUNC (GPIO_FUNC_49)
#endif
/*********** ADC configure *********/
#if defined(BSP_USING_ADC1)
#define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC12_IN10 */
#define ADC1_CH_PIN (GPIO_PIN_00)
#define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC12_IN10 */
#define ADC1_CH_PIN (GPIO_PIN_00)
#endif
#if defined(BSP_USING_ADC2)
#define ADC2_CH_PORT (GPIO_PORT_C) /* Default ADC12_IN11 */
#define ADC2_CH_PIN (GPIO_PIN_01)
#define ADC2_CH_PORT (GPIO_PORT_C) /* Default ADC12_IN11 */
#define ADC2_CH_PIN (GPIO_PIN_01)
#endif
/*********** CAN configure *********/
#if defined(BSP_USING_CAN1)
#define CAN1_TX_PORT (GPIO_PORT_B)
#define CAN1_TX_PIN (GPIO_PIN_07)
#define CAN1_TX_PIN_FUNC (GPIO_FUNC_50)
#define CAN1_TX_PORT (GPIO_PORT_B)
#define CAN1_TX_PIN (GPIO_PIN_07)
#define CAN1_TX_PIN_FUNC (GPIO_FUNC_50)
#define CAN1_RX_PORT (GPIO_PORT_B)
#define CAN1_RX_PIN (GPIO_PIN_06)
#define CAN1_RX_PIN_FUNC (GPIO_FUNC_51)
#define CAN1_RX_PORT (GPIO_PORT_B)
#define CAN1_RX_PIN (GPIO_PIN_06)
#define CAN1_RX_PIN_FUNC (GPIO_FUNC_51)
#define CAN1_STB_PORT (GPIO_PORT_D)
#define CAN1_STB_PIN (GPIO_PIN_15)
#define CAN1_STB_PORT (GPIO_PORT_D)
#define CAN1_STB_PIN (GPIO_PIN_15)
#endif
/************************* SPI port ***********************/
#if defined(BSP_USING_SPI3)
#define SPI3_CS_PORT (GPIO_PORT_C)
#define SPI3_CS_PIN (GPIO_PIN_07)
#define SPI3_CS_PORT (GPIO_PORT_C)
#define SPI3_CS_PIN (GPIO_PIN_07)
#define SPI3_SCK_PORT (GPIO_PORT_C)
#define SPI3_SCK_PIN (GPIO_PIN_06)
#define SPI3_SCK_FUNC (GPIO_FUNC_43)
#define SPI3_SCK_PORT (GPIO_PORT_C)
#define SPI3_SCK_PIN (GPIO_PIN_06)
#define SPI3_SCK_FUNC (GPIO_FUNC_43)
#define SPI3_MOSI_PORT (GPIO_PORT_D)
#define SPI3_MOSI_PIN (GPIO_PIN_08)
#define SPI3_MOSI_FUNC (GPIO_FUNC_40)
#define SPI3_MOSI_PORT (GPIO_PORT_D)
#define SPI3_MOSI_PIN (GPIO_PIN_08)
#define SPI3_MOSI_FUNC (GPIO_FUNC_40)
#define SPI3_MISO_PORT (GPIO_PORT_D)
#define SPI3_MISO_PIN (GPIO_PIN_09)
#define SPI3_MISO_FUNC (GPIO_FUNC_41)
#define SPI3_MISO_PORT (GPIO_PORT_D)
#define SPI3_MISO_PIN (GPIO_PIN_09)
#define SPI3_MISO_FUNC (GPIO_FUNC_41)
#define SPI3_WP_PORT (GPIO_PORT_D)
#define SPI3_WP_PIN (GPIO_PIN_10)
#define SPI3_WP_PORT (GPIO_PORT_D)
#define SPI3_WP_PIN (GPIO_PIN_10)
#define SPI3_HOLD_PORT (GPIO_PORT_D)
#define SPI3_HOLD_PIN (GPIO_PIN_11)
#define SPI3_HOLD_PORT (GPIO_PORT_D)
#define SPI3_HOLD_PIN (GPIO_PIN_11)
#endif
/************************ SDIOC port **********************/
#if defined(BSP_USING_SDIO1)
#define SDIOC1_CK_PORT (GPIO_PORT_C)
#define SDIOC1_CK_PIN (GPIO_PIN_12)
#define SDIOC1_CK_FUNC (GPIO_FUNC_9)
#define SDIOC1_CK_PORT (GPIO_PORT_C)
#define SDIOC1_CK_PIN (GPIO_PIN_12)
#define SDIOC1_CK_FUNC (GPIO_FUNC_9)
#define SDIOC1_CMD_PORT (GPIO_PORT_D)
#define SDIOC1_CMD_PIN (GPIO_PIN_02)
#define SDIOC1_CMD_FUNC (GPIO_FUNC_9)
#define SDIOC1_CMD_PORT (GPIO_PORT_D)
#define SDIOC1_CMD_PIN (GPIO_PIN_02)
#define SDIOC1_CMD_FUNC (GPIO_FUNC_9)
#define SDIOC1_D0_PORT (GPIO_PORT_C)
#define SDIOC1_D0_PIN (GPIO_PIN_08)
#define SDIOC1_D0_FUNC (GPIO_FUNC_9)
#define SDIOC1_D0_PORT (GPIO_PORT_C)
#define SDIOC1_D0_PIN (GPIO_PIN_08)
#define SDIOC1_D0_FUNC (GPIO_FUNC_9)
#define SDIOC1_D1_PORT (GPIO_PORT_C)
#define SDIOC1_D1_PIN (GPIO_PIN_09)
#define SDIOC1_D1_FUNC (GPIO_FUNC_9)
#define SDIOC1_D1_PORT (GPIO_PORT_C)
#define SDIOC1_D1_PIN (GPIO_PIN_09)
#define SDIOC1_D1_FUNC (GPIO_FUNC_9)
#define SDIOC1_D2_PORT (GPIO_PORT_C)
#define SDIOC1_D2_PIN (GPIO_PIN_10)
#define SDIOC1_D2_FUNC (GPIO_FUNC_9)
#define SDIOC1_D2_PORT (GPIO_PORT_C)
#define SDIOC1_D2_PIN (GPIO_PIN_10)
#define SDIOC1_D2_FUNC (GPIO_FUNC_9)
#define SDIOC1_D3_PORT (GPIO_PORT_C)
#define SDIOC1_D3_PIN (GPIO_PIN_11)
#define SDIOC1_D3_FUNC (GPIO_FUNC_9)
#define SDIOC1_D3_PORT (GPIO_PORT_C)
#define SDIOC1_D3_PIN (GPIO_PIN_11)
#define SDIOC1_D3_FUNC (GPIO_FUNC_9)
#endif
/************************ RTC/PM *****************************/
#if defined(BSP_USING_RTC) || defined(RT_USING_PM)
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
#define XTAL32_PORT (GPIO_PORT_C)
#define XTAL32_IN_PIN (GPIO_PIN_15)
#define XTAL32_OUT_PIN (GPIO_PIN_14)
#endif
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
#define XTAL32_PORT (GPIO_PORT_C)
#define XTAL32_IN_PIN (GPIO_PIN_15)
#define XTAL32_OUT_PIN (GPIO_PIN_14)
#endif
#endif
#if defined(RT_USING_PWM)
/*********** PWM_TMRA configure *********/
#if defined(BSP_USING_PWM_TMRA_1)
#if defined(BSP_USING_PWM_TMRA_1_CH1)
#define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08)
#define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4)
#endif
#if defined(BSP_USING_PWM_TMRA_1_CH2)
#define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09)
#define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4)
#endif
#if defined(BSP_USING_PWM_TMRA_1_CH3)
#define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10)
#define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4)
#endif
#if defined(BSP_USING_PWM_TMRA_1_CH4)
#define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11)
#define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4)
#endif
#endif
#if defined(BSP_USING_PWM_TMRA_1)
#if defined(BSP_USING_PWM_TMRA_1_CH1)
#define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08)
#define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4)
#endif
#if defined(BSP_USING_PWM_TMRA_1_CH2)
#define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09)
#define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4)
#endif
#if defined(BSP_USING_PWM_TMRA_1_CH3)
#define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10)
#define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4)
#endif
#if defined(BSP_USING_PWM_TMRA_1_CH4)
#define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11)
#define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4)
#endif
#endif
/*********** PWM_TMR4 configure *********/
#if defined(BSP_USING_PWM_TMR4_1)
#if defined(BSP_USING_PWM_TMR4_1_OUH)
#define PWM_TMR4_1_OUH_PORT (GPIO_PORT_E)
#define PWM_TMR4_1_OUH_PIN (GPIO_PIN_09)
#define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OUL)
#define PWM_TMR4_1_OUL_PORT (GPIO_PORT_E)
#define PWM_TMR4_1_OUL_PIN (GPIO_PIN_08)
#define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OVH)
#define PWM_TMR4_1_OVH_PORT (GPIO_PORT_E)
#define PWM_TMR4_1_OVH_PIN (GPIO_PIN_11)
#define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OVL)
#define PWM_TMR4_1_OVL_PORT (GPIO_PORT_E)
#define PWM_TMR4_1_OVL_PIN (GPIO_PIN_10)
#define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OWH)
#define PWM_TMR4_1_OWH_PORT (GPIO_PORT_E)
#define PWM_TMR4_1_OWH_PIN (GPIO_PIN_13)
#define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OWL)
#define PWM_TMR4_1_OWL_PORT (GPIO_PORT_E)
#define PWM_TMR4_1_OWL_PIN (GPIO_PIN_12)
#define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2)
#endif
#endif
#if defined(BSP_USING_PWM_TMR4_1)
#if defined(BSP_USING_PWM_TMR4_1_OUH)
#define PWM_TMR4_1_OUH_PORT (GPIO_PORT_E)
#define PWM_TMR4_1_OUH_PIN (GPIO_PIN_09)
#define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OUL)
#define PWM_TMR4_1_OUL_PORT (GPIO_PORT_E)
#define PWM_TMR4_1_OUL_PIN (GPIO_PIN_08)
#define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OVH)
#define PWM_TMR4_1_OVH_PORT (GPIO_PORT_E)
#define PWM_TMR4_1_OVH_PIN (GPIO_PIN_11)
#define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OVL)
#define PWM_TMR4_1_OVL_PORT (GPIO_PORT_E)
#define PWM_TMR4_1_OVL_PIN (GPIO_PIN_10)
#define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OWH)
#define PWM_TMR4_1_OWH_PORT (GPIO_PORT_E)
#define PWM_TMR4_1_OWH_PIN (GPIO_PIN_13)
#define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2)
#endif
#if defined(BSP_USING_PWM_TMR4_1_OWL)
#define PWM_TMR4_1_OWL_PORT (GPIO_PORT_E)
#define PWM_TMR4_1_OWL_PIN (GPIO_PIN_12)
#define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2)
#endif
#endif
/*********** PWM_TMR6 configure *********/
#if defined(BSP_USING_PWM_TMR6_1)
#if defined(BSP_USING_PWM_TMR6_1_A)
#define PWM_TMR6_1_A_PORT (GPIO_PORT_A)
#define PWM_TMR6_1_A_PIN (GPIO_PIN_08)
#define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3)
#endif
#if defined(BSP_USING_PWM_TMR6_1_B)
#define PWM_TMR6_1_B_PORT (GPIO_PORT_A)
#define PWM_TMR6_1_B_PIN (GPIO_PIN_07)
#define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3)
#endif
#endif
#if defined(BSP_USING_PWM_TMR6_1)
#if defined(BSP_USING_PWM_TMR6_1_A)
#define PWM_TMR6_1_A_PORT (GPIO_PORT_A)
#define PWM_TMR6_1_A_PIN (GPIO_PIN_08)
#define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3)
#endif
#if defined(BSP_USING_PWM_TMR6_1_B)
#define PWM_TMR6_1_B_PORT (GPIO_PORT_A)
#define PWM_TMR6_1_B_PIN (GPIO_PIN_07)
#define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3)
#endif
#endif
#endif
#if defined(BSP_USING_INPUT_CAPTURE)
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1)
#define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_A)
#define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_08)
#define INPUT_CAPTURE_TMR6_1_PIN_FUNC (GPIO_FUNC_3)
#endif
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2)
#define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_B)
#define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_02)
#define INPUT_CAPTURE_TMR6_2_PIN_FUNC (GPIO_FUNC_3)
#endif
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3)
#define INPUT_CAPTURE_TMR6_3_PORT (GPIO_PORT_A)
#define INPUT_CAPTURE_TMR6_3_PIN (GPIO_PIN_12)
#define INPUT_CAPTURE_TMR6_3_PIN_FUNC (GPIO_FUNC_3)
#endif
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1)
#define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_A)
#define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_08)
#define INPUT_CAPTURE_TMR6_1_PIN_FUNC (GPIO_FUNC_3)
#endif
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2)
#define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_B)
#define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_02)
#define INPUT_CAPTURE_TMR6_2_PIN_FUNC (GPIO_FUNC_3)
#endif
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3)
#define INPUT_CAPTURE_TMR6_3_PORT (GPIO_PORT_A)
#define INPUT_CAPTURE_TMR6_3_PIN (GPIO_PIN_12)
#define INPUT_CAPTURE_TMR6_3_PIN_FUNC (GPIO_FUNC_3)
#endif
#endif
#if defined(RT_USING_CHERRYUSB)
#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || \
defined(BSP_USING_USBFS) || defined(RT_USING_USB)
#error "When using CherryUSB, Please donot Enable 'On-Chip Peripheral Driver---> []Enable USB' or using USB legacy version!"
#endif
#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || \
defined(BSP_USING_USBFS) || defined(RT_USING_USB)
#error "When using CherryUSB, Please donot Enable 'On-Chip Peripheral Driver---> []Enable USB' or using USB legacy version!"
#endif
#endif
#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB)
#if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB)
#if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB)
/* USBFS Core*/
#define USBF_DP_PORT (GPIO_PORT_A)
#define USBF_DP_PIN (GPIO_PIN_12)
#define USBF_DM_PORT (GPIO_PORT_A)
#define USBF_DM_PIN (GPIO_PIN_11)
#define USBF_VBUS_PORT (GPIO_PORT_A)
#define USBF_VBUS_PIN (GPIO_PIN_09)
#define USBF_VBUS_FUNC (GPIO_FUNC_10)
#define USBF_DRVVBUS_PORT (GPIO_PORT_B)
#define USBF_DRVVBUS_PIN (GPIO_PIN_08)
#define USBF_DRVVBUS_FUNC (GPIO_FUNC_10)
#endif
#define USBF_DP_PORT (GPIO_PORT_A)
#define USBF_DP_PIN (GPIO_PIN_12)
#define USBF_DM_PORT (GPIO_PORT_A)
#define USBF_DM_PIN (GPIO_PIN_11)
#define USBF_VBUS_PORT (GPIO_PORT_A)
#define USBF_VBUS_PIN (GPIO_PIN_09)
#define USBF_VBUS_FUNC (GPIO_FUNC_10)
#define USBF_DRVVBUS_PORT (GPIO_PORT_B)
#define USBF_DRVVBUS_PIN (GPIO_PIN_08)
#define USBF_DRVVBUS_FUNC (GPIO_FUNC_10)
#endif
#endif
#if defined(BSP_USING_QSPI)
#ifndef BSP_QSPI_USING_SOFT_CS
#ifndef BSP_QSPI_USING_SOFT_CS
/* QSSN */
#define QSPI_FLASH_CS_PORT (GPIO_PORT_C)
#define QSPI_FLASH_CS_PIN (GPIO_PIN_07)
#define QSPI_FLASH_CS_FUNC (GPIO_FUNC_7)
#endif
#define QSPI_FLASH_CS_PORT (GPIO_PORT_C)
#define QSPI_FLASH_CS_PIN (GPIO_PIN_07)
#define QSPI_FLASH_CS_FUNC (GPIO_FUNC_7)
#endif
/* QSCK */
#define QSPI_FLASH_SCK_PORT (GPIO_PORT_C)
#define QSPI_FLASH_SCK_PIN (GPIO_PIN_06)
#define QSPI_FLASH_SCK_FUNC (GPIO_FUNC_7)
#define QSPI_FLASH_SCK_PORT (GPIO_PORT_C)
#define QSPI_FLASH_SCK_PIN (GPIO_PIN_06)
#define QSPI_FLASH_SCK_FUNC (GPIO_FUNC_7)
/* QSIO0 */
#define QSPI_FLASH_IO0_PORT (GPIO_PORT_D)
#define QSPI_FLASH_IO0_PIN (GPIO_PIN_08)
#define QSPI_FLASH_IO0_FUNC (GPIO_FUNC_7)
#define QSPI_FLASH_IO0_PORT (GPIO_PORT_D)
#define QSPI_FLASH_IO0_PIN (GPIO_PIN_08)
#define QSPI_FLASH_IO0_FUNC (GPIO_FUNC_7)
/* QSIO1 */
#define QSPI_FLASH_IO1_PORT (GPIO_PORT_D)
#define QSPI_FLASH_IO1_PIN (GPIO_PIN_09)
#define QSPI_FLASH_IO1_FUNC (GPIO_FUNC_7)
#define QSPI_FLASH_IO1_PORT (GPIO_PORT_D)
#define QSPI_FLASH_IO1_PIN (GPIO_PIN_09)
#define QSPI_FLASH_IO1_FUNC (GPIO_FUNC_7)
/* QSIO2 */
#define QSPI_FLASH_IO2_PORT (GPIO_PORT_D)
#define QSPI_FLASH_IO2_PIN (GPIO_PIN_10)
#define QSPI_FLASH_IO2_FUNC (GPIO_FUNC_7)
#define QSPI_FLASH_IO2_PORT (GPIO_PORT_D)
#define QSPI_FLASH_IO2_PIN (GPIO_PIN_10)
#define QSPI_FLASH_IO2_FUNC (GPIO_FUNC_7)
/* QSIO3 */
#define QSPI_FLASH_IO3_PORT (GPIO_PORT_D)
#define QSPI_FLASH_IO3_PIN (GPIO_PIN_11)
#define QSPI_FLASH_IO3_FUNC (GPIO_FUNC_7)
#define QSPI_FLASH_IO3_PORT (GPIO_PORT_D)
#define QSPI_FLASH_IO3_PIN (GPIO_PIN_11)
#define QSPI_FLASH_IO3_FUNC (GPIO_FUNC_7)
#endif
/*********** TMRA_PULSE_ENCODER configure *********/
#if defined(RT_USING_PULSE_ENCODER)
#if defined(BSP_USING_TMRA_PULSE_ENCODER)
#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
#define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A)
#define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08)
#define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4)
#define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A)
#define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09)
#define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4)
#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
#endif /* BSP_USING_TMRA_PULSE_ENCODER */
#if defined(BSP_USING_TMRA_PULSE_ENCODER)
#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
#define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A)
#define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08)
#define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4)
#define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A)
#define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09)
#define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4)
#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
#endif /* BSP_USING_TMRA_PULSE_ENCODER */
#if defined(BSP_USING_TMR6_PULSE_ENCODER)
#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
#define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_E)
#define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_09)
#define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3)
#define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_E)
#define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_08)
#define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3)
#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
#endif /* BSP_USING_TMR6_PULSE_ENCODER */
#if defined(BSP_USING_TMR6_PULSE_ENCODER)
#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
#define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_E)
#define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_09)
#define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3)
#define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_E)
#define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_08)
#define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3)
#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
#endif /* BSP_USING_TMR6_PULSE_ENCODER */
#endif /* RT_USING_PULSE_ENCODER */
#endif

126
bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/adc_config.h
View File

@ -20,42 +20,41 @@ extern "C" {
#ifdef BSP_USING_ADC1
#ifndef ADC1_INIT_PARAMS
#define ADC1_INIT_PARAMS \
{ \
.name = "adc1", \
.vref = 3300, \
.resolution = ADC_RESOLUTION_12BIT, \
.data_align = ADC_DATAALIGN_RIGHT, \
.eoc_poll_time_max = 100, \
.hard_trig_enable = RT_FALSE, \
.hard_trig_src = ADC_HARDTRIG_EVT0, \
.internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
.internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_MAX, \
.continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \
#define ADC1_INIT_PARAMS \
{ \
.name = "adc1", \
.vref = 3300, \
.resolution = ADC_RESOLUTION_12BIT, \
.data_align = ADC_DATAALIGN_RIGHT, \
.eoc_poll_time_max = 100, \
.hard_trig_enable = RT_FALSE, \
.hard_trig_src = ADC_HARDTRIG_EVT0, \
.internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
.internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_MAX, \
.continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \
}
#endif /* ADC1_INIT_PARAMS */
#if defined (BSP_ADC1_USING_DMA)
#if defined(BSP_ADC1_USING_DMA)
#ifndef ADC1_EOCA_DMA_CONFIG
#define ADC1_EOCA_DMA_CONFIG \
{ \
.Instance = ADC1_EOCA_DMA_INSTANCE, \
.channel = ADC1_EOCA_DMA_CHANNEL, \
.clock = ADC1_EOCA_DMA_CLOCK, \
.trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_ADC1_EOCA, \
.flag = ADC1_EOCA_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = ADC1_EOCA_DMA_IRQn, \
.irq_prio = ADC1_EOCA_DMA_INT_PRIO, \
.int_src = ADC1_EOCA_DMA_INT_SRC, \
}, \
#define ADC1_EOCA_DMA_CONFIG \
{ \
.Instance = ADC1_EOCA_DMA_INSTANCE, \
.channel = ADC1_EOCA_DMA_CHANNEL, \
.clock = ADC1_EOCA_DMA_CLOCK, \
.trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_ADC1_EOCA, \
.flag = ADC1_EOCA_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = ADC1_EOCA_DMA_IRQn, \
.irq_prio = ADC1_EOCA_DMA_INT_PRIO, \
.int_src = ADC1_EOCA_DMA_INT_SRC, \
}, \
}
#endif /* ADC1_EOCA_DMA_CONFIG */
#endif /* BSP_ADC1_USING_DMA */
@ -63,42 +62,41 @@ extern "C" {
#ifdef BSP_USING_ADC2
#ifndef ADC2_INIT_PARAMS
#define ADC2_INIT_PARAMS \
{ \
.name = "adc2", \
.vref = 3300, \
.resolution = ADC_RESOLUTION_12BIT, \
.data_align = ADC_DATAALIGN_RIGHT, \
.eoc_poll_time_max = 100, \
.hard_trig_enable = RT_FALSE, \
.hard_trig_src = ADC_HARDTRIG_EVT0, \
.internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
.internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_MAX, \
.continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \
#define ADC2_INIT_PARAMS \
{ \
.name = "adc2", \
.vref = 3300, \
.resolution = ADC_RESOLUTION_12BIT, \
.data_align = ADC_DATAALIGN_RIGHT, \
.eoc_poll_time_max = 100, \
.hard_trig_enable = RT_FALSE, \
.hard_trig_src = ADC_HARDTRIG_EVT0, \
.internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
.internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_MAX, \
.continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \
}
#endif /* ADC2_INIT_PARAMS */
#if defined (BSP_ADC2_USING_DMA)
#if defined(BSP_ADC2_USING_DMA)
#ifndef ADC2_EOCA_DMA_CONFIG
#define ADC2_EOCA_DMA_CONFIG \
{ \
.Instance = ADC2_EOCA_DMA_INSTANCE, \
.channel = ADC2_EOCA_DMA_CHANNEL, \
.clock = ADC2_EOCA_DMA_CLOCK, \
.trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_ADC2_EOCA, \
.flag = ADC2_EOCA_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = ADC2_EOCA_DMA_IRQn, \
.irq_prio = ADC2_EOCA_DMA_INT_PRIO, \
.int_src = ADC2_EOCA_DMA_INT_SRC, \
}, \
#define ADC2_EOCA_DMA_CONFIG \
{ \
.Instance = ADC2_EOCA_DMA_INSTANCE, \
.channel = ADC2_EOCA_DMA_CHANNEL, \
.clock = ADC2_EOCA_DMA_CLOCK, \
.trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_ADC2_EOCA, \
.flag = ADC2_EOCA_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = ADC2_EOCA_DMA_IRQn, \
.irq_prio = ADC2_EOCA_DMA_INT_PRIO, \
.int_src = ADC2_EOCA_DMA_INT_SRC, \
}, \
}
#endif /* ADC2_EOCA_DMA_CONFIG */
#endif /* BSP_ADC2_USING_DMA */

118
bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/can_config.h
View File

@ -19,12 +19,12 @@ extern "C" {
#endif
#ifdef BSP_USING_CAN1
#define CAN1_NAME ("can1")
#define CAN1_NAME ("can1")
#ifndef CAN1_INIT_PARAMS
#define CAN1_INIT_PARAMS \
{ \
.name = CAN1_NAME, \
.single_trans_mode = RT_FALSE \
#define CAN1_INIT_PARAMS \
{ \
.name = CAN1_NAME, \
.single_trans_mode = RT_FALSE \
}
#endif /* CAN1_INIT_PARAMS */
#endif /* BSP_USING_CAN1 */
@ -38,76 +38,76 @@ extern "C" {
The following bit time configures are based on CAN Clock 8M
*/
#define CAN_BIT_TIME_CONFIG_1M_BAUD \
{ \
.u32Prescaler = 1, \
.u32TimeSeg1 = 6, \
.u32TimeSeg2 = 2, \
.u32SJW = 2 \
#define CAN_BIT_TIME_CONFIG_1M_BAUD \
{ \
.u32Prescaler = 1, \
.u32TimeSeg1 = 6, \
.u32TimeSeg2 = 2, \
.u32SJW = 2 \
}
#define CAN_BIT_TIME_CONFIG_800K_BAUD \
{ \
.u32Prescaler = 1, \
.u32TimeSeg1 = 7, \
.u32TimeSeg2 = 3, \
.u32SJW = 3 \
#define CAN_BIT_TIME_CONFIG_800K_BAUD \
{ \
.u32Prescaler = 1, \
.u32TimeSeg1 = 7, \
.u32TimeSeg2 = 3, \
.u32SJW = 3 \
}
#define CAN_BIT_TIME_CONFIG_500K_BAUD \
{ \
.u32Prescaler = 1, \
.u32TimeSeg1 = 12, \
.u32TimeSeg2 = 4, \
.u32SJW = 4 \
#define CAN_BIT_TIME_CONFIG_500K_BAUD \
{ \
.u32Prescaler = 1, \
.u32TimeSeg1 = 12, \
.u32TimeSeg2 = 4, \
.u32SJW = 4 \
}
#define CAN_BIT_TIME_CONFIG_250K_BAUD \
{ \
.u32Prescaler = 2, \
.u32TimeSeg1 = 12, \
.u32TimeSeg2 = 4, \
.u32SJW = 4 \
#define CAN_BIT_TIME_CONFIG_250K_BAUD \
{ \
.u32Prescaler = 2, \
.u32TimeSeg1 = 12, \
.u32TimeSeg2 = 4, \
.u32SJW = 4 \
}
#define CAN_BIT_TIME_CONFIG_125K_BAUD \
{ \
.u32Prescaler = 4, \
.u32TimeSeg1 = 12, \
.u32TimeSeg2 = 4, \
.u32SJW = 4 \
#define CAN_BIT_TIME_CONFIG_125K_BAUD \
{ \
.u32Prescaler = 4, \
.u32TimeSeg1 = 12, \
.u32TimeSeg2 = 4, \
.u32SJW = 4 \
}
#define CAN_BIT_TIME_CONFIG_100K_BAUD \
{ \
.u32Prescaler = 4, \
.u32TimeSeg1 = 16, \
.u32TimeSeg2 = 4, \
.u32SJW = 4 \
#define CAN_BIT_TIME_CONFIG_100K_BAUD \
{ \
.u32Prescaler = 4, \
.u32TimeSeg1 = 16, \
.u32TimeSeg2 = 4, \
.u32SJW = 4 \
}
#define CAN_BIT_TIME_CONFIG_50K_BAUD \
{ \
.u32Prescaler = 8, \
.u32TimeSeg1 = 16, \
.u32TimeSeg2 = 4, \
.u32SJW = 4 \
#define CAN_BIT_TIME_CONFIG_50K_BAUD \
{ \
.u32Prescaler = 8, \
.u32TimeSeg1 = 16, \
.u32TimeSeg2 = 4, \
.u32SJW = 4 \
}
#define CAN_BIT_TIME_CONFIG_20K_BAUD \
{ \
.u32Prescaler = 20, \
.u32TimeSeg1 = 16, \
.u32TimeSeg2 = 4, \
.u32SJW = 4 \
#define CAN_BIT_TIME_CONFIG_20K_BAUD \
{ \
.u32Prescaler = 20, \
.u32TimeSeg1 = 16, \
.u32TimeSeg2 = 4, \
.u32SJW = 4 \
}
#define CAN_BIT_TIME_CONFIG_10K_BAUD \
{ \
.u32Prescaler = 40, \
.u32TimeSeg1 = 16, \
.u32TimeSeg2 = 4, \
.u32SJW = 4 \
#define CAN_BIT_TIME_CONFIG_10K_BAUD \
{ \
.u32Prescaler = 40, \
.u32TimeSeg1 = 16, \
.u32TimeSeg2 = 4, \
.u32SJW = 4 \
}
#ifdef __cplusplus

464
bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/dma_config.h
View File

@ -20,287 +20,287 @@ extern "C" {
/* DMA1 ch0 */
#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
#define SPI1_RX_DMA_INSTANCE CM_DMA1
#define SPI1_RX_DMA_CHANNEL DMA_CH0
#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0
#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0
#define SPI1_RX_DMA_INSTANCE CM_DMA1
#define SPI1_RX_DMA_CHANNEL DMA_CH0
#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0
#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0
#elif defined(BSP_USING_SDIO1) && !defined(SDIO1_RX_DMA_INSTANCE)
#define SDIO1_RX_DMA_INSTANCE CM_DMA1
#define SDIO1_RX_DMA_CHANNEL DMA_CH0
#define SDIO1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SDIO1_RX_DMA_TRIG_SELECT AOS_DMA1_0
#define SDIO1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define SDIO1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
#define SDIO1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
#define SDIO1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0
#define SDIO1_RX_DMA_INSTANCE CM_DMA1
#define SDIO1_RX_DMA_CHANNEL DMA_CH0
#define SDIO1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SDIO1_RX_DMA_TRIG_SELECT AOS_DMA1_0
#define SDIO1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define SDIO1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
#define SDIO1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
#define SDIO1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0
#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE)
#define I2C1_TX_DMA_INSTANCE CM_DMA1
#define I2C1_TX_DMA_CHANNEL DMA_CH0
#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0
#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0
#define I2C1_TX_DMA_INSTANCE CM_DMA1
#define I2C1_TX_DMA_CHANNEL DMA_CH0
#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0
#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0
#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
#define UART1_RX_DMA_INSTANCE CM_DMA1
#define UART1_RX_DMA_CHANNEL DMA_CH0
#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define UART1_RX_DMA_TRIG_SELECT AOS_DMA1_0
#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define UART1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
#define UART1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
#define UART1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0
#define UART1_RX_DMA_INSTANCE CM_DMA1
#define UART1_RX_DMA_CHANNEL DMA_CH0
#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define UART1_RX_DMA_TRIG_SELECT AOS_DMA1_0
#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define UART1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
#define UART1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
#define UART1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0
#endif
/* DMA1 ch1 */
#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
#define SPI1_TX_DMA_INSTANCE CM_DMA1
#define SPI1_TX_DMA_CHANNEL DMA_CH1
#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1
#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1
#define SPI1_TX_DMA_INSTANCE CM_DMA1
#define SPI1_TX_DMA_CHANNEL DMA_CH1
#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1
#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1
#elif defined(BSP_USING_SDIO1) && !defined(SDIO1_TX_DMA_INSTANCE)
#define SDIO1_TX_DMA_INSTANCE CM_DMA1
#define SDIO1_TX_DMA_CHANNEL DMA_CH1
#define SDIO1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SDIO1_TX_DMA_TRIG_SELECT AOS_DMA1_1
#define SDIO1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define SDIO1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
#define SDIO1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
#define SDIO1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1
#define SDIO1_TX_DMA_INSTANCE CM_DMA1
#define SDIO1_TX_DMA_CHANNEL DMA_CH1
#define SDIO1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SDIO1_TX_DMA_TRIG_SELECT AOS_DMA1_1
#define SDIO1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define SDIO1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
#define SDIO1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
#define SDIO1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1
#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE)
#define I2C1_RX_DMA_INSTANCE CM_DMA1
#define I2C1_RX_DMA_CHANNEL DMA_CH1
#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1
#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1
#define I2C1_RX_DMA_INSTANCE CM_DMA1
#define I2C1_RX_DMA_CHANNEL DMA_CH1
#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1
#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1
#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
#define UART2_RX_DMA_INSTANCE CM_DMA1
#define UART2_RX_DMA_CHANNEL DMA_CH1
#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define UART2_RX_DMA_TRIG_SELECT AOS_DMA1_1
#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define UART2_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
#define UART2_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
#define UART2_RX_DMA_INT_SRC INT_SRC_DMA1_TC1
#define UART2_RX_DMA_INSTANCE CM_DMA1
#define UART2_RX_DMA_CHANNEL DMA_CH1
#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define UART2_RX_DMA_TRIG_SELECT AOS_DMA1_1
#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define UART2_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
#define UART2_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
#define UART2_RX_DMA_INT_SRC INT_SRC_DMA1_TC1
#endif
/* DMA1 ch2 */
#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
#define SPI2_RX_DMA_INSTANCE CM_DMA1
#define SPI2_RX_DMA_CHANNEL DMA_CH2
#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2
#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2
#define SPI2_RX_DMA_INSTANCE CM_DMA1
#define SPI2_RX_DMA_CHANNEL DMA_CH2
#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2
#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2
#elif defined(BSP_USING_SDIO2) && !defined(SDIO2_RX_DMA_INSTANCE)
#define SDIO2_RX_DMA_INSTANCE CM_DMA1
#define SDIO2_RX_DMA_CHANNEL DMA_CH2
#define SDIO2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SDIO2_RX_DMA_TRIG_SELECT AOS_DMA1_2
#define SDIO2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define SDIO2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
#define SDIO2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
#define SDIO2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2
#define SDIO2_RX_DMA_INSTANCE CM_DMA1
#define SDIO2_RX_DMA_CHANNEL DMA_CH2
#define SDIO2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SDIO2_RX_DMA_TRIG_SELECT AOS_DMA1_2
#define SDIO2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define SDIO2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
#define SDIO2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
#define SDIO2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2
#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE)
#define I2C2_TX_DMA_INSTANCE CM_DMA1
#define I2C2_TX_DMA_CHANNEL DMA_CH2
#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2
#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2
#define I2C2_TX_DMA_INSTANCE CM_DMA1
#define I2C2_TX_DMA_CHANNEL DMA_CH2
#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2
#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2
#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
#define UART3_RX_DMA_INSTANCE CM_DMA1
#define UART3_RX_DMA_CHANNEL DMA_CH2
#define UART3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define UART3_RX_DMA_TRIG_SELECT AOS_DMA1_2
#define UART3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define UART3_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
#define UART3_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
#define UART3_RX_DMA_INT_SRC INT_SRC_DMA1_TC2
#define UART3_RX_DMA_INSTANCE CM_DMA1
#define UART3_RX_DMA_CHANNEL DMA_CH2
#define UART3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define UART3_RX_DMA_TRIG_SELECT AOS_DMA1_2
#define UART3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define UART3_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
#define UART3_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
#define UART3_RX_DMA_INT_SRC INT_SRC_DMA1_TC2
#elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE)
#define ADC1_EOCA_DMA_INSTANCE CM_DMA1
#define ADC1_EOCA_DMA_CHANNEL DMA_CH2
#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_2
#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC2
#define ADC1_EOCA_DMA_INSTANCE CM_DMA1
#define ADC1_EOCA_DMA_CHANNEL DMA_CH2
#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_2
#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC2
#endif
/* DMA1 ch3 */
#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
#define SPI2_TX_DMA_INSTANCE CM_DMA1
#define SPI2_TX_DMA_CHANNEL DMA_CH3
#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3
#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3
#define SPI2_TX_DMA_INSTANCE CM_DMA1
#define SPI2_TX_DMA_CHANNEL DMA_CH3
#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3
#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3
#elif defined(BSP_USING_SDIO2) && !defined(SDIO2_TX_DMA_INSTANCE)
#define SDIO2_TX_DMA_INSTANCE CM_DMA1
#define SDIO2_TX_DMA_CHANNEL DMA_CH3
#define SDIO2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SDIO2_TX_DMA_TRIG_SELECT AOS_DMA1_3
#define SDIO2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define SDIO2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
#define SDIO2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
#define SDIO2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3
#define SDIO2_TX_DMA_INSTANCE CM_DMA1
#define SDIO2_TX_DMA_CHANNEL DMA_CH3
#define SDIO2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SDIO2_TX_DMA_TRIG_SELECT AOS_DMA1_3
#define SDIO2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define SDIO2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
#define SDIO2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
#define SDIO2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3
#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE)
#define I2C2_RX_DMA_INSTANCE CM_DMA1
#define I2C2_RX_DMA_CHANNEL DMA_CH3
#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3
#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3
#define I2C2_RX_DMA_INSTANCE CM_DMA1
#define I2C2_RX_DMA_CHANNEL DMA_CH3
#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3
#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3
#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
#define UART4_RX_DMA_INSTANCE CM_DMA1
#define UART4_RX_DMA_CHANNEL DMA_CH3
#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define UART4_RX_DMA_TRIG_SELECT AOS_DMA1_3
#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define UART4_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
#define UART4_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
#define UART4_RX_DMA_INT_SRC INT_SRC_DMA1_TC3
#define UART4_RX_DMA_INSTANCE CM_DMA1
#define UART4_RX_DMA_CHANNEL DMA_CH3
#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define UART4_RX_DMA_TRIG_SELECT AOS_DMA1_3
#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define UART4_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
#define UART4_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
#define UART4_RX_DMA_INT_SRC INT_SRC_DMA1_TC3
#endif
/* DMA2 ch0 */
#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
#define SPI3_RX_DMA_INSTANCE CM_DMA2
#define SPI3_RX_DMA_CHANNEL DMA_CH0
#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA2_0
#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define SPI3_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
#define SPI3_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA2_TC0
#define SPI3_RX_DMA_INSTANCE CM_DMA2
#define SPI3_RX_DMA_CHANNEL DMA_CH0
#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA2_0
#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define SPI3_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
#define SPI3_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA2_TC0
#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_INSTANCE)
#define I2C3_TX_DMA_INSTANCE CM_DMA2
#define I2C3_TX_DMA_CHANNEL DMA_CH0
#define I2C3_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define I2C3_TX_DMA_TRIG_SELECT AOS_DMA2_0
#define I2C3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define I2C3_TX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
#define I2C3_TX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
#define I2C3_TX_DMA_INT_SRC INT_SRC_DMA2_TC0
#define I2C3_TX_DMA_INSTANCE CM_DMA2
#define I2C3_TX_DMA_CHANNEL DMA_CH0
#define I2C3_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define I2C3_TX_DMA_TRIG_SELECT AOS_DMA2_0
#define I2C3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define I2C3_TX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
#define I2C3_TX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
#define I2C3_TX_DMA_INT_SRC INT_SRC_DMA2_TC0
#elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
#define UART1_TX_DMA_INSTANCE CM_DMA2
#define UART1_TX_DMA_CHANNEL DMA_CH0
#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_0
#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define UART1_TX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC0
#define UART1_TX_DMA_INSTANCE CM_DMA2
#define UART1_TX_DMA_CHANNEL DMA_CH0
#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_0
#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define UART1_TX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC0
#elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE)
#define ADC2_EOCA_DMA_INSTANCE CM_DMA2
#define ADC2_EOCA_DMA_CHANNEL DMA_CH0
#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA2_0
#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define ADC2_EOCA_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA2_TC0
#define ADC2_EOCA_DMA_INSTANCE CM_DMA2
#define ADC2_EOCA_DMA_CHANNEL DMA_CH0
#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA2_0
#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define ADC2_EOCA_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA2_TC0
#endif
/* DMA2 ch1 */
#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
#define SPI3_TX_DMA_INSTANCE CM_DMA2
#define SPI3_TX_DMA_CHANNEL DMA_CH1
#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA2_1
#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define SPI3_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM
#define SPI3_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO
#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA2_TC1
#define SPI3_TX_DMA_INSTANCE CM_DMA2
#define SPI3_TX_DMA_CHANNEL DMA_CH1
#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA2_1
#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define SPI3_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM
#define SPI3_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO
#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA2_TC1
#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_INSTANCE)
#define I2C3_RX_DMA_INSTANCE CM_DMA2
#define I2C3_RX_DMA_CHANNEL DMA_CH1
#define I2C3_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define I2C3_RX_DMA_TRIG_SELECT AOS_DMA2_1
#define I2C3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define I2C3_RX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM
#define I2C3_RX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO
#define I2C3_RX_DMA_INT_SRC INT_SRC_DMA2_TC1
#define I2C3_RX_DMA_INSTANCE CM_DMA2
#define I2C3_RX_DMA_CHANNEL DMA_CH1
#define I2C3_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define I2C3_RX_DMA_TRIG_SELECT AOS_DMA2_1
#define I2C3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define I2C3_RX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM
#define I2C3_RX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO
#define I2C3_RX_DMA_INT_SRC INT_SRC_DMA2_TC1
#elif defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
#define UART2_TX_DMA_INSTANCE CM_DMA2
#define UART2_TX_DMA_CHANNEL DMA_CH1
#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_1
#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define UART2_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM
#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO
#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC1
#define UART2_TX_DMA_INSTANCE CM_DMA2
#define UART2_TX_DMA_CHANNEL DMA_CH1
#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_1
#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define UART2_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM
#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO
#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC1
#endif
/* DMA2 ch2 */
#if defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
#define SPI4_RX_DMA_INSTANCE CM_DMA2
#define SPI4_RX_DMA_CHANNEL DMA_CH2
#define SPI4_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define SPI4_RX_DMA_TRIG_SELECT AOS_DMA2_2
#define SPI4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define SPI4_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM
#define SPI4_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO
#define SPI4_RX_DMA_INT_SRC INT_SRC_DMA2_TC2
#define SPI4_RX_DMA_INSTANCE CM_DMA2
#define SPI4_RX_DMA_CHANNEL DMA_CH2
#define SPI4_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define SPI4_RX_DMA_TRIG_SELECT AOS_DMA2_2
#define SPI4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define SPI4_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM
#define SPI4_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO
#define SPI4_RX_DMA_INT_SRC INT_SRC_DMA2_TC2
#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
#define UART3_TX_DMA_INSTANCE CM_DMA2
#define UART3_TX_DMA_CHANNEL DMA_CH2
#define UART3_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART3_TX_DMA_TRIG_SELECT AOS_DMA2_2
#define UART3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define UART3_TX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM
#define UART3_TX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO
#define UART3_TX_DMA_INT_SRC INT_SRC_DMA2_TC2
#define UART3_TX_DMA_INSTANCE CM_DMA2
#define UART3_TX_DMA_CHANNEL DMA_CH2
#define UART3_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART3_TX_DMA_TRIG_SELECT AOS_DMA2_2
#define UART3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define UART3_TX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM
#define UART3_TX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO
#define UART3_TX_DMA_INT_SRC INT_SRC_DMA2_TC2
#elif defined(BSP_USING_QSPI) && !defined(QSPI_DMA_INSTANCE)
#define QSPI_DMA_INSTANCE CM_DMA2
#define QSPI_DMA_CHANNEL DMA_CH2
#define QSPI_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define QSPI_DMA_TRIG_SELECT AOS_DMA2_2
#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define QSPI_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM
#define QSPI_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO
#define QSPI_DMA_INT_SRC INT_SRC_DMA2_TC2
#define QSPI_DMA_INSTANCE CM_DMA2
#define QSPI_DMA_CHANNEL DMA_CH2
#define QSPI_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define QSPI_DMA_TRIG_SELECT AOS_DMA2_2
#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define QSPI_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM
#define QSPI_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO
#define QSPI_DMA_INT_SRC INT_SRC_DMA2_TC2
#endif
/* DMA2 ch3 */
#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
#define SPI4_TX_DMA_INSTANCE CM_DMA2
#define SPI4_TX_DMA_CHANNEL DMA_CH3
#define SPI4_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define SPI4_TX_DMA_TRIG_SELECT AOS_DMA2_3
#define SPI4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define SPI4_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM
#define SPI4_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO
#define SPI4_TX_DMA_INT_SRC INT_SRC_DMA2_TC3
#define SPI4_TX_DMA_INSTANCE CM_DMA2
#define SPI4_TX_DMA_CHANNEL DMA_CH3
#define SPI4_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define SPI4_TX_DMA_TRIG_SELECT AOS_DMA2_3
#define SPI4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define SPI4_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM
#define SPI4_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO
#define SPI4_TX_DMA_INT_SRC INT_SRC_DMA2_TC3
#elif defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
#define UART4_TX_DMA_INSTANCE CM_DMA2
#define UART4_TX_DMA_CHANNEL DMA_CH3
#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART4_TX_DMA_TRIG_SELECT AOS_DMA2_3
#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define UART4_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM
#define UART4_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO
#define UART4_TX_DMA_INT_SRC INT_SRC_DMA2_TC3
#define UART4_TX_DMA_INSTANCE CM_DMA2
#define UART4_TX_DMA_CHANNEL DMA_CH3
#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART4_TX_DMA_TRIG_SELECT AOS_DMA2_3
#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define UART4_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM
#define UART4_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO
#define UART4_TX_DMA_INT_SRC INT_SRC_DMA2_TC3
#endif
#ifdef __cplusplus

160
bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/gpio_config.h
View File

@ -22,146 +22,146 @@ extern "C" {
#if defined(RT_USING_PIN)
#ifndef EXTINT0_IRQ_CONFIG
#define EXTINT0_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT0_IRQ_NUM, \
.irq_prio = BSP_EXTINT0_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ0, \
#define EXTINT0_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT0_IRQ_NUM, \
.irq_prio = BSP_EXTINT0_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ0, \
}
#endif /* EXTINT1_IRQ_CONFIG */
#ifndef EXTINT1_IRQ_CONFIG
#define EXTINT1_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT1_IRQ_NUM, \
.irq_prio = BSP_EXTINT1_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ1, \
#define EXTINT1_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT1_IRQ_NUM, \
.irq_prio = BSP_EXTINT1_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ1, \
}
#endif /* EXTINT1_IRQ_CONFIG */
#ifndef EXTINT2_IRQ_CONFIG
#define EXTINT2_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT2_IRQ_NUM, \
.irq_prio = BSP_EXTINT2_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ2, \
#define EXTINT2_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT2_IRQ_NUM, \
.irq_prio = BSP_EXTINT2_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ2, \
}
#endif /* EXTINT2_IRQ_CONFIG */
#ifndef EXTINT3_IRQ_CONFIG
#define EXTINT3_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT3_IRQ_NUM, \
.irq_prio = BSP_EXTINT3_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ3, \
#define EXTINT3_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT3_IRQ_NUM, \
.irq_prio = BSP_EXTINT3_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ3, \
}
#endif /* EXTINT3_IRQ_CONFIG */
#ifndef EXTINT4_IRQ_CONFIG
#define EXTINT4_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT4_IRQ_NUM, \
.irq_prio = BSP_EXTINT4_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ4, \
#define EXTINT4_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT4_IRQ_NUM, \
.irq_prio = BSP_EXTINT4_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ4, \
}
#endif /* EXTINT4_IRQ_CONFIG */
#ifndef EXTINT5_IRQ_CONFIG
#define EXTINT5_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT5_IRQ_NUM, \
.irq_prio = BSP_EXTINT5_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ5, \
#define EXTINT5_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT5_IRQ_NUM, \
.irq_prio = BSP_EXTINT5_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ5, \
}
#endif /* EXTINT5_IRQ_CONFIG */
#ifndef EXTINT6_IRQ_CONFIG
#define EXTINT6_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT6_IRQ_NUM, \
.irq_prio = BSP_EXTINT6_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ6, \
#define EXTINT6_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT6_IRQ_NUM, \
.irq_prio = BSP_EXTINT6_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ6, \
}
#endif /* EXTINT6_IRQ_CONFIG */
#ifndef EXTINT7_IRQ_CONFIG
#define EXTINT7_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT7_IRQ_NUM, \
.irq_prio = BSP_EXTINT7_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ7, \
#define EXTINT7_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT7_IRQ_NUM, \
.irq_prio = BSP_EXTINT7_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ7, \
}
#endif /* EXTINT7_IRQ_CONFIG */
#ifndef EXTINT8_IRQ_CONFIG
#define EXTINT8_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT8_IRQ_NUM, \
.irq_prio = BSP_EXTINT8_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ8, \
#define EXTINT8_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT8_IRQ_NUM, \
.irq_prio = BSP_EXTINT8_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ8, \
}
#endif /* EXTINT8_IRQ_CONFIG */
#ifndef EXTINT9_IRQ_CONFIG
#define EXTINT9_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT9_IRQ_NUM, \
.irq_prio = BSP_EXTINT9_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ9, \
#define EXTINT9_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT9_IRQ_NUM, \
.irq_prio = BSP_EXTINT9_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ9, \
}
#endif /* EXTINT9_IRQ_CONFIG */
#ifndef EXTINT10_IRQ_CONFIG
#define EXTINT10_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT10_IRQ_NUM, \
.irq_prio = BSP_EXTINT10_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ10, \
#define EXTINT10_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT10_IRQ_NUM, \
.irq_prio = BSP_EXTINT10_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ10, \
}
#endif /* EXTINT10_IRQ_CONFIG */
#ifndef EXTINT11_IRQ_CONFIG
#define EXTINT11_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT11_IRQ_NUM, \
.irq_prio = BSP_EXTINT11_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ11, \
#define EXTINT11_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT11_IRQ_NUM, \
.irq_prio = BSP_EXTINT11_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ11, \
}
#endif /* EXTINT11_IRQ_CONFIG */
#ifndef EXTINT12_IRQ_CONFIG
#define EXTINT12_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT12_IRQ_NUM, \
.irq_prio = BSP_EXTINT12_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ12, \
#define EXTINT12_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT12_IRQ_NUM, \
.irq_prio = BSP_EXTINT12_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ12, \
}
#endif /* EXTINT12_IRQ_CONFIG */
#ifndef EXTINT13_IRQ_CONFIG
#define EXTINT13_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT13_IRQ_NUM, \
.irq_prio = BSP_EXTINT13_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ13, \
#define EXTINT13_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT13_IRQ_NUM, \
.irq_prio = BSP_EXTINT13_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ13, \
}
#endif /* EXTINT13_IRQ_CONFIG */
#ifndef EXTINT14_IRQ_CONFIG
#define EXTINT14_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT14_IRQ_NUM, \
.irq_prio = BSP_EXTINT14_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ14, \
#define EXTINT14_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT14_IRQ_NUM, \
.irq_prio = BSP_EXTINT14_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ14, \
}
#endif /* EXTINT14_IRQ_CONFIG */
#ifndef EXTINT15_IRQ_CONFIG
#define EXTINT15_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT15_IRQ_NUM, \
.irq_prio = BSP_EXTINT15_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ15, \
#define EXTINT15_IRQ_CONFIG \
{ \
.irq_num = BSP_EXTINT15_IRQ_NUM, \
.irq_prio = BSP_EXTINT15_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ15, \
}
#endif /* EXTINT15_IRQ_CONFIG */

204
bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/i2c_config.h
View File

@ -20,101 +20,97 @@ extern "C" {
#if defined(BSP_USING_I2C1)
#ifndef I2C1_CONFIG
#define I2C1_CONFIG \
{ \
.name = "i2c1", \
.Instance = CM_I2C1, \
.clock = FCG1_PERIPH_I2C1, \
.baudrate = 100000UL, \
.timeout = 10000UL, \
#define I2C1_CONFIG \
{ \
.name = "i2c1", \
.Instance = CM_I2C1, \
.clock = FCG1_PERIPH_I2C1, \
.baudrate = 100000UL, \
.timeout = 10000UL, \
}
#endif /* I2C1_CONFIG */
#endif
#if defined(BSP_I2C1_USING_DMA)
#ifndef I2C1_TX_DMA_CONFIG
#define I2C1_TX_DMA_CONFIG \
{ \
.Instance = I2C1_TX_DMA_INSTANCE, \
.channel = I2C1_TX_DMA_CHANNEL, \
.clock = I2C1_TX_DMA_CLOCK, \
.trigger_select = I2C1_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C1_TEI, \
.flag = I2C1_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = I2C1_TX_DMA_IRQn, \
.irq_prio = I2C1_TX_DMA_INT_PRIO, \
.int_src = I2C1_TX_DMA_INT_SRC, \
}, \
#define I2C1_TX_DMA_CONFIG \
{ \
.Instance = I2C1_TX_DMA_INSTANCE, \
.channel = I2C1_TX_DMA_CHANNEL, \
.clock = I2C1_TX_DMA_CLOCK, \
.trigger_select = I2C1_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C1_TEI, \
.flag = I2C1_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = I2C1_TX_DMA_IRQn, \
.irq_prio = I2C1_TX_DMA_INT_PRIO, \
.int_src = I2C1_TX_DMA_INT_SRC, \
}, \
}
#endif /* I2C1_TX_DMA_CONFIG */
#ifndef I2C1_RX_DMA_CONFIG
#define I2C1_RX_DMA_CONFIG \
{ \
.Instance = I2C1_RX_DMA_INSTANCE, \
.channel = I2C1_RX_DMA_CHANNEL, \
.clock = I2C1_RX_DMA_CLOCK, \
.trigger_select = I2C1_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C1_RXI, \
.flag = I2C1_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = I2C1_RX_DMA_IRQn, \
.irq_prio = I2C1_RX_DMA_INT_PRIO, \
.int_src = I2C1_RX_DMA_INT_SRC, \
}, \
#define I2C1_RX_DMA_CONFIG \
{ \
.Instance = I2C1_RX_DMA_INSTANCE, \
.channel = I2C1_RX_DMA_CHANNEL, \
.clock = I2C1_RX_DMA_CLOCK, \
.trigger_select = I2C1_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C1_RXI, \
.flag = I2C1_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = I2C1_RX_DMA_IRQn, \
.irq_prio = I2C1_RX_DMA_INT_PRIO, \
.int_src = I2C1_RX_DMA_INT_SRC, \
}, \
}
#endif /* I2C1_RX_DMA_CONFIG */
#endif /* BSP_I2C1_USING_DMA */
#if defined(BSP_USING_I2C2)
#ifndef I2C2_CONFIG
#define I2C2_CONFIG \
{ \
.name = "i2c2", \
.Instance = CM_I2C2, \
.clock = FCG1_PERIPH_I2C2, \
.baudrate = 100000UL, \
.timeout = 10000UL, \
#define I2C2_CONFIG \
{ \
.name = "i2c2", \
.Instance = CM_I2C2, \
.clock = FCG1_PERIPH_I2C2, \
.baudrate = 100000UL, \
.timeout = 10000UL, \
}
#endif /* I2C2_CONFIG */
#if defined(BSP_I2C2_USING_DMA)
#ifndef I2C2_TX_DMA_CONFIG
#define I2C2_TX_DMA_CONFIG \
{ \
.Instance = I2C2_TX_DMA_INSTANCE, \
.channel = I2C2_TX_DMA_CHANNEL, \
.clock = I2C2_TX_DMA_CLOCK, \
.trigger_select = I2C2_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C2_TEI, \
.flag = I2C2_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = I2C2_TX_DMA_IRQn, \
.irq_prio = I2C2_TX_DMA_INT_PRIO, \
.int_src = I2C2_TX_DMA_INT_SRC, \
}, \
#define I2C2_TX_DMA_CONFIG \
{ \
.Instance = I2C2_TX_DMA_INSTANCE, \
.channel = I2C2_TX_DMA_CHANNEL, \
.clock = I2C2_TX_DMA_CLOCK, \
.trigger_select = I2C2_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C2_TEI, \
.flag = I2C2_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = I2C2_TX_DMA_IRQn, \
.irq_prio = I2C2_TX_DMA_INT_PRIO, \
.int_src = I2C2_TX_DMA_INT_SRC, \
}, \
}
#endif /* I2C2_TX_DMA_CONFIG */
#ifndef I2C2_RX_DMA_CONFIG
#define I2C2_RX_DMA_CONFIG \
{ \
.Instance = I2C2_RX_DMA_INSTANCE, \
.channel = I2C2_RX_DMA_CHANNEL, \
.clock = I2C2_RX_DMA_CLOCK, \
.trigger_select = I2C2_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C2_RXI, \
.flag = I2C2_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = I2C2_RX_DMA_IRQn, \
.irq_prio = I2C2_RX_DMA_INT_PRIO, \
.int_src = I2C2_RX_DMA_INT_SRC, \
}, \
#define I2C2_RX_DMA_CONFIG \
{ \
.Instance = I2C2_RX_DMA_INSTANCE, \
.channel = I2C2_RX_DMA_CHANNEL, \
.clock = I2C2_RX_DMA_CLOCK, \
.trigger_select = I2C2_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C2_RXI, \
.flag = I2C2_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = I2C2_RX_DMA_IRQn, \
.irq_prio = I2C2_RX_DMA_INT_PRIO, \
.int_src = I2C2_RX_DMA_INT_SRC, \
}, \
}
#endif /* I2C2_RX_DMA_CONFIG */
#endif /* BSP_I2C2_USING_DMA */
@ -122,50 +118,48 @@ extern "C" {
#if defined(BSP_USING_I2C3)
#ifndef I2C3_CONFIG
#define I2C3_CONFIG \
{ \
.name = "i2c3", \
.Instance = CM_I2C3, \
.clock = FCG1_PERIPH_I2C3, \
.baudrate = 100000UL, \
.timeout = 10000UL, \
#define I2C3_CONFIG \
{ \
.name = "i2c3", \
.Instance = CM_I2C3, \
.clock = FCG1_PERIPH_I2C3, \
.baudrate = 100000UL, \
.timeout = 10000UL, \
}
#endif /* I2C3_CONFIG */
#if defined(BSP_I2C3_USING_DMA)
#ifndef I2C3_TX_DMA_CONFIG
#define I2C3_TX_DMA_CONFIG \
{ \
.Instance = I2C3_TX_DMA_INSTANCE, \
.channel = I2C3_TX_DMA_CHANNEL, \
.clock = I2C3_TX_DMA_CLOCK, \
.trigger_select = I2C3_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C3_TEI, \
.flag = I2C3_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = I2C3_TX_DMA_IRQn, \
.irq_prio = I2C3_TX_DMA_INT_PRIO, \
.int_src = I2C3_TX_DMA_INT_SRC, \
}, \
#define I2C3_TX_DMA_CONFIG \
{ \
.Instance = I2C3_TX_DMA_INSTANCE, \
.channel = I2C3_TX_DMA_CHANNEL, \
.clock = I2C3_TX_DMA_CLOCK, \
.trigger_select = I2C3_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C3_TEI, \
.flag = I2C3_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = I2C3_TX_DMA_IRQn, \
.irq_prio = I2C3_TX_DMA_INT_PRIO, \
.int_src = I2C3_TX_DMA_INT_SRC, \
}, \
}
#endif /* I2C3_TX_DMA_CONFIG */
#ifndef I2C3_RX_DMA_CONFIG
#define I2C3_RX_DMA_CONFIG \
{ \
.Instance = I2C3_RX_DMA_INSTANCE, \
.channel = I2C3_RX_DMA_CHANNEL, \
.clock = I2C3_RX_DMA_CLOCK, \
.trigger_select = I2C3_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C3_RXI, \
.flag = I2C3_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = I2C3_RX_DMA_IRQn, \
.irq_prio = I2C3_RX_DMA_INT_PRIO, \
.int_src = I2C3_RX_DMA_INT_SRC, \
}, \
#define I2C3_RX_DMA_CONFIG \
{ \
.Instance = I2C3_RX_DMA_INSTANCE, \
.channel = I2C3_RX_DMA_CHANNEL, \
.clock = I2C3_RX_DMA_CLOCK, \
.trigger_select = I2C3_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C3_RXI, \
.flag = I2C3_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = I2C3_RX_DMA_IRQn, \
.irq_prio = I2C3_RX_DMA_INT_PRIO, \
.int_src = I2C3_RX_DMA_INT_SRC, \
}, \
}
#endif /* I2C3_RX_DMA_CONFIG */
#endif /* BSP_I2C3_USING_DMA */

370
bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/irq_config.h
View File

@ -17,316 +17,316 @@
extern "C" {
#endif
#define BSP_EXTINT0_IRQ_NUM INT022_IRQn
#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT1_IRQ_NUM INT023_IRQn
#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT2_IRQ_NUM INT024_IRQn
#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT3_IRQ_NUM INT025_IRQn
#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT4_IRQ_NUM INT026_IRQn
#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT5_IRQ_NUM INT027_IRQn
#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT6_IRQ_NUM INT028_IRQn
#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT7_IRQ_NUM INT029_IRQn
#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT8_IRQ_NUM INT030_IRQn
#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT9_IRQ_NUM INT031_IRQn
#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT10_IRQ_NUM INT032_IRQn
#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT11_IRQ_NUM INT033_IRQn
#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT12_IRQ_NUM INT034_IRQn
#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT13_IRQ_NUM INT035_IRQn
#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT14_IRQ_NUM INT036_IRQn
#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT15_IRQ_NUM INT037_IRQn
#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT0_IRQ_NUM INT022_IRQn
#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT1_IRQ_NUM INT023_IRQn
#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT2_IRQ_NUM INT024_IRQn
#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT3_IRQ_NUM INT025_IRQn
#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT4_IRQ_NUM INT026_IRQn
#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT5_IRQ_NUM INT027_IRQn
#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT6_IRQ_NUM INT028_IRQn
#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT7_IRQ_NUM INT029_IRQn
#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT8_IRQ_NUM INT030_IRQn
#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT9_IRQ_NUM INT031_IRQn
#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT10_IRQ_NUM INT032_IRQn
#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT11_IRQ_NUM INT033_IRQn
#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT12_IRQ_NUM INT034_IRQn
#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT13_IRQ_NUM INT035_IRQn
#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT14_IRQ_NUM INT036_IRQn
#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT15_IRQ_NUM INT037_IRQn
#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch0 */
#define BSP_DMA1_CH0_IRQ_NUM INT038_IRQn
#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA1_CH0_IRQ_NUM INT038_IRQn
#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch1 */
#define BSP_DMA1_CH1_IRQ_NUM INT039_IRQn
#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA1_CH1_IRQ_NUM INT039_IRQn
#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch2 */
#define BSP_DMA1_CH2_IRQ_NUM INT040_IRQn
#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA1_CH2_IRQ_NUM INT040_IRQn
#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch3 */
#define BSP_DMA1_CH3_IRQ_NUM INT041_IRQn
#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA1_CH3_IRQ_NUM INT041_IRQn
#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA2 ch0 */
#define BSP_DMA2_CH0_IRQ_NUM INT042_IRQn
#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA2_CH0_IRQ_NUM INT042_IRQn
#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA2 ch1 */
#define BSP_DMA2_CH1_IRQ_NUM INT043_IRQn
#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA2_CH1_IRQ_NUM INT043_IRQn
#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA2 ch2 */
#define BSP_DMA2_CH2_IRQ_NUM INT020_IRQn
#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA2_CH2_IRQ_NUM INT020_IRQn
#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA2 ch3 */
#define BSP_DMA2_CH3_IRQ_NUM INT021_IRQn
#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_DMA2_CH3_IRQ_NUM INT021_IRQn
#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if defined(BSP_USING_UART1)
#define BSP_UART1_RXERR_IRQ_NUM INT012_IRQn
#define BSP_UART1_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART1_RX_IRQ_NUM INT082_IRQn
#define BSP_UART1_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART1_TX_IRQ_NUM INT081_IRQn
#define BSP_UART1_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART1_RXERR_IRQ_NUM INT012_IRQn
#define BSP_UART1_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART1_RX_IRQ_NUM INT082_IRQn
#define BSP_UART1_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART1_TX_IRQ_NUM INT081_IRQn
#define BSP_UART1_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if defined(BSP_UART1_RX_USING_DMA)
#define BSP_UART1_RXTO_IRQ_NUM INT013_IRQn
#define BSP_UART1_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART1_RXTO_IRQ_NUM INT013_IRQn
#define BSP_UART1_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)
#define BSP_UART1_TX_CPLT_IRQ_NUM INT080_IRQn
#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART1_TX_CPLT_IRQ_NUM INT080_IRQn
#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#elif defined(RT_USING_SERIAL_V2)
#define BSP_UART1_TX_CPLT_IRQ_NUM INT080_IRQn
#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART1_TX_CPLT_IRQ_NUM INT080_IRQn
#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#endif /* BSP_USING_UART1 */
#if defined(BSP_USING_UART2)
#define BSP_UART2_RXERR_IRQ_NUM INT014_IRQn
#define BSP_UART2_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART2_RX_IRQ_NUM INT085_IRQn
#define BSP_UART2_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART2_TX_IRQ_NUM INT084_IRQn
#define BSP_UART2_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART2_RXERR_IRQ_NUM INT014_IRQn
#define BSP_UART2_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART2_RX_IRQ_NUM INT085_IRQn
#define BSP_UART2_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART2_TX_IRQ_NUM INT084_IRQn
#define BSP_UART2_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if defined(BSP_UART2_RX_USING_DMA)
#define BSP_UART2_RXTO_IRQ_NUM INT015_IRQn
#define BSP_UART2_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART2_RXTO_IRQ_NUM INT015_IRQn
#define BSP_UART2_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)
#define BSP_UART2_TX_CPLT_IRQ_NUM INT083_IRQn
#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART2_TX_CPLT_IRQ_NUM INT083_IRQn
#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#elif defined(RT_USING_SERIAL_V2)
#define BSP_UART2_TX_CPLT_IRQ_NUM INT083_IRQn
#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART2_TX_CPLT_IRQ_NUM INT083_IRQn
#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#endif /* BSP_USING_UART2 */
#if defined(BSP_USING_UART3)
#define BSP_UART3_RXERR_IRQ_NUM INT016_IRQn
#define BSP_UART3_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART3_RX_IRQ_NUM INT088_IRQn
#define BSP_UART3_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART3_TX_IRQ_NUM INT087_IRQn
#define BSP_UART3_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART3_RXERR_IRQ_NUM INT016_IRQn
#define BSP_UART3_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART3_RX_IRQ_NUM INT088_IRQn
#define BSP_UART3_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART3_TX_IRQ_NUM INT087_IRQn
#define BSP_UART3_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if defined(BSP_UART3_RX_USING_DMA)
#define BSP_UART3_RXTO_IRQ_NUM INT017_IRQn
#define BSP_UART3_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART3_RXTO_IRQ_NUM INT017_IRQn
#define BSP_UART3_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART3_TX_USING_DMA)
#define BSP_UART3_TX_CPLT_IRQ_NUM INT086_IRQn
#define BSP_UART3_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART3_TX_CPLT_IRQ_NUM INT086_IRQn
#define BSP_UART3_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#elif defined(RT_USING_SERIAL_V2)
#define BSP_UART3_TX_CPLT_IRQ_NUM INT086_IRQn
#define BSP_UART3_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART3_TX_CPLT_IRQ_NUM INT086_IRQn
#define BSP_UART3_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#endif /* BSP_USING_UART3 */
#if defined(BSP_USING_UART4)
#define BSP_UART4_RXERR_IRQ_NUM INT018_IRQn
#define BSP_UART4_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART4_RX_IRQ_NUM INT091_IRQn
#define BSP_UART4_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART4_TX_IRQ_NUM INT090_IRQn
#define BSP_UART4_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART4_RXERR_IRQ_NUM INT018_IRQn
#define BSP_UART4_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART4_RX_IRQ_NUM INT091_IRQn
#define BSP_UART4_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART4_TX_IRQ_NUM INT090_IRQn
#define BSP_UART4_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if defined(BSP_UART4_RX_USING_DMA)
#define BSP_UART4_RXTO_IRQ_NUM INT019_IRQn
#define BSP_UART4_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART4_RXTO_IRQ_NUM INT019_IRQn
#define BSP_UART4_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)
#define BSP_UART4_TX_CPLT_IRQ_NUM INT089_IRQn
#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART4_TX_CPLT_IRQ_NUM INT089_IRQn
#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#elif defined(RT_USING_SERIAL_V2)
#define BSP_UART4_TX_CPLT_IRQ_NUM INT089_IRQn
#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART4_TX_CPLT_IRQ_NUM INT089_IRQn
#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#endif /* BSP_USING_UART4 */
#if defined(BSP_USING_SPI1)
#define BSP_SPI1_ERR_IRQ_NUM INT008_IRQn
#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_SPI1_ERR_IRQ_NUM INT008_IRQn
#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#if defined(BSP_USING_SPI2)
#define BSP_SPI2_ERR_IRQ_NUM INT009_IRQn
#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_SPI2_ERR_IRQ_NUM INT009_IRQn
#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#if defined(BSP_USING_SPI3)
#define BSP_SPI3_ERR_IRQ_NUM INT010_IRQn
#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_SPI3_ERR_IRQ_NUM INT010_IRQn
#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#if defined(BSP_USING_SPI4)
#define BSP_SPI4_ERR_IRQ_NUM INT011_IRQn
#define BSP_SPI4_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_SPI4_ERR_IRQ_NUM INT011_IRQn
#define BSP_SPI4_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#if defined(BSP_USING_CAN1)
#define BSP_CAN1_IRQ_NUM INT126_IRQn
#define BSP_CAN1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_CAN1_IRQ_NUM INT126_IRQn
#define BSP_CAN1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif /* BSP_USING_CAN1 */
#if defined(BSP_USING_SDIO1)
#define BSP_SDIO1_IRQ_NUM INT122_IRQn
#define BSP_SDIO1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_SDIO1_IRQ_NUM INT122_IRQn
#define BSP_SDIO1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif /* BSP_USING_SDIO1 */
#if defined(BSP_USING_SDIO2)
#define BSP_SDIO2_IRQ_NUM INT124_IRQn
#define BSP_SDIO2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_SDIO2_IRQ_NUM INT124_IRQn
#define BSP_SDIO2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif /* BSP_USING_SDIO2 */
#if defined(RT_USING_ALARM)
#define BSP_RTC_ALARM_IRQ_NUM INT044_IRQn
#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_RTC_ALARM_IRQ_NUM INT044_IRQn
#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* RT_USING_ALARM */
#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB)
#define BSP_USBFS_GLB_IRQ_NUM INT003_IRQn
#define BSP_USBFS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_USBFS_GLB_IRQ_NUM INT003_IRQn
#define BSP_USBFS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_USBD */
#if defined (BSP_USING_QSPI)
#define BSP_QSPI_ERR_IRQ_NUM INT004_IRQn
#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if defined(BSP_USING_QSPI)
#define BSP_QSPI_ERR_IRQ_NUM INT004_IRQn
#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif /* BSP_USING_QSPI */
#if defined(BSP_USING_TMRA_1)
#define BSP_USING_TMRA_1_IRQ_NUM INT080_IRQn
#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_USING_TMRA_1_IRQ_NUM INT080_IRQn
#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_1 */
#if defined(BSP_USING_TMRA_2)
#define BSP_USING_TMRA_2_IRQ_NUM INT081_IRQn
#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_USING_TMRA_2_IRQ_NUM INT081_IRQn
#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_2 */
#if defined(BSP_USING_TMRA_3)
#define BSP_USING_TMRA_3_IRQ_NUM INT082_IRQn
#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_USING_TMRA_3_IRQ_NUM INT082_IRQn
#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_3 */
#if defined(BSP_USING_TMRA_4)
#define BSP_USING_TMRA_4_IRQ_NUM INT083_IRQn
#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_USING_TMRA_4_IRQ_NUM INT083_IRQn
#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_4 */
#if defined(BSP_USING_TMRA_5)
#define BSP_USING_TMRA_5_IRQ_NUM INT084_IRQn
#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_USING_TMRA_5_IRQ_NUM INT084_IRQn
#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_5 */
#if defined(BSP_USING_TMRA_6)
#define BSP_USING_TMRA_6_IRQ_NUM INT085_IRQn
#define BSP_USING_TMRA_6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_USING_TMRA_6_IRQ_NUM INT085_IRQn
#define BSP_USING_TMRA_6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_6 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM INT080_IRQn
#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM INT081_IRQn
#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM INT080_IRQn
#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM INT081_IRQn
#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_2)
#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM INT082_IRQn
#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM INT083_IRQn
#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM INT082_IRQn
#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM INT083_IRQn
#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_3)
#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM INT084_IRQn
#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM INT085_IRQn
#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM INT084_IRQn
#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM INT085_IRQn
#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_4)
#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM INT080_IRQn
#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM INT081_IRQn
#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM INT080_IRQn
#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM INT081_IRQn
#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_5)
#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM INT082_IRQn
#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM INT083_IRQn
#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM INT082_IRQn
#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM INT083_IRQn
#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_6)
#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM INT084_IRQn
#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM INT085_IRQn
#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM INT084_IRQn
#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM INT085_IRQn
#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_6 */
#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM INT050_IRQn
#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM INT051_IRQn
#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM INT050_IRQn
#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM INT051_IRQn
#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */
#if defined(BSP_USING_PULSE_ENCODER_TMR6_2)
#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM INT052_IRQn
#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM INT053_IRQn
#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM INT052_IRQn
#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM INT053_IRQn
#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */
#if defined(BSP_USING_PULSE_ENCODER_TMR6_3)
#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM INT054_IRQn
#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM INT055_IRQn
#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM INT054_IRQn
#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM INT055_IRQn
#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMR6_3 */
#if defined(BSP_USING_TMR0_1A)
#define BSP_USING_TMR0_1A_IRQ_NUM INT046_IRQn
#define BSP_USING_TMR0_1A_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_USING_TMR0_1A_IRQ_NUM INT046_IRQn
#define BSP_USING_TMR0_1A_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMR0_1A */
#if defined(BSP_USING_TMR0_1B)
#define BSP_USING_TMR0_1B_IRQ_NUM INT047_IRQn
#define BSP_USING_TMR0_1B_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_USING_TMR0_1B_IRQ_NUM INT047_IRQn
#define BSP_USING_TMR0_1B_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMR0_1B */
#if defined(BSP_USING_TMR0_2A)
#define BSP_USING_TMR0_2A_IRQ_NUM INT048_IRQn
#define BSP_USING_TMR0_2A_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_USING_TMR0_2A_IRQ_NUM INT048_IRQn
#define BSP_USING_TMR0_2A_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMR0_2A */
#if defined(BSP_USING_TMR0_2B)
#define BSP_USING_TMR0_2B_IRQ_NUM INT049_IRQn
#define BSP_USING_TMR0_2B_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_USING_TMR0_2B_IRQ_NUM INT049_IRQn
#define BSP_USING_TMR0_2B_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMR0_2B */
#if defined(BSP_USING_INPUT_CAPTURE)
#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT012_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT013_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT012_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT013_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT014_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT015_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT014_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT015_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM (INT016_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM (INT017_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM (INT016_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM (INT017_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#endif
#ifdef __cplusplus

66
bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/pm_config.h
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@ -23,16 +23,16 @@ extern "C" {
extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
#ifndef PM_TICKLESS_TIMER_ENABLE_MASK
#define PM_TICKLESS_TIMER_ENABLE_MASK (0UL)
#define PM_TICKLESS_TIMER_ENABLE_MASK (0UL)
#endif
/**
* @brief run mode config @ref pm_run_mode_config structure
*/
#ifndef PM_RUN_MODE_CFG
#define PM_RUN_MODE_CFG \
{ \
.sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \
#define PM_RUN_MODE_CFG \
{ \
.sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \
}
#endif /* PM_RUN_MODE_CFG */
@ -40,53 +40,53 @@ extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
* @brief sleep idle config @ref pm_sleep_mode_idle_config structure
*/
#ifndef PM_SLEEP_IDLE_CFG
#define PM_SLEEP_IDLE_CFG \
{ \
.pwc_sleep_type = PWC_SLEEP_WFE_INT, \
}
#define PM_SLEEP_IDLE_CFG \
{ \
.pwc_sleep_type = PWC_SLEEP_WFE_INT, \
}
#endif /*PM_SLEEP_IDLE_CFG*/
/**
* @brief sleep deep config @ref pm_sleep_mode_deep_config structure
*/
#ifndef PM_SLEEP_DEEP_CFG
#define PM_SLEEP_DEEP_CFG \
{ \
{ \
.u16Clock = PWC_STOP_CLK_KEEP, \
.u8StopDrv = PWC_STOP_DRV_HIGH, \
.u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \
}, \
.pwc_stop_type = PWC_STOP_WFE_INT, \
}
#define PM_SLEEP_DEEP_CFG \
{ \
{ \
.u16Clock = PWC_STOP_CLK_KEEP, \
.u8StopDrv = PWC_STOP_DRV_HIGH, \
.u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \
}, \
.pwc_stop_type = PWC_STOP_WFE_INT, \
}
#endif /*PM_SLEEP_DEEP_CFG*/
/**
* @brief sleep standby config @ref pm_sleep_mode_standby_config structure
*/
#ifndef PM_SLEEP_STANDBY_CFG
#define PM_SLEEP_STANDBY_CFG \
{ \
{ \
.u8Mode = PWC_PD_MD1, \
.u8IOState = PWC_PD_IO_KEEP1, \
.u8VcapCtrl = PWC_PD_VCAP_0P047UF, \
}, \
}
#define PM_SLEEP_STANDBY_CFG \
{ \
{ \
.u8Mode = PWC_PD_MD1, \
.u8IOState = PWC_PD_IO_KEEP1, \
.u8VcapCtrl = PWC_PD_VCAP_0P047UF, \
}, \
}
#endif /*PM_SLEEP_STANDBY_CFG*/
/**
* @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure
*/
#ifndef PM_SLEEP_SHUTDOWN_CFG
#define PM_SLEEP_SHUTDOWN_CFG \
{ \
{ \
.u8Mode = PWC_PD_MD3, \
.u8IOState = PWC_PD_IO_KEEP1, \
.u8VcapCtrl = PWC_PD_VCAP_0P047UF, \
}, \
}
#define PM_SLEEP_SHUTDOWN_CFG \
{ \
{ \
.u8Mode = PWC_PD_MD3, \
.u8IOState = PWC_PD_IO_KEEP1, \
.u8VcapCtrl = PWC_PD_VCAP_0P047UF, \
}, \
}
#endif /*PM_SLEEP_SHUTDOWN_CFG*/
#endif /* BSP_USING_PM */

342
bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/pulse_encoder_config.h
View File

@ -21,234 +21,216 @@ extern "C" {
#ifdef BSP_USING_PULSE_ENCODER_TMRA_1
#ifndef PULSE_ENCODER_TMRA_1_CONFIG
#define PULSE_ENCODER_TMRA_1_CONFIG \
{ \
.tmr_handler = CM_TMRA_1, \
.u32PeriphClock = FCG2_PERIPH_TMRA_1, \
.hw_count = \
{ \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = \
{ \
.enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a1" \
#define PULSE_ENCODER_TMRA_1_CONFIG \
{ \
.tmr_handler = CM_TMRA_1, \
.u32PeriphClock = FCG2_PERIPH_TMRA_1, \
.hw_count = { \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = { \
.enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a1" \
}
#endif /* PULSE_ENCODER_TMRA_1_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
#ifdef BSP_USING_PULSE_ENCODER_TMRA_2
#ifndef PULSE_ENCODER_TMRA_2_CONFIG
#define PULSE_ENCODER_TMRA_2_CONFIG \
{ \
.tmr_handler = CM_TMRA_2, \
.u32PeriphClock = FCG2_PERIPH_TMRA_2, \
.hw_count = \
{ \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = \
{ \
.enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a2" \
#define PULSE_ENCODER_TMRA_2_CONFIG \
{ \
.tmr_handler = CM_TMRA_2, \
.u32PeriphClock = FCG2_PERIPH_TMRA_2, \
.hw_count = { \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = { \
.enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a2" \
}
#endif /* PULSE_ENCODER_TMRA_2_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */
#ifdef BSP_USING_PULSE_ENCODER_TMRA_3
#ifndef PULSE_ENCODER_TMRA_3_CONFIG
#define PULSE_ENCODER_TMRA_3_CONFIG \
{ \
.tmr_handler = CM_TMRA_3, \
.u32PeriphClock = FCG2_PERIPH_TMRA_3, \
.hw_count = \
{ \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = \
{ \
.enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a3" \
#define PULSE_ENCODER_TMRA_3_CONFIG \
{ \
.tmr_handler = CM_TMRA_3, \
.u32PeriphClock = FCG2_PERIPH_TMRA_3, \
.hw_count = { \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = { \
.enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a3" \
}
#endif /* PULSE_ENCODER_TMRA_3_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */
#ifdef BSP_USING_PULSE_ENCODER_TMRA_4
#ifndef PULSE_ENCODER_TMRA_4_CONFIG
#define PULSE_ENCODER_TMRA_4_CONFIG \
{ \
.tmr_handler = CM_TMRA_4, \
.u32PeriphClock = FCG2_PERIPH_TMRA_4, \
.hw_count = \
{ \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = \
{ \
.enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a4" \
#define PULSE_ENCODER_TMRA_4_CONFIG \
{ \
.tmr_handler = CM_TMRA_4, \
.u32PeriphClock = FCG2_PERIPH_TMRA_4, \
.hw_count = { \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = { \
.enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a4" \
}
#endif /* PULSE_ENCODER_TMRA_4_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */
#ifdef BSP_USING_PULSE_ENCODER_TMRA_5
#ifndef PULSE_ENCODER_TMRA_5_CONFIG
#define PULSE_ENCODER_TMRA_5_CONFIG \
{ \
.tmr_handler = CM_TMRA_5, \
.u32PeriphClock = FCG2_PERIPH_TMRA_5, \
.hw_count = \
{ \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = \
{ \
.enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a5" \
#define PULSE_ENCODER_TMRA_5_CONFIG \
{ \
.tmr_handler = CM_TMRA_5, \
.u32PeriphClock = FCG2_PERIPH_TMRA_5, \
.hw_count = { \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = { \
.enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a5" \
}
#endif /* PULSE_ENCODER_TMRA_5_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */
#ifdef BSP_USING_PULSE_ENCODER_TMRA_6
#ifndef PULSE_ENCODER_TMRA_6_CONFIG
#define PULSE_ENCODER_TMRA_6_CONFIG \
{ \
.tmr_handler = CM_TMRA_6, \
.u32PeriphClock = FCG2_PERIPH_TMRA_6, \
.hw_count = \
{ \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = \
{ \
.enIntSrc_Ovf = INT_SRC_TMRA_6_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_6_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a6" \
#define PULSE_ENCODER_TMRA_6_CONFIG \
{ \
.tmr_handler = CM_TMRA_6, \
.u32PeriphClock = FCG2_PERIPH_TMRA_6, \
.hw_count = { \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
}, \
.isr = { \
.enIntSrc_Ovf = INT_SRC_TMRA_6_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMRA_6_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_a6" \
}
#endif /* PULSE_ENCODER_TMRA_6_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_6 */
#ifdef BSP_USING_PULSE_ENCODER_TMR6_1
#ifndef PULSE_ENCODER_TMR6_1_CONFIG
#define PULSE_ENCODER_TMR6_1_CONFIG \
{ \
.tmr_handler = CM_TMR6_1, \
.u32PeriphClock = FCG2_PERIPH_TMR6_1, \
.hw_count = \
{ \
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
}, \
.isr = \
{ \
.enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_61" \
#define PULSE_ENCODER_TMR6_1_CONFIG \
{ \
.tmr_handler = CM_TMR6_1, \
.u32PeriphClock = FCG2_PERIPH_TMR6_1, \
.hw_count = { \
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
}, \
.isr = { \
.enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_61" \
}
#endif /* PULSE_ENCODER_TMR6_1_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
#ifdef BSP_USING_PULSE_ENCODER_TMR6_2
#ifndef PULSE_ENCODER_TMR6_2_CONFIG
#define PULSE_ENCODER_TMR6_2_CONFIG \
{ \
.tmr_handler = CM_TMR6_2, \
.u32PeriphClock = FCG2_PERIPH_TMR6_2, \
.hw_count = \
{ \
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
}, \
.isr = \
{ \
.enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_62" \
#define PULSE_ENCODER_TMR6_2_CONFIG \
{ \
.tmr_handler = CM_TMR6_2, \
.u32PeriphClock = FCG2_PERIPH_TMR6_2, \
.hw_count = { \
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
}, \
.isr = { \
.enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_62" \
}
#endif /* PULSE_ENCODER_TMR6_2_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */
#ifdef BSP_USING_PULSE_ENCODER_TMR6_3
#ifndef PULSE_ENCODER_TMR6_3_CONFIG
#define PULSE_ENCODER_TMR6_3_CONFIG \
{ \
.tmr_handler = CM_TMR6_3, \
.u32PeriphClock = FCG2_PERIPH_TMR6_3, \
.hw_count = \
{ \
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
}, \
.isr = \
{ \
.enIntSrc_Ovf = INT_SRC_TMR6_3_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMR6_3_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_63" \
#define PULSE_ENCODER_TMR6_3_CONFIG \
{ \
.tmr_handler = CM_TMR6_3, \
.u32PeriphClock = FCG2_PERIPH_TMR6_3, \
.hw_count = { \
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
}, \
.isr = { \
.enIntSrc_Ovf = INT_SRC_TMR6_3_OVF, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO, \
.enIntSrc_Udf = INT_SRC_TMR6_3_UDF, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO, \
}, \
.u32PeriodValue = 1000UL, \
.name = "pulse_63" \
}
#endif /* PULSE_ENCODER_TMR6_3_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMR6_3 */

612
bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/pwm_tmr_config.h
View File

@ -21,180 +21,162 @@ extern "C" {
#ifdef BSP_USING_PWM_TMRA_1
#ifndef PWM_TMRA_1_CONFIG
#define PWM_TMRA_1_CONFIG \
{ \
.name = "pwm_a1", \
.instance = CM_TMRA_1, \
.channel = 0, \
.stcTmraInit = \
{ \
.u8CountSrc = TMRA_CNT_SRC_SW, \
.u32PeriodValue = 0xFFFF, \
.sw_count = \
{ \
.u8ClockDiv = TMRA_CLK_DIV1, \
.u8CountMode = TMRA_MD_SAWTOOTH, \
.u8CountDir = TMRA_DIR_DOWN, \
}, \
}, \
.stcPwmInit = \
{ \
.u32CompareValue = 0x0000, \
.u16StartPolarity = TMRA_PWM_LOW, \
.u16StopPolarity = TMRA_PWM_LOW, \
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
}, \
#define PWM_TMRA_1_CONFIG \
{ \
.name = "pwm_a1", \
.instance = CM_TMRA_1, \
.channel = 0, \
.stcTmraInit = { \
.u8CountSrc = TMRA_CNT_SRC_SW, \
.u32PeriodValue = 0xFFFF, \
.sw_count = { \
.u8ClockDiv = TMRA_CLK_DIV1, \
.u8CountMode = TMRA_MD_SAWTOOTH, \
.u8CountDir = TMRA_DIR_DOWN, \
}, \
}, \
.stcPwmInit = { \
.u32CompareValue = 0x0000, \
.u16StartPolarity = TMRA_PWM_LOW, \
.u16StopPolarity = TMRA_PWM_LOW, \
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
}, \
}
#endif /* PWM_TMRA_1_CONFIG */
#endif /* BSP_USING_PWM_TMRA_1 */
#ifdef BSP_USING_PWM_TMRA_2
#ifndef PWM_TMRA_2_CONFIG
#define PWM_TMRA_2_CONFIG \
{ \
.name = "pwm_a2", \
.instance = CM_TMRA_2, \
.channel = 0, \
.stcTmraInit = \
{ \
.u8CountSrc = TMRA_CNT_SRC_SW, \
.u32PeriodValue = 0xFFFF, \
.sw_count = \
{ \
.u8ClockDiv = TMRA_CLK_DIV1, \
.u8CountMode = TMRA_MD_SAWTOOTH, \
.u8CountDir = TMRA_DIR_DOWN, \
}, \
}, \
.stcPwmInit = \
{ \
.u32CompareValue = 0x0000, \
.u16StartPolarity = TMRA_PWM_LOW, \
.u16StopPolarity = TMRA_PWM_LOW, \
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
}, \
#define PWM_TMRA_2_CONFIG \
{ \
.name = "pwm_a2", \
.instance = CM_TMRA_2, \
.channel = 0, \
.stcTmraInit = { \
.u8CountSrc = TMRA_CNT_SRC_SW, \
.u32PeriodValue = 0xFFFF, \
.sw_count = { \
.u8ClockDiv = TMRA_CLK_DIV1, \
.u8CountMode = TMRA_MD_SAWTOOTH, \
.u8CountDir = TMRA_DIR_DOWN, \
}, \
}, \
.stcPwmInit = { \
.u32CompareValue = 0x0000, \
.u16StartPolarity = TMRA_PWM_LOW, \
.u16StopPolarity = TMRA_PWM_LOW, \
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
}, \
}
#endif /* PWM_TMRA_2_CONFIG */
#endif /* BSP_USING_PWM_TMRA_2 */
#ifdef BSP_USING_PWM_TMRA_3
#ifndef PWM_TMRA_3_CONFIG
#define PWM_TMRA_3_CONFIG \
{ \
.name = "pwm_a3", \
.instance = CM_TMRA_3, \
.channel = 0, \
.stcTmraInit = \
{ \
.u8CountSrc = TMRA_CNT_SRC_SW, \
.u32PeriodValue = 0xFFFF, \
.sw_count = \
{ \
.u8ClockDiv = TMRA_CLK_DIV1, \
.u8CountMode = TMRA_MD_SAWTOOTH, \
.u8CountDir = TMRA_DIR_DOWN, \
}, \
}, \
.stcPwmInit = \
{ \
.u32CompareValue = 0x0000, \
.u16StartPolarity = TMRA_PWM_LOW, \
.u16StopPolarity = TMRA_PWM_LOW, \
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
}, \
#define PWM_TMRA_3_CONFIG \
{ \
.name = "pwm_a3", \
.instance = CM_TMRA_3, \
.channel = 0, \
.stcTmraInit = { \
.u8CountSrc = TMRA_CNT_SRC_SW, \
.u32PeriodValue = 0xFFFF, \
.sw_count = { \
.u8ClockDiv = TMRA_CLK_DIV1, \
.u8CountMode = TMRA_MD_SAWTOOTH, \
.u8CountDir = TMRA_DIR_DOWN, \
}, \
}, \
.stcPwmInit = { \
.u32CompareValue = 0x0000, \
.u16StartPolarity = TMRA_PWM_LOW, \
.u16StopPolarity = TMRA_PWM_LOW, \
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
}, \
}
#endif /* PWM_TMRA_3_CONFIG */
#endif /* BSP_USING_PWM_TMRA_3 */
#ifdef BSP_USING_PWM_TMRA_4
#ifndef PWM_TMRA_4_CONFIG
#define PWM_TMRA_4_CONFIG \
{ \
.name = "pwm_a4", \
.instance = CM_TMRA_4, \
.channel = 0, \
.stcTmraInit = \
{ \
.u8CountSrc = TMRA_CNT_SRC_SW, \
.u32PeriodValue = 0xFFFF, \
.sw_count = \
{ \
.u8ClockDiv = TMRA_CLK_DIV1, \
.u8CountMode = TMRA_MD_SAWTOOTH, \
.u8CountDir = TMRA_DIR_DOWN, \
}, \
}, \
.stcPwmInit = \
{ \
.u32CompareValue = 0x0000, \
.u16StartPolarity = TMRA_PWM_LOW, \
.u16StopPolarity = TMRA_PWM_LOW, \
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
}, \
#define PWM_TMRA_4_CONFIG \
{ \
.name = "pwm_a4", \
.instance = CM_TMRA_4, \
.channel = 0, \
.stcTmraInit = { \
.u8CountSrc = TMRA_CNT_SRC_SW, \
.u32PeriodValue = 0xFFFF, \
.sw_count = { \
.u8ClockDiv = TMRA_CLK_DIV1, \
.u8CountMode = TMRA_MD_SAWTOOTH, \
.u8CountDir = TMRA_DIR_DOWN, \
}, \
}, \
.stcPwmInit = { \
.u32CompareValue = 0x0000, \
.u16StartPolarity = TMRA_PWM_LOW, \
.u16StopPolarity = TMRA_PWM_LOW, \
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
}, \
}
#endif /* PWM_TMRA_4_CONFIG */
#endif /* BSP_USING_PWM_TMRA_4 */
#ifdef BSP_USING_PWM_TMRA_5
#ifndef PWM_TMRA_5_CONFIG
#define PWM_TMRA_5_CONFIG \
{ \
.name = "pwm_a5", \
.instance = CM_TMRA_5, \
.channel = 0, \
.stcTmraInit = \
{ \
.u8CountSrc = TMRA_CNT_SRC_SW, \
.u32PeriodValue = 0xFFFF, \
.sw_count = \
{ \
.u8ClockDiv = TMRA_CLK_DIV1, \
.u8CountMode = TMRA_MD_SAWTOOTH, \
.u8CountDir = TMRA_DIR_DOWN, \
}, \
}, \
.stcPwmInit = \
{ \
.u32CompareValue = 0x0000, \
.u16StartPolarity = TMRA_PWM_LOW, \
.u16StopPolarity = TMRA_PWM_LOW, \
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
}, \
#define PWM_TMRA_5_CONFIG \
{ \
.name = "pwm_a5", \
.instance = CM_TMRA_5, \
.channel = 0, \
.stcTmraInit = { \
.u8CountSrc = TMRA_CNT_SRC_SW, \
.u32PeriodValue = 0xFFFF, \
.sw_count = { \
.u8ClockDiv = TMRA_CLK_DIV1, \
.u8CountMode = TMRA_MD_SAWTOOTH, \
.u8CountDir = TMRA_DIR_DOWN, \
}, \
}, \
.stcPwmInit = { \
.u32CompareValue = 0x0000, \
.u16StartPolarity = TMRA_PWM_LOW, \
.u16StopPolarity = TMRA_PWM_LOW, \
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
}, \
}
#endif /* PWM_TMRA_5_CONFIG */
#endif /* BSP_USING_PWM_TMRA_5 */
#ifdef BSP_USING_PWM_TMRA_6
#ifndef PWM_TMRA_6_CONFIG
#define PWM_TMRA_6_CONFIG \
{ \
.name = "pwm_a6", \
.instance = CM_TMRA_6, \
.channel = 0, \
.stcTmraInit = \
{ \
.u8CountSrc = TMRA_CNT_SRC_SW, \
.u32PeriodValue = 0xFFFF, \
.sw_count = \
{ \
.u8ClockDiv = TMRA_CLK_DIV1, \
.u8CountMode = TMRA_MD_SAWTOOTH, \
.u8CountDir = TMRA_DIR_DOWN, \
}, \
}, \
.stcPwmInit = \
{ \
.u32CompareValue = 0x0000, \
.u16StartPolarity = TMRA_PWM_LOW, \
.u16StopPolarity = TMRA_PWM_LOW, \
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
}, \
#define PWM_TMRA_6_CONFIG \
{ \
.name = "pwm_a6", \
.instance = CM_TMRA_6, \
.channel = 0, \
.stcTmraInit = { \
.u8CountSrc = TMRA_CNT_SRC_SW, \
.u32PeriodValue = 0xFFFF, \
.sw_count = { \
.u8ClockDiv = TMRA_CLK_DIV1, \
.u8CountMode = TMRA_MD_SAWTOOTH, \
.u8CountDir = TMRA_DIR_DOWN, \
}, \
}, \
.stcPwmInit = { \
.u32CompareValue = 0x0000, \
.u16StartPolarity = TMRA_PWM_LOW, \
.u16StopPolarity = TMRA_PWM_LOW, \
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
}, \
}
#endif /* PWM_TMRA_6_CONFIG */
#endif /* BSP_USING_PWM_TMRA_6 */
@ -205,96 +187,87 @@ extern "C" {
#ifdef BSP_USING_PWM_TMR4_1
#ifndef PWM_TMR4_1_CONFIG
#define PWM_TMR4_1_CONFIG \
{ \
.name = "pwm_t41", \
.instance = CM_TMR4_1, \
.channel = 0, \
.stcTmr4Init = \
{ \
.u16ClockDiv = TMR4_CLK_DIV1, \
.u16PeriodValue = 0xFFFFU, \
.u16CountMode = TMR4_MD_SAWTOOTH, \
.u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\
}, \
.stcTmr4OcInit = \
{ \
.u16CompareValue = 0x0000, \
.u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \
.u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\
.u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \
.u16BufLinkTransObject = 0U, \
}, \
.stcTmr4PwmInit = \
{ \
.u16Mode = TMR4_PWM_MD_THROUGH, \
.u16ClockDiv = TMR4_PWM_CLK_DIV1, \
.u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\
}, \
#define PWM_TMR4_1_CONFIG \
{ \
.name = "pwm_t41", \
.instance = CM_TMR4_1, \
.channel = 0, \
.stcTmr4Init = { \
.u16ClockDiv = TMR4_CLK_DIV1, \
.u16PeriodValue = 0xFFFFU, \
.u16CountMode = TMR4_MD_SAWTOOTH, \
.u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \
}, \
.stcTmr4OcInit = { \
.u16CompareValue = 0x0000, \
.u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \
.u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \
.u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \
.u16BufLinkTransObject = 0U, \
}, \
.stcTmr4PwmInit = { \
.u16Mode = TMR4_PWM_MD_THROUGH, \
.u16ClockDiv = TMR4_PWM_CLK_DIV1, \
.u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \
}, \
}
#endif /* PWM_TMR4_1_CONFIG */
#endif /* BSP_USING_PWM_TMR4_1 */
#ifdef BSP_USING_PWM_TMR4_2
#ifndef PWM_TMR4_2_CONFIG
#define PWM_TMR4_2_CONFIG \
{ \
.name = "pwm_t42", \
.instance = CM_TMR4_2, \
.channel = 0, \
.stcTmr4Init = \
{ \
.u16ClockDiv = TMR4_CLK_DIV1, \
.u16PeriodValue = 0xFFFFU, \
.u16CountMode = TMR4_MD_SAWTOOTH, \
.u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\
}, \
.stcTmr4OcInit = \
{ \
.u16CompareValue = 0x0000, \
.u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \
.u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\
.u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \
.u16BufLinkTransObject = 0U, \
}, \
.stcTmr4PwmInit = \
{ \
.u16Mode = TMR4_PWM_MD_THROUGH, \
.u16ClockDiv = TMR4_PWM_CLK_DIV1, \
.u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\
}, \
#define PWM_TMR4_2_CONFIG \
{ \
.name = "pwm_t42", \
.instance = CM_TMR4_2, \
.channel = 0, \
.stcTmr4Init = { \
.u16ClockDiv = TMR4_CLK_DIV1, \
.u16PeriodValue = 0xFFFFU, \
.u16CountMode = TMR4_MD_SAWTOOTH, \
.u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \
}, \
.stcTmr4OcInit = { \
.u16CompareValue = 0x0000, \
.u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \
.u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \
.u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \
.u16BufLinkTransObject = 0U, \
}, \
.stcTmr4PwmInit = { \
.u16Mode = TMR4_PWM_MD_THROUGH, \
.u16ClockDiv = TMR4_PWM_CLK_DIV1, \
.u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \
}, \
}
#endif /* PWM_TMR4_2_CONFIG */
#endif /* BSP_USING_PWM_TMR4_2 */
#ifdef BSP_USING_PWM_TMR4_3
#ifndef PWM_TMR4_3_CONFIG
#define PWM_TMR4_3_CONFIG \
{ \
.name = "pwm_t43", \
.instance = CM_TMR4_3, \
.channel = 0, \
.stcTmr4Init = \
{ \
.u16ClockDiv = TMR4_CLK_DIV1, \
.u16PeriodValue = 0xFFFFU, \
.u16CountMode = TMR4_MD_SAWTOOTH, \
.u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\
}, \
.stcTmr4OcInit = \
{ \
.u16CompareValue = 0x0000, \
.u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \
.u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\
.u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \
.u16BufLinkTransObject = 0U, \
}, \
.stcTmr4PwmInit = \
{ \
.u16Mode = TMR4_PWM_MD_THROUGH, \
.u16ClockDiv = TMR4_PWM_CLK_DIV1, \
.u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\
}, \
#define PWM_TMR4_3_CONFIG \
{ \
.name = "pwm_t43", \
.instance = CM_TMR4_3, \
.channel = 0, \
.stcTmr4Init = { \
.u16ClockDiv = TMR4_CLK_DIV1, \
.u16PeriodValue = 0xFFFFU, \
.u16CountMode = TMR4_MD_SAWTOOTH, \
.u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \
}, \
.stcTmr4OcInit = { \
.u16CompareValue = 0x0000, \
.u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \
.u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \
.u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \
.u16BufLinkTransObject = 0U, \
}, \
.stcTmr4PwmInit = { \
.u16Mode = TMR4_PWM_MD_THROUGH, \
.u16ClockDiv = TMR4_PWM_CLK_DIV1, \
.u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \
}, \
}
#endif /* PWM_TMR4_3_CONFIG */
#endif /* BSP_USING_PWM_TMR4_3 */
@ -305,121 +278,106 @@ extern "C" {
#ifdef BSP_USING_PWM_TMR6_1
#ifndef PWM_TMR6_1_CONFIG
#define PWM_TMR6_1_CONFIG \
{ \
.name = "pwm_t61", \
.instance = CM_TMR6_1, \
.channel = 0, \
.stcTmr6Init = \
{ \
.u8CountSrc = TMR6_CNT_SRC_SW, \
.sw_count = \
{ \
.u32ClockDiv = TMR6_CLK_DIV1, \
.u32CountMode = TMR6_MD_SAWTOOTH, \
.u32CountDir = TMR6_CNT_UP, \
}, \
.u32PeriodValue = 0xFFFF, \
}, \
.stcPwmInit = \
{ \
{ \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_HIGH, \
.u32StopPolarity = TMR6_PWM_HIGH, \
.u32CompareMatchPolarity = TMR6_PWM_LOW, \
.u32PeriodMatchPolarity = TMR6_PWM_HIGH, \
.u32StartStopHold = TMR6_PWM_START_STOP_HOLD, \
}, \
{ \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_HIGH, \
.u32StopPolarity = TMR6_PWM_HIGH, \
.u32CompareMatchPolarity = TMR6_PWM_LOW, \
.u32PeriodMatchPolarity = TMR6_PWM_HIGH, \
.u32StartStopHold = TMR6_PWM_START_STOP_HOLD, \
} \
}, \
#define PWM_TMR6_1_CONFIG \
{ \
.name = "pwm_t61", \
.instance = CM_TMR6_1, \
.channel = 0, \
.stcTmr6Init = { \
.u8CountSrc = TMR6_CNT_SRC_SW, \
.sw_count = { \
.u32ClockDiv = TMR6_CLK_DIV1, \
.u32CountMode = TMR6_MD_SAWTOOTH, \
.u32CountDir = TMR6_CNT_UP, \
}, \
.u32PeriodValue = 0xFFFF, \
}, \
.stcPwmInit = { { \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_HIGH, \
.u32StopPolarity = TMR6_PWM_HIGH, \
.u32CompareMatchPolarity = TMR6_PWM_LOW, \
.u32PeriodMatchPolarity = TMR6_PWM_HIGH, \
.u32StartStopHold = TMR6_PWM_START_STOP_HOLD, \
}, \
{ \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_HIGH, \
.u32StopPolarity = TMR6_PWM_HIGH, \
.u32CompareMatchPolarity = TMR6_PWM_LOW, \
.u32PeriodMatchPolarity = TMR6_PWM_HIGH, \
.u32StartStopHold = TMR6_PWM_START_STOP_HOLD, \
} }, \
}
#endif /* PWM_TMR6_1_CONFIG */
#endif /* BSP_USING_PWM_TMR6_1 */
#ifdef BSP_USING_PWM_TMR6_2
#ifndef PWM_TMR6_2_CONFIG
#define PWM_TMR6_2_CONFIG \
{ \
.name = "pwm_t61", \
.instance = CM_TMR6_2, \
.channel = 0, \
.stcTmr6Init = \
{ \
.u8CountSrc = TMR6_CNT_SRC_SW, \
.sw_count = \
{ \
.u32ClockDiv = TMR6_CLK_DIV1, \
.u32CountMode = TMR6_MD_SAWTOOTH, \
.u32CountDir = TMR6_CNT_DOWN, \
}, \
.u32PeriodValue = 0xFFFF, \
}, \
.stcPwmInit = \
{ \
{ \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_LOW, \
.u32StopPolarity = TMR6_PWM_LOW, \
.u32CompareMatchPolarity = TMR6_PWM_HIGH, \
.u32PeriodMatchPolarity = TMR6_PWM_LOW, \
.u32StartStopHold = TMR6_PWM_START_STOP_HOLD, \
}, \
{ \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_LOW, \
.u32StopPolarity = TMR6_PWM_LOW, \
.u32CompareMatchPolarity = TMR6_PWM_HIGH, \
.u32PeriodMatchPolarity = TMR6_PWM_LOW, \
.u32StartStopHold = TMR6_PWM_START_STOP_HOLD, \
} \
}, \
#define PWM_TMR6_2_CONFIG \
{ \
.name = "pwm_t61", \
.instance = CM_TMR6_2, \
.channel = 0, \
.stcTmr6Init = { \
.u8CountSrc = TMR6_CNT_SRC_SW, \
.sw_count = { \
.u32ClockDiv = TMR6_CLK_DIV1, \
.u32CountMode = TMR6_MD_SAWTOOTH, \
.u32CountDir = TMR6_CNT_DOWN, \
}, \
.u32PeriodValue = 0xFFFF, \
}, \
.stcPwmInit = { { \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_LOW, \
.u32StopPolarity = TMR6_PWM_LOW, \
.u32CompareMatchPolarity = TMR6_PWM_HIGH, \
.u32PeriodMatchPolarity = TMR6_PWM_LOW, \
.u32StartStopHold = TMR6_PWM_START_STOP_HOLD, \
}, \
{ \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_LOW, \
.u32StopPolarity = TMR6_PWM_LOW, \
.u32CompareMatchPolarity = TMR6_PWM_HIGH, \
.u32PeriodMatchPolarity = TMR6_PWM_LOW, \
.u32StartStopHold = TMR6_PWM_START_STOP_HOLD, \
} }, \
}
#endif /* PWM_TMR6_2_CONFIG */
#endif /* BSP_USING_PWM_TMR6_2 */
#ifdef BSP_USING_PWM_TMR6_3
#ifndef PWM_TMR6_3_CONFIG
#define PWM_TMR6_3_CONFIG \
{ \
.name = "pwm_t61", \
.instance = CM_TMR6_3, \
.channel = 0, \
.stcTmr6Init = \
{ \
.u8CountSrc = TMR6_CNT_SRC_SW, \
.sw_count = \
{ \
.u32ClockDiv = TMR6_CLK_DIV1, \
.u32CountMode = TMR6_MD_SAWTOOTH, \
.u32CountDir = TMR6_CNT_DOWN, \
}, \
.u32PeriodValue = 0xFFFF, \
}, \
.stcPwmInit = \
{ \
{ \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_LOW, \
.u32StopPolarity = TMR6_PWM_LOW, \
.u32CompareMatchPolarity = TMR6_PWM_HIGH, \
.u32PeriodMatchPolarity = TMR6_PWM_LOW, \
.u32StartStopHold = TMR6_PWM_START_STOP_HOLD, \
}, \
{ \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_LOW, \
.u32StopPolarity = TMR6_PWM_LOW, \
.u32CompareMatchPolarity = TMR6_PWM_HIGH, \
.u32PeriodMatchPolarity = TMR6_PWM_LOW, \
.u32StartStopHold = TMR6_PWM_START_STOP_HOLD, \
} \
}, \
#define PWM_TMR6_3_CONFIG \
{ \
.name = "pwm_t61", \
.instance = CM_TMR6_3, \
.channel = 0, \
.stcTmr6Init = { \
.u8CountSrc = TMR6_CNT_SRC_SW, \
.sw_count = { \
.u32ClockDiv = TMR6_CLK_DIV1, \
.u32CountMode = TMR6_MD_SAWTOOTH, \
.u32CountDir = TMR6_CNT_DOWN, \
}, \
.u32PeriodValue = 0xFFFF, \
}, \
.stcPwmInit = { { \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_LOW, \
.u32StopPolarity = TMR6_PWM_LOW, \
.u32CompareMatchPolarity = TMR6_PWM_HIGH, \
.u32PeriodMatchPolarity = TMR6_PWM_LOW, \
.u32StartStopHold = TMR6_PWM_START_STOP_HOLD, \
}, \
{ \
.u32CompareValue = 0x0000, \
.u32StartPolarity = TMR6_PWM_LOW, \
.u32StopPolarity = TMR6_PWM_LOW, \
.u32CompareMatchPolarity = TMR6_PWM_HIGH, \
.u32PeriodMatchPolarity = TMR6_PWM_LOW, \
.u32StartStopHold = TMR6_PWM_START_STOP_HOLD, \
} }, \
}
#endif /* PWM_TMR6_3_CONFIG */
#endif /* BSP_USING_PWM_TMR6_3 */

62
bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/qspi_config.h
View File

@ -20,48 +20,46 @@ extern "C" {
#ifdef BSP_USING_QSPI
#ifndef QSPI_BUS_CONFIG
#define QSPI_BUS_CONFIG \
{ \
.Instance = CM_QSPI, \
.clock = FCG1_PERIPH_QSPI, \
.timeout = 5000UL, \
.err_irq.irq_config = \
{ \
.irq_num = BSP_QSPI_ERR_IRQ_NUM, \
.irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \
.int_src = INT_SRC_QSPI_INTR, \
}, \
#define QSPI_BUS_CONFIG \
{ \
.Instance = CM_QSPI, \
.clock = FCG1_PERIPH_QSPI, \
.timeout = 5000UL, \
.err_irq.irq_config = { \
.irq_num = BSP_QSPI_ERR_IRQ_NUM, \
.irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \
.int_src = INT_SRC_QSPI_INTR, \
}, \
}
#endif /* QSPI_BUS_CONFIG */
#ifndef QSPI_INIT_PARAMS
#define QSPI_INIT_PARAMS \
{ \
.u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \
.u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \
.u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \
.u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \
#define QSPI_INIT_PARAMS \
{ \
.u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \
.u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \
.u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \
.u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \
}
#endif /* QSPI_INIT_PARAMS */
#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH
#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH
#ifdef BSP_QSPI_USING_DMA
#ifndef QSPI_DMA_CONFIG
#define QSPI_DMA_CONFIG \
{ \
.Instance = QSPI_DMA_INSTANCE, \
.channel = QSPI_DMA_CHANNEL, \
.clock = QSPI_DMA_CLOCK, \
.trigger_select = QSPI_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_AOS_STRG, \
.flag = QSPI_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = QSPI_DMA_IRQn, \
.irq_prio = QSPI_DMA_INT_PRIO, \
.int_src = QSPI_DMA_INT_SRC, \
} \
#define QSPI_DMA_CONFIG \
{ \
.Instance = QSPI_DMA_INSTANCE, \
.channel = QSPI_DMA_CHANNEL, \
.clock = QSPI_DMA_CLOCK, \
.trigger_select = QSPI_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_AOS_STRG, \
.flag = QSPI_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = QSPI_DMA_IRQn, \
.irq_prio = QSPI_DMA_INT_PRIO, \
.int_src = QSPI_DMA_INT_SRC, \
} \
}
#endif /* QSPI_DMA_CONFIG */
#endif /* BSP_QSPI_USING_DMA */

102
bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/sdio_config.h
View File

@ -21,66 +21,60 @@ extern "C" {
#if defined(BSP_USING_SDIO1)
#ifndef SDIO1_BUS_CONFIG
#define SDIO1_BUS_CONFIG \
{ \
.name = "sdio1", \
.instance = CM_SDIOC1, \
.clock = FCG1_PERIPH_SDIOC1, \
.irq_config = \
{ \
.irq_num = BSP_SDIO1_IRQ_NUM, \
.irq_prio = BSP_SDIO1_IRQ_PRIO, \
.int_src = INT_SRC_SDIOC1_SD, \
}, \
.dma_rx = \
{ \
.Instance = SDIO1_RX_DMA_INSTANCE, \
.channel = SDIO1_RX_DMA_CHANNEL, \
.clock = SDIO1_RX_DMA_CLOCK, \
.trigger_select = SDIO1_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SDIOC1_DMAR, \
}, \
.dma_tx = \
{ \
.Instance = SDIO1_TX_DMA_INSTANCE, \
.channel = SDIO1_TX_DMA_CHANNEL, \
.clock = SDIO1_TX_DMA_CLOCK, \
.trigger_select = SDIO1_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SDIOC1_DMAW, \
}, \
#define SDIO1_BUS_CONFIG \
{ \
.name = "sdio1", \
.instance = CM_SDIOC1, \
.clock = FCG1_PERIPH_SDIOC1, \
.irq_config = { \
.irq_num = BSP_SDIO1_IRQ_NUM, \
.irq_prio = BSP_SDIO1_IRQ_PRIO, \
.int_src = INT_SRC_SDIOC1_SD, \
}, \
.dma_rx = { \
.Instance = SDIO1_RX_DMA_INSTANCE, \
.channel = SDIO1_RX_DMA_CHANNEL, \
.clock = SDIO1_RX_DMA_CLOCK, \
.trigger_select = SDIO1_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SDIOC1_DMAR, \
}, \
.dma_tx = { \
.Instance = SDIO1_TX_DMA_INSTANCE, \
.channel = SDIO1_TX_DMA_CHANNEL, \
.clock = SDIO1_TX_DMA_CLOCK, \
.trigger_select = SDIO1_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SDIOC1_DMAW, \
}, \
}
#endif /* SDIO1_BUS_CONFIG */
#endif /* BSP_USING_SDIO1 */
#if defined(BSP_USING_SDIO2)
#ifndef SDIO2_BUS_CONFIG
#define SDIO2_BUS_CONFIG \
{ \
.name = "sdio2", \
.instance = CM_SDIOC2, \
.clock = FCG1_PERIPH_SDIOC2, \
.irq_config = \
{ \
.irq_num = BSP_SDIO2_IRQ_NUM, \
.irq_prio = BSP_SDIO2_IRQ_PRIO, \
.int_src = INT_SRC_SDIOC2_SD, \
}, \
.dma_rx = \
{ \
.Instance = SDIO2_RX_DMA_INSTANCE, \
.channel = SDIO2_RX_DMA_CHANNEL, \
.clock = SDIO2_RX_DMA_CLOCK, \
.trigger_select = SDIO2_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SDIOC2_DMAR, \
}, \
.dma_tx = \
{ \
.Instance = SDIO2_TX_DMA_INSTANCE, \
.channel = SDIO2_TX_DMA_CHANNEL, \
.clock = SDIO2_TX_DMA_CLOCK, \
.trigger_select = SDIO2_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SDIOC2_DMAW, \
}, \
#define SDIO2_BUS_CONFIG \
{ \
.name = "sdio2", \
.instance = CM_SDIOC2, \
.clock = FCG1_PERIPH_SDIOC2, \
.irq_config = { \
.irq_num = BSP_SDIO2_IRQ_NUM, \
.irq_prio = BSP_SDIO2_IRQ_PRIO, \
.int_src = INT_SRC_SDIOC2_SD, \
}, \
.dma_rx = { \
.Instance = SDIO2_RX_DMA_INSTANCE, \
.channel = SDIO2_RX_DMA_CHANNEL, \
.clock = SDIO2_RX_DMA_CLOCK, \
.trigger_select = SDIO2_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SDIOC2_DMAR, \
}, \
.dma_tx = { \
.Instance = SDIO2_TX_DMA_INSTANCE, \
.channel = SDIO2_TX_DMA_CHANNEL, \
.clock = SDIO2_TX_DMA_CLOCK, \
.trigger_select = SDIO2_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SDIOC2_DMAW, \
}, \
}
#endif /* SDIO2_BUS_CONFIG */
#endif /* BSP_USING_SDIO2 */

308
bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/spi_config.h
View File

@ -21,134 +21,127 @@ extern "C" {
#ifdef BSP_USING_SPI1
#ifndef SPI1_BUS_CONFIG
#define SPI1_BUS_CONFIG \
{ \
.Instance = CM_SPI1, \
.bus_name = "spi1", \
.clock = FCG1_PERIPH_SPI1, \
.timeout = 5000UL, \
.err_irq.irq_config = \
{ \
.irq_num = BSP_SPI1_ERR_IRQ_NUM, \
.irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \
.int_src = INT_SRC_SPI1_SPEI, \
}, \
#define SPI1_BUS_CONFIG \
{ \
.Instance = CM_SPI1, \
.bus_name = "spi1", \
.clock = FCG1_PERIPH_SPI1, \
.timeout = 5000UL, \
.err_irq.irq_config = { \
.irq_num = BSP_SPI1_ERR_IRQ_NUM, \
.irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \
.int_src = INT_SRC_SPI1_SPEI, \
}, \
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
{ \
.Instance = SPI1_TX_DMA_INSTANCE, \
.channel = SPI1_TX_DMA_CHANNEL, \
.clock = SPI1_TX_DMA_CLOCK, \
.trigger_select = SPI1_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI1_SPTI, \
.flag = SPI1_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = SPI1_TX_DMA_IRQn, \
.irq_prio = SPI1_TX_DMA_INT_PRIO, \
.int_src = SPI1_TX_DMA_INT_SRC, \
} \
#define SPI1_TX_DMA_CONFIG \
{ \
.Instance = SPI1_TX_DMA_INSTANCE, \
.channel = SPI1_TX_DMA_CHANNEL, \
.clock = SPI1_TX_DMA_CLOCK, \
.trigger_select = SPI1_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI1_SPTI, \
.flag = SPI1_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = SPI1_TX_DMA_IRQn, \
.irq_prio = SPI1_TX_DMA_INT_PRIO, \
.int_src = SPI1_TX_DMA_INT_SRC, \
} \
}
#endif /* SPI1_TX_DMA_CONFIG */
#endif /* BSP_SPI1_TX_USING_DMA */
#ifdef BSP_SPI1_RX_USING_DMA
#ifndef SPI1_RX_DMA_CONFIG
#define SPI1_RX_DMA_CONFIG \
{ \
.Instance = SPI1_RX_DMA_INSTANCE, \
.channel = SPI1_RX_DMA_CHANNEL, \
.clock = SPI1_RX_DMA_CLOCK, \
.trigger_select = SPI1_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI1_SPRI, \
.flag = SPI1_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = SPI1_RX_DMA_IRQn, \
.irq_prio = SPI1_RX_DMA_INT_PRIO, \
.int_src = SPI1_RX_DMA_INT_SRC, \
} \
#define SPI1_RX_DMA_CONFIG \
{ \
.Instance = SPI1_RX_DMA_INSTANCE, \
.channel = SPI1_RX_DMA_CHANNEL, \
.clock = SPI1_RX_DMA_CLOCK, \
.trigger_select = SPI1_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI1_SPRI, \
.flag = SPI1_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = SPI1_RX_DMA_IRQn, \
.irq_prio = SPI1_RX_DMA_INT_PRIO, \
.int_src = SPI1_RX_DMA_INT_SRC, \
} \
}
#endif /* SPI1_RX_DMA_CONFIG */
#endif /* BSP_SPI1_RX_USING_DMA */
#ifdef BSP_USING_SPI2
#ifndef SPI2_BUS_CONFIG
#define SPI2_BUS_CONFIG \
{ \
.Instance = CM_SPI2, \
.bus_name = "spi2", \
.clock = FCG1_PERIPH_SPI2, \
.timeout = 5000UL, \
.err_irq.irq_config = \
{ \
.irq_num = BSP_SPI2_ERR_IRQ_NUM, \
.irq_prio = BSP_SPI2_ERR_IRQ_PRIO, \
.int_src = INT_SRC_SPI2_SPEI, \
}, \
#define SPI2_BUS_CONFIG \
{ \
.Instance = CM_SPI2, \
.bus_name = "spi2", \
.clock = FCG1_PERIPH_SPI2, \
.timeout = 5000UL, \
.err_irq.irq_config = { \
.irq_num = BSP_SPI2_ERR_IRQ_NUM, \
.irq_prio = BSP_SPI2_ERR_IRQ_PRIO, \
.int_src = INT_SRC_SPI2_SPEI, \
}, \
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#ifdef BSP_SPI2_TX_USING_DMA
#ifndef SPI2_TX_DMA_CONFIG
#define SPI2_TX_DMA_CONFIG \
{ \
.Instance = SPI2_TX_DMA_INSTANCE, \
.channel = SPI2_TX_DMA_CHANNEL, \
.clock = SPI2_TX_DMA_CLOCK, \
.trigger_select = SPI2_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI2_SPTI, \
.flag = SPI2_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = SPI2_TX_DMA_IRQn, \
.irq_prio = SPI2_TX_DMA_INT_PRIO, \
.int_src = SPI2_TX_DMA_INT_SRC, \
} \
#define SPI2_TX_DMA_CONFIG \
{ \
.Instance = SPI2_TX_DMA_INSTANCE, \
.channel = SPI2_TX_DMA_CHANNEL, \
.clock = SPI2_TX_DMA_CLOCK, \
.trigger_select = SPI2_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI2_SPTI, \
.flag = SPI2_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = SPI2_TX_DMA_IRQn, \
.irq_prio = SPI2_TX_DMA_INT_PRIO, \
.int_src = SPI2_TX_DMA_INT_SRC, \
} \
}
#endif /* SPI2_TX_DMA_CONFIG */
#endif /* BSP_SPI2_TX_USING_DMA */
#ifdef BSP_SPI2_RX_USING_DMA
#ifndef SPI2_RX_DMA_CONFIG
#define SPI2_RX_DMA_CONFIG \
{ \
.Instance = SPI2_RX_DMA_INSTANCE, \
.channel = SPI2_RX_DMA_CHANNEL, \
.clock = SPI2_RX_DMA_CLOCK, \
.trigger_select = SPI2_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI2_SPRI, \
.flag = SPI2_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = SPI2_RX_DMA_IRQn, \
.irq_prio = SPI2_RX_DMA_INT_PRIO, \
.int_src = SPI2_RX_DMA_INT_SRC, \
} \
#define SPI2_RX_DMA_CONFIG \
{ \
.Instance = SPI2_RX_DMA_INSTANCE, \
.channel = SPI2_RX_DMA_CHANNEL, \
.clock = SPI2_RX_DMA_CLOCK, \
.trigger_select = SPI2_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI2_SPRI, \
.flag = SPI2_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = SPI2_RX_DMA_IRQn, \
.irq_prio = SPI2_RX_DMA_INT_PRIO, \
.int_src = SPI2_RX_DMA_INT_SRC, \
} \
}
#endif /* SPI2_RX_DMA_CONFIG */
#endif /* BSP_SPI2_RX_USING_DMA */
#ifdef BSP_USING_SPI3
#ifndef SPI3_BUS_CONFIG
#define SPI3_BUS_CONFIG \
{ \
.Instance = CM_SPI3, \
.bus_name = "spi3", \
.clock = FCG1_PERIPH_SPI3, \
.timeout = 5000UL, \
.err_irq.irq_config = \
{ \
.irq_num = BSP_SPI3_ERR_IRQ_NUM, \
.irq_prio = BSP_SPI3_ERR_IRQ_PRIO, \
.int_src = INT_SRC_SPI3_SPEI, \
}, \
#define SPI3_BUS_CONFIG \
{ \
.Instance = CM_SPI3, \
.bus_name = "spi3", \
.clock = FCG1_PERIPH_SPI3, \
.timeout = 5000UL, \
.err_irq.irq_config = { \
.irq_num = BSP_SPI3_ERR_IRQ_NUM, \
.irq_prio = BSP_SPI3_ERR_IRQ_PRIO, \
.int_src = INT_SRC_SPI3_SPEI, \
}, \
}
#endif /* SPI3_BUS_CONFIG */
#endif /* BSP_USING_SPI3 */
@ -156,98 +149,93 @@ extern "C" {
#ifdef BSP_SPI3_TX_USING_DMA
#ifndef SPI3_TX_DMA_CONFIG
#define SPI3_TX_DMA_CONFIG \
{ \
.Instance = SPI3_TX_DMA_INSTANCE, \
.channel = SPI3_TX_DMA_CHANNEL, \
.clock = SPI3_TX_DMA_CLOCK, \
.trigger_select = SPI3_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI3_SPTI, \
.flag = SPI3_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = SPI3_TX_DMA_IRQn, \
.irq_prio = SPI3_TX_DMA_INT_PRIO, \
.int_src = SPI3_TX_DMA_INT_SRC, \
} \
#define SPI3_TX_DMA_CONFIG \
{ \
.Instance = SPI3_TX_DMA_INSTANCE, \
.channel = SPI3_TX_DMA_CHANNEL, \
.clock = SPI3_TX_DMA_CLOCK, \
.trigger_select = SPI3_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI3_SPTI, \
.flag = SPI3_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = SPI3_TX_DMA_IRQn, \
.irq_prio = SPI3_TX_DMA_INT_PRIO, \
.int_src = SPI3_TX_DMA_INT_SRC, \
} \
}
#endif /* SPI3_TX_DMA_CONFIG */
#endif /* BSP_SPI3_TX_USING_DMA */
#ifdef BSP_SPI3_RX_USING_DMA
#ifndef SPI3_RX_DMA_CONFIG
#define SPI3_RX_DMA_CONFIG \
{ \
.Instance = SPI3_RX_DMA_INSTANCE, \
.channel = SPI3_RX_DMA_CHANNEL, \
.clock = SPI3_RX_DMA_CLOCK, \
.trigger_select = SPI3_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI3_SPRI, \
.flag = SPI3_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = SPI3_RX_DMA_IRQn, \
.irq_prio = SPI3_RX_DMA_INT_PRIO, \
.int_src = SPI3_RX_DMA_INT_SRC, \
} \
#define SPI3_RX_DMA_CONFIG \
{ \
.Instance = SPI3_RX_DMA_INSTANCE, \
.channel = SPI3_RX_DMA_CHANNEL, \
.clock = SPI3_RX_DMA_CLOCK, \
.trigger_select = SPI3_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI3_SPRI, \
.flag = SPI3_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = SPI3_RX_DMA_IRQn, \
.irq_prio = SPI3_RX_DMA_INT_PRIO, \
.int_src = SPI3_RX_DMA_INT_SRC, \
} \
}
#endif /* SPI3_RX_DMA_CONFIG */
#endif /* BSP_SPI3_RX_USING_DMA */
#ifdef BSP_USING_SPI4
#ifndef SPI4_BUS_CONFIG
#define SPI4_BUS_CONFIG \
{ \
.Instance = CM_SPI4, \
.bus_name = "spi4", \
.clock = FCG1_PERIPH_SPI4, \
.timeout = 5000UL, \
.err_irq.irq_config = \
{ \
.irq_num = BSP_SPI4_ERR_IRQ_NUM, \
.irq_prio = BSP_SPI4_ERR_IRQ_PRIO, \
.int_src = INT_SRC_SPI4_SPEI, \
}, \
#define SPI4_BUS_CONFIG \
{ \
.Instance = CM_SPI4, \
.bus_name = "spi4", \
.clock = FCG1_PERIPH_SPI4, \
.timeout = 5000UL, \
.err_irq.irq_config = { \
.irq_num = BSP_SPI4_ERR_IRQ_NUM, \
.irq_prio = BSP_SPI4_ERR_IRQ_PRIO, \
.int_src = INT_SRC_SPI4_SPEI, \
}, \
}
#endif /* SPI4_BUS_CONFIG */
#endif /* BSP_USING_SPI4 */
#ifdef BSP_SPI4_TX_USING_DMA
#ifndef SPI4_TX_DMA_CONFIG
#define SPI4_TX_DMA_CONFIG \
{ \
.Instance = SPI4_TX_DMA_INSTANCE, \
.channel = SPI4_TX_DMA_CHANNEL, \
.clock = SPI4_TX_DMA_CLOCK, \
.trigger_select = SPI4_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI4_SPTI, \
.flag = SPI4_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = SPI4_TX_DMA_IRQn, \
.irq_prio = SPI4_TX_DMA_INT_PRIO, \
.int_src = SPI4_TX_DMA_INT_SRC, \
} \
#define SPI4_TX_DMA_CONFIG \
{ \
.Instance = SPI4_TX_DMA_INSTANCE, \
.channel = SPI4_TX_DMA_CHANNEL, \
.clock = SPI4_TX_DMA_CLOCK, \
.trigger_select = SPI4_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI4_SPTI, \
.flag = SPI4_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = SPI4_TX_DMA_IRQn, \
.irq_prio = SPI4_TX_DMA_INT_PRIO, \
.int_src = SPI4_TX_DMA_INT_SRC, \
} \
}
#endif /* SPI4_TX_DMA_CONFIG */
#endif /* BSP_SPI4_TX_USING_DMA */
#ifdef BSP_SPI4_RX_USING_DMA
#ifndef SPI4_RX_DMA_CONFIG
#define SPI4_RX_DMA_CONFIG \
{ \
.Instance = SPI4_RX_DMA_INSTANCE, \
.channel = SPI4_RX_DMA_CHANNEL, \
.clock = SPI4_RX_DMA_CLOCK, \
.trigger_select = SPI4_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI4_SPRI, \
.flag = SPI4_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = SPI4_RX_DMA_IRQn, \
.irq_prio = SPI4_RX_DMA_INT_PRIO, \
.int_src = SPI4_RX_DMA_INT_SRC, \
} \
#define SPI4_RX_DMA_CONFIG \
{ \
.Instance = SPI4_RX_DMA_INSTANCE, \
.channel = SPI4_RX_DMA_CHANNEL, \
.clock = SPI4_RX_DMA_CLOCK, \
.trigger_select = SPI4_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI4_SPRI, \
.flag = SPI4_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = SPI4_RX_DMA_IRQn, \
.irq_prio = SPI4_RX_DMA_INT_PRIO, \
.int_src = SPI4_RX_DMA_INT_SRC, \
} \
}
#endif /* SPI4_RX_DMA_CONFIG */
#endif /* BSP_SPI4_RX_USING_DMA */

150
bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/timer_config.h
View File

@ -19,114 +19,108 @@ extern "C" {
#ifdef BSP_USING_TMRA_1
#ifndef TMRA_1_CONFIG
#define TMRA_1_CONFIG \
{ \
.tmr_handle = CM_TMRA_1, \
.clock_source = CLK_BUS_PCLK1, \
.clock = FCG2_PERIPH_TMRA_1, \
.flag = TMRA_FLAG_OVF, \
.isr = \
{ \
.enIntSrc = INT_SRC_TMRA_1_OVF, \
.enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \
}, \
.name = "tmra_1" \
#define TMRA_1_CONFIG \
{ \
.tmr_handle = CM_TMRA_1, \
.clock_source = CLK_BUS_PCLK1, \
.clock = FCG2_PERIPH_TMRA_1, \
.flag = TMRA_FLAG_OVF, \
.isr = { \
.enIntSrc = INT_SRC_TMRA_1_OVF, \
.enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \
}, \
.name = "tmra_1" \
}
#endif /* TMRA_1_CONFIG */
#endif /* BSP_USING_TMRA_1 */
#ifdef BSP_USING_TMRA_2
#ifndef TMRA_2_CONFIG
#define TMRA_2_CONFIG \
{ \
.tmr_handle = CM_TMRA_2, \
.clock_source = CLK_BUS_PCLK1, \
.clock = FCG2_PERIPH_TMRA_2, \
.flag = TMRA_FLAG_OVF, \
.isr = \
{ \
.enIntSrc = INT_SRC_TMRA_2_OVF, \
.enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \
}, \
.name = "tmra_2" \
#define TMRA_2_CONFIG \
{ \
.tmr_handle = CM_TMRA_2, \
.clock_source = CLK_BUS_PCLK1, \
.clock = FCG2_PERIPH_TMRA_2, \
.flag = TMRA_FLAG_OVF, \
.isr = { \
.enIntSrc = INT_SRC_TMRA_2_OVF, \
.enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \
}, \
.name = "tmra_2" \
}
#endif /* TMRA_2_CONFIG */
#endif /* BSP_USING_TMRA_2 */
#ifdef BSP_USING_TMRA_3
#ifndef TMRA_3_CONFIG
#define TMRA_3_CONFIG \
{ \
.tmr_handle = CM_TMRA_3, \
.clock_source = CLK_BUS_PCLK1, \
.clock = FCG2_PERIPH_TMRA_3, \
.flag = TMRA_FLAG_OVF, \
.isr = \
{ \
.enIntSrc = INT_SRC_TMRA_3_OVF, \
.enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \
}, \
.name = "tmra_3" \
#define TMRA_3_CONFIG \
{ \
.tmr_handle = CM_TMRA_3, \
.clock_source = CLK_BUS_PCLK1, \
.clock = FCG2_PERIPH_TMRA_3, \
.flag = TMRA_FLAG_OVF, \
.isr = { \
.enIntSrc = INT_SRC_TMRA_3_OVF, \
.enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \
}, \
.name = "tmra_3" \
}
#endif /* TMRA_3_CONFIG */
#endif /* BSP_USING_TMRA_3 */
#ifdef BSP_USING_TMRA_4
#ifndef TMRA_4_CONFIG
#define TMRA_4_CONFIG \
{ \
.tmr_handle = CM_TMRA_4, \
.clock_source = CLK_BUS_PCLK1, \
.clock = FCG2_PERIPH_TMRA_4, \
.flag = TMRA_FLAG_OVF, \
.isr = \
{ \
.enIntSrc = INT_SRC_TMRA_4_OVF, \
.enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \
}, \
.name = "tmra_4" \
#define TMRA_4_CONFIG \
{ \
.tmr_handle = CM_TMRA_4, \
.clock_source = CLK_BUS_PCLK1, \
.clock = FCG2_PERIPH_TMRA_4, \
.flag = TMRA_FLAG_OVF, \
.isr = { \
.enIntSrc = INT_SRC_TMRA_4_OVF, \
.enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \
}, \
.name = "tmra_4" \
}
#endif /* TMRA_4_CONFIG */
#endif /* BSP_USING_TMRA_4 */
#ifdef BSP_USING_TMRA_5
#ifndef TMRA_5_CONFIG
#define TMRA_5_CONFIG \
{ \
.tmr_handle = CM_TMRA_5, \
.clock_source = CLK_BUS_PCLK1, \
.clock = FCG2_PERIPH_TMRA_5, \
.flag = TMRA_FLAG_OVF, \
.isr = \
{ \
.enIntSrc = INT_SRC_TMRA_5_OVF, \
.enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \
}, \
.name = "tmra_5" \
#define TMRA_5_CONFIG \
{ \
.tmr_handle = CM_TMRA_5, \
.clock_source = CLK_BUS_PCLK1, \
.clock = FCG2_PERIPH_TMRA_5, \
.flag = TMRA_FLAG_OVF, \
.isr = { \
.enIntSrc = INT_SRC_TMRA_5_OVF, \
.enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \
}, \
.name = "tmra_5" \
}
#endif /* TMRA_5_CONFIG */
#endif /* BSP_USING_TMRA_5 */
#ifdef BSP_USING_TMRA_6
#ifndef TMRA_6_CONFIG
#define TMRA_6_CONFIG \
{ \
.tmr_handle = CM_TMRA_6, \
.clock_source = CLK_BUS_PCLK1, \
.clock = FCG2_PERIPH_TMRA_6, \
.flag = TMRA_FLAG_OVF, \
.isr = \
{ \
.enIntSrc = INT_SRC_TMRA_6_OVF, \
.enIRQn = BSP_USING_TMRA_6_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_6_IRQ_PRIO, \
}, \
.name = "tmra_6" \
#define TMRA_6_CONFIG \
{ \
.tmr_handle = CM_TMRA_6, \
.clock_source = CLK_BUS_PCLK1, \
.clock = FCG2_PERIPH_TMRA_6, \
.flag = TMRA_FLAG_OVF, \
.isr = { \
.enIntSrc = INT_SRC_TMRA_6_OVF, \
.enIRQn = BSP_USING_TMRA_6_IRQ_NUM, \
.u8Int_Prio = BSP_USING_TMRA_6_IRQ_PRIO, \
}, \
.name = "tmra_6" \
}
#endif /* TMRA_6_CONFIG */
#endif /* BSP_USING_TMRA_6 */

72
bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/tmr_capture_config.h
View File

@ -17,49 +17,49 @@
extern "C" {
#endif
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1)
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1)
#define IC1_NAME "ic1"
#define INPUT_CAPTURE_CFG_TMR6_1 \
{ \
.name = IC1_NAME, \
.ch = TMR6_CH_A, \
.clk_div = TMR6_CLK_DIV4, \
.first_edge = TMR6_CAPT_COND_PWMA_FALLING, \
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \
}
#define INPUT_CAPTURE_CFG_TMR6_1 \
{ \
.name = IC1_NAME, \
.ch = TMR6_CH_A, \
.clk_div = TMR6_CLK_DIV4, \
.first_edge = TMR6_CAPT_COND_PWMA_FALLING, \
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \
}
#endif
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2)
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2)
#define IC2_NAME "ic2"
#define INPUT_CAPTURE_CFG_TMR6_2 \
{ \
.name = IC2_NAME, \
.ch = TMR6_CH_A, \
.clk_div = TMR6_CLK_DIV8, \
.first_edge = TMR6_CAPT_COND_TRIGB_RISING, \
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \
}
#define INPUT_CAPTURE_CFG_TMR6_2 \
{ \
.name = IC2_NAME, \
.ch = TMR6_CH_A, \
.clk_div = TMR6_CLK_DIV8, \
.first_edge = TMR6_CAPT_COND_TRIGB_RISING, \
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \
}
#endif
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3)
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3)
#define IC3_NAME "ic3"
#define INPUT_CAPTURE_CFG_TMR6_3 \
{ \
.name = IC3_NAME, \
.ch = TMR6_CH_B, \
.clk_div = TMR6_CLK_DIV16, \
.first_edge = TMR6_CAPT_COND_TRIGA_FALLING, \
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM, \
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO, \
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM, \
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO, \
}
#define INPUT_CAPTURE_CFG_TMR6_3 \
{ \
.name = IC3_NAME, \
.ch = TMR6_CH_B, \
.clk_div = TMR6_CLK_DIV16, \
.first_edge = TMR6_CAPT_COND_TRIGA_FALLING, \
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM, \
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO, \
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM, \
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO, \
}
#endif
#ifdef __cplusplus

600
bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/uart_config.h
View File

@ -21,110 +21,102 @@ extern "C" {
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = CM_USART1, \
.clock = FCG1_PERIPH_USART1, \
.rxerr_irq.irq_config = \
{ \
.irq_num = BSP_UART1_RXERR_IRQ_NUM, \
.irq_prio = BSP_UART1_RXERR_IRQ_PRIO, \
.int_src = INT_SRC_USART1_EI, \
}, \
.rx_irq.irq_config = \
{ \
.irq_num = BSP_UART1_RX_IRQ_NUM, \
.irq_prio = BSP_UART1_RX_IRQ_PRIO, \
.int_src = INT_SRC_USART1_RI, \
}, \
.tx_irq.irq_config = \
{ \
.irq_num = BSP_UART1_TX_IRQ_NUM, \
.irq_prio = BSP_UART1_TX_IRQ_PRIO, \
.int_src = INT_SRC_USART1_TI, \
}, \
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = CM_USART1, \
.clock = FCG1_PERIPH_USART1, \
.rxerr_irq.irq_config = { \
.irq_num = BSP_UART1_RXERR_IRQ_NUM, \
.irq_prio = BSP_UART1_RXERR_IRQ_PRIO, \
.int_src = INT_SRC_USART1_EI, \
}, \
.rx_irq.irq_config = { \
.irq_num = BSP_UART1_RX_IRQ_NUM, \
.irq_prio = BSP_UART1_RX_IRQ_PRIO, \
.int_src = INT_SRC_USART1_RI, \
}, \
.tx_irq.irq_config = { \
.irq_num = BSP_UART1_TX_IRQ_NUM, \
.irq_prio = BSP_UART1_TX_IRQ_PRIO, \
.int_src = INT_SRC_USART1_TI, \
}, \
}
#endif /* UART1_CONFIG */
#if defined(BSP_UART1_RX_USING_DMA)
#ifndef UART1_DMA_RX_CONFIG
#define UART1_DMA_RX_CONFIG \
{ \
.Instance = UART1_RX_DMA_INSTANCE, \
.channel = UART1_RX_DMA_CHANNEL, \
.clock = UART1_RX_DMA_CLOCK, \
.trigger_select = UART1_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART1_RI, \
.flag = UART1_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = UART1_RX_DMA_IRQn, \
.irq_prio = UART1_RX_DMA_INT_PRIO, \
.int_src = UART1_RX_DMA_INT_SRC, \
}, \
#define UART1_DMA_RX_CONFIG \
{ \
.Instance = UART1_RX_DMA_INSTANCE, \
.channel = UART1_RX_DMA_CHANNEL, \
.clock = UART1_RX_DMA_CLOCK, \
.trigger_select = UART1_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART1_RI, \
.flag = UART1_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = UART1_RX_DMA_IRQn, \
.irq_prio = UART1_RX_DMA_INT_PRIO, \
.int_src = UART1_RX_DMA_INT_SRC, \
}, \
}
#endif /* UART1_DMA_RX_CONFIG */
#ifndef UART1_RXTO_CONFIG
#define UART1_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_1, \
.channel = TMR0_CH_A, \
.clock = FCG2_PERIPH_TMR0_1, \
.timeout_bits = 20UL, \
.irq_config = \
{ \
.irq_num = BSP_UART1_RXTO_IRQ_NUM, \
.irq_prio = BSP_UART1_RXTO_IRQ_PRIO, \
.int_src = INT_SRC_USART1_RTO, \
}, \
#define UART1_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_1, \
.channel = TMR0_CH_A, \
.clock = FCG2_PERIPH_TMR0_1, \
.timeout_bits = 20UL, \
.irq_config = { \
.irq_num = BSP_UART1_RXTO_IRQ_NUM, \
.irq_prio = BSP_UART1_RXTO_IRQ_PRIO, \
.int_src = INT_SRC_USART1_RTO, \
}, \
}
#endif /* UART1_RXTO_CONFIG */
#endif /* BSP_UART1_RX_USING_DMA */
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)
#ifndef UART1_TX_CPLT_CONFIG
#define UART1_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART1_TCI, \
}, \
#define UART1_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART1_TCI, \
}, \
}
#endif
#elif defined(RT_USING_SERIAL_V2)
#ifndef UART1_TX_CPLT_CONFIG
#define UART1_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART1_TCI, \
}, \
#define UART1_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART1_TCI, \
}, \
}
#endif
#endif /* UART1_TX_CPLT_CONFIG */
#if defined(BSP_UART1_TX_USING_DMA)
#ifndef UART1_DMA_TX_CONFIG
#define UART1_DMA_TX_CONFIG \
{ \
.Instance = UART1_TX_DMA_INSTANCE, \
.channel = UART1_TX_DMA_CHANNEL, \
.clock = UART1_TX_DMA_CLOCK, \
.trigger_select = UART1_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART1_TI, \
.flag = UART1_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = UART1_TX_DMA_IRQn, \
.irq_prio = UART1_TX_DMA_INT_PRIO, \
.int_src = UART1_TX_DMA_INT_SRC, \
}, \
#define UART1_DMA_TX_CONFIG \
{ \
.Instance = UART1_TX_DMA_INSTANCE, \
.channel = UART1_TX_DMA_CHANNEL, \
.clock = UART1_TX_DMA_CLOCK, \
.trigger_select = UART1_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART1_TI, \
.flag = UART1_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = UART1_TX_DMA_IRQn, \
.irq_prio = UART1_TX_DMA_INT_PRIO, \
.int_src = UART1_TX_DMA_INT_SRC, \
}, \
}
#endif /* UART1_DMA_TX_CONFIG */
#endif /* BSP_UART1_TX_USING_DMA */
@ -132,110 +124,102 @@ extern "C" {
#if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = CM_USART2, \
.clock = FCG1_PERIPH_USART2, \
.rxerr_irq.irq_config = \
{ \
.irq_num = BSP_UART2_RXERR_IRQ_NUM, \
.irq_prio = BSP_UART2_RXERR_IRQ_PRIO, \
.int_src = INT_SRC_USART2_EI, \
}, \
.rx_irq.irq_config = \
{ \
.irq_num = BSP_UART2_RX_IRQ_NUM, \
.irq_prio = BSP_UART2_RX_IRQ_PRIO, \
.int_src = INT_SRC_USART2_RI, \
}, \
.tx_irq.irq_config = \
{ \
.irq_num = BSP_UART2_TX_IRQ_NUM, \
.irq_prio = BSP_UART2_TX_IRQ_PRIO, \
.int_src = INT_SRC_USART2_TI, \
}, \
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = CM_USART2, \
.clock = FCG1_PERIPH_USART2, \
.rxerr_irq.irq_config = { \
.irq_num = BSP_UART2_RXERR_IRQ_NUM, \
.irq_prio = BSP_UART2_RXERR_IRQ_PRIO, \
.int_src = INT_SRC_USART2_EI, \
}, \
.rx_irq.irq_config = { \
.irq_num = BSP_UART2_RX_IRQ_NUM, \
.irq_prio = BSP_UART2_RX_IRQ_PRIO, \
.int_src = INT_SRC_USART2_RI, \
}, \
.tx_irq.irq_config = { \
.irq_num = BSP_UART2_TX_IRQ_NUM, \
.irq_prio = BSP_UART2_TX_IRQ_PRIO, \
.int_src = INT_SRC_USART2_TI, \
}, \
}
#endif /* UART2_CONFIG */
#if defined(BSP_UART2_RX_USING_DMA)
#ifndef UART2_DMA_RX_CONFIG
#define UART2_DMA_RX_CONFIG \
{ \
.Instance = UART2_RX_DMA_INSTANCE, \
.channel = UART2_RX_DMA_CHANNEL, \
.clock = UART2_RX_DMA_CLOCK, \
.trigger_select = UART2_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART2_RI, \
.flag = UART2_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = UART2_RX_DMA_IRQn, \
.irq_prio = UART2_RX_DMA_INT_PRIO, \
.int_src = UART2_RX_DMA_INT_SRC, \
}, \
#define UART2_DMA_RX_CONFIG \
{ \
.Instance = UART2_RX_DMA_INSTANCE, \
.channel = UART2_RX_DMA_CHANNEL, \
.clock = UART2_RX_DMA_CLOCK, \
.trigger_select = UART2_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART2_RI, \
.flag = UART2_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = UART2_RX_DMA_IRQn, \
.irq_prio = UART2_RX_DMA_INT_PRIO, \
.int_src = UART2_RX_DMA_INT_SRC, \
}, \
}
#endif /* UART2_DMA_RX_CONFIG */
#ifndef UART2_RXTO_CONFIG
#define UART2_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_1, \
.channel = TMR0_CH_B, \
.clock = FCG2_PERIPH_TMR0_1, \
.timeout_bits = 20UL, \
.irq_config = \
{ \
.irq_num = BSP_UART2_RXTO_IRQ_NUM, \
.irq_prio = BSP_UART2_RXTO_IRQ_PRIO, \
.int_src = INT_SRC_USART2_RTO, \
}, \
#define UART2_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_1, \
.channel = TMR0_CH_B, \
.clock = FCG2_PERIPH_TMR0_1, \
.timeout_bits = 20UL, \
.irq_config = { \
.irq_num = BSP_UART2_RXTO_IRQ_NUM, \
.irq_prio = BSP_UART2_RXTO_IRQ_PRIO, \
.int_src = INT_SRC_USART2_RTO, \
}, \
}
#endif /* UART2_RXTO_CONFIG */
#endif /* BSP_UART2_RX_USING_DMA */
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)
#ifndef UART2_TX_CPLT_CONFIG
#define UART2_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART2_TCI, \
}, \
#define UART2_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART2_TCI, \
}, \
}
#endif
#elif defined(RT_USING_SERIAL_V2)
#ifndef UART2_TX_CPLT_CONFIG
#define UART2_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART2_TCI, \
}, \
#define UART2_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART2_TCI, \
}, \
}
#endif
#endif /* UART2_TX_CPLT_CONFIG */
#if defined(BSP_UART2_TX_USING_DMA)
#ifndef UART2_DMA_TX_CONFIG
#define UART2_DMA_TX_CONFIG \
{ \
.Instance = UART2_TX_DMA_INSTANCE, \
.channel = UART2_TX_DMA_CHANNEL, \
.clock = UART2_TX_DMA_CLOCK, \
.trigger_select = UART2_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART2_TI, \
.flag = UART2_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = UART2_TX_DMA_IRQn, \
.irq_prio = UART2_TX_DMA_INT_PRIO, \
.int_src = UART2_TX_DMA_INT_SRC, \
}, \
#define UART2_DMA_TX_CONFIG \
{ \
.Instance = UART2_TX_DMA_INSTANCE, \
.channel = UART2_TX_DMA_CHANNEL, \
.clock = UART2_TX_DMA_CLOCK, \
.trigger_select = UART2_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART2_TI, \
.flag = UART2_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = UART2_TX_DMA_IRQn, \
.irq_prio = UART2_TX_DMA_INT_PRIO, \
.int_src = UART2_TX_DMA_INT_SRC, \
}, \
}
#endif /* UART2_DMA_TX_CONFIG */
#endif /* BSP_UART2_TX_USING_DMA */
@ -243,110 +227,102 @@ extern "C" {
#if defined(BSP_USING_UART3)
#ifndef UART3_CONFIG
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = CM_USART3, \
.clock = FCG1_PERIPH_USART3, \
.rxerr_irq.irq_config = \
{ \
.irq_num = BSP_UART3_RXERR_IRQ_NUM, \
.irq_prio = BSP_UART3_RXERR_IRQ_PRIO, \
.int_src = INT_SRC_USART3_EI, \
}, \
.rx_irq.irq_config = \
{ \
.irq_num = BSP_UART3_RX_IRQ_NUM, \
.irq_prio = BSP_UART3_RX_IRQ_PRIO, \
.int_src = INT_SRC_USART3_RI, \
}, \
.tx_irq.irq_config = \
{ \
.irq_num = BSP_UART3_TX_IRQ_NUM, \
.irq_prio = BSP_UART3_TX_IRQ_PRIO, \
.int_src = INT_SRC_USART3_TI, \
}, \
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = CM_USART3, \
.clock = FCG1_PERIPH_USART3, \
.rxerr_irq.irq_config = { \
.irq_num = BSP_UART3_RXERR_IRQ_NUM, \
.irq_prio = BSP_UART3_RXERR_IRQ_PRIO, \
.int_src = INT_SRC_USART3_EI, \
}, \
.rx_irq.irq_config = { \
.irq_num = BSP_UART3_RX_IRQ_NUM, \
.irq_prio = BSP_UART3_RX_IRQ_PRIO, \
.int_src = INT_SRC_USART3_RI, \
}, \
.tx_irq.irq_config = { \
.irq_num = BSP_UART3_TX_IRQ_NUM, \
.irq_prio = BSP_UART3_TX_IRQ_PRIO, \
.int_src = INT_SRC_USART3_TI, \
}, \
}
#endif /* UART3_CONFIG */
#if defined(BSP_UART3_RX_USING_DMA)
#ifndef UART3_DMA_RX_CONFIG
#define UART3_DMA_RX_CONFIG \
{ \
.Instance = UART3_RX_DMA_INSTANCE, \
.channel = UART3_RX_DMA_CHANNEL, \
.clock = UART3_RX_DMA_CLOCK, \
.trigger_select = UART3_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART3_RI, \
.flag = UART3_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = UART3_RX_DMA_IRQn, \
.irq_prio = UART3_RX_DMA_INT_PRIO, \
.int_src = UART3_RX_DMA_INT_SRC, \
}, \
#define UART3_DMA_RX_CONFIG \
{ \
.Instance = UART3_RX_DMA_INSTANCE, \
.channel = UART3_RX_DMA_CHANNEL, \
.clock = UART3_RX_DMA_CLOCK, \
.trigger_select = UART3_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART3_RI, \
.flag = UART3_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = UART3_RX_DMA_IRQn, \
.irq_prio = UART3_RX_DMA_INT_PRIO, \
.int_src = UART3_RX_DMA_INT_SRC, \
}, \
}
#endif /* UART3_DMA_RX_CONFIG */
#ifndef UART3_RXTO_CONFIG
#define UART3_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_2, \
.channel = TMR0_CH_A, \
.clock = FCG2_PERIPH_TMR0_2, \
.timeout_bits = 20UL, \
.irq_config = \
{ \
.irq_num = BSP_UART3_RXTO_IRQ_NUM, \
.irq_prio = BSP_UART3_RXTO_IRQ_PRIO, \
.int_src = INT_SRC_USART3_RTO, \
}, \
#define UART3_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_2, \
.channel = TMR0_CH_A, \
.clock = FCG2_PERIPH_TMR0_2, \
.timeout_bits = 20UL, \
.irq_config = { \
.irq_num = BSP_UART3_RXTO_IRQ_NUM, \
.irq_prio = BSP_UART3_RXTO_IRQ_PRIO, \
.int_src = INT_SRC_USART3_RTO, \
}, \
}
#endif /* UART3_RXTO_CONFIG */
#endif /* BSP_UART3_RX_USING_DMA */
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART3_TX_USING_DMA)
#ifndef UART3_TX_CPLT_CONFIG
#define UART3_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART3_TCI, \
}, \
#define UART3_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART3_TCI, \
}, \
}
#endif
#elif defined(RT_USING_SERIAL_V2)
#ifndef UART3_TX_CPLT_CONFIG
#define UART3_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART3_TCI, \
}, \
#define UART3_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART3_TCI, \
}, \
}
#endif
#endif /* UART3_TX_CPLT_CONFIG */
#if defined(BSP_UART3_TX_USING_DMA)
#ifndef UART3_DMA_TX_CONFIG
#define UART3_DMA_TX_CONFIG \
{ \
.Instance = UART3_TX_DMA_INSTANCE, \
.channel = UART3_TX_DMA_CHANNEL, \
.clock = UART3_TX_DMA_CLOCK, \
.trigger_select = UART3_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART3_TI, \
.flag = UART3_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = UART3_TX_DMA_IRQn, \
.irq_prio = UART3_TX_DMA_INT_PRIO, \
.int_src = UART3_TX_DMA_INT_SRC, \
}, \
#define UART3_DMA_TX_CONFIG \
{ \
.Instance = UART3_TX_DMA_INSTANCE, \
.channel = UART3_TX_DMA_CHANNEL, \
.clock = UART3_TX_DMA_CLOCK, \
.trigger_select = UART3_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART3_TI, \
.flag = UART3_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = UART3_TX_DMA_IRQn, \
.irq_prio = UART3_TX_DMA_INT_PRIO, \
.int_src = UART3_TX_DMA_INT_SRC, \
}, \
}
#endif /* UART3_DMA_TX_CONFIG */
#endif /* BSP_UART3_TX_USING_DMA */
@ -354,110 +330,102 @@ extern "C" {
#if defined(BSP_USING_UART4)
#ifndef UART4_CONFIG
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = CM_USART4, \
.clock = FCG1_PERIPH_USART4, \
.rxerr_irq.irq_config = \
{ \
.irq_num = BSP_UART4_RXERR_IRQ_NUM, \
.irq_prio = BSP_UART4_RXERR_IRQ_PRIO, \
.int_src = INT_SRC_USART4_EI, \
}, \
.rx_irq.irq_config = \
{ \
.irq_num = BSP_UART4_RX_IRQ_NUM, \
.irq_prio = BSP_UART4_RX_IRQ_PRIO, \
.int_src = INT_SRC_USART4_RI, \
}, \
.tx_irq.irq_config = \
{ \
.irq_num = BSP_UART4_TX_IRQ_NUM, \
.irq_prio = BSP_UART4_TX_IRQ_PRIO, \
.int_src = INT_SRC_USART4_TI, \
}, \
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = CM_USART4, \
.clock = FCG1_PERIPH_USART4, \
.rxerr_irq.irq_config = { \
.irq_num = BSP_UART4_RXERR_IRQ_NUM, \
.irq_prio = BSP_UART4_RXERR_IRQ_PRIO, \
.int_src = INT_SRC_USART4_EI, \
}, \
.rx_irq.irq_config = { \
.irq_num = BSP_UART4_RX_IRQ_NUM, \
.irq_prio = BSP_UART4_RX_IRQ_PRIO, \
.int_src = INT_SRC_USART4_RI, \
}, \
.tx_irq.irq_config = { \
.irq_num = BSP_UART4_TX_IRQ_NUM, \
.irq_prio = BSP_UART4_TX_IRQ_PRIO, \
.int_src = INT_SRC_USART4_TI, \
}, \
}
#endif /* UART4_CONFIG */
#if defined(BSP_UART4_RX_USING_DMA)
#ifndef UART4_DMA_RX_CONFIG
#define UART4_DMA_RX_CONFIG \
{ \
.Instance = UART4_RX_DMA_INSTANCE, \
.channel = UART4_RX_DMA_CHANNEL, \
.clock = UART4_RX_DMA_CLOCK, \
.trigger_select = UART4_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART4_RI, \
.flag = UART4_RX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = UART4_RX_DMA_IRQn, \
.irq_prio = UART4_RX_DMA_INT_PRIO, \
.int_src = UART4_RX_DMA_INT_SRC, \
}, \
#define UART4_DMA_RX_CONFIG \
{ \
.Instance = UART4_RX_DMA_INSTANCE, \
.channel = UART4_RX_DMA_CHANNEL, \
.clock = UART4_RX_DMA_CLOCK, \
.trigger_select = UART4_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART4_RI, \
.flag = UART4_RX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = UART4_RX_DMA_IRQn, \
.irq_prio = UART4_RX_DMA_INT_PRIO, \
.int_src = UART4_RX_DMA_INT_SRC, \
}, \
}
#endif /* UART4_DMA_RX_CONFIG */
#ifndef UART4_RXTO_CONFIG
#define UART4_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_2, \
.channel = TMR0_CH_B, \
.clock = FCG2_PERIPH_TMR0_2, \
.timeout_bits = 20UL, \
.irq_config = \
{ \
.irq_num = BSP_UART4_RXTO_IRQ_NUM, \
.irq_prio = BSP_UART4_RXTO_IRQ_PRIO, \
.int_src = INT_SRC_USART4_RTO, \
}, \
#define UART4_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_2, \
.channel = TMR0_CH_B, \
.clock = FCG2_PERIPH_TMR0_2, \
.timeout_bits = 20UL, \
.irq_config = { \
.irq_num = BSP_UART4_RXTO_IRQ_NUM, \
.irq_prio = BSP_UART4_RXTO_IRQ_PRIO, \
.int_src = INT_SRC_USART4_RTO, \
}, \
}
#endif /* UART4_RXTO_CONFIG */
#endif /* BSP_UART4_RX_USING_DMA */
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)
#ifndef UART4_TX_CPLT_CONFIG
#define UART4_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART4_TCI, \
}, \
#define UART4_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART4_TCI, \
}, \
}
#endif
#elif defined(RT_USING_SERIAL_V2)
#ifndef UART4_TX_CPLT_CONFIG
#define UART4_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART4_TCI, \
}, \
#define UART4_TX_CPLT_CONFIG \
{ \
.irq_config = { \
.irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART4_TCI, \
}, \
}
#endif
#endif /* UART4_TX_CPLT_CONFIG */
#if defined(BSP_UART4_TX_USING_DMA)
#ifndef UART4_DMA_TX_CONFIG
#define UART4_DMA_TX_CONFIG \
{ \
.Instance = UART4_TX_DMA_INSTANCE, \
.channel = UART4_TX_DMA_CHANNEL, \
.clock = UART4_TX_DMA_CLOCK, \
.trigger_select = UART4_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART4_TI, \
.flag = UART4_TX_DMA_TRANS_FLAG, \
.irq_config = \
{ \
.irq_num = UART4_TX_DMA_IRQn, \
.irq_prio = UART4_TX_DMA_INT_PRIO, \
.int_src = UART4_TX_DMA_INT_SRC, \
}, \
#define UART4_DMA_TX_CONFIG \
{ \
.Instance = UART4_TX_DMA_INSTANCE, \
.channel = UART4_TX_DMA_CHANNEL, \
.clock = UART4_TX_DMA_CLOCK, \
.trigger_select = UART4_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART4_TI, \
.flag = UART4_TX_DMA_TRANS_FLAG, \
.irq_config = { \
.irq_num = UART4_TX_DMA_IRQn, \
.irq_prio = UART4_TX_DMA_INT_PRIO, \
.int_src = UART4_TX_DMA_INT_SRC, \
}, \
}
#endif /* UART4_DMA_TX_CONFIG */
#endif /* BSP_UART4_TX_USING_DMA */

33
bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/usb_config/usb_app_conf.h
View File

@ -13,8 +13,7 @@
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
extern "C" {
#endif
/*******************************************************************************
@ -40,30 +39,30 @@ extern "C"
#endif
#ifndef USB_FS_MODE
#error "USB_FS_MODE should be defined"
#error "USB_FS_MODE should be defined"
#endif
#ifndef USE_DEVICE_MODE
#ifndef USE_HOST_MODE
#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined"
#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined"
#endif
#endif
#if defined(BSP_USING_USBD)
/* USB DEVICE FIFO CONFIGURATION */
#ifdef USB_FS_MODE
#define RX_FIFO_FS_SIZE (128U)
#define TX0_FIFO_FS_SIZE (32U)
#define TX1_FIFO_FS_SIZE (32U)
#define TX2_FIFO_FS_SIZE (32U)
#define TX3_FIFO_FS_SIZE (32U)
#define TX4_FIFO_FS_SIZE (32U)
#define TX5_FIFO_FS_SIZE (32U)
#define RX_FIFO_FS_SIZE (128U)
#define TX0_FIFO_FS_SIZE (32U)
#define TX1_FIFO_FS_SIZE (32U)
#define TX2_FIFO_FS_SIZE (32U)
#define TX3_FIFO_FS_SIZE (32U)
#define TX4_FIFO_FS_SIZE (32U)
#define TX5_FIFO_FS_SIZE (32U)
#if ((RX_FIFO_FS_SIZE + \
#if ((RX_FIFO_FS_SIZE + \
TX0_FIFO_FS_SIZE + TX1_FIFO_FS_SIZE + TX2_FIFO_FS_SIZE + TX3_FIFO_FS_SIZE + TX4_FIFO_FS_SIZE + \
TX5_FIFO_FS_SIZE) > 320U)
#error "The USB max FIFO size is 320 x 4 Bytes!"
#error "The USB max FIFO size is 320 x 4 Bytes!"
#endif
#endif
@ -75,12 +74,12 @@ extern "C"
#if defined(BSP_USING_USBH)
/* USB HOST FIFO CONFIGURATION */
#ifdef USB_FS_MODE
#define RX_FIFO_FS_SIZE (128U)
#define TXH_NP_FS_FIFOSIZ (64U)
#define TXH_P_FS_FIFOSIZ (128U)
#define RX_FIFO_FS_SIZE (128U)
#define TXH_NP_FS_FIFOSIZ (64U)
#define TXH_P_FS_FIFOSIZ (128U)
#if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 320U)
#error "The USB max FIFO size is 320 x 4 Bytes!"
#error "The USB max FIFO size is 320 x 4 Bytes!"
#endif
#endif

3
bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/usb_config/usb_bsp.h
View File

@ -13,8 +13,7 @@
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
extern "C" {
#endif
#include "hc32_ll_utility.h"

99
bsp/hc32/ev_hc32f460_lqfp100_v2/board/hc32f4xx_conf.h
View File

@ -27,8 +27,7 @@
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
extern "C" {
#endif
/*******************************************************************************
@ -48,55 +47,55 @@ extern "C"
* Library.
* @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function.
*/
#define LL_ICG_ENABLE (DDL_ON)
#define LL_UTILITY_ENABLE (DDL_ON)
#define LL_PRINT_ENABLE (DDL_OFF)
#define LL_ICG_ENABLE (DDL_ON)
#define LL_UTILITY_ENABLE (DDL_ON)
#define LL_PRINT_ENABLE (DDL_OFF)
#define LL_ADC_ENABLE (DDL_ON)
#define LL_AES_ENABLE (DDL_ON)
#define LL_AOS_ENABLE (DDL_ON)
#define LL_CAN_ENABLE (DDL_ON)
#define LL_CLK_ENABLE (DDL_ON)
#define LL_CMP_ENABLE (DDL_ON)
#define LL_CRC_ENABLE (DDL_ON)
#define LL_DBGC_ENABLE (DDL_OFF)
#define LL_DCU_ENABLE (DDL_ON)
#define LL_DMA_ENABLE (DDL_ON)
#define LL_EFM_ENABLE (DDL_ON)
#define LL_EMB_ENABLE (DDL_ON)
#define LL_EVENT_PORT_ENABLE (DDL_OFF)
#define LL_FCG_ENABLE (DDL_ON)
#define LL_FCM_ENABLE (DDL_ON)
#define LL_GPIO_ENABLE (DDL_ON)
#define LL_HASH_ENABLE (DDL_ON)
#define LL_I2C_ENABLE (DDL_ON)
#define LL_I2S_ENABLE (DDL_ON)
#define LL_INTERRUPTS_ENABLE (DDL_ON)
#define LL_INTERRUPTS_SHARE_ENABLE (DDL_ON)
#define LL_KEYSCAN_ENABLE (DDL_ON)
#define LL_MPU_ENABLE (DDL_ON)
#define LL_OTS_ENABLE (DDL_ON)
#define LL_PWC_ENABLE (DDL_ON)
#define LL_QSPI_ENABLE (DDL_ON)
#define LL_RMU_ENABLE (DDL_ON)
#define LL_RTC_ENABLE (DDL_ON)
#define LL_SDIOC_ENABLE (DDL_ON)
#define LL_SPI_ENABLE (DDL_ON)
#define LL_SRAM_ENABLE (DDL_ON)
#define LL_SWDT_ENABLE (DDL_ON)
#define LL_TMR0_ENABLE (DDL_ON)
#define LL_TMR4_ENABLE (DDL_ON)
#define LL_TMR6_ENABLE (DDL_ON)
#define LL_TMRA_ENABLE (DDL_ON)
#define LL_TRNG_ENABLE (DDL_ON)
#define LL_USART_ENABLE (DDL_ON)
#define LL_USB_ENABLE (DDL_ON)
#define LL_WDT_ENABLE (DDL_ON)
#define LL_ADC_ENABLE (DDL_ON)
#define LL_AES_ENABLE (DDL_ON)
#define LL_AOS_ENABLE (DDL_ON)
#define LL_CAN_ENABLE (DDL_ON)
#define LL_CLK_ENABLE (DDL_ON)
#define LL_CMP_ENABLE (DDL_ON)
#define LL_CRC_ENABLE (DDL_ON)
#define LL_DBGC_ENABLE (DDL_OFF)
#define LL_DCU_ENABLE (DDL_ON)
#define LL_DMA_ENABLE (DDL_ON)
#define LL_EFM_ENABLE (DDL_ON)
#define LL_EMB_ENABLE (DDL_ON)
#define LL_EVENT_PORT_ENABLE (DDL_OFF)
#define LL_FCG_ENABLE (DDL_ON)
#define LL_FCM_ENABLE (DDL_ON)
#define LL_GPIO_ENABLE (DDL_ON)
#define LL_HASH_ENABLE (DDL_ON)
#define LL_I2C_ENABLE (DDL_ON)
#define LL_I2S_ENABLE (DDL_ON)
#define LL_INTERRUPTS_ENABLE (DDL_ON)
#define LL_INTERRUPTS_SHARE_ENABLE (DDL_ON)
#define LL_KEYSCAN_ENABLE (DDL_ON)
#define LL_MPU_ENABLE (DDL_ON)
#define LL_OTS_ENABLE (DDL_ON)
#define LL_PWC_ENABLE (DDL_ON)
#define LL_QSPI_ENABLE (DDL_ON)
#define LL_RMU_ENABLE (DDL_ON)
#define LL_RTC_ENABLE (DDL_ON)
#define LL_SDIOC_ENABLE (DDL_ON)
#define LL_SPI_ENABLE (DDL_ON)
#define LL_SRAM_ENABLE (DDL_ON)
#define LL_SWDT_ENABLE (DDL_ON)
#define LL_TMR0_ENABLE (DDL_ON)
#define LL_TMR4_ENABLE (DDL_ON)
#define LL_TMR6_ENABLE (DDL_ON)
#define LL_TMRA_ENABLE (DDL_ON)
#define LL_TRNG_ENABLE (DDL_ON)
#define LL_USART_ENABLE (DDL_ON)
#define LL_USB_ENABLE (DDL_ON)
#define LL_WDT_ENABLE (DDL_ON)
/**
* @brief The following is a list of currently supported BSP boards.
*/
#define BSP_EV_HC32F460_LQFP100_V2 (4U)
#define BSP_EV_HC32F460_LQFP100_V2 (4U)
/**
* @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently
@ -105,15 +104,15 @@ extern "C"
* @note If there is no supported BSP board or the BSP function is not used,
* the value needs to be set to 0U.
*/
#define BSP_EV_HC32F4XX (0U)
#define BSP_EV_HC32F4XX (0U)
/**
* @brief This is the list of BSP components to be used.
* Select the components you need to use to DDL_ON.
*/
#define BSP_24CXX_ENABLE (DDL_OFF)
#define BSP_W25QXX_ENABLE (DDL_OFF)
#define BSP_WM8731_ENABLE (DDL_OFF)
#define BSP_24CXX_ENABLE (DDL_OFF)
#define BSP_W25QXX_ENABLE (DDL_OFF)
#define BSP_WM8731_ENABLE (DDL_OFF)
/*******************************************************************************
* Global variable definitions ('extern')

20
bsp/hc32/ev_hc32f460_lqfp100_v2/board/ports/fal_cfg.h
View File

@ -23,20 +23,20 @@ extern const struct fal_flash_dev hc32_onchip_flash;
extern struct fal_flash_dev ext_nor_flash0;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&hc32_onchip_flash, \
&ext_nor_flash0, \
}
#define FAL_FLASH_DEV_TABLE \
{ \
&hc32_onchip_flash, \
&ext_nor_flash0, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 512 * 1024, 0}, \
{FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0}, \
}
#define FAL_PART_TABLE \
{ \
{ FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 512 * 1024, 0 }, \
{ FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0 }, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#endif /* _FAL_CFG_H_ */

116
bsp/hc32/ev_hc32f460_lqfp100_v2/board/ports/usb_config.h
View File

@ -14,15 +14,15 @@
/* ================ USB common Configuration ================ */
#ifdef __RTTHREAD__
#include <rtthread.h>
#include <rtthread.h>
#define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__)
#define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__)
#else
#define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__)
#define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__)
#endif
#ifndef CONFIG_USB_DBG_LEVEL
#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO
#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO
#endif
/* Enable print with color */
@ -32,9 +32,9 @@
/* data align size when use dma or use dcache */
#ifdef CONFIG_USB_DCACHE_ENABLE
#define CONFIG_USB_ALIGN_SIZE 32 // 32 or 64
#define CONFIG_USB_ALIGN_SIZE 32 // 32 or 64
#else
#define CONFIG_USB_ALIGN_SIZE 4
#define CONFIG_USB_ALIGN_SIZE 4
#endif
/* attribute data into no cache ram */
@ -49,7 +49,7 @@
/* Ep0 in and out transfer buffer */
#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN
#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512
#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512
#endif
/* Send ep0 in data from user buffer instead of copying into ep0 reqdata
@ -70,31 +70,31 @@
// #define CONFIG_USBDEV_EP0_THREAD
#ifndef CONFIG_USBDEV_EP0_PRIO
#define CONFIG_USBDEV_EP0_PRIO 4
#define CONFIG_USBDEV_EP0_PRIO 4
#endif
#ifndef CONFIG_USBDEV_EP0_STACKSIZE
#define CONFIG_USBDEV_EP0_STACKSIZE 2048
#define CONFIG_USBDEV_EP0_STACKSIZE 2048
#endif
#ifndef CONFIG_USBDEV_MSC_MAX_LUN
#define CONFIG_USBDEV_MSC_MAX_LUN 1
#define CONFIG_USBDEV_MSC_MAX_LUN 1
#endif
#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE
#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512
#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512
#endif
#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING
#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING ""
#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING ""
#endif
#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING
#define CONFIG_USBDEV_MSC_PRODUCT_STRING ""
#define CONFIG_USBDEV_MSC_PRODUCT_STRING ""
#endif
#ifndef CONFIG_USBDEV_MSC_VERSION_STRING
#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01"
#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01"
#endif
/* move msc read & write from isr to while(1), you should call usbd_msc_polling in while(1) */
@ -104,50 +104,50 @@
// #define CONFIG_USBDEV_MSC_THREAD
#ifndef CONFIG_USBDEV_MSC_PRIO
#define CONFIG_USBDEV_MSC_PRIO 4
#define CONFIG_USBDEV_MSC_PRIO 4
#endif
#ifndef CONFIG_USBDEV_MSC_STACKSIZE
#define CONFIG_USBDEV_MSC_STACKSIZE 2048
#define CONFIG_USBDEV_MSC_STACKSIZE 2048
#endif
#ifndef CONFIG_USBDEV_MTP_MAX_BUFSIZE
#define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048
#define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048
#endif
#ifndef CONFIG_USBDEV_MTP_MAX_OBJECTS
#define CONFIG_USBDEV_MTP_MAX_OBJECTS 256
#define CONFIG_USBDEV_MTP_MAX_OBJECTS 256
#endif
#ifndef CONFIG_USBDEV_MTP_MAX_PATHNAME
#define CONFIG_USBDEV_MTP_MAX_PATHNAME 256
#define CONFIG_USBDEV_MTP_MAX_PATHNAME 256
#endif
#define CONFIG_USBDEV_MTP_THREAD
#ifndef CONFIG_USBDEV_MTP_PRIO
#define CONFIG_USBDEV_MTP_PRIO 4
#define CONFIG_USBDEV_MTP_PRIO 4
#endif
#ifndef CONFIG_USBDEV_MTP_STACKSIZE
#define CONFIG_USBDEV_MTP_STACKSIZE 4096
#define CONFIG_USBDEV_MTP_STACKSIZE 4096
#endif
#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE
#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156
#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156
#endif
/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/
#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE
#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580
#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580
#endif
#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID
#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff
#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff
#endif
#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC
#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB"
#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB"
#endif
#define CONFIG_USBDEV_RNDIS_USING_LWIP
@ -171,95 +171,95 @@
#define CONFIG_USBHOST_DEV_NAMELEN 16
#ifndef CONFIG_USBHOST_PSC_PRIO
#define CONFIG_USBHOST_PSC_PRIO 0
#define CONFIG_USBHOST_PSC_PRIO 0
#endif
#ifndef CONFIG_USBHOST_PSC_STACKSIZE
#define CONFIG_USBHOST_PSC_STACKSIZE 2048
#define CONFIG_USBHOST_PSC_STACKSIZE 2048
#endif
//#define CONFIG_USBHOST_GET_STRING_DESC
// #define CONFIG_USBHOST_MSOS_ENABLE
#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE
#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00
#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00
#endif
/* Ep0 max transfer buffer */
#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN
#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512
#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512
#endif
#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT
#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500
#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500
#endif
#ifndef CONFIG_USBHOST_MSC_TIMEOUT
#define CONFIG_USBHOST_MSC_TIMEOUT 5000
#define CONFIG_USBHOST_MSC_TIMEOUT 5000
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048)
#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048)
#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048)
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048)
#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048)
#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048)
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048)
#define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048)
#define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048)
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048)
#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048)
#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048)
#endif
#define CONFIG_USBHOST_BLUETOOTH_HCI_H4
// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG
#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE
#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048
#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048
#endif
#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE
#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048
#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048
#endif
/* ================ USB Device Port Configuration ================*/
#ifndef CONFIG_USBDEV_MAX_BUS
#define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip
#define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip
#endif
#ifndef CONFIG_USBDEV_EP_NUM
#define CONFIG_USBDEV_EP_NUM 8
#define CONFIG_USBDEV_EP_NUM 8
#endif
// #define CONFIG_USBDEV_SOF_ENABLE
@ -270,38 +270,38 @@
// #define CONFIG_USB_DWC2_DMA_ENABLE
/* Defined FS Core device FIFO Size in words 32-bits */
#define CONFIG_USB_FS_CORE_DEVICE_RX_FIFO_SIZE (128)
#define CONFIG_USB_FS_CORE_DEVICE_TX0_FIFO_SIZE (32)
#define CONFIG_USB_FS_CORE_DEVICE_TX1_FIFO_SIZE (32)
#define CONFIG_USB_FS_CORE_DEVICE_TX2_FIFO_SIZE (32)
#define CONFIG_USB_FS_CORE_DEVICE_TX3_FIFO_SIZE (32)
#define CONFIG_USB_FS_CORE_DEVICE_TX4_FIFO_SIZE (32)
#define CONFIG_USB_FS_CORE_DEVICE_TX5_FIFO_SIZE (32)
#define CONFIG_USB_FS_CORE_DEVICE_RX_FIFO_SIZE (128)
#define CONFIG_USB_FS_CORE_DEVICE_TX0_FIFO_SIZE (32)
#define CONFIG_USB_FS_CORE_DEVICE_TX1_FIFO_SIZE (32)
#define CONFIG_USB_FS_CORE_DEVICE_TX2_FIFO_SIZE (32)
#define CONFIG_USB_FS_CORE_DEVICE_TX3_FIFO_SIZE (32)
#define CONFIG_USB_FS_CORE_DEVICE_TX4_FIFO_SIZE (32)
#define CONFIG_USB_FS_CORE_DEVICE_TX5_FIFO_SIZE (32)
/* Defined FS Core host FIFO Size in words 32-bits */
#define CONFIG_USB_FS_CORE_HOST_RX_FIFO_SIZE (128)
#define CONFIG_USB_FS_CORE_HOST_NP_FIFO_SIZE (32)
#define CONFIG_USB_FS_CORE_HOST_PE_FIFO_SIZE (64)
#define CONFIG_USB_FS_CORE_HOST_RX_FIFO_SIZE (128)
#define CONFIG_USB_FS_CORE_HOST_NP_FIFO_SIZE (32)
#define CONFIG_USB_FS_CORE_HOST_PE_FIFO_SIZE (64)
/* Defined FS Core total FIFO Size in words 32-bits */
#define CONFIG_USB_FS_CORE_TOTAL_FIFO_SIZE (320)
#define CONFIG_USB_FS_CORE_TOTAL_FIFO_SIZE (320)
/* ================ USB Host Port Configuration ==================*/
#ifndef CONFIG_USBHOST_MAX_BUS
#define CONFIG_USBHOST_MAX_BUS 1
#define CONFIG_USBHOST_MAX_BUS 1
#endif
#ifndef CONFIG_USBHOST_PIPE_NUM
#define CONFIG_USBHOST_PIPE_NUM 10
#define CONFIG_USBHOST_PIPE_NUM 10
#endif
#ifndef usb_phyaddr2ramaddr
#define usb_phyaddr2ramaddr(addr) (addr)
#define usb_phyaddr2ramaddr(addr) (addr)
#endif
#ifndef usb_ramaddr2phyaddr
#define usb_ramaddr2phyaddr(addr) (addr)
#define usb_ramaddr2phyaddr(addr) (addr)
#endif
#endif

10
bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.h
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@ -72,7 +72,7 @@
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
#define IDLE_THREAD_STACK_SIZE 512
/* kservice options */
@ -326,14 +326,6 @@
/* GD32 Drivers */
/* end of GD32 Drivers */
/* HPMicro SDK */
/* end of HPMicro SDK */
/* FT32 HAL & SDK Drivers */
/* end of FT32 HAL & SDK Drivers */
/* end of HAL & SDK Drivers */
/* sensors drivers */

188
bsp/hc32/ev_hc32f467_lqfp144/.ci/attachconfig/ci.attachconfig.yml Normal file
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@ -0,0 +1,188 @@
# ------ device CI ------
devices.adc:
kconfig:
- CONFIG_BSP_USING_ADC=y
- CONFIG_BSP_USING_ADC1=y
- CONFIG_BSP_ADC1_USING_DMA=y
devices.can:
kconfig:
- CONFIG_BSP_USING_CAN=y
- CONFIG_BSP_USING_CAN1=y
- CONFIG_RT_CAN_USING_HDR=y
devices.crypto:
kconfig:
- CONFIG_BSP_USING_HWCRYPTO=y
- CONFIG_BSP_USING_UQID=y
- CONFIG_BSP_USING_RNG=y
- CONFIG_BSP_USING_CRC=y
- CONFIG_BSP_USING_AES=y
- CONFIG_BSP_USING_HASH=y
devices.dac:
kconfig:
- CONFIG_BSP_USING_DAC=y
- CONFIG_BSP_USING_DAC1=y
devices.flash:
kconfig:
- CONFIG_BSP_USING_ON_CHIP_FLASH=y
- CONFIG_RT_USING_FAL=y
- CONFIG_RT_USING_SPI=y
- CONFIG_RT_USING_SFUD=y
devices.gpio:
kconfig:
- CONFIG_BSP_USING_GPIO=y
devices.clock_timer:
kconfig:
- CONFIG_BSP_USING_CLOCK_TIMER=y
- CONFIG_BSP_USING_TMRA_1=y
devices.i2c:
kconfig:
- CONFIG_BSP_USING_I2C=y
- CONFIG_BSP_USING_I2C1=y
- CONFIG_BSP_I2C1_TX_USING_DMA=y
- CONFIG_BSP_I2C1_RX_USING_DMA=y
devices.input_capture:
kconfig:
- CONFIG_BSP_USING_INPUT_CAPTURE=y
- CONFIG_BSP_USING_INPUT_CAPTURE_TMR6=y
- CONFIG_BSP_USING_INPUT_CAPTURE_TMR6_1=y
devices.pm:
kconfig:
- CONFIG_BSP_USING_PM=y
- CONFIG_IDLE_THREAD_STACK_SIZE=512
devices.pulse_encoder_tmr6:
kconfig:
- CONFIG_BSP_USING_PULSE_ENCODER=y
- CONFIG_BSP_USING_TMR6_PULSE_ENCODER=y
- CONFIG_BSP_USING_PULSE_ENCODER_TMR6_1=y
devices.pulse_encoder_tmra:
kconfig:
- CONFIG_BSP_USING_PULSE_ENCODER=y
- CONFIG_BSP_USING_TMRA_PULSE_ENCODER=y
- CONFIG_BSP_USING_PULSE_ENCODER_TMRA_1=y
devices.pwm_tmr4:
kconfig:
- CONFIG_BSP_USING_PWM=y
- CONFIG_BSP_USING_PWM_TMR4=y
- CONFIG_BSP_USING_PWM_TMR4_1=y
- CONFIG_BSP_USING_PWM_TMR4_1_OUH=y
- CONFIG_BSP_USING_PWM_TMR4_1_OUL=y
devices.pwm_tmr6:
kconfig:
- CONFIG_BSP_USING_PWM=y
- CONFIG_BSP_USING_PWM_TMR6=y
- CONFIG_BSP_USING_PWM_TMR6_1=y
- CONFIG_BSP_USING_PWM_TMR6_1_A=y
- CONFIG_BSP_USING_PWM_TMR6_1_B=y
devices.pwm_tmra:
kconfig:
- CONFIG_BSP_USING_PWM=y
- CONFIG_BSP_USING_PWM_TMRA=y
- CONFIG_BSP_USING_PWM_TMRA_1=y
- CONFIG_BSP_USING_PWM_TMRA_1_CH1=y
- CONFIG_BSP_USING_PWM_TMRA_1_CH2=y
devices.qspi:
kconfig:
- CONFIG_BSP_USING_QSPI=y
- CONFIG_BSP_QSPI_USING_DMA=y
- CONFIG_BSP_QSPI_USING_SOFT_CS=y
devices.rtc:
kconfig:
- CONFIG_BSP_USING_RTC=y
- CONFIG_RT_USING_ALARM=y
devices.sdio:
kconfig:
- CONFIG_BSP_USING_SDIO=y
- CONFIG_BSP_USING_SDIO1=y
- CONFIG_RT_USING_DFS=y
- CONFIG_RT_USING_DFS_ELMFAT=y
devices.soft_i2c:
kconfig:
- CONFIG_BSP_USING_I2C=y
- CONFIG_BSP_USING_I2C1_SW=y
devices.spi:
kconfig:
- CONFIG_BSP_USING_SPI=y
- CONFIG_BSP_USING_SPI1=y
- CONFIG_BSP_SPI1_TX_USING_DMA=y
- CONFIG_BSP_SPI1_RX_USING_DMA=y
- CONFIG_BSP_SPI_USING_DMA=y
- CONFIG_RT_USING_DFS=y
- CONFIG_RT_USING_DFS_ELMFAT=y
devices.uart_v1:
kconfig:
- CONFIG_RT_USING_SERIAL_V1=y
- CONFIG_BSP_USING_UART=y
- CONFIG_BSP_USING_UART6=y
- CONFIG_RT_SERIAL_USING_DMA=y
- CONFIG_BSP_UART6_RX_USING_DMA=y
- CONFIG_BSP_UART6_TX_USING_DMA=y
devices.uart_v2:
kconfig:
- CONFIG_RT_USING_SERIAL_V2=y
- CONFIG_BSP_USING_UART=y
- CONFIG_BSP_USING_UART6=y
- CONFIG_RT_SERIAL_USING_DMA=y
- CONFIG_BSP_UART6_RX_USING_DMA=y
- CONFIG_BSP_UART6_TX_USING_DMA=y
devices.usb_hs_device:
kconfig:
- CONFIG_BSP_USING_USB=y
- CONFIG_BSP_USING_USBD=y
- CONFIG_BSP_USING_USBHS=y
- CONFIG_BSP_USING_USBD_HS=y
- CONFIG_RT_USB_DEVICE_MSTORAGE=y
devices.usb_hs_host:
kconfig:
- CONFIG_BSP_USING_USB=y
- CONFIG_BSP_USING_USBH=y
- CONFIG_BSP_USING_USBHS=y
- CONFIG_BSP_USING_USBH_HS=y
- CONFIG_RT_USBH_MSTORAGE=y
- CONFIG_RT_USING_DFS=y
- CONFIG_RT_USING_DFS_ELMFAT=y
devices.usb_fs_device:
kconfig:
- CONFIG_BSP_USING_USB=y
- CONFIG_BSP_USING_USBD=y
- CONFIG_BSP_USING_USBFS=y
- CONFIG_BSP_USING_USBD_FS=y
- CONFIG_RT_USB_DEVICE_MSTORAGE=y
devices.usb_fs_host:
kconfig:
- CONFIG_BSP_USING_USB=y
- CONFIG_BSP_USING_USBH=y
- CONFIG_BSP_USING_USBFS=y
- CONFIG_BSP_USING_USBH_FS=y
- CONFIG_RT_USBH_MSTORAGE=y
- CONFIG_RT_USING_DFS=y
- CONFIG_RT_USING_DFS_ELMFAT=y
devices.watchdog_swdt:
kconfig:
- CONFIG_BSP_USING_WDT_TMR=y
- CONFIG_BSP_USING_SWDT=y
devices.watchdog_wdt:
kconfig:
- CONFIG_BSP_USING_WDT_TMR=y
- CONFIG_BSP_USING_WDT=y
# ------ peripheral CI ------
peripheral.eth_rmii:
kconfig:
- CONFIG_BSP_USING_ETH=y
- CONFIG_ETH_INTERFACE_USING_RMII=y
- CONFIG_ETH_PHY_USING_INTERRUPT_MODE=y
- CONFIG_RT_USING_LWIP212=y
- CONFIG_RT_USING_LWIP_VER_NUM=0x20102
peripheral.exmc_nand:
kconfig:
- CONFIG_BSP_USING_EXMC=y
- CONFIG_BSP_USING_NAND=y
- CONFIG_FINSH_USING_MSH=y
peripheral.exmc_sdram:
kconfig:
- CONFIG_BSP_USING_EXMC=y
- CONFIG_BSP_USING_SDRAM=y
- CONFIG_FINSH_USING_MSH=y
peripheral.spi_flash:
kconfig:
- CONFIG_BSP_USING_SPI_FLASH=y

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bsp/hc32/ev_hc32f467_lqfp144/.config Normal file
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224
bsp/hc32/ev_hc32f467_lqfp144/.cproject Normal file
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42
bsp/hc32/ev_hc32f467_lqfp144/.gitignore vendored Normal file
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@ -0,0 +1,42 @@
*.pyc
*.map
*.dblite
*.elf
*.bin
*.hex
*.axf
*.exe
*.pdb
*.idb
*.ilk
*.old
build
Debug
documentation/html
packages/
*~
*.o
*.obj
*.out
*.bak
*.dep
*.lib
*.i
*.d
.DS_Stor*
.config 3
.config 4
.config 5
Midea-X1
*.uimg
GPATH
GRTAGS
GTAGS
.vscode
JLinkLog.txt
JLinkSettings.ini
DebugConfig/
RTE/
settings/
*.uvguix*
cconfig.h

78
bsp/hc32/ev_hc32f467_lqfp144/.project Normal file
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@ -0,0 +1,78 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>ev_hc32f467_lqfp144</name>
<comment />
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
<linkedResources>
<link>
<name>rt-thread</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>rt-thread/bsp</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>rt-thread/components</name>
<type>2</type>
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/components</locationURI>
</link>
<link>
<name>rt-thread/include</name>
<type>2</type>
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/include</locationURI>
</link>
<link>
<name>rt-thread/libcpu</name>
<type>2</type>
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/libcpu</locationURI>
</link>
<link>
<name>rt-thread/src</name>
<type>2</type>
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/src</locationURI>
</link>
<link>
<name>rt-thread/bsp/hc32</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>rt-thread/bsp/hc32/libraries</name>
<type>2</type>
<locationURI>$%7BPARENT-1-PROJECT_LOC%7D/libraries</locationURI>
</link>
<link>
<name>rt-thread/bsp/hc32/platform</name>
<type>2</type>
<locationURI>PARENT-1-PROJECT_LOC/platform</locationURI>
</link>
<link>
<name>rt-thread/bsp/hc32/tests</name>
<type>2</type>
<locationURI>PARENT-1-PROJECT_LOC/tests</locationURI>
</link>
</linkedResources>
</projectDescription>

9
bsp/hc32/ev_hc32f467_lqfp144/EventRecorderStub.scvd Normal file
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@ -0,0 +1,9 @@
<?xml version="1.0" encoding="utf-8"?>
<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
<events>
</events>
</component_viewer>

12
bsp/hc32/ev_hc32f467_lqfp144/Kconfig Normal file
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@ -0,0 +1,12 @@
mainmenu "RT-Thread Configuration"
BSP_DIR := .
RTT_DIR := ../../..
PKGS_DIR := packages
source "$(RTT_DIR)/Kconfig"
osource "$PKGS_DIR/Kconfig"
rsource "../libraries/Kconfig"
rsource "board/Kconfig"

142
bsp/hc32/ev_hc32f467_lqfp144/README.md Normal file
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@ -0,0 +1,142 @@
# XHSC EV_F467_LQ144 开发板 BSP 说明
## 简介
本文档为小华半导体为 EV_F467_LQ144 开发板提供的 BSP (板级支持包) 说明。
主要内容如下：
- 开发板资源介绍
- BSP 快速上手
- 进阶使用方法
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
## 开发板介绍
EV_F467_LQ144 是 XHSC 官方推出的开发板，搭载 HC32F467RGTI 芯片，基于 ARM Cortex-M4 内核，最高主频 240 MHz，具有丰富的板载资源，可以充分发挥 HC32F467RGTI 的芯片性能。
开发板外观如下图所示：
![board](figures/board.jpg)
EV_F467_LQ144 开发板常用 **板载资源** 如下：
- MCU：HC32F466RGTI，主频240MHz，1048KB FLASH，512KB RAM
- 外部RAM：IS62WV51216(SRAM，1MB) IS42S16400J(SDRAM，8MB)
- 外部FLASH: MT29F2G08AB(Nand，256MB) W25Q64(SPI NOR，8MB)
- 常用外设
- LED：3 个，User LED(LED0、LED1、LED2)。
- 按键：6 个，矩阵键盘(K1~K4)、WAKEUP(K5)、RESET(K0)。
- 常用接口：SD卡接口、以太网接口、LCD接口、USB FS/HS接口、DVP接口、3.5mm耳机接口、Line in接口、CAN接口、LIN接口。
- 调试接口：板载DAP调试器（含USB转串口）、标准JTAG/SWD。
开发板更多详细信息请参考小华半导体半导体[EV_F467_LQ144](https://www.xhsc.com.cn)
## 外设支持
本 BSP 目前对外设的支持情况如下：
| **板载外设** | **支持情况** | **备注** |
| :------------ | :-----------: | :-----------------------------------: |
| ETH | 支持 | RTL8201F |
| Nand | 支持 | MT29F2G08AB |
| SDRAM | 支持 | IS42S16400J |
| USB 转串口 | 支持 | 使用 UART7 |
| **片上外设** | **支持情况** | **备注** |
| :------------ | :-----------: | :-----------------------------------: |
| ADC | 支持 | |
| CAN | 支持 | |
| Crypto | 支持 | AES，CRC，HASH，RNG |
| DAC | 支持 | |
| FLASH | 支持 | |
| GPIO | 支持 | PA0，PA1...PI13 ---> PIN：0，1...141 |
| CLOCK_TIMER | 支持 | |
| I2C | 支持 | 软件、硬件 I2C |
| InputCapture | 支持 | |
| PM | 支持 | |
| PulseEncoder | 支持 | |
| PWM | 支持 | |
| QSPI | 支持 | |
| RTC | 支持 | 闹钟精度为1分钟 |
| SDIO | 支持 | |
| SPI | 支持 | |
| UART V1 & V2 | 支持 | |
| USB | 支持 | USBFS/HS Core， device/host模式 |
| WDT | 支持 | |
## 使用说明
使用说明分为如下两个章节：
- 快速上手
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
- 进阶使用
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
### 快速上手
本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
#### 硬件连接
使用Type-A to MircoUSB线连接开发板和PC供电。
#### 编译下载
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
> 工程默认配置使用板载 DAP 下载程序，点击下载按钮即可下载程序到开发板。
#### 运行结果
下载程序成功之后，系统会自动运行，观察开发板上LED的运行效果，绿色LED10会周期性闪烁。
USB虚拟COM端口默认连接串口7，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息:
```
\ | /
- RT - Thread Operating System
/ | \ 4.1.0 build Apr 24 2022 13:32:39
2006 - 2022 Copyright by RT-Thread team
msh >
```
### 进阶使用
此 BSP 默认只开启了 GPIO 和 串口 7 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下：
1. 在 bsp 下打开 env 工具。
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
## 注意事项
| 板载外设 | 模式 | 协议栈 | 注意事项 |
| :------: | :----: | :------------: | :----------------------------------------------------------- |
| USB | device | ALL | 由于协议栈的设计，当配置为CDC设备时，打开USB虚拟串口，需使能流控的DTR信号。（如使用SSCOM串口助手打开USB虚拟串口时，勾选DTR选框） |
| USB | device | ALL | 由于外部PHY管脚复用的原因，当配置使用USBHS Core并且使用外部PHY时，需先通过J14连接到主机（如PC），再复位MCU运行程序；或者将J24跳帽先短接，再复位MCU运行程序。 |
| USB | ALL | ALL | 由于main()函数中的LED闪烁示例，使用的是USBFS主机的供电控制管脚，因而当配置为使用USBFS Core时，需要将main()函数中的LED示例代码手动屏蔽。 |
| USB | host | ALL | 为确保USB主机对外供电充足，建议通过J35外接5V电源供电，并短接J32的EXT跳帽。 |
| USB | host | ALL | 由于外部PHY管脚复用的原因，当配置使用USBHS Core并且使用外部PHY时，需通过J14先连接好OTG线，再复位MCU运行程序；或者将J24跳帽先短接，再复位MCU运行程序。 |
| USB | host | RTT legacy USB | 目前仅实现并测试了对U盘的支持。 |
| USB | host | RTT legacy USB | 若配置为U盘主机模式，出现部分U盘无法识别或者写入失败时，可以尝试将RTT抽象层中rt_udisk_run()函数的rt_usbh_storage_reset()操作注释掉，测试是否可以获得更好的兼容性。 |
| USB | ALL | ALL | 由于管脚复用的原因，当配置使用USBHS Core时，无法同时使用板载SPI FLASH。 |
| USB | ALL | ALL | CherryUSB 与 RTT legacy USB 组件不可同时使用;<br />CherryUSB与 ”On-Chip Peripheral Driver---> []Enable USB“ 不可同时使能及配置。 |
| USB | ALL | RTT legacy USB | 通过“board/config/usb_config/usb_app_conf.h” 进行应用个性化配置（主要为FIFO分配） |
| USB | ALL | CherryUSB | 通过“board/ports/usb_config.h”进行应用个性化配置（如FIFO分配、是否使用DMA[Device]、是否使用高速PHY等） |
## 联系人信息
维护人:
- [小华半导体MCU](https://www.xhsc.com.cn)，邮箱：<xhsc_ae_cd_ap@xhsc.com.cn>

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bsp/hc32/ev_hc32f467_lqfp144/SConscript Normal file
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# for module compiling
import os
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

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bsp/hc32/ev_hc32f467_lqfp144/SConstruct Normal file
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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
def bsp_pkg_check():
import subprocess
check_paths = [
os.path.join("packages", "hc32-f4-cmsis-latest"),
os.path.join("packages", "hc32-f4-series-latest")
]
need_update = not all(os.path.exists(p) for p in check_paths)
if need_update:
print("\n===============================================================================")
print("Dependency packages missing, please running 'pkgs --update'...")
print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
print("===============================================================================")
exit(1)
RegisterPreBuildingAction(bsp_pkg_check)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM in ['iccarm']:
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/libraries'):
libraries_path_prefix = SDK_ROOT + '/libraries'
else:
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
rtconfig.BSP_LIBRARY_TYPE = None
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))
# include platform
platform_path_prefix = os.path.dirname(SDK_ROOT) + '/platform'
objs.extend(SConscript(os.path.join(platform_path_prefix, 'SConscript')))
# include tests
test_path_prefix = os.path.dirname(SDK_ROOT) + '/tests'
objs.extend(SConscript(os.path.join(test_path_prefix, 'SConscript')))
# make a building
DoBuilding(TARGET, objs)

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bsp/hc32/ev_hc32f467_lqfp144/applications/SConscript Normal file
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from building import *
import os
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
list = os.listdir(cwd)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
group = group + SConscript(os.path.join(item, 'SConscript'))
Return('group')

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bsp/hc32/ev_hc32f467_lqfp144/applications/main.c Normal file
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/*
* Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-06-03 CDT first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
#include <tca9539_port.h>
int main(void)
{
/* set LED_BLUE_PIN pin mode to output */
TCA9539_ConfigPin(LED_BLUE_PORT, LED_BLUE_PIN, TCA9539_DIR_OUT);
while (1)
{
TCA9539_WritePin(LED_BLUE_PORT, LED_BLUE_PIN, TCA9539_PIN_SET);
rt_thread_mdelay(500);
TCA9539_WritePin(LED_BLUE_PORT, LED_BLUE_PIN, TCA9539_PIN_RESET);
rt_thread_mdelay(500);
}
}

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