Commit Graph

7536 Commits

Author SHA1 Message Date
Hanlu Li 7b638be386 build: remove Meson deprecation warnings
Generate both pkgconfig machine-file keys for compatibility, replace deprecated root-directory APIs, use boolean option values, and drop the no-op gui_app argument.

Validated on LoongArch with build64.sh -c, build32.sh -c, and build-release.sh; all completed without compiler or Meson warning matches.

Signed-off-by: Hanlu Li <heuleehanlu@gmail.com>
2026-08-07 11:56:21 +08:00
Hanlu Li 2dafc11dfc LATX: guide users when guest runtimes fail to load
A PT_INTERP failure previously exposed only a low-level host error, leaving users unable to tell which guest ABI, runtime root, or loader path LATX had selected.

Report the selected runtime source, the guest PT_INTERP value, the configured candidate from the shared path resolver, the actually attempted host path, a stable failure category, and the underlying detail. Use QEMU error-reporting APIs and direct users to the companion latu-runtime-manager status command.

The diagnostic is emitted only at the interpreter load failure. Successful dynamic guests and static guests retain their existing behavior. Synthetic x86_64 and i386 fixtures cover absolute and relative interpreters, missing, unreadable, corrupt, truncated, valid dynamic, and static cases.

Signed-off-by: Hanlu Li <heuleehanlu@gmail.com>
2026-08-05 07:33:25 +08:00
Hanlu Li 0863f52ad6 linux-user: allow ELF loader errors to be returned
Interpreter ELF failures were previously reported and terminated inside load_elf_image(), so LATX callers could not attach the selected runtime context.

Return a success value and optionally propagate Error objects while preserving the existing fatal behavior at unchanged call sites. Release the mmap lock before returning an error. Also centralize the interp_prefix declaration in linux-user/qemu.h and remove KZT-local duplicates.

Factor runtime-prefix eligibility into one path helper and expose the configured candidate path for later diagnostics without changing path() fallback behavior. This commit intentionally does not change user-visible diagnostics.

Signed-off-by: Hanlu Li <heuleehanlu@gmail.com>
2026-08-05 07:33:25 +08:00
Hanlu Li 442a4b6034 LATX: expose selected runtime information
LATX selects its guest runtime root from defaults, system and user configuration, the environment, and -L, but previously exposed neither the selected value nor its source.

Track the source whenever LAT_LD_PREFIX is applied and add --runtime-info to latx-x86_64 and latx-i386. The option accepts an optional guest program for per-program configuration and emits versioned JSON for manager tooling without starting guest execution. When no guest is supplied, apply global configuration entries only and ignore per-program sections.

While answering the query, apply only runtime-selection options so unrelated inherited settings cannot emit output, terminate the process, or otherwise contaminate the JSON contract. Keep configuration diagnostics on stderr and add end-to-end coverage for both guest ABIs, including conflicting diagnostic and terminal environment options.

Signed-off-by: Hanlu Li <heuleehanlu@gmail.com>
2026-08-05 07:33:25 +08:00
Hanlu Li f7f5dcd0a8 runtime: support symlinked translator installs
Signed-off-by: Hanlu Li <heuleehanlu@gmail.com>
2026-08-04 20:43:37 +08:00
Hanlu Li ff70bc14b6 build: install and exercise the runtime manager
Signed-off-by: Hanlu Li <heuleehanlu@gmail.com>
2026-08-04 20:43:37 +08:00
Hanlu Li 16142a29ac runtime: report both LATX translators
Signed-off-by: Hanlu Li <heuleehanlu@gmail.com>
2026-08-04 20:43:37 +08:00
Hanlu Li 152ca82b70 LATX: ignore unsafe user configuration homes
Load the per-user LATX configuration only when HOME is an absolute path and the derived filename fits. Cover unset and relative HOME without changing system configuration handling.

Signed-off-by: Hanlu Li <heuleehanlu@gmail.com>
2026-08-04 20:24:14 +08:00
Hanlu Li 8c25f34929 LATX: honor loader prefix config in release builds
Signed-off-by: Hanlu Li <heuleehanlu@gmail.com>
2026-08-04 20:24:14 +08:00
Hanlu Li eb228bea9a LATX: share config plumbing across x86 targets
Name target-specific system and user configuration files once, reuse the common loading path, and run the focused configuration regression for both x86_64 and i386 targets.

Signed-off-by: Hanlu Li <heuleehanlu@gmail.com>
2026-08-04 20:24:14 +08:00
yuerengan 8299cef200 LATX, fix: track IPC namespace joined with setns
A guest can enter an IPC namespace through setns() with either an explicit
CLONE_NEWIPC type or a zero type inferred from the namespace fd. Record both
successful paths so the AOT exit worker remains synchronous and cannot keep
the namespace alive after guest exit.

Inspect NS_GET_NSTYPE only for the zero-type namespace-fd form and preserve
the real setns() result when that ioctl is not applicable. This keeps pidfd
namespace masks working while handling invalid descriptors explicitly.

Add integration coverage for invalid descriptors, pidfd namespace joins, and
both namespace-fd forms with AOT and mqueue lifecycle validation.

Signed-off-by: yuerengan <y347812075@163.com>
2026-08-03 10:40:30 +08:00
yuerengan 4b471ee55b LATX, fix: support mount, IPC and UTS clone namespaces
Fork-like guest clone calls rejected mount, IPC and UTS namespace flags even
though the host clone path can create those namespaces together with the
already supported PID and network namespaces.

Accept the additional flags and pass them through the deferred
single-threaded clone path. Add an integration test that verifies the child
receives distinct mount, IPC and UTS namespaces.

Signed-off-by: yuerengan <y347812075@163.com>
2026-08-03 10:40:30 +08:00
yuerengan c90d0b6901 LATX, fix: lazily start the RCU callback thread
Starting the RCU callback consumer during process initialization exposes an
extra host thread before the guest creates one. Namespace operations that
require a single-threaded caller can then fail for a single-threaded guest.

Start the consumer when callback work first needs it, while preserving the
existing deferred start required by namespace children. Add unit and
integration coverage for the lazy lifecycle and host-thread visibility.

Signed-off-by: yuerengan <y347812075@163.com>
2026-08-03 10:40:30 +08:00
Hanlu Li 7fc3fb1366 LATX, fix: Keep procfs outside the runtime prefix
An inert /proc directory in the x86 runtime prefix shadows the live procfs, so directory enumeration reports only dot entries.

Resolve /proc paths in the calling task's current namespace while retaining the existing prefix behavior for other paths. Reject parent traversal before bypassing the prefix.

Add deterministic path-policy and syscall regression tests using an empty runtime /proc, covering the default, TU0, and TU1 modes.

Refs #359

Signed-off-by: Hanlu Li <heuleehanlu@gmail.com>
2026-07-31 17:58:43 +08:00
Hanlu Li 2577408158 LATX, fix: terminate truncated program names
Signed-off-by: Hanlu Li <heuleehanlu@gmail.com>
2026-07-31 16:03:41 +08:00
Hanlu Li 96a892dc02 LATX, fix: handle empty config values
Signed-off-by: Hanlu Li <heuleehanlu@gmail.com>
2026-07-31 16:03:41 +08:00
Hanlu Li 78067436a4 tests: order syscall headers before LATX tests
Signed-off-by: Hanlu Li <heuleehanlu@gmail.com>
2026-07-31 15:09:21 +08:00
Hanlu Li d0d2132877 tests: order TCG trace headers before LATX tests
Signed-off-by: Hanlu Li <heuleehanlu@gmail.com>
2026-07-31 15:09:21 +08:00
Hanlu Li 44e1670add tests: order generated headers before LATX tests
Signed-off-by: Hanlu Li <heuleehanlu@gmail.com>
2026-07-31 15:09:21 +08:00
Hanlu Li 0535094fb7 tests: classify Meson tests by CI suite
Signed-off-by: Hanlu Li <heuleehanlu@gmail.com>
2026-07-31 15:09:21 +08:00
Wenqiang Wei 34432ed181 LATX, fix: bound final AOT exclusive wait
Bound final AOT exclusive entry so shutdown cannot wait forever for a
CPU blocked in native code. On timeout, cancel pending waiter state and
skip final AOT without retaining an exclusive context.

Use the timeout only for exit_group, self SIGKILL, and signals that
already selected the default fatal action. Use an explicit exit reason
so ordinary call sites cannot accidentally select the final path.

Tests:
- meson test test-exclusive-timeout --print-errorlogs

Signed-off-by: Wenqiang Wei <weiwenqiang@mail.ustc.edu.cn>
2026-07-30 19:51:25 +08:00
yuerengan c27f620b46 LATX, fix: Complete Chromium namespace sandbox isolation
Signed-off-by: yuerengan <y347812075@163.com>
2026-07-29 17:00:29 +08:00
Hanlu Li c8cae54426 LATX, build: Require explicit test enablement
Define root-project test executables only when the tests feature is explicitly enabled. This keeps test-only binaries out of ordinary builds while preserving an explicit --enable-tests workflow.

The root-project audit found four Meson tests: three SMC reload tests and test-elfload-pagesize. The libvhost-user link-test is an unreferenced standalone subproject target, and gen-vdso is a build tool rather than a test.

RED before the fix with tests=auto:

  4 tests registered; all 4 executables had build_by_default=true.

GREEN with tests=auto:

  0 tests registered; 0 test targets; default ninja dry-run planned 0 test builds.

GREEN with tests=enabled:

  Built all 4 test executables explicitly.
  meson test reported 4/4 OK.

Signed-off-by: Hanlu Li <heuleehanlu@gmail.com>
2026-07-23 20:48:48 +08:00
Hanlu Li 5de651a1ac linux-user: Avoid PT_LOAD overlap on 16K hosts
On host pages larger than TARGET_PAGE_SIZE, keep using host-page
ELF load granularity only when widening a PT_LOAD down to the host
page boundary does not overlap another PT_LOAD.

The Claude Code x86_64 binary places the tail of an RX PT_LOAD and
start of a later RW PT_LOAD in the same 16K host page. Widening the
RW PT_LOAD backward to the host page start overwrites the earlier
.plt/.iplt bytes with zeros before guest execution begins. Execution
then reaches 0x00 0x00, decodes it as 'add byte ptr [rax], al', and
faults when the translated access touches address 0.

Fix this by selecting TARGET_PAGE_SIZE only for PT_LOADs whose
host-page widening would overlap another PT_LOAD. This preserves the
older host-page behavior for aligned non-overlapping data segments
while preventing a later writable segment from clobbering an earlier
executable tail page.

Add unit tests covering the overlap fallback, the aligned
non-overlapping host-page case, and the small-p_align fallback.
2026-06-10 11:50:43 +08:00
Hanlu Li c667f16d32 LATX, clean: Remove some submodules from configure
Signed-off-by: Hanlu Li <heuleehanlu@gmail.com>
2025-03-28 11:15:10 +08:00
Hanlu Li cbdb01a35a LATX, init: LATX user-level binary translator
Initialize the LATX (Loongson Architecture Translator for x86) project, a
high-performance user-level binary translator based on QEMU 6, designed to
efficiently run x86 applications on LoongArch architecture.

This commit merges nearly two thousand previous patchs into a single commit,
providing a clean baseline for LATX project.

Signed-off-by: Hanlu Li <heuleehanlu@gmail.com>
Change-Id: I26e76bc8b4ad5e71d65146113a9c13bd16cce62d
2025-03-21 15:26:22 +08:00
Peter Maydell d45a5270d0 Trivial patches pull request 20210503
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Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.1-pull-request' into staging

Trivial patches pull request 20210503

# gpg: Signature made Mon 03 May 2021 09:34:56 BST
# gpg:                using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg:                issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg:                 aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* remotes/vivier2/tags/trivial-branch-for-6.1-pull-request: (23 commits)
  hw/rx/rx-gdbsim: Do not accept invalid memory size
  docs: More precisely describe memory-backend-*::id's user
  scripts: fix generation update-binfmts templates
  docs/system: Document the removal of "compat" property for POWER CPUs
  mc146818rtc: put it into the 'misc' category
  Do not include exec/address-spaces.h if it's not really necessary
  Do not include cpu.h if it's not really necessary
  Do not include hw/boards.h if it's not really necessary
  Do not include sysemu/sysemu.h if it's not really necessary
  hw: Do not include qemu/log.h if it is not necessary
  hw: Do not include hw/irq.h if it is not necessary
  hw: Do not include hw/sysbus.h if it is not necessary
  hw: Remove superfluous includes of hw/hw.h
  ui: Fix memory leak in qemu_xkeymap_mapping_table()
  hw/usb: Constify VMStateDescription
  hw/display/qxl: Constify VMStateDescription
  hw/arm: Constify VMStateDescription
  vmstate: Constify some VMStateDescriptions
  Fix typo in CFI build documentation
  hw/pcmcia: Do not register PCMCIA type if not required
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-05 13:52:00 +01:00
Peter Maydell 87c6cef605 Aspeed patches :
* Fixes for the DMA space
 * New model for ASPEED's Hash and Crypto Engine (Joel and Klaus)
 * Acceptance tests (Joel)
 * A fix for the XDMA  model
 * Some extra features for the SMC controller.
 * Two new boards : rainier-bmc and quanta-q7l1-bmc (Patrick)
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Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20210503' into staging

Aspeed patches :

* Fixes for the DMA space
* New model for ASPEED's Hash and Crypto Engine (Joel and Klaus)
* Acceptance tests (Joel)
* A fix for the XDMA  model
* Some extra features for the SMC controller.
* Two new boards : rainier-bmc and quanta-q7l1-bmc (Patrick)

# gpg: Signature made Mon 03 May 2021 06:23:36 BST
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* remotes/legoater/tags/pull-aspeed-20210503:
  aspeed: Add support for the quanta-q7l1-bmc board
  hw/block: m25p80: Add support for mt25ql02g and mt25qu02g
  aspeed: Add support for the rainier-bmc board
  aspeed: Deprecate the swift-bmc machine
  tests/qtest: Rename m25p80 test in aspeed_smc test
  aspeed/smc: Add extra controls to request DMA
  aspeed/smc: Add a 'features' attribute to the object class
  hw/misc/aspeed_xdma: Add AST2600 support
  tests/acceptance: Test ast2600 machine
  tests/acceptance: Test ast2400 and ast2500 machines
  tests/qtest: Add test for Aspeed HACE
  aspeed: Integrate HACE
  hw: Model ASPEED's Hash and Crypto Engine
  hw/arm/aspeed: Do not sysbus-map mmio flash region directly, use alias
  aspeed/i2c: Rename DMA address space
  aspeed/i2c: Fix DMA address mask
  aspeed/smc: Remove unused "sdram-base" property
  aspeed/smc: Use the RAM memory region for DMAs

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-04 17:05:53 +01:00
Thomas Huth ee86213aa3 Do not include exec/address-spaces.h if it's not really necessary
Stop including exec/address-spaces.h in files that don't need it.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20210416171314.2074665-5-thuth@redhat.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-05-02 17:24:51 +02:00
Thomas Huth 4c386f8064 Do not include sysemu/sysemu.h if it's not really necessary
Stop including sysemu/sysemu.h in files that don't need it.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20210416171314.2074665-2-thuth@redhat.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-05-02 17:24:50 +02:00
Peter Maydell 15106f7dc3 Minor cleanups.
Finish the rest of the hexagon integer instructions.
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 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-hex-20210502' into staging

Minor cleanups.
Finish the rest of the hexagon integer instructions.

# gpg: Signature made Sun 02 May 2021 15:38:17 BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth-gitlab/tags/pull-hex-20210502: (31 commits)
  Hexagon (target/hexagon) CABAC decode bin
  Hexagon (target/hexagon) load into shifted register instructions
  Hexagon (target/hexagon) load and unpack bytes instructions
  Hexagon (target/hexagon) bit reverse (brev) addressing
  Hexagon (target/hexagon) circular addressing
  Hexagon (target/hexagon) add A4_addp_c/A4_subp_c
  Hexagon (target/hexagon) add A6_vminub_RdP
  Hexagon (target/hexagon) add A5_ACS (vacsh)
  Hexagon (target/hexagon) add F2_sfinvsqrta
  Hexagon (target/hexagon) add F2_sfrecipa instruction
  Hexagon (target/hexagon) compile all debug code
  Hexagon (target/hexagon) move QEMU_GENERATE to only be on during macros.h
  Hexagon (target/hexagon) cleanup reg_field_info definition
  Hexagon (target/hexagon) cleanup ternary operators in semantics
  Hexagon (target/hexagon) use softfloat for float-to-int conversions
  Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbn
  Hexagon (target/hexagon) use softfloat default NaN and tininess
  Hexagon (target/hexagon) change type of softfloat_roundingmodes
  Hexagon (target/hexagon) remove unused carry_from_add64 function
  Hexagon (target/hexagon) change variables from int to bool when appropriate
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-02 16:23:05 +01:00
Taylor Simpson e628c0156b Hexagon (target/hexagon) CABAC decode bin
The following instruction is added
    S2_cabacdecbin            Rdd32=decbin(Rss32,Rtt32)

Test cases added to tests/tcg/hexagon/misc.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-27-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01 16:06:11 -07:00
Taylor Simpson 7aa9ffab79 Hexagon (target/hexagon) load into shifted register instructions
The following instructions are added
    L2_loadalignb_io          Ryy32 = memb_fifo(Rs32+#s11:1)
    L2_loadalignh_io          Ryy32 = memh_fifo(Rs32+#s11:1)
    L4_loadalignb_ur          Ryy32 = memb_fifo(Rt32<<#u2+#U6)
    L4_loadalignh_ur          Ryy32 = memh_fifo(Rt32<<#u2+#U6)
    L4_loadalignb_ap          Ryy32 = memb_fifo(Re32=#U6)
    L4_loadalignh_ap          Ryy32 = memh_fifo(Re32=#U6)
    L2_loadalignb_pr          Ryy32 = memb_fifo(Rx32++Mu2)
    L2_loadalignh_pr          Ryy32 = memh_fifo(Rx32++Mu2)
    L2_loadalignb_pbr         Ryy32 = memb_fifo(Rx32++Mu2:brev)
    L2_loadalignh_pbr         Ryy32 = memh_fifo(Rx32++Mu2:brev)
    L2_loadalignb_pi          Ryy32 = memb_fifo(Rx32++#s4:1)
    L2_loadalignh_pi          Ryy32 = memh_fifo(Rx32++#s4:1)
    L2_loadalignb_pci         Ryy32 = memb_fifo(Rx32++#s4:1:circ(Mu2))
    L2_loadalignh_pci         Ryy32 = memh_fifo(Rx32++#s4:1:circ(Mu2))
    L2_loadalignb_pcr         Ryy32 = memb_fifo(Rx32++I:circ(Mu2))
    L2_loadalignh_pcr         Ryy32 = memh_fifo(Rx32++I:circ(Mu2))

Test cases in tests/tcg/hexagon/load_align.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-26-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01 16:06:11 -07:00
Taylor Simpson 0d0b91a804 Hexagon (target/hexagon) load and unpack bytes instructions
The following instructions are added
    L2_loadbzw2_io          Rd32 = memubh(Rs32+#s11:1)
    L2_loadbzw4_io          Rdd32 = memubh(Rs32+#s11:1)
    L2_loadbsw2_io          Rd32 = membh(Rs32+#s11:1)
    L2_loadbsw4_io          Rdd32 = membh(Rs32+#s11:1)

    L4_loadbzw2_ur          Rd32 = memubh(Rt32<<#u2+#U6)
    L4_loadbzw4_ur          Rdd32 = memubh(Rt32<<#u2+#U6)
    L4_loadbsw2_ur          Rd32 = membh(Rt32<<#u2+#U6)
    L4_loadbsw4_ur          Rdd32 = membh(Rt32<<#u2+#U6)

    L4_loadbzw2_ap          Rd32 = memubh(Re32=#U6)
    L4_loadbzw4_ap          Rdd32 = memubh(Re32=#U6)
    L4_loadbsw2_ap          Rd32 = membh(Re32=#U6)
    L4_loadbsw4_ap          Rdd32 = membh(Re32=#U6)

    L2_loadbzw2_pr          Rd32 = memubh(Rx32++Mu2)
    L2_loadbzw4_pr          Rdd32 = memubh(Rx32++Mu2)
    L2_loadbsw2_pr          Rd32 = membh(Rx32++Mu2)
    L2_loadbsw4_pr          Rdd32 = membh(Rx32++Mu2)

    L2_loadbzw2_pbr         Rd32 = memubh(Rx32++Mu2:brev)
    L2_loadbzw4_pbr         Rdd32 = memubh(Rx32++Mu2:brev)
    L2_loadbsw2_pbr         Rd32 = membh(Rx32++Mu2:brev)
    L2_loadbsw4_pbr         Rdd32 = membh(Rx32++Mu2:brev)

    L2_loadbzw2_pi          Rd32 = memubh(Rx32++#s4:1)
    L2_loadbzw4_pi          Rdd32 = memubh(Rx32++#s4:1)
    L2_loadbsw2_pi          Rd32 = membh(Rx32++#s4:1)
    L2_loadbsw4_pi          Rdd32 = membh(Rx32++#s4:1)

    L2_loadbzw2_pci         Rd32 = memubh(Rx32++#s4:1:circ(Mu2))
    L2_loadbzw4_pci         Rdd32 = memubh(Rx32++#s4:1:circ(Mu2))
    L2_loadbsw2_pci         Rd32 = membh(Rx32++#s4:1:circ(Mu2))
    L2_loadbsw4_pci         Rdd32 = membh(Rx32++#s4:1:circ(Mu2))

    L2_loadbzw2_pcr         Rd32 = memubh(Rx32++I:circ(Mu2))
    L2_loadbzw4_pcr         Rdd32 = memubh(Rx32++I:circ(Mu2))
    L2_loadbsw2_pcr         Rd32 = membh(Rx32++I:circ(Mu2))
    L2_loadbsw4_pcr         Rdd32 = membh(Rx32++I:circ(Mu2))

Test cases in tests/tcg/hexagon/load_unpack.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-25-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01 16:06:09 -07:00
Taylor Simpson af7f182127 Hexagon (target/hexagon) bit reverse (brev) addressing
The following instructions are added
    L2_loadrub_pbr          Rd32 = memub(Rx32++Mu2:brev)
    L2_loadrb_pbr           Rd32 = memb(Rx32++Mu2:brev)
    L2_loadruh_pbr          Rd32 = memuh(Rx32++Mu2:brev)
    L2_loadrh_pbr           Rd32 = memh(Rx32++Mu2:brev)
    L2_loadri_pbr           Rd32 = memw(Rx32++Mu2:brev)
    L2_loadrd_pbr           Rdd32 = memd(Rx32++Mu2:brev)
    S2_storerb_pbr          memb(Rx32++Mu2:brev).=.Rt32
    S2_storerh_pbr          memh(Rx32++Mu2:brev).=.Rt32
    S2_storerf_pbr          memh(Rx32++Mu2:brev).=.Rt.H32
    S2_storeri_pbr          memw(Rx32++Mu2:brev).=.Rt32
    S2_storerd_pbr          memd(Rx32++Mu2:brev).=.Rt32
    S2_storerinew_pbr       memw(Rx32++Mu2:brev).=.Nt8.new
    S2_storerbnew_pbr       memw(Rx32++Mu2:brev).=.Nt8.new
    S2_storerhnew_pbr       memw(Rx32++Mu2:brev).=.Nt8.new

Test cases in tests/tcg/hexagon/brev.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-24-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01 16:03:10 -07:00
Taylor Simpson 46ef47e2a7 Hexagon (target/hexagon) circular addressing
The following instructions are added
    L2_loadrub_pci          Rd32 = memub(Rx32++#s4:0:circ(Mu2))
    L2_loadrb_pci           Rd32 = memb(Rx32++#s4:0:circ(Mu2))
    L2_loadruh_pci          Rd32 = memuh(Rx32++#s4:1:circ(Mu2))
    L2_loadrh_pci           Rd32 = memh(Rx32++#s4:1:circ(Mu2))
    L2_loadri_pci           Rd32 = memw(Rx32++#s4:2:circ(Mu2))
    L2_loadrd_pci           Rdd32 = memd(Rx32++#s4:3:circ(Mu2))
    S2_storerb_pci          memb(Rx32++#s4:0:circ(Mu2)) = Rt32
    S2_storerh_pci          memh(Rx32++#s4:1:circ(Mu2)) = Rt32
    S2_storerf_pci          memh(Rx32++#s4:1:circ(Mu2)) = Rt.H32
    S2_storeri_pci          memw(Rx32++#s4:2:circ(Mu2)) = Rt32
    S2_storerd_pci          memd(Rx32++#s4:3:circ(Mu2)) = Rtt32
    S2_storerbnew_pci       memb(Rx32++#s4:0:circ(Mu2)) = Nt8.new
    S2_storerhnew_pci       memw(Rx32++#s4:1:circ(Mu2)) = Nt8.new
    S2_storerinew_pci       memw(Rx32++#s4:2:circ(Mu2)) = Nt8.new
    L2_loadrub_pcr          Rd32 = memub(Rx32++I:circ(Mu2))
    L2_loadrb_pcr           Rd32 = memb(Rx32++I:circ(Mu2))
    L2_loadruh_pcr          Rd32 = memuh(Rx32++I:circ(Mu2))
    L2_loadrh_pcr           Rd32 = memh(Rx32++I:circ(Mu2))
    L2_loadri_pcr           Rd32 = memw(Rx32++I:circ(Mu2))
    L2_loadrd_pcr           Rdd32 = memd(Rx32++I:circ(Mu2))
    S2_storerb_pcr          memb(Rx32++I:circ(Mu2)) = Rt32
    S2_storerh_pcr          memh(Rx32++I:circ(Mu2)) = Rt32
    S2_storerf_pcr          memh(Rx32++I:circ(Mu2)) = Rt32.H32
    S2_storeri_pcr          memw(Rx32++I:circ(Mu2)) = Rt32
    S2_storerd_pcr          memd(Rx32++I:circ(Mu2)) = Rtt32
    S2_storerbnew_pcr       memb(Rx32++I:circ(Mu2)) = Nt8.new
    S2_storerhnew_pcr       memh(Rx32++I:circ(Mu2)) = Nt8.new
    S2_storerinew_pcr       memw(Rx32++I:circ(Mu2)) = Nt8.new

Test cases in tests/tcg/hexagon/circ.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-23-git-send-email-tsimpson@quicinc.com>
[rth: Squash <1619667142-29636-1-git-send-email-tsimpson@quicinc.com>
removing gen_read_reg and gen_set_byte to avoid clang Werror.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01 16:01:39 -07:00
Richard Henderson af93ccacc7 decodetree: Extend argument set syntax to allow types
Rather than force all structure members to be 'int',
allow the type of the member to be specified.

Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01 11:45:35 -07:00
Taylor Simpson 57d352ac29 Hexagon (target/hexagon) add A4_addp_c/A4_subp_c
Rdd32 = add(Rss32, Rtt32, Px4):carry
    Add with carry
Rdd32 = sub(Rss32, Rtt32, Px4):carry
    Sub with carry

Test cases in tests/tcg/hexagon/multi_result.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-22-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01 08:31:43 -07:00
Taylor Simpson 0a65d28693 Hexagon (target/hexagon) add A6_vminub_RdP
Rdd32,Pe4 = vminub(Rtt32, Rss32)
    Vector min of bytes

Test cases in tests/tcg/hexagon/multi_result.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-21-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01 08:31:43 -07:00
Taylor Simpson da74cd2dce Hexagon (target/hexagon) add A5_ACS (vacsh)
Rxx32,Pe4 = vacsh(Rss32, Rtt32)
    Add compare and select elements of two vectors

Test cases in tests/tcg/hexagon/multi_result.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-20-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01 08:31:43 -07:00
Taylor Simpson dd8705bdf5 Hexagon (target/hexagon) add F2_sfinvsqrta
Rd32,Pe4 = sfinvsqrta(Rs32)
    Square root approx

The helper packs the 2 32-bit results into a 64-bit value,
and the fGEN_TCG override unpacks them into the proper results.

Test cases in tests/tcg/hexagon/multi_result.c
FP exception tests added to tests/tcg/hexagon/fpstuff.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-19-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01 08:31:43 -07:00
Taylor Simpson d934c16d8a Hexagon (target/hexagon) add F2_sfrecipa instruction
Rd32,Pe4 = sfrecipa(Rs32, Rt32)
    Recripocal approx

Test cases in tests/tcg/hexagon/multi_result.c
FP exception tests added to tests/tcg/hexagon/fpstuff.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-18-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01 08:31:43 -07:00
Taylor Simpson b3f37abdd3 Hexagon (target/hexagon) use softfloat for float-to-int conversions
Use the proper return for helpers that convert to unsigned
Remove target/hexagon/conv_emu.[ch]

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-13-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01 08:31:43 -07:00
Taylor Simpson 6c677c60ae Hexagon (target/hexagon) decide if pred has been written at TCG gen time
Multiple writes to the same preg are and'ed together.  Rather than
generating a runtime check, we can determine at TCG generation time
if the predicate has previously been written in the packet.

Test added to tests/tcg/hexagon/misc.c

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-7-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01 08:31:43 -07:00
Cédric Le Goater 5fde7f10c0 tests/qtest: Rename m25p80 test in aspeed_smc test
The m25p80 test depends on the Aspeed SMC controller to test our
SPI-NOR flash support. Reflect this dependency by changing the name.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20210407171637.777743-17-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-05-01 10:03:52 +02:00
Joel Stanley 224f010ba8 tests/acceptance: Test ast2600 machine
This tests a Debian multi-soc arm32 Linux kernel on the AST2600 based
Tacoma BMC machine.

There is no root file system so the test terminates when boot reaches
the stage where it attempts and fails to mount something.

Cc: Cleber Rosa <crosa@redhat.com>
Cc: Wainer dos Santos Moschetta <wainersm@redhat.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
[ clg : - removed comment
        - removed ending self.vm.shutdown() ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210304123951.163411-3-joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Message-Id: <20210407171637.777743-13-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-05-01 10:03:51 +02:00
Joel Stanley a3a178c663 tests/acceptance: Test ast2400 and ast2500 machines
Test MTD images from the OpenBMC project on AST2400 and AST2500 SoCs
from ASPEED, by booting Palmetto and Romulus BMC machines.

The images are fetched from OpenBMC's release directory on github.

Cc: Cleber Rosa <crosa@redhat.com>
Cc: Wainer dos Santos Moschetta <wainersm@redhat.com>
Co-developed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cleber Rosa <crosa@redhat.com>
Tested-by: Cleber Rosa <crosa@redhat.com>
[ clg : - removed comment
        - removed ending self.vm.shutdown() ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210304123951.163411-2-joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Message-Id: <20210407171637.777743-12-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-05-01 10:03:51 +02:00
Joel Stanley 666099520a tests/qtest: Add test for Aspeed HACE
This adds a test for the Aspeed Hash and Crypto (HACE) engine. It tests
the currently implemented behavior of the hash functionality.

The tests are similar, but are cut/pasted instead of broken out into a
common function so the assert machinery produces useful output when a
test fails.

Co-developed-by: Cédric Le Goater <clg@kaod.org>
Co-developed-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com>
Acked-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20210409000253.1475587-4-joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-05-01 10:03:51 +02:00
Peter Maydell 8f860d2633 QAPI patches patches for 2021-04-30
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Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-04-30' into staging

QAPI patches patches for 2021-04-30

# gpg: Signature made Fri 30 Apr 2021 12:42:32 BST
# gpg:                using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653
# gpg:                issuer "armbru@redhat.com"
# gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full]
# gpg:                 aka "Markus Armbruster <armbru@pond.sub.org>" [full]
# Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867  4E5F 3870 B400 EB91 8653

* remotes/armbru/tags/pull-qapi-2021-04-30: (25 commits)
  qapi/error.py: enable mypy checks
  qapi/error: Add type hints
  qapi/error.py: enable pylint checks
  qapi/error.py: move QAPIParseError to parser.py
  qapi/error: assert QAPISourceInfo is not None
  qapi/error: Make QAPISourceError 'col' parameter optional
  qapi/error: Use Python3-style super()
  qapi/error: Repurpose QAPIError as an abstract base exception class
  qapi/expr: Update authorship and copyright information
  qapi/expr.py: Use tuples instead of lists for static data
  qapi/expr.py: Add docstrings
  qapi/expr: Only explicitly prohibit 'Kind' nor 'List' for type names
  qapi/expr.py: enable pylint checks
  qapi/expr.py: Remove single-letter variable
  qapi/expr.py: Consolidate check_if_str calls in check_if
  qapi/expr.py: add type hint annotations
  qapi/expr.py: Modify check_keys to accept any Collection
  qapi/expr.py: Add casts in a few select cases
  qapi/expr.py: Check type of union and alternate 'data' member
  qapi/expr.py: move string check upwards in check_type
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-04-30 16:02:00 +01:00
Peter Maydell f38d1ea497 Block layer patches
- Fix permission update order problems with block graph changes
 - qemu-img convert: Unshare write permission for source
 - vhost-user-blk: Fail gracefully on too large queue size
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Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging

Block layer patches

- Fix permission update order problems with block graph changes
- qemu-img convert: Unshare write permission for source
- vhost-user-blk: Fail gracefully on too large queue size

# gpg: Signature made Fri 30 Apr 2021 11:27:51 BST
# gpg:                using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6
# gpg:                issuer "kwolf@redhat.com"
# gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full]
# Primary key fingerprint: DC3D EB15 9A9A F95D 3D74  56FE 7F09 B272 C88F 2FD6

* remotes/kevin/tags/for-upstream: (39 commits)
  vhost-user-blk: Fail gracefully on too large queue size
  qemu-img convert: Unshare write permission for source
  block: Add BDRV_O_NO_SHARE for blk_new_open()
  block: refactor bdrv_node_check_perm()
  block: rename bdrv_replace_child_safe() to bdrv_replace_child()
  block: refactor bdrv_child_set_perm_safe() transaction action
  block: inline bdrv_replace_child()
  block: inline bdrv_check_perm_common()
  block: drop unused permission update functions
  block: bdrv_reopen_multiple: refresh permissions on updated graph
  block: bdrv_reopen_multiple(): move bdrv_flush to separate pre-prepare
  block: add bdrv_set_backing_noperm() transaction action
  block: make bdrv_refresh_limits() to be a transaction action
  block: make bdrv_unset_inherits_from to be a transaction action
  block: drop ignore_children for permission update functions
  block/backup-top: drop .active
  block: introduce bdrv_drop_filter()
  block: add bdrv_remove_filter_or_cow transaction action
  block: adapt bdrv_append() for inserting filters
  block: split out bdrv_replace_node_noperm()
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-04-30 13:46:42 +01:00