Merge pull request #6981 from RT-Thread/master

sync from master

.github/SECURITY.md

@@ -1,34 +0,0 @@
-# Security Policy
-
-## Supported Versions
-
-The RT-Thread project supports the following versions with security updates:
-
-  - The most recent release, and the release prior to that.
-  - Active LTS releases.
-
-At this time, with the latest release of v5.0.0, the supported
-versions are:
-
-  - xxx
-  - xxx
-
-## Reporting a Vulnerability
-
-Please see [xx](xx) for detail about the security vulnerability reporting process.
-Vulnerabilities to the RT-Thread project may be reported via email to the XXX@XXX mailing list. These reports will be acknowledged and analyzed by the security response team within 1 week. Each vulnerability will be entered into the RT-Thread security advisory GitHub.
-
-To report a security vulnerability, you need to provide at least the following information:
-
-### Summary
-_Short summary of the problem. Make the impact and severity as clear as possible. For example: An unsafe deserialization vulnerability allows any unauthenticated user to execute arbitrary code on the server._
-
-### Details
-_Give all details on the vulnerability. Pointing to the incriminated source code is very helpful for the maintainer._
-
-### PoC
-_Complete instructions, including specific configuration details, to reproduce the vulnerability._
-
-### Impact
-_Give all affected versions. What kind of vulnerability is it? Which components are impacted?_ 
-

.github/workflows/action.yml

@@ -1,4 +1,4 @@
-name: RT-Thread BSP build check
+name: RT-Thread
 
 # Controls when the action will run. Triggers the workflow on push or pull request
 # events but only for the master branch
@@ -8,7 +8,7 @@ on:
     - cron:  '0 16 1 * *'
   push:
     branches:
-      - master
+      - serialX-dev
     paths-ignore:
       - documentation/**
       - '**/README.md'
@@ -33,264 +33,212 @@ jobs:
       fail-fast: false
       matrix:
        legs:
-         -  RTT_BSP: "others_at32_hc32"
-            RTT_TOOL_CHAIN: "sourcery-arm"
-            SUB_RTT_BSP: 
-                - "qemu-vexpress-a9"
-                - "airm2m/air32f103"
-                #- "airm2m/air105"
-                - "acm32/acm32f0x0-nucleo"
-                - "CME_M7"
-                - "apollo2"
-                - "asm9260t"
-                - "allwinner_tina"
-                - "ft32/ft32f072xb-starter"
-                - "mini2440"
-                - "at91/at91sam9g45"
-                - "at91/at91sam9260"
-                - "wch/arm/ch32f103c8-core"
-                - "wch/arm/ch32f203r-evt"
-                - "synwit/swm320"
-                - "synwit/swm341"
-                - "beaglebone"
-                - "zynqmp-r5-axu4ev"
-                - "at32/at32f403a-start"
-                - "at32/at32f407-start"
-                - "at32/at32f413-start"
-                - "at32/at32f415-start"
-                - "at32/at32f421-start"
-                - "at32/at32f423-start"
-                - "at32/at32f425-start"
-                - "at32/at32f435-start"
-                - "at32/at32f437-start"
-                - "yichip/yc3122-pos"
-                - "hc32/ev_hc32f4a0_lqfp176"
-                - "hc32/ev_hc32f460_lqfp100_v2"
-                - "hc32l196"
-                #- "tae32f5300"
-                - "mm32/mm32f3270-100ask-pitaya"
-                - "sam7x"   
-                - "hk32/hk32f030c8-mini"
-         -  RTT_BSP: "stm32l4_f0_f1" 
-            RTT_TOOL_CHAIN: "sourcery-arm"
-            SUB_RTT_BSP: 
-                - "stm32/stm32l4r5-st-nucleo"
-                - "stm32/stm32l4r9-st-eval"
-                - "stm32/stm32l4r9-st-sensortile-box"
-                - "stm32/stm32l010-st-nucleo"
-                - "stm32/stm32l053-st-nucleo"
-                - "stm32/stm32l412-st-nucleo"
-                - "stm32/stm32l431-BearPi"
-                - "stm32/stm32l432-st-nucleo"
-                - "stm32/stm32l433-ali-startkit"
-                - "stm32/stm32l433-st-nucleo"
-                - "stm32/stm32l452-st-nucleo"
-                - "stm32/stm32l475-atk-pandora"
-                - "stm32/stm32l475-st-discovery"
-                - "stm32/stm32l476-st-nucleo"
-                - "stm32/stm32l496-ali-developer"
-                - "stm32/stm32l496-st-nucleo"
-                - "stm32/stm32l496-st-discovery"
-                - "stm32/stm32f072-st-nucleo"
-                - "stm32/stm32f091-st-nucleo"
-                - "stm32/stm32f103-100ask-mini"
-                - "stm32/stm32f103-100ask-pro"
-                - "stm32/stm32f103-atk-nano"
-                - "stm32/stm32f103-atk-warshipv3"
-                - "stm32/stm32f103-blue-pill"
-                - "stm32/stm32f103-dofly-lyc8"
-                - "stm32/stm32f103-dofly-M3S"
-                - "stm32/stm32f103-fire-arbitrary"
-                - "stm32/stm32f103-gizwits-gokitv21"
-                - "stm32/stm32f103-hw100k-ibox"
-                - "stm32/stm32f103-onenet-nbiot"
-                - "stm32/stm32f103-yf-ufun"
-                - "stm32/stm32f103-ys-f1pro"
-                - "stm32/stm32f107-uc-eval"
-         -  RTT_BSP: "stm32_f2_f4" 
-            RTT_TOOL_CHAIN: "sourcery-arm"
-            SUB_RTT_BSP: 
-                - "stm32/stm32f207-st-nucleo"
-                - "stm32/stm32f302-st-nucleo"
-                - "stm32/stm32f401-st-nucleo"
-                - "stm32/stm32f401-weact-blackpill"
-                - "stm32/stm32f405-smdz-breadfruit"
-                - "stm32/stm32f407-armfly-v5"
-                - "stm32/stm32f407-atk-explorer"
-                - "stm32/stm32f407-robomaster-c"
-                - "stm32/stm32f407-st-discovery"
-                - "stm32/stm32f410-st-nucleo"
-                - "stm32/stm32f411-atk-nano"
-                - "stm32/stm32f411-st-nucleo"
-                - "stm32/stm32f411-weact-blackpill" 
-                - "stm32/stm32f412-st-nucleo"
-                - "stm32/stm32f413-st-nucleo"
-                - "stm32/stm32f427-robomaster-a"
-                - "stm32/stm32f429-armfly-v6"
-                - "stm32/stm32f429-atk-apollo"
-                - "stm32/stm32f429-fire-challenger"
-                - "stm32/stm32f429-st-disco"
-                - "stm32/stm32f446-st-nucleo"
-                - "stm32/stm32f469-st-disco"
-         -  RTT_BSP: "stm32_f7_g0_h7_mp15_u5_wb5" 
-            RTT_TOOL_CHAIN: "sourcery-arm"
-            SUB_RTT_BSP: 
-                - "stm32/stm32f746-st-disco"
-                - "stm32/stm32f746-st-nucleo"
-                - "stm32/stm32f767-atk-apollo"
-                - "stm32/stm32f767-fire-challenger-v1"
-                - "stm32/stm32f767-st-nucleo"
-                - "stm32/stm32f769-st-disco"
-                - "stm32/stm32f723-st-disco"
-                - "stm32/stm32g070-st-nucleo"
-                - "stm32/stm32g071-st-nucleo"
-                - "stm32/stm32g431-st-nucleo"
-                - "stm32/stm32g474-st-nucleo"
-                - "stm32/stm32h743-armfly-v7"
-                - "stm32/stm32h743-atk-apollo"
-                - "stm32/stm32h743-openmv-h7plus"
-                - "stm32/stm32h743-st-nucleo"
-                - "stm32/stm32h747-st-discovery"
-                - "stm32/stm32h750-artpi"
-                - "stm32/stm32h750-weact-ministm32h7xx"
-                - "stm32/stm32h750-fk750m1-vbt6"
-                - "stm32/stm32mp157a-st-discovery"
-                - "stm32/stm32mp157a-st-ev1"
-                - "stm32/stm32u575-st-nucleo"
-                - "stm32/stm32wb55-st-nucleo"
-         -  RTT_BSP: "nxp_renesas" 
-            RTT_TOOL_CHAIN: "sourcery-arm"
-            SUB_RTT_BSP: 
-                - "lpc55sxx/lpc55s69_nxp_evk"
-                - "lpc55sxx/lpc55s28_nxp_evk"
-                - "lpc55sxx/lpc55s06_nxp_evk"
-                - "lpc55sxx/lpc55s16_nxp_evk"
-                - "lpc55sxx/lpc55s36_nxp_evk"
-                - "lpc178x"
-                - "lpc408x"
-                - "lpc1114"
-                - "lpc2148"
-                - "lpc2478"
-                - "lpc5410x"
-                - "lpc54114-lite"
-                - "imx6sx/cortex-a9"
-                - "imxrt/imxrt1052-atk-commander"
-                - "imxrt/imxrt1052-fire-pro"
-                - "imxrt/imxrt1052-nxp-evk"
-                - "imxrt/imxrt1052-seeed-ArchMix"
-                - "imxrt/imxrt1060-nxp-evk"
-                - "imxrt/imxrt1064-nxp-evk"
-                - "frdm-k64f"
-                - "lpc176x"
-                - "xplorer4330/M4"
-                #- "lpc43xx/M4"
-                - "renesas/ra6m3-ek"
-                - "renesas/ra6m4-cpk"
-                - "renesas/ra6m3-hmi-board"  
-         -  RTT_BSP: "gd32_n32_apm32"   
-            RTT_TOOL_CHAIN: "sourcery-arm"
-            SUB_RTT_BSP:             
-                - "gd32/arm/gd32103c-eval" 
-                - "gd32/arm/gd32105c-eval" 
-                - "gd32/arm/gd32105r-start"
-                - "gd32/arm/gd32107c-eval" 
-                - "gd32/arm/gd32205r-start"
-                - "gd32/arm/gd32207i-eval" 
-                - "gd32/arm/gd32303e-eval" 
-                - "gd32/arm/gd32303c-start"
-                - "gd32/arm/gd32305r-start"
-                - "gd32/arm/gd32307e-start"
-                - "gd32/arm/gd32407v-start"
-                - "gd32/arm/gd32450z-eval" 
-                - "gd32/arm/gd32470z-lckfb"
-                - "gd32e230k-start"        
-                - "gd32303e-eval"
-                - "gd32450z-eval"
-                - "n32/n32g43xcl-stb"
-                - "n32/n32g45xcl-stb"
-                - "n32/n32g45xml-stb"
-                - "n32/n32g45xrl-stb"
-                - "n32/n32g45xvl-stb"
-                - "n32/n32g457qel-stb"
-                - "n32/n32g4frml-stb"
-                - "n32/n32l40xcl-stb"
-                - "n32/n32l43xml-stb"
-                - "n32/n32l43xrl-stb"
-                - "n32/n32l436-evb"
-                - "n32/n32wb45xl-evb"
-                - "apm32/apm32f103xe-minibroard"
-                - "apm32/apm32f407ig-minibroard"
-                - "apm32/apm32f407zg-evalboard"
-                - "apm32/apm32f072vb-miniboard"
-                - "apm32/apm32f107vc-evalboard"
-                - "apm32/apm32f030r8-miniboard"
-                - "apm32/apm32f051r8-evalboard"
-                - "apm32/apm32f091vc-miniboard"
-                - "apm32/apm32f103vb-miniboard"
-                - "apm32/apm32e103ze-evalboard"
-                - "apm32/apm32e103ze-tinyboard"
-                - "apm32/apm32s103vb-miniboard"
-         -  RTT_BSP: "nordic_Infineon_TI_microchip" 
-            RTT_TOOL_CHAIN: "sourcery-arm"
-            SUB_RTT_BSP:  
-                - "nrf5x/nrf51822"
-                - "nrf5x/nrf52832"
-                - "nrf5x/nrf52833"
-                - "nrf5x/nrf52840"
-                - "nrf5x/nrf5340"
-                - "Infineon/psoc6-cy8ckit-062S2-43012"
-                - "Infineon/psoc6-cy8ckit-062-BLE"
-                - "Infineon/psoc6-cy8ckit-062s4"
-                - "Infineon/psoc6-cy8ckit-062-WIFI-BT"
-                - "Infineon/psoc6-cy8cproto-062S3-4343W"
-                - "Infineon/psoc6-evaluationkit-062S2"
-                - "fujitsu/mb9x/mb9bf500r"
-                - "fujitsu/mb9x/mb9bf506r"
-                - "fujitsu/mb9x/mb9bf618s"
-                - "fujitsu/mb9x/mb9bf568r"
-                - "raspberry-pico"
-                - "raspberry-pi/raspi3-32"
-                - "raspberry-pi/raspi4-32"
-                - "lm3s8962"
-                - "lm3s9b9x"
-                - "lm4f232"
-                - "tm4c123bsp"
-                - "tm4c129x"
-                - "microchip/samc21"
-                - "microchip/same54"
-                - "microchip/same70"
-                - "smartfusion2"
-                - "maxim/max32660-evsys"
-                - "efm32"
-         -  RTT_BSP: "mips" 
-            RTT_TOOL_CHAIN: "sourcery-mips"
-            SUB_RTT_BSP:  
-                - "loongson/ls1bdev"
-                - "loongson/ls2kdev"
-                - "loongson/ls1cdev"
-         -  RTT_BSP: "aarch64" 
-            RTT_TOOL_CHAIN: "sourcery-aarch64"
-            SUB_RTT_BSP:  
-                - "qemu-virt64-aarch64"
-                - "raspberry-pi/raspi3-64"
-                - "raspberry-pi/raspi4-64"
-                - "rockchip/rk3568"
-         -  RTT_BSP: "riscv-none" 
-            RTT_TOOL_CHAIN: "sourcery-riscv-none-embed"
-            SUB_RTT_BSP:  
-                - "gd32vf103v-eval"
-                - "k210"
-         -  RTT_BSP: "riscv64-unknown" 
-            RTT_TOOL_CHAIN: "sourcery-riscv64-unknown-elf"
-            SUB_RTT_BSP:  
-                - "bluetrum/ab32vg1-ab-prougen"
-                - "bouffalo_lab/bl60x"
-                - "bouffalo_lab/bl70x"
-         -  RTT_BSP: "llvm-arm" 
-            RTT_TOOL_CHAIN: "llvm-arm"
-            SUB_RTT_BSP:  
-                - "stm32/stm32l475-atk-pandora"
-                - "renesas/ra6m3-hmi-board"
+         - {RTT_BSP: "airm2m/air32f103", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "acm32/acm32f0x0-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "CME_M7", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "apm32/apm32f103xe-minibroard", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "apm32/apm32f407ig-minibroard", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "apm32/apm32f072vb-miniboard", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "apm32/apm32f107vc-evalboard", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "apm32/apm32f030r8-miniboard", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "apm32/apm32f051r8-evalboard", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "apm32/apm32f091vc-miniboard", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "apm32/apm32f103vb-miniboard", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "apm32/apm32f407zg-evalboard", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "apollo2", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "asm9260t", RTT_TOOL_CHAIN: "sourcery-arm"}
+        #  - {RTT_BSP: "ft2004", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "at91/at91sam9g45", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "at91/at91sam9260", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "allwinner_tina", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "Infineon/psoc6-cy8ckit-062S2-43012", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "Infineon/psoc6-cy8ckit-062-BLE", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "Infineon/psoc6-cy8ckit-062s4", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "Infineon/psoc6-cy8ckit-062-WIFI-BT", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "Infineon/psoc6-cy8cproto-062S3-4343W", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "Infineon/psoc6-evaluationkit-062S2", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "ft32/ft32f072xb-starter", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "n32/n32g43xcl-stb", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "n32/n32g45xcl-stb", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "n32/n32g45xml-stb", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "n32/n32g45xrl-stb", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "n32/n32g45xvl-stb", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "n32/n32g457qel-stb", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "n32/n32g4frml-stb", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "n32/n32l40xcl-stb", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "n32/n32l43xml-stb", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "n32/n32l43xrl-stb", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "n32/n32l436-evb", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "n32/n32wb45xl-evb", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "gd32/arm/gd32103c-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "gd32/arm/gd32105c-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "gd32/arm/gd32105r-start", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "gd32/arm/gd32107c-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "gd32/arm/gd32205r-start", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "gd32/arm/gd32207i-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "gd32/arm/gd32303e-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "gd32/arm/gd32303c-start", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "gd32/arm/gd32305r-start", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "gd32/arm/gd32307e-start", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "gd32/arm/gd32407v-start", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "gd32/arm/gd32450z-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "gd32e230k-start", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "gd32vf103v-eval", RTT_TOOL_CHAIN: "sourcery-riscv-none-embed"}
+         - {RTT_BSP: "gd32303e-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "gd32450z-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "imx6sx/cortex-a9", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "imxrt/imxrt1052-atk-commander", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "imxrt/imxrt1052-fire-pro", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "imxrt/imxrt1052-nxp-evk", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "imxrt/imxrt1052-seeed-ArchMix", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "imxrt/imxrt1060-nxp-evk", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "imxrt/imxrt1064-nxp-evk", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lm3s8962", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lm3s9b9x", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lm4f232", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "tm4c123bsp", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "tkm32F499", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "tm4c129x", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc43xx/M4", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc176x", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc55sxx/lpc55s69_nxp_evk", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc178x", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc408x", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc1114", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc2148", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc2478", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc5410x", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc54114-lite", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "loongson/ls1bdev", RTT_TOOL_CHAIN: "sourcery-mips"}
+         - {RTT_BSP: "loongson/ls1cdev", RTT_TOOL_CHAIN: "sourcery-mips"}
+         - {RTT_BSP: "loongson/ls2kdev", RTT_TOOL_CHAIN: "sourcery-mips"}
+         - {RTT_BSP: "fujitsu/mb9x/mb9bf500r", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "fujitsu/mb9x/mb9bf506r", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "fujitsu/mb9x/mb9bf618s", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "fujitsu/mb9x/mb9bf568r", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "mini2440", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "mm32/mm32f3270-100ask-pitaya", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "nrf5x/nrf51822", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "nrf5x/nrf52832", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "nrf5x/nrf52833", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "nrf5x/nrf52840", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "nrf5x/nrf5340", RTT_TOOL_CHAIN: "sourcery-arm"}         
+         - {RTT_BSP: "qemu-vexpress-a9", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "sam7x", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f072-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f091-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-100ask-mini", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-100ask-pro", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-atk-nano", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-atk-warshipv3", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-blue-pill", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-dofly-lyc8", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-dofly-M3S", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-fire-arbitrary", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-gizwits-gokitv21", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-hw100k-ibox", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-onenet-nbiot", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-yf-ufun", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-ys-f1pro", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f107-uc-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f207-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f302-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f401-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f405-smdz-breadfruit", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f407-armfly-v5", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f407-atk-explorer", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f407-robomaster-c", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f407-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f410-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f411-atk-nano", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f411-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f411-weact-blackpill", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f412-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f413-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f427-robomaster-a", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f429-armfly-v6", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f429-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f429-fire-challenger", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f429-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f446-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f469-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f746-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f746-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f767-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f767-fire-challenger-v1", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f767-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f769-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32g070-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32g071-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32g431-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32g474-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32h743-armfly-v7", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32h743-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32h743-openmv-h7plus", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32h743-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32h747-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"}
+        #  - {RTT_BSP: "stm32h750-armfly-h7-tool", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32h750-artpi", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32h750-weact-ministm32h7xx", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l4r5-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l4r9-st-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l4r9-st-sensortile-box", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l010-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l053-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l412-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l431-BearPi", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l432-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l433-ali-startkit", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l433-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l452-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l475-atk-pandora", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l475-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l476-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l496-ali-developer", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l496-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l552-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32mp157a-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32mp157a-st-ev1", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32u575-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32wb55-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+        #  - {RTT_BSP: "stm32/stm32wl55-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+        #  - {RTT_BSP: "stm32/stm32wle5-yizhilian-lm401", RTT_TOOL_CHAIN: "sourcery-arm"}
+        #  - {RTT_BSP: "stm32/stm32wle5-yizhilian-lm402", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "renesas/ra6m3-ek", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "renesas/ra6m4-cpk", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "wch/arm/ch32f103c8-core", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "wch/arm/ch32f203r-evt", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "synwit/swm320", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "synwit/swm341", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "beaglebone", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "zynqmp-r5-axu4ev", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "frdm-k64f", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "xplorer4330/M4", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "at32/at32f403a-start", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "at32/at32f407-start", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "at32/at32f413-start", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "at32/at32f415-start", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "at32/at32f421-start", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "at32/at32f425-start", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "at32/at32f435-start", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "at32/at32f437-start", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "smartfusion2", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "raspberry-pico", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "raspberry-pi/raspi3-32", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "raspberry-pi/raspi4-32", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "hc32/ev_hc32f4a0_lqfp176", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "hc32/ev_hc32f460_lqfp100_v2", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "hc32l196", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "tae32f5300", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "bluetrum/ab32vg1-ab-prougen", RTT_TOOL_CHAIN: "sourcery-riscv64-unknown-elf"}
+         - {RTT_BSP: "k210", RTT_TOOL_CHAIN: "sourcery-riscv-none-embed"}
+         - {RTT_BSP: "qemu-virt64-aarch64", RTT_TOOL_CHAIN: "sourcery-aarch64"}
+         - {RTT_BSP: "raspberry-pi/raspi3-64", RTT_TOOL_CHAIN: "sourcery-aarch64"}
+         - {RTT_BSP: "raspberry-pi/raspi4-64", RTT_TOOL_CHAIN: "sourcery-aarch64"}
+         - {RTT_BSP: "rockchip/rk3568", RTT_TOOL_CHAIN: "sourcery-aarch64"}
+         - {RTT_BSP: "microchip/samc21", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "microchip/same54", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "microchip/same70", RTT_TOOL_CHAIN: "sourcery-arm"}
     steps:
       - uses: actions/checkout@v3
       - name: Set up Python
@@ -302,7 +250,7 @@ jobs:
         shell: bash
         run: |
           sudo apt-get update
-          sudo apt-get -qq install gcc-multilib libncurses5 libncurses5-dev libncursesw5-dev scons
+          sudo apt-get -qq install gcc-multilib libncurses5-dev scons
           sudo python -m pip install --upgrade pip -qq
           pip install requests -qq
           git config --global http.postBuffer 524288000
@@ -319,16 +267,6 @@ jobs:
           /opt/gcc-arm-none-eabi-10-2020-q4-major/bin/arm-none-eabi-gcc --version
           echo "RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-10-2020-q4-major/bin" >> $GITHUB_ENV
 
-      - name: Install LLVM-Arm ToolChains
-        if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'llvm-arm' && success() }}
-        shell: bash
-        run: |
-          wget -q https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-16.0.0/LLVMEmbeddedToolchainForArm-16.0.0-Linux-x86_64.tar.gz
-          sudo tar zxf LLVMEmbeddedToolchainForArm-16.0.0-Linux-x86_64.tar.gz -C /opt
-          /opt/LLVMEmbeddedToolchainForArm-16.0.0-Linux-x86_64/bin/clang --version
-          echo "RTT_CC=llvm-arm" >> $GITHUB_ENV
-          echo "RTT_EXEC_PATH=/opt/LLVMEmbeddedToolchainForArm-16.0.0-Linux-x86_64/bin" >> $GITHUB_ENV
-
       - name: Install AArch64 ToolChains
         if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-aarch64' && success() }}
         shell: bash
@@ -351,7 +289,7 @@ jobs:
         if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-riscv64-unknown-elf' && success() }}
         run: |
           wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.4/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14.tar.gz
-          sudo tar zxf riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14.tar.gz -C /opt
+          sudo tar zxvf riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14.tar.gz -C /opt
           /opt/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gcc --version
           echo "RTT_EXEC_PATH=/opt/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14/bin" >> $GITHUB_ENV
 
@@ -359,7 +297,7 @@ jobs:
         if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-riscv-none-embed' && success() }}
         run: |
           wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.5/xpack-riscv-none-embed-gcc-8.3.0-2.3-linux-x64.tar.gz
-          sudo tar zxf xpack-riscv-none-embed-gcc-8.3.0-2.3-linux-x64.tar.gz -C /opt
+          sudo tar zxvf xpack-riscv-none-embed-gcc-8.3.0-2.3-linux-x64.tar.gz -C /opt
           /opt/xpack-riscv-none-embed-gcc-8.3.0-2.3/bin/riscv-none-embed-gcc --version
           echo "RTT_EXEC_PATH=/opt/xpack-riscv-none-embed-gcc-8.3.0-2.3/bin" >> $GITHUB_ENV
 
@@ -369,21 +307,7 @@ jobs:
         env:
           RTT_BSP: ${{ matrix.legs.RTT_BSP }}
           RTT_TOOL_CHAIN: ${{ matrix.legs.RTT_TOOL_CHAIN }}
-          SRTT_BSP: ${{ join(matrix.legs.SUB_RTT_BSP, ',') }}
         run: |
           source ~/.env/env.sh
-          failed=0
-          count=0
-          for bsp in $(echo $SRTT_BSP | tr ',' '\n'); do
-            count=$((count+1))
-            echo "::group::Compiling BSP: ==$count=== $bsp ===="
-            echo bsp/$bsp
-            pushd bsp/$bsp && pkgs --update && popd
-            scons -C bsp/$bsp -j$(nproc) --debug=time | tee output.log || \
-            { total_time=$(grep "Total command execution time" output.log | awk '{print $5}'); \
-              failed=$((failed+1)) ; echo "::endgroup::" ; echo "::error::build $bsp failed" ; \
-              echo "- ❌ build $bsp failed in $total_time seconds " >> $GITHUB_STEP_SUMMARY ; } && \
-            { total_time=$(grep "Total command execution time" output.log | awk '{print $5}'); \
-              echo "- ✅ build $bsp success in $total_time seconds " >> $GITHUB_STEP_SUMMARY ; echo "::endgroup::" ; }
-          done
-          exit $failed
+          pushd bsp/$RTT_BSP && pkgs --update && popd
+          scons -C bsp/$RTT_BSP

.github/workflows/action_tools.yml

@@ -77,8 +77,3 @@ jobs:
         echo "Test to dist project"
         scons --dist -C $TEST_BSP_ROOT
         scons --dist-ide -C $TEST_BSP_ROOT
-        ls $TEST_BSP_ROOT
-        ls $TEST_BSP_ROOT/dist
-        scons -C $TEST_BSP_ROOT/dist/project
-        scons -C $TEST_BSP_ROOT/rt-studio-project
-        

.github/workflows/action_utest.yml

@@ -37,13 +37,9 @@ jobs:
          - {UTEST: "kernel/irq",       RTT_BSP: "bsp/qemu-vexpress-a9",    QEMU_ARCH: "arm",      QEMU_MACHINE: "vexpress-a9", CONFIG_FILE: "kernel/irq.conf",     SD_FILE: "sd.bin", RUN: "yes"}
          - {UTEST: "kernel/timer",     RTT_BSP: "bsp/qemu-vexpress-a9",    QEMU_ARCH: "arm",      QEMU_MACHINE: "vexpress-a9", CONFIG_FILE: "kernel/timer.conf",   SD_FILE: "sd.bin", RUN: "yes"}
          - {UTEST: "kernel/thread",    RTT_BSP: "bsp/qemu-vexpress-a9",    QEMU_ARCH: "arm",      QEMU_MACHINE: "vexpress-a9", CONFIG_FILE: "kernel/thread.conf",  SD_FILE: "sd.bin", RUN: "yes"}
-         - {UTEST: "kernel/atomic",    RTT_BSP: "bsp/qemu-vexpress-a9",    QEMU_ARCH: "arm",      QEMU_MACHINE: "vexpress-a9", CONFIG_FILE: "kernel/atomic.conf",  SD_FILE: "sd.bin", RUN: "yes"}
-         - {UTEST: "kernel/atomic_c11",    RTT_BSP: "bsp/qemu-vexpress-a9",    QEMU_ARCH: "arm",      QEMU_MACHINE: "vexpress-a9", CONFIG_FILE: "kernel/atomic_c11.conf",  SD_FILE: "sd.bin", RUN: "yes"}
          - {UTEST: "components/utest", RTT_BSP: "bsp/qemu-vexpress-a9",    QEMU_ARCH: "arm",      QEMU_MACHINE: "vexpress-a9", CONFIG_FILE: "utest_self/self.conf", SD_FILE: "sd.bin", RUN: "yes"}
          - {UTEST: "components/cpp11", RTT_BSP: "bsp/qemu-vexpress-a9",    QEMU_ARCH: "arm",      QEMU_MACHINE: "vexpress-a9", CONFIG_FILE: "cpp11/cpp11.conf",    SD_FILE: "sd.bin", RUN: "yes"}
          - {UTEST: "kernel/mem/riscv64", RTT_BSP: "bsp/qemu-virt64-riscv", QEMU_ARCH: "riscv64",  QEMU_MACHINE: "virt",  CONFIG_FILE: "kernel/mem.conf",   SD_FILE: "None", RUN: "yes"}
-         - {UTEST: "kernel/atomic/riscv64", RTT_BSP: "bsp/qemu-virt64-riscv", QEMU_ARCH: "riscv64",  QEMU_MACHINE: "virt",  CONFIG_FILE: "kernel/atomic.conf",   SD_FILE: "None", RUN: "yes"}
-         - {UTEST: "kernel/atomic_c11/riscv64", RTT_BSP: "bsp/qemu-virt64-riscv", QEMU_ARCH: "riscv64",  QEMU_MACHINE: "virt",  CONFIG_FILE: "kernel/atomic_c11.conf",   SD_FILE: "None", RUN: "yes"}
          - {UTEST: "rtsmart/arm",     RTT_BSP: "bsp/qemu-vexpress-a9",    QEMU_ARCH: "arm",      QEMU_MACHINE: "vexpress-a9", CONFIG_FILE: "rtsmart/base.conf",   SD_FILE: "sd.bin", RUN: "no"}
          - {UTEST: "rtsmart/aarch64", RTT_BSP: "bsp/qemu-virt64-aarch64", QEMU_ARCH: "aarch64",  QEMU_MACHINE: "virt",  CONFIG_FILE: "rtsmart/base.conf",   SD_FILE: "sd.bin", RUN: "no"}
          - {UTEST: "rtsmart/riscv64", RTT_BSP: "bsp/qemu-virt64-riscv",   QEMU_ARCH: "riscv64",  QEMU_MACHINE: "virt",  CONFIG_FILE: "rtsmart/base.conf",   SD_FILE: "None", RUN: "yes"}

.github/workflows/file_check.yml

@@ -17,4 +17,4 @@ jobs:
         shell: bash
         run: |
           pip install click chardet PyYaml
-          python tools/ci/file_check.py check 'https://github.com/RT-Thread/rt-thread' 'master'
+          python tools/file_check.py check 'https://github.com/RT-Thread/rt-thread' 'master'

.github/workflows/static_code_analysis.yml

@@ -1,30 +0,0 @@
-name: Static code analysis
-
-on:
-  pull_request:
-    branches:
-      - master
-
-jobs:
-  scancode_job:
-    runs-on: ubuntu-latest
-    name: Static code analysis
-    steps:
-      - uses: actions/checkout@v3
-      - name: Set up Python
-        uses: actions/setup-python@v3
-        with:
-          python-version: 3.8
-      
-      - name: cppcheck
-        shell: bash
-        run: |
-          sudo apt-get update
-          sudo apt-get -qq install cppcheck
-          pip install click PyYaml
-          git remote -v
-          git fetch origin
-          cppcheck --version
-          ls
-          git branch -a
-          python tools/ci/cpp_check.py check

.gitignore

@@ -28,7 +28,7 @@ documentation/html
 *.dfinish
 *.su
 #source insight 4 project files
-*.si4project
+*.si4project 
 tools/kconfig-frontends/kconfig-mconf
 packages
 dist
@@ -45,8 +45,6 @@ tags
 
 .idea
 .vscode
-*.code-workspace
-*.eide.*
 .history
 CMakeLists.txt
 cmake-build-debug

.hooks/pre-commit

@@ -1,70 +0,0 @@
-#!/bin/sh
-# AUTHOR: supperthomas
-
-if git rev-parse --verify HEAD >/dev/null 2>&1
-then
-	against=HEAD
-else
-	# Initial commit: diff against an empty tree object
-	against=$(git hash-object -t tree /dev/null)
-fi
-
-# We only filter the file name with c or cpp file.
-changed_files=$(git diff-index --cached $against | \
-	grep -E '[MA]	.*\.(c|cpp|cc|cxx)$' | cut -d'	' -f 2)
-
-
-if which cppcheck > /dev/null; then 
-	if [ -n "$changed_files" ]; then
-		cppcheck --enable=warning,performance,portability --inline-suppr --error-exitcode=1 --platform=win64 --force $changed_files
-		err=$?
-		if [ $err -ne 0 ]; then
-			echo "[rt-thread][cppcheck] we found a obvious fault, please fix the error then commit again"
-			exit $err
-		else
-			echo "[rt-thread][cppcheck] cppcheck ok."
-		fi
-	fi
-else
-    echo "cppcheck does not exist" 
-fi
-
-# We only filter the file name with c or cpp or h file.
-# astyle only astyle the added file[because of code reivewer], if you want change modify file, please use [MA]
-changed_files=$(git diff-index --cached $against | \
-	grep -E '[MA]	.*\.(c|cpp|h)$' | cut -d'	' -f 2)
-
-if which astyle > /dev/null; then 
-	if [ -n "$changed_files" ]; then
-		astyle --style=allman --indent=spaces=4 --indent=spaces=4 --indent=spaces=4 --pad-header --pad-header --pad-header --align-pointer=name --lineend=linux --convert-tabs --verbose  $changed_files
-		err=$?
-		if [ $err -ne 0 ]; then
-			echo "[rt-thread][astyle] we found a obvious fault, please fix the error then commit again"
-			exit $err
-		else
-			echo "[rt-thread][astyle] astyle file ok"
-		fi
-	fi
-else
-    echo "astyle does not exist" 
-fi
-
-# We only filter the file name with c or cpp file.
-changed_files=$(git diff-index --cached $against | \
-	grep -E '[MA]	.*\.(c|cpp|h)$' | cut -d'	' -f 2)
-# formatting check
-# https://github.com/mysterywolf/formatting
-# formatting cmd ref https://github.com/supperthomas/git_auto_script
-if which formatting > /dev/null; then 
-	if [ -n "$changed_files" ]; then
-		formatting $changed_files
-		echo "[rt-thread] formatting $changed_files is ok"
-		git add $changed_files
-		exit 0
-	fi
-else
-    echo "formatting does not exist" 
-fi
-
-exit 0
-

.hooks/readme.md

@@ -1,15 +0,0 @@
-# How to use git hook
-
-## SDK install 
-
-Please use cmd `git config --local core.hooksPath .hooks` for git hooks local.
-
-## git hooks使用注意事项
-
-- hooks里面的要安装cppcheck和astyle以及formatting命令行才能使用，如果想要去掉某个选项，在pre-commit中注释掉相应的命令即可。
-- 取消hook选项请使用命令`git config --unset --local core.hooksPath .hooks` 可以取消hook格式化文件
-- 这个githook不敲命令是不生效的
-- githook会用astyle格式化一些文件（这个按照rt-thread coding-style里面的设置来的），这里要注意，如果之前文件没有经过astlye格式化的话，会出现很多修改，如果修改过多，建议不用astyle进行格式化。
-- formatting命令只针对`c|cpp|h` 文件，并没有针对文件夹修改等。所以如果有SDK等不希望formatting的文件，请先将hooks功能去掉，commit之后，再考虑使用hooks命令。
-- 如果对git的pre-commit不是很熟悉，建议可以先不用这个hooks。
-

ChangeLog.md

@@ -1,79 +1,3 @@
-# RT-Thread v5.0.0 released
-
-Change log since v4.1.1 released
-
-## kernel
-- Add RT-Thread Smart features, Support user-mode app.
-- Add atomic feature.
-- Add nested mutex feature.
-- Add rt_ssize_t data structure.
-- Add static name for rt_object (#6422).
-- Adopt new version macro definition version control specification: https://semver.org
-- Split scheduler.c (#7103).
-- Fix the Oz optimization problem of AC6 compiler in memheap.
-- Fix rt_memset to be word size independent.
-- Modify RT_ALIGN_SIZE as 8 by default
-
-## Components
-- Add FDT(Flattened Device Tree), TMPFS, CRomFS,
-- Libc:
-  - add musl libc support.
-  - Improve Posix support.
-- LWP:
-  - Add more syscall support.
-  - Add mm(virtual memory management layer) feature.
-  - Improve clock accuracy.
-- Network: add AF_UNIX feature.
-- Drivers Device:
-  - Improve device: sensor, spi, i2c, serial, can, usb, cpu_time, sdio, pwm, etc.
-
-## BSP
-- Add RT-Thread Smart support with some BSP: D1/D1s, raspberry, qemu-vexpress-a9, qemu-virt64-aarch64,qemu-virt64-riscv.
-- Add company readme.md under bsp dir.
-- Fix that use RT_ERROR, RT_EFULL, RT_ENOMEM, RT_EEMPTY, etc.
-- Add some new BSPs:
-  - bouffalo_lab: bl60x/bl70x/bl61x/bl808,
-  - Infineon: 062s2, 062s3-4343w, 062s4, 062-wifi-bt, 062-ble
-  - nuvoton: numaker-iot-m467, numaker-m467hj, numaker-hmi-ma35d1
-  - nxp: LPC55S16, LPC55S36, LPC55S06, LPC5528, LPC55S28
-  - nrf5xxx: nrf5340
-  - gd32: gd32470z-lckfb, GD32303C-START
-  - apm32: apm32f030r8-miniboard, apm32f051r8-evalboard, apm32f091vc-miniboard, apm32f103vb-miniboard, apm32f107vc-evalboard, apm32f407zg-evalboard,apm32f072vb-miniboard
-  - n32: n32g43xcl-stb, n32g457qel-stb, n32g45xcl-stb, n32g45xml-stb, n32g45xrl-stb, n32g45xvl-stb, n32140xcl-stb, n321436_evb, n32143xml-stb, n32143xrl-stb, n32wb45xl-evb, n32g4frml-stb.
-  - mm32: mm32f3270-100ask-pitaya
-  - at32: at32f421-start, at32f425-start
-  - stm32: stm32f723-st-disco
-  - phytium: aarch32, aarch64
-  - other: core-v-cv32e40p, air32f103, YS-F1Pro, etc.
-- Update some stm32 BSP drivers: timer, pwm, uart v2, can, etc.
-- Update BSP:
-  - qemu-vexpress-a9: play the version number of QEMU when QEMU running.
-  - tms320f28379d: fix the startup problem, implement PWM driver.
-  - simulator: fix simulator compilation warnings, fix compile error.
-  - raspberry-pico: add SMP
-  - synopsys: Fix timer call-backs, Fix print syntax, Fix GNU toolchain RTT_CC alias, Use RTT_EXEC_PATH for the toolchain location substitution.
-  - ti/c28x: add support to not disable global interrupt in context-switch to enable zero-latency isr for critical interrupts, add GPIO & pwm & ADC driver, update rt_vsnprintf for compliance with ti c28x cpus,add support to scons-based .project creation.
-  - stm32: update all bsp projects.
-  - renesas: add segger rtt function, add tft-lcd lvgl support, add ra6m4-cpk lvgl for spi-lcd support and update rt_spi_bus_attach_device_cspin function, add tft-lcd pin connection description, and fix some bugs, etc.
-  - Infineon: add capsense support, add Infineon Doc and modify file structure, update spi driver, add slider driver demo, fix spi cs problem, etc.
-  - nuvoton: modify RT_WEAK as rt_weak, fix building issue of Nuvoton porting, etc.
-  - nxp: imxrt1170 Fix usb, Fix flexcan driver, add sdio support. lpc55s69 update PWM. lpc55sxx i2c driver fix & repair, add i2s and wm8904 driver, update spi and pwm driver. etc.
-  - nrf5xxx: add spi twi drv for nrf5340, fix the Kconfig of nrf52832, etc.
-  - gd32: fix bug on spi driver
-  - apm32: fix apm32f0/apm32f1 gcc startup assembly file bug and fix apm32 drv_eth.c bug, add apm32F0 series MCU support, add apm32 rtt sdio/flash/sdram driver. etc.
-  - at32: fixed gcc compiling usb driver errors, update for including file position and adding macros, optimize emac and usart driver code, add support usb driver. etc.
-  - esp32: ESP32_C3 fix compile errors/warnings, igrate to ESP-IDF package, add I2C drivers. ESP32 support applying patch to local IDF. etc.
-  - ch32: add rt_hw_context_switch_interrupt. ch32v307 add uart/spi/adc/gpio/wdt/dac/can/pwm drivers, update readme. etc.
-
-## Libcpu
-- arm: cortex-a revert safety MMU initialization, cortex-m7 change the return type of function rt_hw_cpu_dcache_ops to rt_uint32_t, etc.
-- risc-v: support noncached normal memory, add rt_backtrace function, etc.
-- aarch64: add rt_backtrace function, stop when no page is free.
-
-## Tools
-- Improved ci function
-- Add some scons cmds: scons --exec-path=xxx, scons --exec-prefix=, scons --dist --target=xxx, scons --strict, scons --dist --project-path=xxxx, etc.
-
 # RT-Thread v4.1.1 released
 
 Change log since v4.1.0 released

README.md

@@ -82,7 +82,7 @@ RT-Thread supports many architectures, and has covered the major architectures i
 - **ARM9**：manufacturers like Allwinner、Xilinx 、GOKE
 - **ARM11**：manufacturers like Fullhan
 - **MIPS32**：manufacturers like loongson、Ingenic
-- **RISC-V RV32E/RV32I[F]/RV64[D]**：manufacturers like sifive、[Canaan Kendryte](https://github.com/RT-Thread/rt-thread/tree/master/bsp/k210)、[bouffalo_lab](https://github.com/RT-Thread/rt-thread/tree/master/bsp/bouffalo_lab)、[Nuclei](https://nucleisys.com/)、[T-Head](https://www.t-head.cn/)、[HPMicro](https://github.com/RT-Thread/rt-thread/tree/master/bsp/hpmicro)
+- **RISC-V**：manufacturers like Hifive、Kendryte、Nuclei
 - **ARC**：manufacturers like SYNOPSYS
 - **DSP**：manufacturers like TI
 - **C-Sky**
@@ -107,7 +107,7 @@ RT-Thread Studio IDE (a.k.a. RT-Studio) is a one-stop intergrated development en
 
 ## Env Tool
 
-[User Manual](documentation/env/env.md) | [Tutorial Videos](https://www.youtube.com/watch?v=dEK94o_YoSo)
+[User Manual](documentation/env/env/) | [Tutorial Videos](https://www.youtube.com/watch?v=dEK94o_YoSo)
 
 In the early stage, RT-Thread team also created an auxiliary tool called Env. It is an auxiliary tool with a TUI (Text-based user interface). Developers can use Env tool to configure and generate the GCC, Keil MDK, and IAR projects.
 

README_de.md

@@ -82,7 +82,7 @@ RT-Thread unterstützt viele Architekturen und hat die wichtigsten Architekturen
 - **ARM9**：manufacturers like Allwinner、Xilinx 、GOKE
 - **ARM11**：manufacturers like Fullhan
 - **MIPS32**：manufacturers like loongson、Ingenic
-- **RISC-V RV32E/RV32I[F]/RV64[D]**：manufacturers like Hifive、[Kendryte](https://github.com/RT-Thread/rt-thread/tree/master/bsp/k210)、[bouffalo_lab](https://github.com/RT-Thread/rt-thread/tree/master/bsp/bouffalo_lab)、[Nuclei](https://nucleisys.com/)、[T-Head](https://www.t-head.cn/)、[HPMicro](https://github.com/RT-Thread/rt-thread/tree/master/bsp/hpmicro)
+- **RISC-V**：manufacturers like Hifive、Kendryte、Nuclei
 - **ARC**：manufacturers like SYNOPSYS
 - **DSP**：manufacturers like TI
 - **C-Sky**
@@ -107,7 +107,7 @@ RT-Thread Studio IDE (auch bekannt als RT-Studio) ist eine integrierte Entwicklu
 
 ## Env-Werkzeug
 
-[User Manual](documentation/env/env.md) | [Tutorial Videos](https://www.youtube.com/watch?v=dEK94o_YoSo)
+[User Manual](documentation/env/env/) | [Tutorial Videos](https://www.youtube.com/watch?v=dEK94o_YoSo)
 
 In der Anfangsphase schuf das RT-Thread-Team auch ein Hilfswerkzeug namens Env. Dabei handelt es sich um ein Hilfstool mit einer TUI (textbasierten Benutzeroberfläche). Entwickler können das Env-Tool verwenden, um GCC, Keil MDK und IAR-Projekte zu konfigurieren und zu generieren.
 
@@ -145,3 +145,4 @@ RT-Thread ist sehr dankbar für die Unterstützung durch alle Entwickler der Com
 # Beitrag
 
 Wenn Sie an RT-Thread interessiert sind und sich an der Entwicklung von RT-Thread beteiligen und einen Beitrag zum Code leisten wollen, lesen Sie bitte den [Code Contribution Guide](documentation/contribution_guide/contribution_guide.md).
+

README_es.md

@@ -82,7 +82,7 @@ RT-Thread es compatible con muchas arquitecturas, y ha cubierto las principales
 - **ARM9**：manufacturers like Allwinner、Xilinx 、GOKE
 - **ARM11**：manufacturers like Fullhan
 - **MIPS32**：manufacturers like loongson、Ingenic
-- **RISC-V RV32E/RV32I[F]/RV64[D]**：manufacturers like Hifive、[Kendryte](https://github.com/RT-Thread/rt-thread/tree/master/bsp/k210)、[bouffalo_lab](https://github.com/RT-Thread/rt-thread/tree/master/bsp/bouffalo_lab)、[Nuclei](https://nucleisys.com/)、[T-Head](https://www.t-head.cn/)、[HPMicro](https://github.com/RT-Thread/rt-thread/tree/master/bsp/hpmicro)
+- **RISC-V**：manufacturers like Hifive、Kendryte、Nuclei
 - **ARC**：manufacturers like SYNOPSYS
 - **DSP**：manufacturers like TI
 - **C-Sky**
@@ -107,7 +107,7 @@ RT-Thread Studio IDE (también conocido como RT-Studio) es un entorno de desarro
 
 ## Herramienta Env
 
-[User Manual](documentation/env/env.md) | [Tutorial Videos](https://www.youtube.com/watch?v=dEK94o_YoSo)
+[User Manual](documentation/env/env/) | [Tutorial Videos](https://www.youtube.com/watch?v=dEK94o_YoSo)
 
 En la etapa inicial, el equipo de RT-Thread también creó una herramienta auxiliar llamada Env. Es una herramienta auxiliar con una TUI (interfaz de usuario basada en texto). Los desarrolladores pueden utilizar la herramienta Env para configurar y generar los proyectos GCC, Keil MDK e IAR.
 
@@ -144,3 +144,4 @@ RT-Thread está muy agradecido por el apoyo de todos los desarrolladores de la c
 # Contribución
 
 Si estás interesado en RT-Thread y quieres unirte al desarrollo de RT-Thread y convertirte en un contribuidor de código, por favor consulta la [Guía de Contribución de Código.](documentation/contribution_guide/contribution_guide.md).
+

README_zh.md

@@ -70,7 +70,7 @@ RT-Thread源代码目录结构如下图所示：
 
 Env 是RT-Thread推出的开发辅助工具，针对基于RT-Thread操作系统的项目工程，提供编译构建环境、图形化系统配置及软件包管理功能。其内置的 menuconfig 提供了简单易用的配置剪裁工具，可对内核、组件和软件包进行自由裁剪，使系统以搭积木的方式进行构建。
 
-[下载 Env 工具](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
+[下载 Env 工具](https://www.rt-thread.org/page/download.html)
 
 [Env 用户手册](https://www.rt-thread.org/document/site/#/development-tools/env/env)
 
@@ -93,7 +93,7 @@ RT-Thread RTOS 支持许多架构，并且已经涵盖了当前应用中的主
 - ARM9：如芯片制造商Allwinner、Xilinx 、GOKE
 - ARM11：如芯片制造商Fullhan
 - MIPS32：如芯片制造商loongson、Ingenic
-- RISC-V RV32E/RV32I[F]/RV64[D]：如芯片制造商sifive、[嘉楠Kendryte](https://github.com/RT-Thread/rt-thread/tree/master/bsp/k210)、[博流](https://github.com/RT-Thread/rt-thread/tree/master/bsp/bouffalo_lab)、[芯来Nuclei](https://nucleisys.com/)、[平头哥T-Head](https://www.t-head.cn/)、[先楫](https://github.com/RT-Thread/rt-thread/tree/master/bsp/hpmicro)
+- RISC-V：如芯片制造商Hifive、Kendryte、[芯来Nuclei](https://nucleisys.com/)
 - ARC：如芯片制造商SYNOPSYS
 - DSP：如芯片制造商 TI
 - C-Sky
@@ -131,9 +131,9 @@ RT-Thread BSP可以直接编译并下载到相应的开发板使用。此外，R
 
 ## 文档
 
-[文档中心](https://www.rt-thread.org/document/site/ ) | [编程指南](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/basic/basic )
+[文档中心](https://www.rt-thread.org/document/site/ ) | [编程指南](https://www.rt-thread.org/document/site/programming-manual/basic/basic/ )
 
-[应用 RT-Thread 实现蜂鸣器播放器教程](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/beep-player/README?id=%e5%ba%94%e7%94%a8-rt-thread-%e5%ae%9e%e7%8e%b0%e8%9c%82%e9%b8%a3%e5%99%a8%e6%92%ad%e6%94%be%e5%99%a8) | [分布式温度监控系统教程](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/temperature-system/README?id=%e5%88%86%e5%b8%83%e5%bc%8f%e6%b8%a9%e5%ba%a6%e7%9b%91%e6%8e%a7%e7%b3%bb%e7%bb%9f ) | [智能车连载教程](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/smart-car/README?id=%e6%99%ba%e8%83%bd%e8%bd%a6%e8%bf%9e%e8%bd%bd%e6%95%99%e7%a8%8b%e7%ae%80%e4%bb%8b )
+[应用 RT-Thread 实现蜂鸣器播放器教程](https://www.rt-thread.org/document/site/tutorial/beep-player/) | [分布式温度监控系统教程](https://www.rt-thread.org/document/site/tutorial/temperature-system/ ) | [智能车连载教程](https://www.rt-thread.org/document/site/tutorial/smart-car/ )
 
 ## 例程
 
@@ -174,7 +174,7 @@ RT-Thread微信公众号：
 
 # 贡献代码
 
-如果您对RT-Thread感兴趣，并希望参与RT-Thread的开发并成为代码贡献者，请参阅[代码贡献指南](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github)。
+如果您对RT-Thread感兴趣，并希望参与RT-Thread的开发并成为代码贡献者，请参阅[代码贡献指南](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/githubd)。
 
 ## 感谢以下小伙伴对本仓库的贡献！
 

bsp/CME_M7/.config

@@ -8,7 +8,6 @@
 #
 CONFIG_RT_NAME_MAX=8
 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set
-# CONFIG_RT_USING_SMART is not set
 # CONFIG_RT_USING_SMP is not set
 CONFIG_RT_ALIGN_SIZE=8
 # CONFIG_RT_THREAD_PRIORITY_8 is not set
@@ -59,7 +58,6 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
 #
 # Memory Management
 #
-CONFIG_RT_PAGE_MAX_ORDER=11
 CONFIG_RT_USING_MEMPOOL=y
 CONFIG_RT_USING_SMALL_MEM=y
 # CONFIG_RT_USING_SLAB is not set
@@ -78,21 +76,16 @@ CONFIG_RT_USING_HEAP=y
 #
 CONFIG_RT_USING_DEVICE=y
 # CONFIG_RT_USING_DEVICE_OPS is not set
-# CONFIG_RT_USING_DM is not set
 # CONFIG_RT_USING_INTERRUPT_INFO is not set
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart2"
-CONFIG_RT_VER_NUM=0x50000
-# CONFIG_RT_USING_STDC_ATOMIC is not set
-# CONFIG_RT_USING_CACHE is not set
-CONFIG_RT_USING_HW_ATOMIC=y
-# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
-# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
-CONFIG_RT_USING_CPU_FFS=y
+CONFIG_RT_VER_NUM=0x40101
 CONFIG_ARCH_ARM=y
+CONFIG_RT_USING_CPU_FFS=y
 CONFIG_ARCH_ARM_CORTEX_M=y
 CONFIG_ARCH_ARM_CORTEX_M3=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 
 #
 # RT-Thread Components
@@ -147,17 +140,15 @@ CONFIG_RT_DFS_ELM_REENTRANT=y
 CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
 # CONFIG_RT_USING_DFS_DEVFS is not set
 # CONFIG_RT_USING_DFS_ROMFS is not set
-# CONFIG_RT_USING_DFS_CROMFS is not set
 # CONFIG_RT_USING_DFS_RAMFS is not set
-# CONFIG_RT_USING_DFS_TMPFS is not set
 # CONFIG_RT_USING_DFS_NFS is not set
 # CONFIG_RT_USING_FAL is not set
+# CONFIG_RT_USING_LWP is not set
 
 #
 # Device Drivers
 #
 CONFIG_RT_USING_DEVICE_IPC=y
-CONFIG_RT_UNAMED_PIPE_NUMBER=64
 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
 CONFIG_RT_USING_SERIAL=y
 CONFIG_RT_USING_SERIAL_V1=y
@@ -172,14 +163,10 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_DAC is not set
-# CONFIG_RT_USING_NULL is not set
-# CONFIG_RT_USING_ZERO is not set
-# CONFIG_RT_USING_RANDOM is not set
 # CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_PM is not set
-# CONFIG_RT_USING_FDT is not set
 # CONFIG_RT_USING_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
 # CONFIG_RT_USING_SPI is not set
@@ -187,13 +174,10 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_AUDIO is not set
 # CONFIG_RT_USING_SENSOR is not set
 # CONFIG_RT_USING_TOUCH is not set
-# CONFIG_RT_USING_LCD is not set
 # CONFIG_RT_USING_HWCRYPTO is not set
 # CONFIG_RT_USING_PULSE_ENCODER is not set
 # CONFIG_RT_USING_INPUT_CAPTURE is not set
-# CONFIG_RT_USING_DEV_BUS is not set
 # CONFIG_RT_USING_WIFI is not set
-# CONFIG_RT_USING_VIRTIO is not set
 
 #
 # Using USB
@@ -302,7 +286,6 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_RT_USING_ULOG is not set
 # CONFIG_RT_USING_UTEST is not set
 # CONFIG_RT_USING_VAR_EXPORT is not set
-# CONFIG_RT_USING_ADT is not set
 # CONFIG_RT_USING_RT_LINK is not set
 # CONFIG_RT_USING_VBUS is not set
 
@@ -397,8 +380,6 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_AGILE_FTP is not set
 # CONFIG_PKG_USING_EMBEDDEDPROTO is not set
 # CONFIG_PKG_USING_RT_LINK_HW is not set
-# CONFIG_PKG_USING_RYANMQTT is not set
-# CONFIG_PKG_USING_RYANW5500 is not set
 # CONFIG_PKG_USING_LORA_PKT_FWD is not set
 # CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
 # CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
@@ -406,8 +387,6 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_SMALL_MODBUS is not set
 # CONFIG_PKG_USING_NET_SERVER is not set
 # CONFIG_PKG_USING_ZFTP is not set
-# CONFIG_PKG_USING_WOL is not set
-# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
 
 #
 # security packages
@@ -476,12 +455,17 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_MP3PLAYER is not set
 # CONFIG_PKG_USING_TINYJPEG is not set
 # CONFIG_PKG_USING_UGUI is not set
+
+#
+# PainterEngine: A cross-platform graphics application framework written in C language
+#
+# CONFIG_PKG_USING_PAINTERENGINE is not set
+# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
 # CONFIG_PKG_USING_MCURSES is not set
 # CONFIG_PKG_USING_TERMBOX is not set
 # CONFIG_PKG_USING_VT100 is not set
 # CONFIG_PKG_USING_QRCODE is not set
 # CONFIG_PKG_USING_GUIENGINE is not set
-# CONFIG_PKG_USING_3GPP_AMRNB is not set
 
 #
 # tools packages
@@ -491,9 +475,9 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_EASYLOGGER is not set
 # CONFIG_PKG_USING_SYSTEMVIEW is not set
 # CONFIG_PKG_USING_SEGGER_RTT is not set
-# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
 # CONFIG_PKG_USING_RDB is not set
 # CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
 # CONFIG_PKG_USING_LOGMGR is not set
 # CONFIG_PKG_USING_ADBD is not set
 # CONFIG_PKG_USING_COREMARK is not set
@@ -527,8 +511,8 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_CBOX is not set
 # CONFIG_PKG_USING_SNOWFLAKE is not set
 # CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
 # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
-# CONFIG_PKG_USING_VOFA_PLUS is not set
 
 #
 # system packages
@@ -564,6 +548,7 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_UC_CLK is not set
 # CONFIG_PKG_USING_UC_COMMON is not set
 # CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_RTDUINO is not set
 # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
 # CONFIG_PKG_USING_CAIRO is not set
 # CONFIG_PKG_USING_PIXMAN is not set
@@ -598,95 +583,19 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_KMULTI_RTIMER is not set
 # CONFIG_PKG_USING_TFDB is not set
 # CONFIG_PKG_USING_QPC is not set
-# CONFIG_PKG_USING_AGILE_UPGRADE is not set
-# CONFIG_PKG_USING_FLASH_BLOB is not set
 
 #
 # peripheral libraries and drivers
 #
-
-#
-# sensors drivers
-#
-# CONFIG_PKG_USING_LSM6DSM is not set
-# CONFIG_PKG_USING_LSM6DSL is not set
-# CONFIG_PKG_USING_LPS22HB is not set
-# CONFIG_PKG_USING_HTS221 is not set
-# CONFIG_PKG_USING_LSM303AGR is not set
-# CONFIG_PKG_USING_BME280 is not set
-# CONFIG_PKG_USING_BME680 is not set
-# CONFIG_PKG_USING_BMA400 is not set
-# CONFIG_PKG_USING_BMI160_BMX160 is not set
-# CONFIG_PKG_USING_SPL0601 is not set
-# CONFIG_PKG_USING_MS5805 is not set
-# CONFIG_PKG_USING_DA270 is not set
-# CONFIG_PKG_USING_DF220 is not set
-# CONFIG_PKG_USING_HSHCAL001 is not set
-# CONFIG_PKG_USING_BH1750 is not set
-# CONFIG_PKG_USING_MPU6XXX is not set
-# CONFIG_PKG_USING_AHT10 is not set
-# CONFIG_PKG_USING_AP3216C is not set
-# CONFIG_PKG_USING_TSL4531 is not set
-# CONFIG_PKG_USING_DS18B20 is not set
-# CONFIG_PKG_USING_DHT11 is not set
-# CONFIG_PKG_USING_DHTXX is not set
-# CONFIG_PKG_USING_GY271 is not set
-# CONFIG_PKG_USING_GP2Y10 is not set
-# CONFIG_PKG_USING_SGP30 is not set
-# CONFIG_PKG_USING_HDC1000 is not set
-# CONFIG_PKG_USING_BMP180 is not set
-# CONFIG_PKG_USING_BMP280 is not set
-# CONFIG_PKG_USING_SHTC1 is not set
-# CONFIG_PKG_USING_BMI088 is not set
-# CONFIG_PKG_USING_HMC5883 is not set
-# CONFIG_PKG_USING_MAX6675 is not set
-# CONFIG_PKG_USING_TMP1075 is not set
-# CONFIG_PKG_USING_SR04 is not set
-# CONFIG_PKG_USING_CCS811 is not set
-# CONFIG_PKG_USING_PMSXX is not set
-# CONFIG_PKG_USING_RT3020 is not set
-# CONFIG_PKG_USING_MLX90632 is not set
-# CONFIG_PKG_USING_MLX90393 is not set
-# CONFIG_PKG_USING_MLX90392 is not set
-# CONFIG_PKG_USING_MLX90397 is not set
-# CONFIG_PKG_USING_MS5611 is not set
-# CONFIG_PKG_USING_MAX31865 is not set
-# CONFIG_PKG_USING_VL53L0X is not set
-# CONFIG_PKG_USING_INA260 is not set
-# CONFIG_PKG_USING_MAX30102 is not set
-# CONFIG_PKG_USING_INA226 is not set
-# CONFIG_PKG_USING_LIS2DH12 is not set
-# CONFIG_PKG_USING_HS300X is not set
-# CONFIG_PKG_USING_ZMOD4410 is not set
-# CONFIG_PKG_USING_ISL29035 is not set
-# CONFIG_PKG_USING_MMC3680KJ is not set
-# CONFIG_PKG_USING_QMP6989 is not set
-# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
 # CONFIG_PKG_USING_SHT2X is not set
 # CONFIG_PKG_USING_SHT3X is not set
-# CONFIG_PKG_USING_AD7746 is not set
 # CONFIG_PKG_USING_ADT74XX is not set
-# CONFIG_PKG_USING_MAX17048 is not set
 # CONFIG_PKG_USING_AS7341 is not set
-# CONFIG_PKG_USING_CW2015 is not set
-# CONFIG_PKG_USING_ICM20608 is not set
-# CONFIG_PKG_USING_PAJ7620 is not set
-# CONFIG_PKG_USING_STHS34PF80 is not set
-
-#
-# touch drivers
-#
-# CONFIG_PKG_USING_GT9147 is not set
-# CONFIG_PKG_USING_GT1151 is not set
-# CONFIG_PKG_USING_GT917S is not set
-# CONFIG_PKG_USING_GT911 is not set
-# CONFIG_PKG_USING_FT6206 is not set
-# CONFIG_PKG_USING_FT5426 is not set
-# CONFIG_PKG_USING_FT6236 is not set
-# CONFIG_PKG_USING_XPT2046_TOUCH is not set
-# CONFIG_PKG_USING_REALTEK_AMEBA is not set
 # CONFIG_PKG_USING_STM32_SDIO is not set
 # CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_ICM20608 is not set
 # CONFIG_PKG_USING_BUTTON is not set
 # CONFIG_PKG_USING_PCF8574 is not set
 # CONFIG_PKG_USING_SX12XX is not set
@@ -709,10 +618,12 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_AGILE_LED is not set
 # CONFIG_PKG_USING_AT24CXX is not set
 # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
 # CONFIG_PKG_USING_PCA9685 is not set
-# CONFIG_PKG_USING_ILI9341 is not set
 # CONFIG_PKG_USING_I2C_TOOLS is not set
 # CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
 # CONFIG_PKG_USING_RPLIDAR is not set
 # CONFIG_PKG_USING_AS608 is not set
 # CONFIG_PKG_USING_RC522 is not set
@@ -727,6 +638,7 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_CAN_YMODEM is not set
 # CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
 # CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
 # CONFIG_PKG_USING_AGILE_CONSOLE is not set
 # CONFIG_PKG_USING_LD3320 is not set
 # CONFIG_PKG_USING_WK2124 is not set
@@ -757,11 +669,10 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_BL_MCU_SDK is not set
 # CONFIG_PKG_USING_SOFT_SERIAL is not set
 # CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_CW2015 is not set
 # CONFIG_PKG_USING_RFM300 is not set
 # CONFIG_PKG_USING_IO_INPUT_FILTER is not set
 # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
-# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
-# CONFIG_PKG_USING_FINGERPRINT is not set
 
 #
 # AI packages
@@ -776,12 +687,6 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_QUEST is not set
 # CONFIG_PKG_USING_NAXOS is not set
 
-#
-# Signal Processing and Control Algorithm Packages
-#
-# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
-# CONFIG_PKG_USING_UKAL is not set
-
 #
 # miscellaneous packages
 #
@@ -811,7 +716,6 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_TETRIS is not set
 # CONFIG_PKG_USING_DONUT is not set
 # CONFIG_PKG_USING_COWSAY is not set
-# CONFIG_PKG_USING_MORSE is not set
 # CONFIG_PKG_USING_LIBCSV is not set
 # CONFIG_PKG_USING_OPTPARSE is not set
 # CONFIG_PKG_USING_FASTLZ is not set
@@ -834,6 +738,7 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_VI is not set
 # CONFIG_PKG_USING_KI is not set
 # CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_UKAL is not set
 # CONFIG_PKG_USING_CRCLIB is not set
 # CONFIG_PKG_USING_LWGPS is not set
 # CONFIG_PKG_USING_STATE_MACHINE is not set
@@ -844,218 +749,63 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_SLCAN2RTT is not set
 # CONFIG_PKG_USING_SOEM is not set
 # CONFIG_PKG_USING_QPARAM is not set
-# CONFIG_PKG_USING_CorevMCU_CLI is not set
 
 #
-# Arduino libraries
+# Privated Packages of RealThread
 #
-# CONFIG_PKG_USING_RTDUINO is not set
+# CONFIG_PKG_USING_CODEC is not set
+# CONFIG_PKG_USING_PLAYER is not set
+# CONFIG_PKG_USING_MPLAYER is not set
+# CONFIG_PKG_USING_PERSIMMON_SRC is not set
+# CONFIG_PKG_USING_JS_PERSIMMON is not set
+# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
 
 #
-# Projects
+# Network Utilities
 #
-# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
-# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
-# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+# CONFIG_PKG_USING_MDNS is not set
+# CONFIG_PKG_USING_UPNP is not set
+# CONFIG_PKG_USING_WICED is not set
+# CONFIG_PKG_USING_CLOUDSDK is not set
+# CONFIG_PKG_USING_POWER_MANAGER is not set
+# CONFIG_PKG_USING_RT_OTA is not set
+# CONFIG_PKG_USING_RTINSIGHT is not set
+# CONFIG_PKG_USING_SMARTCONFIG is not set
+# CONFIG_PKG_USING_RTX is not set
+# CONFIG_RT_USING_TESTCASE is not set
+# CONFIG_PKG_USING_NGHTTP2 is not set
+# CONFIG_PKG_USING_AVS is not set
+# CONFIG_PKG_USING_ALI_LINKKIT is not set
+# CONFIG_PKG_USING_STS is not set
+# CONFIG_PKG_USING_DLMS is not set
+# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set
+# CONFIG_PKG_USING_ZBAR is not set
+# CONFIG_PKG_USING_MCF is not set
+# CONFIG_PKG_USING_URPC is not set
+# CONFIG_PKG_USING_DCM is not set
+# CONFIG_PKG_USING_EMQ is not set
+# CONFIG_PKG_USING_CFGM is not set
+# CONFIG_PKG_USING_RT_CMSIS_DAP is not set
+# CONFIG_PKG_USING_SMODULE is not set
+# CONFIG_PKG_USING_SNFD is not set
+# CONFIG_PKG_USING_UDBD is not set
+# CONFIG_PKG_USING_BENCHMARK is not set
+# CONFIG_PKG_USING_UBJSON is not set
+# CONFIG_PKG_USING_DATATYPE is not set
+# CONFIG_PKG_USING_FASTFS is not set
+# CONFIG_PKG_USING_RIL is not set
+# CONFIG_PKG_USING_WATCH_DCM_SVC is not set
+# CONFIG_PKG_USING_WATCH_APP_FWK is not set
+# CONFIG_PKG_USING_GUI_TEST is not set
+# CONFIG_PKG_USING_PMEM is not set
+# CONFIG_PKG_USING_LWRDP is not set
+# CONFIG_PKG_USING_MASAN is not set
+# CONFIG_PKG_USING_BSDIFF_LIB is not set
+# CONFIG_PKG_USING_PRC_DIFF is not set
 
 #
-# Sensors
-#
-# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
-# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
-# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
-# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
-# CONFIG_PKG_USING_SEEED_ITG3200 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
-# CONFIG_PKG_USING_SEEED_MP503 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
-
-#
-# Display
-#
-# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
-# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
-# CONFIG_PKG_USING_SEEED_TM1637 is not set
-
-#
-# Timing
-#
-# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
-
-#
-# Data Processing
-#
-# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
-# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
-
-#
-# Data Storage
-#
-
-#
-# Communication
-#
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
-
-#
-# Device Control
-#
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
-
-#
-# Other
-#
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
-# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
-
-#
-# Signal IO
-#
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
-
-#
-# Uncategorized
+# RT-Thread Smart
 #
+# CONFIG_PKG_USING_UKERNEL is not set
+# CONFIG_PKG_USING_TRACE_AGENT is not set
 CONFIG_SOC_CME_M7=y

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_adc.h

@@ -1,29 +1,29 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_adc.h
-    *
-    * @brief    CMEM7 ADC header file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_adc.h
+	*
+	* @brief    CMEM7 ADC header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #ifndef __CMEM7_ADC_H
 #define __CMEM7_ADC_H
 
@@ -38,8 +38,8 @@
   * @{
   */
 typedef enum {
-    ADC_PERIPH_1,
-    ADC_PERIPH_2,
+	ADC_PERIPH_1,
+	ADC_PERIPH_2,
 } ADC_PERIPH;
 
 #define IS_ADC_ALL_PERIPH(PERIPH)         (((PERIPH) == ADC_PERIPH_1) || \
@@ -67,7 +67,7 @@ typedef enum {
 /** @defgroup ADC_PHASE_CTRL
   * @{
   */
-#define ADC_PHASE_CTRL_0DEG_RISE_EDGE     0         /* ADC-1 and ADC-2 CLK are 0DEG Phase Difference(Rising Edge) */
+#define ADC_PHASE_CTRL_0DEG_RISE_EDGE     0         /* ADC-1 and ADC-2 CLK are 0DEG Phase Difference(Rising Edge) */                                               
 #define ADC_PHASE_CTRL_90DEG_AHEAD        1         /* ADC-1 90DEG ahead of ADC-2 */
 #define ADC_PHASE_CTRL_90DEG_LAG          2         /* ADC-1 90DEG lag of ADC-2 */
 #define ADC_PHASE_CTRL_0DEG_FALL_EDGE     3         /* ADC-1 and ADC-2 CLK are 0DEG Phase Difference(falling Edge) */
@@ -84,11 +84,11 @@ typedef enum {
   * @{
   */
 #define ADC_SYSTEM_MODE_SINGLE_CONV       1
-#define ADC_SYSTEM_MODE_CONTINUOUS_CONV   2
+#define ADC_SYSTEM_MODE_CONTINUOUS_CONV   2	
 
 #define IS_ADC_CONVERSION(CONV)           (((CONV) == ADC_SYSTEM_MODE_SINGLE_CONV) || \
                                            ((CONV) == ADC_SYSTEM_MODE_CONTINUOUS_CONV))
-
+																					 
 /**
   * @}
   */
@@ -119,7 +119,7 @@ typedef enum {
 /** @defgroup ADC1_CHANNEL
   * @{
   */
-#define ADC1_CHANNEL_VIP                  0x1
+#define ADC1_CHANNEL_VIP                  0x1		
 #define ADC1_CHANNEL_VSEN                 0x2
 #define ADC1_CHANNEL_VADIO_0              0x4
 #define ADC1_CHANNEL_VADIO_1              0x8
@@ -136,8 +136,8 @@ typedef enum {
 
 /** @defgroup ADC2_CHANNEL
   * @{
-  */
-#define ADC2_CHANNEL_VIN                  0x1
+  */																																										 
+#define ADC2_CHANNEL_VIN                  0x1		
 #define ADC2_CHANNEL_VTMP                 0x2
 #define ADC2_CHANNEL_VADIO_6              0x4
 #define ADC2_CHANNEL_VADIO_7              0x8
@@ -147,118 +147,118 @@ typedef enum {
 #define ADC2_CHANNEL_VADIO_11             0x80
 #define ADC2_CHANNEL_ALL                  0xFF
 
-#define IS_ADC2_CHANNEL(CHANNEL)          (((CHANNEL) != 0) && ((CHANNEL) & ~ADC2_CHANNEL_ALL) == 0)
+#define IS_ADC2_CHANNEL(CHANNEL)          (((CHANNEL) != 0) && ((CHANNEL) & ~ADC2_CHANNEL_ALL) == 0)                                          																 
 /**
   * @}
   */
 
 /** @defgroup ADC_INT
   * @{
-  */
-#define ADC1_INT_ALMOST_FULL              0x1
+  */																					 
+#define ADC1_INT_ALMOST_FULL              0x1 
 #define ADC2_INT_ALMOST_FULL              0x8
-#define ADC_INT_ALL                                 0x9
+#define ADC_INT_ALL              					0x9
 
-#define IS_ADC_INT(INT)                             (((INT) != 0) && (((INT) & ~ADC_INT_ALL) == 0))
+#define IS_ADC_INT(INT)        						(((INT) != 0) && (((INT) & ~ADC_INT_ALL) == 0))
 /**
   * @}
   */
 
 /**
   * @brief  ADC collection data structure
-    */
+	*/ 
 typedef struct {
-    uint8_t channel;                                                /*!< The channel of collected data, is a value of
-                                                                                             @ref ADC_CHANNEL, @ref ADC1_CHANNEL or @ref ADC2_CHANNEL */
-    uint16_t data;                                                  /*!< collected data                                                                 */
+	uint8_t channel;												/*!< The channel of collected data, is a value of 
+																							 @ref ADC_CHANNEL, @ref ADC1_CHANNEL or @ref ADC2_CHANNEL */
+	uint16_t data;													/*!< collected data                    												*/
 } ADC_Data;
 
 /**
   * @brief  ADC initialization structure
-    */
+	*/ 
 typedef struct
 {
-    uint8_t ADC_PhaseCtrl;                  /*!< Phase between ADC1 and ADC2, is a value of @ref ADC_PHASE_CTRL */
-    uint8_t ADC_VsenSelection;              /*!< ADC1 VSEN selection, is a value of @ref ADC_VSEN                   */
+	uint8_t ADC_PhaseCtrl;                  /*!< Phase between ADC1 and ADC2, is a value of @ref ADC_PHASE_CTRL */
+	uint8_t ADC_VsenSelection;              /*!< ADC1 VSEN selection, is a value of @ref ADC_VSEN					*/
 } ADC_InitTypeDef;
 
 /**
   * @brief  ADC initialization
   * @note   This function should be called at first before any other interfaces.
-    * @param[in] init A pointer to structure ADC_InitTypeDef
+	* @param[in] init A pointer to structure ADC_InitTypeDef
   * @retval None
-    */
+	*/ 
 void ADC_Init(ADC_InitTypeDef* init);
 
 /**
-  * @brief  Enable or disable ADC.
-    * @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
-    * @param[in] Enable The bit indicates if the specific ADC is enable or not
+  * @brief  Enable or disable ADC. 
+	* @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
+	* @param[in] Enable The bit indicates if the specific ADC is enable or not
   * @retval None
-    */
+	*/ 
 void ADC_Enable(uint8_t adc, BOOL enable);
 
 /**
-  * @brief  Enable or disable ADC interrupt.
-    * @param[in] Int interrupt mask bits, which can be a combination of @ref ADC_INT
-    * @param[in] Enable The bit indicates if specific interrupts are enable or not
+  * @brief  Enable or disable ADC interrupt. 
+	* @param[in] Int interrupt mask bits, which can be a combination of @ref ADC_INT
+	* @param[in] Enable The bit indicates if specific interrupts are enable or not
   * @retval None
-    */
+	*/ 
 void ADC_EnableInt(uint32_t Int, BOOL enable);
 
 /**
-  * @brief  Check specific interrupts are set or not
-    * @param[in] Int interrupt mask bits, which can be a combination of @ref ADC_INT
-    * @retval BOOL The bit indicates if the specific interrupts are set or not
-    */
+  * @brief  Check specific interrupts are set or not 
+	* @param[in] Int interrupt mask bits, which can be a combination of @ref ADC_INT
+	* @retval BOOL The bit indicates if the specific interrupts are set or not
+	*/
 BOOL ADC_GetIntStatus(uint32_t Int);
 
 /**
   * @brief  Clear specific interrupts
-    * @param[in] Int interrupt mask bits, which can be a value of @ref ADC_INT
+	* @param[in] Int interrupt mask bits, which can be a value of @ref ADC_INT
   * @retval None
-    */
+	*/
 void ADC_ClearInt(uint32_t Int);
 
 /**
-  * @brief  ADC starts to convert data
-    * @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
-    * @param[in] convMode It should be a value of @ref ADC_CONVERSION
-    * @param[in] channel It should be the value of @ref ADC1_CHANNEL
-    *                    or @ref ADC2_CHANNEL according to parameter 'adc'
+  * @brief  ADC starts to convert data 
+	* @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
+	* @param[in] convMode It should be a value of @ref ADC_CONVERSION
+	* @param[in] channel It should be the value of @ref ADC1_CHANNEL 
+	* 					 or @ref ADC2_CHANNEL according to parameter 'adc'
   * @retval BOOL The bit indicates if the specific ADC starts to convert data
-    */
+	*/ 
 BOOL ADC_StartConversion(uint8_t adc, uint8_t convMode, uint32_t channel);
 
 /**
   * @brief  ADC starts to calibrate and produces one sample
-    * @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
-    * @param[in] convMode It should be a value of @ref ADC_CALIBRATION
+	* @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
+	* @param[in] convMode It should be a value of @ref ADC_CALIBRATION
   * @retval BOOL The bit indicates if the specific ADC starts to convert data
-    */
+	*/ 
 BOOL ADC_StartCalibration(uint8_t adc, uint8_t calibration);
 
 /**
   * @brief  ADC stops conversion or calibration
-    * @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
-    * @retval NULL
-    */
+	* @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
+	* @retval NULL
+	*/ 
 void ADC_Stop(uint8_t adc);
 
 /**
   * @brief  Check if ADC is busy or not
-    * @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
-    * @retval BOOL The bit indicates if the specific ADC is busy or not
-    */
+	* @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
+	* @retval BOOL The bit indicates if the specific ADC is busy or not
+	*/ 
 BOOL ADC_IsBusy(uint8_t adc);
 
 /**
   * @brief  Read data from ADC
-    * @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
-    * @param[in] Size Expected data size to be read
-    * @param[out] data A user-allocated buffer to fetch data to be read
+	* @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
+	* @param[in] Size Expected data size to be read
+	* @param[out] data A user-allocated buffer to fetch data to be read
   * @retval uint8_t Actual read data size
-    */
+	*/
 uint8_t ADC_Read(uint8_t adc, uint8_t size, ADC_Data* data);
 
 #ifdef __cplusplus

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_aes.h

@@ -1,29 +1,29 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_aes.h
-    *
-    * @brief    CMEM7 AES header file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_aes.h
+	*
+	* @brief    CMEM7 AES header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #ifndef __CMEM7_AES_H
 #define __CMEM7_AES_H
 
@@ -36,12 +36,12 @@
 
 /**
   * @brief  AES decryption
-    * @param[in] src A pointer to data to be decrypted
-    * @param[out] dst A user-allocated buffer to fetch decrypted data
+	* @param[in] src A pointer to data to be decrypted
+	* @param[out] dst A user-allocated buffer to fetch decrypted data
   * @param[in] len Expected data size to be decrypted, which should
-    *                        be multiply times of 16
-    * @retval BOOL True if succeed, or flase
-    */
+	*						 be multiply times of 16
+	* @retval BOOL True if succeed, or flase
+	*/
 BOOL AES_Decrypt(const void *src, void *dst, uint32_t len);
 
 #ifdef __cplusplus

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_can.h

@@ -1,29 +1,29 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_can.h
-    *
-    * @brief    CMEM7 CAN header file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_can.h
+	*
+	* @brief    CMEM7 CAN header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #ifndef __CMEM7_CAN_H
 #define __CMEM7_CAN_H
 
@@ -33,13 +33,13 @@
 
 #include "cmem7.h"
 #include "cmem7_conf.h"
-
+	 
 #define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN0) || \
                                    ((PERIPH) == CAN1))
 
 /** @defgroup CAN_FLT
   * @{
-  */
+  */																
 #define CAN_FLT_STANDARD_SINGLE    0x00000000
 #define CAN_FLT_STANDARD_DUAL      0x00000001
 #define CAN_FLT_EXTENDED_SINGLE    0x00000002
@@ -47,15 +47,15 @@
 
 #define IS_CAN_FLT_TYPE(FILTER)    (((FILTER) == CAN_FLT_STANDARD_SINGLE) || \
                                     ((FILTER) == CAN_FLT_STANDARD_DUAL) || \
-                                                                        ((FILTER) == CAN_FLT_EXTENDED_SINGLE) || \
-                                    ((FILTER) == CAN_FLT_EXTENDED_DUAL))
-
+																		((FILTER) == CAN_FLT_EXTENDED_SINGLE) || \
+                                    ((FILTER) == CAN_FLT_EXTENDED_DUAL))	
+																		
 #define IS_CAN_FLT_SINGLE(FILTER)  (((FILTER) == CAN_FLT_STANDARD_SINGLE) || \
                                     ((FILTER) == CAN_FLT_EXTENDED_SINGLE))
 
 #define IS_CAN_FLT_DUAL(FILTER)    (IS_CAN_FLT_TYPE(FILTER) && \
                                     !IS_CAN_FLT_SINGLE(FILTER))
-
+																		
 /**
   * @}
   */
@@ -74,12 +74,12 @@
 
 #define IS_CAN_CDR_DIV(DIV)        (((DIV) == CAN_CDR_DIV_1_2) || \
                                     ((DIV) == CAN_CDR_DIV_1_4) || \
-                                                                        ((DIV) == CAN_CDR_DIV_1_6) || \
-                                                                        ((DIV) == CAN_CDR_DIV_1_8) || \
-                                                                        ((DIV) == CAN_CDR_DIV_1_10) || \
-                                                                        ((DIV) == CAN_CDR_DIV_1_12) || \
-                                                                        ((DIV) == CAN_CDR_DIV_1_14) || \
-                                                                        ((DIV) == CAN_CDR_DIV_1_1))
+																		((DIV) == CAN_CDR_DIV_1_6) || \
+																		((DIV) == CAN_CDR_DIV_1_8) || \
+																		((DIV) == CAN_CDR_DIV_1_10) || \
+																		((DIV) == CAN_CDR_DIV_1_12) || \
+																		((DIV) == CAN_CDR_DIV_1_14) || \
+																		((DIV) == CAN_CDR_DIV_1_1))		
 /**
   * @}
   */
@@ -97,137 +97,137 @@
 #define CAN_INT_BUS_ERR            0x80
 #define CAN_INT_All                0xFF
 
-#define IS_CAN_INT(INT)            (((INT) != 0) && (((INT) & ~CAN_INT_All) == 0))
+#define IS_CAN_INT(INT)            (((INT) != 0) && (((INT) & ~CAN_INT_All) == 0))                                  
 /**
   * @}
   */
 
 /**
   * @brief  CAN standard filter structure
-    */
+	*/ 
 typedef struct {
-    uint16_t  ID28_18;               /*!< 11 bits                                      */
+	uint16_t  ID28_18;               /*!< 11 bits                                      */
   BOOL      RTR;                   /*!< if remote frame                              */
-    uint8_t   data1;                 /*!< data byte 1, if not 2nd CAN_FLT_STANDARD_DUAL*/
-    uint8_t   data2;                 /*!< data byte 2, if CAN_FLT_STANDARD_SINGLE      */
+	uint8_t   data1;                 /*!< data byte 1, if not 2nd CAN_FLT_STANDARD_DUAL*/
+	uint8_t   data2;                 /*!< data byte 2, if CAN_FLT_STANDARD_SINGLE      */
 } CAN_STANDARD_FILTER;
 
 /**
   * @brief  CAN extended filter structure
-    */
+	*/
 typedef struct {
-    uint16_t  ID28_13;               /*!< 16 bits                                      */
-    uint16_t  ID12_0;                /*!< 13 bits, if CAN_FLT_EXTENDED_SINGLE          */
+	uint16_t  ID28_13;               /*!< 16 bits                                      */
+	uint16_t  ID12_0;                /*!< 13 bits, if CAN_FLT_EXTENDED_SINGLE          */
   BOOL      RTR;                   /*!< if remote frame, if CAN_FLT_EXTENDED_SINGLE  */
 } CAN_EXTENDED_FILTER;
 
 /**
   * @brief  CAN filter structure
-    */
+	*/
 typedef struct {
-    uint8_t   type;                  /*!< Filter type, which is a value of @ref CAN_FLT */
-
-    /**
+	uint8_t   type;                  /*!< Filter type, which is a value of @ref CAN_FLT */
+	
+	/**
   * @brief  accepted filter
-    */
-    union {
-        CAN_STANDARD_FILTER sf;
-        CAN_EXTENDED_FILTER ef;
-    } ACCEPT;
-
-    /**
-  * @brief  filter mask
-    */
-    union {
-        CAN_STANDARD_FILTER sf;
-        CAN_EXTENDED_FILTER ef;
-    } MASK;
+	*/
+	union {
+		CAN_STANDARD_FILTER sf;				 
+		CAN_EXTENDED_FILTER ef;				 
+	} ACCEPT;												 
+	
+	/**
+  * @brief  filter mask 
+	*/
+	union {
+		CAN_STANDARD_FILTER sf;        
+		CAN_EXTENDED_FILTER ef;				 
+	} MASK;													 
 } CAN_FILTER;
 
 /**
   * @brief  CAN initialization structure
-    */
-typedef struct {
-    BOOL CAN_TxEn;                       /*!< if transmission is enable                                         */
-    BOOL CAN_Loopback;                   /*!< loop back mode without phy                                        */
-  uint8_t CAN_ClockDiv;                  /*!< input clock divider, ref as @ref CAN_CDR_DIV  */
-    uint16_t CAN_Prescaler;              /*!< Specifies the length of a time quantum.
-                                                                                Time quantum = (CAN_Prescaler + 1) * 2 * input clock */
-  uint8_t CAN_SJW;                       /*!< Specifies the maximum number of time quanta
-                                                                                the CAN hardware is allowed to lengthen or
-                                                                                shorten a bit to perform resynchronization.     */
-    uint8_t CAN_TSEG1;                   /*!< the maximum number of time quanta of
-                                                                                propagation and 1st phase segment                       */
-  uint8_t CAN_TSEG2;                     /*!< the maximum number of time quanta of 2nd
-                                                                                phase segment                                                                   */
-  BOOL CAN_HighSpeed;                    /*!< if CAN is running on high speed bus (class C) */
+	*/
+typedef struct {	
+	BOOL CAN_TxEn;            			 /*!< if transmission is enable 										*/
+	BOOL CAN_Loopback;        			 /*!< loop back mode without phy						 				*/
+  uint8_t CAN_ClockDiv;     			 /*!< input clock divider, ref as @ref CAN_CDR_DIV  */                               
+	uint16_t CAN_Prescaler;   			 /*!< Specifies the length of a time quantum. 
+																				Time quantum = (CAN_Prescaler + 1) * 2 * input clock */ 
+  uint8_t CAN_SJW;          			 /*!< Specifies the maximum number of time quanta 
+																				the CAN hardware is allowed to lengthen or 
+																				shorten a bit to perform resynchronization.		*/
+	uint8_t CAN_TSEG1;        			 /*!< the maximum number of time quanta of 
+																				propagation and 1st phase segment 						*/
+  uint8_t CAN_TSEG2;        			 /*!< the maximum number of time quanta of 2nd 
+																				phase segment																	*/	
+  BOOL CAN_HighSpeed;       			 /*!< if CAN is running on high speed bus (class C) */
 } CAN_InitTypeDef;
 
 /**
   * @brief  CAN frame structure
-    */
+	*/
 typedef struct
 {
-  BOOL SFF;                                      /*!< If standard or extended frame format                  */
-    uint32_t Id;                                     /*!< Specifies the identifier.This parameter can
-                                                                                be a value between 0 to 0x1FFFFFFF.                     */
-  BOOL RTR;                                      /*!< Specifies if the frame is a remote frame      */
-  uint8_t DLC;                                   /*!< Specifies the length of the frame, which is
-                                                                                a value between  0 to 8                                             */
-  uint8_t Data[8];                               /*!< Frame data                                                                        */
+  BOOL SFF;        								 /*!< If standard or extended frame format 					*/ 
+	uint32_t Id;     								 /*!< Specifies the identifier.This parameter can 
+																				be a value between 0 to 0x1FFFFFFF. 					*/
+  BOOL RTR;        								 /*!< Specifies if the frame is a remote frame      */
+  uint8_t DLC;     								 /*!< Specifies the length of the frame, which is 
+																				a value between  0 to 8 											*/
+  uint8_t Data[8]; 								 /*!< Frame data																		*/
 } CAN_Frame;
 
 /**
   * @brief  CAN initialization
   * @note   This function should be called at first before any other interfaces.
-    * @param[in] CANx CAN peripheral, which is CAN0 or CAN1
-    * @param[in] Init A pointer to structure CAN_InitTypeDef
-    * @param[in] f1 A pointer to structure CAN_FILTER
-    * @param[in] f2 NULL if single filter, or a pointer to second filter while dual filters
+	* @param[in] CANx CAN peripheral, which is CAN0 or CAN1
+	* @param[in] Init A pointer to structure CAN_InitTypeDef
+	* @param[in] f1 A pointer to structure CAN_FILTER
+	* @param[in] f2 NULL if single filter, or a pointer to second filter while dual filters
   * @retval BOOL The bit indicates if specific CAN is initialized or not
-    */
-BOOL CAN_Init(CAN0_Type* CANx, CAN_InitTypeDef* Init,
+	*/ 
+BOOL CAN_Init(CAN0_Type* CANx, CAN_InitTypeDef* Init, 
   CAN_FILTER *f1, CAN_FILTER *f2);
 
 /**
   * @brief  CAN is set to sleep or wake up
   * @param[in] CANx CAN peripheral, which is CAN0 or CAN1
-    * @param[in] Enable The bit indicates if sleep mode is enable or not
-    * @retval None
-    */
+	* @param[in] Enable The bit indicates if sleep mode is enable or not
+	* @retval None
+	*/
 void CAN_SetSleepMode(CAN0_Type* CANx, BOOL enable);
 
 /**
-  * @brief  Enable or disable UART interrupt.
-    * @param[in] CANx CAN peripheral, which is CAN0 or CAN1
-    * @param[in] Int interrupt mask bits, which can be the combination of @ref CAN_INT
-    * @param[in] Enable The bit indicates if specific interrupts are enable or not
+  * @brief  Enable or disable UART interrupt. 
+	* @param[in] CANx CAN peripheral, which is CAN0 or CAN1
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref CAN_INT
+	* @param[in] Enable The bit indicates if specific interrupts are enable or not
   * @retval None
-    */
+	*/ 
 void CAN_EnableInt(CAN0_Type* CANx, uint32_t Int, BOOL enable);
 
 /**
-  * @brief  Check specific interrupts are set or not
-    * @note   All interrupts except for receive int are cleared after call this func.
-    * @param[in] CANx CAN peripheral, which is CAN0 or CAN1
-    * @retval uint8_t CAN interrupt bits, which can be the combination of @ref CAN_INT
-    */
+  * @brief  Check specific interrupts are set or not 
+	* @note   All interrupts except for receive int are cleared after call this func.
+	* @param[in] CANx CAN peripheral, which is CAN0 or CAN1
+	* @retval uint8_t CAN interrupt bits, which can be the combination of @ref CAN_INT
+	*/
 uint8_t CAN_GetIntStatus(CAN0_Type* CANx);
 
 /**
   * @brief  CAN perform to transmit data
-    * @param[in] CANx CAN peripheral, which is CAN0 or CAN1
-    * @param[in] frame A pointer to the CAN_Frame to be transmitted
-    * @retval BOOL The bit indicates if data is transmitted or not
-    */
+	* @param[in] CANx CAN peripheral, which is CAN0 or CAN1
+	* @param[in] frame A pointer to the CAN_Frame to be transmitted
+	* @retval BOOL The bit indicates if data is transmitted or not
+	*/ 
 BOOL CAN_Transmit(CAN0_Type* CANx, CAN_Frame* frame);
 
 /**
   * @brief  CAN perform to receive data
-    * @param[in] CANx CAN peripheral, which is CAN0 or CAN1
-    * @param[out] frame A user-allocated buffer to fetch received frame
-    * @retval BOOL The bit indicates if data is recieved or not
-    */
+	* @param[in] CANx CAN peripheral, which is CAN0 or CAN1
+	* @param[out] frame A user-allocated buffer to fetch received frame
+	* @retval BOOL The bit indicates if data is recieved or not
+	*/
 BOOL CAN_Receive(CAN0_Type* CANx, CAN_Frame* frame);
 
 #ifdef __cplusplus

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_conf.h

@@ -1,28 +1,28 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_conf.h
-    *
-    * @brief    CMEM7 config file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
+	*****************************************************************************
+	* @file     cmem7_conf.h
+	*
+	* @brief    CMEM7 config file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
 
 #ifndef __CMEM7_CONF_H
 #define __CMEM7_CONF_H
@@ -50,7 +50,7 @@
 #define _M7NORFLASH
 #define _ME_6095_F
 
-#define USE_FULL_ASSERT    1
+#define USE_FULL_ASSERT    1 
 
 #ifdef  USE_FULL_ASSERT
 /**
@@ -62,11 +62,11 @@
   */
   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((unsigned char *)__FILE__, __LINE__))
 
-    static void assert_failed(unsigned char* file, unsigned long line) {
-        while (1) {
-            ;
-        }
-    }
+	static void assert_failed(unsigned char* file, unsigned long line) {
+		while (1) {
+			;
+		}
+	}
 #else
   #define assert_param(expr) ((void)0)
 #endif /* USE_FULL_ASSERT */
@@ -76,16 +76,16 @@ typedef enum _BOOL {FALSE = 0, TRUE = 1} BOOL;
 /**
   * System clock frequency, unit is Hz.
   */
-#define SYSTEM_CLOCK_FREQ        300000000
+#define SYSTEM_CLOCK_FREQ        300000000 
 //250000000
 //300000000
 
 /**
-  * @brief  usecond delay
-    * @note     It can't delay in an accurate time
-    * @param[in] usec usecond to be delay
-    * @retval None
-    */
+  * @brief  usecond delay 
+	* @note 	It can't delay in an accurate time
+	* @param[in] usec usecond to be delay
+	* @retval None
+	*/
 static void udelay(unsigned long usec) {
   unsigned long count = 0;
   unsigned long utime = SYSTEM_CLOCK_FREQ / 1000000 * usec;
@@ -95,18 +95,18 @@ static void udelay(unsigned long usec) {
 
 /**
   * UART definition for print
-    */
-#define PRINT_UART                          UART2
+	*/
+#define PRINT_UART							UART2
 
 /**
   * DDR type definition
   */
-#define DDR_TYPE                3   // 2 for DDR2, 3 for DDR3
+#define DDR_TYPE				3	// 2 for DDR2, 3 for DDR3
 
 #if (DDR_TYPE == 3)
-# define DDR_SIZE               (256 << 20)
+# define DDR_SIZE				(256 << 20)
 #elif (DDR_TYPE == 2)
-# define DDR_SIZE               (128 << 20)
+# define DDR_SIZE				(128 << 20)
 #else
 # error
 #endif

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_ddr.h

@@ -1,29 +1,29 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_ddr.h
-    *
-    * @brief    CMEM7 AES header file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_ddr.h
+	*
+	* @brief    CMEM7 AES header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #ifndef __CMEM7_DDR_H
 #define __CMEM7_DDR_H
 
@@ -36,11 +36,11 @@
 /** @defgroup _MEM_TYPE
   * @{
   */
-enum _MEM_TYPE
+enum _MEM_TYPE 
 {
-    MEM_DDR2=1,
-    MEM_DDR3
-} ;
+	MEM_DDR2=1,
+	MEM_DDR3		
+} ;	
 /**
   * @}
   */
@@ -50,30 +50,30 @@ enum _MEM_TYPE
   */
 enum _BUS_WIDTH
 {
-    BUS_WIDTH_8,
-    BUS_WIDTH_16,
-    BUS_WIDTH_MAX
+	BUS_WIDTH_8,
+	BUS_WIDTH_16,
+	BUS_WIDTH_MAX
 };
 /**
   * @}
   */
 /** @defgroup _CHIP_TYPE
   * @{
-  */
+  */  
 enum _CHIP_TYPE
 {
-    _32Mbx8,
-    _64Mbx8,
-    _128Mbx8,
-    _256Mbx8,
-    _512Mbx8,
-    _16Mbx16,
-    _32Mbx16,
-    _64Mbx16,
-    _128Mbx16,
-    _256Mbx16,
-    _512Mbx16,
-    CHIP_TYPE_MAX
+	_32Mbx8,
+	_64Mbx8,
+	_128Mbx8,
+	_256Mbx8,
+	_512Mbx8,
+	_16Mbx16,
+	_32Mbx16,
+	_64Mbx16,
+	_128Mbx16,
+	_256Mbx16,
+	_512Mbx16,
+	CHIP_TYPE_MAX
 };
 /**
   * @}
@@ -81,27 +81,27 @@ enum _CHIP_TYPE
 
 /** @defgroup _CHIP_NUM
   * @{
-  */
+  */  
 enum _CHIP_NUM
 {
-    CHIP_NUM_x1,
-    CHIP_NUM_x2,
-    CHIP_NUM_MAX
+	CHIP_NUM_x1,
+	CHIP_NUM_x2,
+	CHIP_NUM_MAX
 };
 /**
   * @}
   */
-
+  
 /** @defgroup MEM_CHIP_INFO
   * @{
   */
 typedef struct {
-    uint8_t mem_type;     /*!< ddr type @ref _MEM_TYPE*/
-    uint8_t Bus_width;  /*!< ddr qs bus width @ref _BUS_WIDTH*/
-    uint8_t Chip_type;  /*!< chip type @ref _CHIP_TYPE*/
-    uint8_t Chip_num;   /*!< chip number @ref _CHIP_NUM*/
-    uint8_t Chip_bank;      /*!< chip bank number*/
-} MEM_CHIP_INFO;
+	uint8_t mem_type;     /*!< ddr type @ref _MEM_TYPE*/
+	uint8_t Bus_width;	/*!< ddr qs bus width @ref _BUS_WIDTH*/
+	uint8_t Chip_type;	/*!< chip type @ref _CHIP_TYPE*/
+	uint8_t Chip_num;	/*!< chip number @ref _CHIP_NUM*/
+	uint8_t Chip_bank;      /*!< chip bank number*/		
+} MEM_CHIP_INFO;								
 /**
   * @}
   */
@@ -111,18 +111,18 @@ typedef struct {
   * @{
   */
 typedef struct {
-    uint32_t tCK;               /*!< Period of clock(ps), not data period */
-    uint32_t tCL;                       /*!< tCL */
-    uint32_t tRCD;                      /*!< tRCD */
-    uint32_t tRP;                       /*!< tRP */
-    uint32_t tRC;                       /*!< tRC */
-    uint32_t tRAS;                      /*!< tRAS */
-    uint32_t tWR;                       /*!< tWR */
-    uint32_t tRRD;                      /*!< tRRD */
-    uint32_t tWTR;                      /*!< tWTR */
-    uint32_t tRTP;                      /*!< tRTP */
-    uint32_t tFAW;                      /*!< tFAW */
-} DDR2MEM;                              /*!< DDR2时序定义 */
+	uint32_t tCK;       		/*!< Period of clock(ps), not data period */ 
+	uint32_t tCL;						/*!< tCL */
+	uint32_t tRCD;						/*!< tRCD */
+	uint32_t tRP;						/*!< tRP */
+	uint32_t tRC;						/*!< tRC */
+	uint32_t tRAS;						/*!< tRAS */
+	uint32_t tWR;						/*!< tWR */
+	uint32_t tRRD;						/*!< tRRD */
+	uint32_t tWTR;						/*!< tWTR */
+	uint32_t tRTP;						/*!< tRTP */
+	uint32_t tFAW;						/*!< tFAW */
+} DDR2MEM;								/*!< DDR2ʱÐò¶¨Òå */
 /**
   * @}
   */
@@ -131,20 +131,20 @@ typedef struct {
   * @{
   */
 typedef struct {
-    uint32_t tCK;               /*!< Period of clock(ps), not data period */
-    uint32_t tCL;                       /*!< tCL */
-    uint32_t tWCL;                      /*!< tWCL */
-    uint32_t tRCD;                      /*!< tRCD */
-    uint32_t tRAS;                      /*!< tRAS */
-    uint32_t tRP;                       /*!< tRP */
-    uint32_t tRC;                       /*!< tRC */
-    uint32_t tRRD;                      /*!< tRRD */
-    uint32_t tFAW;                      /*!< tFAW */
-    uint32_t tWR;                       /*!< tWR */
-    uint32_t tRTP;                      /*!< tRTP */
-    uint32_t tZQoper;                   /*!< tZQCL */
-    uint32_t tZQCS;                     /*!< tZQCS */
-} DDR3MEM;                              /*!< DDR3时序定义 */
+	uint32_t tCK;       		/*!< Period of clock(ps), not data period */ 
+	uint32_t tCL;						/*!< tCL */
+	uint32_t tWCL;						/*!< tWCL */
+	uint32_t tRCD;						/*!< tRCD */
+	uint32_t tRAS;						/*!< tRAS */
+	uint32_t tRP;						/*!< tRP */
+	uint32_t tRC;						/*!< tRC */
+	uint32_t tRRD;						/*!< tRRD */
+	uint32_t tFAW;						/*!< tFAW */
+	uint32_t tWR;						/*!< tWR */
+	uint32_t tRTP;						/*!< tRTP */
+	uint32_t tZQoper;					/*!< tZQCL */
+	uint32_t tZQCS;						/*!< tZQCS */
+} DDR3MEM;								/*!< DDR3ʱÐò¶¨Òå */
 /**
   * @}
   */
@@ -152,8 +152,8 @@ typedef struct {
 /** @defgroup DDR2PREDEF
   * @{
   */
-extern const DDR2MEM DDR2PREDEF[];      /*!< Pre-defined DDR2 Timing in library */
-#define DDR2_400C           0           /*!< sg5E: DDR2-400C CL=4, tCK=5000ps */
+extern const DDR2MEM DDR2PREDEF[];		/*!< Pre-defined DDR2 Timing in library */
+#define DDR2_400C			0			/*!< sg5E: DDR2-400C CL=4, tCK=5000ps */
 
 /**
   * @}
@@ -162,8 +162,8 @@ extern const DDR2MEM DDR2PREDEF[];      /*!< Pre-defined DDR2 Timing in library
 /** @defgroup DDR3PREDEF
   * @{
   */
-extern const DDR3MEM DDR3PREDEF[];      /*!< Pre-defined DDR3 Timing in library */
-#define DDR3_400            0
+extern const DDR3MEM DDR3PREDEF[];		/*!< Pre-defined DDR3 Timing in library */
+#define DDR3_400		  	0
 #define DDR3_667        1
 
 /**

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_dma.h

@@ -1,29 +1,29 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_dma.h
-    *
-    * @brief    CMEM7 DMA header file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_dma.h
+	*
+	* @brief    CMEM7 DMA header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #ifndef __CMEM7_DMA_H
 #define __CMEM7_DMA_H
 
@@ -37,75 +37,75 @@
 /** @defgroup DMA_Int
   * @{
   */
-#define DMA_Int_TfrComplete                0x00000001
+#define DMA_Int_TfrComplete                0x00000001    
 #define DMA_Int_Err                        0x00000002
 #define DMA_Int_All                        0x00000003
 
 #define IS_DMA_INT(INT)        (((INT) != 0) && (((INT) & ~DMA_Int_All) == 0))
 /**
   * @}
-  */
+  */ 
 
 /**
   * @brief  Descriptor structure
-    *   @note       DMA requires users provides a list of descriptors to operation.
-    *                   Meanwhile, memory occupied by descriptors should be in physical
-    *                   memory and keep valid during DMA transfer.
-    */
-typedef struct {
-    uint32_t srcAddr;                  /*!< source address                                                      */
-    uint32_t dstAddr;                  /*!< destination address                                             */
-    uint32_t number;                   /*!< block byte number, no more than 2K Bytes    */
-    uint32_t nextBlock;                /*!< next block descriptor                                       */
-    uint32_t padding;                  /*!< Nonsense, only used to fill                             */
+	*	@note		DMA requires users provides a list of descriptors to operation.
+	*					Meanwhile, memory occupied by descriptors should be in physical
+	*					memory and keep valid during DMA transfer.
+	*/ 
+typedef struct {                      
+	uint32_t srcAddr;                  /*!< source address 														*/		
+	uint32_t dstAddr;                  /*!< destination address 											*/	
+	uint32_t number;                   /*!< block byte number, no more than 2K Bytes 	*/
+	uint32_t nextBlock;                /*!< next block descriptor 										*/
+	uint32_t padding;                  /*!< Nonsense, only used to fill 							*/
 } BLOCK_DESC;
-
+	
 /**
   * @brief  DMA initialization
   * @note   This function should be called at first before any other interfaces.
-    * @param  None
-    * @retval None
-    */
+	* @param  None
+	* @retval None
+	*/ 
 void DMA_Init(void);
 
 /**
-  * @brief  Enable or disable DMA interrupt.
-    * @param[in] Int interrupt mask bits, which can be the combination of @ref DMA_Int
-    * @param[in] Enable The bit indicates if specific interrupts are enable or not
+  * @brief  Enable or disable DMA interrupt. 
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref DMA_Int
+	* @param[in] Enable The bit indicates if specific interrupts are enable or not
   * @retval None
-    */
+	*/ 
 void DMA_EnableInt(uint32_t Int, BOOL enable);
 
 /**
-  * @brief  Check specific interrupts are set or not
-    * @param[in] Int interrupt mask bits, which can be the combination of @ref DMA_Int
+  * @brief  Check specific interrupts are set or not 
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref DMA_Int
   * @retval BOOL The bit indicates if specific interrupts are set or not
-    */
+	*/
 BOOL DMA_GetIntStatus(uint32_t Int);
 
 /**
   * @brief  Clear specific interrupts
-    * @param[in] Int interrupt mask bits, which can be the combination of @ref DMA_Int
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref DMA_Int
   * @retval None
-    */
+	*/
 void DMA_ClearInt(uint32_t Int);
 
 /**
   * @brief  DMA transfer
-    * @note     Make sure that memory occupied by descriptors should be in physical
-    *                   memory and keep valid before DMA transfer is finished (Return false by
-    *                   calling DMA_IsBusy after DMA transfer started).
-    * @param[in] blockList A pointer to header of list of BLOCK_DESC
+	* @note		Make sure that memory occupied by descriptors should be in physical
+	*					memory and keep valid before DMA transfer is finished (Return false by
+	*					calling DMA_IsBusy after DMA transfer started).
+	* @param[in] blockList A pointer to header of list of BLOCK_DESC
   * @retval BOOL The bit indicates if DMA begins to transfer
-    * @see      DMA_IsBusy
-    */
+	* @see		DMA_IsBusy
+	*/
 BOOL DMA_Transfer(BLOCK_DESC *blockList);
 
 /**
   * @brief  DMA is busy or not
   * @param  None
-    * @retval BOOL The bit indicates if DMA is busy or not
-    */
+	* @retval BOOL The bit indicates if DMA is busy or not
+	*/ 
 BOOL DMA_IsBusy(void);
 
 #ifdef __cplusplus

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_efuse.h

@@ -1,29 +1,29 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_efuse.h
-    *
-    * @brief    CMEM7 EFUSE header file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_efuse.h
+	*
+	* @brief    CMEM7 EFUSE header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #ifndef __CMEM7_EFUSE_H
 #define __CMEM7_EFUSE_H
 
@@ -50,60 +50,60 @@
 
 /**
   * @brief  EFUSE timing structure
-    */
+	*/
 typedef struct
 {
-    uint32_t EFUSE_Tpwph;                  /*!< Nano second                                    */
+	uint32_t EFUSE_Tpwph;                  /*!< Nano second                                    */
   uint32_t EFUSE_Trac;                   /*!< Nano second                                    */
-    uint32_t EFUSE_Trah;                   /*!< Nano second                                    */
-    uint32_t EFUSE_Trpw;                   /*!< Nano second                                    */
-    uint32_t EFUSE_Trc;                    /*!< Nano second                                    */
-    uint32_t EFUSE_Tesr;                   /*!< Nano second                                    */
-    uint32_t EFUSE_Tprs;                   /*!< Nano second                                    */
-    uint32_t EFUSE_Tpi;                    /*!< Nano second                                    */
-    uint32_t EFUSE_Tpp;                    /*!< Nano second                                    */
-    uint32_t EFUSE_Teps;                   /*!< Nano second                                    */
-    uint32_t EFUSE_Tpwps;                  /*!< Nano second                                    */
+	uint32_t EFUSE_Trah;                   /*!< Nano second                                    */
+	uint32_t EFUSE_Trpw;                   /*!< Nano second                                    */
+	uint32_t EFUSE_Trc;                    /*!< Nano second                                    */
+	uint32_t EFUSE_Tesr;                   /*!< Nano second                                    */
+	uint32_t EFUSE_Tprs;                   /*!< Nano second                                    */
+	uint32_t EFUSE_Tpi;                    /*!< Nano second                                    */
+	uint32_t EFUSE_Tpp;                    /*!< Nano second                                    */
+	uint32_t EFUSE_Teps;                   /*!< Nano second                                    */
+	uint32_t EFUSE_Tpwps;                  /*!< Nano second                                    */
 } EFUSE_Timing;
 
 /**
   * @brief  EFUSE initialization structure
-    */
+	*/
 typedef struct
 {
-    uint8_t EFUSE_ClockDividor;              /*!< EFUSE clock dividor, 2 in n times */
-    uint8_t EFUSE_TMRF;                    /*!< EFUSE reference resistor select, @ref EFUSE_TMRF_R */
+	uint8_t EFUSE_ClockDividor;       		 /*!< EFUSE clock dividor, 2 in n times */
+	uint8_t EFUSE_TMRF;                    /*!< EFUSE reference resistor select, @ref EFUSE_TMRF_R */
   EFUSE_Timing* timing;                  /*!< Timing configuration, null if default           */
 } EFUSE_InitTypeDef;
 
 /**
   * @brief  EFUSE key structure
-    */
+	*/
 typedef struct
 {
-    uint32_t key0;                         /*!< EFUSE AES key [31:0]                            */
+	uint32_t key0;                         /*!< EFUSE AES key [31:0]                            */
   uint32_t key1;                         /*!< EFUSE AES key [63:32]                           */
-    uint32_t key2;                         /*!< EFUSE AES key [95:64]                           */
-    uint32_t key3;                         /*!< EFUSE AES key [127:96]                          */
-    uint32_t key4;                         /*!< EFUSE AES key [159:128]                         */
+	uint32_t key2;                         /*!< EFUSE AES key [95:64]                           */
+	uint32_t key3;                         /*!< EFUSE AES key [127:96]                          */
+	uint32_t key4;                         /*!< EFUSE AES key [159:128]                         */
   uint32_t key5;                         /*!< EFUSE AES key [191:160]                         */
-    uint32_t key6;                         /*!< EFUSE AES key [223:192]                         */
-    uint32_t key7;                         /*!< EFUSE AES key [255:224]                         */
+	uint32_t key6;                         /*!< EFUSE AES key [223:192]                         */
+	uint32_t key7;                         /*!< EFUSE AES key [255:224]                         */
 } EFUSE_AesKey;
 
 /**
   * @brief  EFUSE initialization
   * @note   This function should be called at first before any other interfaces.
-    * @param[in] init A pointer to structure EFUSE_InitTypeDef
+	* @param[in] init A pointer to structure EFUSE_InitTypeDef
   * @retval None
-    */
+	*/ 
 void EFUSE_Init(EFUSE_InitTypeDef* init);
 
 /**
   * @brief  EFUSE initialization
   * @param[in] key A pointer to EFUSE_AesKey to be compared
   * @retval BOOL True if equal, or false if different
-    */
+	*/ 
 BOOL EFUSE_Compare(EFUSE_AesKey* key);
 
 #ifdef __cplusplus

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_eth.h

@@ -1,29 +1,29 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_eth.h
-    *
-    * @brief    CMEM7 ethernet header file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_eth.h
+	*
+	* @brief    CMEM7 ethernet header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #ifndef __CMEM7_ETH_H
 #define __CMEM7_ETH_H
 
@@ -41,9 +41,9 @@
 #define ETH_SPEED_100M              0x1
 #define ETH_SPEED_1000M             0x2
 
-#define IS_ETH_SPEED(SPEED)             (((SPEED) == ETH_SPEED_10M)  || \
+#define IS_ETH_SPEED(SPEED)    			(((SPEED) == ETH_SPEED_10M)  || \
                                      ((SPEED) == ETH_SPEED_100M) || \
-                                                                         ((SPEED) == ETH_SPEED_1000M))
+																		 ((SPEED) == ETH_SPEED_1000M))
 /**
   * @}
   */
@@ -54,33 +54,33 @@
 #define ETH_DUPLEX_HALF             0x0
 #define ETH_DUPLEX_FULL             0x1
 
-#define IS_ETH_DUPLEX(DUPLEX)           (((DUPLEX) == ETH_DUPLEX_HALF) || \
-                                                                         ((DUPLEX) == ETH_DUPLEX_FULL))
+#define IS_ETH_DUPLEX(DUPLEX)  			(((DUPLEX) == ETH_DUPLEX_HALF) || \
+																		 ((DUPLEX) == ETH_DUPLEX_FULL))
 /**
   * @}
   */
 
 /** @defgroup ETH_INT
   * @{
-  */
-#define ETH_INT_TX_COMPLETE_FRAME       0x0001
+  */																			
+#define ETH_INT_TX_COMPLETE_FRAME		0x0001
 #define ETH_INT_TX_STOP             0x0002
 #define ETH_INT_TX_BUF_UNAVAI       0x0004
-#define ETH_INT_RX_OVERFLOW                 0x0010
-#define ETH_INT_TX_UNDERFLOW                0x0020
+#define ETH_INT_RX_OVERFLOW					0x0010
+#define ETH_INT_TX_UNDERFLOW				0x0020
 #define ETH_INT_RX_COMPLETE_FRAME   0x0040
 #define ETH_INT_RX_BUF_UNAVAI       0x0080
 #define ETH_INT_RX_STOP             0x0100
 #define ETH_INT_BUS_FATAL_ERROR     0x2000
 #define ETH_INT_ALL                 (ETH_INT_TX_COMPLETE_FRAME | \
                                      ETH_INT_TX_STOP           | \
-                                                                         ETH_INT_TX_BUF_UNAVAI     | \
-                                                                         ETH_INT_RX_OVERFLOW       | \
-                                                                         ETH_INT_TX_UNDERFLOW      | \
-                                                                         ETH_INT_RX_COMPLETE_FRAME | \
-                                                                         ETH_INT_RX_BUF_UNAVAI     | \
-                                                                         ETH_INT_RX_STOP           | \
-                                                                         ETH_INT_BUS_FATAL_ERROR)
+																		 ETH_INT_TX_BUF_UNAVAI     | \
+																		 ETH_INT_RX_OVERFLOW       | \
+																		 ETH_INT_TX_UNDERFLOW      | \
+																		 ETH_INT_RX_COMPLETE_FRAME | \
+																		 ETH_INT_RX_BUF_UNAVAI     | \
+																		 ETH_INT_RX_STOP           | \
+																		 ETH_INT_BUS_FATAL_ERROR)
 
 #define IS_ETH_INT(INT)             (((INT) != 0) && (((INT) & ~ETH_INT_ALL) == 0))
 /**
@@ -88,132 +88,132 @@
   */
 /**
   * @brief  EFUSE receive filter structure
-    */
+	*/
 typedef struct
 {
-    BOOL ETH_BroadcastFilterEnable;   /*!< Broadcast is dropped or passed                                       */
-    BOOL ETH_OwnFilterEnable;           /*!< source address filter is on or off                                 */
-    BOOL ETH_SelfDrop;                          /*!< Only own address is dropped or passed                              */
-    BOOL ETH_SourceFilterEnable;        /*!< source address filter is on or off                                 */
-    BOOL ETH_SourceDrop;                      /*!< Only specific source address is dropped or passed    */
-    uint8_t ETH_SourceMacAddr[6];     /*!< Source MAC address                                   */
+	BOOL ETH_BroadcastFilterEnable;   /*!< Broadcast is dropped or passed								        */ 
+	BOOL ETH_OwnFilterEnable;	        /*!< source address filter is on or off     							*/
+	BOOL ETH_SelfDrop;				  			/*!< Only own address is dropped or passed								*/
+	BOOL ETH_SourceFilterEnable;	    /*!< source address filter is on or off     							*/
+	BOOL ETH_SourceDrop;				      /*!< Only specific source address is dropped or passed  	*/
+	uint8_t ETH_SourceMacAddr[6];     /*!< Source MAC address                                   */
 } ETH_FrameFilter;
 
 /**
   * @brief  Ethernet initialization structure
-    */
+	*/ 
 typedef struct
 {
-    BOOL ETH_LinkUp;                   /*!< If ETH is linked up and it can be retrieved from PHY */
-    uint8_t ETH_Speed;                 /*!< speed of ETH, refer as @ref ETH_SPEED                */
-    uint8_t ETH_Duplex;                /*!< duplex mode of ETH, refer as @ref ETH_DUPLEX                 */
-    BOOL ETH_RxEn;                     /*!< Rx enable                                            */
-    BOOL ETH_TxEn;                     /*!< Tx enable                                            */
-    BOOL ETH_ChecksumOffload;          /*!< Checksum offload enable                              */
-    BOOL ETH_JumboFrame;               /*!< Jumbo Frame Enable                                   */
-    uint8_t ETH_MacAddr[6];            /*!< MAC address                                          */
+    BOOL ETH_LinkUp;                   /*!< If ETH is linked up and it can be retrieved from PHY */																	  
+	uint8_t ETH_Speed;                 /*!< speed of ETH, refer as @ref ETH_SPEED                */
+    uint8_t ETH_Duplex;                /*!< duplex mode of ETH, refer as @ref ETH_DUPLEX				 */
+	BOOL ETH_RxEn;                     /*!< Rx enable                                            */
+	BOOL ETH_TxEn;                     /*!< Tx enable                                            */
+	BOOL ETH_ChecksumOffload;          /*!< Checksum offload enable                              */
+	BOOL ETH_JumboFrame;               /*!< Jumbo Frame Enable                                   */
+	uint8_t ETH_MacAddr[6];            /*!< MAC address                                          */ 
     ETH_FrameFilter *ETH_Filter;       /*!< Received frame address filter, receive all if null   */
 } ETH_InitTypeDef;
 
 /**
   * @brief  Ethernet Tx descriptor structure
-    */
-typedef struct {
-    union {
+	*/ 
+typedef struct { 
+	union {
     uint32_t  TX0;
-
-        struct {
-            uint32_t                                :  1;
-            uint32_t UNDERFLOW_ERR  :  1;    /*!< [OUT] Underflow error                                                     */
-            uint32_t                                :  1;
-            uint32_t COLLISION_CNT  :  4;        /*!< [OUT] Collision count                                       */
-            uint32_t                                :  1;
-            uint32_t EX_COLLISION   :  1;        /*!< [OUT] Excessive collision error                         */
-            uint32_t LATE_COLLISION :  1;        /*!< [OUT] Late collision error                              */
-            uint32_t NO_CARRIER     :  1;        /*!< [OUT] No carrier error                                    */
-            uint32_t LOSS_CARRIER   :  1;        /*!< [OUT] loss of carrier error                           */
-            uint32_t PAYLOAD_ERR        :  1;        /*!< [OUT] IP payload error                                    */
-            uint32_t                                :  2;
-            uint32_t ERR_SUM                :  1;        /*!< [OUT] Error summary                                           */
-            uint32_t HEADER_ERR         :  1;        /*!< [OUT] IP header error                                         */
-            uint32_t                                :  8;
-            uint32_t TTSE           :  1;    /*!< enables IEEE1588 hardware timestamping in first segment */
-            uint32_t                                :  2;
-            uint32_t FS             :  1;    /*!< first segment flag                                    */
-            uint32_t LS             :  1;    /*!< last segment flag                                     */
-            uint32_t                                :  2;
-        } TX0_b;
-    } TX_0;
-
-    union {
+		
+		struct {
+			uint32_t 								:  1;
+			uint32_t UNDERFLOW_ERR  :  1; 	 /*!< [OUT] Underflow error            											*/
+			uint32_t 								:  1;
+			uint32_t COLLISION_CNT	:  4;		 /*!< [OUT] Collision count				                          */
+			uint32_t 								:  1;
+			uint32_t EX_COLLISION 	:  1;		 /*!< [OUT] Excessive collision error	                      */
+			uint32_t LATE_COLLISION :  1;		 /*!< [OUT] Late collision error	                          */
+			uint32_t NO_CARRIER     :  1;		 /*!< [OUT] No carrier error                          			*/
+			uint32_t LOSS_CARRIER   :  1;		 /*!< [OUT] loss of carrier error                          	*/
+			uint32_t PAYLOAD_ERR 		:  1;		 /*!< [OUT] IP payload error                          			*/
+			uint32_t 								:  2;
+			uint32_t ERR_SUM 				:  1;		 /*!< [OUT] Error summary		                          			*/
+			uint32_t HEADER_ERR 		:  1;		 /*!< [OUT] IP header error                          				*/
+			uint32_t 								:  8;
+			uint32_t TTSE           :  1; 	 /*!< enables IEEE1588 hardware timestamping in first segment */
+			uint32_t 								:  2;
+			uint32_t FS           	:  1; 	 /*!< first segment flag                                    */
+			uint32_t LS           	:  1; 	 /*!< last segment flag                                     */
+			uint32_t 								:  2;
+		} TX0_b;
+	} TX_0;
+	
+	union {
     uint32_t  TX1;
-
-        struct {
-            uint32_t SIZE                       : 13;       /*!< buffer size                                       */
-            uint32_t                : 19;
-        } TX1_b;
-    } TX_1;
-
-    uint32_t bufAddr;                                           /*!< address of buffer                                           */
-    uint32_t nextDescAddr;                              /*!< address of next descriptor                          */
+		
+		struct {
+			uint32_t SIZE						: 13; 	 	/*!< buffer size                                       */
+			uint32_t                : 19;
+		} TX1_b;
+	} TX_1;
+	
+	uint32_t bufAddr;											/*!< address of buffer						                     */
+	uint32_t nextDescAddr;								/*!< address of next descriptor		                     */
   uint64_t reserved;
-    uint64_t timeStamp;                                     /*!< time stamp while last segment                     */
+	uint64_t timeStamp;									 	/*!< time stamp while last segment                     */
 } ETH_TX_DESC;
 
 /**
   * @brief  Ethernet Rx descriptor structure
-    */
-typedef struct {
-    union {
+	*/ 
+typedef struct { 
+	union {
     uint32_t  RX0;
-
-        struct {
-            uint32_t                                :  1;
-            uint32_t CRC_ERR        :  1;    /*!< [OUT] CRC error while last segment                        */
-            uint32_t                                :  5;
-            uint32_t TTSE           :  1;    /*!< timestamp available while last segment                */
-            uint32_t LS             :  1;    /*!< [OUT] last segment flag                               */
-            uint32_t FS             :  1;    /*!< [OUT] first segment flag                              */
-            uint32_t                                :  1;
-            uint32_t OVERFLOW_ERR   :  1;    /*!< [OUT] FIFO overflow while last segment                */
-            uint32_t LENGTH_ERR     :  1;    /*!< [OUT] length error while last segment                 */
-            uint32_t                                :  2;
-            uint32_t ERR_SUM        :  1;    /*!< [OUT] Error summary while last segment                */
-            uint32_t FL             : 14;    /*!< [OUT] frame length while last segment                 */
-            uint32_t                    :  2;
-        } RX0_b;
-    } RX_0;
-
-    union {
+		
+		struct {
+			uint32_t 								:  1;
+			uint32_t CRC_ERR        :  1; 	 /*!< [OUT] CRC error while last segment                		*/
+			uint32_t 								:  5;
+			uint32_t TTSE           :  1; 	 /*!< timestamp available while last segment                */
+			uint32_t LS           	:  1; 	 /*!< [OUT] last segment flag                               */
+			uint32_t FS           	:  1; 	 /*!< [OUT] first segment flag                              */
+			uint32_t 								:  1;
+			uint32_t OVERFLOW_ERR   :  1; 	 /*!< [OUT] FIFO overflow while last segment                */
+			uint32_t LENGTH_ERR     :  1; 	 /*!< [OUT] length error while last segment                	*/
+			uint32_t 								:  2;
+			uint32_t ERR_SUM        :  1; 	 /*!< [OUT] Error summary while last segment              	*/
+			uint32_t FL           	: 14; 	 /*!< [OUT] frame length while last segment                 */
+			uint32_t 		           	:  2;
+		} RX0_b;
+	} RX_0;
+	
+	union {
     uint32_t  RX1;
-
-        struct {
-            uint32_t SIZE                       : 13;       /*!< buffer size                                       */
-            uint32_t                : 19;
-        } RX1_b;
-    } RX_1;
-
-    uint32_t bufAddr;                                           /*!< buffer address                                    */
-    uint32_t nextDescAddr;                              /*!< address of next descriptor                        */
+		
+		struct {
+			uint32_t SIZE						: 13; 	 	/*!< buffer size                                       */
+			uint32_t                : 19;
+		} RX1_b;
+	} RX_1;
+	
+	uint32_t bufAddr;											/*!< buffer address                                    */
+	uint32_t nextDescAddr;								/*!< address of next descriptor                        */
   uint64_t reserved;
-    uint64_t timeStamp;                                     /*!< time stamp while the last segment                 */
+	uint64_t timeStamp;									 	/*!< time stamp while the last segment                 */
 } ETH_RX_DESC;
 
 /**
   * @brief  Read data from phy chip
-    * @param[in] phyAddr Address of phy chip
-    * @param[in] phyReg Address of phy's register to be read
+	* @param[in] phyAddr Address of phy chip
+	* @param[in] phyReg Address of phy's register to be read
   * @retval uint32_t value of phy's register
-    */
+	*/
 uint32_t ETH_PhyRead(uint32_t phyAddr, uint32_t phyReg);
 
 /**
   * @brief  Write data to phy chip
-    * @param[in] phyAddr Address of phy chip
-    * @param[in] phyReg Address of phy's register to be written
-    * @param[in] data Data to be written
+	* @param[in] phyAddr Address of phy chip
+	* @param[in] phyReg Address of phy's register to be written
+	* @param[in] data Data to be written
   * @retval None
-    */
+	*/
 void ETH_PhyWrite(uint32_t phyAddr, uint32_t phyReg, uint32_t data);
 /**
   * @brief  Fills each ETH_InitStruct member with its default value.
@@ -225,188 +225,188 @@ void ETH_StructInit(ETH_InitTypeDef* init);
 /**
   * @brief  Ethernet initialization
   * @note   This function should be called at first before any other interfaces.
-    * @param[in] init A pointer to structure ETH_InitTypeDef
+	* @param[in] init A pointer to structure ETH_InitTypeDef
   * @retval BOOL The bit indicates if ethernet is initialized successfully
-    */
+	*/ 
 BOOL ETH_Init(ETH_InitTypeDef *init);
 
 /**
-  * @brief  Enable or disable ethernet interrupt.
-    * @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
-    * @param[in] Enable The bit indicates if specific interrupts are enable or not
+  * @brief  Enable or disable ethernet interrupt. 
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
+	* @param[in] Enable The bit indicates if specific interrupts are enable or not
   * @retval None
-    */
+	*/ 
 void ETH_ITConfig(uint32_t Int, BOOL enable);
 
 /**
-  * @brief  Check specific interrupts are set or not
-    * @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
+  * @brief  Check specific interrupts are set or not 
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
   * @retval BOOL The bit indicates if specific interrupts are set or not
-    */
+	*/
 BOOL ETH_GetITStatus(uint32_t Int);
 
 /**
   * @brief  Clear specific interrupts
-    * @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
   * @retval None
-    */
+	*/
 void ETH_ClearITPendingBit(uint32_t Int);
 
 /**
   * @brief  Get ethernte MAC address
-    * @param[in] mac A user-allocated buffer to fetch MAC to be read, 6 bytes.
-    * @retval None
-    */
+	* @param[in] mac A user-allocated buffer to fetch MAC to be read, 6 bytes.
+	* @retval None
+	*/
 void ETH_GetMacAddr(uint8_t *mac);
 
 /**
-  * @brief  Set ethernet transmission descriptor ring
-    * @note     Make sure that memory occupied by descriptors should be in physical
-    *                   memory and keep valid before ethernet transmission is finished.
-    * @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node
-    *                   has a 'nextDescAddr' pointed to first node.
+  * @brief  Set ethernet transmission descriptor ring 
+	* @note		Make sure that memory occupied by descriptors should be in physical
+	*					memory and keep valid before ethernet transmission is finished.
+	* @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node 
+	*					has a 'nextDescAddr' pointed to first node.
   * @retval BOOL The bit indicates if valid ring is set
-    */
+	*/
 BOOL ETH_SetTxDescRing(ETH_TX_DESC *ring);
 
 /**
   * @brief  Start ethernet transmission
-    * @param    None
+	* @param	None
   * @retval None
-    */
+	*/
 void ETH_StartTx(void);
 
 /**
   * @brief  Stop ethernet transmission
-    * @param    None
+	* @param	None
   * @retval None
-    */
+	*/
 void ETH_StopTx(void);
 
 /**
   * @brief  Resume ethernet transmission\n
-    *               While ethernet doesn't have enough buffer to transmit data, it will
-    *                   pause and inform users by interrupt 'ETH_INT_TX_BUF_UNAVAI'. Users
-    *                   must call this function to start ethernet again after new buffer
-    *                   prepared.
-    * @param    None
+	* 				While ethernet doesn't have enough buffer to transmit data, it will
+	*					pause and inform users by interrupt 'ETH_INT_TX_BUF_UNAVAI'. Users
+	*					must call this function to start ethernet again after new buffer 
+	*					prepared.
+	* @param	None
   * @retval None
-    */
+	*/
 void ETH_ResumeTx(void);
 
 /**
   * @brief  Get free transmission descriptor\n
-    * @param    None
-  * @retval ETH_TX_DESC* A pointer of free transmission descriptor,
-    *                   NULL if no free descriptor
-    */
+	* @param	None
+  * @retval ETH_TX_DESC* A pointer of free transmission descriptor, 
+	*					NULL if no free descriptor
+	*/
 ETH_TX_DESC *ETH_AcquireFreeTxDesc(void);
 
 /**
   * @brief  Check if a transmission descriptor is free or not
-    * @param[in] desc A pointer of a transmission descriptor
+	* @param[in] desc A pointer of a transmission descriptor
   * @retval BOOL True if the transmission descriptor is free, or flase.
-    */
+	*/
 BOOL ETH_IsFreeTxDesc(ETH_TX_DESC *desc);
 
 /**
   * @brief  Release a transmission descriptor to ethernet\n
-    *                   After users prepared data in the buffer of a free descriptor,
-    *                   They must call this function to change ownership of the
-    *                   descriptor to hardware.
-    * @param[in] desc A pointer of a transmission descriptor
+	*					After users prepared data in the buffer of a free descriptor,
+	*					They must call this function to change ownership of the 
+	*					descriptor to hardware.
+	* @param[in] desc A pointer of a transmission descriptor
   * @retval None
-    */
+	*/
 void ETH_ReleaseTxDesc(ETH_TX_DESC *desc);
 
 /**
   * @brief  Set buffer address of the specific TX descriptor
-    * @param[in] desc A pointer of a transmission descriptor
+	* @param[in] desc A pointer of a transmission descriptor
   * @param[in] bufAddr buffer address to be sent
   * @retval None
-    */
+	*/
 void ETH_SetTxDescBufAddr(ETH_TX_DESC *desc, uint32_t bufAddr);
 
 /**
   * @brief  Get buffer address of the specific TX descriptor
-    * @param[in] desc A pointer of a transmission descriptor
+	* @param[in] desc A pointer of a transmission descriptor
   * @retval uint32_t buffer address to be gotten
-    */
+	*/
 uint32_t ETH_GetTxDescBufAddr(ETH_TX_DESC *desc);
 
 /**
   * @brief  Set ethernet receive descriptor ring
-    * @note     Make sure that memory occupied by descriptors should be in physical
-    *                   memory and keep valid before ethernet receive is finished.
-    * @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node
-    *                   has a 'nextDescAddr' pointed to first node.
+	* @note		Make sure that memory occupied by descriptors should be in physical
+	*					memory and keep valid before ethernet receive is finished.
+	* @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node 
+	*					has a 'nextDescAddr' pointed to first node.
   * @retval BOOL The bit indicates if valid ring is set
-    */
+	*/
 BOOL ETH_SetRxDescRing(ETH_RX_DESC *ring);
 
 /**
   * @brief  Start ethernet receive
-    * @param    None
+	* @param	None
   * @retval None
-    */
+	*/
 void ETH_StartRx(void);
 
 /**
   * @brief  Stop ethernet receive
-    * @param    None
+	* @param	None
   * @retval None
-    */
+	*/
 void ETH_StopRx(void);
 
 /**
   * @brief  Resume ethernet receive\n
-    *               While ethernet doesn't have enough buffer to receive data, it will
-    *                   pause and inform users by interrupt 'ETH_INT_RX_BUF_UNAVAI'. Users
-    *                   must call this function to start ethernet again after new buffer
-    *                   prepared.
-    * @param    None
+	* 				While ethernet doesn't have enough buffer to receive data, it will
+	*					pause and inform users by interrupt 'ETH_INT_RX_BUF_UNAVAI'. Users
+	*					must call this function to start ethernet again after new buffer 
+	*					prepared.
+	* @param	None
   * @retval None
-    */
+	*/
 void ETH_ResumeRx(void);
 
 /**
   * @brief  Get the free descriptor which contains received data\n
-    * @param    None
-  * @retval ETH_RX_DESC* A pointer of free receive descriptor,
-    *                   NULL if no free descriptor
-    */
+	* @param	None
+  * @retval ETH_RX_DESC* A pointer of free receive descriptor, 
+	*					NULL if no free descriptor
+	*/
 ETH_RX_DESC *ETH_AcquireFreeRxDesc(void);
 
 /**
   * @brief  Check if a receive descriptor is free or not
-    * @param[in] desc A pointer of a receive descriptor
+	* @param[in] desc A pointer of a receive descriptor
   * @retval BOOL True if the receive descriptor is free, or flase.
-    */
+	*/
 BOOL ETH_IsFreeRxDesc(ETH_RX_DESC *desc);
 
 /**
   * @brief  Release a receive descriptor to ethernet\n
-    *                   After users handled data in the buffer of a free descriptor,
-    *                   They must call this function to change ownership of the
-    *                   descriptor to hardware.
-    * @param[in] desc A pointer of a transmission descriptor
+	*					After users handled data in the buffer of a free descriptor,
+	*					They must call this function to change ownership of the 
+	*					descriptor to hardware.
+	* @param[in] desc A pointer of a transmission descriptor
   * @retval None
-    */
+	*/
 void ETH_ReleaseRxDesc(ETH_RX_DESC *desc);
 
 /**
   * @brief  Set buffer address of the specific RX descriptor
-    * @param[in] desc A pointer of a receive descriptor
+	* @param[in] desc A pointer of a receive descriptor
   * @param[in] bufAddr buffer address to be received
   * @retval None
-    */
+	*/
 void ETH_SetRxDescBufAddr(ETH_RX_DESC *desc, uint32_t bufAddr);
 
 /**
   * @brief  Get buffer address of the specific RX descriptor
-    * @param[in] desc A pointer of a receive descriptor
+	* @param[in] desc A pointer of a receive descriptor
   * @retval uint32_t buffer address to be gotten
-    */
+	*/
 uint32_t ETH_GetRxDescBufAddr(ETH_RX_DESC *desc);
 
 #ifdef __cplusplus

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_flash.h

@@ -1,29 +1,29 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_flash.h
-    *
-    * @brief    CMEM7 flash controller source file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_flash.h
+	*
+	* @brief    CMEM7 flash controller source file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #ifndef __CMEM7_FLASH_H
 #define __CMEM7_FLASH_H
 
@@ -37,15 +37,15 @@
 /** @defgroup FLASH_PROTECT_MODE
   * @{
   */
-#define FLASH_PROTECT_MODE_SW           0       /*!< The Status Register can be written to after a Write
+#define FLASH_PROTECT_MODE_SW           0       /*!< The Status Register can be written to after a Write 
                                                      Enable command.(Default) */
-#define FLASH_PROTECT_MODE_HW           1       /*!< WP pin decides if the Status Register can be written
+#define FLASH_PROTECT_MODE_HW           1       /*!< WP pin decides if the Status Register can be written 
                                                      WP#=0, the Status Register locked
-                                                                                                       WP#=1, the Status Register is unlocked and can be written to
+																									   WP#=1, the Status Register is unlocked and can be written to
                                                      after a Write Enable command */
-#define FLASH_PROTECT_MODE_POWERDOWN    2               /*!< Status Register is protected and can not be written to again
-                                                     until the next Power-Down, Power-Up cycle */
-#define FLASH_PROTECT_MODE_OTP          3       /*!< Status Register is permanently protected */
+#define FLASH_PROTECT_MODE_POWERDOWN    2				/*!< Status Register is protected and can not be written to again
+                                                     until the next Power-Down, Power-Up cycle */	
+#define FLASH_PROTECT_MODE_OTP          3       /*!< Status Register is permanently protected */	
 
 #define IS_FLASH_PROTECT_MODE(MODE)     (((MODE) == FLASH_PROTECT_MODE_SW) || \
                                          ((MODE) == FLASH_PROTECT_MODE_HW) || \
@@ -80,21 +80,21 @@
 #define IS_FLASH_PROTECT_REGION(REGION) (((REGION) == FLASH_PROTECT_REGION_NONE) || \
                                          ((REGION) == FLASH_PROTECT_REGION_UP_64K) || \
                                          ((REGION) == FLASH_PROTECT_REGION_UP_128K) || \
-                                                                                 ((REGION) == FLASH_PROTECT_REGION_UP_256K) || \
-                                                                                 ((REGION) == FLASH_PROTECT_REGION_UP_512K) || \
-                                                                                 ((REGION) == FLASH_PROTECT_REGION_LOW_64K) || \
+																				 ((REGION) == FLASH_PROTECT_REGION_UP_256K) || \
+																				 ((REGION) == FLASH_PROTECT_REGION_UP_512K) || \
+																				 ((REGION) == FLASH_PROTECT_REGION_LOW_64K) || \
                                          ((REGION) == FLASH_PROTECT_REGION_LOW_128K) || \
-                                                                                 ((REGION) == FLASH_PROTECT_REGION_LOW_256K) || \
-                                                                                 ((REGION) == FLASH_PROTECT_REGION_LOW_512K) || \
-                                                                                 ((REGION) == FLASH_PROTECT_REGION_ALL) || \
+																				 ((REGION) == FLASH_PROTECT_REGION_LOW_256K) || \
+																				 ((REGION) == FLASH_PROTECT_REGION_LOW_512K) || \
+																				 ((REGION) == FLASH_PROTECT_REGION_ALL) || \
                                          ((REGION) == FLASH_PROTECT_REGION_UP_4K) || \
                                          ((REGION) == FLASH_PROTECT_REGION_UP_8K) || \
-                                                                                 ((REGION) == FLASH_PROTECT_REGION_UP_16K) || \
-                                                                                 ((REGION) == FLASH_PROTECT_REGION_UP_32K) || \
-                                                                                 ((REGION) == FLASH_PROTECT_REGION_LOW_4K) || \
+																				 ((REGION) == FLASH_PROTECT_REGION_UP_16K) || \
+																				 ((REGION) == FLASH_PROTECT_REGION_UP_32K) || \
+																				 ((REGION) == FLASH_PROTECT_REGION_LOW_4K) || \
                                          ((REGION) == FLASH_PROTECT_REGION_LOW_8K) || \
-                                                                                 ((REGION) == FLASH_PROTECT_REGION_LOW_16K) || \
-                                                                                 ((REGION) == FLASH_PROTECT_REGION_LOW_32K))
+																				 ((REGION) == FLASH_PROTECT_REGION_LOW_16K) || \
+																				 ((REGION) == FLASH_PROTECT_REGION_LOW_32K))
 /**
   * @}
   */
@@ -110,96 +110,96 @@
 #define IS_FLASH_READ_MODE(MODE)       (((MODE) == FLASH_READ_MODE_NORMAL) || \
                                         ((MODE) == FLASH_READ_MODE_FAST) || \
                                         ((MODE) == FLASH_READ_MODE_FAST_DUAL) || \
-                                                                                ((MODE) == FLASH_READ_MODE_FAST_QUAD))
+																				((MODE) == FLASH_READ_MODE_FAST_QUAD))																								
 /**
   * @}
   */
 
 /**
   * @brief  UART initialization structure
-    */
+	*/ 
 typedef struct
 {
   uint8_t FLASH_ClockDividor;       /*!< flash clock dividor, 2 in n times */
-    uint8_t FLASH_ProtectMode;        /*!< Status Register protection mode */
-    uint8_t FLASH_ProtectRegion;      /*!< flash protection region */
-    BOOL FLASH_QuadEnable;            /*!< if allows Quad operation */
-    void (*FLASH_Wait)(void);         /*!< When the former read or write operation is excuting,
-                                           Flash has to call a callback to wait it finish.
-                                           If null, Flash will wait forever until finish */
+	uint8_t FLASH_ProtectMode;        /*!< Status Register protection mode */
+	uint8_t FLASH_ProtectRegion;      /*!< flash protection region */
+	BOOL FLASH_QuadEnable;            /*!< if allows Quad operation */
+	void (*FLASH_Wait)(void);         /*!< When the former read or write operation is excuting, 
+	                                       Flash has to call a callback to wait it finish. 
+	                                       If null, Flash will wait forever until finish */
 } FLASH_InitTypeDef;
 
 /**
   * @brief  flash initialization
   * @note   This function should be called at first before any other interfaces.
-    *                   Users should make sure that doesn't erase or write data in a
-    *                   write-protected region.
-    * @param[in] init A pointer to structure FLASH_InitTypeDef
+	*					Users should make sure that doesn't erase or write data in a 
+	*					write-protected region.
+	* @param[in] init A pointer to structure FLASH_InitTypeDef
   * @retval None
-    */
+	*/ 
 void FLASH_Init(FLASH_InitTypeDef* init);
 
 /**
-  * @brief  Get flash status
+  * @brief  Get flash status 
   * @param[out] ProtectMode flash protect mode, ref as @ref FLASH_PROTECT_MODE
   * @param[out] ProtectRegion flash protect region, ref as @ref FLASH_PROTECT_REGION
-    * @param[out] QuadEnable quad speed mode enable bit
-    * @retval None
-    */
+	* @param[out] QuadEnable quad speed mode enable bit
+	* @retval None
+	*/ 
 void FLASH_GetStatus(uint8_t* ProtectMode, uint8_t* ProtectRegion, BOOL* QuadEnable);
 
 /**
   * @brief  Erase a sector, which is 4K bytes large.
   * @param[in] addr Start address of a sector
-    * @retval None
-    */
+	* @retval None
+	*/
 void FLASH_EraseSector(uint32_t addr);
 
 /**
   * @brief  Erase a block, which is 32K bytes large.
   * @param[in] addr Start address of a block
-    * @retval None
-    */
+	* @retval None
+	*/
 void FLASH_Erase32kBlock(uint32_t addr);
 
 /**
   * @brief  Erase a block, which is 64K bytes large.
   * @param[in] addr Start address of a block
-    * @retval None
-    */
+	* @retval None
+	*/
 void FLASH_Erase64kBlock(uint32_t addr);
 
 /**
   * @brief  Erase all chip
-  * @param  None
-    * @retval None
-    */
+  * @param	None
+	* @retval None
+	*/
 void FLASH_EraseChip(void);
 
 /**
   * @brief  Enable flash power down mode or not
   * @param[in] enable The bit indicates if flash power down mode is enable or not
-    * @retval None
-    */
+	* @retval None
+	*/
 void FLASH_EnableDeepPowerDown(BOOL enable);
 
 /**
   * @brief  Read data from flash
-    * @param[in] ReadMode Normal or fast read, ref as @ref FLASH_READ_MODE
-    * @param[in] addr Start address to be read
-    * @param[in] size Expected data size to be read
-    * @param[out] data A user-allocated buffer to fetch data to be read
+	* @param[in] ReadMode Normal or fast read, ref as @ref FLASH_READ_MODE
+	* @param[in] addr Start address to be read
+	* @param[in] size Expected data size to be read
+	* @param[out] data A user-allocated buffer to fetch data to be read
   * @retval None
-    */
+	*/
 void FLASH_Read(uint8_t ReadMode, uint32_t addr, uint16_t size, uint8_t* data);
 
 /**
   * @brief  Write data to flash
-    * @param[in] addr Start address to be read
-    * @param[in] size Expected data size to be read
-    * @param[out] data A pointer to the data to be written
+	* @param[in] addr Start address to be read
+	* @param[in] size Expected data size to be read
+	* @param[out] data A pointer to the data to be written
   * @retval None
-    */
+	*/
 void FLASH_Write(uint32_t addr, uint16_t size, uint8_t* data);
 
 

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_gpio.h

@@ -1,29 +1,29 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_gpio.h
-    *
-    * @brief    CMEM7 GPIO header file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_gpio.h
+	*
+	* @brief    CMEM7 GPIO header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #ifndef __CMEM7_GPIO_H
 #define __CMEM7_GPIO_H
 
@@ -38,7 +38,7 @@
   * @{
   */
 typedef enum {
-    GPIO_GROUP_GPIO,
+	GPIO_GROUP_GPIO,
 } GPIO_GROUP;
 
 #define IS_GPIO_GROUP(GROUP)  (((GROUP) == GPIO_GROUP_GPIO))
@@ -50,105 +50,105 @@ typedef enum {
   * @{
   */
 typedef enum {
-    GPIO_PWM_CHANNEL_GPIO_31,
+	GPIO_PWM_CHANNEL_GPIO_31,
 } GPIO_PWM_CHANNEL;
-
+        
 #define IS_GPIO_PWM_CHANNEL(CHANNEL)  (((CHANNEL) == GPIO_PWM_CHANNEL_GPIO_31))
 /**
   * @}
   */
-
+	
 /**
   * @brief  GPIO initialization
   * @note   This function should be called at first before any other interfaces.
-    * @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
-    * @param[in] PositiveTrigger Positive edge interrupt trigger if true, or negative edge
+	* @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
+	* @param[in] PositiveTrigger Positive edge interrupt trigger if true, or negative edge
   * @retval None
-    */
+	*/ 	
 void GPIO_Init(uint8_t Group, uint32_t PositiveTrigger);
 
 /**
-  * @brief  Enable or disable GPIO output in the specific group.
-    * @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
-    * @param[in] Enable each bit indicates if the corresponding GPIO pin
-    *                       in the specific GPIO group is enable or not
+  * @brief  Enable or disable GPIO output in the specific group. 
+	* @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
+	* @param[in] Enable each bit indicates if the corresponding GPIO pin 
+	*						in the specific GPIO group is enable or not
   * @retval None
-    */
+	*/ 
 void GPIO_EnableOutput(uint8_t Group, uint32_t Enable);
 
 /**
-  * @brief  Enable or disable GPIO interrupt in the specific group.
-    * @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
-    * @param[in] Enable each bit indicates if the corresponding GPIO pin interrupt
-    *                       in the specific GPIO group is enable or not
+  * @brief  Enable or disable GPIO interrupt in the specific group. 
+	* @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
+	* @param[in] Enable each bit indicates if the corresponding GPIO pin interrupt 
+	*						in the specific GPIO group is enable or not
   * @retval None
-    */
+	*/ 
 void GPIO_EnableInt(uint8_t Group, uint32_t Enable);
 
 /**
-  * @brief  Check specific interrupts are set or not
-    * @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
-    * @retval uint32_t each bit indicates if the corresponding GPIO pin interrupt
-    *                   in the specific GPIO group is set or not
-    */
+  * @brief  Check specific interrupts are set or not 
+	* @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
+	* @retval uint32_t each bit indicates if the corresponding GPIO pin interrupt 
+	*					in the specific GPIO group is set or not
+	*/
 uint32_t GPIO_GetIntStatus(uint8_t Group);
 
 /**
-  * @brief  Clear GPIO interrupt in the specific group.
-    * @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
-    * @param[in] Clear each bit indicates if the corresponding GPIO pin interrupt
-    *                       in the specific GPIO group is clear or not
+  * @brief  Clear GPIO interrupt in the specific group. 
+	* @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
+	* @param[in] Clear each bit indicates if the corresponding GPIO pin interrupt 
+	*						in the specific GPIO group is clear or not
   * @retval None
-    */
+	*/ 
 void GPIO_ClearInt(uint8_t Group, uint32_t Clear);
 
 /**
   * @brief  Get value of each GPIO pin in the specific group
-    * @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
-    * @retval uint32_t each bit indicates value of the corresponding GPIO pin
-    *                   in the specific GPIO group
-    */
+	* @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
+	* @retval uint32_t each bit indicates value of the corresponding GPIO pin 
+	*					in the specific GPIO group
+	*/
 uint32_t GPIO_Read(uint8_t Group);
 
 /**
   * @brief  Set value of each GPIO pin in the specific group
-    * @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
-    * @param[in] Unmask each bit indicates value of the corresponding GPIO pin
-    *                        in the specific GPIO group is set or not
-    * @param[in] data each bit indicates value of the corresponding GPIO pin
-    *                        in the specific GPIO group to be set
+	* @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
+	* @param[in] Unmask each bit indicates value of the corresponding GPIO pin 
+	*						 in the specific GPIO group is set or not
+	* @param[in] data each bit indicates value of the corresponding GPIO pin
+	*						 in the specific GPIO group to be set
   * @retval None
-    */
+	*/ 
 void GPIO_Write(uint8_t Group, uint32_t Unmask, uint32_t data);
 
 /**
   * @brief  Initialize PWM for the specific GPIO pin
-    * @note     It can work before call GPIO_EnableOutput for the specific GPIO pin
-    * @param[in] Channel PWM channel, which is a value of @ref GPIO_PWM_CHANNEL
-    * @param[in] HighLevelNanoSecond Nanosecond which high level lasts
-    * @param[in] LowLevelNanoSecond Nanosecond which low level lasts
+	* @note		It can work before call GPIO_EnableOutput for the specific GPIO pin
+	* @param[in] Channel PWM channel, which is a value of @ref GPIO_PWM_CHANNEL
+	* @param[in] HighLevelNanoSecond Nanosecond which high level lasts 
+	* @param[in] LowLevelNanoSecond Nanosecond which low level lasts 
   * @retval None
-    * @see      GPIO_EnableOutput
-    */
+	* @see		GPIO_EnableOutput
+	*/ 
 void GPIO_InitPwm(uint8_t Channel, uint32_t HighLevelNanoSecond, uint32_t LowLevelNanoSecond);
 
 /**
-  * @brief  Enable or disable GPIO PWM in the specific channel.
-    *   @param[in] Channel PWM channel, which is a value of @ref GPIO_PWM_CHANNEL
-    * @param[in] Enable The bit indicates if the specific channel is enable or not
+  * @brief  Enable or disable GPIO PWM in the specific channel. 
+	*	@param[in] Channel PWM channel, which is a value of @ref GPIO_PWM_CHANNEL
+	* @param[in] Enable The bit indicates if the specific channel is enable or not
   * @retval None
-    */
+	*/ 
 void GPIO_EnablePwm(uint8_t Channel, BOOL Enable);
 
 
 
 /**
   xjf 20150324
-
+  
 **/
 void GPIO_SetBits(uint32_t mask);
 void GPIO_clrBits(uint32_t mask);
-uint32_t GPIO_getBits(uint32_t mask);
+uint32_t GPIO_getBits(uint32_t mask); 
 
 
 #ifdef __cplusplus

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_i2c.h

@@ -1,29 +1,29 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_i2c.h
-    *
-    * @brief    CMEM7 I2C header file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_i2c.h
+	*
+	* @brief    CMEM7 I2C header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #ifndef __CMEM7_I2C_H
 #define __CMEM7_I2C_H
 
@@ -62,18 +62,18 @@
 
 /** @defgroup I2C_INT
   * @{
-  */
-#define I2C_INT_RX_FIFO_NOT_EMPTY      0x00000004       /*!< Can't be clear but read FIFO */
+  */			
+#define I2C_INT_RX_FIFO_NOT_EMPTY      0x00000004 		/*!< Can't be clear but read FIFO */
 #define I2C_INT_RD_REQUEST             0x00000020     /*!< Slave was requested to send data */
 #define I2C_INT_TX_ABORT               0x00000040     /*!< Error while sending data */
 #define I2C_INT_RX_DONE                0x00000080     /*!< Slave sent all requested data */
 #define I2C_INT_TX_DONE                0x00000100     /*!< Master accomplish to send all data */
 
 #define I2C_INT_ALL                    (I2C_INT_RX_FIFO_NOT_EMPTY | \
-                                                                                I2C_INT_RD_REQUEST | \
-                                                                                I2C_INT_TX_ABORT | \
-                                                                                I2C_INT_RX_DONE | \
-                                                                                I2C_INT_TX_DONE)
+																				I2C_INT_RD_REQUEST | \
+																				I2C_INT_TX_ABORT | \
+																				I2C_INT_RX_DONE | \
+																				I2C_INT_TX_DONE)
 
 #define IS_I2C_INT(INT)                (((INT) != 0) && (((INT) & ~I2C_INT_ALL) == 0))
 /**
@@ -83,17 +83,17 @@
 /** @defgroup I2C_STATUS
   * @{
   */
-#define I2C_STATUS_RX_FIFO_NOT_EMPTY   0x00200000       /*!< Can't be clear but read FIFO */
+#define I2C_STATUS_RX_FIFO_NOT_EMPTY   0x00200000 		/*!< Can't be clear but read FIFO */
 #define I2C_STATUS_RD_REQUEST          0x01000000     /*!< Slave was requested to send data */
 #define I2C_STATUS_TX_ABORT            0x02000000     /*!< Error while sending data */
 #define I2C_STATUS_RX_DONE             0x04000000     /*!< Slave sent all requested data */
 #define I2C_STATUS_TX_DONE             0x08000000     /*!< Master accomplish to send all data */
 
 #define I2C_STATUS_ALL                 (I2C_STATUS_RX_FIFO_NOT_EMPTY | \
-                                                                                I2C_STATUS_RD_REQUEST | \
-                                                                                I2C_STATUS_TX_ABORT | \
-                                                                                I2C_STATUS_RX_DONE | \
-                                                                                I2C_STATUS_TX_DONE)
+																				I2C_STATUS_RD_REQUEST | \
+																				I2C_STATUS_TX_ABORT | \
+																				I2C_STATUS_RX_DONE | \
+																				I2C_STATUS_TX_DONE)
 
 #define IS_I2C_STATUS(STATUS)          (((STATUS) != 0) && (((STATUS) & ~I2C_STATUS_ALL) == 0))
 /**
@@ -102,141 +102,141 @@
 
 /**
   * @brief  I2C timing structure
-    */
+	*/
 typedef struct
 {
   uint32_t I2C_Freq;                /*!< I2C frquency */
 
-    uint16_t I2C_TsuDat;              /*!< nano second of TSU:DAT */
-  uint16_t I2C_Tsetup;              /*!< nano second of THD:STA and TSU:STO */
-  uint16_t I2C_Tbuf;                /*!< nano second of TBUF */
-    uint16_t I2C_TsuSta;              /*!< nano second of TSU:STA */
-
-    BOOL I2C_SdaFilterEn;             /*!< enabled flag of SDA filter */
-    uint8_t I2C_SdaFilterSpike;       /*!< spikes of SDA filter */
-    BOOL I2C_SclFilterEn;             /*!< enabled flag of SCL filter */
-    uint8_t I2C_SclFilterSpike;       /*!< spikes of SCL filter */
-
+	uint16_t I2C_TsuDat;              /*!< nano second of TSU:DAT */
+  uint16_t I2C_Tsetup;              /*!< nano second of THD:STA and TSU:STO */ 
+  uint16_t I2C_Tbuf;                /*!< nano second of TBUF */       	
+	uint16_t I2C_TsuSta;              /*!< nano second of TSU:STA */ 
+	
+	BOOL I2C_SdaFilterEn;             /*!< enabled flag of SDA filter */
+	uint8_t I2C_SdaFilterSpike;       /*!< spikes of SDA filter */
+	BOOL I2C_SclFilterEn;             /*!< enabled flag of SCL filter */
+	uint8_t I2C_SclFilterSpike;       /*!< spikes of SCL filter */
+	
 } I2C_InitTimingDef;
 
 /**
   * @brief  I2C initialization structure
-    */
+	*/
 typedef struct
 {
   uint8_t I2C_Mode;                 /*!< Specifies the I2C mode.
                                          This parameter can be a value of @ref I2C_mode */
-    uint8_t I2C_AddressWidth;         /*!< 7- or 10-bits width address, ref as @ref I2C_ADDR_WIDTH */
-    uint8_t I2C_Address;              /*!< 7- or 10-bits address */
-    I2C_InitTimingDef* timing;        /*!< timing structure, null if don't set */
+	uint8_t I2C_AddressWidth;         /*!< 7- or 10-bits width address, ref as @ref I2C_ADDR_WIDTH */
+	uint8_t I2C_Address;              /*!< 7- or 10-bits address */
+	I2C_InitTimingDef* timing;        /*!< timing structure, null if don't set */		
 } I2C_InitTypeDef;
 
 /**
   * @brief  I2C initialization
   * @note   This function should be called at first before any other interfaces.
-    * @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
-    * @param[in] init A pointer to structure I2C_InitTypeDef
+	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+	* @param[in] init A pointer to structure I2C_InitTypeDef
   * @retval None
-    */
+	*/ 
 void I2C_Init(I2C0_Type* I2Cx, I2C_InitTypeDef* I2C_Init);
 
 /**
-  * @brief  Enable or disable I2C.
-    * @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
-    * @param[in] Enable The bit indicates if the specific I2C is enable or not
+  * @brief  Enable or disable I2C. 
+	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+	* @param[in] Enable The bit indicates if the specific I2C is enable or not
   * @retval None
-    */
+	*/ 
 void I2C_Enable(I2C0_Type* I2Cx, BOOL enable);
 
 /**
-  * @brief  Enable or disable I2C interrupt.
-    * @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
-    * @param[in] Int interrupt mask bits, which can be the combination of @ref I2C_Int
-    * @param[in] Enable The bit indicates if specific interrupts are enable or not
+  * @brief  Enable or disable I2C interrupt. 
+	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref I2C_Int
+	* @param[in] Enable The bit indicates if specific interrupts are enable or not
   * @retval None
-    */
+	*/ 
 void I2C_EnableInt(I2C0_Type* I2Cx, uint32_t Int, BOOL enable);
 
 /**
-  * @brief  Check specific interrupts are set or not
-    * @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
-    * @param[in] Int interrupt mask bits, which can be the combination of @ref I2C_Int
+  * @brief  Check specific interrupts are set or not 
+	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref I2C_Int
   * @retval BOOL The bit indicates if specific interrupts are enable or not
-    */
+	*/
 BOOL I2C_GetIntStatus(I2C0_Type* I2Cx, uint32_t Int);
 
 /**
   * @brief  Clear specific interrupts
-    * @note   Specific interrupt clear will clear correspective status as well
-    * @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
-    * @param[in] Int interrupt mask bits, which can be the combination of @ref I2C_Int
+	* @note   Specific interrupt clear will clear correspective status as well
+	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref I2C_Int
   * @retval None
-    */
+	*/
 void I2C_ClearInt(I2C0_Type* I2Cx, uint32_t Int);
 
 /**
-  * @brief  Check specific status are set or not
-    * @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
-    * @param[in] Status Status mask bits, which can be the combination of @ref I2C_STATUS
+  * @brief  Check specific status are set or not 
+	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+	* @param[in] Status Status mask bits, which can be the combination of @ref I2C_STATUS
   * @retval BOOL The bit indicates if specific status are set or not
-    */
+	*/
 BOOL I2C_GetStatus(I2C0_Type* I2Cx, uint32_t Status);
 
 /**
   * @brief  Clear specific status
-    * @note   Specific status clear will clear correspective interrupt as well
-    * @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
-    * @param[in] Status Status mask bits, which can be the combination of @ref I2C_STATUS
+	* @note   Specific status clear will clear correspective interrupt as well
+	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+	* @param[in] Status Status mask bits, which can be the combination of @ref I2C_STATUS
   * @retval None
-    */
+	*/
 void I2C_ClearStatus(I2C0_Type* I2Cx, uint32_t Status);
 
 /**
   * @brief  I2C send read request in master mode
-    * @note   Users must call I2C_StopReq between 2 requests
-    * @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
-    * @param[in] size Expected data size to be read
+	* @note   Users must call I2C_StopReq between 2 requests
+	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+	* @param[in] size Expected data size to be read
   * @retval BOOL The bit indicates if read request to be sent is valid
-    * @see      I2C_StopReq
-    */
+	* @see		I2C_StopReq
+	*/
 BOOL I2C_MasterReadReq(I2C0_Type* I2Cx, uint8_t size);
 
 /**
   * @brief  Read data from I2C
-    * @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
-    * @param[in] size Expected data size to be read
-    * @param[out] Data A user-allocated buffer to fetch data to be read
+	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+	* @param[in] size Expected data size to be read
+	* @param[out] Data A user-allocated buffer to fetch data to be read
   * @retval uint8_t Actual read data size
-    */
+	*/
 uint8_t I2C_ReadFifo(I2C0_Type* I2Cx, uint8_t size, uint8_t* data);
 
 /**
   * @brief  I2C send write request in master or slave mode
-    * @note   Users must call I2C_StopReq between 2 requests
-    * @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
-    * @param[in] size Expected data size to be written, includes the first data
-    * @param[in] firstData The first data to be written
+	* @note   Users must call I2C_StopReq between 2 requests
+	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+	* @param[in] size Expected data size to be written, includes the first data
+	* @param[in] firstData The first data to be written
   * @retval BOOL The bit indicates if write request to be sent is valid
-    * @see      I2C_StopReq
-    */
+	* @see		I2C_StopReq
+	*/
 BOOL I2C_WriteReq(I2C0_Type* I2Cx, uint8_t size, uint8_t firstData);
 
 /**
   * @brief  Write data to I2C
-    * @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
-    * @param[in] size Expected data size to be written
-    * @param[in] Data A pointer to the data to be written
+	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+	* @param[in] size Expected data size to be written
+	* @param[in] Data A pointer to the data to be written
   * @retval uint8_t Actual written data size
-    */
+	*/
 uint8_t I2C_WriteFifo(I2C0_Type* I2Cx, uint8_t size, uint8_t* data);
 
 /**
   * @brief  I2C stop request
-    * @note   Users must call I2C_StopReq between 2 requests
-    * @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
-    * @retval BOOL The bit indicates if request is stopped.
-    * @see      I2C_MasterReadReq I2C_WriteReq
-    */
+	* @note   Users must call I2C_StopReq between 2 requests
+	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
+	* @retval BOOL The bit indicates if request is stopped.
+	* @see		I2C_MasterReadReq I2C_WriteReq 
+	*/
 BOOL I2C_StopReq(I2C0_Type* I2Cx);
 
 #ifdef __cplusplus

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_includes.h

@@ -1,28 +1,28 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_includes.h
-    *
-    * @brief    CMEM7 includes file, easy to use CMEM7 library
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
+	*****************************************************************************
+	* @file     cmem7_includes.h
+	*
+	* @brief    CMEM7 includes file, easy to use CMEM7 library
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
 
 #ifndef __CMEM7_INCLUDES_H
 #define __CMEM7_INCLUDES_H
@@ -33,84 +33,84 @@
 
 #include "cmem7_conf.h"
 #include "cmem7_it.h"
-
+	 
 #ifdef _ADC
-    #include "cmem7_adc.h"
+	#include "cmem7_adc.h"
 #endif
-
+	 
 #ifdef _AES
-    #include "cmem7_aes.h"
+	#include "cmem7_aes.h"
 #endif
-
+	 
 #ifdef _CAN
-    #include "cmem7_can.h"
+	#include "cmem7_can.h"
 #endif
-
+	 
 #ifdef _DDR
-    #include "cmem7_ddr.h"
+	#include "cmem7_ddr.h"
 #endif
-
+	 
 #ifdef _DMA
-    #include "cmem7_dma.h"
+	#include "cmem7_dma.h"
 #endif
-
+	 
 #ifdef _EFUSE
-    #include "cmem7_efuse.h"
+	#include "cmem7_efuse.h"
 #endif
-
+	 
 #ifdef _ETH
-    #include "cmem7_eth.h"
+	#include "cmem7_eth.h"
 #endif
-
+	 
 #ifdef _FLASH
-    #include "cmem7_flash.h"
+	#include "cmem7_flash.h"
 #endif
-
+	 
 #ifdef _GPIO
-    #include "cmem7_gpio.h"
+	#include "cmem7_gpio.h"
 #endif
-
+	 
 #ifdef _I2C
-    #include "cmem7_i2c.h"
+	#include "cmem7_i2c.h"
 #endif
-
+	 
 #ifdef _MISC
-    #include "cmem7_misc.h"
+	#include "cmem7_misc.h"
 #endif
-
+	 
 #ifdef _RTC
-    #include "cmem7_rtc.h"
+	#include "cmem7_rtc.h"
 #endif
-
+	 
 #ifdef _SPI
-    #include "cmem7_spi.h"
+	#include "cmem7_spi.h"
 #endif
-
+	 
 #ifdef _TIM
-    #include "cmem7_tim.h"
+	#include "cmem7_tim.h"
 #endif
-
+	 
 #ifdef _UART
-    #include "cmem7_uart.h"
+	#include "cmem7_uart.h"
 #endif
 
 #ifdef _USB
-    #include "cmem7_usb.h"
+	#include "cmem7_usb.h"
 #endif
 
 #ifdef _WDG
-    #include "cmem7_wdg.h"
+	#include "cmem7_wdg.h"
 #endif
 
 
 #ifdef _MARVELL
   #include <marvel_98dx242.h>
-    #include <s24g_i2c.h>
-#endif
-
+	#include <s24g_i2c.h>
+#endif	
+	
 #ifdef _IP1826D
   #include <ip1826d_v00.h>
-#endif
+#endif	
 
 #ifdef __cplusplus
 }

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_misc.h

@@ -1,29 +1,29 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_misc.h
-    *
-    * @brief    CMEM7 miscellaneous header file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_misc.h
+	*
+	* @brief    CMEM7 miscellaneous header file
+	* 
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #ifndef __CMEM7_MISC_H
 #define __CMEM7_MISC_H
 
@@ -36,36 +36,36 @@
 
 /**
   * @brief  NVIC initialization structure
-    */
+	*/
 /**
-@code
-    The table below gives the allowed values of the pre-emption priority and subpriority according
-    to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
-    ============================================================================================================================
-        NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description
-    ============================================================================================================================
-     NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for pre-emption priority
-                                                 |                                   |                             |   4 bits for subpriority
-    ----------------------------------------------------------------------------------------------------------------------------
-     NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for pre-emption priority
-                                                 |                                   |                             |   3 bits for subpriority
-    ----------------------------------------------------------------------------------------------------------------------------
-     NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for pre-emption priority
-                                                 |                                   |                             |   2 bits for subpriority
-    ----------------------------------------------------------------------------------------------------------------------------
-     NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for pre-emption priority
-                                                 |                                   |                             |   1 bits for subpriority
-    ----------------------------------------------------------------------------------------------------------------------------
-     NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for pre-emption priority
-                                                 |                                   |                             |   0 bits for subpriority
-    ============================================================================================================================
+@code  
+	The table below gives the allowed values of the pre-emption priority and subpriority according
+	to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+	============================================================================================================================
+		NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description
+	============================================================================================================================
+	 NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for pre-emption priority
+												 |                                   |                             |   4 bits for subpriority
+	----------------------------------------------------------------------------------------------------------------------------
+	 NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for pre-emption priority
+												 |                                   |                             |   3 bits for subpriority
+	----------------------------------------------------------------------------------------------------------------------------    
+	 NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for pre-emption priority
+												 |                                   |                             |   2 bits for subpriority
+	----------------------------------------------------------------------------------------------------------------------------    
+	 NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for pre-emption priority
+												 |                                   |                             |   1 bits for subpriority
+	----------------------------------------------------------------------------------------------------------------------------    
+	 NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for pre-emption priority
+												 |                                   |                             |   0 bits for subpriority                       
+	============================================================================================================================
 @endcode
-    */
-
+	*/
+	
 typedef struct
 {
   uint8_t NVIC_IRQChannel;                    /*!< Specifies the IRQ channel to be enabled or disabled.
-                                                   This parameter can be a value of @ref IRQn_Type
+                                                   This parameter can be a value of @ref IRQn_Type 
                                                    (For the complete Capital-micro Devices IRQ Channels list, please
                                                     refer to cmem7.h file) */
 
@@ -78,10 +78,10 @@ typedef struct
                                                    between 0 and 15 as described in the table @ref NVIC_Priority_Table */
 
   BOOL NVIC_IRQChannelCmd;                    /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
-                                                   will be enabled or disabled.
-                                                   This parameter can be set either to ENABLE or DISABLE */
+                                                   will be enabled or disabled. 
+                                                   This parameter can be set either to ENABLE or DISABLE */   
 } NVIC_InitTypeDef;
-
+ 
 
 /** @defgroup NVIC_VectTab
   * @{
@@ -132,7 +132,7 @@ typedef struct
 /**
   * @}
   */
-
+	
 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
 
 #define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
@@ -141,7 +141,7 @@ typedef struct
 
 /**
   * @brief  Configures the priority grouping: pre-emption priority and subpriority.
-  * @param  NVIC_PriorityGroup: specifies the priority grouping bits length.
+  * @param  NVIC_PriorityGroup: specifies the priority grouping bits length. 
   *   This parameter can be one of the following values, ref as @ref NVIC_PriorityGroup:
   *     @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
   *                                4 bits for subpriority
@@ -172,7 +172,7 @@ void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
   *   This parameter can be one of the following values, ref as @ref NVIC_VectTab:
   *     @arg NVIC_VectTab_RAM
   *     @arg NVIC_VectTab_FLASH
-  * @param  Offset: Vector Table base offset field. This value must be a multiple
+  * @param  Offset: Vector Table base offset field. This value must be a multiple 
   *         of 0x200.
   * @retval None
   */
@@ -192,70 +192,70 @@ void NVIC_SystemLPConfig(uint8_t LowPowerMode, BOOL NewState);
 
 /**
   * @brief  Memory map from address 'from' to 'address 'to' and open icache or not
-    * @param[in] from address to be mapped from
-    * @param[in] to address to be mapped to
-    * @param[in] isIcacheOn icache is on or off
+	* @param[in] from address to be mapped from
+	* @param[in] to address to be mapped to
+	* @param[in] isIcacheOn icache is on or off
   * @retval None
-    */
+	*/
 void GLB_MMAP(uint32_t from, uint32_t to, BOOL isIcacheOn);
 
 /**
   * @brief  Convert the mapping destination address to source address
-    * @param[in] to address to be mapped to
+	* @param[in] to address to be mapped to
   * @retval uint32_t address to be mapped from
-    */
+	*/
 uint32_t GLB_ConvertToMappingFromAddr(uint32_t to);
 
 /**
   * @brief  Convert the mapping source address to destination address
-    * @param[in] from address to be mapped from
+	* @param[in] from address to be mapped from
   * @retval uint32_t address to be mapped to
-    */
+	*/
 uint32_t GLB_ConvertToMappingToAddr(uint32_t from);
 
 /**
   * @brief  Set NMI irq number, it should be one of @ref IRQn_Type.
-    * @Note     You can assign any valid IRQn_Type to NMI. After that, you will enter NMI
-    *                   interrupt routine if the specific 'irq' occurs. By default, NMI irq number
-    *                   is 0, same as ETH_INT_IRQn
-    * @param[in] irq irq number
+	* @Note		You can assign any valid IRQn_Type to NMI. After that, you will enter NMI 
+	*					interrupt routine if the specific 'irq' occurs. By default, NMI irq number
+	*					is 0, same as ETH_INT_IRQn
+	* @param[in] irq irq number 
   * @retval None
-    */
+	*/
 void GLB_SetNmiIrqNum(uint32_t irq);
 
 /** @defgroup SYS_CLK_SEL
   * @{
   */
-#define SYS_CLK_SEL_OSC                 0x0
-#define SYS_CLK_SEL_DLL                 0x1
-#define SYS_CLK_SEL_CRYSTAL         0x2
-#define SYS_CLK_SEL_EXTERNAL        0x3
+#define SYS_CLK_SEL_OSC					0x0
+#define SYS_CLK_SEL_DLL					0x1
+#define SYS_CLK_SEL_CRYSTAL			0x2
+#define SYS_CLK_SEL_EXTERNAL		0x3	
 /**
   * @}
   */
-
+	
 /**
   * @brief  Select system clock source, it should be one of @ref SYS_CLK_SEL.
-    * @Note     You MUST make sure externel clock has been stabled if clock
-    *                 source is external before call this function.
-    *               Default value is SYS_CLK_SEL_OSC
-    * @param[in] irq irq number
+	* @Note		You MUST make sure externel clock has been stabled if clock 
+	*				  source is external before call this function. 
+	* 				Default value is SYS_CLK_SEL_OSC
+	* @param[in] irq irq number 
   * @retval None
-    */
+	*/
 void GLB_SelectSysClkSource(uint8_t source);
 
 /**
   * @brief  Simulate instruction 'STRB' or 'STRH' with 'BFI'
-    * @Note     In M7, you have to write a register in 32-bit alignment,
-    *                 not in 8-bit or 16-bit.
-    * @param[in] addr register address to be written
+	* @Note		In M7, you have to write a register in 32-bit alignment,
+	*				  not in 8-bit or 16-bit. 
+	* @param[in] addr register address to be written 
   * @param[in] value value to be written
   * @param[in] lsb LSB in register to be written
   * @param[in] len bit length to be written
   * @retval None
-    */
-
-
+	*/
+	
+	
 //#define aaaa(len) __asm("LDR len, 11")
 
 #define CMEM7_BFI(addr, value, lsb, len)        \
@@ -266,7 +266,7 @@ void GLB_SelectSysClkSource(uint8_t source);
     __asm("LDR tmp, [tmp1]\n"                   \
       "BFI tmp, "#value", "#lsb", "#len" \n"    \
       "STR tmp, [tmp1]\n");                     \
-        } while (0)
+		} while (0)
 
 #ifdef __cplusplus
 }

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_retarget.h

@@ -1,28 +1,28 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_retarget.h
-    *
-    * @brief    CMEM7 retarget header file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
+	*****************************************************************************
+	* @file     cmem7_retarget.h
+	*
+	* @brief    CMEM7 retarget header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
 
 #ifndef __CMEM7_RETARGET_H
 #define __CMEM7_RETARGET_H
@@ -46,21 +46,21 @@ FILE __stderr;
 
 int fputc(int c, FILE *f) {
   uint8_t ch = c;
-    if (c == '\n')  {
-        ch = '\r';
+	if (c == '\n')  {
+		ch = '\r';
     while (0 == UART_Write(PRINT_UART, 1, &ch));
-        ch = '\n';
+		ch = '\n';
   }
-
-    while (0 == UART_Write(PRINT_UART, 1, &ch)) ;
+	
+	while (0 == UART_Write(PRINT_UART, 1, &ch)) ;
   return ch;
 }
 
 
 int fgetc(FILE *f) {
-    uint8_t ch;
-
-    while (0 == UART_Read(PRINT_UART, 1, &ch)) ;
+	uint8_t ch;
+	
+	while (0 == UART_Read(PRINT_UART, 1, &ch)) ;
   return ch;
 }
 

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_rtc.h

@@ -1,29 +1,29 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_rtc.h
-    *
-    * @brief    CMEM7 RTC header file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_rtc.h
+	*
+	* @brief    CMEM7 RTC header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #ifndef __CMEM7_RTC_H
 #define __CMEM7_RTC_H
 
@@ -44,41 +44,41 @@
 /**
   * @}
   */
-
+   
 /**
-  * @brief  Enable or disable RTC interrupt.
-    * @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
-    * @param[in] Enable The bit indicates if specific interrupts are enable or not
+  * @brief  Enable or disable RTC interrupt. 
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
+	* @param[in] Enable The bit indicates if specific interrupts are enable or not
   * @retval None
-    */
+	*/ 
 void RTC_ITConfig(uint32_t Int, BOOL Enable);
 
 /**
-  * @brief  Check specific interrupts are set or not
-    * @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
+  * @brief  Check specific interrupts are set or not 
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
   * @retval BOOL The bit indicates if specific interrupts are set or not
-    */
+	*/
 BOOL RTC_GetITStatus(uint32_t Int);
 
 /**
   * @brief  Clear specific interrupts
-    * @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
   * @retval None
-    */
+	*/
 void RTC_ClearITPendingBit(uint32_t Int);
 
 /**
   * @brief  Get seconds since power up
-    * @param    None
+	* @param	None
   * @retval uint32_t Seconds since power up
-    */
+	*/
 uint32_t RTC_GetSecond(void);
 
 /**
   * @brief  Get current millseconds
-    * @param    None
+	* @param	None
   * @retval uint32_t Current millseconds
-    */
+	*/
 uint16_t RTC_GetMillSecond(void);
 
 #ifdef __cplusplus

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_spi.h

@@ -1,29 +1,29 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_spi.h
-    *
-    * @brief    CMEM7 SPI header file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_spi.h
+	*
+	* @brief    CMEM7 SPI header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #ifndef __CMEM7_SPI_H
 #define __CMEM7_SPI_H
 
@@ -43,29 +43,29 @@
 /** @defgroup SPI_MODE
   * @{
   */
-#define SPI_MODE_CPOL_0_CPHA_0         0    /*!< CPOL : Idle clock level is low level.
-                                                                                                 CPHA : Capture data at the first edge */
-#define SPI_MODE_CPOL_0_CPHA_1         1        /*!< CPOL : Idle clock level is low level.
-                                                                                                 CPHA : Capture data at the second edge */
-#define SPI_MODE_CPOL_1_CPHA_0         2        /*!< CPOL : Idle clock level is high level.
-                                                                                                 CPHA : Capture data at the first edge */
-#define SPI_MODE_CPOL_1_CPHA_1         3        /*!< CPOL : Idle clock level is high level.
-                                                                                                 CPHA : Capture data at the first edge */
+#define SPI_MODE_CPOL_0_CPHA_0         0   	/*!< CPOL : Idle clock level is low level. 
+																								 CPHA : Capture data at the first edge */
+#define SPI_MODE_CPOL_0_CPHA_1         1		/*!< CPOL : Idle clock level is low level. 
+																								 CPHA : Capture data at the second edge */	
+#define SPI_MODE_CPOL_1_CPHA_0         2		/*!< CPOL : Idle clock level is high level. 
+																								 CPHA : Capture data at the first edge */
+#define SPI_MODE_CPOL_1_CPHA_1         3	 	/*!< CPOL : Idle clock level is high level. 
+																								 CPHA : Capture data at the first edge */    
 #define IS_SPI_MODE(MODE)              (((MODE) == SPI_MODE_CPOL_0_CPHA_0) || \
                                         ((MODE) == SPI_MODE_CPOL_0_CPHA_1) || \
                                         ((MODE) == SPI_MODE_CPOL_1_CPHA_0) || \
-                                                                                ((MODE) == SPI_MODE_CPOL_1_CPHA_1))
+																				((MODE) == SPI_MODE_CPOL_1_CPHA_1))
 /**
   * @}
   */
 
 /** @defgroup SPI_INT
   * @{
-  */
-#define SPI_INT_RX_FIFO_UNDERFLOW      0x00000001
+  */	
+#define SPI_INT_RX_FIFO_UNDERFLOW      0x00000001    
 #define SPI_INT_RX_FIFO_OVERFLOW       0x00000002
 #define SPI_INT_RX_FIFO_ALMOST_FULL    0x00000004
-#define SPI_INT_TX_FIFO_UNDERFLOW      0x00000008
+#define SPI_INT_TX_FIFO_UNDERFLOW      0x00000008    
 #define SPI_INT_TX_FIFO_OVERFLOW       0x00000010
 #define SPI_INT_TX_FIFO_ALMOST_FULL    0x00000020
 #define SPI_INT_DONE                   0x00000040
@@ -78,14 +78,14 @@
 
 /**
   * @brief  SPI initialization structure
-    */
+	*/ 
 typedef struct
 {
   uint8_t SPI_Mode;                 /*!< indicates SPI's CPOL and CPHA, ref as @ref SPI_MODE */
   BOOL SPI_RxEn;                    /*!< indicates if SPI receiver is enabled or not */
   uint8_t SPI_BitLength;            /*!< bit length while transmitting and receiving */
-  uint8_t SPI_Gap;                  /*!< cycle number between continuous data frame */
-    uint8_t SPI_ClockDividor;         /*!< SPI clock dividor, 1 / ((1 + DIV) * 2) */
+  uint8_t SPI_Gap;                  /*!< cycle number between continuous data frame */ 
+	uint8_t SPI_ClockDividor;         /*!< SPI clock dividor, 1 / ((1 + DIV) * 2) */
 } SPI_InitTypeDef;
 /**
   * @}
@@ -94,69 +94,69 @@ typedef struct
 /**
   * @brief  SPI initialization
   * @note   This function should be called at first before any other interfaces.
-    * @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
-    * @param[in] init A pointer to structure SPI_InitTypeDef
+	* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
+	* @param[in] init A pointer to structure SPI_InitTypeDef
   * @retval None
-    */
+	*/ 
 void SPI_Init(SPI0_Type* SPIx, SPI_InitTypeDef *init);
 
 /**
-  * @brief  Enable or disable SPI.
-    * @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
-    * @param[in] Enable The bit indicates if the specific SPI is enable or not
+  * @brief  Enable or disable SPI. 
+	* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
+	* @param[in] Enable The bit indicates if the specific SPI is enable or not
   * @retval None
-    */
+	*/ 
 void SPI_Enable(SPI0_Type* SPIx, BOOL enable);
 
 /**
-  * @brief  Enable or disable SPI interrupt.
-    * @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
-    * @param[in] Int interrupt mask bits, which can be the combination of @ref SPI_Int
-    * @param[in] Enable The bit indicates if specific interrupts are enable or not
+  * @brief  Enable or disable SPI interrupt. 
+	* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref SPI_Int
+	* @param[in] Enable The bit indicates if specific interrupts are enable or not
   * @retval None
-    */
+	*/ 
 void SPI_EnableInt(SPI0_Type* SPIx, uint32_t Int, BOOL enable);
 
 /**
-  * @brief  Check specific interrupts are set or not
-    * @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
-    * @param[in] Int interrupt mask bits, which can be the combination of @ref SPI_Int
+  * @brief  Check specific interrupts are set or not 
+	* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref SPI_Int
   * @retval BOOL The bit indicates if specific interrupts are set or not
-    */
+	*/
 BOOL SPI_GetIntStatus(SPI0_Type* SPIx, uint32_t Int);
 
 /**
   * @brief  Clear specific interrupts
-    * @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
-    * @param[in] Int interrupt mask bits, which can be the combination of @ref SPI_Int
+	* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref SPI_Int
   * @retval None
-    */
+	*/
 void SPI_ClearInt(SPI0_Type* SPIx, uint32_t Int);
 
 /**
   * @brief  Read data from SPI FIFO
-    * @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
-    * @param[in] size Expected data size to be read
-    * @param[out] data A user-allocated buffer to fetch data to be read
+	* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
+	* @param[in] size Expected data size to be read
+	* @param[out] data A user-allocated buffer to fetch data to be read
   * @retval uint8_t Actual read data size
-    */
+	*/
 uint8_t SPI_ReadFifo(SPI0_Type* SPIx, uint8_t size, uint32_t* data);
 
 /**
   * @brief  Write data to SPI FIFO
-    * @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
-    * @param[in] size Expected data size to be written
-    * @param[in] data A pointer to the data to be written
+	* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
+	* @param[in] size Expected data size to be written
+	* @param[in] data A pointer to the data to be written
   * @retval uint8_t Actual written data size
-    */
+	*/
 uint8_t SPI_WriteFifo(SPI0_Type* SPIx, uint8_t Size, uint32_t* data);
 
 /**
-  * @brief  send a SPI transcation request
-    * @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
-    * @param[in] size Expected data size to be written and read
-    * @retval BOOL The bit indicates if the request is sent
-    */
+  * @brief  send a SPI transcation request 
+	* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
+	* @param[in] size Expected data size to be written and read
+	* @retval BOOL The bit indicates if the request is sent
+	*/
 BOOL SPI_Transcation(SPI0_Type* SPIx, uint8_t size);
 
 #ifdef __cplusplus

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_tim.h

@@ -1,29 +1,29 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_tim.h
-    *
-    * @brief    CMEM7 timer header file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_tim.h
+	*
+	* @brief    CMEM7 timer header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #ifndef __CMEM7_TIM_H
 #define __CMEM7_TIM_H
 
@@ -39,58 +39,58 @@
                                    ((PERIPH) == TIMER1) || \
                                    ((PERIPH) == TIMER2) || \
                                    ((PERIPH) == TIMER3))
-
+																	 
 /**
   * @brief  Timer initialization
   * @note   This function should be called at first before any other interfaces.
-    * @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
-    * @param[in] Ms overflow micro-seconds of the specific timer
+	* @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
+	* @param[in] Ms overflow micro-seconds of the specific timer
   * @retval None
-    */
+	*/
 void TIM_Init(TIMER0_Type* Timx, uint16_t Ms);
 
 /**
-  * @brief  Enable or disable timer interrupt.
-    * @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
-    * @param[in] Enable The bit indicates if the specific interrupt is enable or not
+  * @brief  Enable or disable timer interrupt. 
+	* @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
+	* @param[in] Enable The bit indicates if the specific interrupt is enable or not
   * @retval None
-    */
+	*/ 
 void TIM_EnableInt(TIMER0_Type* Timx, BOOL Enable);
 
 /**
-  * @brief  Check the specific interrupt is set or not
-    * @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
-    * @retval BOOL The bit indicates if the specific interrupt is set or not
-    */
+  * @brief  Check the specific interrupt is set or not 
+	* @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
+	* @retval BOOL The bit indicates if the specific interrupt is set or not
+	*/
 BOOL TIM_GetIntStatus(TIMER0_Type* Timx);
 
 /**
   * @brief  Clear specific interrupts
-    * @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
-    * @retval None
-    */
+	* @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
+	* @retval None
+	*/
 void TIM_ClearInt(TIMER0_Type* Timx);
 
 /**
-  * @brief  Enable or disable timer.
-    * @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
-    * @param[in] Enable The bit indicates if the specific timer is enable or not
+  * @brief  Enable or disable timer. 
+	* @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
+	* @param[in] Enable The bit indicates if the specific timer is enable or not
   * @retval None
-    */
+	*/ 
 void TIM_Enable(TIMER0_Type* Timx, BOOL Enable);
 
 /**
-  * @brief  Check the specific timer is overflow or not
-    * @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
-    * @retval BOOL The bit indicates if the specific timer is overflow or not
-    */
+  * @brief  Check the specific timer is overflow or not 
+	* @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
+	* @retval BOOL The bit indicates if the specific timer is overflow or not
+	*/
 BOOL TIM_IsOverflow(TIMER0_Type* Timx);
 
 /**
   * @brief  Get current counter of timer
-    * @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
-    * @retval uint32_t current counter
-    */
+	* @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
+	* @retval uint32_t current counter
+	*/
 uint32_t TIM_GetCounter(TIMER0_Type* Timx);
 
 #ifdef __cplusplus

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_uart.h

@@ -1,28 +1,28 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_uart.h
-    *
-    * @brief    CMEM7 uart header file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
+	*****************************************************************************
+	* @file     cmem7_uart.h
+	*
+	* @brief    CMEM7 uart header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
 
 #ifndef __CMEM7_UART_H
 #define __CMEM7_UART_H
@@ -37,7 +37,7 @@
 #define IS_UART_ALL_PERIPH(PERIPH) (((PERIPH) == UART0) || \
                                      ((PERIPH) == UART1) || \
                                      ((PERIPH) == UART2))
-
+	
 /** @defgroup UART_StopBits
   * @{
   */
@@ -61,7 +61,7 @@
 #define UART_Parity_None                  2
 #define IS_UART_PARITY(PARITY) (((PARITY) == UART_Parity_Even) || \
                                  ((PARITY) == UART_Parity_Odd) || \
-                                                                 ((PARITY) == UART_Parity_None))
+																 ((PARITY) == UART_Parity_None))										 
 /**
   * @}
   */
@@ -69,7 +69,7 @@
 /** @defgroup UART_Int
   * @{
   */
-#define UART_Int_RxNotEmpty               0x00000001
+#define UART_Int_RxNotEmpty               0x00000001    
 #define UART_Int_TxEmpty                  0x00000002
 #define UART_Int_TxHalfEmpty              0x00000004
 #define UART_Int_TxTimeoutNotEmpty        0x00000008
@@ -87,80 +87,80 @@
 /**
   * @}
   */
-
+	
 /**
   * @brief  UART initialization structure
-    */
+	*/ 
 typedef struct
 {
-    uint32_t UART_BaudRate;            /*!< Baudrate */
-    uint8_t UART_StopBits;             /*!< Specifies the number of stop bits transmitted,
-                                                                                    It's a value of @ref UART_StopBits */
-    uint8_t UART_Parity;               /*!< Specifies the parity mode.
-                                                                                    It's a value of @ref UART_Parity */
-    BOOL UART_LoopBack;                /*!< loop back mode */
-    BOOL UART_RxEn;                    /*!< Receive enable bit */
-    BOOL UART_CtsEn;                   /*!< Clear to set */
+	uint32_t UART_BaudRate;            /*!< Baudrate */																	  
+	uint8_t UART_StopBits;             /*!< Specifies the number of stop bits transmitted, 
+																					It's a value of @ref UART_StopBits */
+	uint8_t UART_Parity;               /*!< Specifies the parity mode. 
+																					It's a value of @ref UART_Parity */
+	BOOL UART_LoopBack;                /*!< loop back mode */
+	BOOL UART_RxEn;                    /*!< Receive enable bit */
+	BOOL UART_CtsEn;                   /*!< Clear to set */
 } UART_InitTypeDef;
 
 /**
   * @brief  UART initialization
   * @note   This function should be called at first before any other interfaces.
-    * @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
-    * @param[in] init A pointer to structure UART_InitTypeDef
+	* @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
+	* @param[in] init A pointer to structure UART_InitTypeDef
   * @retval None
-    */
+	*/ 
 void UART_Init(UART0_Type* UARTx, UART_InitTypeDef *init);
 
 /**
-  * @brief  Enable or disable UART interrupt.
-    * @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
-    * @param[in] Int interrupt mask bits, which can be the combination of @ref UART_Int
-    * @param[in] Enable The bit indicates if specific interrupts are enable or not
+  * @brief  Enable or disable UART interrupt. 
+	* @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref UART_Int
+	* @param[in] Enable The bit indicates if specific interrupts are enable or not
   * @retval None
-    */
+	*/ 
 void UART_EnableInt(UART0_Type* UARTx, uint32_t Int, BOOL Enable);
 
 /**
-  * @brief  Enable or disable UART.
-    * @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
-    * @param[in] Enable The bit indicates if the specific UART is enable or not
+  * @brief  Enable or disable UART. 
+	* @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
+	* @param[in] Enable The bit indicates if the specific UART is enable or not
   * @retval None
-    */
+	*/ 
 void UART_Enable(UART0_Type* UARTx, BOOL enable);
 
 /**
-  * @brief  Check specific interrupts are set or not
-    * @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
-    * @param[in] Int interrupt mask bits, which can be the combination of @ref UART_Int
+  * @brief  Check specific interrupts are set or not 
+	* @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref UART_Int
   * @retval BOOL The bit indicates if specific interrupts are set or not
-    */
+	*/
 BOOL UART_GetIntStatus(UART0_Type* UARTx, uint32_t Int);
 
 /**
   * @brief  Clear specific interrupts
-    * @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
-    * @param[in] Int interrupt mask bits, which can be the combination of @ref UART_Int
+	* @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
+	* @param[in] Int interrupt mask bits, which can be the combination of @ref UART_Int
   * @retval None
-    */
+	*/
 void UART_ClearInt(UART0_Type* UARTx, uint32_t Int);
 
 /**
   * @brief  Write data to UART
-    * @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
-    * @param[in] Size Expected data size to be written
-    * @param[in] Data A pointer to the data to be written
+	* @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
+	* @param[in] Size Expected data size to be written
+	* @param[in] Data A pointer to the data to be written
   * @retval uint8_t Actual written data size
-    */
+	*/
 uint8_t UART_Write(UART0_Type* UARTx, uint8_t Size, uint8_t* Data);
 
 /**
   * @brief  Read data from UART
-    * @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
-    * @param[in] Size Expected data size to be read
-    * @param[out] Data A user-allocated buffer to fetch data to be read
+	* @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
+	* @param[in] Size Expected data size to be read
+	* @param[out] Data A user-allocated buffer to fetch data to be read
   * @retval uint8_t Actual read data size
-    */
+	*/
 uint8_t UART_Read(UART0_Type* UARTx, uint8_t Size, uint8_t* Data);
 
 

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_usb.h

@@ -1,28 +1,28 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_usb.h
-    *
-    * @brief    CMEM7 USB header file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
+	*****************************************************************************
+	* @file     cmem7_usb.h
+	*
+	* @brief    CMEM7 USB header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
 
 #ifndef __CMEM7_USB_H
 #define __CMEM7_USB_H
@@ -38,19 +38,19 @@
 /**
  *
  */
-#define SET_HCDMA_DESC_ADDR(a)      (((uint32_t)(a)) >> 9)
-#define MIN(a, b)                   (((a) <= (b)) ? (a) : (b))
-#define MAX(a, b)                   (((a) >= (b)) ? (a) : (b))
-#define BIT(b)                      (0x1U << (b))
+#define SET_HCDMA_DESC_ADDR(a)		(((uint32_t)(a)) >> 9)
+#define MIN(a, b)					(((a) <= (b)) ? (a) : (b))
+#define MAX(a, b)					(((a) >= (b)) ? (a) : (b))
+#define BIT(b)						(0x1u << (b))
 
 /** @defgroup USB_HOST_PID
   * @{
   */
-#define USB_HOST_PID_DATA0          0x0             /*!< Indicates the Data PID is DATA0                                       */
-#define USB_HOST_PID_DATA2          0x1             /*!< Indicates the Data PID is DATA2                                       */
-#define USB_HOST_PID_DATA1          0x2             /*!< Indicates the Data PID is DATA1                                       */
-#define USB_HOST_PID_MDATA          0x3             /*!< Indicates the Data PID is MDATA (non-control)                         */
-#define USB_HOST_PID_SETUP          0x3             /*!< Indicates the Data PID is SETUP (control)                             */
+#define USB_HOST_PID_DATA0			0x0				/*!< Indicates the Data PID is DATA0                                       */
+#define USB_HOST_PID_DATA2			0x1				/*!< Indicates the Data PID is DATA2                                       */
+#define USB_HOST_PID_DATA1			0x2				/*!< Indicates the Data PID is DATA1                                       */
+#define USB_HOST_PID_MDATA			0x3				/*!< Indicates the Data PID is MDATA (non-control)                         */
+#define USB_HOST_PID_SETUP			0x3				/*!< Indicates the Data PID is SETUP (control)                             */
 /**
   * @}
   */
@@ -59,10 +59,10 @@
   * @{
   */
 typedef enum {
-    USB_EP_TYPE_CONTROL =           0x0,            /*!< Control                                                               */
-    USB_EP_TYPE_ISO =               0x1,            /*!< Isochronous                                                           */
-    USB_EP_TYPE_BULK =              0x2,            /*!< Bulk                                                                  */
-    USB_EP_TYPE_INT =               0x3,            /*!< Interrupt                                                             */
+	USB_EP_TYPE_CONTROL =			0x0,			/*!< Control                                                               */
+	USB_EP_TYPE_ISO =				0x1,			/*!< Isochronous                                                           */
+	USB_EP_TYPE_BULK =				0x2,			/*!< Bulk                                                                  */
+	USB_EP_TYPE_INT =				0x3,			/*!< Interrupt                                                             */
 } USB_EP_TYPE;
 /**
   * @}
@@ -72,10 +72,10 @@ typedef enum {
   * @{
   */
 typedef enum {
-    USB_ENUM_SPEED_HS =             0x0,            /*!< Enumerated Speed is High Speed                                        */
-    USB_ENUM_SPEED_FS =             0x1,            /*!< Enumerated Speed is Full Speed                                        */
-    USB_ENUM_SPEED_LS =             0x2,            /*!< Enumerated Speed is Low  Speed                                        */
-    USB_ENUM_SPEED_FS_48M =         0x3,            /*!< Enumerated Speed is Full Speed (PHY clock is running at 48MHz)        */
+	USB_ENUM_SPEED_HS =				0x0,			/*!< Enumerated Speed is High Speed                                        */
+	USB_ENUM_SPEED_FS =				0x1,			/*!< Enumerated Speed is Full Speed                                        */
+	USB_ENUM_SPEED_LS =				0x2,			/*!< Enumerated Speed is Low  Speed                                        */
+	USB_ENUM_SPEED_FS_48M =			0x3,			/*!< Enumerated Speed is Full Speed (PHY clock is running at 48MHz)        */
 } USB_ENUM_SPEED;
 /**
   * @}
@@ -85,15 +85,15 @@ typedef enum {
   * @{
   */
 typedef enum {
-    USB_INT_GP_HOST_DISC,                           /*!< Device disconnection interrupt (Only for HOST Mode)                   */
-    USB_INT_GP_DEV_RESET,                           /*!< USB Port Reset Interrupt (Only for DEVICE Mode)                       */
-    USB_INT_GP_DEV_ENUMDONE,                        /*!< Enumeration Done Interrupt (Only for DEVICE Mode)                     */
-    USB_INT_GP_DEV_SUSP,                            /*!< USB Suspend Interrupt (Only for DEVICE Mode)                          */
-    USB_INT_GP_DEV_EARLY,                           /*!< USB Idle Interrupt (Only for DEVICE Mode)                             */
-    USB_INT_GP_SOF,                                 /*!< SOF Interrupt                                                         */
-    USB_INT_GP_MIS,                                 /*!< USB access overstep the boundary Interrupt                            */
-    USB_INT_GP_IDCHG,                               /*!< OTG Connector ID Status Change Interrupt                              */
-    USB_INT_GP_SESSREQ,                             /*!< Session Request / Create Interrupt                                    */
+	USB_INT_GP_HOST_DISC,							/*!< Device disconnection interrupt (Only for HOST Mode)                   */
+	USB_INT_GP_DEV_RESET,							/*!< USB Port Reset Interrupt (Only for DEVICE Mode)                       */
+	USB_INT_GP_DEV_ENUMDONE,						/*!< Enumeration Done Interrupt (Only for DEVICE Mode)                     */
+	USB_INT_GP_DEV_SUSP,							/*!< USB Suspend Interrupt (Only for DEVICE Mode)                          */
+	USB_INT_GP_DEV_EARLY,							/*!< USB Idle Interrupt (Only for DEVICE Mode)                             */
+	USB_INT_GP_SOF,									/*!< SOF Interrupt                                                         */
+	USB_INT_GP_MIS,									/*!< USB access overstep the boundary Interrupt                            */
+	USB_INT_GP_IDCHG,								/*!< OTG Connector ID Status Change Interrupt                              */
+	USB_INT_GP_SESSREQ,								/*!< Session Request / Create Interrupt                                    */
 } USB_INT_GP;
 /**
   * @}
@@ -103,11 +103,11 @@ typedef enum {
   * @{
   */
 typedef enum {
-    USB_INT_OTG_SESEND,                             /*!< Session End Interrupt                                                 */
-    USB_INT_OTG_STANDAUP,                           /*!< B Device timeout to connect Interrupt                                 */
-    USB_INT_OTG_HNDETECT,                           /*!< Host Negotiation Detected Interrupt                                   */
-    USB_INT_OTG_HNSUCCHG,                           /*!< Host Negotiation Success Status Change Interrupt                      */
-    USB_INT_OTG_KEEPAPP,                            /*!< Debounce Done Interrupt (Only for HOST Mode)                          */
+	USB_INT_OTG_SESEND,								/*!< Session End Interrupt                                                 */
+	USB_INT_OTG_STANDAUP,							/*!< B Device timeout to connect Interrupt                                 */
+	USB_INT_OTG_HNDETECT,							/*!< Host Negotiation Detected Interrupt                                   */
+	USB_INT_OTG_HNSUCCHG,							/*!< Host Negotiation Success Status Change Interrupt                      */
+	USB_INT_OTG_KEEPAPP,							/*!< Debounce Done Interrupt (Only for HOST Mode)                          */
 } USB_INT_OTG;
 /**
   * @}
@@ -117,10 +117,10 @@ typedef enum {
   * @{
   */
 typedef enum {
-    USB_OTG_DEV_HNSUCC = 8,                         /*!< Host Negotiation Success (Only for DEVICE Mode, Read Only)            */
-    USB_OTG_DEV_HNPREQ = 9,                         /*!< HNP Request (Only for DEVICE Mode)                                    */
-    USB_OTG_HST_HNPENABLE = 10,                     /*!< Host Set HNP Enable (Only for HOST Mode)                              */
-    USB_OTG_DEV_HNPENABLE = 11,                     /*!< Device HNP Enabled (Only for DEVICE Mode)                             */
+	USB_OTG_DEV_HNSUCC = 8,							/*!< Host Negotiation Success (Only for DEVICE Mode, Read Only)            */
+	USB_OTG_DEV_HNPREQ = 9,							/*!< HNP Request (Only for DEVICE Mode)                                    */
+	USB_OTG_HST_HNPENABLE = 10,						/*!< Host Set HNP Enable (Only for HOST Mode)                              */
+	USB_OTG_DEV_HNPENABLE = 11,						/*!< Device HNP Enabled (Only for DEVICE Mode)                             */
 } USB_OTG_CTL;
 
 /**
@@ -129,7 +129,7 @@ typedef enum {
 
 typedef union {
     __IO uint32_t  HPRT;                            /*!< Host Port Control and Status Register                                 */
-
+    
     struct {
       __I  uint32_t  PCS        :  1;               /*!< If a device is attached to the port                                   */
       __IO uint32_t  PCD        :  1;               /*!< A device connection is detected                                       */
@@ -212,7 +212,7 @@ void USB_EnableInt(BOOL enable);
 
 /**
  * @brief Flush TX/RX FIFO
-   * @param[in] num Flush FIFO, 0: non-periodic TX FIFO (HOST Mode) or FIFO 0 (DEVICE Mode); 1: Periodic TX FIFO (HOST Mode) or FIFO 1 (DEVICE Mode); 2-15: FIFO n in DEVICE Mode; 16: Flush All TX FIFO; otherwise: Flush RX FIFO
+   * @param[in] num Flush FIFO£¬0: non-periodic TX FIFO (HOST Mode) or FIFO 0 (DEVICE Mode); 1: Periodic TX FIFO (HOST Mode) or FIFO 1 (DEVICE Mode); 2-15: FIFO n in DEVICE Mode; 16: Flush All TX FIFO; otherwise: Flush RX FIFO
  * @retval void
    */
 void USB_FlushFIFO(uint32_t num);
@@ -233,7 +233,7 @@ BOOL USB_roleIsHost(void);
 /**
  * @brief Control and get VBus Status (Only for HOST Mode)
    * @param[in] opt Bit1: Set VBus using Bit0; Bit0: Turn VBus On or Off
- * @retval BOOL TRUE: VBus is on; FALSE: VBus is off
+ * @retval BOOL TRUE: VBus is on; FALSE£ºVBus is off
  * @note It cannot control VBus actually due to HW problem
    */
 BOOL USB_hostVBus(uint32_t opt);
@@ -363,13 +363,13 @@ BOOL USB_hostINT_isPCD(void);
 void USB_hostINT_clrPCD(void);
 
 /**
- * @brief Port Enable/Disable Change (PEDC) Interrupt Asserted (Only for HOST Mode)
+ * @brief Port Enable/Disable Change£¨PEDC£©Interrupt Asserted (Only for HOST Mode)
  * @retval BOOL TRUE: Interrupt Asserted; FALSE: Interrupt is NOT asserted
    */
 BOOL USB_hostINT_isPEDC(void);
 
 /**
- * @brief Clear Port Enable/Disable Change (PEDC) Interrupt Flag (Only for HOST Mode)
+ * @brief Clear Port Enable/Disable Change£¨PEDC£©Interrupt Flag (Only for HOST Mode)
  * @retval void
    */
 void USB_hostINT_clrPEDC(void);
@@ -520,7 +520,7 @@ void USB_devINT_enDone(uint32_t ep, BOOL in, BOOL en);
  * @brief Transaction Done Interrupt Asserted (Only for DEVICE Mode)
    * @param[in] ep Endpoint
    * @param[in] in Endpoint Direction, TRUE: IN; FALSE: OUT
- * @retval uint32_t Result, Bit0: Done; Bit1: Buffer Not Available Error; Bit2: SETUP Phase Done
+ * @retval uint32_t Result, Bit0: Done; Bit1£ºBuffer Not Available Error; Bit2: SETUP Phase Done
    */
 uint32_t USB_devINT_isDone(uint32_t ep, BOOL in);
 

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_wdg.h

@@ -1,29 +1,29 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_wdg.h
-    *
-    * @brief    CMEM7 watchdog header file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_wdg.h
+	*
+	* @brief    CMEM7 watchdog header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #ifndef __CMEM7_WDG_H
 #define __CMEM7_WDG_H
 
@@ -58,47 +58,47 @@
 
 /**
   * @brief  Deinitializes the Watchdog peripheral registers to their default reset values.
-    * @param[in] None
+	* @param[in] None
   * @retval None
-    */
+	*/ 
 void WDG_DeInit(void);
 
 /**
   * @brief  Watchdog initialization
   * @note   This function should be called at first before any other interfaces.
-    * @param[in] trigger Watchdog interrupt trigger mode, which is a value of @ref WDG_TRIGGER_MODE
-    * @param[in] ResetMillSecond MillSeconds lasts before global reset
+	* @param[in] trigger Watchdog interrupt trigger mode, which is a value of @ref WDG_TRIGGER_MODE
+	* @param[in] ResetMillSecond MillSeconds lasts before global reset
   * @retval None
-    */
+	*/ 
 void WDG_Init(uint8_t trigger, uint16_t ResetMillSecond);
 
 /**
-  * @brief  Enable or disable watchdog interrupt.
-    * @param[in] Int interrupt mask bits, which is a value of @ref WDG_INT
-    * @param[in] Enable The bit indicates if the specific interrupt are enable or not
+  * @brief  Enable or disable watchdog interrupt. 
+	* @param[in] Int interrupt mask bits, which is a value of @ref WDG_INT
+	* @param[in] Enable The bit indicates if the specific interrupt are enable or not
   * @retval None
-    */
+	*/ 
 void WDG_ITConfig(uint8_t Int, BOOL Enable);
 
 /**
-  * @brief  Check the specific interrupt are set or not
-    * @param    None
+  * @brief  Check the specific interrupt are set or not 
+	* @param	None
   * @retval BOOL The bit indicates if the specific interrupt are set or not
-    */
+	*/
 BOOL WDG_GetITStatus(void);
 
 /**
   * @brief  Clear the specific interrupt
-    * @param    None
+	* @param	None
   * @retval None
-    */
+	*/
 void WDG_ClearITPendingBit(void);
 
 /**
-  * @brief  Enable or disable watchdog.
-    * @param[in] Enable The bit indicates if watchdog is enable or not
+  * @brief  Enable or disable watchdog. 
+	* @param[in] Enable The bit indicates if watchdog is enable or not
   * @retval None
-    */
+	*/ 
 void WDG_Cmd(BOOL Enable);
 
 

bsp/CME_M7/StdPeriph_Driver/inc/system_cmem7.h

@@ -1,42 +1,42 @@
 /**
-    *****************************************************************************
-    * @file     system_cmem7.h
-    *
-    * @brief    CMEM7 system initial header file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
+	*****************************************************************************
+	* @file     system_cmem7.h
+	*
+	* @brief    CMEM7 system initial header file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note      
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
 
 #ifndef __SYSTEM_CMEM7_H
 #define __SYSTEM_CMEM7_H
 
 #ifdef __cplusplus
  extern "C" {
-#endif
+#endif 
 
 /**
   * @brief  Setup the microcontroller system.
   * @note   This function should be used only after reset.
-    * @param  None
+	* @param  None
   * @retval None
-    */
+	*/  
 void SystemInit(void);
 
 #ifdef __cplusplus

bsp/CME_M7/StdPeriph_Driver/src/cmem7_adc.c

@@ -1,309 +1,309 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_adc.c
-    *
-    * @brief    CMEM7 ADC source file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_adc.c
+	*
+	* @brief    CMEM7 ADC source file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #include "cmem7_adc.h"
 #include "cmem7.h"
 
 #define ADC_SYSTEM_MODE_IDLE       0
 
 static BOOL adc_IsMultiChannel(uint32_t channel) {
-    uint32_t i = 0;
-
-    for (i = 0; channel != 0; i++) {
+	uint32_t i = 0;
+  
+	for (i = 0; channel != 0; i++) {
     channel &= (channel - 1);
-    }
-
-    return ((i > 1) ? TRUE : FALSE);
+	}
+	
+	return ((i > 1) ? TRUE : FALSE);
 }
 
 static uint8_t adc_GetChannel(uint32_t channel) {
-    uint32_t i = 0;
-
-    for (i = 0; channel > 1; i++) {
+	uint32_t i = 0;
+  
+	for (i = 0; channel > 1; i++) {
     channel >>= 1;
-    }
-
-    return i;
+	}
+	
+	return i;
 }
 
 static void adc_Reset(uint8_t adc, BOOL enable) {
-    if (adc == ADC_PERIPH_1) {
-        ADC->POWERDOWN_RESET_b.POWERDOWN_ADC1 = TRUE;
-        ADC->POWERDOWN_RESET_b.RESET_ADC1 = TRUE;
-        udelay(8000);
-        if (enable) {
-            ADC->POWERDOWN_RESET_b.POWERDOWN_ADC1 = FALSE;
-            ADC->POWERDOWN_RESET_b.RESET_ADC1 = FALSE;
-            udelay(8000);
-        }
-    } else {
-        ADC->POWERDOWN_RESET_b.POWERDOWN_ADC2 = TRUE;
-        ADC->POWERDOWN_RESET_b.RESET_ADC2 = TRUE;
-        udelay(8000);
-        if (enable) {
-            ADC->POWERDOWN_RESET_b.POWERDOWN_ADC2 = FALSE;
-            ADC->POWERDOWN_RESET_b.RESET_ADC2 = FALSE;
-            udelay(8000);
-        }
-    }
+	if (adc == ADC_PERIPH_1) {
+		ADC->POWERDOWN_RESET_b.POWERDOWN_ADC1 = TRUE;
+		ADC->POWERDOWN_RESET_b.RESET_ADC1 = TRUE;
+		udelay(8000);
+		if (enable) {
+			ADC->POWERDOWN_RESET_b.POWERDOWN_ADC1 = FALSE;
+			ADC->POWERDOWN_RESET_b.RESET_ADC1 = FALSE;
+			udelay(8000);
+		}
+	} else {
+		ADC->POWERDOWN_RESET_b.POWERDOWN_ADC2 = TRUE;
+		ADC->POWERDOWN_RESET_b.RESET_ADC2 = TRUE;
+		udelay(8000);
+		if (enable) {
+			ADC->POWERDOWN_RESET_b.POWERDOWN_ADC2 = FALSE;
+			ADC->POWERDOWN_RESET_b.RESET_ADC2 = FALSE;
+			udelay(8000);
+		}
+	}
 }
 
 void ADC_Init(ADC_InitTypeDef* init) {
-    assert_param(init);
-    assert_param(IS_ADC_PHASE_CTRL(init->ADC_PhaseCtrl));
-    assert_param(IS_ADC_VSEN(init->ADC_VsenSelection));
-
-    SOFT_RESET->SOFTRST_b.ADC_n = 0;
-    SOFT_RESET->SOFTRST_b.ADC_n = 1;
-
-    ADC->CFG0_b.PHASE_CTRL = init->ADC_PhaseCtrl;
-    ADC->CFG0_b.VSEN = init->ADC_VsenSelection;
+	assert_param(init);
+	assert_param(IS_ADC_PHASE_CTRL(init->ADC_PhaseCtrl));
+	assert_param(IS_ADC_VSEN(init->ADC_VsenSelection));
+	
+	SOFT_RESET->SOFTRST_b.ADC_n = 0;
+	SOFT_RESET->SOFTRST_b.ADC_n = 1;
+	
+	ADC->CFG0_b.PHASE_CTRL = init->ADC_PhaseCtrl;
+	ADC->CFG0_b.VSEN = init->ADC_VsenSelection;
 }
 
 void ADC_Enable(uint8_t adc, BOOL enable) {
-    assert_param(IS_ADC_ALL_PERIPH(adc));
-
-    adc_Reset(adc, enable);
+	assert_param(IS_ADC_ALL_PERIPH(adc));
+	
+	adc_Reset(adc, enable);
 }
 
 void ADC_EnableInt(uint32_t Int, BOOL enable) {
-    assert_param(IS_ADC_INT(Int));
-
-    if (enable) {
-      ADC->INT_MASK &= ~Int;
-    } else {
-        ADC->INT_MASK |= Int;
-    }
+	assert_param(IS_ADC_INT(Int));
+	
+	if (enable) {
+	  ADC->INT_MASK &= ~Int;
+	} else {
+		ADC->INT_MASK |= Int;
+	}
 }
 
 BOOL ADC_GetIntStatus(uint32_t Int) {
-    assert_param(IS_ADC_INT(Int));
-
-    if (0 != (ADC->INT_STATUS & Int)) {
-        return TRUE;
-    }
-
-    return FALSE;
+	assert_param(IS_ADC_INT(Int));
+	
+	if (0 != (ADC->INT_STATUS & Int)) {
+		return TRUE;
+	}
+	
+	return FALSE;
 }
 
 void ADC_ClearInt(uint32_t Int) {
-    assert_param(IS_ADC_INT(Int));
-
-    ADC->INT_STATUS = Int;
+	assert_param(IS_ADC_INT(Int));
+	
+	ADC->INT_STATUS = Int;
 }
 
 BOOL ADC_StartConversion(uint8_t adc, uint8_t convMode, uint32_t channel) {
-    assert_param(IS_ADC_ALL_PERIPH(adc));
-    assert_param(IS_ADC_CONVERSION(convMode));
-
-    if (adc == ADC_PERIPH_1) {
-        assert_param(IS_ADC1_CHANNEL(channel));
-        if (ADC->BUSY_b.ADC1_BUSY) {
-            return FALSE;
-        }
-
-        if (adc_IsMultiChannel(channel)) {
-            ADC->CFG_ADC1_b.SYSTEM_MODE = ADC_SYSTEM_MODE_SINGLE_CONV;
-            ADC->CFG_ADC1_b.MULTI_CHANNEL_BIT = channel;
-            ADC->CFG_ADC1_b.MULTI_CHANNEL_CONTINUE_SCAN =
-                (convMode == ADC_SYSTEM_MODE_CONTINUOUS_CONV) ? 1 : 0;
-        } else {
-            ADC->CFG_ADC1_b.SYSTEM_MODE = convMode;
-
-            if (convMode == ADC_SYSTEM_MODE_CONTINUOUS_CONV) {
-                ADC->CFG_ADC1_b.CHANNEL_SEL = adc_GetChannel(channel);
-            } else {
-                ADC->CFG_ADC1_b.MULTI_CHANNEL_BIT = channel;
-                ADC->CFG_ADC1_b.MULTI_CHANNEL_CONTINUE_SCAN = 0;
-            }
-        }
-
-        ADC->ADC1_START_b.EN = TRUE;
-    } else {
-        assert_param(IS_ADC2_CHANNEL(channel));
-        if (ADC->BUSY_b.ADC2_BUSY) {
-            return FALSE;
-        }
-
-        if (adc_IsMultiChannel(channel)) {
-            ADC->CFG_ADC2_b.SYSTEM_MODE = ADC_SYSTEM_MODE_SINGLE_CONV;
-            ADC->CFG_ADC2_b.MULTI_CHANNEL_BIT = channel;
-            ADC->CFG_ADC2_b.MULTI_CHANNEL_CONTINUE_SCAN =
-                (convMode == ADC_SYSTEM_MODE_CONTINUOUS_CONV) ? 1 : 0;
-        } else {
-            ADC->CFG_ADC2_b.SYSTEM_MODE = convMode;
-
-            if (convMode == ADC_SYSTEM_MODE_CONTINUOUS_CONV) {
-                ADC->CFG_ADC2_b.CHANNEL_SEL = adc_GetChannel(channel);
-            } else {
-                ADC->CFG_ADC2_b.MULTI_CHANNEL_BIT = channel;
-                ADC->CFG_ADC2_b.MULTI_CHANNEL_CONTINUE_SCAN = 0;
-            }
-        }
-
-        ADC->ADC2_START_b.EN = TRUE;
-    }
-
-    return TRUE;
+	assert_param(IS_ADC_ALL_PERIPH(adc));
+	assert_param(IS_ADC_CONVERSION(convMode));
+	
+	if (adc == ADC_PERIPH_1) {
+		assert_param(IS_ADC1_CHANNEL(channel));
+		if (ADC->BUSY_b.ADC1_BUSY) {
+			return FALSE;
+		}
+		
+		if (adc_IsMultiChannel(channel)) {
+			ADC->CFG_ADC1_b.SYSTEM_MODE = ADC_SYSTEM_MODE_SINGLE_CONV;
+			ADC->CFG_ADC1_b.MULTI_CHANNEL_BIT = channel;
+			ADC->CFG_ADC1_b.MULTI_CHANNEL_CONTINUE_SCAN = 
+				(convMode == ADC_SYSTEM_MODE_CONTINUOUS_CONV) ? 1 : 0;
+		} else {
+			ADC->CFG_ADC1_b.SYSTEM_MODE = convMode;
+				
+			if (convMode == ADC_SYSTEM_MODE_CONTINUOUS_CONV) {
+				ADC->CFG_ADC1_b.CHANNEL_SEL = adc_GetChannel(channel);
+			} else {
+				ADC->CFG_ADC1_b.MULTI_CHANNEL_BIT = channel;
+				ADC->CFG_ADC1_b.MULTI_CHANNEL_CONTINUE_SCAN = 0;
+			}				
+		}
+				
+		ADC->ADC1_START_b.EN = TRUE;
+	} else {
+		assert_param(IS_ADC2_CHANNEL(channel));
+		if (ADC->BUSY_b.ADC2_BUSY) {
+			return FALSE;
+		}		
+		
+		if (adc_IsMultiChannel(channel)) {
+			ADC->CFG_ADC2_b.SYSTEM_MODE = ADC_SYSTEM_MODE_SINGLE_CONV;
+			ADC->CFG_ADC2_b.MULTI_CHANNEL_BIT = channel;
+			ADC->CFG_ADC2_b.MULTI_CHANNEL_CONTINUE_SCAN = 
+				(convMode == ADC_SYSTEM_MODE_CONTINUOUS_CONV) ? 1 : 0;
+		} else {
+			ADC->CFG_ADC2_b.SYSTEM_MODE = convMode;
+				
+			if (convMode == ADC_SYSTEM_MODE_CONTINUOUS_CONV) {
+				ADC->CFG_ADC2_b.CHANNEL_SEL = adc_GetChannel(channel);
+			} else {
+				ADC->CFG_ADC2_b.MULTI_CHANNEL_BIT = channel;
+				ADC->CFG_ADC2_b.MULTI_CHANNEL_CONTINUE_SCAN = 0;
+			}				
+		}
+				
+		ADC->ADC2_START_b.EN = TRUE;
+	}
+	
+	return TRUE;
 }
 
 BOOL ADC_StartCalibration(uint8_t adc, uint8_t calibration) {
-    assert_param(IS_ADC_ALL_PERIPH(adc));
-    assert_param(IS_ADC_CALIBRATION(calibration));
+	assert_param(IS_ADC_ALL_PERIPH(adc));
+	assert_param(IS_ADC_CALIBRATION(calibration));
+	
+	if (adc == ADC_PERIPH_1) {
+		if (ADC->BUSY_b.ADC1_BUSY) {
+			return FALSE;
+		}
+		
+		ADC->CFG_ADC1_b.SYSTEM_MODE = calibration;
+		ADC->ADC1_START_b.EN = TRUE;
+	} else {
+		if (ADC->BUSY_b.ADC2_BUSY) {
+			return FALSE;
+		}
 
-    if (adc == ADC_PERIPH_1) {
-        if (ADC->BUSY_b.ADC1_BUSY) {
-            return FALSE;
-        }
-
-        ADC->CFG_ADC1_b.SYSTEM_MODE = calibration;
-        ADC->ADC1_START_b.EN = TRUE;
-    } else {
-        if (ADC->BUSY_b.ADC2_BUSY) {
-            return FALSE;
-        }
-
-        ADC->CFG_ADC2_b.SYSTEM_MODE = calibration;
-        ADC->ADC2_START_b.EN = TRUE;
-    }
-
-    return TRUE;
+		ADC->CFG_ADC2_b.SYSTEM_MODE = calibration;
+		ADC->ADC2_START_b.EN = TRUE;
+	}
+	
+	return TRUE;	
 }
 
 void ADC_Stop(uint8_t adc) {
-    assert_param(IS_ADC_ALL_PERIPH(adc));
-
-    if (adc == ADC_PERIPH_1) {
-        if (IS_ADC_CONVERSION(ADC->CFG_ADC1_b.SYSTEM_MODE)) {
-            ADC->ADC1_STOP_b.EN = TRUE;
-        }
-        while (ADC->BUSY_b.ADC1_BUSY) ;
-
-        ADC->ADC1_FIFO_CLEAR_b.CLEAR = TRUE;
-        //udelay(1000);
-        ADC->ADC1_FIFO_CLEAR_b.CLEAR = FALSE;
-    } else {
-        if (IS_ADC_CONVERSION(ADC->CFG_ADC2_b.SYSTEM_MODE)) {
-            ADC->ADC2_STOP_b.EN = TRUE;
-        }
-        while (ADC->BUSY_b.ADC2_BUSY) ;
-
-        ADC->ADC2_FIFO_CLEAR_b.CLEAR = TRUE;
-        //udelay(1000);
-        ADC->ADC2_FIFO_CLEAR_b.CLEAR = FALSE;
-    }
+	assert_param(IS_ADC_ALL_PERIPH(adc));
+	
+	if (adc == ADC_PERIPH_1) {
+		if (IS_ADC_CONVERSION(ADC->CFG_ADC1_b.SYSTEM_MODE)) {
+			ADC->ADC1_STOP_b.EN = TRUE;
+		}
+		while (ADC->BUSY_b.ADC1_BUSY) ;
+		
+		ADC->ADC1_FIFO_CLEAR_b.CLEAR = TRUE;
+		//udelay(1000);
+		ADC->ADC1_FIFO_CLEAR_b.CLEAR = FALSE;
+	} else {
+		if (IS_ADC_CONVERSION(ADC->CFG_ADC2_b.SYSTEM_MODE)) {
+			ADC->ADC2_STOP_b.EN = TRUE;
+		}
+		while (ADC->BUSY_b.ADC2_BUSY) ;
+			
+		ADC->ADC2_FIFO_CLEAR_b.CLEAR = TRUE;
+		//udelay(1000);
+		ADC->ADC2_FIFO_CLEAR_b.CLEAR = FALSE;
+	}	
 }
 
 BOOL ADC_IsBusy(uint8_t adc) {
-    assert_param(IS_ADC_ALL_PERIPH(adc));
-
-    if (adc == ADC_PERIPH_1) {
-        if (ADC->BUSY_b.ADC1_BUSY) {
-            return TRUE;
-        }
-    } else {
-        if (ADC->BUSY_b.ADC2_BUSY) {
-            return TRUE;
-        }
-    }
-
-    return FALSE;
+	assert_param(IS_ADC_ALL_PERIPH(adc));
+	
+	if (adc == ADC_PERIPH_1) {
+		if (ADC->BUSY_b.ADC1_BUSY) {
+			return TRUE;
+		}
+	} else {
+		if (ADC->BUSY_b.ADC2_BUSY) {
+			return TRUE;
+		}
+	}
+	
+	return FALSE;
 }
 
 /* return value is actual read data size */
 uint8_t ADC_Read(uint8_t adc, uint8_t size, ADC_Data* data) {
-    uint8_t count = 0;
-    uint8_t sysMode;
-    uint32_t tmp = 0;
-    assert_param(IS_ADC_ALL_PERIPH(adc));
-    assert_param(data);
-
-    if (adc == ADC_PERIPH_1) {
-        sysMode = ADC->CFG_ADC1_b.SYSTEM_MODE;
-    } else {
-        sysMode = ADC->CFG_ADC2_b.SYSTEM_MODE;
-    }
-
-    if ((sysMode == ADC_SYSTEM_MODE_SINGLE_CONV) ||
-        (sysMode == ADC_SYSTEM_MODE_CONTINUOUS_CONV)) {
-        while (count < size) {
-            if (adc == ADC_PERIPH_1) {
-                if (ADC->STATUS_b.ADC1_READ_EMPTY) {
-                    break;
-                }
-
-                tmp = ADC->ADC1_FIFO_READ;
-                (data + count)->channel = 1 << ((tmp&0xf000) >> 12);
-                (data + count++)->data = (tmp & 0xfff);
-            } else {
-                if (ADC->STATUS_b.ADC2_READ_EMPTY) {
-                    break;
-                }
-                tmp = ADC->ADC2_FIFO_READ;
-                (data + count)->channel = 1 << ((tmp&0xf000) >> 12);
-                (data + count++)->data = (tmp & 0xfff);
-            }
-        }
-    } else if (sysMode == ADC_CALIBRATION_OFFSET) {
-        if (adc == ADC_PERIPH_1) {
-            if (!ADC->BUSY_b.ADC1_BUSY) {
-                (data + count)->channel = ADC_CHANNEL_CALIBRATION;
-                (data + count++)->data = ADC->ADC1_OUT_OFFSET_CALIBRATION;
-          }
-        } else {
-            if (!ADC->BUSY_b.ADC2_BUSY) {
-                (data + count)->channel = ADC_CHANNEL_CALIBRATION;
-                (data + count++)->data = ADC->ADC2_OUT_OFFSET_CALIBRATION;
-          }
-        }
-    } else if (sysMode == ADC_CALIBRATION_NEGTIVE_GAIN) {
-        if (adc == ADC_PERIPH_1) {
-            if (!ADC->BUSY_b.ADC1_BUSY) {
-                (data + count)->channel = ADC_CHANNEL_CALIBRATION;
-                (data + count++)->data = ADC->ADC1_OUT_NEGTIVE_GAIN_CALIBRATION;
-            }
-        } else {
-            if (!ADC->BUSY_b.ADC2_BUSY) {
-              (data + count)->channel = ADC_CHANNEL_CALIBRATION;
-                (data + count++)->data = ADC->ADC2_OUT_NEGTIVE_GAIN_CALIBRATION;
-          }
-        }
-    } else {
-        if (adc == ADC_PERIPH_1) {
-            if (!ADC->BUSY_b.ADC1_BUSY) {
-                (data + count)->channel = ADC_CHANNEL_CALIBRATION;
-                (data + count++)->data = ADC->ADC1_OUT_POSITIVE_GAIN_CALIBRATION;
-            }
-        } else {
-            if (!ADC->BUSY_b.ADC2_BUSY) {
-              (data + count)->channel = ADC_CHANNEL_CALIBRATION;
-                (data + count++)->data = ADC->ADC2_OUT_POSITIVE_GAIN_CALIBRATION;
-          }
-        }
-    }
-
-    return count;
+	uint8_t count = 0;
+	uint8_t sysMode;
+	uint32_t tmp = 0;
+	assert_param(IS_ADC_ALL_PERIPH(adc));
+	assert_param(data);
+	
+	if (adc == ADC_PERIPH_1) {
+		sysMode = ADC->CFG_ADC1_b.SYSTEM_MODE;
+	} else {
+		sysMode = ADC->CFG_ADC2_b.SYSTEM_MODE;
+	}
+	
+	if ((sysMode == ADC_SYSTEM_MODE_SINGLE_CONV) ||
+		(sysMode == ADC_SYSTEM_MODE_CONTINUOUS_CONV)) {
+		while (count < size) {
+			if (adc == ADC_PERIPH_1) {
+				if (ADC->STATUS_b.ADC1_READ_EMPTY) {
+					break;
+				}
+				
+				tmp = ADC->ADC1_FIFO_READ;
+				(data + count)->channel = 1 << ((tmp&0xf000) >> 12);
+				(data + count++)->data = (tmp & 0xfff);
+			} else {
+				if (ADC->STATUS_b.ADC2_READ_EMPTY) {
+					break;
+				}
+				tmp = ADC->ADC2_FIFO_READ;
+				(data + count)->channel = 1 << ((tmp&0xf000) >> 12);
+				(data + count++)->data = (tmp & 0xfff);
+			}
+		}
+	} else if (sysMode == ADC_CALIBRATION_OFFSET) {
+		if (adc == ADC_PERIPH_1) {
+			if (!ADC->BUSY_b.ADC1_BUSY) {
+				(data + count)->channel = ADC_CHANNEL_CALIBRATION;
+				(data + count++)->data = ADC->ADC1_OUT_OFFSET_CALIBRATION;
+		  }	
+		} else {
+			if (!ADC->BUSY_b.ADC2_BUSY) {
+				(data + count)->channel = ADC_CHANNEL_CALIBRATION;
+				(data + count++)->data = ADC->ADC2_OUT_OFFSET_CALIBRATION;
+		  }
+		}
+	} else if (sysMode == ADC_CALIBRATION_NEGTIVE_GAIN) {	
+		if (adc == ADC_PERIPH_1) {
+			if (!ADC->BUSY_b.ADC1_BUSY) {
+				(data + count)->channel = ADC_CHANNEL_CALIBRATION;
+				(data + count++)->data = ADC->ADC1_OUT_NEGTIVE_GAIN_CALIBRATION;
+			}	
+		} else {
+			if (!ADC->BUSY_b.ADC2_BUSY) {
+			  (data + count)->channel = ADC_CHANNEL_CALIBRATION;
+				(data + count++)->data = ADC->ADC2_OUT_NEGTIVE_GAIN_CALIBRATION;
+		  }
+		}
+	} else {
+		if (adc == ADC_PERIPH_1) {
+			if (!ADC->BUSY_b.ADC1_BUSY) {
+				(data + count)->channel = ADC_CHANNEL_CALIBRATION;
+				(data + count++)->data = ADC->ADC1_OUT_POSITIVE_GAIN_CALIBRATION;
+			}	
+		} else {
+			if (!ADC->BUSY_b.ADC2_BUSY) {
+			  (data + count)->channel = ADC_CHANNEL_CALIBRATION;
+				(data + count++)->data = ADC->ADC2_OUT_POSITIVE_GAIN_CALIBRATION;
+		  }
+		}
+	}
+	
+	return count;
 }

bsp/CME_M7/StdPeriph_Driver/src/cmem7_aes.c

@@ -1,53 +1,53 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_aes.c
-    *
-    * @brief    CMEM7 AES source file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_aes.c
+	*
+	* @brief    CMEM7 AES source file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #include "cmem7_aes.h"
 
 BOOL AES_Decrypt(const void *src, void *dst, uint32_t len)
 {
-    uint32_t *po = dst;
-    const uint32_t *pi = src;
+	uint32_t *po = dst;
+	const uint32_t *pi = src;
 
-    if (len & 0xF)
-        return FALSE;
+	if (len & 0xF)
+		return FALSE;
 
-    AES->FIFO_CLEAR = 1;
-    AES->FIFO_CLEAR = 0;
-    GLOBAL_CTRL->AES_BURST_TYPE = 0x1;                      // Cannot be 0
-    while (len > 0) {
-        while (0 == GLOBAL_CTRL->AES_STATUS_b.IDLE);        // 0x41007010
-        udelay(2);
-        GLOBAL_CTRL->AES_TARGET_ADDR = (uint32_t)po;        // 0x41800000;
-        po += 4;
-        len -= 4 * sizeof(uint32_t);
-        while (0 == GLOBAL_CTRL->AES_STATUS_b.RD_EMPTY);    // 0x41007010
-        AES->FIFO = *pi++;
-        AES->FIFO = *pi++;
-        AES->FIFO = *pi++;
-        AES->FIFO = *pi++;
-    }
-    return TRUE;
+	AES->FIFO_CLEAR = 1;
+	AES->FIFO_CLEAR = 0;
+	GLOBAL_CTRL->AES_BURST_TYPE = 0x1;						// Cannot be 0
+	while (len > 0) {
+		while (0 == GLOBAL_CTRL->AES_STATUS_b.IDLE);		// 0x41007010
+		udelay(2);
+		GLOBAL_CTRL->AES_TARGET_ADDR = (uint32_t)po;		// 0x41800000;
+		po += 4;
+		len -= 4 * sizeof(uint32_t);
+		while (0 == GLOBAL_CTRL->AES_STATUS_b.RD_EMPTY);	// 0x41007010
+		AES->FIFO = *pi++;
+		AES->FIFO = *pi++;
+		AES->FIFO = *pi++;
+		AES->FIFO = *pi++;
+	}
+	return TRUE;
 }

bsp/CME_M7/StdPeriph_Driver/src/cmem7_can.c

@@ -1,36 +1,36 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_can.c
-    *
-    * @brief    CMEM7 CAN source file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_can.c
+	*
+	* @brief    CMEM7 CAN source file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #include "cmem7_can.h"
 
 typedef struct {
   union {
     __IO uint8_t   FI;                        /*!< Transmit Frame Information if writting or Receive Frame Information
                                                    if reading, ACR[0] if reset mode                                      */
-
+                                                    
     struct {
       __IO uint8_t   DLC        :  4;         /*!< byte number in the data                                               */
            uint8_t              :  2;
@@ -42,12 +42,12 @@ typedef struct {
 } CAN_FRAME_INFO;
 
 typedef struct {
-    union {
+	union {
     uint16_t  ID;                             /*!< ID                                  */
-
+    
     struct {
       uint16_t  ID28_21   :  8;               /*!< ID28 to ID21                        */
-      uint16_t            :  4;
+      uint16_t            :  4;               
       uint16_t  RTR       :  1;               /*!< if remote frame                     */
       uint16_t  ID20_18   :  3;               /*!< ID20 to ID18                        */
     } ID_b;                                   /*!< BitSize                             */
@@ -57,12 +57,12 @@ typedef struct {
 typedef struct {
   union {
     uint32_t  ID;                             /*!< ID                                  */
-
+    
     struct {
       uint32_t  ID28_21   :  8;               /*!< ID28 to ID21                        */
       uint32_t  ID20_13   :  8;               /*!< ID20 to ID13                        */
-            uint32_t  ID12_5    :  8;               /*!< ID12 to ID5                         */
-            uint32_t            :  2;
+			uint32_t  ID12_5    :  8;               /*!< ID12 to ID5                         */
+			uint32_t            :  2;
       uint32_t  RTR       :  1;               /*!< if remote frame                     */
       uint32_t  ID4_0     :  5;               /*!< ID4 to ID0                          */
     } ID_b;                                   /*!< BitSize                             */
@@ -80,307 +80,307 @@ typedef struct {
 #define CAN_OCR_CLOCK              0x03
 
 static BOOL can_SetFilter(CAN0_Type* CANx, CAN_FILTER *f1, CAN_FILTER *f2) {
-    if (!f1) {
-        return FALSE;
-    }
-
-    if (!IS_CAN_FLT_TYPE(f1->type)) {
-        return FALSE;
-    }
-
-    if(IS_CAN_FLT_DUAL(f1->type)) {
-        if (!f2 || IS_CAN_FLT_SINGLE(f2->type)) {
-            return FALSE;
-        }
-    }
-
-    if (f1->type == CAN_FLT_STANDARD_SINGLE) {
-      CANx->FI_OR_ACR0 = f1->ACCEPT.sf.ID28_18 >> 3;
-        CANx->DI0_OR_ACR1 = (f1->ACCEPT.sf.ID28_18 & 0x07) << 5;
-        CANx->DI0_OR_ACR1 |= f1->ACCEPT.sf.RTR << 4;
-        CANx->DI1_OR_ACR2 = f1->ACCEPT.sf.data1;
-        CANx->DI2_OR_ACR3 = f1->ACCEPT.sf.data2;
-
-        CANx->DI3_OR_AMR0 = f1->MASK.sf.ID28_18 >> 3;
-        CANx->DI4_OR_AMR1 = (f1->MASK.sf.ID28_18 & 0x07) << 5;
-        CANx->DI4_OR_AMR1 |= f1->MASK.sf.RTR << 4;
-        CANx->DI5_OR_AMR2 = f1->MASK.sf.data1;
-        CANx->DI6_OR_AMR3 = f1->MASK.sf.data2;
-    } else if (f1->type == CAN_FLT_STANDARD_DUAL) {
-      CANx->FI_OR_ACR0 = f1->ACCEPT.sf.ID28_18 >> 3;
-        CANx->DI0_OR_ACR1 = (f1->ACCEPT.sf.ID28_18 & 0x07) << 5;
-        CANx->DI0_OR_ACR1 |= f1->ACCEPT.sf.RTR << 4;
-        CANx->DI0_OR_ACR1 |= f1->ACCEPT.sf.data1 >> 4;
-        CANx->DI2_OR_ACR3 = f1->ACCEPT.sf.data1 & 0x0F;
-
-        CANx->DI3_OR_AMR0 = f1->MASK.sf.ID28_18 >> 3;
-        CANx->DI4_OR_AMR1 = (f1->MASK.sf.ID28_18 & 0x07) << 5;
-        CANx->DI4_OR_AMR1 |= f1->MASK.sf.RTR << 4;
-        CANx->DI4_OR_AMR1 = f1->MASK.sf.data1 >> 4;
-        CANx->DI6_OR_AMR3 = f1->MASK.sf.data1 & 0x0F;
-    } else if (f1->type == CAN_FLT_EXTENDED_SINGLE) {
-      CANx->FI_OR_ACR0 = f1->ACCEPT.ef.ID28_13 >> 8;
-        CANx->DI0_OR_ACR1 = f1->ACCEPT.ef.ID28_13 & 0xFF;
-        CANx->DI1_OR_ACR2 = f1->ACCEPT.ef.ID12_0 >> 5;
-        CANx->DI2_OR_ACR3 = (f1->ACCEPT.ef.ID12_0 & 0x1F) << 3;
-        CANx->DI2_OR_ACR3 |= f1->ACCEPT.ef.RTR << 2;
-
-        CANx->DI3_OR_AMR0 = f1->MASK.ef.ID28_13 >> 8;
-        CANx->DI4_OR_AMR1 = f1->MASK.ef.ID28_13 & 0xFF;
-        CANx->DI5_OR_AMR2 = f1->MASK.ef.ID12_0 >> 5;
-        CANx->DI6_OR_AMR3 = (f1->MASK.ef.ID12_0 & 0x1F) << 3;
-        CANx->DI6_OR_AMR3 |= f1->MASK.ef.RTR << 2;
-    } else {
-      CANx->FI_OR_ACR0 = f1->ACCEPT.ef.ID28_13 >> 8;
-        CANx->DI0_OR_ACR1 = f1->ACCEPT.ef.ID28_13 & 0xFF;
-
-        CANx->DI3_OR_AMR0 = f1->MASK.ef.ID28_13 >> 8;
-        CANx->DI4_OR_AMR1 = f1->MASK.ef.ID28_13 & 0xFF;
-    }
-
-    if (IS_CAN_FLT_DUAL(f1->type)) {
-        if (f2->type == CAN_FLT_STANDARD_DUAL) {
-            CANx->DI1_OR_ACR2 = f2->ACCEPT.sf.ID28_18 >> 3;
-            CANx->DI2_OR_ACR3 |= (f2->ACCEPT.sf.ID28_18 & 0x07) << 5;
-            CANx->DI2_OR_ACR3 |= f2->ACCEPT.sf.RTR << 4;
-
-            CANx->DI5_OR_AMR2 = f2->MASK.sf.ID28_18 >> 3;
-            CANx->DI6_OR_AMR3 |= (f2->MASK.sf.ID28_18 & 0x07) << 5;
-            CANx->DI6_OR_AMR3 |= f2->MASK.sf.RTR << 4;
-        } else {
-            CANx->DI1_OR_ACR2 = f2->ACCEPT.ef.ID28_13 >> 8;
-            CANx->DI2_OR_ACR3 = f2->ACCEPT.ef.ID28_13 & 0xFF;
-
-            CANx->DI5_OR_AMR2 = f2->MASK.ef.ID28_13 >> 8;
-            CANx->DI6_OR_AMR3 = f2->MASK.ef.ID28_13 & 0xFF;
-        }
-    }
-
-    if (IS_CAN_FLT_SINGLE(f1->type)) {
-        CANx->MODE_b.AFM = 1;
-    } else {
-      CANx->MODE_b.AFM = 0;
-    }
-
-    return TRUE;
+	if (!f1) {
+		return FALSE;
+	}
+	
+	if (!IS_CAN_FLT_TYPE(f1->type)) {
+		return FALSE;
+	}
+	
+	if(IS_CAN_FLT_DUAL(f1->type)) {
+		if (!f2 || IS_CAN_FLT_SINGLE(f2->type)) {
+			return FALSE;
+		}
+	}
+	
+	if (f1->type == CAN_FLT_STANDARD_SINGLE) {
+	  CANx->FI_OR_ACR0 = f1->ACCEPT.sf.ID28_18 >> 3;
+		CANx->DI0_OR_ACR1 = (f1->ACCEPT.sf.ID28_18 & 0x07) << 5;
+		CANx->DI0_OR_ACR1 |= f1->ACCEPT.sf.RTR << 4;
+		CANx->DI1_OR_ACR2 = f1->ACCEPT.sf.data1;
+		CANx->DI2_OR_ACR3 = f1->ACCEPT.sf.data2;
+		
+		CANx->DI3_OR_AMR0 = f1->MASK.sf.ID28_18 >> 3;
+		CANx->DI4_OR_AMR1 = (f1->MASK.sf.ID28_18 & 0x07) << 5;
+		CANx->DI4_OR_AMR1 |= f1->MASK.sf.RTR << 4;
+		CANx->DI5_OR_AMR2 = f1->MASK.sf.data1;
+		CANx->DI6_OR_AMR3 = f1->MASK.sf.data2;
+	} else if (f1->type == CAN_FLT_STANDARD_DUAL) {
+	  CANx->FI_OR_ACR0 = f1->ACCEPT.sf.ID28_18 >> 3;
+		CANx->DI0_OR_ACR1 = (f1->ACCEPT.sf.ID28_18 & 0x07) << 5;
+		CANx->DI0_OR_ACR1 |= f1->ACCEPT.sf.RTR << 4;
+		CANx->DI0_OR_ACR1 |= f1->ACCEPT.sf.data1 >> 4;
+		CANx->DI2_OR_ACR3 = f1->ACCEPT.sf.data1 & 0x0F;
+		
+		CANx->DI3_OR_AMR0 = f1->MASK.sf.ID28_18 >> 3;
+		CANx->DI4_OR_AMR1 = (f1->MASK.sf.ID28_18 & 0x07) << 5;
+		CANx->DI4_OR_AMR1 |= f1->MASK.sf.RTR << 4;
+		CANx->DI4_OR_AMR1 = f1->MASK.sf.data1 >> 4;
+		CANx->DI6_OR_AMR3 = f1->MASK.sf.data1 & 0x0F;
+	} else if (f1->type == CAN_FLT_EXTENDED_SINGLE) {
+	  CANx->FI_OR_ACR0 = f1->ACCEPT.ef.ID28_13 >> 8;
+		CANx->DI0_OR_ACR1 = f1->ACCEPT.ef.ID28_13 & 0xFF;
+		CANx->DI1_OR_ACR2 = f1->ACCEPT.ef.ID12_0 >> 5;
+		CANx->DI2_OR_ACR3 = (f1->ACCEPT.ef.ID12_0 & 0x1F) << 3;
+		CANx->DI2_OR_ACR3 |= f1->ACCEPT.ef.RTR << 2;
+		
+		CANx->DI3_OR_AMR0 = f1->MASK.ef.ID28_13 >> 8;
+		CANx->DI4_OR_AMR1 = f1->MASK.ef.ID28_13 & 0xFF;
+		CANx->DI5_OR_AMR2 = f1->MASK.ef.ID12_0 >> 5;
+		CANx->DI6_OR_AMR3 = (f1->MASK.ef.ID12_0 & 0x1F) << 3;
+		CANx->DI6_OR_AMR3 |= f1->MASK.ef.RTR << 2;
+	} else {
+	  CANx->FI_OR_ACR0 = f1->ACCEPT.ef.ID28_13 >> 8;
+		CANx->DI0_OR_ACR1 = f1->ACCEPT.ef.ID28_13 & 0xFF;
+		
+		CANx->DI3_OR_AMR0 = f1->MASK.ef.ID28_13 >> 8;
+		CANx->DI4_OR_AMR1 = f1->MASK.ef.ID28_13 & 0xFF;
+	}
+	
+	if (IS_CAN_FLT_DUAL(f1->type)) {
+		if (f2->type == CAN_FLT_STANDARD_DUAL) {
+			CANx->DI1_OR_ACR2 = f2->ACCEPT.sf.ID28_18 >> 3;
+			CANx->DI2_OR_ACR3 |= (f2->ACCEPT.sf.ID28_18 & 0x07) << 5;
+			CANx->DI2_OR_ACR3 |= f2->ACCEPT.sf.RTR << 4;
+			
+			CANx->DI5_OR_AMR2 = f2->MASK.sf.ID28_18 >> 3;
+			CANx->DI6_OR_AMR3 |= (f2->MASK.sf.ID28_18 & 0x07) << 5;
+			CANx->DI6_OR_AMR3 |= f2->MASK.sf.RTR << 4;
+		} else {
+			CANx->DI1_OR_ACR2 = f2->ACCEPT.ef.ID28_13 >> 8;
+			CANx->DI2_OR_ACR3 = f2->ACCEPT.ef.ID28_13 & 0xFF;
+			
+			CANx->DI5_OR_AMR2 = f2->MASK.ef.ID28_13 >> 8;
+			CANx->DI6_OR_AMR3 = f2->MASK.ef.ID28_13 & 0xFF;
+		}
+	}
+	
+	if (IS_CAN_FLT_SINGLE(f1->type)) {
+		CANx->MODE_b.AFM = 1;
+	} else {
+	  CANx->MODE_b.AFM = 0;
+	}
+	
+	return TRUE;
 }
 
-BOOL CAN_Init(CAN0_Type* CANx, CAN_InitTypeDef* Init,
+BOOL CAN_Init(CAN0_Type* CANx, CAN_InitTypeDef* Init, 
   CAN_FILTER *f1, CAN_FILTER *f2) {
-    assert_param(IS_CAN_ALL_PERIPH(CANx));
-    assert_param(Init);
-    assert_param(IS_CAN_CDR_DIV(Init->CAN_ClockDiv));
-
-    /* Quit to sleep mode in operation mode */
-    if (CANx->MODE_b.SM) {
-        CANx->MODE_b.RM = FALSE;
-        CANx->MODE_b.SM = FALSE;
-    }
-
-    /* switch to reset mode to set parameter */
-    CANx->MODE_b.RM = TRUE;
-
-    /* disable all interrupts and clear except receive interrupt */
-    {
-        uint8_t tmp;
-        CANx->INT_EN &= ~CAN_INT_All;
-        tmp = CANx->INT;
-        tmp = tmp;
-    }
-
-    CANx->MODE_b.LOM = (Init->CAN_TxEn) ? FALSE : TRUE;
-
-    CANx->MODE_b.STM = Init->CAN_Loopback;
-
-    CANx->CDR_b.OFF = FALSE;
-    CANx->CDR_b.DIVIDER = Init->CAN_ClockDiv;
-
-    CANx->BTR0_b.BRP = Init->CAN_Prescaler;
-    CANx->BTR0_b.SJW = Init->CAN_SJW;
-
-    CANx->BTR1_b.TSEG1 = Init->CAN_TSEG1;
-    CANx->BTR1_b.TSEG2 = Init->CAN_TSEG2;
-    CANx->BTR1_b.SAM = !Init->CAN_HighSpeed;
-
-    CANx->OCR_b.MODE = CAN_OCR_CLOCK;
+	assert_param(IS_CAN_ALL_PERIPH(CANx));
+	assert_param(Init);
+	assert_param(IS_CAN_CDR_DIV(Init->CAN_ClockDiv));
+		
+	/* Quit to sleep mode in operation mode */
+	if (CANx->MODE_b.SM) {
+		CANx->MODE_b.RM = FALSE;
+		CANx->MODE_b.SM = FALSE;
+	}
+	
+	/* switch to reset mode to set parameter */
+	CANx->MODE_b.RM = TRUE;
 
+	/* disable all interrupts and clear except receive interrupt */
+	{
+		uint8_t tmp;
+		CANx->INT_EN &= ~CAN_INT_All;
+		tmp = CANx->INT;
+		tmp = tmp;
+	}
+	
+	CANx->MODE_b.LOM = (Init->CAN_TxEn) ? FALSE : TRUE;
+	
+	CANx->MODE_b.STM = Init->CAN_Loopback;
+		
+	CANx->CDR_b.OFF = FALSE;
+	CANx->CDR_b.DIVIDER = Init->CAN_ClockDiv;
+	
+	CANx->BTR0_b.BRP = Init->CAN_Prescaler;
+	CANx->BTR0_b.SJW = Init->CAN_SJW;
+	
+	CANx->BTR1_b.TSEG1 = Init->CAN_TSEG1;
+	CANx->BTR1_b.TSEG2 = Init->CAN_TSEG2;
+	CANx->BTR1_b.SAM = !Init->CAN_HighSpeed;
+	
+	CANx->OCR_b.MODE = CAN_OCR_CLOCK;
+	
   if (!can_SetFilter(CANx, f1, f2)) {
-        return FALSE;
-    }
+		return FALSE;
+	}
+	
+	/* switch to operation mode */
+	CANx->MODE_b.RM = FALSE;
 
-    /* switch to operation mode */
-    CANx->MODE_b.RM = FALSE;
-
-    return TRUE;
+	return TRUE;
 }
 
 void CAN_SetSleepMode(CAN0_Type* CANx, BOOL enable) {
-    assert_param(IS_CAN_ALL_PERIPH(CANx));
-
-    /* switch to operation mode */
-    CANx->MODE_b.RM = FALSE;
-
-    CANx->MODE_b.SM = enable;
+	assert_param(IS_CAN_ALL_PERIPH(CANx));
+	
+	/* switch to operation mode */
+	CANx->MODE_b.RM = FALSE;
+	
+	CANx->MODE_b.SM = enable;
 }
 
 void CAN_EnableInt(CAN0_Type* CANx, uint32_t Int, BOOL enable) {
   assert_param(IS_CAN_ALL_PERIPH(CANx));
-    assert_param(IS_CAN_INT(Int));
-
-    if (enable) {
-        CANx->INT_EN |= CAN_INT_All;
-    } else {
-        CANx->INT_EN &= ~CAN_INT_All;
-    }
+	assert_param(IS_CAN_INT(Int));
+	
+	if (enable) {
+		CANx->INT_EN |= CAN_INT_All;
+	} else {
+		CANx->INT_EN &= ~CAN_INT_All;
+	}
 }
 
 uint8_t CAN_GetIntStatus(CAN0_Type* CANx) {
-    assert_param(IS_CAN_ALL_PERIPH(CANx));
-
-    return CANx->INT;
+	assert_param(IS_CAN_ALL_PERIPH(CANx));
+	
+	return CANx->INT;
 }
 
 BOOL CAN_Transmit(CAN0_Type* CANx, CAN_Frame* frame) {
-    assert_param(IS_CAN_ALL_PERIPH(CANx));
+	assert_param(IS_CAN_ALL_PERIPH(CANx));
+	
+	if (!frame) {
+		return FALSE;
+	}
+	
+	if (CANx->MODE_b.LOM) {
+		return FALSE;
+	}
+	
+	if (CANx->MODE_b.SM) {
+		CANx->MODE_b.RM = FALSE;
+		CANx->MODE_b.SM = FALSE;
+	}
+	
+	{
+		CAN_FRAME_INFO fi;
+		
+		fi.U.FI_b.FF = !frame->SFF;
+		fi.U.FI_b.RTR = frame->RTR;
+		fi.U.FI_b.DLC = frame->DLC;
 
-    if (!frame) {
-        return FALSE;
-    }
-
-    if (CANx->MODE_b.LOM) {
-        return FALSE;
-    }
-
-    if (CANx->MODE_b.SM) {
-        CANx->MODE_b.RM = FALSE;
-        CANx->MODE_b.SM = FALSE;
-    }
-
-    {
-        CAN_FRAME_INFO fi;
-
-        fi.U.FI_b.FF = !frame->SFF;
-        fi.U.FI_b.RTR = frame->RTR;
-        fi.U.FI_b.DLC = frame->DLC;
-
-        CANx->FI_OR_ACR0 = fi.U.FI;
+		CANx->FI_OR_ACR0 = fi.U.FI;
   }
-
+	
   if (frame->SFF) {
-        CAN_STANDARD_ID id;
-
-        id.U.ID_b.ID28_21 = frame->Id >> 3;
-        id.U.ID_b.RTR = frame->RTR;
-        id.U.ID_b.ID20_18 = frame->Id & 0x07;
-
-        CANx->DI0_OR_ACR1 = id.U.ID & 0xFF;
-        CANx->DI1_OR_ACR2 = id.U.ID >> 8;
-
-        CANx->DI2_OR_ACR3 = frame->Data[0];
-        CANx->DI3_OR_AMR0 = frame->Data[1];
-        CANx->DI4_OR_AMR1 = frame->Data[2];
-        CANx->DI5_OR_AMR2 = frame->Data[3];
-        CANx->DI6_OR_AMR3 = frame->Data[4];
-        CANx->DI7 = frame->Data[5];
-        CANx->DI8 = frame->Data[6];
-        CANx->DI9 = frame->Data[7];
-    } else {
-        CAN_EXTENDED_ID id;
-
-        id.U.ID_b.ID28_21 = frame->Id >> 21;
-        id.U.ID_b.ID20_13 = (frame->Id >> 13) & 0xFF;
-        id.U.ID_b.ID12_5 = (frame->Id >> 5) & 0xFF;
-        id.U.ID_b.RTR = frame->RTR;
-        id.U.ID_b.ID4_0 = frame->Id & 0x1F;
-
-        CANx->DI0_OR_ACR1 = id.U.ID & 0xFF;
-        CANx->DI1_OR_ACR2 = (id.U.ID >> 8) & 0xFF;
-        CANx->DI2_OR_ACR3 = (id.U.ID >> 16) & 0xFF;
-        CANx->DI3_OR_AMR0 = (id.U.ID >> 24) & 0xFF;
-
-        CANx->DI4_OR_AMR1 = frame->Data[0];
-        CANx->DI5_OR_AMR2 = frame->Data[1];
-        CANx->DI6_OR_AMR3 = frame->Data[2];
-        CANx->DI7 = frame->Data[3];
-        CANx->DI8 = frame->Data[4];
-        CANx->DI9 = frame->Data[5];
-        CANx->DI10 = frame->Data[6];
-        CANx->DI11 = frame->Data[7];
-    }
+		CAN_STANDARD_ID id;
+		
+		id.U.ID_b.ID28_21 = frame->Id >> 3;
+		id.U.ID_b.RTR = frame->RTR;
+		id.U.ID_b.ID20_18 = frame->Id & 0x07;
+		
+		CANx->DI0_OR_ACR1 = id.U.ID & 0xFF;
+		CANx->DI1_OR_ACR2 = id.U.ID >> 8;
+		
+		CANx->DI2_OR_ACR3 = frame->Data[0];
+		CANx->DI3_OR_AMR0 = frame->Data[1];
+		CANx->DI4_OR_AMR1 = frame->Data[2];
+		CANx->DI5_OR_AMR2 = frame->Data[3];
+		CANx->DI6_OR_AMR3 = frame->Data[4];
+		CANx->DI7 = frame->Data[5];
+		CANx->DI8 = frame->Data[6];
+		CANx->DI9 = frame->Data[7];
+	} else {
+		CAN_EXTENDED_ID id;
+		
+		id.U.ID_b.ID28_21 = frame->Id >> 21;
+		id.U.ID_b.ID20_13 = (frame->Id >> 13) & 0xFF;
+		id.U.ID_b.ID12_5 = (frame->Id >> 5) & 0xFF;
+		id.U.ID_b.RTR = frame->RTR;
+		id.U.ID_b.ID4_0 = frame->Id & 0x1F;
+		
+		CANx->DI0_OR_ACR1 = id.U.ID & 0xFF;
+		CANx->DI1_OR_ACR2 = (id.U.ID >> 8) & 0xFF;
+		CANx->DI2_OR_ACR3 = (id.U.ID >> 16) & 0xFF;
+		CANx->DI3_OR_AMR0 = (id.U.ID >> 24) & 0xFF;
+		
+		CANx->DI4_OR_AMR1 = frame->Data[0];
+		CANx->DI5_OR_AMR2 = frame->Data[1];
+		CANx->DI6_OR_AMR3 = frame->Data[2];
+		CANx->DI7 = frame->Data[3];
+		CANx->DI8 = frame->Data[4];
+		CANx->DI9 = frame->Data[5];
+		CANx->DI10 = frame->Data[6];
+		CANx->DI11 = frame->Data[7];
+	}
 
   if (CANx->MODE_b.STM) {
-      CANx->CMD_b.SSR = TRUE;
-    } else {
-        CANx->CMD_b.TR = TRUE;
-    }
+	  CANx->CMD_b.SSR = TRUE;
+	} else {
+		CANx->CMD_b.TR = TRUE;
+	}
 
   return TRUE;
 }
 
 BOOL CAN_Receive(CAN0_Type* CANx, CAN_Frame* frame) {
-    assert_param(IS_CAN_ALL_PERIPH(CANx));
-
-    if (!frame) {
-        return FALSE;
-    }
-
-    if (CANx->MODE_b.SM) {
-        CANx->MODE_b.RM = FALSE;
-        CANx->MODE_b.SM = FALSE;
-    }
-
-    {
-        CAN_FRAME_INFO fi;
-
-        fi.U.FI = CANx->FI_OR_ACR0;
-
-        frame->SFF = fi.U.FI_b.FF ? FALSE : TRUE;
-        frame->RTR = fi.U.FI_b.RTR ? TRUE : FALSE;
-        frame->DLC = fi.U.FI_b.DLC;
+	assert_param(IS_CAN_ALL_PERIPH(CANx));
+	
+	if (!frame) {
+		return FALSE;
+	}
+	
+	if (CANx->MODE_b.SM) {
+		CANx->MODE_b.RM = FALSE;
+		CANx->MODE_b.SM = FALSE;
+	}
+	
+	{
+		CAN_FRAME_INFO fi;
+		
+		fi.U.FI = CANx->FI_OR_ACR0;
+		
+		frame->SFF = fi.U.FI_b.FF ? FALSE : TRUE;
+		frame->RTR = fi.U.FI_b.RTR ? TRUE : FALSE;
+		frame->DLC = fi.U.FI_b.DLC;
   }
-
+	
   if (frame->SFF) {
-        CAN_STANDARD_ID id;
-
-        id.U.ID = CANx->DI0_OR_ACR1;
-        id.U.ID |= CANx->DI1_OR_ACR2 << 8;
-
-        frame->Id = id.U.ID_b.ID28_21 << 3;
-        frame->Id |= id.U.ID_b.ID20_18;
-
-        frame->Data[0] = CANx->DI2_OR_ACR3;
-        frame->Data[1] = CANx->DI3_OR_AMR0;
-        frame->Data[2] = CANx->DI4_OR_AMR1;
-        frame->Data[3] = CANx->DI5_OR_AMR2;
-        frame->Data[4] = CANx->DI6_OR_AMR3;
-        frame->Data[5] = CANx->DI7;
-        frame->Data[6] = CANx->DI8;
-        frame->Data[7] = CANx->DI9;
-    } else {
-        CAN_EXTENDED_ID id;
-
-        id.U.ID = CANx->DI0_OR_ACR1;
-        id.U.ID |= CANx->DI1_OR_ACR2 << 8;
-        id.U.ID |= CANx->DI2_OR_ACR3 << 16;
-        id.U.ID |= CANx->DI3_OR_AMR0 << 24;
-
+		CAN_STANDARD_ID id;
+		
+		id.U.ID = CANx->DI0_OR_ACR1;
+		id.U.ID |= CANx->DI1_OR_ACR2 << 8;
+		
+		frame->Id = id.U.ID_b.ID28_21 << 3;
+		frame->Id |= id.U.ID_b.ID20_18;
+		
+		frame->Data[0] = CANx->DI2_OR_ACR3;
+		frame->Data[1] = CANx->DI3_OR_AMR0;
+		frame->Data[2] = CANx->DI4_OR_AMR1;
+		frame->Data[3] = CANx->DI5_OR_AMR2;
+		frame->Data[4] = CANx->DI6_OR_AMR3;
+		frame->Data[5] = CANx->DI7;
+		frame->Data[6] = CANx->DI8;
+		frame->Data[7] = CANx->DI9;
+	} else {
+		CAN_EXTENDED_ID id;
+		
+		id.U.ID = CANx->DI0_OR_ACR1;
+		id.U.ID |= CANx->DI1_OR_ACR2 << 8;
+		id.U.ID |= CANx->DI2_OR_ACR3 << 16;
+		id.U.ID |= CANx->DI3_OR_AMR0 << 24;
+		
     frame->Id = id.U.ID_b.ID28_21 << 21;
-        frame->Id |= id.U.ID_b.ID20_13 << 13;
-        frame->Id |= id.U.ID_b.ID12_5 << 5;
-        frame->Id |= id.U.ID_b.ID4_0;
-
-        frame->Data[0] = CANx->DI4_OR_AMR1;
-        frame->Data[1] = CANx->DI5_OR_AMR2;
-        frame->Data[2] = CANx->DI6_OR_AMR3;
-        frame->Data[3] = CANx->DI7;
-        frame->Data[4] = CANx->DI8;
-        frame->Data[5] = CANx->DI9;
-        frame->Data[6] = CANx->DI10;
-        frame->Data[7] = CANx->DI11;
-    }
+		frame->Id |= id.U.ID_b.ID20_13 << 13;
+		frame->Id |= id.U.ID_b.ID12_5 << 5;
+		frame->Id |= id.U.ID_b.ID4_0;
+		
+		frame->Data[0] = CANx->DI4_OR_AMR1;
+		frame->Data[1] = CANx->DI5_OR_AMR2;
+		frame->Data[2] = CANx->DI6_OR_AMR3;
+		frame->Data[3] = CANx->DI7;
+		frame->Data[4] = CANx->DI8;
+		frame->Data[5] = CANx->DI9;
+		frame->Data[6] = CANx->DI10;
+		frame->Data[7] = CANx->DI11;
+	}
 
   CANx->CMD_b.RRB = TRUE;
 
-  return TRUE;
+  return TRUE;	
 }
 

bsp/CME_M7/StdPeriph_Driver/src/cmem7_ddr.c

@@ -1,32 +1,32 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_ddr.c
-    *
-    * @brief    CMEM7 DDR source file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_ddr.c
+	*
+	* @brief    CMEM7 DDR source file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #include "cmem7_ddr.h"
 
-#define MAX(a, b)   ((a >= b) ? (a) : (b))
+#define MAX(a, b)	((a >= b) ? (a) : (b))
 #define CAL_DDR3_CL(cl)   ((cl>11)?(((cl-12)<<MR_CL_OFFSET)|0x4):((cl-4)<<MR_CL_OFFSET))
 
 #define CHIP_MIN_CAPACITY  32
@@ -40,8 +40,8 @@
 /** @defgroup DDR time
   * @{
   */
-  #define POWER_UP_NOP      200*1000        /*ns*//*JEDEC Standard No. 79-2E   page 17   */
-  #define PRE_ALL_NOP           400        /*ns*/
+  #define POWER_UP_NOP		200*1000        /*ns*//*JEDEC Standard No. 79-2E   page 17   */
+  #define PRE_ALL_NOP			400        /*ns*/
   #define POWER_UP_MIN_CK    200
   #define DDR2_TMRD                2            /*JEDEC Standard No. 79-2E   page 80   */
   #define DDR3_TMRD                4            /*JEDEC Standard No. 79-2E   page 80   */
@@ -50,41 +50,41 @@
   #define DDR3_TZQINIT_CK                512         /*JEDEC Standard No. 79-3E   page 171  table 68   */
   #define DDR3_TZQINIT                640   /*ns*/      /*JEDEC Standard No. 79-3E   page 171  table 68   */
   #define DDR3_TDLLK_CK                512         /*JEDEC Standard No. 79-3E   page 171  table 68   */
-  #define RSTH_NOP      500*1000        /*ns*//*JEDEC Standard No. 79-3E   page 20   */
+  #define RSTH_NOP		500*1000        /*ns*//*JEDEC Standard No. 79-3E   page 20   */
   #define DDR_TREF      7800 /*ns*/
   /**
   * @}
   */
 #ifndef NULL
-#define NULL    0
+#define	NULL	0
 #endif
 
 /** @defgroup DDRC_SW_PROC_CMD
   * @{
   */
 #define SW_CMD_NO_PARM        0
-#define SW_CMD_DES          0x0       /*des 5'b00000     [31:29]=3'b000           [28:0] DES time cke hold*/
-#define SW_CMD_NOP          0x20000000        /*nop 5'b00100     [31:29]=3'b001           [28:0] NOP time cke hold*/
-#define SW_CMD_DESCKE         0x40000000       /*descke 5'b01000     [31:29]=3'b010           [28:0] DES time change cke high*/
-#define SW_CMD_NOPCKE         0x60000000     /*nopcke 5'b01100     [31:29]=3'b011           [28:0] NOP time change cke high*/
-#define SW_CMD_PREA             0x80000000   /*nopcke 5'b10000     [31:27]=5'b10000           */
+#define SW_CMD_DES			0x0       /*des 5'b00000     [31:29]=3'b000           [28:0] DES time cke hold*/	
+#define SW_CMD_NOP			0x20000000        /*nop 5'b00100     [31:29]=3'b001           [28:0] NOP time cke hold*/		
+#define SW_CMD_DESCKE         0x40000000	   /*descke 5'b01000     [31:29]=3'b010           [28:0] DES time change cke high*/			
+#define SW_CMD_NOPCKE         0x60000000	 /*nopcke 5'b01100     [31:29]=3'b011           [28:0] NOP time change cke high*/	
+#define SW_CMD_PREA         	0x80000000	 /*nopcke 5'b10000     [31:27]=5'b10000           */	
 
-#define SW_CMD_MR           0x88000000      /*JEDEC Standard No. 79-2E   page 19   */
-#define SW_CMD_EMR1             0x88010000  /*JEDEC Standard No. 79-2E   page 19   */
-#define SW_CMD_EMR2             0x88020000
-#define SW_CMD_EMR3             0x88030000
-#define SW_CMD_EMR1_TEST  0x88010004
-#define SW_CMD_REF          0x90000000  /*REF 5'b10010     [31:27]=5'b10010       */
+#define SW_CMD_MR         	0x88000000		/*JEDEC Standard No. 79-2E   page 19   */
+#define SW_CMD_EMR1         	0x88010000	/*JEDEC Standard No. 79-2E   page 19   */
+#define SW_CMD_EMR2         	0x88020000
+#define SW_CMD_EMR3         	0x88030000
+#define SW_CMD_EMR1_TEST  0x88010004	
+#define SW_CMD_REF         	0x90000000  /*REF 5'b10010     [31:27]=5'b10010       */	
 
-#define SW_CMD_RSTH         0xb0000000  /*RSTH 5'b10110    [31:27]=5'b10110       */
-#define SW_CMD_ZQCL         0xb8000000  /*ZQCL 5'b10111    [31:27]=5'b10111       */
+#define SW_CMD_RSTH        	0xb0000000  /*RSTH 5'b10110    [31:27]=5'b10110       */	
+#define SW_CMD_ZQCL       	0xb8000000  /*ZQCL 5'b10111    [31:27]=5'b10111       */	
 
 #define SW_CMD_DLL_EN         0x880103C4
 #define SW_CMD_DLL_RST        0x88000953
 /**
   * @}
   */
-/** @defgroup DDR2  mode register
+/** @defgroup DDR2  mode register 
   * @{
   */
  /*JEDEC Standard    */
@@ -92,7 +92,7 @@
 #define MR_BURST_LEN_8          0x3
 #define MR_BT_SEQ                    0x0
 #define MR_BT_INT                    0x08
-#define MR_CL_OFFSET             4
+#define MR_CL_OFFSET             4 
 #define MR_TM_NORMAL            0
 #define MR_TM_TEST                 0x80
 #define MR_DLL_NO                   0
@@ -106,418 +106,418 @@
   */
 const uint8_t DDR2_MODE[BUS_WIDTH_MAX][CHIP_NUM_MAX][CHIP_TYPE_MAX]=
 {
-    {
-        {0x20,0x23,0x28,0x2a,0x30,0x21,0x22,0x29,0x2b,0x31,0xff},/*chip x1*/
-        {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff}/*chip x2*/
-    },/*bus width x8*/
+	{
+		{0x20,0x23,0x28,0x2a,0x30,0x21,0x22,0x29,0x2b,0x31,0xff},/*chip x1*/
+		{0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff}/*chip x2*/
+	},/*bus width x8*/
 
-    {
-        {0xff,0xff,0xff,0xff,0xff,0x25,0x26,0x2d,0x2f,0x33,0xff},/*chip x1*/
-        {0x24,0x27,0x2c,0x2e,0x32,0xff,0xff,0xff,0xff,0xff,0xff}/*chip x2*/
-    }/*bus width x16*/
+	{
+		{0xff,0xff,0xff,0xff,0xff,0x25,0x26,0x2d,0x2f,0x33,0xff},/*chip x1*/
+		{0x24,0x27,0x2c,0x2e,0x32,0xff,0xff,0xff,0xff,0xff,0xff}/*chip x2*/
+	}/*bus width x16*/
 };
 const uint8_t DDR3_MODE[BUS_WIDTH_MAX][CHIP_NUM_MAX][CHIP_TYPE_MAX]=
 {
-    {
-        {0xff,0x00,0x01,0x02,0x03,0xff,0x04,0x05,0x06,0x07,0x10},/*chip x1*/
-        {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff}/*chip x2*/
-    },/*bus width x8*/
+	{
+		{0xff,0x00,0x01,0x02,0x03,0xff,0x04,0x05,0x06,0x07,0x10},/*chip x1*/
+		{0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff}/*chip x2*/
+	},/*bus width x8*/
 
-    {
-        {0xff,0xff,0xff,0xff,0xff,0xff,0x0c,0x0d,0x0e,0x0f,0x11},/*chip x1*/
-        {0xff,0x08,0x09,0x0a,0x0b,0xff,0xff,0xff,0xff,0xff,0xff}/*chip x2*/
-    }/*bus width x16*/
+	{
+		{0xff,0xff,0xff,0xff,0xff,0xff,0x0c,0x0d,0x0e,0x0f,0x11},/*chip x1*/
+		{0xff,0x08,0x09,0x0a,0x0b,0xff,0xff,0xff,0xff,0xff,0xff}/*chip x2*/
+	}/*bus width x16*/
 };
 const DDR2MEM DDR2PREDEF[] = {
-    {
-// #define DDR2_400C            4   // sg5E //DDR2-400C CL=4, tCK=5000 ps (dev-brd using)
-        /*tCK*/ 5000,
-        /*tCL*/ 6,//4,
-        /*RCD*/4, /*RP*/4, /*RC*/13, /*RAS*/9, /*WR*/3, /*RRD*/2, /*WTR*/11, /*RTP*/4,
-        /*FAW*/10,
-    },
-
-    {
-// #define DDR2_800D            0   // sg25E //DDR2-800D CL=5, tCK=2500 ps
-        /*tCK*/ 2500,
-        /*tCL*/ 5, /*RCD*/5, /*RP*/5, /*RC*/24, //from sim model
-        /*RAS*/18, /*WR*/6, /*RRD*/4, /*WTR*/11, /*RTP*/5,
-        /*FAW*/30, //from sim model
-    }, {
-// #define DDR2_667C            1   // sg3E //DDR2-667C CL=4, tCK=3000 ps
-        /*tCK*/ 3000,
-        /*tCL*/ 4, /*RCD*/4, /*RP*/4, /*RC*/19, /*RAS*/15, /*WR*/5, /*RRD*/4, /*WTR*/10, /*RTP*/5,
-        /*FAW*/17,
-    }, {
-// #define DDR2_667D            2   // sg3 //DDR2-667D CL=5, tCK=3000 ps
-        /*tCK*/ 3000,
-        /*tCL*/ 5, /*RCD*/5, /*RP*/5, /*RC*/20, /*RAS*/15, /*WR*/5, /*RRD*/4, /*WTR*/3, /*RTP*/3,
-        /*FAW*/17,
-    }, {
-// #define DDR2_533C            3   // sg37E //DDR2-533C CL=4, tCK=3750 ps
-        /*tCK*/ 3750,
-        /*tCL*/ 4, /*RCD*/4, /*RP*/4, /*RC*/16, /*RAS*/12, /*WR*/4, /*RRD*/3, /*WTR*/9, /*RTP*/4,
-        /*FAW*/14,
-    },
+	{
+// #define DDR2_400C			4	// sg5E //DDR2-400C CL=4, tCK=5000 ps (dev-brd using)
+		/*tCK*/ 5000,
+		/*tCL*/ 6,//4,
+		/*RCD*/4, /*RP*/4, /*RC*/13, /*RAS*/9, /*WR*/3, /*RRD*/2, /*WTR*/11, /*RTP*/4,
+		/*FAW*/10,
+	},
+	 
+	{
+// #define DDR2_800D			0	// sg25E //DDR2-800D CL=5, tCK=2500 ps
+		/*tCK*/ 2500,
+		/*tCL*/ 5, /*RCD*/5, /*RP*/5, /*RC*/24, //from sim model
+		/*RAS*/18, /*WR*/6, /*RRD*/4, /*WTR*/11, /*RTP*/5,
+		/*FAW*/30, //from sim model
+	}, {
+// #define DDR2_667C			1	// sg3E //DDR2-667C CL=4, tCK=3000 ps
+		/*tCK*/ 3000,
+		/*tCL*/ 4, /*RCD*/4, /*RP*/4, /*RC*/19, /*RAS*/15, /*WR*/5, /*RRD*/4, /*WTR*/10, /*RTP*/5,
+		/*FAW*/17,
+	}, {
+// #define DDR2_667D			2	// sg3 //DDR2-667D CL=5, tCK=3000 ps
+		/*tCK*/ 3000,
+		/*tCL*/ 5, /*RCD*/5, /*RP*/5, /*RC*/20, /*RAS*/15, /*WR*/5, /*RRD*/4, /*WTR*/3, /*RTP*/3,
+		/*FAW*/17,
+	}, {
+// #define DDR2_533C			3	// sg37E //DDR2-533C CL=4, tCK=3750 ps
+		/*tCK*/ 3750,
+		/*tCL*/ 4, /*RCD*/4, /*RP*/4, /*RC*/16, /*RAS*/12, /*WR*/4, /*RRD*/3, /*WTR*/9, /*RTP*/4,
+		/*FAW*/14,
+	},
 };
 
 const DDR3MEM DDR3PREDEF[] = {
-    {
-// #define DDR3_400         14  //  Base on DDR3-800D (5-5-5) tCK=5ns
-        /*tCK*/ 2500,
-        /*tCL*//*9*/ 5, /*WCL*/7/*cwl should be 5 ,but phy has 2 cycles delay.So,wcl should plus the 2 cycles delay.*/ , /*RCD*//*9*/5, /*RAS*//*24*/8, /*RP*//*9*/5, /*RC*//*33*/10, /*RRD*/ 100,
-        /*FAW*//*30*/10, /*WR*/5/*10*/, /*RTP*/4, /*ZQCL*/256, /*ZQCS*/64,
-    }  ,
+	{
+// #define DDR3_400			14	//  Base on DDR3-800D (5-5-5) tCK=5ns
+		/*tCK*/ 2500,
+		/*tCL*//*9*/ 5, /*WCL*/7/*cwl should be 5 ,but phy has 2 cycles delay.So,wcl should plus the 2 cycles delay.*/ , /*RCD*//*9*/5, /*RAS*//*24*/8, /*RP*//*9*/5, /*RC*//*33*/10, /*RRD*/ 100,
+		/*FAW*//*30*/10, /*WR*/5/*10*/, /*RTP*/4, /*ZQCL*/256, /*ZQCS*/64,
+	}  ,
 
-    {
-// #define DDR3_667         15  //  Base on DDR3-800D (5-5-5) tCK=5ns
-        /*tCK*/ 3000,
-        /*tCL*//*9*/ 5, /*WCL*/7 /*cwl should be 5 ,but phy has 2 cycles delay.So,wcl should plus the 2 cycles delay.*/ , /*RCD*//*9*/5, /*RAS*//*24*/30, /*RP*//*9*/5, /*RC*//*33*/60, /*RRD*/16,
-        /*FAW*//*30*/17, /*WR*/5/*10*/, /*RTP*/4, /*ZQCL*/256, /*ZQCS*/64,
-    },
+	{
+// #define DDR3_667			15	//  Base on DDR3-800D (5-5-5) tCK=5ns
+		/*tCK*/ 3000,
+		/*tCL*//*9*/ 5, /*WCL*/7 /*cwl should be 5 ,but phy has 2 cycles delay.So,wcl should plus the 2 cycles delay.*/ , /*RCD*//*9*/5, /*RAS*//*24*/30, /*RP*//*9*/5, /*RC*//*33*/60, /*RRD*/16,
+		/*FAW*//*30*/17, /*WR*/5/*10*/, /*RTP*/4, /*ZQCL*/256, /*ZQCS*/64,
+	},
 
-    {
-// #define DDR3_2133N           0   // sg093 //DDR3-2133N (14-14-14) tCK=0.938ns
-        /*tCK*/ 938,
-        /*tCL*/ 14, /*WCL*/10, /*RCD*/14, /*RAS*/36, /*RP*/14, /*RC*/50, /*RRD*/7,
-        /*FAW*/38, /*WR*/16, /*RTP*/10, /*ZQCL*/342, /*ZQCS*/86,
-    }, {
-// #define DDR3_2133M           1   // sg093E //DDR3-2133M (13-13-13) tCK=0.938ns
-        /*tCK*/ 938,
-        /*tCL*/ 13, /*WCL*/10, /*RCD*/13, /*RAS*/36, /*RP*/13, /*RC*/49, /*RRD*/7,
-        /*FAW*/38, /*WR*/16, /*RTP*/10, /*ZQCL*/342, /*ZQCS*/86,
-    }, {
-// #define DDR3_2133L           2   // sg093F //DDR3-2133L (12-12-12) tCK=0.938ns
-        /*tCK*/ 938,
-        /*tCL*/ 12, /*WCL*/10, /*RCD*/12, /*RAS*/36, /*RP*/12, /*RC*/48, /*RRD*/7,
-        /*FAW*/38, /*WR*/16, /*RTP*/10, /*ZQCL*/342, /*ZQCS*/86,
-    }, {
-// #define DDR3_1866L           3   // sg107E //DDR3-1866L (12-12-12) tCK=1.07ns
-        /*tCK*/ 1070,
-        /*tCL*/ 12, /*WCL*/9, /*RCD*/12, /*RAS*/32, /*RP*/12, /*RC*/44, /*RRD*/6,
-        /*FAW*/33, /*WR*/14, /*RTP*/9, /*ZQCL*/300, /*ZQCS*/75,
-    }, {
-// #define DDR3_1866K           4   // sg107F //DDR3-1866K (11-11-11) tCK=1.07ns
-        /*tCK*/ 1070,
-        /*tCL*/ 11, /*WCL*/9, /*RCD*/11, /*RAS*/32, /*RP*/11, /*RC*/43, /*RRD*/6,
-        /*FAW*/33, /*WR*/14, /*RTP*/9, /*ZQCL*/300, /*ZQCS*/75,
-    }, {
-// #define DDR3_1600J           5   // sg125E //DDR3-1600J (10-10-10) tCK=1.25ns
-        /*tCK*/ 1250,
-        /*tCL*/ 10, /*WCL*/8, /*RCD*/10, /*RAS*/28, /*RP*/10, /*RC*/38, /*RRD*/6,
-        /*FAW*/32, /*WR*/12, /*RTP*/8, /*ZQCL*/256, /*ZQCS*/64,
-    }, {
-// #define DDR3_1600K           6   // sg125 //DDR3-1600K (11-11-11) tCK=1.25ns
-        /*tCK*/ 1250,
-        /*tCL*/ 11, /*WCL*/8, /*RCD*/11, /*RAS*/28, /*RP*/11, /*RC*/37, /*RRD*/6,
-        /*FAW*/32, /*WR*/12, /*RTP*/8, /*ZQCL*/256, /*ZQCS*/64,
-    }, {
-// #define DDR3_1333H           7   // sg15E //DDR3-1333H (9-9-9) tCK=1.5ns
-        /*tCK*/ 1500,
-        /*tCL*/ 9, /*WCL*/7, /*RCD*/9, /*RAS*/24, /*RP*/9, /*RC*/33, /*RRD*/5,
-        /*FAW*/30, /*WR*/10, /*RTP*/5, /*ZQCL*/256, /*ZQCS*/64,
-    }, {
-// #define DDR3_1333J           8   // sg15 //DDR3-1333J (10-10-10) tCK=1.5ns
-        /*tCK*/ 1500,
-        /*tCL*/ 10, /*WCL*/7, /*RCD*/10, /*RAS*/24, /*RP*/10, /*RC*/34, /*RRD*/5,
-        /*FAW*/30, /*WR*/10, /*RTP*/7, /*ZQCL*/256, /*ZQCS*/64,
-    }, {
-// #define DDR3_1066F           9   // sg187E //DDR3-1066F (7-7-7) tCK=1.875ns
-        /*tCK*/ 1875,
-        /*tCL*/ 7, /*WCL*/6, /*RCD*/7, /*RAS*/20, /*RP*/7, /*RC*/27, /*RRD*/6,
-        /*FAW*/27, /*WR*/8, /*RTP*/6, /*ZQCL*/256, /*ZQCS*/64,
-    }, {
-// #define DDR3_1066G           10  // sg187 //DDR3-1066G (8-8-8) tCK=1.875ns
-        /*tCK*/ 1875,
-        /*tCL*/ 8, /*WCL*/6, /*RCD*/8, /*RAS*/20, /*RP*/8, /*RC*/28, /*RRD*/6,
-        /*FAW*/27, /*WR*/8, /*RTP*/6, /*ZQCL*/256, /*ZQCS*/64,
-    }, {
-// #define DDR3_800D            11  // sg25E //DDR3-800D (5-5-5) tCK=2.5ns
-        /*tCK*/ 2500,
-        /*tCL*/ 5, /*WCL*/5, /*RCD*/5, /*RAS*/15, /*RP*/5, /*RC*/20, /*RRD*/4,
-        /*FAW*/17, /*WR*/5, /*RTP*/3, /*ZQCL*/256, /*ZQCS*/64,
-    }, {
-// #define DDR3_800E            12  // sg25 //DDR3-800E (6-6-6) tCK=2.5ns
-        /*tCK*/ 2500,
-        /*tCL*/ 6, /*WCL*/5, /*RCD*/6, /*RAS*/15, /*RP*/6, /*RC*/21, /*RRD*/4,
-        /*FAW*/20, /*WR*/6, /*RTP*/6, /*ZQCL*/256, /*ZQCS*/64,
-    },
-    {
-    // #define DDR3_266MPW          13  // sg25 //DDR3-800E (5-5-5) tCK=2.5ns
-//      /*tCL*/ 5, /*WCL*/7, /*RCD*/5, /*RAS*/9/*37.5/4*/, /*RP*/5, /*RC*/13, /*RRD*/4,
-//      /*FAW 50/4*/15, /*WR6*/5, /*RTP*/4, /*ZQCL*/256, /*ZQCS*/64,
-// #define DDR3_250MPW          13  // sg25 //DDR3-800E (5-5-5) tCK=2.5ns
-        /*tCK*/ 2500,
-        /*tCL*/ 5, /*WCL*/7, /*RCD*/5, /*RAS*/9/*37.5/4*/, /*RP*/5, /*RC*/13, /*RRD*/4,
-        /*FAW 50/4*/15, /*WR6*/5, /*RTP*/4, /*ZQCL*/256, /*ZQCS*/64,
+	{
+// #define DDR3_2133N			0	// sg093 //DDR3-2133N (14-14-14) tCK=0.938ns
+		/*tCK*/ 938,
+		/*tCL*/ 14, /*WCL*/10, /*RCD*/14, /*RAS*/36, /*RP*/14, /*RC*/50, /*RRD*/7,
+		/*FAW*/38, /*WR*/16, /*RTP*/10, /*ZQCL*/342, /*ZQCS*/86,
+	}, {
+// #define DDR3_2133M			1	// sg093E //DDR3-2133M (13-13-13) tCK=0.938ns
+		/*tCK*/ 938,
+		/*tCL*/ 13, /*WCL*/10, /*RCD*/13, /*RAS*/36, /*RP*/13, /*RC*/49, /*RRD*/7,
+		/*FAW*/38, /*WR*/16, /*RTP*/10, /*ZQCL*/342, /*ZQCS*/86,
+	}, {
+// #define DDR3_2133L			2	// sg093F //DDR3-2133L (12-12-12) tCK=0.938ns
+		/*tCK*/ 938,
+		/*tCL*/ 12, /*WCL*/10, /*RCD*/12, /*RAS*/36, /*RP*/12, /*RC*/48, /*RRD*/7,
+		/*FAW*/38, /*WR*/16, /*RTP*/10, /*ZQCL*/342, /*ZQCS*/86,
+	}, {
+// #define DDR3_1866L			3	// sg107E //DDR3-1866L (12-12-12) tCK=1.07ns
+		/*tCK*/ 1070,
+		/*tCL*/ 12, /*WCL*/9, /*RCD*/12, /*RAS*/32, /*RP*/12, /*RC*/44, /*RRD*/6,
+		/*FAW*/33, /*WR*/14, /*RTP*/9, /*ZQCL*/300, /*ZQCS*/75,
+	}, {
+// #define DDR3_1866K			4	// sg107F //DDR3-1866K (11-11-11) tCK=1.07ns
+		/*tCK*/ 1070,
+		/*tCL*/ 11, /*WCL*/9, /*RCD*/11, /*RAS*/32, /*RP*/11, /*RC*/43, /*RRD*/6,
+		/*FAW*/33, /*WR*/14, /*RTP*/9, /*ZQCL*/300, /*ZQCS*/75,
+	}, {
+// #define DDR3_1600J			5	// sg125E //DDR3-1600J (10-10-10) tCK=1.25ns
+		/*tCK*/ 1250,
+		/*tCL*/ 10, /*WCL*/8, /*RCD*/10, /*RAS*/28, /*RP*/10, /*RC*/38, /*RRD*/6,
+		/*FAW*/32, /*WR*/12, /*RTP*/8, /*ZQCL*/256, /*ZQCS*/64,
+	}, {
+// #define DDR3_1600K			6	// sg125 //DDR3-1600K (11-11-11) tCK=1.25ns
+		/*tCK*/ 1250,
+		/*tCL*/ 11, /*WCL*/8, /*RCD*/11, /*RAS*/28, /*RP*/11, /*RC*/37, /*RRD*/6,
+		/*FAW*/32, /*WR*/12, /*RTP*/8, /*ZQCL*/256, /*ZQCS*/64,
+	}, {
+// #define DDR3_1333H			7	// sg15E //DDR3-1333H (9-9-9) tCK=1.5ns
+		/*tCK*/ 1500,
+		/*tCL*/ 9, /*WCL*/7, /*RCD*/9, /*RAS*/24, /*RP*/9, /*RC*/33, /*RRD*/5,
+		/*FAW*/30, /*WR*/10, /*RTP*/5, /*ZQCL*/256, /*ZQCS*/64,
+	}, {
+// #define DDR3_1333J			8	// sg15 //DDR3-1333J (10-10-10) tCK=1.5ns
+		/*tCK*/ 1500,
+		/*tCL*/ 10, /*WCL*/7, /*RCD*/10, /*RAS*/24, /*RP*/10, /*RC*/34, /*RRD*/5,
+		/*FAW*/30, /*WR*/10, /*RTP*/7, /*ZQCL*/256, /*ZQCS*/64,
+	}, {
+// #define DDR3_1066F			9	// sg187E //DDR3-1066F (7-7-7) tCK=1.875ns
+		/*tCK*/ 1875,
+		/*tCL*/ 7, /*WCL*/6, /*RCD*/7, /*RAS*/20, /*RP*/7, /*RC*/27, /*RRD*/6,
+		/*FAW*/27, /*WR*/8, /*RTP*/6, /*ZQCL*/256, /*ZQCS*/64,
+	}, {
+// #define DDR3_1066G			10	// sg187 //DDR3-1066G (8-8-8) tCK=1.875ns
+		/*tCK*/ 1875,
+		/*tCL*/ 8, /*WCL*/6, /*RCD*/8, /*RAS*/20, /*RP*/8, /*RC*/28, /*RRD*/6,
+		/*FAW*/27, /*WR*/8, /*RTP*/6, /*ZQCL*/256, /*ZQCS*/64,
+	}, {
+// #define DDR3_800D			11	// sg25E //DDR3-800D (5-5-5) tCK=2.5ns
+		/*tCK*/ 2500,
+		/*tCL*/ 5, /*WCL*/5, /*RCD*/5, /*RAS*/15, /*RP*/5, /*RC*/20, /*RRD*/4,
+		/*FAW*/17, /*WR*/5, /*RTP*/3, /*ZQCL*/256, /*ZQCS*/64,
+	}, {
+// #define DDR3_800E			12	// sg25 //DDR3-800E (6-6-6) tCK=2.5ns
+		/*tCK*/ 2500,
+		/*tCL*/ 6, /*WCL*/5, /*RCD*/6, /*RAS*/15, /*RP*/6, /*RC*/21, /*RRD*/4,
+		/*FAW*/20, /*WR*/6, /*RTP*/6, /*ZQCL*/256, /*ZQCS*/64,
+	},
+	{
+	// #define DDR3_266MPW			13	// sg25 //DDR3-800E (5-5-5) tCK=2.5ns
+//		/*tCL*/ 5, /*WCL*/7, /*RCD*/5, /*RAS*/9/*37.5/4*/, /*RP*/5, /*RC*/13, /*RRD*/4,
+//		/*FAW 50/4*/15, /*WR6*/5, /*RTP*/4, /*ZQCL*/256, /*ZQCS*/64,
+// #define DDR3_250MPW			13	// sg25 //DDR3-800E (5-5-5) tCK=2.5ns
+		/*tCK*/ 2500,
+		/*tCL*/ 5, /*WCL*/7, /*RCD*/5, /*RAS*/9/*37.5/4*/, /*RP*/5, /*RC*/13, /*RRD*/4,
+		/*FAW 50/4*/15, /*WR6*/5, /*RTP*/4, /*ZQCL*/256, /*ZQCS*/64,
 
-    },
+	},
 };
 uint32_t Get_DDR_Capacity(const MEM_CHIP_INFO *chip_info)
 {
-    uint32_t n=0;
-    uint32_t capacity=0;
-
-    assert_param(chip_info);
-    n=(chip_info->Chip_type<_16Mbx16)?(chip_info->Chip_type):(chip_info->Chip_type-_16Mbx16);
-    capacity=(chip_info->Chip_type<_16Mbx16)?(CHIP_MIN_CAPACITY*(1<<n)*(chip_info->Chip_num+1)):(CHIP_MIN_CAPACITY*(1<<n)*(chip_info->Bus_width+1)/(BUS_WIDTH_16+1));
-    return capacity;
-
+	uint32_t n=0;
+	uint32_t capacity=0;
 
+	assert_param(chip_info);
+	n=(chip_info->Chip_type<_16Mbx16)?(chip_info->Chip_type):(chip_info->Chip_type-_16Mbx16);
+	capacity=(chip_info->Chip_type<_16Mbx16)?(CHIP_MIN_CAPACITY*(1<<n)*(chip_info->Chip_num+1)):(CHIP_MIN_CAPACITY*(1<<n)*(chip_info->Bus_width+1)/(BUS_WIDTH_16+1));
+	return capacity;
+	
+	
 }
 uint32_t Calc_DDR_RFC(const MEM_CHIP_INFO *chip_info)
 {
-    uint32_t capacity=0;
-    uint32_t tRFC=0;
-    assert_param(chip_info);
-
-
-    capacity=Get_DDR_Capacity(chip_info);
-    if (chip_info->mem_type==MEM_DDR2) {
-
-        switch(capacity){
-            case CHIP_CAPACITY_32MB:tRFC=75;break;
-            case CHIP_CAPACITY_64MB:tRFC=105;break;
-            case CHIP_CAPACITY_128MB:tRFC=128;break;
-            case CHIP_CAPACITY_256MB:tRFC=195;break;
-            case CHIP_CAPACITY_512MB:tRFC=328;break;
-        }
-    }
-    else{
-        switch(capacity){
-            case CHIP_CAPACITY_64MB:tRFC=90;break;
-            case CHIP_CAPACITY_128MB:tRFC=110;break;
-            case CHIP_CAPACITY_256MB:tRFC=160;break;
-            case CHIP_CAPACITY_512MB:tRFC=300;break;
-            case CHIP_CAPACITY_1024MB:tRFC=350;break;
-        }
-    }
-
-    return tRFC;
+	uint32_t capacity=0;
+	uint32_t tRFC=0;
+	assert_param(chip_info);
 
+	
+	capacity=Get_DDR_Capacity(chip_info);
+	if (chip_info->mem_type==MEM_DDR2) {
+	
+		switch(capacity){
+			case CHIP_CAPACITY_32MB:tRFC=75;break;
+			case CHIP_CAPACITY_64MB:tRFC=105;break;
+			case CHIP_CAPACITY_128MB:tRFC=128;break;
+			case CHIP_CAPACITY_256MB:tRFC=195;break;
+			case CHIP_CAPACITY_512MB:tRFC=328;break;
+		}
+	}
+	else{
+		switch(capacity){
+			case CHIP_CAPACITY_64MB:tRFC=90;break;
+			case CHIP_CAPACITY_128MB:tRFC=110;break;
+			case CHIP_CAPACITY_256MB:tRFC=160;break;
+			case CHIP_CAPACITY_512MB:tRFC=300;break;
+			case CHIP_CAPACITY_1024MB:tRFC=350;break;
+		}
+	}
 
+	return tRFC;
+	
+	
 }
 static void DDR_Cmd(const uint32_t cmd ,const uint32_t param)
 {
-        DDRC->CMD =((cmd)|(param));
-
+		DDRC->CMD =((cmd)|(param));
+	
 }
 static void DDR_Latency(const uint32_t cycle  )
 {
-    DDR_Cmd(SW_CMD_NOP,cycle);
+	DDR_Cmd(SW_CMD_NOP,cycle);
 }
 static void DDR2_conf(const MEM_CHIP_INFO *chip_info ,const void *ddr)
 {
-    uint32_t period=0;
-    const DDR2MEM *ptr = (const DDR2MEM *)ddr;
-    uint32_t tRFC=0;
+	uint32_t period=0;
+	const DDR2MEM *ptr = (const DDR2MEM *)ddr;
+	uint32_t tRFC=0;
+	
+	assert_param(ddr);
+	tRFC=Calc_DDR_RFC(chip_info);
+	period = (1000 / (SYSTEM_CLOCK_FREQ / 1000000));	
+	CFG_CTRL->DONE_b.CMD = 0x1;
 
-    assert_param(ddr);
-    tRFC=Calc_DDR_RFC(chip_info);
-    period = (1000 / (SYSTEM_CLOCK_FREQ / 1000000));
-    CFG_CTRL->DONE_b.CMD = 0x1;
+	DDRC->MODE_b.LANE = 1;
+	DDRC->MODE_b.B16 = 1;
+	DDRC->REF_b.TIME =( DDR_TREF/period);
+	DDRC->RP_b.RPA = 1;
+	DDRC->RFC_b.DI = (tRFC/period);
+	DDRC->PHUNG_b.MODE = 1;
+	DDRC->RD_SEL_b.PHY_SEL = 5;
 
-    DDRC->MODE_b.LANE = 1;
-    DDRC->MODE_b.B16 = 1;
-    DDRC->REF_b.TIME =( DDR_TREF/period);
-    DDRC->RP_b.RPA = 1;
-    DDRC->RFC_b.DI = (tRFC/period);
-    DDRC->PHUNG_b.MODE = 1;
-    DDRC->RD_SEL_b.PHY_SEL = 5;
+	DDRC->DQSEN0_b.DL = 2;
+	DDRC->DQSEN1_b.DL = 2;
+	DDRC->DQSEN2_b.DL = 2;
+	DDRC->DQSEN3_b.DL = 2;
+	DDRC->INTCTL_b.DONE = 1;
+	DDRC->INTCTL_b.ERR = 0;
+	DDRC->RDQ_b.L3 = DDRC->RDQ_b.L2 = DDRC->RDQ_b.L1 = DDRC->RDQ_b.L0 = 0x32;
+	DDRC->ITMDLY_b.I0 = DDRC->ITMDLY_b.IS0 = DDRC->ITMDLY_b.I1 = DDRC->ITMDLY_b.IS1 = 
+		DDRC->ITMDLY_b.I2 = DDRC->ITMDLY_b.IS2 = DDRC->ITMDLY_b.I3 = DDRC->ITMDLY_b.IS3 = 3;
 
-    DDRC->DQSEN0_b.DL = 2;
-    DDRC->DQSEN1_b.DL = 2;
-    DDRC->DQSEN2_b.DL = 2;
-    DDRC->DQSEN3_b.DL = 2;
-    DDRC->INTCTL_b.DONE = 1;
-    DDRC->INTCTL_b.ERR = 0;
-    DDRC->RDQ_b.L3 = DDRC->RDQ_b.L2 = DDRC->RDQ_b.L1 = DDRC->RDQ_b.L0 = 0x32;
-    DDRC->ITMDLY_b.I0 = DDRC->ITMDLY_b.IS0 = DDRC->ITMDLY_b.I1 = DDRC->ITMDLY_b.IS1 =
-        DDRC->ITMDLY_b.I2 = DDRC->ITMDLY_b.IS2 = DDRC->ITMDLY_b.I3 = DDRC->ITMDLY_b.IS3 = 3;
-
-
-    DDR_Latency((POWER_UP_NOP/period));
-    DDR_Cmd(SW_CMD_NOPCKE,(PRE_ALL_NOP/period));
-    DDR_Cmd(SW_CMD_PREA,NULL);
-    DDR_Latency(ptr->tRP);/*tRP*/
-    DDR_Cmd(SW_CMD_EMR2,NULL);
-    DDR_Latency(DDR2_TMRD);
-    DDR_Cmd(SW_CMD_EMR3,NULL);
-    DDR_Latency(DDR2_TMRD);
-    DDR_Cmd(SW_CMD_DLL_EN,NULL);
-    DDR_Latency(DDR2_TMRD);
-    DDR_Cmd(SW_CMD_DLL_RST,NULL);
-    DDR_Latency(DDR2_TMRD);
-    DDR_Cmd(SW_CMD_PREA,NULL);
-    DDR_Latency(ptr->tRP);
-    DDR_Cmd(SW_CMD_REF,NULL);
-    DDR_Latency((tRFC/period));/*tRFC*/
-    DDR_Cmd(SW_CMD_REF,NULL);
-    DDR_Latency((tRFC/period));
-    DDR_Cmd(SW_CMD_MR,(((ptr->tWR-1)<<MR_WR_OFFSET)|(ptr->tCL<<MR_CL_OFFSET)|MR_BURST_LEN_8));
-    DDR_Latency(POWER_UP_MIN_CK);
-    DDR_Cmd(SW_CMD_EMR1_TEST,NULL);
-    DDR_Latency(DDR2_TMRD);
+	
+	DDR_Latency((POWER_UP_NOP/period));
+	DDR_Cmd(SW_CMD_NOPCKE,(PRE_ALL_NOP/period));
+	DDR_Cmd(SW_CMD_PREA,NULL);
+	DDR_Latency(ptr->tRP);/*tRP*/
+	DDR_Cmd(SW_CMD_EMR2,NULL);
+	DDR_Latency(DDR2_TMRD);
+	DDR_Cmd(SW_CMD_EMR3,NULL);
+	DDR_Latency(DDR2_TMRD);
+	DDR_Cmd(SW_CMD_DLL_EN,NULL);
+	DDR_Latency(DDR2_TMRD);
+	DDR_Cmd(SW_CMD_DLL_RST,NULL);
+	DDR_Latency(DDR2_TMRD);
+	DDR_Cmd(SW_CMD_PREA,NULL);
+	DDR_Latency(ptr->tRP);
+	DDR_Cmd(SW_CMD_REF,NULL);
+	DDR_Latency((tRFC/period));/*tRFC*/
+	DDR_Cmd(SW_CMD_REF,NULL);
+	DDR_Latency((tRFC/period));
+	DDR_Cmd(SW_CMD_MR,(((ptr->tWR-1)<<MR_WR_OFFSET)|(ptr->tCL<<MR_CL_OFFSET)|MR_BURST_LEN_8));
+	DDR_Latency(POWER_UP_MIN_CK);
+	DDR_Cmd(SW_CMD_EMR1_TEST,NULL);
+	DDR_Latency(DDR2_TMRD);
 }
 
 static void DDR3_conf(const MEM_CHIP_INFO *chip_info ,const void *ddr)
 {
 
-    uint32_t period = 0;
-    uint32_t tRFC = 0;
-    const DDR3MEM *ptr = (const DDR3MEM *)ddr;
+	uint32_t period = 0;
+	uint32_t tRFC = 0;
+	const DDR3MEM *ptr = (const DDR3MEM *)ddr;
 
-    tRFC = Calc_DDR_RFC(chip_info);
-    period = (1000 / (SYSTEM_CLOCK_FREQ / 1000000));
+	tRFC = Calc_DDR_RFC(chip_info);
+	period = (1000 / (SYSTEM_CLOCK_FREQ / 1000000));	
+	
+	DDRC->MODE_b.LANE = 0x1;
+	DDRC->QUE_b.DEPTH=1;
+	DDRC->REF_b.TIME = (DDR_TREF / period);////// //2Gb periodic refresh interval 7.8us 7.8us/5ns
+	DDRC->REF_b.TRIG = 1;
+	DDRC->REF_b.THRD = 8; 
+	DDRC->ZQCSR_b.EN = 1;
+	DDRC->ZQCSI = 128 * 1000000 / period;
+	DDRC->RP_b.RPA = 1;
+	DDRC->RFC_b.DI = (tRFC / period);
+	
+	if (ptr->tCK == 2500) { // 200MHz 
+		DDRC->RD_SEL_b.PHY_SEL = 5;
+	} else if (ptr->tCK == 3000) { // 333MHz 
+		DDRC->RD_SEL_b.PHY_SEL = 6;
+	}
+	
+	DDRC->PHUNG_b.MODE = 1;	
+	DDRC->DQSEN0_b.DL = 2;
+	DDRC->DQSEN1_b.DL = 2;
+	DDRC->DQSEN2_b.DL = 2;
+	DDRC->DQSEN3_b.DL = 2;
 
-    DDRC->MODE_b.LANE = 0x1;
-    DDRC->QUE_b.DEPTH=1;
-    DDRC->REF_b.TIME = (DDR_TREF / period);////// //2Gb periodic refresh interval 7.8us 7.8us/5ns
-    DDRC->REF_b.TRIG = 1;
-    DDRC->REF_b.THRD = 8;
-    DDRC->ZQCSR_b.EN = 1;
-    DDRC->ZQCSI = 128 * 1000000 / period;
-    DDRC->RP_b.RPA = 1;
-    DDRC->RFC_b.DI = (tRFC / period);
-
-    if (ptr->tCK == 2500) { // 200MHz
-        DDRC->RD_SEL_b.PHY_SEL = 5;
-    } else if (ptr->tCK == 3000) { // 333MHz
-        DDRC->RD_SEL_b.PHY_SEL = 6;
-    }
-
-    DDRC->PHUNG_b.MODE = 1;
-    DDRC->DQSEN0_b.DL = 2;
-    DDRC->DQSEN1_b.DL = 2;
-    DDRC->DQSEN2_b.DL = 2;
-    DDRC->DQSEN3_b.DL = 2;
-
-    // config MR#
-    DDR_Latency((POWER_UP_NOP/period));//200us nop
-    DDR_Cmd(SW_CMD_RSTH,NULL);// RESET H
-    DDR_Latency((RSTH_NOP/period));// 500us nop
-    DDR_Cmd(SW_CMD_NOPCKE,((tRFC+10)/period));//     cke high 170/tck tck txpr max(5nck, trfc(min) + 10ns)   2Gb refresh time 160ns
-    DDR_Cmd(SW_CMD_EMR2,((ptr->tWCL-5)<<MR2_CWL_OFFSET)); //MR2
-    DDR_Latency(DDR3_TMRD);// tmrd  4nck
-    DDR_Cmd(SW_CMD_EMR3,NULL);// MR3
-    DDR_Latency(DDR3_TMRD); // tmrd
-    DDR_Cmd(SW_CMD_EMR1,MR1_RZQ_4); // MR1
-    DDR_Latency(DDR3_TMRD); // tmrd
-    DDR_Cmd(SW_CMD_MR,(MR_PPD_FAST|MR_DLL_YES|((ptr->tWR-1)<<MR_WR_OFFSET)|(CAL_DDR3_CL(ptr->tCL))));
-                                                        // MR0
-                                                        // A1 , A0 2'b0 fixed 8
-                                                        // A2 CL 0
-                                                        // A3 nibble sequential 0  Interleave 1
-                                                        // A6,A5,A4 CL 101 CL =9
-                                                        // A7 normal mode 0
-                                                        // A8 DLL reset 1
-                                                        // A11,A10,A9 wr=(twr/ck)=(15/3)=5  =001
-                                                        // A12 DLL control for precharge PD fast exit 1
-                                                        // MR0 =0xb50
-    DDR_Latency(MAX(DDR3_TMOD_CK,(DDR3_TMOD/period)));// tmod max (12nck,15ns)
-    DDR_Cmd(SW_CMD_ZQCL,NULL);// ZQCL starting ZQ calibration
-    DDR_Latency(MAX(DDR3_TZQINIT_CK,(DDR3_TZQINIT/period))); // tdllk 512nck (should be 500nck)
-    DDR_Latency(DDR3_TDLLK_CK); // tZQinit max(512nck,640ns)
+	// config MR#
+	DDR_Latency((POWER_UP_NOP/period));//200us nop
+	DDR_Cmd(SW_CMD_RSTH,NULL);// RESET H
+	DDR_Latency((RSTH_NOP/period));// 500us nop  
+	DDR_Cmd(SW_CMD_NOPCKE,((tRFC+10)/period));//	 cke high 170/tck tck txpr max(5nck, trfc(min) + 10ns)	 2Gb refresh time 160ns
+	DDR_Cmd(SW_CMD_EMR2,((ptr->tWCL-5)<<MR2_CWL_OFFSET)); //MR2
+	DDR_Latency(DDR3_TMRD);// tmrd  4nck
+	DDR_Cmd(SW_CMD_EMR3,NULL);// MR3
+	DDR_Latency(DDR3_TMRD); // tmrd
+	DDR_Cmd(SW_CMD_EMR1,MR1_RZQ_4); // MR1	
+	DDR_Latency(DDR3_TMRD); // tmrd
+	DDR_Cmd(SW_CMD_MR,(MR_PPD_FAST|MR_DLL_YES|((ptr->tWR-1)<<MR_WR_OFFSET)|(CAL_DDR3_CL(ptr->tCL))));
+														// MR0
+														// A1 , A0 2'b0 fixed 8 
+														// A2 CL 0 
+														// A3 nibble sequential 0  Interleave 1
+														// A6,A5,A4 CL 101 CL =9 
+														// A7 normal mode 0
+														// A8 DLL reset 1
+														// A11,A10,A9 wr=(twr/ck)=(15/3)=5	=001
+														// A12 DLL control for precharge PD fast exit 1
+														// MR0 =0xb50
+	DDR_Latency(MAX(DDR3_TMOD_CK,(DDR3_TMOD/period)));// tmod max (12nck,15ns) 
+	DDR_Cmd(SW_CMD_ZQCL,NULL);// ZQCL starting ZQ calibration
+	DDR_Latency(MAX(DDR3_TZQINIT_CK,(DDR3_TZQINIT/period))); // tdllk 512nck (should be 500nck)
+	DDR_Latency(DDR3_TDLLK_CK); // tZQinit max(512nck,640ns) 
 
 }
 
 BOOL DDR_Init(const MEM_CHIP_INFO *chip_info, const void *ddr)
 {
-    uint32_t tCL, tWR, tWCL, tWTR, tCK,mode;
+	uint32_t tCL, tWR, tWCL, tWTR, tCK,mode;
+	
+	assert_param(chip_info);
+	assert_param(ddr);
+	if((chip_info->Bus_width<BUS_WIDTH_MAX)
+		&&(chip_info->Chip_num<CHIP_NUM_MAX)
+		&&(chip_info->Chip_type<	CHIP_TYPE_MAX))
+	{
+		if(chip_info->mem_type==MEM_DDR2)
+		{
+			mode=DDR2_MODE[chip_info->Bus_width][chip_info->Chip_num][chip_info->Chip_type];
+		}
+		else
+		{
+			mode=DDR3_MODE[chip_info->Bus_width][chip_info->Chip_num][chip_info->Chip_type];
+		}
+		if(mode==0xff)
+		{
+			return FALSE;
+		}
+		
+	
+	}
+	else
+	{
+		return FALSE;
+	}
+		
+	
+	PDPROT->LOCK_b.EN = 0;
+	do {
+		CFG_CTRL->PDLLSTR_b.C2R1D = 0; // rst dll_c2r1
+		udelay(10);
+		CFG_CTRL->PDLLSTR_b.C2R1D = 1; // releset rst
+		udelay(10);
+	} while ((PDLOCK->GCLK & 0x40) != 0x40);
+	PDPROT->LOCK_b.EN = 1;
 
-    assert_param(chip_info);
-    assert_param(ddr);
-    if((chip_info->Bus_width<BUS_WIDTH_MAX)
-        &&(chip_info->Chip_num<CHIP_NUM_MAX)
-        &&(chip_info->Chip_type<    CHIP_TYPE_MAX))
-    {
-        if(chip_info->mem_type==MEM_DDR2)
-        {
-            mode=DDR2_MODE[chip_info->Bus_width][chip_info->Chip_num][chip_info->Chip_type];
-        }
-        else
-        {
-            mode=DDR3_MODE[chip_info->Bus_width][chip_info->Chip_num][chip_info->Chip_type];
-        }
-        if(mode==0xff)
-        {
-            return FALSE;
-        }
+	DDRC->MODE_b.MODE = mode;
 
+	if (chip_info->mem_type==MEM_DDR2) {
+		const DDR2MEM *ptr = (const DDR2MEM *)ddr;
+		DDRC->RL_b.VAL = ptr->tCL;
+		DDRC->RCD_b.DI = ptr->tRCD;
+		DDRC->RP_b.DI = ptr->tRP;
+		DDRC->RC_b.DI = ptr->tRC;
+		DDRC->RAS_b.DI = ptr->tRAS;
+		tWR = ptr->tWR;
+		tWTR = ptr->tWTR;
+		DDRC->RRD_b.DI = ptr->tRRD;
+		DDRC->RTP_b.DI = ptr->tRTP;
+		DDRC->FAW_b.DI = ptr->tFAW;
+		DDR2_conf(chip_info,ptr);
+	} else {
+		const DDR3MEM *ptr = (const DDR3MEM *)ddr;
+		DDRC->RL_b.VAL = ptr->tCL;
+		tWCL = ptr->tWCL;
+		DDRC->RCD_b.DI = ptr->tRCD;
+		DDRC->RAS_b.DI = ptr->tRAS;
+		DDRC->RP_b.DI = ptr->tRP;
+		DDRC->RC_b.DI = ptr->tRC;
+		DDRC->RRD_b.DI = ptr->tRRD;
+		DDRC->FAW_b.DI = ptr->tFAW;
+		tWR = ptr->tWR;
+		tCK = ptr->tCK;
+		DDRC->RTP_b.DI = ptr->tRTP;
+		DDRC->ZQCL_b.DI = ptr->tZQoper;
+		DDRC->ZQCS_b.DI = ptr->tZQCS;
+		DDR3_conf(chip_info,ptr);
+	}
 
-    }
-    else
-    {
-        return FALSE;
-    }
+	tCL = DDRC->RL_b.VAL;
 
+	DDRC->WTR_b.DI  = (DDRC->MODE_b.MODE & 0x20) ? 
+		(tWCL + tWTR + (DDRC->BURST_b.LEN ? 2 : 4)) : 
+		((tCK * 4) > 7500) ? 18 : (tCK * 4 + 7500 - 1) / 7500;				 //4
 
-    PDPROT->LOCK_b.EN = 0;
-    do {
-        CFG_CTRL->PDLLSTR_b.C2R1D = 0; // rst dll_c2r1
-        udelay(10);
-        CFG_CTRL->PDLLSTR_b.C2R1D = 1; // releset rst
-        udelay(10);
-    } while ((PDLOCK->GCLK & 0x40) != 0x40);
-    PDPROT->LOCK_b.EN = 1;
+	DDRC->CCD_b.DI  = (DDRC->MODE_b.MODE & 0x20) ? (DDRC->BURST_b.LEN ? 2 : 4) : 4;
+	DDRC->RTW_b.DI  = (DDRC->MODE_b.MODE & 0x20) ? (DDRC->BURST_b.LEN ? 4 : 6) : (tCL + DDRC->CCD_b.DI - tWCL + (DDRC->BURST_b.LEN ? 0 : 2));
+	DDRC->WTP_b.DI  = (DDRC->MODE_b.MODE & 0x20) ? (tCL + tWR + (DDRC->BURST_b.LEN ? 1 : 3)) : (tWCL + tWR + (DDRC->BURST_b.LEN ? 2 : 4));
+	DDRC->WL_b.VAL  = (DDRC->MODE_b.MODE & 0x20) ? (MAX(tCL, 3) - 3) : (tWCL - 2);
+	DDRC->ODTH_b.DL = (DDRC->MODE_b.MODE & 0x20) ? (MAX(tCL, 4) - 4) : 0;
+	if (tCK == 2500) { // 200MHz 
+		DDRC->ODTL_b.DL = (DDRC->MODE_b.MODE & 0x20) ? (DDRC->BURST_b.LEN ? (tCL - 1) : (tCL + 1)) : (DDRC->BURST_b.LEN ? 4 : 6);
+	} else if (tCK == 3000) { // 333MHz 
+		DDRC->ODTL_b.DL = 0x1f;
+	}
 
-    DDRC->MODE_b.MODE = mode;
+	
+	// DEBUG INFO HERE
+	DDRC->CTRL_b.STR = 1;
 
-    if (chip_info->mem_type==MEM_DDR2) {
-        const DDR2MEM *ptr = (const DDR2MEM *)ddr;
-        DDRC->RL_b.VAL = ptr->tCL;
-        DDRC->RCD_b.DI = ptr->tRCD;
-        DDRC->RP_b.DI = ptr->tRP;
-        DDRC->RC_b.DI = ptr->tRC;
-        DDRC->RAS_b.DI = ptr->tRAS;
-        tWR = ptr->tWR;
-        tWTR = ptr->tWTR;
-        DDRC->RRD_b.DI = ptr->tRRD;
-        DDRC->RTP_b.DI = ptr->tRTP;
-        DDRC->FAW_b.DI = ptr->tFAW;
-        DDR2_conf(chip_info,ptr);
-    } else {
-        const DDR3MEM *ptr = (const DDR3MEM *)ddr;
-        DDRC->RL_b.VAL = ptr->tCL;
-        tWCL = ptr->tWCL;
-        DDRC->RCD_b.DI = ptr->tRCD;
-        DDRC->RAS_b.DI = ptr->tRAS;
-        DDRC->RP_b.DI = ptr->tRP;
-        DDRC->RC_b.DI = ptr->tRC;
-        DDRC->RRD_b.DI = ptr->tRRD;
-        DDRC->FAW_b.DI = ptr->tFAW;
-        tWR = ptr->tWR;
-        tCK = ptr->tCK;
-        DDRC->RTP_b.DI = ptr->tRTP;
-        DDRC->ZQCL_b.DI = ptr->tZQoper;
-        DDRC->ZQCS_b.DI = ptr->tZQCS;
-        DDR3_conf(chip_info,ptr);
-    }
+	while (0 == DDRC->STA_b.EMPTY);
+	while(0 == DDRC->INTRAW_b.DONE);
+	DDRC->CTRL_b.STR = DDRC->CTRL_b.TO = 0;
 
-    tCL = DDRC->RL_b.VAL;
-
-    DDRC->WTR_b.DI  = (DDRC->MODE_b.MODE & 0x20) ?
-        (tWCL + tWTR + (DDRC->BURST_b.LEN ? 2 : 4)) :
-        ((tCK * 4) > 7500) ? 18 : (tCK * 4 + 7500 - 1) / 7500;               //4
-
-    DDRC->CCD_b.DI  = (DDRC->MODE_b.MODE & 0x20) ? (DDRC->BURST_b.LEN ? 2 : 4) : 4;
-    DDRC->RTW_b.DI  = (DDRC->MODE_b.MODE & 0x20) ? (DDRC->BURST_b.LEN ? 4 : 6) : (tCL + DDRC->CCD_b.DI - tWCL + (DDRC->BURST_b.LEN ? 0 : 2));
-    DDRC->WTP_b.DI  = (DDRC->MODE_b.MODE & 0x20) ? (tCL + tWR + (DDRC->BURST_b.LEN ? 1 : 3)) : (tWCL + tWR + (DDRC->BURST_b.LEN ? 2 : 4));
-    DDRC->WL_b.VAL  = (DDRC->MODE_b.MODE & 0x20) ? (MAX(tCL, 3) - 3) : (tWCL - 2);
-    DDRC->ODTH_b.DL = (DDRC->MODE_b.MODE & 0x20) ? (MAX(tCL, 4) - 4) : 0;
-    if (tCK == 2500) { // 200MHz
-        DDRC->ODTL_b.DL = (DDRC->MODE_b.MODE & 0x20) ? (DDRC->BURST_b.LEN ? (tCL - 1) : (tCL + 1)) : (DDRC->BURST_b.LEN ? 4 : 6);
-    } else if (tCK == 3000) { // 333MHz
-        DDRC->ODTL_b.DL = 0x1f;
-    }
-
-
-    // DEBUG INFO HERE
-    DDRC->CTRL_b.STR = 1;
-
-    while (0 == DDRC->STA_b.EMPTY);
-    while(0 == DDRC->INTRAW_b.DONE);
-    DDRC->CTRL_b.STR = DDRC->CTRL_b.TO = 0;
-
-    return TRUE;
+	return TRUE;
 }

bsp/CME_M7/StdPeriph_Driver/src/cmem7_dma.c

@@ -1,72 +1,72 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_dma.c
-    *
-    * @brief    CMEM7 DMA source file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_dma.c
+	*
+	* @brief    CMEM7 DMA source file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #include "cmem7_dma.h"
 
 typedef struct {
-    union {
-    uint32_t  CTL_LOW;
-
+	union {
+    uint32_t  CTL_LOW;                              
+    
     struct {
-      uint32_t  INT_EN     :  1;
-      uint32_t  DST_TR_WIDTH:  3;
-      uint32_t  SRC_TR_WIDTH:  3;
-      uint32_t  DINC       :  2;
-      uint32_t  SINC       :  2;
-      uint32_t  DEST_MSIZE :  3;
-      uint32_t  SRC_MSIZE  :  3;
-      uint32_t  SRC_GATHER_EN:  1;
-      uint32_t  DST_SCATTER_EN:  1;
+      uint32_t  INT_EN     :  1;               
+      uint32_t  DST_TR_WIDTH:  3;              
+      uint32_t  SRC_TR_WIDTH:  3;              
+      uint32_t  DINC       :  2;              
+      uint32_t  SINC       :  2;               
+      uint32_t  DEST_MSIZE :  3;              
+      uint32_t  SRC_MSIZE  :  3;              
+      uint32_t  SRC_GATHER_EN:  1;           
+      uint32_t  DST_SCATTER_EN:  1;          
       uint32_t             :  1;
-      uint32_t  TT_FC      :  3;
-      uint32_t  DMS        :  2;
-      uint32_t  SMS        :  2;
-      uint32_t  LLP_DST_EN :  1;
-      uint32_t  LLP_SRC_EN :  1;
-    } CTL_LOW_b;
+      uint32_t  TT_FC      :  3;           
+      uint32_t  DMS        :  2;              
+      uint32_t  SMS        :  2;            
+      uint32_t  LLP_DST_EN :  1;              
+      uint32_t  LLP_SRC_EN :  1;              
+    } CTL_LOW_b;                                
   } INNER;
 } INNER_CTL_LOW;
 
 typedef struct {
   union {
-    uint32_t  CTL_HI;
-
+    uint32_t  CTL_HI;     
+    
     struct {
-      uint32_t  BLOCK_TS   : 12;
-      uint32_t  DONE       :  1;
-    } CTL_HI_b;
+      uint32_t  BLOCK_TS   : 12;    
+      uint32_t  DONE       :  1;                   
+    } CTL_HI_b;                                      
   } INNER;
 } INNER_CTL_HIGH;
 
-typedef struct {
-    uint32_t srcAddr;
-    uint32_t dstAddr;
-    uint32_t nextBlock;
-    INNER_CTL_LOW low;
-    INNER_CTL_HIGH high;
+typedef struct {                      
+	uint32_t srcAddr;                  
+	uint32_t dstAddr;                  
+	uint32_t nextBlock;              
+	INNER_CTL_LOW low;                 
+	INNER_CTL_HIGH high;                 
 } INNER_BLOCK_DESC;
 
 
@@ -87,176 +87,176 @@ typedef struct {
 #define DMA_LOCK_DMA_BLOCK_TRANSFER          1
 #define DMA_LOCK_DMA_BLOCK_TRANSACTION       2
 
-
+            
 void DMA_Init() {
-    DMA->DMA_EN_b.EN = TRUE;
-
-    // only open channel 0
-    DMA->CH_EN = (0xFF << DMA_MAX_CHANNEL_NUM) | 0x0;
-
-    DMA_ClearInt(DMA_Int_All);
-    DMA_EnableInt(DMA_Int_All, FALSE);
-
-    DMA->SAR0 = 0x0;
-    DMA->DAR0 = 0x0;
-
-    DMA->CTL_HI0_b.BLOCK_TS             = 0;
-    DMA->CTL_LOW0_b.INT_EN              = FALSE;
-    DMA->CTL_LOW0_b.DST_TR_WIDTH    = DMA_TR_WIDTH_32_BIT;
-    DMA->CTL_LOW0_b.SRC_TR_WIDTH    = DMA_TR_WIDTH_32_BIT;
-    DMA->CTL_LOW0_b.DINC                    = DMA_INC_INCREMENT;
-    DMA->CTL_LOW0_b.SINC                    = DMA_INC_INCREMENT;
-    DMA->CTL_LOW0_b.DEST_MSIZE      = 0;
-    DMA->CTL_LOW0_b.SRC_MSIZE       = 0;
-    DMA->CTL_LOW0_b.SRC_GATHER_EN = FALSE;
-    DMA->CTL_LOW0_b.DST_SCATTER_EN = FALSE;
-    DMA->CTL_LOW0_b.TT_FC               = 0;
-  DMA->CTL_LOW0_b.DMS                   = 0;
-    DMA->CTL_LOW0_b.SMS                 = 0;
-    DMA->CTL_LOW0_b.LLP_DST_EN      = FALSE;
-    DMA->CTL_LOW0_b.LLP_SRC_EN      = FALSE;
-
-  DMA->LLP0_b.LOC = 0;
-    DMA->LLP0_b.LMS = 0;
+	DMA->DMA_EN_b.EN = TRUE;
+	
+	// only open channel 0
+	DMA->CH_EN = (0xFF << DMA_MAX_CHANNEL_NUM) | 0x0;
+	
+	DMA_ClearInt(DMA_Int_All);
+ 	DMA_EnableInt(DMA_Int_All, FALSE);
+	
+	DMA->SAR0 = 0x0;
+	DMA->DAR0 = 0x0;
+	
+	DMA->CTL_HI0_b.BLOCK_TS 			= 0;
+	DMA->CTL_LOW0_b.INT_EN 				= FALSE;
+	DMA->CTL_LOW0_b.DST_TR_WIDTH 	= DMA_TR_WIDTH_32_BIT;
+	DMA->CTL_LOW0_b.SRC_TR_WIDTH 	= DMA_TR_WIDTH_32_BIT;
+	DMA->CTL_LOW0_b.DINC 					= DMA_INC_INCREMENT;
+	DMA->CTL_LOW0_b.SINC 					= DMA_INC_INCREMENT;
+	DMA->CTL_LOW0_b.DEST_MSIZE 		= 0;
+	DMA->CTL_LOW0_b.SRC_MSIZE 		= 0;
+	DMA->CTL_LOW0_b.SRC_GATHER_EN = FALSE;
+	DMA->CTL_LOW0_b.DST_SCATTER_EN = FALSE;
+	DMA->CTL_LOW0_b.TT_FC 				= 0;
+  DMA->CTL_LOW0_b.DMS    				= 0;
+	DMA->CTL_LOW0_b.SMS    				= 0;
+	DMA->CTL_LOW0_b.LLP_DST_EN   	= FALSE;
+	DMA->CTL_LOW0_b.LLP_SRC_EN   	= FALSE;
+	
+  DMA->LLP0_b.LOC = 0; 
+	DMA->LLP0_b.LMS = 0;
 
   DMA->SGR0_b.SGC = 0x1;
-    DMA->SGR0_b.SGI = 0x0;
-
-    DMA->DSR0_b.DSC = 0x0;
-    DMA->DSR0_b.DSI = 0x0;
+	DMA->SGR0_b.SGI = 0x0;
+	
+	DMA->DSR0_b.DSC = 0x0;
+	DMA->DSR0_b.DSI = 0x0;
 
   DMA->SSTATAR0 = 0x0;
-    DMA->DSTATAR0 = 0x0;
-
-    DMA->CFG_HI0                                = 0x0;
-    DMA->CFG_LOW0_b.CH_PRIOR        = 0;
-    DMA->CFG_LOW0_b.CH_SUSP         = 0;
-    DMA->CFG_LOW0_b.HS_SEL_DST  = 0;
-    DMA->CFG_LOW0_b.LOCK_B_L        = 0;
-  DMA->CFG_LOW0_b.HS_SEL_SRC    = 0;
-    DMA->CFG_LOW0_b.LOCK_CH_L   = DMA_LOCK_DMA_TRANSFER;
-  DMA->CFG_LOW0_b.LOCK_B_L      = DMA_LOCK_DMA_TRANSFER;
-    DMA->CFG_LOW0_b.LOCK_CH         = TRUE;
-    DMA->CFG_LOW0_b.LOCK_B          = TRUE;
-    DMA->CFG_LOW0_b.DST_HS_POL  = 0;
-    DMA->CFG_LOW0_b.SRC_HS_POL  = 0;
-    DMA->CFG_LOW0_b.RELOAD_SRC  = FALSE;
-    DMA->CFG_LOW0_b.RELOAD_DST  = FALSE;
+	DMA->DSTATAR0 = 0x0;
+	
+	DMA->CFG_HI0 								= 0x0;
+	DMA->CFG_LOW0_b.CH_PRIOR 		= 0;
+	DMA->CFG_LOW0_b.CH_SUSP 		= 0;
+	DMA->CFG_LOW0_b.HS_SEL_DST 	= 0;
+	DMA->CFG_LOW0_b.LOCK_B_L 		= 0;
+  DMA->CFG_LOW0_b.HS_SEL_SRC 	= 0;
+	DMA->CFG_LOW0_b.LOCK_CH_L 	= DMA_LOCK_DMA_TRANSFER;
+  DMA->CFG_LOW0_b.LOCK_B_L 		= DMA_LOCK_DMA_TRANSFER;
+	DMA->CFG_LOW0_b.LOCK_CH 		= TRUE;
+	DMA->CFG_LOW0_b.LOCK_B 			= TRUE;
+	DMA->CFG_LOW0_b.DST_HS_POL 	= 0;
+	DMA->CFG_LOW0_b.SRC_HS_POL 	= 0;
+	DMA->CFG_LOW0_b.RELOAD_SRC 	= FALSE;
+	DMA->CFG_LOW0_b.RELOAD_DST 	= FALSE;
 }
 
 void DMA_EnableInt(uint32_t Int, BOOL enable) {
-    assert_param(IS_DMA_INT(Int));
-
+	assert_param(IS_DMA_INT(Int));
+	
   if (enable) {
-        if (Int & DMA_Int_TfrComplete) {
-            DMA->INT_EN_TFR = (0x1 << DMA_MAX_CHANNEL_NUM) | 0x1;
-        }
-
-        if (Int & DMA_Int_Err) {
-            DMA->INT_EN_ERR = (0x1 << DMA_MAX_CHANNEL_NUM) | 0x1;
-        }
-    } else {
-        if (Int & DMA_Int_TfrComplete) {
-            DMA->INT_EN_TFR = (0x1 << DMA_MAX_CHANNEL_NUM) | 0x0;
-        }
-
-        if (Int & DMA_Int_Err) {
-            DMA->INT_EN_ERR = (0x1 << DMA_MAX_CHANNEL_NUM) | 0x0;
-        }
-    }
+		if (Int & DMA_Int_TfrComplete) {
+			DMA->INT_EN_TFR = (0x1 << DMA_MAX_CHANNEL_NUM) | 0x1;
+		} 
+		
+		if (Int & DMA_Int_Err) {
+			DMA->INT_EN_ERR = (0x1 << DMA_MAX_CHANNEL_NUM) | 0x1;
+		}
+	} else {
+		if (Int & DMA_Int_TfrComplete) {
+			DMA->INT_EN_TFR = (0x1 << DMA_MAX_CHANNEL_NUM) | 0x0;
+		} 
+		
+		if (Int & DMA_Int_Err) {
+			DMA->INT_EN_ERR = (0x1 << DMA_MAX_CHANNEL_NUM) | 0x0;
+		}
+	}
 }
 
 BOOL DMA_GetIntStatus(uint32_t Int) {
-    assert_param(IS_DMA_INT(Int));
-
-    if (Int & DMA_Int_TfrComplete) {
-        if (DMA->INT_TFR) {
-            return TRUE;
-        }
-    }
-
-    if (Int & DMA_Int_Err) {
-        if (DMA->INT_ERR) {
-            return TRUE;
-        }
-    }
-
-    return FALSE;
+	assert_param(IS_DMA_INT(Int));
+	
+	if (Int & DMA_Int_TfrComplete) {
+		if (DMA->INT_TFR) {
+			return TRUE;
+		}
+	}
+	
+	if (Int & DMA_Int_Err) {
+		if (DMA->INT_ERR) {
+			return TRUE;
+		}
+	}
+		
+	return FALSE;
 }
 
 void DMA_ClearInt(uint32_t Int) {
-    assert_param(IS_DMA_INT(Int));
-
-    if (Int & DMA_Int_TfrComplete) {
-        DMA->INT_CLEAR_TFR = 0x1;
-    }
-
-    if (Int & DMA_Int_Err) {
-        DMA->INT_CLEAR_ERR = 0x1;
-    }
+	assert_param(IS_DMA_INT(Int));
+	
+	if (Int & DMA_Int_TfrComplete) {
+		DMA->INT_CLEAR_TFR = 0x1;
+	}
+	
+	if (Int & DMA_Int_Err) {
+		DMA->INT_CLEAR_ERR = 0x1;
+	}
 }
 
 BOOL DMA_IsBusy() {
-    return (DMA->CH_EN_b.EN) ? TRUE : FALSE;
+	return (DMA->CH_EN_b.EN) ? TRUE : FALSE;
 }
 
 BOOL DMA_Transfer(BLOCK_DESC *blockList) {
-    BLOCK_DESC *p;
-    if (!blockList) {
-        return FALSE;
-    }
+	BLOCK_DESC *p;
+	if (!blockList) {
+		return FALSE;
+	}
+	
+	if (DMA_IsBusy()) {
+		return FALSE;
+	}
+	
+	p = blockList;
+	while (p) {
+		BOOL llp = FALSE;
+		INNER_BLOCK_DESC *inner = (INNER_BLOCK_DESC *)p;
+		if (p->nextBlock) {
+			llp = TRUE;
+		}
+		
+		inner->high.INNER.CTL_HI = 0;
+		inner->high.INNER.CTL_HI_b.BLOCK_TS = (p->number >> DMA_TR_WIDTH_32_BIT);
+		inner->high.INNER.CTL_HI_b.DONE = 0;
+		
+		inner->nextBlock = p->nextBlock;
+		
+		inner->low.INNER.CTL_LOW = 0;
+		inner->low.INNER.CTL_LOW_b.INT_EN = TRUE;
+		inner->low.INNER.CTL_LOW_b.DST_TR_WIDTH 	= DMA_TR_WIDTH_32_BIT;
+	  inner->low.INNER.CTL_LOW_b.SRC_TR_WIDTH 	= DMA_TR_WIDTH_32_BIT;
+	  inner->low.INNER.CTL_LOW_b.DINC 					= DMA_INC_INCREMENT;
+	  inner->low.INNER.CTL_LOW_b.SINC 					= DMA_INC_INCREMENT;
+	  inner->low.INNER.CTL_LOW_b.DEST_MSIZE 		= 0;
+	  inner->low.INNER.CTL_LOW_b.SRC_MSIZE 		  = 0;
+	  inner->low.INNER.CTL_LOW_b.SRC_GATHER_EN  = FALSE;
+	  inner->low.INNER.CTL_LOW_b.DST_SCATTER_EN = FALSE;
+	  inner->low.INNER.CTL_LOW_b.TT_FC 					= 0;
+    inner->low.INNER.CTL_LOW_b.DMS    				= 0;
+	  inner->low.INNER.CTL_LOW_b.SMS    				= 0;
+	  inner->low.INNER.CTL_LOW_b.LLP_DST_EN   	= llp;
+	  inner->low.INNER.CTL_LOW_b.LLP_SRC_EN   	= llp;
+		
+		if ((uint32_t)inner == (uint32_t)blockList) {
+			// copy to DMA
+			DMA->SAR0 = llp ? 0x0 : inner->srcAddr ;
+			DMA->DAR0 = llp ? 0x0 : inner->dstAddr ;
+			
+			DMA->CTL_HI0 = llp ? 0x0 : inner->high.INNER.CTL_HI;
+			DMA->CTL_LOW0 = inner->low.INNER.CTL_LOW;
+			
+			DMA->LLP0 = llp ? (uint32_t)inner : 0x0;
+		}
+		
+		p = (BLOCK_DESC *)inner->nextBlock;
+	}
 
-    if (DMA_IsBusy()) {
-        return FALSE;
-    }
-
-    p = blockList;
-    while (p) {
-        BOOL llp = FALSE;
-        INNER_BLOCK_DESC *inner = (INNER_BLOCK_DESC *)p;
-        if (p->nextBlock) {
-            llp = TRUE;
-        }
-
-        inner->high.INNER.CTL_HI = 0;
-        inner->high.INNER.CTL_HI_b.BLOCK_TS = (p->number >> DMA_TR_WIDTH_32_BIT);
-        inner->high.INNER.CTL_HI_b.DONE = 0;
-
-        inner->nextBlock = p->nextBlock;
-
-        inner->low.INNER.CTL_LOW = 0;
-        inner->low.INNER.CTL_LOW_b.INT_EN = TRUE;
-        inner->low.INNER.CTL_LOW_b.DST_TR_WIDTH     = DMA_TR_WIDTH_32_BIT;
-      inner->low.INNER.CTL_LOW_b.SRC_TR_WIDTH   = DMA_TR_WIDTH_32_BIT;
-      inner->low.INNER.CTL_LOW_b.DINC                   = DMA_INC_INCREMENT;
-      inner->low.INNER.CTL_LOW_b.SINC                   = DMA_INC_INCREMENT;
-      inner->low.INNER.CTL_LOW_b.DEST_MSIZE         = 0;
-      inner->low.INNER.CTL_LOW_b.SRC_MSIZE        = 0;
-      inner->low.INNER.CTL_LOW_b.SRC_GATHER_EN  = FALSE;
-      inner->low.INNER.CTL_LOW_b.DST_SCATTER_EN = FALSE;
-      inner->low.INNER.CTL_LOW_b.TT_FC                  = 0;
-    inner->low.INNER.CTL_LOW_b.DMS                  = 0;
-      inner->low.INNER.CTL_LOW_b.SMS                    = 0;
-      inner->low.INNER.CTL_LOW_b.LLP_DST_EN     = llp;
-      inner->low.INNER.CTL_LOW_b.LLP_SRC_EN     = llp;
-
-        if ((uint32_t)inner == (uint32_t)blockList) {
-            // copy to DMA
-            DMA->SAR0 = llp ? 0x0 : inner->srcAddr ;
-            DMA->DAR0 = llp ? 0x0 : inner->dstAddr ;
-
-            DMA->CTL_HI0 = llp ? 0x0 : inner->high.INNER.CTL_HI;
-            DMA->CTL_LOW0 = inner->low.INNER.CTL_LOW;
-
-            DMA->LLP0 = llp ? (uint32_t)inner : 0x0;
-        }
-
-        p = (BLOCK_DESC *)inner->nextBlock;
-    }
-
-    // open channel 0
-    DMA->CH_EN = (0x1 << DMA_MAX_CHANNEL_NUM) | 0x1;
-
-    return TRUE;
+	// open channel 0
+	DMA->CH_EN = (0x1 << DMA_MAX_CHANNEL_NUM) | 0x1;
+	
+	return TRUE;
 }
 

bsp/CME_M7/StdPeriph_Driver/src/cmem7_efuse.c

@@ -1,255 +1,255 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_efuse.c
-    *
-    * @brief    CMEM7 EFUSE source file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_efuse.c
+	*
+	* @brief    CMEM7 EFUSE source file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #include "cmem7_efuse.h"
 
 static void efuse_SetClock(uint8_t dividor) {
-    if (dividor <= 2) {
-        GLOBAL_CTRL->CLK_SEL_1_b.EFUSE_CLK = 0;
-    } else if (dividor <= 4) {
-        GLOBAL_CTRL->CLK_SEL_1_b.EFUSE_CLK = 1;
-    } else if (dividor <= 8) {
-        GLOBAL_CTRL->CLK_SEL_1_b.EFUSE_CLK = 2;
-    } else {
-        GLOBAL_CTRL->CLK_SEL_1_b.EFUSE_CLK = 3;
-    }
+	if (dividor <= 2) {
+		GLOBAL_CTRL->CLK_SEL_1_b.EFUSE_CLK = 0;
+	} else if (dividor <= 4) {
+		GLOBAL_CTRL->CLK_SEL_1_b.EFUSE_CLK = 1;
+	} else if (dividor <= 8) {
+		GLOBAL_CTRL->CLK_SEL_1_b.EFUSE_CLK = 2;
+	} else {
+		GLOBAL_CTRL->CLK_SEL_1_b.EFUSE_CLK = 3;
+	}
 }
 
 static uint32_t efuse_GetClock() {
-    return SYSTEM_CLOCK_FREQ / (1 << (GLOBAL_CTRL->CLK_SEL_1_b.EFUSE_CLK + 1));
+	return SYSTEM_CLOCK_FREQ / (1 << (GLOBAL_CTRL->CLK_SEL_1_b.EFUSE_CLK + 1));
 }
 
 // static uint8_t efuse_Crc8Bit(uint8_t data, uint8_t crc) {
-//  uint8_t newCrc;
-//  uint8_t d[8], c[8], i;
-//
-//  for (i = 0; i < 8; i++) {
-//      d[i] = (data >> i) & 0x01;
-//      c[i] = (crc >> i) & 0x01;
-//  }
-//
-//  newCrc = d[7] ^ d[6] ^ d[0] ^ c[0] ^ c[6] ^ c[7];
-//  newCrc |= (d[6] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[6]) << 1;
-//  newCrc |= (d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[6]) << 2;
-//  newCrc |= (d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[3] ^ c[7]) << 3;
-//  newCrc |= (d[4] ^ d[3] ^ d[2] ^ c[2] ^ c[3] ^ c[4]) << 4;
-//  newCrc |= (d[5] ^ d[4] ^ d[3] ^ c[3] ^ c[4] ^ c[5]) << 5;
-//  newCrc |= (d[6] ^ d[5] ^ d[4] ^ c[4] ^ c[5] ^ c[6]) << 6;
-//  newCrc |= (d[7] ^ d[6] ^ d[5] ^ c[5] ^ c[6] ^ c[7]) << 1;
-//
-//  return newCrc;
+// 	uint8_t newCrc;
+// 	uint8_t d[8], c[8], i;
+// 	
+// 	for (i = 0; i < 8; i++) {
+// 		d[i] = (data >> i) & 0x01;
+// 		c[i] = (crc >> i) & 0x01;
+// 	}
+// 	
+// 	newCrc = d[7] ^ d[6] ^ d[0] ^ c[0] ^ c[6] ^ c[7];
+// 	newCrc |= (d[6] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[6]) << 1;
+// 	newCrc |= (d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[6]) << 2;
+// 	newCrc |= (d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[3] ^ c[7]) << 3;
+// 	newCrc |= (d[4] ^ d[3] ^ d[2] ^ c[2] ^ c[3] ^ c[4]) << 4;
+// 	newCrc |= (d[5] ^ d[4] ^ d[3] ^ c[3] ^ c[4] ^ c[5]) << 5;
+// 	newCrc |= (d[6] ^ d[5] ^ d[4] ^ c[4] ^ c[5] ^ c[6]) << 6;
+// 	newCrc |= (d[7] ^ d[6] ^ d[5] ^ c[5] ^ c[6] ^ c[7]) << 1;
+// 	
+// 	return newCrc;
 // }
 
 // static uint8_t efuse_Crc(EFUSE_AesKey* key, uint8_t lock, BOOL isLowRegion) {
-//  uint8_t crc = 0;
-//
-//  if (isLowRegion) {
-//      crc = efuse_Crc8Bit(key->key0, crc);
-//      crc = efuse_Crc8Bit(key->key0 >> 8, crc);
-//      crc = efuse_Crc8Bit(key->key0 >> 16, crc);
-//      crc = efuse_Crc8Bit(key->key0 >> 24, crc);
-//      crc = efuse_Crc8Bit(key->key1, crc);
-//      crc = efuse_Crc8Bit(key->key1 >> 8, crc);
-//      crc = efuse_Crc8Bit(key->key1 >> 16, crc);
-//      crc = efuse_Crc8Bit(key->key1 >> 24, crc);
-//      crc = efuse_Crc8Bit(key->key2, crc);
-//      crc = efuse_Crc8Bit(key->key2 >> 8, crc);
-//      crc = efuse_Crc8Bit(key->key2 >> 16, crc);
-//      crc = efuse_Crc8Bit(key->key2 >> 24, crc);
-//      crc = efuse_Crc8Bit(key->key3, crc);
-//      crc = efuse_Crc8Bit(key->key3 >> 8, crc);
-//      crc = efuse_Crc8Bit(key->key3 >> 16, crc);
-//      crc = efuse_Crc8Bit(key->key3 >> 24, crc);
-//      crc = efuse_Crc8Bit(lock, crc);
-//      crc = efuse_Crc8Bit(0x0, crc);
-//      crc = efuse_Crc8Bit(0x0, crc);
-//  } else {
-//      crc = efuse_Crc8Bit(key->key4, crc);
-//      crc = efuse_Crc8Bit(key->key4 >> 8, crc);
-//      crc = efuse_Crc8Bit(key->key4 >> 16, crc);
-//      crc = efuse_Crc8Bit(key->key4 >> 24, crc);
-//      crc = efuse_Crc8Bit(key->key5, crc);
-//      crc = efuse_Crc8Bit(key->key5 >> 8, crc);
-//      crc = efuse_Crc8Bit(key->key5 >> 16, crc);
-//      crc = efuse_Crc8Bit(key->key5 >> 24, crc);
-//      crc = efuse_Crc8Bit(key->key6, crc);
-//      crc = efuse_Crc8Bit(key->key6 >> 8, crc);
-//      crc = efuse_Crc8Bit(key->key6 >> 16, crc);
-//      crc = efuse_Crc8Bit(key->key6 >> 24, crc);
-//      crc = efuse_Crc8Bit(key->key7, crc);
-//      crc = efuse_Crc8Bit(key->key7 >> 8, crc);
-//      crc = efuse_Crc8Bit(key->key7 >> 16, crc);
-//      crc = efuse_Crc8Bit(key->key7 >> 24, crc);
-//      crc = efuse_Crc8Bit(lock, crc);
-//      crc = efuse_Crc8Bit(0x0, crc);
-//      crc = efuse_Crc8Bit(0x0, crc);
-//  }
-//
-//  return crc;
+// 	uint8_t crc = 0;
+// 	
+// 	if (isLowRegion) {
+// 		crc = efuse_Crc8Bit(key->key0, crc);
+// 		crc = efuse_Crc8Bit(key->key0 >> 8, crc);
+// 		crc = efuse_Crc8Bit(key->key0 >> 16, crc);
+// 		crc = efuse_Crc8Bit(key->key0 >> 24, crc);
+// 		crc = efuse_Crc8Bit(key->key1, crc);
+// 		crc = efuse_Crc8Bit(key->key1 >> 8, crc);
+// 		crc = efuse_Crc8Bit(key->key1 >> 16, crc);
+// 		crc = efuse_Crc8Bit(key->key1 >> 24, crc);
+// 		crc = efuse_Crc8Bit(key->key2, crc);
+// 		crc = efuse_Crc8Bit(key->key2 >> 8, crc);
+// 		crc = efuse_Crc8Bit(key->key2 >> 16, crc);
+// 		crc = efuse_Crc8Bit(key->key2 >> 24, crc);
+// 		crc = efuse_Crc8Bit(key->key3, crc);
+// 		crc = efuse_Crc8Bit(key->key3 >> 8, crc);
+// 		crc = efuse_Crc8Bit(key->key3 >> 16, crc);
+// 		crc = efuse_Crc8Bit(key->key3 >> 24, crc);
+// 		crc = efuse_Crc8Bit(lock, crc);
+// 		crc = efuse_Crc8Bit(0x0, crc);
+// 		crc = efuse_Crc8Bit(0x0, crc);
+// 	} else {
+// 		crc = efuse_Crc8Bit(key->key4, crc);
+// 		crc = efuse_Crc8Bit(key->key4 >> 8, crc);
+// 		crc = efuse_Crc8Bit(key->key4 >> 16, crc);
+// 		crc = efuse_Crc8Bit(key->key4 >> 24, crc);
+// 		crc = efuse_Crc8Bit(key->key5, crc);
+// 		crc = efuse_Crc8Bit(key->key5 >> 8, crc);
+// 		crc = efuse_Crc8Bit(key->key5 >> 16, crc);
+// 		crc = efuse_Crc8Bit(key->key5 >> 24, crc);
+// 		crc = efuse_Crc8Bit(key->key6, crc);
+// 		crc = efuse_Crc8Bit(key->key6 >> 8, crc);
+// 		crc = efuse_Crc8Bit(key->key6 >> 16, crc);
+// 		crc = efuse_Crc8Bit(key->key6 >> 24, crc);
+// 		crc = efuse_Crc8Bit(key->key7, crc);
+// 		crc = efuse_Crc8Bit(key->key7 >> 8, crc);
+// 		crc = efuse_Crc8Bit(key->key7 >> 16, crc);
+// 		crc = efuse_Crc8Bit(key->key7 >> 24, crc);
+// 		crc = efuse_Crc8Bit(lock, crc);
+// 		crc = efuse_Crc8Bit(0x0, crc);
+// 		crc = efuse_Crc8Bit(0x0, crc);
+// 	}
+// 	
+// 	return crc;
 // }
 
 void EFUSE_Init(EFUSE_InitTypeDef* init) {
-    assert_param(init);
-    assert_param(IS_EFUSE_TMRF(init->EFUSE_TMRF));
+	assert_param(init);
+	assert_param(IS_EFUSE_TMRF(init->EFUSE_TMRF));
+	
+	efuse_SetClock(init->EFUSE_ClockDividor);
+	EFUSE->USER_CTRL_LOW_b.TMRF = init->EFUSE_TMRF;
+	EFUSE->USER_CTRL_HI_b.TMRF = init->EFUSE_TMRF;
+	if (init->timing) {
+		uint32_t value;
+		
+		value = (init->timing->EFUSE_Tpwph * (efuse_GetClock() / 1000000) / 1000);
+		value = (value == 0) ? 1 : value;
+		EFUSE->TIMING_0_b.TPWPH = value >> 2;
+		EFUSE->TIMING_1_b.TPWPH = value & 0x00000003;
 
-    efuse_SetClock(init->EFUSE_ClockDividor);
-    EFUSE->USER_CTRL_LOW_b.TMRF = init->EFUSE_TMRF;
-    EFUSE->USER_CTRL_HI_b.TMRF = init->EFUSE_TMRF;
-    if (init->timing) {
-        uint32_t value;
+		value = (init->timing->EFUSE_Trac * (efuse_GetClock() / 1000000) / 1000);
+		value = (value == 0) ? 1 : value;
+		EFUSE->TIMING_0_b.TRAC = value;
 
-        value = (init->timing->EFUSE_Tpwph * (efuse_GetClock() / 1000000) / 1000);
-        value = (value == 0) ? 1 : value;
-        EFUSE->TIMING_0_b.TPWPH = value >> 2;
-        EFUSE->TIMING_1_b.TPWPH = value & 0x00000003;
+		value = (init->timing->EFUSE_Trah * (efuse_GetClock() / 1000000) / 1000);
+		value = (value == 0) ? 1 : value;
+		EFUSE->TIMING_0_b.TRAH = value;
+		
+		value = (init->timing->EFUSE_Trpw * (efuse_GetClock() / 1000000) / 1000);
+		value = (value == 0) ? 1 : value;
+		EFUSE->TIMING_0_b.TRPW = value;
 
-        value = (init->timing->EFUSE_Trac * (efuse_GetClock() / 1000000) / 1000);
-        value = (value == 0) ? 1 : value;
-        EFUSE->TIMING_0_b.TRAC = value;
+		value = (init->timing->EFUSE_Trc * (efuse_GetClock() / 1000000) / 1000);
+		value = (value == 0) ? 1 : value;
+		EFUSE->TIMING_0_b.TRC = value;
+		
+		value = (init->timing->EFUSE_Tesr * (efuse_GetClock() / 1000000) / 1000);
+		value = (value == 0) ? 1 : value;
+		EFUSE->TIMING_0_b.TESR = value;
 
-        value = (init->timing->EFUSE_Trah * (efuse_GetClock() / 1000000) / 1000);
-        value = (value == 0) ? 1 : value;
-        EFUSE->TIMING_0_b.TRAH = value;
+		value = (init->timing->EFUSE_Tprs * (efuse_GetClock() / 1000000) / 1000);
+		value = (value == 0) ? 1 : value;
+		EFUSE->TIMING_0_b.TPRS = value;
 
-        value = (init->timing->EFUSE_Trpw * (efuse_GetClock() / 1000000) / 1000);
-        value = (value == 0) ? 1 : value;
-        EFUSE->TIMING_0_b.TRPW = value;
+		value = (init->timing->EFUSE_Tpi * (efuse_GetClock() / 1000000) / 1000);
+		value = (value == 0) ? 1 : value;
+		EFUSE->TIMING_1_b.TPIT = value;
 
-        value = (init->timing->EFUSE_Trc * (efuse_GetClock() / 1000000) / 1000);
-        value = (value == 0) ? 1 : value;
-        EFUSE->TIMING_0_b.TRC = value;
+		value = (init->timing->EFUSE_Tpp * (efuse_GetClock() / 1000000) / 1000);
+		value = (value == 0) ? 1 : value;
+		EFUSE->TIMING_1_b.TPP = value;
 
-        value = (init->timing->EFUSE_Tesr * (efuse_GetClock() / 1000000) / 1000);
-        value = (value == 0) ? 1 : value;
-        EFUSE->TIMING_0_b.TESR = value;
+		value = (init->timing->EFUSE_Teps * (efuse_GetClock() / 1000000) / 1000);
+		value = (value == 0) ? 1 : value;
+		EFUSE->TIMING_1_b.TEPS = value;
 
-        value = (init->timing->EFUSE_Tprs * (efuse_GetClock() / 1000000) / 1000);
-        value = (value == 0) ? 1 : value;
-        EFUSE->TIMING_0_b.TPRS = value;
-
-        value = (init->timing->EFUSE_Tpi * (efuse_GetClock() / 1000000) / 1000);
-        value = (value == 0) ? 1 : value;
-        EFUSE->TIMING_1_b.TPIT = value;
-
-        value = (init->timing->EFUSE_Tpp * (efuse_GetClock() / 1000000) / 1000);
-        value = (value == 0) ? 1 : value;
-        EFUSE->TIMING_1_b.TPP = value;
-
-        value = (init->timing->EFUSE_Teps * (efuse_GetClock() / 1000000) / 1000);
-        value = (value == 0) ? 1 : value;
-        EFUSE->TIMING_1_b.TEPS = value;
-
-        value = (init->timing->EFUSE_Teps * (efuse_GetClock() / 1000000) / 1000);
-        value = (value == 0) ? 1 : value;
-        EFUSE->TIMING_1_b.TPWPS = value;
-    }
+		value = (init->timing->EFUSE_Teps * (efuse_GetClock() / 1000000) / 1000);
+		value = (value == 0) ? 1 : value;
+		EFUSE->TIMING_1_b.TPWPS = value;
+	}
 }
 
 /* It only can be written once */
 // BOOL EFUSE_Write(EFUSE_AesKey* key) {
-//   assert_param(key);
-//
-//  if ((EFUSE->USER_CTRL_LOW_b.LOCK || EFUSE->USER_CTRL_LOW_b.BUSY) ||
-//      (EFUSE->USER_CTRL_HI_b.LOCK || EFUSE->USER_CTRL_HI_b.BUSY)) {
-//      return FALSE;
-//  }
-//
-//  // write low region
-//  EFUSE->USER_DATA0_LOW = key->key0;
-//  EFUSE->USER_DATA1_LOW = key->key1;
-//  EFUSE->USER_DATA2_LOW = key->key2;
-//  EFUSE->USER_DATA3_LOW = key->key3;
-//  EFUSE->USER_DATA4_LOW_b.CRC = efuse_Crc(key, 0x1, TRUE);
-//  EFUSE->USER_DATA4_LOW_b.LOCK = 1;
-//  EFUSE->USER_CTRL_LOW_b.WR_EN = FALSE;
-//  EFUSE->USER_CTRL_LOW_b.WR_EN = TRUE;
-//
-//  udelay(1000);
-//  while (EFUSE->USER_CTRL_LOW_b.BUSY) ;
-//
-//  if (EFUSE->USER_CTRL_LOW_b.WR_CRC_ERR) {
-//      return FALSE;
-//  }
-//
-//  // write high region
-//  EFUSE->USER_DATA0_HI = key->key4;
-//  EFUSE->USER_DATA1_HI = key->key5;
-//  EFUSE->USER_DATA2_HI = key->key6;
-//  EFUSE->USER_DATA3_HI = key->key7;
-//  EFUSE->USER_DATA4_HI_b.CRC = efuse_Crc(key, 0x1, FALSE);
-//  EFUSE->USER_DATA4_HI_b.LOCK = 1;
-//  EFUSE->USER_CTRL_HI_b.WR_EN = FALSE;
-//  EFUSE->USER_CTRL_HI_b.WR_EN = TRUE;
-//
-//  udelay(1000);
-//  while (EFUSE->USER_CTRL_HI_b.BUSY) ;
-//
-//  if (EFUSE->USER_CTRL_HI_b.WR_CRC_ERR) {
-//      return FALSE;
-//  }
-//  return TRUE;
+//   assert_param(key);	
+// 	
+// 	if ((EFUSE->USER_CTRL_LOW_b.LOCK || EFUSE->USER_CTRL_LOW_b.BUSY) ||
+// 		(EFUSE->USER_CTRL_HI_b.LOCK || EFUSE->USER_CTRL_HI_b.BUSY)) {
+// 		return FALSE;
+// 	}
+// 	
+// 	// write low region
+// 	EFUSE->USER_DATA0_LOW = key->key0;
+// 	EFUSE->USER_DATA1_LOW = key->key1;
+// 	EFUSE->USER_DATA2_LOW = key->key2;
+// 	EFUSE->USER_DATA3_LOW = key->key3;
+// 	EFUSE->USER_DATA4_LOW_b.CRC = efuse_Crc(key, 0x1, TRUE);
+// 	EFUSE->USER_DATA4_LOW_b.LOCK = 1;
+// 	EFUSE->USER_CTRL_LOW_b.WR_EN = FALSE;
+// 	EFUSE->USER_CTRL_LOW_b.WR_EN = TRUE;
+// 	
+// 	udelay(1000);
+// 	while (EFUSE->USER_CTRL_LOW_b.BUSY) ;
+// 	
+// 	if (EFUSE->USER_CTRL_LOW_b.WR_CRC_ERR) {
+// 		return FALSE;
+// 	}
+// 	
+// 	// write high region
+// 	EFUSE->USER_DATA0_HI = key->key4;
+// 	EFUSE->USER_DATA1_HI = key->key5;
+// 	EFUSE->USER_DATA2_HI = key->key6;
+// 	EFUSE->USER_DATA3_HI = key->key7;
+// 	EFUSE->USER_DATA4_HI_b.CRC = efuse_Crc(key, 0x1, FALSE);
+// 	EFUSE->USER_DATA4_HI_b.LOCK = 1;
+// 	EFUSE->USER_CTRL_HI_b.WR_EN = FALSE;
+// 	EFUSE->USER_CTRL_HI_b.WR_EN = TRUE;
+// 	
+// 	udelay(1000);
+// 	while (EFUSE->USER_CTRL_HI_b.BUSY) ;
+// 	
+// 	if (EFUSE->USER_CTRL_HI_b.WR_CRC_ERR) {
+// 		return FALSE;
+// 	}
+// 	return TRUE;
 // }
 
 BOOL EFUSE_Compare(EFUSE_AesKey* key) {
-  assert_param(key);
-
-    if (EFUSE->USER_CTRL_LOW_b.BUSY || EFUSE->USER_CTRL_HI_b.BUSY) {
-        return FALSE;
-    }
-
-    // compare low region
-    EFUSE->USER_DATA0_LOW = key->key0;
-    EFUSE->USER_DATA1_LOW = key->key1;
-    EFUSE->USER_DATA2_LOW = key->key2;
-    EFUSE->USER_DATA3_LOW = key->key3;
-    EFUSE->USER_CTRL_LOW_b.RD_EN = FALSE;
-    EFUSE->USER_CTRL_LOW_b.RD_EN = TRUE;
-
-    udelay(2);
-    while (EFUSE->USER_CTRL_LOW_b.BUSY) ;
-
-    if (EFUSE->USER_CTRL_LOW_b.COMPARE_FAIL) {
-        return FALSE;
-    }
-
-    // compare high region
-    EFUSE->USER_DATA0_HI = key->key4;
-    EFUSE->USER_DATA1_HI = key->key5;
-    EFUSE->USER_DATA2_HI = key->key6;
-    EFUSE->USER_DATA3_HI = key->key7;
-    EFUSE->USER_CTRL_HI_b.RD_EN = FALSE;
-    EFUSE->USER_CTRL_HI_b.RD_EN = TRUE;
-
-    udelay(2);
-    while (EFUSE->USER_CTRL_HI_b.BUSY) ;
-
-    if (EFUSE->USER_CTRL_HI_b.COMPARE_FAIL) {
-        return FALSE;
-    }
-
-    return TRUE;
+  assert_param(key);	
+	
+	if (EFUSE->USER_CTRL_LOW_b.BUSY || EFUSE->USER_CTRL_HI_b.BUSY) {
+		return FALSE;
+	}
+	
+	// compare low region
+	EFUSE->USER_DATA0_LOW = key->key0;
+	EFUSE->USER_DATA1_LOW = key->key1;
+	EFUSE->USER_DATA2_LOW = key->key2;
+	EFUSE->USER_DATA3_LOW = key->key3;
+	EFUSE->USER_CTRL_LOW_b.RD_EN = FALSE;
+	EFUSE->USER_CTRL_LOW_b.RD_EN = TRUE;
+	
+	udelay(2);
+	while (EFUSE->USER_CTRL_LOW_b.BUSY) ;
+	
+	if (EFUSE->USER_CTRL_LOW_b.COMPARE_FAIL) {
+		return FALSE;
+	}
+	
+	// compare high region
+	EFUSE->USER_DATA0_HI = key->key4;
+	EFUSE->USER_DATA1_HI = key->key5;
+	EFUSE->USER_DATA2_HI = key->key6;
+	EFUSE->USER_DATA3_HI = key->key7;
+	EFUSE->USER_CTRL_HI_b.RD_EN = FALSE;
+	EFUSE->USER_CTRL_HI_b.RD_EN = TRUE;
+	
+	udelay(2);
+	while (EFUSE->USER_CTRL_HI_b.BUSY) ;
+	
+	if (EFUSE->USER_CTRL_HI_b.COMPARE_FAIL) {
+		return FALSE;
+	}
+	
+	return TRUE;	
 }
 

bsp/CME_M7/StdPeriph_Driver/src/cmem7_flash.c

@@ -1,35 +1,35 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_flash.c
-    *
-    * @brief    CMEM7 flash controller source file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_flash.c
+	*
+	* @brief    CMEM7 flash controller source file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #include "cmem7_flash.h"
 
 typedef struct {
   union {
     uint16_t  STATUS;                         /*!< status register                     */
-
+    
     struct {
       uint16_t  WIP:  1;                      /*!< in writting                         */
       uint16_t  WEL:  1;                      /*!< write enable                        */
@@ -76,325 +76,325 @@ typedef void (*WAIT)(void);
 static WAIT wait;
 
 static void flash_setClock(uint8_t dividor) {
-    dividor = (dividor < 2) ? 2 : dividor;
-    NOR_FLASH->CTRL0_b.DIV = dividor / 2 - 1;
+	dividor = (dividor < 2) ? 2 : dividor;
+	NOR_FLASH->CTRL0_b.DIV = dividor / 2 - 1;
 }
 
 static void flash_cleanOperation() {
-    NOR_FLASH->TRIGGER_b.OP_CLEAN = TRUE;
-    while (NOR_FLASH->STATUS_b.BUSY);
-
-    NOR_FLASH->TRIGGER_b.OP_CLEAN = FALSE;
-    while (NOR_FLASH->STATUS_b.BUSY);
+	NOR_FLASH->TRIGGER_b.OP_CLEAN = TRUE;	
+	while (NOR_FLASH->STATUS_b.BUSY);
+	
+	NOR_FLASH->TRIGGER_b.OP_CLEAN = FALSE;	
+	while (NOR_FLASH->STATUS_b.BUSY);
 }
 
 static uint8_t flash_ReadInnerStatusLow() {
-    NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 1;
-    NOR_FLASH->CTRL1_b.CMD = FLASH_CMD_RD_INNER_STATUS_LOW;
-    NOR_FLASH->TRIGGER_b.OP_START = TRUE;
-
-    while (NOR_FLASH->STATUS_b.BUSY);
-
-    return (uint8_t)NOR_FLASH->DATA;
+	NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 1;
+	NOR_FLASH->CTRL1_b.CMD = FLASH_CMD_RD_INNER_STATUS_LOW;
+	NOR_FLASH->TRIGGER_b.OP_START = TRUE;
+	
+	while (NOR_FLASH->STATUS_b.BUSY);
+	
+	return (uint8_t)NOR_FLASH->DATA;
 }
 
 static uint8_t flash_ReadInnerStatusHigh() {
   NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 1;
-    NOR_FLASH->CTRL1_b.CMD = FLASH_CMD_RD_INNER_STATUS_HIGH;
-    NOR_FLASH->TRIGGER_b.OP_START = TRUE;
-
-    while (NOR_FLASH->STATUS_b.BUSY);
-
-    return (uint8_t)NOR_FLASH->DATA;
+	NOR_FLASH->CTRL1_b.CMD = FLASH_CMD_RD_INNER_STATUS_HIGH;
+	NOR_FLASH->TRIGGER_b.OP_START = TRUE;
+	
+	while (NOR_FLASH->STATUS_b.BUSY);
+	
+	return (uint8_t)NOR_FLASH->DATA;	
 }
 
 //static void flash_WaitInWritting() {
 void flash_WaitInWritting(void) {
-    FLASH_INNER_STATUS s;
-
-    while (NOR_FLASH->STATUS_b.BUSY);
-
-    do {
-        s.INNER.STATUS = flash_ReadInnerStatusLow();
-        if (!s.INNER.STATUS_b.WIP) {
-            break;
-        }
-
-        if (wait) {
-            (*wait)();
-        }
-    } while (1);
+	FLASH_INNER_STATUS s;
+	
+	while (NOR_FLASH->STATUS_b.BUSY);
+	
+	do {
+		s.INNER.STATUS = flash_ReadInnerStatusLow();
+		if (!s.INNER.STATUS_b.WIP) {
+			break;
+		}
+		
+		if (wait) {
+			(*wait)();
+		}
+	} while (1);
 }
 
 static void flash_WriteWriteEnable(BOOL enable) {
   NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 0;
-    NOR_FLASH->CTRL1_b.CMD =
-      enable ? FLASH_CMD_WR_WRITE_ENABLE : FLASH_CMD_WR_WRITE_DISABLE;
-
-    NOR_FLASH->TRIGGER_b.OP_START = TRUE;
-
-    flash_WaitInWritting();
+	NOR_FLASH->CTRL1_b.CMD = 
+	  enable ? FLASH_CMD_WR_WRITE_ENABLE : FLASH_CMD_WR_WRITE_DISABLE;
+	
+	NOR_FLASH->TRIGGER_b.OP_START = TRUE;
+	
+	flash_WaitInWritting();
 }
 
 static void flash_WriteStatusReg(FLASH_INNER_STATUS *s) {
   uint16_t tmp = s->INNER.STATUS;
-
-    NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 2;
-    NOR_FLASH->CTRL1_b.CMD = FLASH_CME_WR_STATUS_REG;
-    NOR_FLASH->DATA = ((tmp << 8) | (tmp >> 8)) << 16;
-    NOR_FLASH->TRIGGER_b.OP_START = TRUE;
-
-    flash_WaitInWritting();
+	
+	NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 2;
+	NOR_FLASH->CTRL1_b.CMD = FLASH_CME_WR_STATUS_REG;
+	NOR_FLASH->DATA = ((tmp << 8) | (tmp >> 8)) << 16;
+	NOR_FLASH->TRIGGER_b.OP_START = TRUE;
+	
+	flash_WaitInWritting();
 }
 
-static void flash_Erase(uint8_t cmd, uint32_t addr) {
-    NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 0;
-    NOR_FLASH->CTRL1_b.CMD = cmd;
-    NOR_FLASH->CTRL1_b.ADDRESS = addr;
-    NOR_FLASH->TRIGGER_b.OP_START = TRUE;
-
-    flash_WaitInWritting();
+static void flash_Erase(uint8_t cmd, uint32_t addr) {	
+	NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 0;
+	NOR_FLASH->CTRL1_b.CMD = cmd;
+	NOR_FLASH->CTRL1_b.ADDRESS = addr;
+	NOR_FLASH->TRIGGER_b.OP_START = TRUE;
+	
+	flash_WaitInWritting();
 }
 
 static void flash_WriteDeepPowerDownEnable(BOOL enable) {
   NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 0;
-    NOR_FLASH->CTRL1_b.CMD =
-      enable ? FLASH_CME_WR_ENTER_DEEP_PD : FLASH_CME_WR_EXIT_DEEP_PD;
-
-    NOR_FLASH->TRIGGER_b.OP_START = TRUE;
-
-    flash_WaitInWritting();
+	NOR_FLASH->CTRL1_b.CMD = 
+	  enable ? FLASH_CME_WR_ENTER_DEEP_PD : FLASH_CME_WR_EXIT_DEEP_PD;
+	
+	NOR_FLASH->TRIGGER_b.OP_START = TRUE;
+	
+	flash_WaitInWritting();
 }
 
 static void flash_RwReq(uint8_t cmd, uint32_t addr, uint16_t size) {
-    NOR_FLASH->CTRL0_b.RW_BYTE_CNT = size;
-    NOR_FLASH->CTRL1_b.CMD = cmd;
-    NOR_FLASH->CTRL1_b.ADDRESS = addr;
-
-    NOR_FLASH->TRIGGER_b.OP_START = TRUE;
+	NOR_FLASH->CTRL0_b.RW_BYTE_CNT = size;
+	NOR_FLASH->CTRL1_b.CMD = cmd;
+	NOR_FLASH->CTRL1_b.ADDRESS = addr;
+	
+	NOR_FLASH->TRIGGER_b.OP_START = TRUE;
 }
 
 //static void flash_WaitReadFifoNotEmpty() {
 void flash_WaitReadFifoNotEmpty(void) {
-    while (NOR_FLASH->STATUS_b.RD_FIFO_EMPTY) {
-        if (wait) {
-            (*wait)();
-        }
-    }
+	while (NOR_FLASH->STATUS_b.RD_FIFO_EMPTY) {
+		if (wait) {
+			(*wait)();
+		}
+	}
 }
 
 //static uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) {
 uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) {
-    uint16_t count = 0;
-
-    while (!NOR_FLASH->STATUS_b.RD_FIFO_EMPTY && size != 0) {
-    uint32_t d =    NOR_FLASH->DATA;
-        if (size > 3) {
-            *(data + count++) = d >> 24;
-            *(data + count++) = (d & 0x00FF0000) >> 16;
-            *(data + count++) = (d & 0x0000FF00) >> 8;
-            *(data + count++) = (d & 0x000000FF);
-            size -= 4;
-        } else if (size == 3) {
-            *(data + count++) = (d & 0x00FF0000) >> 16;
-            *(data + count++) = (d & 0x0000FF00) >> 8;
-            *(data + count++) = (d & 0x000000FF);
-            size -= 3;
-        } else if (size == 2) {
-            *(data + count++) = (d & 0x0000FF00) >> 8;
-            *(data + count++) = (d & 0x000000FF);
-            size -= 2;
-        } else if (size == 1) {
-            *(data + count++) = (d & 0x000000FF);
-            size -= 1;
-        }
-    }
-
-    return count;
+	uint16_t count = 0;
+	
+	while (!NOR_FLASH->STATUS_b.RD_FIFO_EMPTY && size != 0) {
+  	uint32_t d =	NOR_FLASH->DATA;
+		if (size > 3) {
+			*(data + count++) = d >> 24;
+			*(data + count++) = (d & 0x00FF0000) >> 16;
+			*(data + count++) = (d & 0x0000FF00) >> 8;
+			*(data + count++) = (d & 0x000000FF);
+			size -= 4;
+		} else if (size == 3) {
+			*(data + count++) = (d & 0x00FF0000) >> 16;
+			*(data + count++) = (d & 0x0000FF00) >> 8;
+			*(data + count++) = (d & 0x000000FF);
+			size -= 3;
+		} else if (size == 2) {
+			*(data + count++) = (d & 0x0000FF00) >> 8;
+			*(data + count++) = (d & 0x000000FF);
+			size -= 2;
+		} else if (size == 1) {
+			*(data + count++) = (d & 0x000000FF);
+			size -= 1;
+		}
+	}
+	
+	return count;
 }
 
 static uint16_t flash_WriteFifo(uint16_t size, uint8_t* data) {
-    uint16_t count = 0;
-
-    while (!NOR_FLASH->STATUS_b.WR_FIFO_FULL && size != 0) {
-        uint32_t d = 0;
-
-        if (size > 3) {
-            d = *(data + count++) << 24;
-            d |= *(data + count++) << 16;
-            d |= *(data + count++) << 8;
-            d |= *(data + count++);
-            size -= 4;
-        } else if (size == 3) {
-            d = *(data + count++) << 24;
-            d |= *(data + count++) << 16;
-            d |= *(data + count++) << 8;
-            size -= 3;
-        } else if (size == 2) {
-            d = *(data + count++) << 24;
-            d |= *(data + count++) << 16;
-            size -= 2;
-        } else if (size == 1) {
-            d = *(data + count++) << 24;
-            size -= 1;
-        }
-
-        NOR_FLASH->DATA = d;
-    }
-
-    return count;
+	uint16_t count = 0;
+	
+	while (!NOR_FLASH->STATUS_b.WR_FIFO_FULL && size != 0) { 	
+		uint32_t d = 0;
+		
+		if (size > 3) {
+			d = *(data + count++) << 24;
+			d |= *(data + count++) << 16;
+			d |= *(data + count++) << 8;
+			d |= *(data + count++);
+			size -= 4;
+		} else if (size == 3) {
+			d = *(data + count++) << 24;
+			d |= *(data + count++) << 16;
+			d |= *(data + count++) << 8;
+			size -= 3;
+		} else if (size == 2) {
+			d = *(data + count++) << 24;
+			d |= *(data + count++) << 16;
+			size -= 2;
+		} else if (size == 1) {
+			d = *(data + count++) << 24;
+			size -= 1;
+		}
+		
+		NOR_FLASH->DATA = d;		
+	}
+	
+	return count;
 }
 
 static uint16_t flash_WritePage(uint32_t addr, uint16_t size, uint8_t* data) {
-    uint16_t actualSize, retSize;
-
-    flash_WriteWriteEnable(TRUE);
-
-    actualSize = FLASH_PAGE_SIZE - (addr & (FLASH_PAGE_SIZE - 1));
-    actualSize = (size > actualSize) ? actualSize : size;
+	uint16_t actualSize, retSize;
+  
+	flash_WriteWriteEnable(TRUE);
+	
+	actualSize = FLASH_PAGE_SIZE - (addr & (FLASH_PAGE_SIZE - 1)); 
+	actualSize = (size > actualSize) ? actualSize : size;
   retSize = actualSize;
-
-    flash_RwReq(FLASH_CME_WR, addr, actualSize);
-
-    while (actualSize != 0) {
-        uint8_t count = flash_WriteFifo(actualSize, data);
-
-        actualSize -= count;
-        data += count;
-    }
-
-    flash_WaitInWritting();
-
-    return retSize;
+	
+	flash_RwReq(FLASH_CME_WR, addr, actualSize);
+	
+	while (actualSize != 0) {
+		uint8_t count = flash_WriteFifo(actualSize, data);
+		
+		actualSize -= count;
+		data += count;
+	}
+	
+	flash_WaitInWritting();
+	
+	return retSize;
 }
 
 void FLASH_Init(FLASH_InitTypeDef* init) {
-    FLASH_INNER_STATUS s;
+	FLASH_INNER_STATUS s;
+	
+	assert_param(init);
+	assert_param(IS_FLASH_PROTECT_MODE(init->FLASH_ProtectMode));
+	assert_param(IS_FLASH_PROTECT_REGION(init->FLASH_ProtectRegion));
+	
+	wait = init->FLASH_Wait;
+	flash_setClock(init->FLASH_ClockDividor);
+	
+	flash_cleanOperation();
+	
+	flash_WaitInWritting();
+	
+	s.INNER.STATUS = flash_ReadInnerStatusLow();
+	s.INNER.STATUS |= ((uint16_t)flash_ReadInnerStatusHigh()) << 8;
+	s.INNER.STATUS_b.BP = init->FLASH_ProtectRegion;
+	s.INNER.STATUS_b.SRP = init->FLASH_ProtectMode;
+	s.INNER.STATUS_b.QE = init->FLASH_QuadEnable;
 
-    assert_param(init);
-    assert_param(IS_FLASH_PROTECT_MODE(init->FLASH_ProtectMode));
-    assert_param(IS_FLASH_PROTECT_REGION(init->FLASH_ProtectRegion));
-
-    wait = init->FLASH_Wait;
-    flash_setClock(init->FLASH_ClockDividor);
-
-    flash_cleanOperation();
-
-    flash_WaitInWritting();
-
-    s.INNER.STATUS = flash_ReadInnerStatusLow();
-    s.INNER.STATUS |= ((uint16_t)flash_ReadInnerStatusHigh()) << 8;
-    s.INNER.STATUS_b.BP = init->FLASH_ProtectRegion;
-    s.INNER.STATUS_b.SRP = init->FLASH_ProtectMode;
-    s.INNER.STATUS_b.QE = init->FLASH_QuadEnable;
-
-    flash_WriteWriteEnable(TRUE);
-    flash_WriteStatusReg(&s);
+	flash_WriteWriteEnable(TRUE);
+	flash_WriteStatusReg(&s);
 }
 
 void FLASH_GetStatus(uint8_t* ProtectMode, uint8_t* ProtectRegion, BOOL* QuadEnable) {
-    FLASH_INNER_STATUS s;
-
-    assert_param(ProtectMode);
-    assert_param(ProtectRegion);
-    assert_param(QuadEnable);
-
-    flash_WaitInWritting();
-
-    s.INNER.STATUS = flash_ReadInnerStatusLow();
-    s.INNER.STATUS |= ((uint16_t)flash_ReadInnerStatusHigh()) << 8;
-    *ProtectRegion = s.INNER.STATUS_b.BP;
-    *ProtectMode = s.INNER.STATUS_b.SRP;
-    *QuadEnable = (s.INNER.STATUS_b.QE == 1) ?  TRUE : FALSE;
+	FLASH_INNER_STATUS s;
+	
+	assert_param(ProtectMode);
+	assert_param(ProtectRegion);
+	assert_param(QuadEnable);
+	
+	flash_WaitInWritting();
+	
+	s.INNER.STATUS = flash_ReadInnerStatusLow();
+	s.INNER.STATUS |= ((uint16_t)flash_ReadInnerStatusHigh()) << 8;
+	*ProtectRegion = s.INNER.STATUS_b.BP;
+	*ProtectMode = s.INNER.STATUS_b.SRP;
+	*QuadEnable = (s.INNER.STATUS_b.QE == 1) ?  TRUE : FALSE;
 }
 
 void FLASH_EraseSector(uint32_t addr) {
-    flash_WaitInWritting();
-    flash_WriteWriteEnable(TRUE);
-
-    addr = (addr << 8) >> 8;
-    addr = addr / FLASH_SECTOR_SIZE * FLASH_SECTOR_SIZE;
-    flash_Erase(FLASH_CME_ERASE_SECTOR, addr);
+	flash_WaitInWritting();
+	flash_WriteWriteEnable(TRUE);
+	
+	addr = (addr << 8) >> 8;
+	addr = addr / FLASH_SECTOR_SIZE * FLASH_SECTOR_SIZE;
+	flash_Erase(FLASH_CME_ERASE_SECTOR, addr);
 }
 
 void FLASH_Erase32kBlock(uint32_t addr) {
-    flash_WaitInWritting();
-    flash_WriteWriteEnable(TRUE);
-
-    addr = (addr << 8) >> 8;
-    addr = addr / FLASH_BLOCK_32K_SIZE * FLASH_BLOCK_32K_SIZE;
-    flash_Erase(FLASH_CME_ERASE_BLOCK_32K, addr);
+	flash_WaitInWritting();
+	flash_WriteWriteEnable(TRUE);
+	
+	addr = (addr << 8) >> 8;
+	addr = addr / FLASH_BLOCK_32K_SIZE * FLASH_BLOCK_32K_SIZE;
+	flash_Erase(FLASH_CME_ERASE_BLOCK_32K, addr);
 }
 
 void FLASH_Erase64kBlock(uint32_t addr) {
-    flash_WaitInWritting();
-    flash_WriteWriteEnable(TRUE);
-
-    addr = (addr << 8) >> 8;
-    addr = addr / FLASH_BLOCK_64K_SIZE * FLASH_BLOCK_64K_SIZE;
-    flash_Erase(FLASH_CME_ERASE_BLOCK_64K, addr);
+	flash_WaitInWritting();
+	flash_WriteWriteEnable(TRUE);
+	
+	addr = (addr << 8) >> 8;
+	addr = addr / FLASH_BLOCK_64K_SIZE * FLASH_BLOCK_64K_SIZE;
+	flash_Erase(FLASH_CME_ERASE_BLOCK_64K, addr);
 }
 
 void FLASH_EraseChip(void) {
-    flash_WaitInWritting();
-    flash_WriteWriteEnable(TRUE);
-    flash_Erase(FLASH_CME_ERASE_CHIP, 0x0);
+	flash_WaitInWritting();
+	flash_WriteWriteEnable(TRUE);
+	flash_Erase(FLASH_CME_ERASE_CHIP, 0x0);
 }
 
 void FLASH_EnableDeepPowerDown(BOOL enable) {
-    flash_WaitInWritting();
-    flash_WriteWriteEnable(TRUE);
-    flash_WriteDeepPowerDownEnable(enable);
+	flash_WaitInWritting();
+	flash_WriteWriteEnable(TRUE);
+	flash_WriteDeepPowerDownEnable(enable);
 }
 
 void FLASH_Read(uint8_t ReadMode, uint32_t addr, uint16_t size, uint8_t* data) {
-    uint8_t cmd;
-
-    assert_param(IS_FLASH_READ_MODE(ReadMode));
-    assert_param(addr + size <= FLASH_MAX_SIZE);
-    assert_param(data);
-
-    if (size == 0) {
-        return ;
-    }
-
-    flash_WaitInWritting();
-
-    if (ReadMode == FLASH_READ_MODE_NORMAL) {
-        cmd = FLASH_CME_RD_NORMAL;
-    } else if (ReadMode == FLASH_READ_MODE_FAST) {
-        cmd = FLASH_CME_RD_FAST;
-    } else if (ReadMode == FLASH_READ_MODE_FAST_DUAL) {
-        cmd = FLASH_CME_RD_FAST_DUAL;
-    } else {
-        cmd = FLASH_CME_RD_FAST_QUAD;
-    }
-
-    flash_RwReq(cmd, addr, size);
-
+	uint8_t cmd;
+	
+	assert_param(IS_FLASH_READ_MODE(ReadMode));
+	assert_param(addr + size <= FLASH_MAX_SIZE);
+	assert_param(data);
+	
+	if (size == 0) {
+		return ;
+	}
+	
+	flash_WaitInWritting();
+	
+	if (ReadMode == FLASH_READ_MODE_NORMAL) {
+		cmd = FLASH_CME_RD_NORMAL;
+	} else if (ReadMode == FLASH_READ_MODE_FAST) {
+		cmd = FLASH_CME_RD_FAST;
+	} else if (ReadMode == FLASH_READ_MODE_FAST_DUAL) {
+		cmd = FLASH_CME_RD_FAST_DUAL;
+	} else {
+		cmd = FLASH_CME_RD_FAST_QUAD;
+	}
+	
+	flash_RwReq(cmd, addr, size);
+	
   while (size > 0) {
-        uint16_t count = 0;
-
+		uint16_t count = 0;
+		
     flash_WaitReadFifoNotEmpty();
-
-      count = flash_ReadFifo(size, data);
-        size -= count;
-        data += count;
-    }
+	
+	  count = flash_ReadFifo(size, data);
+		size -= count;
+		data += count;
+	}
 }
 
 void FLASH_Write(uint32_t addr, uint16_t size, uint8_t* data) {
-    assert_param(addr + size <= FLASH_MAX_SIZE);
-    assert_param(data);
+	assert_param(addr + size <= FLASH_MAX_SIZE);
+	assert_param(data);
+	
+	flash_WaitInWritting();
+	
+	while (size > 0) {
+	  uint16_t count = flash_WritePage(addr, size, data);
 
-    flash_WaitInWritting();
-
-    while (size > 0) {
-      uint16_t count = flash_WritePage(addr, size, data);
-
-        addr += count;
-        size -= count;
-        data += count;
-    }
+		addr += count;
+		size -= count;
+		data += count;
+	}
 }
 

bsp/CME_M7/StdPeriph_Driver/src/cmem7_gpio.c

@@ -1,204 +1,204 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_gpio.c
-    *
-    * @brief    CMEM7 GPIO source file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_gpio.c
+	*
+	* @brief    CMEM7 GPIO source file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #include "cmem7_gpio.h"
 
-#define GPIO_GROUP_GPIO_H                   (GPIO_GROUP_GPIO + 1)
-#define GPIO_GROUP_GPIO_N                   (GPIO_GROUP_GPIO + 2)
+#define GPIO_GROUP_GPIO_H 					(GPIO_GROUP_GPIO + 1)
+#define GPIO_GROUP_GPIO_N 					(GPIO_GROUP_GPIO + 2)
 
 #define IS_INNER_GPIO_GROUP(GROUP)  (((GROUP) == GPIO_GROUP_GPIO) || \
-                                                                            ((GROUP) == GPIO_GROUP_GPIO_H) || \
-                                                                            ((GROUP) == GPIO_GROUP_GPIO_N))
-
-#define GPIO_PWM_CHANNEL_GPIO_H_9   (GPIO_PWM_CHANNEL_GPIO_31 + 1)
-#define GPIO_PWM_CHANNEL_GPIO_H_19  (GPIO_PWM_CHANNEL_GPIO_31 + 2)
-#define GPIO_PWM_CHANNEL_GPIO_H_20  (GPIO_PWM_CHANNEL_GPIO_31 + 3)
+																			((GROUP) == GPIO_GROUP_GPIO_H) || \
+																			((GROUP) == GPIO_GROUP_GPIO_N))
 
+#define GPIO_PWM_CHANNEL_GPIO_H_9 	(GPIO_PWM_CHANNEL_GPIO_31 + 1)
+#define GPIO_PWM_CHANNEL_GPIO_H_19 	(GPIO_PWM_CHANNEL_GPIO_31 + 2)
+#define GPIO_PWM_CHANNEL_GPIO_H_20 	(GPIO_PWM_CHANNEL_GPIO_31 + 3)
+        
 #define IS_INNER_GPIO_PWM_CHANNEL(CHANNEL)  (((CHANNEL) == GPIO_PWM_CHANNEL_GPIO_31) || \
                                        ((CHANNEL) == GPIO_PWM_CHANNEL_GPIO_H_9) || \
                                        ((CHANNEL) == GPIO_PWM_CHANNEL_GPIO_H_19) || \
                                        ((CHANNEL) == GPIO_PWM_CHANNEL_GPIO_H_20))
 static uint32_t gpio_GetClock() {
-    return SYSTEM_CLOCK_FREQ / (1 << (GLOBAL_CTRL->CLK_SEL_0_b.GPIO_CLK + 1));
+	return SYSTEM_CLOCK_FREQ / (1 << (GLOBAL_CTRL->CLK_SEL_0_b.GPIO_CLK + 1));
 }
 
 void GPIO_Init(uint8_t Group, uint32_t PositiveTrigger) {
-    assert_param(IS_GPIO_GROUP(Group));
-
-    if (Group == GPIO_GROUP_GPIO) {
-      GPIO->GPIO_POSITIVE_EDGE_INT_TRIGGER = PositiveTrigger;
-    } else if (Group == GPIO_GROUP_GPIO_H) {
-        GPIO->GPIO_H_POSITIVE_EDGE_INT_TRIGGER = PositiveTrigger;
-    } else {
-        GPIO->GPIO_N_POSITIVE_EDGE_INT_TRIGGER = PositiveTrigger;
-    }
+	assert_param(IS_GPIO_GROUP(Group));
+	
+	if (Group == GPIO_GROUP_GPIO) {
+	  GPIO->GPIO_POSITIVE_EDGE_INT_TRIGGER = PositiveTrigger;
+	} else if (Group == GPIO_GROUP_GPIO_H) {
+		GPIO->GPIO_H_POSITIVE_EDGE_INT_TRIGGER = PositiveTrigger;
+	} else {
+		GPIO->GPIO_N_POSITIVE_EDGE_INT_TRIGGER = PositiveTrigger;
+	}
 }
 
 void GPIO_EnableOutput(uint8_t Group, uint32_t Enable) {
-    assert_param(IS_GPIO_GROUP(Group));
-
-    if (Group == GPIO_GROUP_GPIO) {
-      GPIO->GPIO_OE = Enable;
-    } else if (Group == GPIO_GROUP_GPIO_H) {
-        GPIO->GPIO_H_OE = Enable;
-    } else {
-        GPIO->GPIO_N_OE = Enable;
-    }
+	assert_param(IS_GPIO_GROUP(Group));
+	
+	if (Group == GPIO_GROUP_GPIO) {
+	  GPIO->GPIO_OE = Enable;
+	} else if (Group == GPIO_GROUP_GPIO_H) {
+		GPIO->GPIO_H_OE = Enable;
+	} else {
+		GPIO->GPIO_N_OE = Enable;
+	}
 }
 
 void GPIO_EnableInt(uint8_t Group, uint32_t Enable) {
-    assert_param(IS_GPIO_GROUP(Group));
-
-    if (Group == GPIO_GROUP_GPIO) {
-      GPIO->GPIO_INT_MASK = ~Enable;
-    } else if (Group == GPIO_GROUP_GPIO_H) {
-        GPIO->GPIO_H_INT_MASK = ~Enable;
-    } else {
-        GPIO->GPIO_N_INT_MASK = ~Enable;
-    }
+	assert_param(IS_GPIO_GROUP(Group));
+	
+	if (Group == GPIO_GROUP_GPIO) {
+	  GPIO->GPIO_INT_MASK = ~Enable;
+	} else if (Group == GPIO_GROUP_GPIO_H) {
+		GPIO->GPIO_H_INT_MASK = ~Enable;
+	} else {
+		GPIO->GPIO_N_INT_MASK = ~Enable;
+	}
 }
 
 uint32_t GPIO_GetIntStatus(uint8_t Group) {
-    assert_param(IS_GPIO_GROUP(Group));
-
-    if (Group == GPIO_GROUP_GPIO) {
-      return GPIO->GPIO_INT_STATUS;
-    } else if (Group == GPIO_GROUP_GPIO_H) {
-        return GPIO->GPIO_H_INT_STATUS;
-    }
-
-    return GPIO->GPIO_N_INT_STATUS;
+	assert_param(IS_GPIO_GROUP(Group));
+	
+	if (Group == GPIO_GROUP_GPIO) {
+	  return GPIO->GPIO_INT_STATUS;
+	} else if (Group == GPIO_GROUP_GPIO_H) {
+		return GPIO->GPIO_H_INT_STATUS;
+	} 
+	
+	return GPIO->GPIO_N_INT_STATUS;
 }
 
 void GPIO_ClearInt(uint8_t Group, uint32_t Clear) {
-    assert_param(IS_GPIO_GROUP(Group));
-
-    if (Group == GPIO_GROUP_GPIO) {
-      GPIO->GPIO_INT_STATUS = Clear;
-    } else if (Group == GPIO_GROUP_GPIO_H) {
-        GPIO->GPIO_H_INT_STATUS = Clear;
-    } else {
-        GPIO->GPIO_N_INT_STATUS = Clear;
-    }
+	assert_param(IS_GPIO_GROUP(Group));
+	
+	if (Group == GPIO_GROUP_GPIO) {
+	  GPIO->GPIO_INT_STATUS = Clear;
+	} else if (Group == GPIO_GROUP_GPIO_H) {
+		GPIO->GPIO_H_INT_STATUS = Clear;
+	} else {
+		GPIO->GPIO_N_INT_STATUS = Clear;
+	}
 }
 
 uint32_t GPIO_Read(uint8_t Group) {
   uint32_t data;
-
-    assert_param(IS_GPIO_GROUP(Group));
-
-    if (Group == GPIO_GROUP_GPIO) {
-      data = GPIO->GPIO_IN;
-    } else if (Group == GPIO_GROUP_GPIO_H) {
-        data = GPIO->GPIO_H_IN;
-    } else {
-        data = GPIO->GPIO_N_IN;
-    }
-
-    return data;
+	
+	assert_param(IS_GPIO_GROUP(Group));
+	
+	if (Group == GPIO_GROUP_GPIO) {
+	  data = GPIO->GPIO_IN;
+	} else if (Group == GPIO_GROUP_GPIO_H) {
+		data = GPIO->GPIO_H_IN;
+	} else {
+		data = GPIO->GPIO_N_IN;
+	}
+	
+	return data;
 }
 
 void GPIO_Write(uint8_t Group, uint32_t Unmask, uint32_t data) {
-    assert_param(IS_GPIO_GROUP(Group));
-
-    if (Group == GPIO_GROUP_GPIO) {
-        GPIO->GPIO_OUT_UNMASK = Unmask;
-      GPIO->GPIO_OUT_DATA = data;
-    } else if (Group == GPIO_GROUP_GPIO_H) {
-        GPIO->GPIO_H_OUT_UNMASK = Unmask;
-      GPIO->GPIO_H_OUT_DATA = data;
-    } else {
-        GPIO->GPIO_N_OUT_UNMASK = Unmask;
-      GPIO->GPIO_N_OUT_DATA = data;
-    }
+	assert_param(IS_GPIO_GROUP(Group));
+	
+	if (Group == GPIO_GROUP_GPIO) {
+		GPIO->GPIO_OUT_UNMASK = Unmask;
+	  GPIO->GPIO_OUT_DATA = data;
+	} else if (Group == GPIO_GROUP_GPIO_H) {
+		GPIO->GPIO_H_OUT_UNMASK = Unmask;
+	  GPIO->GPIO_H_OUT_DATA = data;
+	} else {
+		GPIO->GPIO_N_OUT_UNMASK = Unmask;
+	  GPIO->GPIO_N_OUT_DATA = data;
+	}
 }
 
 void GPIO_InitPwm(uint8_t Channel, uint32_t HighLevelNanoSecond, uint32_t LowLevelNanoSecond) {
-    uint16_t lowTick, highTick;
-
-    assert_param(IS_GPIO_PWM_CHANNEL(Channel));
-
-    lowTick = LowLevelNanoSecond * (gpio_GetClock() / 1000000) / 1000;
-    highTick = HighLevelNanoSecond * (gpio_GetClock() / 1000000) / 1000;
-    lowTick = (lowTick < 1) ? lowTick : lowTick - 1;
-    highTick = (highTick < 1) ? highTick : highTick - 1;
-
-    if (Channel == GPIO_PWM_CHANNEL_GPIO_31) {
-        GPIO->PWM_OUT0_LEN_b.LOW_LEVEL_TICK = lowTick;
-        GPIO->PWM_OUT0_LEN_b.HIGH_LEVEL_TICK = highTick;
-    } else if (Channel == GPIO_PWM_CHANNEL_GPIO_H_9) {
-        GPIO->PWM_OUT1_LEN_b.LOW_LEVEL_TICK = lowTick;
-        GPIO->PWM_OUT1_LEN_b.HIGH_LEVEL_TICK = highTick;
-    } else if (Channel == GPIO_PWM_CHANNEL_GPIO_H_19) {
-        GPIO->PWM_OUT2_LEN_b.LOW_LEVEL_TICK = lowTick;
-        GPIO->PWM_OUT2_LEN_b.HIGH_LEVEL_TICK = highTick;
+	uint16_t lowTick, highTick;
+	
+	assert_param(IS_GPIO_PWM_CHANNEL(Channel));
+	
+	lowTick = LowLevelNanoSecond * (gpio_GetClock() / 1000000) / 1000;
+	highTick = HighLevelNanoSecond * (gpio_GetClock() / 1000000) / 1000;
+	lowTick = (lowTick < 1) ? lowTick : lowTick - 1;
+	highTick = (highTick < 1) ? highTick : highTick - 1;
+	
+	if (Channel == GPIO_PWM_CHANNEL_GPIO_31) {
+		GPIO->PWM_OUT0_LEN_b.LOW_LEVEL_TICK = lowTick; 
+		GPIO->PWM_OUT0_LEN_b.HIGH_LEVEL_TICK = highTick; 
+	} else if (Channel == GPIO_PWM_CHANNEL_GPIO_H_9) {
+		GPIO->PWM_OUT1_LEN_b.LOW_LEVEL_TICK = lowTick; 
+		GPIO->PWM_OUT1_LEN_b.HIGH_LEVEL_TICK = highTick; 
+	} else if (Channel == GPIO_PWM_CHANNEL_GPIO_H_19) {
+		GPIO->PWM_OUT2_LEN_b.LOW_LEVEL_TICK = lowTick; 
+		GPIO->PWM_OUT2_LEN_b.HIGH_LEVEL_TICK = highTick; 
   } else {
-        GPIO->PWM_OUT3_LEN_b.LOW_LEVEL_TICK = lowTick;
-        GPIO->PWM_OUT3_LEN_b.HIGH_LEVEL_TICK = highTick;
-    }
+		GPIO->PWM_OUT3_LEN_b.LOW_LEVEL_TICK = lowTick; 
+		GPIO->PWM_OUT3_LEN_b.HIGH_LEVEL_TICK = highTick; 
+	}
 }
 
 void GPIO_EnablePwm(uint8_t Channel, BOOL Enable) {
-    assert_param(IS_GPIO_PWM_CHANNEL(Channel));
-
-    if (Channel == GPIO_PWM_CHANNEL_GPIO_31) {
-        GPIO->PWM_OUT_EN_b.GPIO_31 = Enable;
-        GPIO->PWM_OUT_SEL_b.GPIO_31 = Enable;
-    } else if (Channel == GPIO_PWM_CHANNEL_GPIO_H_9) {
-        GPIO->PWM_OUT_EN_b.GPIO_H_9 = Enable;
-        GPIO->PWM_OUT_SEL_b.GPIO_H_9 = Enable;
-    } else if (Channel == GPIO_PWM_CHANNEL_GPIO_H_19) {
-        GPIO->PWM_OUT_EN_b.GPIO_H_19 = Enable;
-    GPIO->PWM_OUT_SEL_b.GPIO_H_19 = Enable;
+	assert_param(IS_GPIO_PWM_CHANNEL(Channel));
+	
+	if (Channel == GPIO_PWM_CHANNEL_GPIO_31) {
+		GPIO->PWM_OUT_EN_b.GPIO_31 = Enable; 
+		GPIO->PWM_OUT_SEL_b.GPIO_31 = Enable; 
+	} else if (Channel == GPIO_PWM_CHANNEL_GPIO_H_9) {
+		GPIO->PWM_OUT_EN_b.GPIO_H_9 = Enable; 
+		GPIO->PWM_OUT_SEL_b.GPIO_H_9 = Enable;
+	} else if (Channel == GPIO_PWM_CHANNEL_GPIO_H_19) {
+		GPIO->PWM_OUT_EN_b.GPIO_H_19 = Enable;
+	GPIO->PWM_OUT_SEL_b.GPIO_H_19 = Enable;		
   } else {
-        GPIO->PWM_OUT_EN_b.GPIO_H_20 = Enable;
-        GPIO->PWM_OUT_SEL_b.GPIO_H_20 = Enable;
-    }
+		GPIO->PWM_OUT_EN_b.GPIO_H_20 = Enable; 
+		GPIO->PWM_OUT_SEL_b.GPIO_H_20 = Enable;
+	}
 }
 
 /**
    xjf 20150324
-
+   
 **/
 void GPIO_SetBits(uint32_t mask)
 {
   static uint32_t g_GPIO_OUT_UNMASK;
   static uint32_t g_GPIO_OUT_DATA;
   static uint32_t g_GPIO_OE;
-
-    g_GPIO_OUT_UNMASK = GPIO->GPIO_OUT_UNMASK ;
+	
+	g_GPIO_OUT_UNMASK = GPIO->GPIO_OUT_UNMASK ;
   g_GPIO_OUT_DATA   = GPIO->GPIO_OUT_DATA   ;
-    g_GPIO_OE         = GPIO->GPIO_OE ;
-  g_GPIO_OUT_UNMASK |=mask;
+	g_GPIO_OE         = GPIO->GPIO_OE ;
+  g_GPIO_OUT_UNMASK |=mask;  
   g_GPIO_OE         |=mask;
-    g_GPIO_OUT_DATA   |=mask;
-
-    GPIO->GPIO_OUT_UNMASK =g_GPIO_OUT_UNMASK ;
+	g_GPIO_OUT_DATA   |=mask;
+	
+	GPIO->GPIO_OUT_UNMASK =g_GPIO_OUT_UNMASK ;
   GPIO->GPIO_OUT_DATA   =g_GPIO_OUT_DATA ;
-    GPIO->GPIO_OE         =g_GPIO_OE       ;
+	GPIO->GPIO_OE         =g_GPIO_OE       ;
 }
 
 void GPIO_clrBits(uint32_t mask)
@@ -206,17 +206,17 @@ void GPIO_clrBits(uint32_t mask)
   static uint32_t g_GPIO_OUT_UNMASK;
   static uint32_t g_GPIO_OUT_DATA;
   static uint32_t g_GPIO_OE;
-
-    g_GPIO_OUT_UNMASK = GPIO->GPIO_OUT_UNMASK ;
+	
+	g_GPIO_OUT_UNMASK = GPIO->GPIO_OUT_UNMASK ;
   g_GPIO_OUT_DATA   = GPIO->GPIO_OUT_DATA   ;
-    g_GPIO_OE         = GPIO->GPIO_OE ;
-  g_GPIO_OUT_UNMASK |=mask;
+	g_GPIO_OE         = GPIO->GPIO_OE ;
+  g_GPIO_OUT_UNMASK |=mask;  
   g_GPIO_OE         |=mask;
-    g_GPIO_OUT_DATA   &=(~ mask);
-
-    GPIO->GPIO_OUT_UNMASK =g_GPIO_OUT_UNMASK ;
+	g_GPIO_OUT_DATA   &=(~ mask);
+	
+	GPIO->GPIO_OUT_UNMASK =g_GPIO_OUT_UNMASK ;
   GPIO->GPIO_OUT_DATA   =g_GPIO_OUT_DATA ;
-    GPIO->GPIO_OE         =g_GPIO_OE       ;
+	GPIO->GPIO_OE         =g_GPIO_OE       ;
 }
 
 uint32_t GPIO_getBits(uint32_t mask)
@@ -224,33 +224,33 @@ uint32_t GPIO_getBits(uint32_t mask)
   static uint32_t g_GPIO_OUT_UNMASK;
   //static uint32_t g_GPIO_OUT_DATA;
   static uint32_t g_GPIO_OE;
-
-    uint32_t  get_delay = 0;
-    uint32_t  saved_mask;
-
-    saved_mask=mask;
-
-    g_GPIO_OUT_UNMASK      = GPIO->GPIO_OUT_UNMASK ;
-    g_GPIO_OE              = GPIO->GPIO_OE ;
-  g_GPIO_OUT_UNMASK     &=(~mask);
+	
+	uint32_t  get_delay = 0;
+	uint32_t  saved_mask;
+	
+	saved_mask=mask;
+	
+	g_GPIO_OUT_UNMASK      = GPIO->GPIO_OUT_UNMASK ;
+	g_GPIO_OE              = GPIO->GPIO_OE ;
+  g_GPIO_OUT_UNMASK     &=(~mask);  
   g_GPIO_OE             &=(~mask);
-    GPIO->GPIO_OUT_UNMASK  =g_GPIO_OUT_UNMASK ;
-    GPIO->GPIO_OE          =g_GPIO_OE       ;
-    for(get_delay=0;get_delay<100;get_delay++)
-      {
+	GPIO->GPIO_OUT_UNMASK  =g_GPIO_OUT_UNMASK ;
+	GPIO->GPIO_OE          =g_GPIO_OE       ;
+	for(get_delay=0;get_delay<100;get_delay++)
+	  {
     }
-    //get_delay=(GPIO->GPIO_IN)&saved_mask;
-  if(((GPIO->GPIO_IN)&saved_mask)==saved_mask)
-       {
-             return(1);
-        }
-    else
-    {
-            return(0);
+	//get_delay=(GPIO->GPIO_IN)&saved_mask;
+  if(((GPIO->GPIO_IN)&saved_mask)==saved_mask)	
+	   {
+			 return(1);
+	    }		
+	else
+   	{
+			return(0);
     }
-
+	
 }
 /**
    xjf 20150324
-
+   
 **/

bsp/CME_M7/StdPeriph_Driver/src/cmem7_i2c.c

@@ -1,322 +1,321 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_i2c.c
-    *
-    * @brief    CMEM7 I2C source file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_i2c.c
+	*
+	* @brief    CMEM7 I2C source file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #include "cmem7_i2c.h"
 
-#define I2C_INNER_INT_ALL               0x3FF
+#define I2C_INNER_INT_ALL				0x3FF
 
 typedef struct {
-    union {
-    uint32_t  DATA_CMD;
-
+	union {
+    uint32_t  DATA_CMD;                                                           
+    
     struct {
-      uint32_t  DATA       :  8;
-      uint32_t  RD_CMD     :  1;
-      uint32_t  WR_CMD     :  1;
-      uint32_t  WR_RD_CMD  :  1;
-    } DATA_CMD_b;
+      uint32_t  DATA       :  8;                                                                   
+      uint32_t  RD_CMD     :  1;              
+      uint32_t  WR_CMD     :  1;                
+      uint32_t  WR_RD_CMD  :  1;               
+    } DATA_CMD_b;                                   
   } INNER;
 } I2C_INNER_DATA_CMD;
 
 static uint32_t i2c_GetClock(I2C0_Type* I2Cx) {
-    uint32_t dividor;
-    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+	uint32_t dividor;
 
-    if ((uint32_t)I2Cx == (uint32_t)I2C0) {
-        dividor = GLOBAL_CTRL->CLK_SEL_0_b.I2C0_CLK;
-    } else if ((uint32_t)I2Cx == (uint32_t)I2C1) {
-        dividor = GLOBAL_CTRL->CLK_SEL_0_b.I2C1_CLK;
-    }
-
-    return SYSTEM_CLOCK_FREQ / (1 << (dividor + 1));
+	if ((uint32_t)I2Cx == (uint32_t)I2C0) {
+		dividor = GLOBAL_CTRL->CLK_SEL_0_b.I2C0_CLK;
+	} else if ((uint32_t)I2Cx == (uint32_t)I2C1) {
+		dividor = GLOBAL_CTRL->CLK_SEL_0_b.I2C1_CLK;
+	} 
+	
+	return SYSTEM_CLOCK_FREQ / (1 << (dividor + 1));
 }
 
 static uint16_t i2c_NormalizeAddr(I2C0_Type* I2Cx, uint16_t addr) {
-    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
-    if (I2Cx->CTRL_b.MODE == I2C_Mode_Master) {
-        if (I2Cx->CTRL_b.MASTER_ADDR_WIDTH == I2C_ADDR_WIDTH_7BIT) {
-            addr &= 0x007F;
-        } else {
-            addr &= 0x3FF;
-        }
-    }
-
-    if (I2Cx->CTRL_b.MODE == I2C_Mode_Slave) {
-        if (I2Cx->CTRL_b.SLAVE_ADDR_WIDTH == I2C_ADDR_WIDTH_7BIT) {
-            addr &= 0x007F;
-        } else {
-            addr &= 0x3FF;
-        }
-    }
-
-    return addr;
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+	
+	if (I2Cx->CTRL_b.MODE == I2C_Mode_Master) {
+		if (I2Cx->CTRL_b.MASTER_ADDR_WIDTH == I2C_ADDR_WIDTH_7BIT) {
+			addr &= 0x007F;
+		} else {
+			addr &= 0x3FF;
+		}
+	}
+	
+	if (I2Cx->CTRL_b.MODE == I2C_Mode_Slave) {
+		if (I2Cx->CTRL_b.SLAVE_ADDR_WIDTH == I2C_ADDR_WIDTH_7BIT) {
+			addr &= 0x007F;
+		} else {
+			addr &= 0x3FF;
+		}
+	}
+	
+	return addr;
 }
 
 static void i2c_ReadClear(uint32_t bit) {
-    uint32_t tmp;
-    tmp = bit;
-    tmp = tmp;
+	uint32_t tmp;
+	tmp = bit;
+	tmp = tmp;	
 }
-
+		
 void I2C_Init(I2C0_Type* I2Cx, I2C_InitTypeDef* I2C_Init) {
-    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-    assert_param(I2C_Init);
-    assert_param(IS_I2C_MODE(I2C_Init->I2C_Mode));
-    assert_param(IS_I2C_ADDR_WIDTH(I2C_Init->I2C_AddressWidth));
-
-    // reset
-    I2Cx->ENABLE_b.RESET = FALSE;
-    I2Cx->ENABLE_b.RESET = TRUE;
-
-    // clear interrupt
-    I2Cx->INT_MASK = I2C_INNER_INT_ALL;
-    i2c_ReadClear(I2Cx->CLR_ALL_INT_b.CLEAR);
-
-    I2Cx->CTRL_b.MODE = I2C_Init->I2C_Mode;
-    if (I2Cx->CTRL_b.MODE == I2C_Mode_Master) {
-        I2Cx->CTRL_b.MASTER_ADDR_WIDTH = I2C_Init->I2C_AddressWidth;
-        I2Cx->TAR_b.START_BYTE = TRUE;
-        I2Cx->TAR_b.ADDR10 = i2c_NormalizeAddr(I2Cx, I2C_Init->I2C_Address);
-    }
-    if (I2Cx->CTRL_b.MODE == I2C_Mode_Slave) {
-        I2Cx->CTRL_b.SLAVE_ADDR_WIDTH = I2C_Init->I2C_AddressWidth;
-        I2Cx->SAR_b.ADDR10 = i2c_NormalizeAddr(I2Cx, I2C_Init->I2C_Address);
-    }
-
-    I2Cx->RX_TL_b.THRESHOLD = 0;
-    I2Cx->TX_TL_b.THRESHOLD = 0;
-
-    I2Cx->SLAVE_NACK_b.NACK = FALSE;
-
-    if (I2C_Init->timing) {
-        I2Cx->SCL_CNT_b.HIGH_LEVEL_TICK =
-          i2c_GetClock(I2Cx) / I2C_Init->timing->I2C_Freq / 2;
-        I2Cx->SCL_CNT_b.LOW_LEVEL_TICK =
-          i2c_GetClock(I2Cx) / I2C_Init->timing->I2C_Freq / 2;
-        I2Cx->SDA_SETUP_b.TSU_DAT = ((uint64_t)I2C_Init->timing->I2C_TsuDat) *
-          i2c_GetClock(I2Cx) / 1000000000;
-        I2Cx->SDA_SETUP_b.TSETUP = ((uint64_t)I2C_Init->timing->I2C_Tsetup) *
-          i2c_GetClock(I2Cx) / 1000000000;
-        I2Cx->TSU_STA_SETUP_b.TBUF = ((uint64_t)I2C_Init->timing->I2C_Tbuf) *
-          i2c_GetClock(I2Cx) / 1000000000;
-        I2Cx->TSU_STA_SETUP_b.TSU_STA = ((uint64_t)I2C_Init->timing->I2C_TsuSta) *
-          i2c_GetClock(I2Cx) / 1000000000;
-        I2Cx->TSU_STA_SETUP_b.SDA_FILTER_EN = I2C_Init->timing->I2C_SdaFilterEn;
-        I2Cx->TSU_STA_SETUP_b.SDA_FILTER_CNT = I2C_Init->timing->I2C_SdaFilterSpike;
-        I2Cx->TSU_STA_SETUP_b.SCL_FILTER_EN = I2C_Init->timing->I2C_SclFilterEn;
-        I2Cx->TSU_STA_SETUP_b.SCL_FILTER_CNT = I2C_Init->timing->I2C_SclFilterSpike;
+	assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+	assert_param(I2C_Init);
+	assert_param(IS_I2C_MODE(I2C_Init->I2C_Mode));
+	assert_param(IS_I2C_ADDR_WIDTH(I2C_Init->I2C_AddressWidth));
+	
+	// reset
+	I2Cx->ENABLE_b.RESET = FALSE;
+	I2Cx->ENABLE_b.RESET = TRUE;
+	
+	// clear interrupt
+	I2Cx->INT_MASK = I2C_INNER_INT_ALL;
+	i2c_ReadClear(I2Cx->CLR_ALL_INT_b.CLEAR);
+	
+	I2Cx->CTRL_b.MODE = I2C_Init->I2C_Mode;
+	if (I2Cx->CTRL_b.MODE == I2C_Mode_Master) {
+	  I2Cx->CTRL_b.MASTER_ADDR_WIDTH = I2C_Init->I2C_AddressWidth;
+		I2Cx->TAR_b.START_BYTE = TRUE;
+		I2Cx->TAR_b.ADDR10 = i2c_NormalizeAddr(I2Cx, I2C_Init->I2C_Address);
+	}
+	if (I2Cx->CTRL_b.MODE == I2C_Mode_Slave) {
+	  I2Cx->CTRL_b.SLAVE_ADDR_WIDTH = I2C_Init->I2C_AddressWidth;
+		I2Cx->SAR_b.ADDR10 = i2c_NormalizeAddr(I2Cx, I2C_Init->I2C_Address);
+	}
+	
+	I2Cx->RX_TL_b.THRESHOLD = 0;
+	I2Cx->TX_TL_b.THRESHOLD = 0;
+	
+	I2Cx->SLAVE_NACK_b.NACK = FALSE;
+	
+	if (I2C_Init->timing) {
+		I2Cx->SCL_CNT_b.HIGH_LEVEL_TICK = 
+		  i2c_GetClock(I2Cx) / I2C_Init->timing->I2C_Freq / 2;
+		I2Cx->SCL_CNT_b.LOW_LEVEL_TICK = 
+		  i2c_GetClock(I2Cx) / I2C_Init->timing->I2C_Freq / 2;
+	  I2Cx->SDA_SETUP_b.TSU_DAT = ((uint64_t)I2C_Init->timing->I2C_TsuDat) * 
+		  i2c_GetClock(I2Cx) / 1000000000;
+		I2Cx->SDA_SETUP_b.TSETUP = ((uint64_t)I2C_Init->timing->I2C_Tsetup) * 
+		  i2c_GetClock(I2Cx) / 1000000000;
+		I2Cx->TSU_STA_SETUP_b.TBUF = ((uint64_t)I2C_Init->timing->I2C_Tbuf) * 
+		  i2c_GetClock(I2Cx) / 1000000000;
+	  I2Cx->TSU_STA_SETUP_b.TSU_STA = ((uint64_t)I2C_Init->timing->I2C_TsuSta) * 
+		  i2c_GetClock(I2Cx) / 1000000000;
+		I2Cx->TSU_STA_SETUP_b.SDA_FILTER_EN = I2C_Init->timing->I2C_SdaFilterEn;
+		I2Cx->TSU_STA_SETUP_b.SDA_FILTER_CNT = I2C_Init->timing->I2C_SdaFilterSpike;
+		I2Cx->TSU_STA_SETUP_b.SCL_FILTER_EN = I2C_Init->timing->I2C_SclFilterEn;
+		I2Cx->TSU_STA_SETUP_b.SCL_FILTER_CNT = I2C_Init->timing->I2C_SclFilterSpike;
   }
 }
 
 void I2C_Enable(I2C0_Type* I2Cx, BOOL enable) {
-    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
-    I2Cx->ENABLE_b.EN = enable;
+	assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+	
+  I2Cx->ENABLE_b.EN = enable;
 }
 
 void I2C_EnableInt(I2C0_Type* I2Cx, uint32_t Int, BOOL enable) {
-    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-    assert_param(IS_I2C_INT(Int));
-
-    if (enable) {
-      I2Cx->INT_MASK &= ~Int;
-    } else {
-        I2Cx->INT_MASK |= Int;
-    }
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+	assert_param(IS_I2C_INT(Int));
+	
+  if (enable) {
+	  I2Cx->INT_MASK &= ~Int;
+	} else {
+		I2Cx->INT_MASK |= Int;
+	}
 }
 
 BOOL I2C_GetIntStatus(I2C0_Type* I2Cx, uint32_t Int) {
-    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-    assert_param(IS_I2C_INT(Int));
-
-    if (0 != (I2Cx->INT_STATUS & Int)) {
-        return TRUE;
-    }
-
-    return FALSE;
+	assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+	assert_param(IS_I2C_INT(Int));
+	
+	if (0 != (I2Cx->INT_STATUS & Int)) {
+		return TRUE;
+	}
+	
+	return FALSE;
 }
 void I2C_ClearInt(I2C0_Type* I2Cx, uint32_t Int) {
-    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-    assert_param(IS_I2C_INT(Int));
-
-    if (Int == I2C_INT_RX_FIFO_NOT_EMPTY) {
-        // It can't be clear by sw but read data
-    }
-
-    if (Int == I2C_INT_RD_REQUEST) {
-        i2c_ReadClear(I2Cx->CLR_RD_REQ_b.CLEAR);
-    }
-
-    if (Int == I2C_INT_TX_ABORT) {
-        i2c_ReadClear(I2Cx->CLR_TX_ABRT_b.CLEAR);
-    }
-
-    if (Int == I2C_INT_RX_DONE) {
-        i2c_ReadClear(I2Cx->CLR_RX_DONE_b.CLEAR);
-    }
-
-    if (Int == I2C_INT_TX_DONE) {
-        i2c_ReadClear(I2Cx->CLR_TX_DONE_b.CLEAR);
-    }
+	assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+	assert_param(IS_I2C_INT(Int));
+	
+	if (Int == I2C_INT_RX_FIFO_NOT_EMPTY) {
+		// It can't be clear by sw but read data
+	} 
+	
+	if (Int == I2C_INT_RD_REQUEST) {
+		i2c_ReadClear(I2Cx->CLR_RD_REQ_b.CLEAR);
+	} 
+	
+	if (Int == I2C_INT_TX_ABORT) {
+		i2c_ReadClear(I2Cx->CLR_TX_ABRT_b.CLEAR);
+	} 
+	
+	if (Int == I2C_INT_RX_DONE) {
+		i2c_ReadClear(I2Cx->CLR_RX_DONE_b.CLEAR);
+	} 
+	
+	if (Int == I2C_INT_TX_DONE) {
+		i2c_ReadClear(I2Cx->CLR_TX_DONE_b.CLEAR);
+	} 
 }
 
 BOOL I2C_GetStatus(I2C0_Type* I2Cx, uint32_t Status) {
-    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-    assert_param(IS_I2C_STATUS(Status));
-
-    if (0 != (I2Cx->STATUS & Status)) {
-        return TRUE;
-    }
-
-    return FALSE;
+	assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+	assert_param(IS_I2C_STATUS(Status));
+	
+	if (0 != (I2Cx->STATUS & Status)) {
+		return TRUE;
+	}
+	
+	return FALSE;
 }
 
 void I2C_ClearStatus(I2C0_Type* I2Cx, uint32_t Status) {
-    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-    assert_param(IS_I2C_STATUS(Status));
-
-    if (Status & I2C_STATUS_RX_FIFO_NOT_EMPTY) {
-        // It can't be clear by sw but read
-    }
-
-    if (Status & I2C_STATUS_RD_REQUEST) {
-        i2c_ReadClear(I2Cx->CLR_RD_REQ_b.CLEAR);
-    }
-
-    if (Status & I2C_STATUS_TX_ABORT) {
-        i2c_ReadClear(I2Cx->CLR_TX_ABRT_b.CLEAR);
-    }
-
-    if (Status & I2C_STATUS_RX_DONE) {
-        i2c_ReadClear(I2Cx->CLR_RX_DONE_b.CLEAR);
-    }
-
-    if (Status & I2C_STATUS_TX_DONE) {
-        i2c_ReadClear(I2Cx->CLR_TX_DONE_b.CLEAR);
-    }
+	assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+	assert_param(IS_I2C_STATUS(Status));
+	
+	if (Status & I2C_STATUS_RX_FIFO_NOT_EMPTY) {
+		// It can't be clear by sw but read
+	} 
+	
+	if (Status & I2C_STATUS_RD_REQUEST) {
+		i2c_ReadClear(I2Cx->CLR_RD_REQ_b.CLEAR);
+	} 
+	
+	if (Status & I2C_STATUS_TX_ABORT) {
+		i2c_ReadClear(I2Cx->CLR_TX_ABRT_b.CLEAR);
+	} 
+	
+	if (Status & I2C_STATUS_RX_DONE) {
+		i2c_ReadClear(I2Cx->CLR_RX_DONE_b.CLEAR);
+	} 
+	
+	if (Status & I2C_STATUS_TX_DONE) {
+		i2c_ReadClear(I2Cx->CLR_TX_DONE_b.CLEAR);
+	} 
 }
 
 BOOL I2C_MasterReadReq(I2C0_Type* I2Cx, uint8_t size) {
-    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+	assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+	
+	if (!I2Cx->ENABLE_b.EN || I2Cx->STATUS_b.BUSY) {
+		return FALSE;
+	}
 
-    if (!I2Cx->ENABLE_b.EN || I2Cx->STATUS_b.BUSY) {
-        return FALSE;
-    }
-
-    if (I2Cx->CTRL_b.MODE == I2C_Mode_Slave) {
-      return FALSE;
-    }
-
-    if (size == 0) {
-        return FALSE;
-    }
-
-    I2Cx->WRITE_READ_CNT_b.RD_BYTE_CNT = size;
-    if (size != 0) {
+	if (I2Cx->CTRL_b.MODE == I2C_Mode_Slave) {
+	  return FALSE;
+	}
+	
+	if (size == 0) {
+		return FALSE;
+	}
+	
+	I2Cx->WRITE_READ_CNT_b.RD_BYTE_CNT = size;
+	if (size != 0) {
     I2C_INNER_DATA_CMD inner;
-
+    
     inner.INNER.DATA_CMD_b.DATA = 0;
-        inner.INNER.DATA_CMD_b.RD_CMD = TRUE;
-        inner.INNER.DATA_CMD_b.WR_CMD = FALSE;
-        inner.INNER.DATA_CMD_b.WR_RD_CMD = FALSE;
-
-        I2Cx->DATA_CMD = inner.INNER.DATA_CMD;
-    }
-
-    return TRUE;
+		inner.INNER.DATA_CMD_b.RD_CMD = TRUE;
+		inner.INNER.DATA_CMD_b.WR_CMD = FALSE;
+		inner.INNER.DATA_CMD_b.WR_RD_CMD = FALSE;
+		
+		I2Cx->DATA_CMD = inner.INNER.DATA_CMD;
+	}
+	
+	return TRUE;
 }
 
 uint8_t I2C_ReadFifo(I2C0_Type* I2Cx, uint8_t size, uint8_t* data) {
-    uint8_t count;
-
-    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-    assert_param(data);
-
-    if (!I2Cx->ENABLE_b.EN) {
-        return 0;
-    }
-
-    count = 0;
-    while (I2Cx->STATUS_b.RX_FIFO_NOT_EMPTY && count < size) {
-        *(data + count++) = I2Cx->DATA_CMD_b.DATA;
-    }
-
-    return count;
+	uint8_t count;
+	
+	assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+	assert_param(data);
+	
+	if (!I2Cx->ENABLE_b.EN) {
+		return 0;
+	}
+	
+	count = 0;
+	while (I2Cx->STATUS_b.RX_FIFO_NOT_EMPTY && count < size) {
+		*(data + count++) = I2Cx->DATA_CMD_b.DATA;
+	}
+	
+	return count;
 }
 
 BOOL I2C_WriteReq(I2C0_Type* I2Cx, uint8_t size, uint8_t firstData) {
-    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
-    if (!I2Cx->ENABLE_b.EN || I2Cx->STATUS_b.BUSY) {
-        return FALSE;
-    }
-
-    if (size == 0) {
-        return FALSE;
-    }
-
-    I2Cx->WRITE_READ_CNT_b.WR_BYTE_CNT = size;
-    if (size != 0) {
+	assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+	
+	if (!I2Cx->ENABLE_b.EN || I2Cx->STATUS_b.BUSY) {
+		return FALSE;
+	}
+	
+	if (size == 0) {
+		return FALSE;
+	}
+	
+	I2Cx->WRITE_READ_CNT_b.WR_BYTE_CNT = size;
+	if (size != 0) {
     I2C_INNER_DATA_CMD inner;
+    
+    inner.INNER.DATA_CMD_b.DATA = firstData	;
+		inner.INNER.DATA_CMD_b.RD_CMD = FALSE;
+		inner.INNER.DATA_CMD_b.WR_CMD = 
+		  (I2Cx->CTRL_b.MODE == I2C_Mode_Slave) ? FALSE : TRUE;
+		inner.INNER.DATA_CMD_b.WR_RD_CMD = FALSE;
 
-    inner.INNER.DATA_CMD_b.DATA = firstData ;
-        inner.INNER.DATA_CMD_b.RD_CMD = FALSE;
-        inner.INNER.DATA_CMD_b.WR_CMD =
-          (I2Cx->CTRL_b.MODE == I2C_Mode_Slave) ? FALSE : TRUE;
-        inner.INNER.DATA_CMD_b.WR_RD_CMD = FALSE;
+		I2Cx->DATA_CMD = inner.INNER.DATA_CMD;
+	}
 
-        I2Cx->DATA_CMD = inner.INNER.DATA_CMD;
-    }
-
-    return TRUE;
+	return TRUE;
 }
 
 uint8_t I2C_WriteFifo(I2C0_Type* I2Cx, uint8_t size, uint8_t* data) {
-    uint8_t count;
+	uint8_t count;
+	
+	assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+	assert_param(data);
+	
+	if (!I2Cx->ENABLE_b.EN) {
+		return 0;
+	}
 
-    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-    assert_param(data);
-
-    if (!I2Cx->ENABLE_b.EN) {
-        return 0;
-    }
-
-    count = 0;
-    while (I2Cx->STATUS_b.TX_FIFO_NOT_FULL && count < size) {
-      I2Cx->DATA_CMD_b.DATA = *(data + count++);
-    }
-
-    return count;
+	count = 0;
+	while (I2Cx->STATUS_b.TX_FIFO_NOT_FULL && count < size) {
+	  I2Cx->DATA_CMD_b.DATA = *(data + count++);
+	}
+	
+	return count;	
 }
 
 BOOL I2C_StopReq(I2C0_Type* I2Cx) {
-    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
-    udelay(600);
-
-    return TRUE;
+	assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+	
+	udelay(600);
+	
+	return TRUE;
 }

bsp/CME_M7/StdPeriph_Driver/src/cmem7_misc.c

@@ -1,28 +1,28 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_misc.c
-    *
-    * @brief    CMEM7 miscellaneous file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
+	*****************************************************************************
+	* @file     cmem7_misc.c
+	*
+	* @brief    CMEM7 miscellaneous file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
 
 #include "cmem7_misc.h"
 
@@ -32,7 +32,7 @@ void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
 {
   /* Check the parameters */
   assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
-
+  
   /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
   SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
 }
@@ -40,14 +40,14 @@ void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
 void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
 {
   uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
-
+  
   /* Check the parameters */
-  assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));  
   assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
-
+    
   if (NVIC_InitStruct->NVIC_IRQChannelCmd != FALSE)
   {
-    /* Compute the Corresponding IRQ Priority --------------------------------*/
+    /* Compute the Corresponding IRQ Priority --------------------------------*/    
     tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
     tmppre = (0x4 - tmppriority);
     tmpsub = tmpsub >> tmppriority;
@@ -55,9 +55,9 @@ void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
     tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
     tmppriority |=  NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
     tmppriority = tmppriority << 0x04;
-
+        
     NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
-
+    
     /* Enable the Selected IRQ Channels --------------------------------------*/
     NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
       (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
@@ -71,11 +71,11 @@ void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
 }
 
 void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
-{
+{ 
   /* Check the parameters */
   assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
-  assert_param(IS_NVIC_OFFSET(Offset));
-
+  assert_param(IS_NVIC_OFFSET(Offset));  
+   
   SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
 }
 
@@ -83,20 +83,20 @@ void NVIC_SystemLPConfig(uint8_t LowPowerMode, BOOL NewState)
 {
   /* Check the parameters */
   assert_param(IS_NVIC_LP(LowPowerMode));
-
+  
   if (!NewState)
   {
     SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
   } else {
-        SCB->SCR |= LowPowerMode;
-    }
+		SCB->SCR |= LowPowerMode;
+	}
 }
 
 #define DEF_IBUS_OFFSET     0x1FFE0000
 #define DEF_EXT_ADDR        0x08020000
 static BOOL isMappingOn() {
   /* If default values aren't changed */
-  if ((GLOBAL_CTRL->IBUSOFF == DEF_IBUS_OFFSET) &&
+  if ((GLOBAL_CTRL->IBUSOFF == DEF_IBUS_OFFSET) && 
     (GLOBAL_CTRL->EXTADDR == DEF_EXT_ADDR)) {
     return FALSE;
   }
@@ -105,15 +105,15 @@ static BOOL isMappingOn() {
 }
 
 void GLB_MMAP(uint32_t from, uint32_t to, BOOL isIcacheOn) {
-    volatile int n;
-
-    GLOBAL_CTRL->IBUSOFF = GLOBAL_CTRL->DBUSOFF = (from - to);
-    GLOBAL_CTRL->EXTADDR = to;
-
-    // Delay several cycles
-    for (n = 0; n < 100; n++);
-    GLOBAL_CTRL->ICACHE_b.EN = isIcacheOn;
-    for (n = 0; n < 100; n++);
+	volatile int n;
+	
+	GLOBAL_CTRL->IBUSOFF = GLOBAL_CTRL->DBUSOFF = (from - to);
+	GLOBAL_CTRL->EXTADDR = to;
+	
+	// Delay several cycles 
+	for (n = 0; n < 100; n++);
+	GLOBAL_CTRL->ICACHE_b.EN = isIcacheOn;
+	for (n = 0; n < 100; n++);
 }
 
 /*
@@ -128,11 +128,11 @@ uint32_t GLB_ConvertToMappingFromAddr(uint32_t to) {
   if (!isMappingOn()) {
     return to;
   }
-
+  
   if ((to > MAPPING_TO_REGION_END) || (to < GLOBAL_CTRL->EXTADDR)) {
     return to;
   }
-
+  
   return (to + GLOBAL_CTRL->IBUSOFF);
 }
 
@@ -140,44 +140,44 @@ uint32_t GLB_ConvertToMappingToAddr(uint32_t from) {
   if (!isMappingOn()) {
     return from;
   }
-
+  
   if (from < MAPPING_FROM_REGION_START) {
     return from;
   }
-
+  
   return (from - GLOBAL_CTRL->IBUSOFF);
 }
 
 void GLB_SetNmiIrqNum(uint32_t irq) {
-    GLOBAL_CTRL->NMI_SEL_b.NMI = irq;
+	GLOBAL_CTRL->NMI_SEL_b.NMI = irq;
 }
 
 void GLB_SelectSysClkSource(uint8_t source) {
-    switch (source) {
-    case SYS_CLK_SEL_DLL :
-        // M7's DLL clock should be fixed at PLL loation 2
-        // In constrast, it's C2R1.
-        // Wait DLL clock stable
-        while (PDLOCK->GCLK_b.C2R1D == 0) ;
-        GLOBAL_CTRL->CLK_SEL_1_b.SYS_CLK = SYS_CLK_SEL_DLL;
-        break;
-    case SYS_CLK_SEL_CRYSTAL :
-        GLOBAL_CTRL->CLK_SEL_1_b.SYS_CLK = SYS_CLK_SEL_CRYSTAL;
-        break;
-    case SYS_CLK_SEL_EXTERNAL :
-        // TODO, Add the condition that makes sure input
-        // external clock is stable
-        // For example :
-        //  PLL location 0
-        //  while (PDLOCK->GCLK_b.C1R1P == 0) ;
-        //  DLL location 0
-        //  while (PDLOCK->GCLK_b.C1R1D == 0) ;
-        GLOBAL_CTRL->CLK_SEL_1_b.SYS_CLK = SYS_CLK_SEL_EXTERNAL;
-        break;
-    case SYS_CLK_SEL_OSC :
-        // Fall through
-    default :
-        GLOBAL_CTRL->CLK_SEL_1_b.SYS_CLK = SYS_CLK_SEL_OSC;
-        break;
-    }
+	switch (source) {
+	case SYS_CLK_SEL_DLL :
+		// M7's DLL clock should be fixed at PLL loation 2
+		// In constrast, it's C2R1.
+		// Wait DLL clock stable
+		while (PDLOCK->GCLK_b.C2R1D == 0) ;
+		GLOBAL_CTRL->CLK_SEL_1_b.SYS_CLK = SYS_CLK_SEL_DLL;
+		break;
+	case SYS_CLK_SEL_CRYSTAL :
+		GLOBAL_CTRL->CLK_SEL_1_b.SYS_CLK = SYS_CLK_SEL_CRYSTAL;
+		break;
+	case SYS_CLK_SEL_EXTERNAL :
+		// TODO, Add the condition that makes sure input
+		// external clock is stable
+		// For example :
+		//	PLL location 0
+		// 	while (PDLOCK->GCLK_b.C1R1P == 0) ;
+		// 	DLL location 0
+		// 	while (PDLOCK->GCLK_b.C1R1D == 0) ;
+		GLOBAL_CTRL->CLK_SEL_1_b.SYS_CLK = SYS_CLK_SEL_EXTERNAL;
+		break;
+	case SYS_CLK_SEL_OSC :
+		// Fall through
+	default :
+		GLOBAL_CTRL->CLK_SEL_1_b.SYS_CLK = SYS_CLK_SEL_OSC;
+		break;		
+	}
 }

bsp/CME_M7/StdPeriph_Driver/src/cmem7_rtc.c

@@ -1,63 +1,63 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_rtc.c
-    *
-    * @brief    CMEM7 RTC source file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_rtc.c
+	*
+	* @brief    CMEM7 RTC source file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #include "cmem7_rtc.h"
 
 #define SECONDS_IN_A_DAY                (86400)
 
 void RTC_ITConfig(uint32_t Int, BOOL Enable) {
-    assert_param(IS_RTC_INT(Int));
-
-    if (Enable) {
-      GLOBAL_CTRL->RTC_INT_EN |= Int;
-    } else {
-        GLOBAL_CTRL->RTC_INT_EN &= ~Int;
-    }
+	assert_param(IS_RTC_INT(Int));  
+	
+	if (Enable) {
+	  GLOBAL_CTRL->RTC_INT_EN |= Int;
+	} else {
+		GLOBAL_CTRL->RTC_INT_EN &= ~Int;
+	}
 }
 
 BOOL RTC_GetITStatus(uint32_t Int) {
-    assert_param(IS_RTC_INT(Int));
-
-    if (0 != (RTC->INT_STATUS & Int)) {
-        return TRUE;
-    }
-
-    return FALSE;
+	assert_param(IS_RTC_INT(Int)); 
+	
+	if (0 != (RTC->INT_STATUS & Int)) {
+		return TRUE;
+	}
+	
+	return FALSE;
 }
 
 void RTC_ClearITPendingBit(uint32_t Int) {
-  assert_param(IS_RTC_INT(Int));
-
-    RTC->INT_STATUS = Int;
+  assert_param(IS_RTC_INT(Int));  
+	
+	RTC->INT_STATUS = Int;
 }
 
 uint32_t RTC_GetSecond() {
-    return RTC->SECOND;
+	return RTC->SECOND;
 }
 
 uint16_t RTC_GetMillSecond() {
-    return RTC->MILLSECOND_b.MS;
+	return RTC->MILLSECOND_b.MS;
 }

bsp/CME_M7/StdPeriph_Driver/src/cmem7_spi.c

@@ -1,145 +1,145 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_spi.c
-    *
-    * @brief    CMEM7 SPI source file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_spi.c
+	*
+	* @brief    CMEM7 SPI source file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #include "cmem7_spi.h"
 
 void SPI_Init(SPI0_Type* SPIx, SPI_InitTypeDef *init) {
-    assert_param(IS_SPI_ALL_PERIPH(SPIx));
-    assert_param(init);
-    assert_param(IS_SPI_MODE(init->SPI_Mode));
-    assert_param(init->SPI_BitLength != 0);
-
-    if (init->SPI_Mode == SPI_MODE_CPOL_0_CPHA_0) {
-        SPIx->CTRL_b.CLK_HIGH = FALSE;
-        SPIx->CTRL_b.NEG_EDGE = TRUE;
+	assert_param(IS_SPI_ALL_PERIPH(SPIx));
+	assert_param(init);
+	assert_param(IS_SPI_MODE(init->SPI_Mode));
+	assert_param(init->SPI_BitLength != 0);
+	
+	if (init->SPI_Mode == SPI_MODE_CPOL_0_CPHA_0) {
+		SPIx->CTRL_b.CLK_HIGH = FALSE;
+		SPIx->CTRL_b.NEG_EDGE = TRUE;
   } else if (init->SPI_Mode == SPI_MODE_CPOL_0_CPHA_1) {
-        SPIx->CTRL_b.CLK_HIGH = FALSE;
-        SPIx->CTRL_b.NEG_EDGE = FALSE;
+		SPIx->CTRL_b.CLK_HIGH = FALSE;
+		SPIx->CTRL_b.NEG_EDGE = FALSE;
   } else if (init->SPI_Mode == SPI_MODE_CPOL_1_CPHA_0) {
-        SPIx->CTRL_b.CLK_HIGH = TRUE;
-        SPIx->CTRL_b.NEG_EDGE = FALSE;
+		SPIx->CTRL_b.CLK_HIGH = TRUE;
+		SPIx->CTRL_b.NEG_EDGE = FALSE;
   } else {
-        SPIx->CTRL_b.CLK_HIGH = TRUE;
-        SPIx->CTRL_b.NEG_EDGE = TRUE;
-  }
+		SPIx->CTRL_b.CLK_HIGH = TRUE;
+		SPIx->CTRL_b.NEG_EDGE = TRUE;
+  } 		
 
-    SPIx->CTRL_b.RX_EN = init->SPI_RxEn;
-    SPIx->BCNT_b.CNT = init->SPI_BitLength - 1;
-    SPIx->DIV = init->SPI_ClockDividor;
-    SPIx->GAP = (init->SPI_Gap == 0) ? 0 : init->SPI_Gap / 2 + 1;
+	SPIx->CTRL_b.RX_EN = init->SPI_RxEn;
+	SPIx->BCNT_b.CNT = init->SPI_BitLength - 1;
+	SPIx->DIV = init->SPI_ClockDividor;
+	SPIx->GAP = (init->SPI_Gap == 0) ? 0 : init->SPI_Gap / 2 + 1;
 }
 
 void SPI_Enable(SPI0_Type* SPIx, BOOL enable) {
-    assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
+	assert_param(IS_SPI_ALL_PERIPH(SPIx));
+	
   SPIx->CTRL_b.EN = enable;
 }
 
 void SPI_EnableInt(SPI0_Type* SPIx, uint32_t Int, BOOL enable) {
   assert_param(IS_SPI_ALL_PERIPH(SPIx));
-    assert_param(IS_SPI_INT(Int));
-
+	assert_param(IS_SPI_INT(Int));
+	
   if (enable) {
-      SPIx->INT_MASK &= ~Int;
-    } else {
-        SPIx->INT_MASK |= Int;
-    }
-
-    SPIx->INT_MASK &= SPI_INT_ALL;
+	  SPIx->INT_MASK &= ~Int;
+	} else {
+		SPIx->INT_MASK |= Int;
+	}
+	
+	SPIx->INT_MASK &= SPI_INT_ALL;
 }
 
 BOOL SPI_GetIntStatus(SPI0_Type* SPIx, uint32_t Int) {
-    assert_param(IS_SPI_ALL_PERIPH(SPIx));
-    assert_param(IS_SPI_INT(Int));
-
-    if (0 != (SPIx->INT_STATUS & Int)) {
-        return TRUE;
-    }
-
-    return FALSE;
+	assert_param(IS_SPI_ALL_PERIPH(SPIx));
+	assert_param(IS_SPI_INT(Int));
+	
+	if (0 != (SPIx->INT_STATUS & Int)) {
+		return TRUE;
+	}
+	
+	return FALSE;
 }
 void SPI_ClearInt(SPI0_Type* SPIx, uint32_t Int) {
-    assert_param(IS_SPI_ALL_PERIPH(SPIx));
-    assert_param(IS_SPI_INT(Int));
-
-    SPIx->INT_STATUS = Int;
+	assert_param(IS_SPI_ALL_PERIPH(SPIx));
+	assert_param(IS_SPI_INT(Int));
+	
+	SPIx->INT_STATUS = Int;
 }
 
 uint8_t SPI_ReadFifo(SPI0_Type* SPIx, uint8_t size, uint32_t* data) {
-    uint8_t count;
-
-    assert_param(IS_SPI_ALL_PERIPH(SPIx));
-    assert_param(data);
-
-    if (!SPIx->CTRL_b.EN) {
-        return 0;
-    }
-
-    count = 0;
-    while (!SPIx->STATUS_b.RFIFO_EMPTY && count < size) {
-      uint32_t d = SPIx->RW_DATA;
-      d <<= (32 - SPIx->BCNT_b.CNT - 1);
-      d >>= (32 - SPIx->BCNT_b.CNT - 1);
-        *(data + count++) = d;
-    }
-
-    return count;
+	uint8_t count;
+	
+	assert_param(IS_SPI_ALL_PERIPH(SPIx));
+	assert_param(data);
+	
+	if (!SPIx->CTRL_b.EN) {
+		return 0;
+	}
+	
+	count = 0;
+	while (!SPIx->STATUS_b.RFIFO_EMPTY && count < size) {
+	  uint32_t d = SPIx->RW_DATA;
+	  d <<= (32 - SPIx->BCNT_b.CNT - 1);
+	  d >>= (32 - SPIx->BCNT_b.CNT - 1);
+		*(data + count++) = d;
+	}
+	
+	return count;
 }
-
+	
 uint8_t SPI_WriteFifo(SPI0_Type* SPIx, uint8_t Size, uint32_t* data) {
-    uint8_t count;
-
-    assert_param(IS_SPI_ALL_PERIPH(SPIx));
-    assert_param(data);
-
-    if (!SPIx->CTRL_b.EN) {
-        return 0;
-    }
-
-    count = 0;
-    while (!SPIx->STATUS_b.TFIFO_FULL && count < Size) {
-      uint32_t d = *(data + count++);
-        d <<= (32 - SPIx->BCNT_b.CNT - 1);
-        SPIx->RW_DATA = d;
-    }
-
-    return count;
+	uint8_t count;
+	
+	assert_param(IS_SPI_ALL_PERIPH(SPIx));
+	assert_param(data);
+	
+	if (!SPIx->CTRL_b.EN) {
+		return 0;
+	}
+	
+	count = 0;
+	while (!SPIx->STATUS_b.TFIFO_FULL && count < Size) {
+	  uint32_t d = *(data + count++);
+		d <<= (32 - SPIx->BCNT_b.CNT - 1);
+		SPIx->RW_DATA = d;
+	}
+	
+	return count;
 }
 
 BOOL SPI_Transcation(SPI0_Type* SPIx, uint8_t size) {
-    assert_param(IS_SPI_ALL_PERIPH(SPIx));
-    assert_param(size);
-
-    if (!SPIx->CTRL_b.EN) {
-        return FALSE;
-    }
-
-    SPIx->TRANS_CNT = size - 1;
-    SPIx->TRANS_START_b.TX_TRIGGER = TRUE;
-
-    return TRUE;
+	assert_param(IS_SPI_ALL_PERIPH(SPIx));
+	assert_param(size);
+	
+	if (!SPIx->CTRL_b.EN) {
+		return FALSE;
+	}
+	
+	SPIx->TRANS_CNT = size - 1;
+	SPIx->TRANS_START_b.TX_TRIGGER = TRUE;
+	
+	return TRUE;
 }
 

bsp/CME_M7/StdPeriph_Driver/src/cmem7_tim.c

@@ -1,80 +1,80 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_tim.c
-    *
-    * @brief    CMEM7 timer source file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_tim.c
+	*
+	* @brief    CMEM7 timer source file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #include "cmem7_tim.h"
 
 static uint32_t tim_GetClock() {
-    return SYSTEM_CLOCK_FREQ / (1 << (GLOBAL_CTRL->CLK_SEL_0_b.TIMER_CLK + 1));
+	return SYSTEM_CLOCK_FREQ / (1 << (GLOBAL_CTRL->CLK_SEL_0_b.TIMER_CLK + 1));
 }
 
 void TIM_Init(TIMER0_Type* Timx, uint16_t Ms) {
-    assert_param(IS_TIM_ALL_PERIPH(Timx));
-
-    Timx->CTRL_b.EN = FALSE;
-    Timx->LEN = tim_GetClock() / 1000 * Ms;
-    Timx->TYPE_b.SIGNLE_SHOT = TRUE;
+	assert_param(IS_TIM_ALL_PERIPH(Timx));
+	
+	Timx->CTRL_b.EN = FALSE;
+	Timx->LEN = tim_GetClock() / 1000 * Ms;
+	Timx->TYPE_b.SIGNLE_SHOT = TRUE;
 }
 
 void TIM_EnableInt(TIMER0_Type* Timx, BOOL Enable) {
-    assert_param(IS_TIM_ALL_PERIPH(Timx));
-
-    if (Enable == TRUE) {
-      Timx->INT_EN_b.EN_REVERSE = FALSE;
-    } else {
-        Timx->INT_EN_b.EN_REVERSE = TRUE;
-    }
+	assert_param(IS_TIM_ALL_PERIPH(Timx));
+	
+	if (Enable == TRUE) {
+	  Timx->INT_EN_b.EN_REVERSE = FALSE;
+	} else {
+		Timx->INT_EN_b.EN_REVERSE = TRUE;
+	}
 }
 
 BOOL TIM_GetIntStatus(TIMER0_Type* Timx) {
-    assert_param(IS_TIM_ALL_PERIPH(Timx));
-
-    return (Timx->INT_STA_b.STA ? TRUE : FALSE);
+	assert_param(IS_TIM_ALL_PERIPH(Timx));
+	
+	return (Timx->INT_STA_b.STA ? TRUE : FALSE);
 }
 
 void TIM_ClearInt(TIMER0_Type* Timx) {
-    assert_param(IS_TIM_ALL_PERIPH(Timx));
-
-    Timx->INT_STA_b.STA = 1;
+	assert_param(IS_TIM_ALL_PERIPH(Timx));
+	
+	Timx->INT_STA_b.STA = 1;
 }
 
 void TIM_Enable(TIMER0_Type* Timx, BOOL Enable) {
-    assert_param(IS_TIM_ALL_PERIPH(Timx));
-
-    Timx->CTRL_b.EN = Enable;
+	assert_param(IS_TIM_ALL_PERIPH(Timx));
+	
+	Timx->CTRL_b.EN = Enable;
 }
 
 BOOL TIM_IsOverflow(TIMER0_Type* Timx) {
-    assert_param(IS_TIM_ALL_PERIPH(Timx));
-
-    return (Timx->CNT == 0) ? TRUE : FALSE;
+	assert_param(IS_TIM_ALL_PERIPH(Timx));
+	
+	return (Timx->CNT == 0) ? TRUE : FALSE;
 }
 
 uint32_t TIM_GetCounter(TIMER0_Type* Timx) {
-    assert_param(IS_TIM_ALL_PERIPH(Timx));
-
-    return Timx->CNT;
+	assert_param(IS_TIM_ALL_PERIPH(Timx));
+	
+	return Timx->CNT;
 }
 

bsp/CME_M7/StdPeriph_Driver/src/cmem7_uart.c

@@ -1,28 +1,28 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_uart.c
-    *
-    * @brief    CMEM7 uart file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
+	*****************************************************************************
+	* @file     cmem7_uart.c
+	*
+	* @brief    CMEM7 uart file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
 
 #include "cmem7_uart.h"
 
@@ -31,148 +31,147 @@
 
 #define UART_BaudMode_0                     0
 #define UART_BaudMode_1                     1
-#define UART_BaudMode_Division                          19200
+#define UART_BaudMode_Division							19200
 
-#define UART_WR_MAX_FIFO_SIZE               16
+#define UART_WR_MAX_FIFO_SIZE               16	
 
 static uint32_t UART_GetClock(UART0_Type* UARTx) {
-    uint32_t dividor;
-    assert_param(IS_UART_ALL_PERIPH(UARTx));
+	uint32_t dividor;
 
-    if ((uint32_t)UARTx == (uint32_t)UART0) {
-        dividor = GLOBAL_CTRL->CLK_SEL_0_b.UART0_CLK;
-    } else if ((uint32_t)UARTx == (uint32_t)UART1) {
-        dividor = GLOBAL_CTRL->CLK_SEL_0_b.UART1_CLK;
-    } else if ((uint32_t)UARTx == (uint32_t)UART2) {
-        dividor = GLOBAL_CTRL->CLK_SEL_1_b.UART2_CLK;
-    }
-
-    return SYSTEM_CLOCK_FREQ / (1 << (dividor + 1));
+	if ((uint32_t)UARTx == (uint32_t)UART0) {
+		dividor = GLOBAL_CTRL->CLK_SEL_0_b.UART0_CLK;
+	} else if ((uint32_t)UARTx == (uint32_t)UART1) {
+		dividor = GLOBAL_CTRL->CLK_SEL_0_b.UART1_CLK;
+	} else if ((uint32_t)UARTx == (uint32_t)UART2) {
+		dividor = GLOBAL_CTRL->CLK_SEL_1_b.UART2_CLK;
+	}
+	
+	return SYSTEM_CLOCK_FREQ / (1 << (dividor + 1));
 }
 
 static uint16_t UART_CalcBaudrateReload(uint32_t FreqHz, uint32_t Baudrate) {
-  if (Baudrate <= UART_BaudMode_Division) {
-        /** reload in mode 0
-          *    reload = FreqHz / 16 * Baudrate
-          * round up
-          *    reload = FreqHz / 16 * Baudrate + 1/ 2
-          *    reload = (2 * FreqHz + 16 * Baudrate) / 2 * 16 * Baudrate
-          */
-        return ((FreqHz << 1) + (Baudrate << 4)) / (Baudrate << 5);
-    }
-
-    /** reload in mode 1
-        *    reload = Baudrate * 16 * 65536 / FreqHz
-        * round up
-        *    reload = Baudrate * 16 * 65536 / FreqHz + 1/ 2
-        *    reload = (2 * Baudrate * 16 * 65536 + FreqHz) / 2 * FreqHz
-        */
-    return ((((uint64_t)(Baudrate)) << 21) + FreqHz) / (FreqHz << 1);
+  if (Baudrate <= UART_BaudMode_Division) {                     
+		/** reload in mode 0
+		  *    reload = FreqHz / 16 * Baudrate
+		  * round up 
+		  *    reload = FreqHz / 16 * Baudrate + 1/ 2
+		  *    reload = (2 * FreqHz + 16 * Baudrate) / 2 * 16 * Baudrate
+		  */
+		return ((FreqHz << 1) + (Baudrate << 4)) / (Baudrate << 5);
+	} 
+	
+	/** reload in mode 1
+		*    reload = Baudrate * 16 * 65536 / FreqHz
+		* round up 
+		*    reload = Baudrate * 16 * 65536 / FreqHz + 1/ 2
+		*    reload = (2 * Baudrate * 16 * 65536 + FreqHz) / 2 * FreqHz
+		*/
+	return ((((uint64_t)(Baudrate)) << 21) + FreqHz) / (FreqHz << 1);
 }
-
+            
 void UART_Init(UART0_Type* UARTx, UART_InitTypeDef *init) {
-    assert_param(IS_UART_ALL_PERIPH(UARTx));
-    assert_param(init);
-    assert_param(IS_UART_STOPBITS(init->UART_StopBits));
-    assert_param(IS_UART_PARITY(init->UART_Parity));
-
-    /* TODO : assume clock is 50MHz */
-    UARTx->BAUDRATE = UART_CalcBaudrateReload(
-      UART_GetClock(UARTx), init->UART_BaudRate);
-    UARTx->CTRL_b.MODE =
-      (init->UART_Parity == UART_Parity_None) ?
-      UART_Mode_8b : UART_Mode_8b_Parity;
-    UARTx->CTRL_b.STOP = init->UART_StopBits;
-    UARTx->CTRL_b.PARITY =
-      (init->UART_Parity == UART_Parity_None) ?
-      UART_Parity_Even : init->UART_Parity;
-    UARTx->CTRL_b.LOOPBACK = init->UART_LoopBack;
-    UARTx->CTRL_b.RX_EN = init->UART_RxEn;
-    UARTx->CTRL_b.CTS = init->UART_CtsEn;
-    UARTx->CTRL_b.BAUD_MODE =
-      (init->UART_BaudRate > UART_BaudMode_Division) ?
-      UART_BaudMode_1 : UART_BaudMode_0;
-    UARTx->CTRL_b.FIFO_EN = TRUE;
-    UARTx->CTRL_b.RX_THRESHOLD = UART_WR_MAX_FIFO_SIZE;
-    UARTx->CTRL_b.RX_HALF_FULL = (UART_WR_MAX_FIFO_SIZE >> 1);
-    UARTx->TIMEOUT = 0xFF;
-
-    UARTx->INT_MASK |= UART_Int_All;
-    UARTx->INT_SEEN &= UART_Int_All;
+ 	assert_param(IS_UART_ALL_PERIPH(UARTx));
+	assert_param(init);
+ 	assert_param(IS_UART_STOPBITS(init->UART_StopBits));
+ 	assert_param(IS_UART_PARITY(init->UART_Parity));
+	
+	/* TODO : assume clock is 50MHz */
+	UARTx->BAUDRATE = UART_CalcBaudrateReload(
+	  UART_GetClock(UARTx), init->UART_BaudRate);
+	UARTx->CTRL_b.MODE = 
+	  (init->UART_Parity == UART_Parity_None) ? 
+	  UART_Mode_8b : UART_Mode_8b_Parity;	
+	UARTx->CTRL_b.STOP = init->UART_StopBits;
+	UARTx->CTRL_b.PARITY = 
+	  (init->UART_Parity == UART_Parity_None) ? 
+	  UART_Parity_Even : init->UART_Parity;
+	UARTx->CTRL_b.LOOPBACK = init->UART_LoopBack;
+	UARTx->CTRL_b.RX_EN = init->UART_RxEn;
+	UARTx->CTRL_b.CTS = init->UART_CtsEn;
+	UARTx->CTRL_b.BAUD_MODE = 
+	  (init->UART_BaudRate > UART_BaudMode_Division) ? 
+	  UART_BaudMode_1 : UART_BaudMode_0;
+	UARTx->CTRL_b.FIFO_EN = TRUE;
+	UARTx->CTRL_b.RX_THRESHOLD = UART_WR_MAX_FIFO_SIZE;
+	UARTx->CTRL_b.RX_HALF_FULL = (UART_WR_MAX_FIFO_SIZE >> 1);
+	UARTx->TIMEOUT = 0xFF;
+	
+	UARTx->INT_MASK |= UART_Int_All;
+	UARTx->INT_SEEN &= UART_Int_All;
 }
 
 void UART_EnableInt(UART0_Type* UARTx, uint32_t Int, BOOL enable) {
-    assert_param(IS_UART_ALL_PERIPH(UARTx));
-    assert_param(IS_UART_INT(Int));
-
+	assert_param(IS_UART_ALL_PERIPH(UARTx));
+	assert_param(IS_UART_INT(Int));
+	
   if (enable) {
-      UARTx->INT_MASK &= ~Int;
-    } else {
-        UARTx->INT_MASK |= Int;
-    }
-
-    UARTx->INT_MASK &= UART_Int_All;
+	  UARTx->INT_MASK &= ~Int;
+	} else {
+		UARTx->INT_MASK |= Int;
+	}
+	
+	UARTx->INT_MASK &= UART_Int_All;
 }
 
 void UART_Enable(UART0_Type* UARTx, BOOL enable) {
-    assert_param(IS_UART_ALL_PERIPH(UARTx));
-
-    UARTx->RUN_b.EN = enable;
+	assert_param(IS_UART_ALL_PERIPH(UARTx));
+	
+	UARTx->RUN_b.EN = enable;
 }
 
 BOOL UART_GetIntStatus(UART0_Type* UARTx, uint32_t Int) {
-    assert_param(IS_UART_ALL_PERIPH(UARTx));
-    assert_param(IS_UART_INT(Int));
-
-    if (0 != (UARTx->INT_SEEN & Int)) {
-        return TRUE;
-    }
-
-    return FALSE;
+	assert_param(IS_UART_ALL_PERIPH(UARTx));
+	assert_param(IS_UART_INT(Int));
+	
+	if (0 != (UARTx->INT_SEEN & Int)) {
+		return TRUE;
+	}
+	
+	return FALSE;
 }
 
 void UART_ClearInt(UART0_Type* UARTx, uint32_t Int) {
-    assert_param(IS_UART_ALL_PERIPH(UARTx));
-    assert_param(IS_UART_INT(Int));
-
-    UARTx->INT_SEEN = Int;
+	assert_param(IS_UART_ALL_PERIPH(UARTx));
+	assert_param(IS_UART_INT(Int));
+	
+	UARTx->INT_SEEN = Int;
 }
 
 uint8_t UART_Write(UART0_Type* UARTx, uint8_t Size, uint8_t* Data) {
-    uint8_t count;
-
-    /* Check the parameters */
+	uint8_t count;
+	
+	/* Check the parameters */
   assert_param(IS_UART_ALL_PERIPH(UARTx));
-    assert_param(Data);
-
-    if (!UARTx->RUN_b.EN) {
-        return 0;
-    }
-
-    count = 0;
-    while (!UARTx->STATUS_b.TF && count < Size) {
-        UARTx->TX_BUF = *(Data + count++);
-    }
-
-    return count;
+	assert_param(Data);
+	
+	if (!UARTx->RUN_b.EN) {
+		return 0;
+	}
+	
+	count = 0;
+	while (!UARTx->STATUS_b.TF && count < Size) {
+		UARTx->TX_BUF = *(Data + count++);
+	}
+  
+	return count;
 }
 
 /* return value is actual read data size */
 uint8_t UART_Read(UART0_Type* UARTx, uint8_t Size, uint8_t* Data) {
-    uint8_t count;
-
-    assert_param(IS_UART_ALL_PERIPH(UARTx));
-    assert_param(Data);
-
-    if (!UARTx->RUN_b.EN) {
-        return 0;
-    }
-
-    count = 0;
-    while (UARTx->STATUS_b.RNE && count < Size) {
-        *(Data + count++) = (UARTx->RX_BUF & 0x00FF);
-    }
-
-    return count;
+	uint8_t count;
+	
+	assert_param(IS_UART_ALL_PERIPH(UARTx));
+	assert_param(Data);
+	
+	if (!UARTx->RUN_b.EN) {
+		return 0;
+	}
+	
+	count = 0;
+	while (UARTx->STATUS_b.RNE && count < Size) {
+		*(Data + count++) = (UARTx->RX_BUF & 0x00FF);
+	}
+	
+	return count;	
 }
 

bsp/CME_M7/StdPeriph_Driver/src/cmem7_wdg.c

@@ -1,63 +1,63 @@
 /**
-    *****************************************************************************
-    * @file     cmem7_wdg.c
-    *
-    * @brief    CMEM7 watchdog source file
-    *
-    *
-    * @version  V1.0
-    * @date     3. September 2013
-    *
-    * @note
-    *
-    *****************************************************************************
-    * @attention
-    *
-    * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-    * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-    * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-    * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-    * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-    * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-    *
-    * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-    *****************************************************************************
-    */
-
+	*****************************************************************************
+	* @file     cmem7_wdg.c
+	*
+	* @brief    CMEM7 watchdog source file
+	*
+	*
+	* @version  V1.0
+	* @date     3. September 2013
+	*
+	* @note               
+	*           
+	*****************************************************************************
+	* @attention
+	*
+	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
+	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+	*
+	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
+	*****************************************************************************
+	*/
+	
 #include "cmem7_wdg.h"
 
 static uint32_t wdg_GetClock() {
-    return SYSTEM_CLOCK_FREQ / (1 << (GLOBAL_CTRL->CLK_SEL_0_b.WDG_CLK + 1));
+	return SYSTEM_CLOCK_FREQ / (1 << (GLOBAL_CTRL->CLK_SEL_0_b.WDG_CLK + 1));
 }
 
 void WDG_DeInit(void){
   SOFT_RESET->SOFTRST_b.WDT_n = 0;
-    SOFT_RESET->SOFTRST_b.WDT_n = 1;
+	SOFT_RESET->SOFTRST_b.WDT_n = 1;
 }
 
 void WDG_Init(uint8_t trigger, uint16_t ResetMillSecond) {
-    assert_param(IS_WDG_TRIGGER_MODE(trigger));
-
-    WDG->INT_CTRL_b.TRIGGER_MODE = trigger;
-    WDG->LEN = ((uint64_t)wdg_GetClock()) * ResetMillSecond / 1000;
+	assert_param(IS_WDG_TRIGGER_MODE(trigger));
+	
+	WDG->INT_CTRL_b.TRIGGER_MODE = trigger;
+	WDG->LEN = ((uint64_t)wdg_GetClock()) * ResetMillSecond / 1000;
 }
 
 void WDG_ITConfig(uint8_t Int, BOOL Enable) {
-    assert_param(IS_WDG_INT(Int));
-
-    WDG->CTRL_b.INT_LEN = Int;
-    WDG->INT_CTRL_b.MASK = !Enable;
+	assert_param(IS_WDG_INT(Int));
+	
+	WDG->CTRL_b.INT_LEN = Int;
+	WDG->INT_CTRL_b.MASK = !Enable;
 }
 
 BOOL WDG_GetITStatus() {
-    return (WDG->INT_STA_b.STA == 1) ? TRUE : FALSE;
+	return (WDG->INT_STA_b.STA == 1) ? TRUE : FALSE;
 }
 
 void WDG_ClearITPendingBit() {
-    WDG->INT_STA_b.STA = 1;
+	WDG->INT_STA_b.STA = 1;
 }
 
 void WDG_Cmd(BOOL Enable) {
-    WDG->CTRL_b.EN = Enable;
+	WDG->CTRL_b.EN = Enable;
 }
 

bsp/CME_M7/drivers/app_phy.c

@@ -107,7 +107,7 @@ BOOL phy_Init() {
             speed = 1000;
         }
 
-        printf("PHY runs in %uM speed %s duplex\n",
+        printf("PHY runs in %dM speed %s duplex\n",
             speed, (phy_GetDuplex() == PHY_DUPLEX_HALF) ? "half" : "full");
     }
 

bsp/CME_M7/project.uvproj

@@ -361,9 +361,9 @@
             <useXO>0</useXO>
             <VariousControls>
               <MiscControls />
-              <Define>RT_USING_LIBC, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define>
+              <Define>RT_USING_LIBC, __RTTHREAD__, __STDC_LIMIT_MACROS, RT_USING_ARM_LIBC, __CLK_TCK=RT_TICK_PER_SECOND</Define>
               <Undefine />
-              <IncludePath>.;..\..\components\libc\compilers\common\extension;..\..\libcpu\arm\cortex-m3;..\..\include;CMSIS\CMSIS\Include;..\..\components\net\lwip\lwip-2.0.3\src\include\netif;..\..\components\net\lwip\lwip-2.0.3\src\include\posix;applications;..\..\components\finsh;..\..\components\drivers\include;..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\components\libc\posix\io\stdio;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\dfs\include;..\..\components\net\lwip\lwip-2.0.3\src\include\ipv4;StdPeriph_Driver\inc;..\..\components\drivers\include;..\..\libcpu\arm\common;..\..\components\libc\posix\ipc;CMSIS\CME_M7;..\..\components\net\lwip\port;..\..\components\libc\posix\io\poll;..\..\components\libc\compilers\common\include;drivers;..\..\components\net\lwip\lwip-2.0.3\src\include</IncludePath>
+              <IncludePath>applications;.;CMSIS\CME_M7;CMSIS\CMSIS\Include;..\..\components\libc\compilers\common\include;..\..\components\libc\compilers\common\extension;..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;drivers;..\..\components\dfs\include;..\..\components\dfs\filesystems\elmfat;..\..\components\finsh;.;..\..\include;StdPeriph_Driver\inc;..\..\components\net\lwip\lwip-2.0.3\src\include;..\..\components\net\lwip\lwip-2.0.3\src\include\ipv4;..\..\components\net\lwip\lwip-2.0.3\src\include\netif;..\..\components\net\lwip\lwip-2.0.3\src\include\posix;..\..\components\net\lwip\port;..\..\components\libc\posix\io\poll;..\..\components\libc\posix\io\stdio;..\..\components\libc\posix\ipc</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -407,9 +407,9 @@
           <GroupName>Applications</GroupName>
           <Files>
             <File>
-              <FileName>application.c</FileName>
+              <FileName>startup.c</FileName>
               <FileType>1</FileType>
-              <FilePath>applications\application.c</FilePath>
+              <FilePath>applications\startup.c</FilePath>
             </File>
           </Files>
           <Files>
@@ -421,9 +421,9 @@
           </Files>
           <Files>
             <File>
-              <FileName>startup.c</FileName>
+              <FileName>application.c</FileName>
               <FileType>1</FileType>
-              <FilePath>applications\startup.c</FilePath>
+              <FilePath>applications\application.c</FilePath>
             </File>
           </Files>
         </Group>
@@ -507,9 +507,9 @@
           <GroupName>CPU</GroupName>
           <Files>
             <File>
-              <FileName>atomic_arm.c</FileName>
+              <FileName>backtrace.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\common\atomic_arm.c</FilePath>
+              <FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath>
             </File>
           </Files>
           <Files>
@@ -802,9 +802,9 @@
           </Files>
           <Files>
             <File>
-              <FileName>scheduler_up.c</FileName>
+              <FileName>scheduler.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\scheduler_up.c</FilePath>
+              <FilePath>..\..\src\scheduler.c</FilePath>
             </File>
           </Files>
           <Files>
@@ -831,90 +831,6 @@
               <FilePath>StdPeriph_Driver\src\cmem7_eth.c</FilePath>
             </File>
           </Files>
-          <Files>
-            <File>
-              <FileName>cmem7_adc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>StdPeriph_Driver\src\cmem7_adc.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>cmem7_misc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>StdPeriph_Driver\src\cmem7_misc.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>cmem7_can.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>StdPeriph_Driver\src\cmem7_can.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>cmem7_uart.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>StdPeriph_Driver\src\cmem7_uart.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>cmem7_efuse.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>StdPeriph_Driver\src\cmem7_efuse.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>cmem7_flash.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>StdPeriph_Driver\src\cmem7_flash.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>cmem7_usb.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>StdPeriph_Driver\src\cmem7_usb.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>cmem7_gpio.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>StdPeriph_Driver\src\cmem7_gpio.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>cmem7_aes.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>StdPeriph_Driver\src\cmem7_aes.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>cmem7_i2c.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>StdPeriph_Driver\src\cmem7_i2c.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>cmem7_rtc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>StdPeriph_Driver\src\cmem7_rtc.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>cmem7_tim.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>StdPeriph_Driver\src\cmem7_tim.c</FilePath>
-            </File>
-          </Files>
           <Files>
             <File>
               <FileName>cmem7_dma.c</FileName>
@@ -924,9 +840,9 @@
           </Files>
           <Files>
             <File>
-              <FileName>cmem7_spi.c</FileName>
+              <FileName>cmem7_uart.c</FileName>
               <FileType>1</FileType>
-              <FilePath>StdPeriph_Driver\src\cmem7_spi.c</FilePath>
+              <FilePath>StdPeriph_Driver\src\cmem7_uart.c</FilePath>
             </File>
           </Files>
           <Files>
@@ -943,6 +859,90 @@
               <FilePath>StdPeriph_Driver\src\cmem7_ddr.c</FilePath>
             </File>
           </Files>
+          <Files>
+            <File>
+              <FileName>cmem7_aes.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>StdPeriph_Driver\src\cmem7_aes.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>cmem7_flash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>StdPeriph_Driver\src\cmem7_flash.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>cmem7_rtc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>StdPeriph_Driver\src\cmem7_rtc.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>cmem7_efuse.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>StdPeriph_Driver\src\cmem7_efuse.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>cmem7_usb.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>StdPeriph_Driver\src\cmem7_usb.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>cmem7_adc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>StdPeriph_Driver\src\cmem7_adc.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>cmem7_i2c.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>StdPeriph_Driver\src\cmem7_i2c.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>cmem7_misc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>StdPeriph_Driver\src\cmem7_misc.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>cmem7_spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>StdPeriph_Driver\src\cmem7_spi.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>cmem7_tim.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>StdPeriph_Driver\src\cmem7_tim.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>cmem7_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>StdPeriph_Driver\src\cmem7_gpio.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>cmem7_can.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>StdPeriph_Driver\src\cmem7_can.c</FilePath>
+            </File>
+          </Files>
         </Group>
         <Group>
           <GroupName>lwIP</GroupName>

bsp/CME_M7/rtconfig.h

@@ -35,7 +35,6 @@
 
 /* Memory Management */
 
-#define RT_PAGE_MAX_ORDER 11
 #define RT_USING_MEMPOOL
 #define RT_USING_SMALL_MEM
 #define RT_USING_SMALL_MEM_AS_HEAP
@@ -47,10 +46,9 @@
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart2"
-#define RT_VER_NUM 0x50000
-#define RT_USING_HW_ATOMIC
-#define RT_USING_CPU_FFS
+#define RT_VER_NUM 0x40101
 #define ARCH_ARM
+#define RT_USING_CPU_FFS
 #define ARCH_ARM_CORTEX_M
 #define ARCH_ARM_CORTEX_M3
 
@@ -95,7 +93,6 @@
 /* Device Drivers */
 
 #define RT_USING_DEVICE_IPC
-#define RT_UNAMED_PIPE_NUMBER 64
 #define RT_USING_SERIAL
 #define RT_USING_SERIAL_V1
 #define RT_SERIAL_USING_DMA
@@ -205,6 +202,9 @@
 /* u8g2: a monochrome graphic library */
 
 
+/* PainterEngine: A cross-platform graphics application framework written in C language */
+
+
 /* tools packages */
 
 
@@ -224,11 +224,6 @@
 
 /* peripheral libraries and drivers */
 
-/* sensors drivers */
-
-
-/* touch drivers */
-
 
 /* Kendryte SDK */
 
@@ -236,9 +231,6 @@
 /* AI packages */
 
 
-/* Signal Processing and Control Algorithm Packages */
-
-
 /* miscellaneous packages */
 
 /* project laboratory */
@@ -249,39 +241,13 @@
 /* entertainment: terminal games and other interesting software packages */
 
 
-/* Arduino libraries */
+/* Privated Packages of RealThread */
 
 
-/* Projects */
+/* Network Utilities */
 
 
-/* Sensors */
-
-
-/* Display */
-
-
-/* Timing */
-
-
-/* Data Processing */
-
-
-/* Data Storage */
-
-/* Communication */
-
-
-/* Device Control */
-
-
-/* Other */
-
-
-/* Signal IO */
-
-
-/* Uncategorized */
+/* RT-Thread Smart */
 
 #define SOC_CME_M7
 

bsp/ESP32_C3/.config

@@ -45,7 +45,6 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
 #
 # Memory Management
 #
-CONFIG_RT_PAGE_MAX_ORDER=11
 CONFIG_RT_USING_MEMPOOL=y
 CONFIG_RT_USING_SMALL_MEM=y
 # CONFIG_RT_USING_SLAB is not set
@@ -64,18 +63,13 @@ CONFIG_RT_USING_HEAP=y
 #
 CONFIG_RT_USING_DEVICE=y
 # CONFIG_RT_USING_DEVICE_OPS is not set
-# CONFIG_RT_USING_DM is not set
 # CONFIG_RT_USING_INTERRUPT_INFO is not set
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=256
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart"
 CONFIG_RT_VER_NUM=0x50000
-# CONFIG_RT_USING_STDC_ATOMIC is not set
-# CONFIG_RT_USING_CACHE is not set
-# CONFIG_RT_USING_HW_ATOMIC is not set
-# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
-# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 # CONFIG_RT_USING_CPU_FFS is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 
 #
 # RT-Thread Components
@@ -107,7 +101,6 @@ CONFIG_FINSH_ARG_MAX=10
 # Device Drivers
 #
 CONFIG_RT_USING_DEVICE_IPC=y
-CONFIG_RT_UNAMED_PIPE_NUMBER=64
 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
 CONFIG_RT_USING_SERIAL=y
 CONFIG_RT_USING_SERIAL_V1=y
@@ -122,14 +115,10 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_DAC is not set
-# CONFIG_RT_USING_NULL is not set
-# CONFIG_RT_USING_ZERO is not set
-# CONFIG_RT_USING_RANDOM is not set
 # CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_PM is not set
-# CONFIG_RT_USING_FDT is not set
 # CONFIG_RT_USING_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
 # CONFIG_RT_USING_SPI is not set
@@ -137,13 +126,10 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_AUDIO is not set
 # CONFIG_RT_USING_SENSOR is not set
 # CONFIG_RT_USING_TOUCH is not set
-# CONFIG_RT_USING_LCD is not set
 # CONFIG_RT_USING_HWCRYPTO is not set
 # CONFIG_RT_USING_PULSE_ENCODER is not set
 # CONFIG_RT_USING_INPUT_CAPTURE is not set
-# CONFIG_RT_USING_DEV_BUS is not set
 # CONFIG_RT_USING_WIFI is not set
-# CONFIG_RT_USING_VIRTIO is not set
 
 #
 # Using USB
@@ -194,7 +180,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_RT_USING_ULOG is not set
 # CONFIG_RT_USING_UTEST is not set
 # CONFIG_RT_USING_VAR_EXPORT is not set
-# CONFIG_RT_USING_ADT is not set
 # CONFIG_RT_USING_RT_LINK is not set
 # CONFIG_RT_USING_VBUS is not set
 
@@ -289,8 +274,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_AGILE_FTP is not set
 # CONFIG_PKG_USING_EMBEDDEDPROTO is not set
 # CONFIG_PKG_USING_RT_LINK_HW is not set
-# CONFIG_PKG_USING_RYANMQTT is not set
-# CONFIG_PKG_USING_RYANW5500 is not set
 # CONFIG_PKG_USING_LORA_PKT_FWD is not set
 # CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
 # CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
@@ -298,8 +281,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_SMALL_MODBUS is not set
 # CONFIG_PKG_USING_NET_SERVER is not set
 # CONFIG_PKG_USING_ZFTP is not set
-# CONFIG_PKG_USING_WOL is not set
-# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
 
 #
 # security packages
@@ -368,12 +349,17 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_MP3PLAYER is not set
 # CONFIG_PKG_USING_TINYJPEG is not set
 # CONFIG_PKG_USING_UGUI is not set
+
+#
+# PainterEngine: A cross-platform graphics application framework written in C language
+#
+# CONFIG_PKG_USING_PAINTERENGINE is not set
+# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
 # CONFIG_PKG_USING_MCURSES is not set
 # CONFIG_PKG_USING_TERMBOX is not set
 # CONFIG_PKG_USING_VT100 is not set
 # CONFIG_PKG_USING_QRCODE is not set
 # CONFIG_PKG_USING_GUIENGINE is not set
-# CONFIG_PKG_USING_3GPP_AMRNB is not set
 
 #
 # tools packages
@@ -383,9 +369,9 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_EASYLOGGER is not set
 # CONFIG_PKG_USING_SYSTEMVIEW is not set
 # CONFIG_PKG_USING_SEGGER_RTT is not set
-# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
 # CONFIG_PKG_USING_RDB is not set
 # CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
 # CONFIG_PKG_USING_LOGMGR is not set
 # CONFIG_PKG_USING_ADBD is not set
 # CONFIG_PKG_USING_COREMARK is not set
@@ -419,6 +405,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_CBOX is not set
 # CONFIG_PKG_USING_SNOWFLAKE is not set
 # CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
 # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
 # CONFIG_PKG_USING_VOFA_PLUS is not set
 
@@ -494,97 +481,22 @@ CONFIG_PKG_FREERTOS_WRAPPER_VER="latest"
 # CONFIG_PKG_USING_TFDB is not set
 # CONFIG_PKG_USING_QPC is not set
 # CONFIG_PKG_USING_AGILE_UPGRADE is not set
-# CONFIG_PKG_USING_FLASH_BLOB is not set
 
 #
 # peripheral libraries and drivers
 #
-
-#
-# sensors drivers
-#
-# CONFIG_PKG_USING_LSM6DSM is not set
-# CONFIG_PKG_USING_LSM6DSL is not set
-# CONFIG_PKG_USING_LPS22HB is not set
-# CONFIG_PKG_USING_HTS221 is not set
-# CONFIG_PKG_USING_LSM303AGR is not set
-# CONFIG_PKG_USING_BME280 is not set
-# CONFIG_PKG_USING_BME680 is not set
-# CONFIG_PKG_USING_BMA400 is not set
-# CONFIG_PKG_USING_BMI160_BMX160 is not set
-# CONFIG_PKG_USING_SPL0601 is not set
-# CONFIG_PKG_USING_MS5805 is not set
-# CONFIG_PKG_USING_DA270 is not set
-# CONFIG_PKG_USING_DF220 is not set
-# CONFIG_PKG_USING_HSHCAL001 is not set
-# CONFIG_PKG_USING_BH1750 is not set
-# CONFIG_PKG_USING_MPU6XXX is not set
-# CONFIG_PKG_USING_AHT10 is not set
-# CONFIG_PKG_USING_AP3216C is not set
-# CONFIG_PKG_USING_TSL4531 is not set
-# CONFIG_PKG_USING_DS18B20 is not set
-# CONFIG_PKG_USING_DHT11 is not set
-# CONFIG_PKG_USING_DHTXX is not set
-# CONFIG_PKG_USING_GY271 is not set
-# CONFIG_PKG_USING_GP2Y10 is not set
-# CONFIG_PKG_USING_SGP30 is not set
-# CONFIG_PKG_USING_HDC1000 is not set
-# CONFIG_PKG_USING_BMP180 is not set
-# CONFIG_PKG_USING_BMP280 is not set
-# CONFIG_PKG_USING_SHTC1 is not set
-# CONFIG_PKG_USING_BMI088 is not set
-# CONFIG_PKG_USING_HMC5883 is not set
-# CONFIG_PKG_USING_MAX6675 is not set
-# CONFIG_PKG_USING_TMP1075 is not set
-# CONFIG_PKG_USING_SR04 is not set
-# CONFIG_PKG_USING_CCS811 is not set
-# CONFIG_PKG_USING_PMSXX is not set
-# CONFIG_PKG_USING_RT3020 is not set
-# CONFIG_PKG_USING_MLX90632 is not set
-# CONFIG_PKG_USING_MLX90393 is not set
-# CONFIG_PKG_USING_MLX90392 is not set
-# CONFIG_PKG_USING_MLX90397 is not set
-# CONFIG_PKG_USING_MS5611 is not set
-# CONFIG_PKG_USING_MAX31865 is not set
-# CONFIG_PKG_USING_VL53L0X is not set
-# CONFIG_PKG_USING_INA260 is not set
-# CONFIG_PKG_USING_MAX30102 is not set
-# CONFIG_PKG_USING_INA226 is not set
-# CONFIG_PKG_USING_LIS2DH12 is not set
-# CONFIG_PKG_USING_HS300X is not set
-# CONFIG_PKG_USING_ZMOD4410 is not set
-# CONFIG_PKG_USING_ISL29035 is not set
-# CONFIG_PKG_USING_MMC3680KJ is not set
-# CONFIG_PKG_USING_QMP6989 is not set
-# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
 # CONFIG_PKG_USING_SHT2X is not set
 # CONFIG_PKG_USING_SHT3X is not set
-# CONFIG_PKG_USING_AD7746 is not set
 # CONFIG_PKG_USING_ADT74XX is not set
-# CONFIG_PKG_USING_MAX17048 is not set
 # CONFIG_PKG_USING_AS7341 is not set
-# CONFIG_PKG_USING_CW2015 is not set
-# CONFIG_PKG_USING_ICM20608 is not set
-# CONFIG_PKG_USING_PAJ7620 is not set
-# CONFIG_PKG_USING_STHS34PF80 is not set
-
-#
-# touch drivers
-#
-# CONFIG_PKG_USING_GT9147 is not set
-# CONFIG_PKG_USING_GT1151 is not set
-# CONFIG_PKG_USING_GT917S is not set
-# CONFIG_PKG_USING_GT911 is not set
-# CONFIG_PKG_USING_FT6206 is not set
-# CONFIG_PKG_USING_FT5426 is not set
-# CONFIG_PKG_USING_FT6236 is not set
-# CONFIG_PKG_USING_XPT2046_TOUCH is not set
-# CONFIG_PKG_USING_REALTEK_AMEBA is not set
 # CONFIG_PKG_USING_STM32_SDIO is not set
 CONFIG_PKG_USING_ESP_IDF=y
 CONFIG_PKG_ESP_IDF_PATH="/packages/peripherals/ESP-IDF"
 CONFIG_PKG_USING_ESP_IDF_LATEST_VERSION=y
 CONFIG_PKG_ESP_IDF_VER="latest"
+# CONFIG_PKG_USING_ICM20608 is not set
 # CONFIG_PKG_USING_BUTTON is not set
 # CONFIG_PKG_USING_PCF8574 is not set
 # CONFIG_PKG_USING_SX12XX is not set
@@ -607,10 +519,12 @@ CONFIG_PKG_ESP_IDF_VER="latest"
 # CONFIG_PKG_USING_AGILE_LED is not set
 # CONFIG_PKG_USING_AT24CXX is not set
 # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
 # CONFIG_PKG_USING_PCA9685 is not set
-# CONFIG_PKG_USING_ILI9341 is not set
 # CONFIG_PKG_USING_I2C_TOOLS is not set
 # CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
 # CONFIG_PKG_USING_RPLIDAR is not set
 # CONFIG_PKG_USING_AS608 is not set
 # CONFIG_PKG_USING_RC522 is not set
@@ -625,6 +539,7 @@ CONFIG_PKG_ESP_IDF_VER="latest"
 # CONFIG_PKG_USING_CAN_YMODEM is not set
 # CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
 # CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
 # CONFIG_PKG_USING_AGILE_CONSOLE is not set
 # CONFIG_PKG_USING_LD3320 is not set
 # CONFIG_PKG_USING_WK2124 is not set
@@ -655,11 +570,10 @@ CONFIG_PKG_ESP_IDF_VER="latest"
 # CONFIG_PKG_USING_BL_MCU_SDK is not set
 # CONFIG_PKG_USING_SOFT_SERIAL is not set
 # CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_CW2015 is not set
 # CONFIG_PKG_USING_RFM300 is not set
 # CONFIG_PKG_USING_IO_INPUT_FILTER is not set
 # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
-# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
-# CONFIG_PKG_USING_FINGERPRINT is not set
 
 #
 # AI packages
@@ -674,12 +588,6 @@ CONFIG_PKG_ESP_IDF_VER="latest"
 # CONFIG_PKG_USING_QUEST is not set
 # CONFIG_PKG_USING_NAXOS is not set
 
-#
-# Signal Processing and Control Algorithm Packages
-#
-# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
-# CONFIG_PKG_USING_UKAL is not set
-
 #
 # miscellaneous packages
 #
@@ -709,7 +617,6 @@ CONFIG_PKG_ESP_IDF_VER="latest"
 # CONFIG_PKG_USING_TETRIS is not set
 # CONFIG_PKG_USING_DONUT is not set
 # CONFIG_PKG_USING_COWSAY is not set
-# CONFIG_PKG_USING_MORSE is not set
 # CONFIG_PKG_USING_LIBCSV is not set
 # CONFIG_PKG_USING_OPTPARSE is not set
 # CONFIG_PKG_USING_FASTLZ is not set
@@ -732,6 +639,7 @@ CONFIG_PKG_ESP_IDF_VER="latest"
 # CONFIG_PKG_USING_VI is not set
 # CONFIG_PKG_USING_KI is not set
 # CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_UKAL is not set
 # CONFIG_PKG_USING_CRCLIB is not set
 # CONFIG_PKG_USING_LWGPS is not set
 # CONFIG_PKG_USING_STATE_MACHINE is not set
@@ -742,7 +650,6 @@ CONFIG_PKG_ESP_IDF_VER="latest"
 # CONFIG_PKG_USING_SLCAN2RTT is not set
 # CONFIG_PKG_USING_SOEM is not set
 # CONFIG_PKG_USING_QPARAM is not set
-# CONFIG_PKG_USING_CorevMCU_CLI is not set
 
 #
 # Arduino libraries
@@ -754,153 +661,30 @@ CONFIG_PKG_ESP_IDF_VER="latest"
 #
 # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
 # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
-# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
 
 #
 # Sensors
 #
-# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
-# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
-# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
-# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
-# CONFIG_PKG_USING_SEEED_ITG3200 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
-# CONFIG_PKG_USING_SEEED_MP503 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
 
 #
 # Display
 #
 # CONFIG_PKG_USING_ARDUINO_U8G2 is not set
-# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
-# CONFIG_PKG_USING_SEEED_TM1637 is not set
 
 #
 # Timing
@@ -911,7 +695,6 @@ CONFIG_PKG_ESP_IDF_VER="latest"
 # Data Processing
 #
 # CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
-# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
 
 #
 # Data Storage
@@ -920,38 +703,20 @@ CONFIG_PKG_ESP_IDF_VER="latest"
 #
 # Communication
 #
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
 
 #
 # Device Control
 #
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
 
 #
 # Other
 #
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
-# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
 
 #
 # Signal IO
 #
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
 
 #
 # Uncategorized
@@ -979,4 +744,3 @@ CONFIG_RT_BSP_UART_RX_PIN=20
 #
 CONFIG_BSP_USING_GPIO=y
 CONFIG_BSP_USING_UART=y
-# CONFIG_BSP_USING_I2C0 is not set

bsp/ESP32_C3/drivers/Kconfig

@@ -1,6 +1,6 @@
 
 config SOC_ESPRESSIF
-    bool 
+    bool
 
 config SOC_ESP32_C3
     bool
@@ -24,7 +24,7 @@ choice
         bool "LUATOS ESP32C3 board"
 
     config BSP_BOARD_HX_EXP32C3
-        bool "HONGXU ESP32C3 board"    
+        bool "HONGXU ESP32C3 board"
 endchoice
 
 menu "Onboard Peripheral Drivers"
@@ -57,17 +57,12 @@ menu "On-chip Peripheral Drivers"
         bool "Enable GPIO"
         select RT_USING_PIN
         default y
-    
+
     config BSP_USING_UART
-		bool "Enable UART"
+        bool "Enable UART"
         select RT_USING_SERIAL
         select RT_USING_SERIAL_V1
         default y
-
-    config BSP_USING_I2C0
-        bool "Enable I2C0"
-        select RT_USING_I2C
-        default n        
 endmenu
 
 endmenu

bsp/ESP32_C3/drivers/drv_gpio.c

@@ -15,20 +15,20 @@
 
 #ifdef RT_USING_PIN
 
-static void mcu_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
+static void mcu_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
 {
     gpio_set_level(pin, value);
     /*TODO:set gpio out put mode */
 }
 
-static rt_int8_t mcu_pin_read(rt_device_t dev, rt_base_t pin)
+static int mcu_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    rt_int8_t value;
+    int value;
     value = gpio_get_level(pin);
     return value;
 }
 
-static void mcu_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
+static void mcu_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
 {
     gpio_config_t io_conf;
     io_conf.intr_type = GPIO_INTR_DISABLE;
@@ -45,22 +45,22 @@ static void mcu_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 }
 
 
-static rt_err_t mcu_pin_attach_irq(struct rt_device *device, rt_base_t pin,
-                                   rt_uint8_t irq_mode, void (*hdr)(void *args), void *args)
+static rt_err_t mcu_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                                   rt_uint32_t irq_mode, void (*hdr)(void *args), void *args)
 {
 
     /*TODO: start irq handle */
-    return -RT_ENOSYS;
+    return RT_EOK;
 }
 
-static rt_err_t mcu_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t mcu_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
 {
     /*TODO:disable gpio irq handle */
     return RT_EOK;
 }
 
 static rt_err_t mcu_pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                                   rt_uint8_t enabled)
+                                   rt_uint32_t enabled)
 {
     /*TODO:start irq handle */
     return RT_EOK;
@@ -72,7 +72,7 @@ const static struct rt_pin_ops _mcu_pin_ops =
     mcu_pin_write,
     mcu_pin_read,
     mcu_pin_attach_irq,
-    mcu_pin_detach_irq,
+    mcu_pin_dettach_irq,
     mcu_pin_irq_enable,
     RT_NULL,
 };

bsp/ESP32_C3/drivers/drv_hw_i2c.c

@@ -1,133 +0,0 @@
-/*
- * Copyright (c) 2006-2023, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- *2023-03-28      Zxy          first version
- */
-#ifdef RT_USING_I2C
-#include "drv_hw_i2c.h"
-#include "driver/i2c.h"//bsp/ESP32_C3/packages/ESP-IDF-latest/components/driver/include/driver/i2c.h
-#include "hal/i2c_types.h"//bsp/ESP32_C3/packages/ESP-IDF-latest/tools/mocks/hal/include/hal/i2c_types.h
-#include "esp_err.h"
-//#include "portmacro.h"//bsp/ESP32_C3/packages/FreeRTOS_Wrapper-latest/FreeRTOS/portable/rt-thread/portmacro.h
-
-struct esp32_i2c
-{
-    struct rt_i2c_bus_device bus;
-
-    i2c_config_t *base;
-
-    char *device_name;
-};
-
-// #if defined(BSP_USING_I2C0)
-static struct esp32_i2c i2c0 = {0};
-// #endif
-
-static rt_size_t _master_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num)
-{
-    i2c_cmd_handle_t cmd;//创建流程
-    rt_size_t ret = (0);
-    rt_uint32_t index = 0;
-    // struct esp32_i2c *esp32_i2c = RT_NULL;
-    struct rt_i2c_msg *msg = RT_NULL;
-    i2c_rw_t direction;//w-0 r-1
-    esp_err_t result = ESP_OK;
-
-    RT_ASSERT(bus != RT_NULL);
-
-    // esp32_i2c = (struct esp32_i2c *)bus;
-
-    for(index = 0; index < num; index++)
-    {
-        msg = &msgs[index];
-        direction = ((msg->flags & RT_I2C_RD) ? I2C_MASTER_READ : I2C_MASTER_WRITE);
-
-        if (!(msg->flags & RT_I2C_NO_START))
-        {
-            /* Start condition and slave address. */
-            cmd = i2c_cmd_link_create();//创建流程
-            i2c_master_start(cmd);//启动流程录入
-            result = i2c_master_write_byte(cmd, msg->addr << 1 | WRITE_BIT, ACK_CHECK_EN);//发送起始信号和从设备地址
-            i2c_master_stop(cmd);//流程录入完毕
-            ret = i2c_master_cmd_begin(I2C_NUMBER(0), cmd, 1000 / portTICK_PERIOD_MS);//执行流程
-            i2c_cmd_link_delete(cmd);//删除流程任务
-            if (ret != ESP_OK) return ret;
-        }
-
-        if (result == ESP_OK)
-        {
-            if (direction == I2C_MASTER_WRITE)
-            {
-                /* Transmit data. */
-                cmd = i2c_cmd_link_create();//创建流程
-                i2c_master_start(cmd);//启动流程录入
-                result = i2c_master_write_byte(cmd, msg->buf, ACK_CHECK_EN);
-                i2c_master_stop(cmd);//流程录入完毕
-                ret = i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 1000 / portTICK_PERIOD_MS);//执行流程
-                i2c_cmd_link_delete(cmd);//删除流程任务
-            }
-            else
-            {
-                /* Receive Data. */
-                cmd = i2c_cmd_link_create();//创建流程
-                i2c_master_start(cmd);//启动流程录入
-                result = i2c_master_read_byte(cmd, msg->buf, ACK_VAL);
-                i2c_master_stop(cmd);//流程录入完毕
-                ret = i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 1000 / portTICK_PERIOD_MS);//执行流程
-                i2c_cmd_link_delete(cmd);//删除流程任务
-            }
-        }
-    }
-
-    if (result == ESP_OK)
-    {
-        ret = index;
-    }
-
-    return ret;
-}
-
-static rt_size_t _slave_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num)
-{
-    return -RT_ENOSYS;
-}
-
-static rt_err_t _i2c_bus_control(struct rt_i2c_bus_device *bus, rt_uint32_t cmd, rt_uint32_t arg)
-{
-    return -RT_EINVAL;
-}
-
-static const struct rt_i2c_bus_device_ops i2c_ops =
-{
-    _master_xfer,
-    _slave_xfer,
-    _i2c_bus_control,
-};
-
-int rt_hw_i2c_init(void)
-{
-    i2c0.base = &i2c0;
-    i2c0.device_name = "i2c0";
-    i2c0.bus.ops = &i2c_ops;
-    int i2c_master_port = I2C_MASTER_NUM;//iic0
-        i2c_config_t conf = {
-        .mode = I2C_MODE_MASTER,
-        .sda_io_num = I2C_MASTER_SDA_IO,
-        .sda_pullup_en = GPIO_PULLUP_ENABLE,
-        .scl_io_num = I2C_MASTER_SCL_IO,
-        .scl_pullup_en = GPIO_PULLUP_ENABLE,
-        .master.clk_speed = 100000,
-        // .clk_flags = 0,          /*!< Optional, you can use I2C_SCLK_SRC_FLAG_* flags to choose i2c source clock here. */
-    };
-
-    i2c_param_config(i2c_master_port, &conf);//配置完成
-    i2c_driver_install(i2c_master_port, conf.mode, 0, 0, 0);// I2C 设备的初始化
-    rt_i2c_bus_device_register(&i2c0.bus, i2c0.device_name);
-    return RT_EOK;
-}
-INIT_BOARD_EXPORT(rt_hw_i2c_init);
-#endif /* RT_USING_I2C */

bsp/ESP32_C3/drivers/drv_hw_i2c.h

@@ -1,32 +0,0 @@
-/*
- * Copyright (c) 2006-2023, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- *2023-03-28      Zxy          first version
- */
-#ifndef __DRV_HW_I2C_H__
-#define __DRV_HW_I2C_H__
-
-#include <rtthread.h>
-#include <rtdevice.h>
-#include "sdkconfig.h"
-
-#define WRITE_BIT I2C_MASTER_WRITE              /*!< I2C master write */
-#define READ_BIT I2C_MASTER_READ                /*!< I2C master read */
-#define ACK_CHECK_EN 0x1                        /*!< I2C master will check ack from slave*/
-#define ACK_CHECK_DIS 0x0                       /*!< I2C master will not check ack from slave */
-#define ACK_VAL 0x0                             /*!< I2C ack value */
-#define NACK_VAL 0x1                            /*!< I2C nack value */
-#define _I2C_NUMBER(num) I2C_NUM_##num
-#define I2C_NUMBER(num) _I2C_NUMBER(num)
-#define I2C_MASTER_NUM I2C_NUMBER(0) /*!< I2C port number for master dev */
-#define I2C_MASTER_SCL_IO CONFIG_I2C_MASTER_SCL               /*!< gpio number for I2C master clock */
-#define I2C_MASTER_SDA_IO CONFIG_I2C_MASTER_SDA               /*!< gpio number for I2C master data  */
-#define CONFIG_I2C_MASTER_SCL 6
-#define CONFIG_I2C_MASTER_SDA 5
-int rt_hw_i2c_init(void);
-
-#endif /* __DRV_HW_I2C_H__ */

bsp/ESP32_C3/rtconfig.h

@@ -29,7 +29,6 @@
 
 /* Memory Management */
 
-#define RT_PAGE_MAX_ORDER 11
 #define RT_USING_MEMPOOL
 #define RT_USING_SMALL_MEM
 #define RT_USING_SMALL_MEM_AS_HEAP
@@ -66,7 +65,6 @@
 /* Device Drivers */
 
 #define RT_USING_DEVICE_IPC
-#define RT_UNAMED_PIPE_NUMBER 64
 #define RT_USING_SERIAL
 #define RT_USING_SERIAL_V1
 #define RT_SERIAL_RB_BUFSZ 64
@@ -132,6 +130,9 @@
 /* u8g2: a monochrome graphic library */
 
 
+/* PainterEngine: A cross-platform graphics application framework written in C language */
+
+
 /* tools packages */
 
 
@@ -153,11 +154,6 @@
 
 /* peripheral libraries and drivers */
 
-/* sensors drivers */
-
-
-/* touch drivers */
-
 #define PKG_USING_ESP_IDF
 #define PKG_USING_ESP_IDF_LATEST_VERSION
 
@@ -167,9 +163,6 @@
 /* AI packages */
 
 
-/* Signal Processing and Control Algorithm Packages */
-
-
 /* miscellaneous packages */
 
 /* project laboratory */
@@ -202,13 +195,10 @@
 
 /* Communication */
 
-
 /* Device Control */
 
-
 /* Other */
 
-
 /* Signal IO */
 
 

bsp/ESP32_C3/rtt.patch

@@ -113,7 +113,6 @@ index d6670bf759..1d51ffeea0 100644
 +      __stack_cpu0 = .;
 +      __stack_end__ = .;
 +  } > dram0_0_seg
-+  PROVIDE( __rt_rvstack = __stack_end__);
 +
 +  .heap :
 +  {

bsp/Infineon/docs/PSOC6系列BSP制作教程.md

@@ -119,64 +119,14 @@ Modus 生成的源库文件路径如下图，在 Modus 工作空间下的 `mtb_s
 
 ![](./figures/hal_config1.png)
 
-接下来需要添加板级配置文件，接下来介绍使用英飞凌官方以及非官方开发板的添加步骤：
+同时下载 [TARGET_CY8CKIT-062S2-43012](https://github.com/Infineon/TARGET_CY8CKIT-062S2-43012/releases)  **V3.0.0** 发行版本（需根据不同芯片型号下载），至具体 BSP 的 libs 文件夹下。
 
-1、**英飞凌官方开发板步骤**
+![](./figures/hal_config4.png)
 
-打开 `ModusToolbox` 软件(版本需 >=V3.0.0)，点击新建项目：
-
-![](./figures/ModusToolbox.png)
-
-输入开发板型号信息，然后选择下一步：
-
-![](./figures/ModusToolbox1.png)
-
-选择 `Hello World` 模板工程，接下来点击创建该工程：
-
-![](./figures/ModusToolbox2.png)
-
-值得注意的是，`APP_CY8CKIT-062S2-43012` 这个 bsp 需要为 4.1.0 版本：
-
-![](./figures/ModusToolbox2.2.png)
-
-等待下载完成后，打开对应的 BSP 文件夹，找到 bsps 下生成的文件：
-
-![](./figures/ModusToolbox3.png)
-
-拷贝其中的内容到 RT-Thread 具体 BSP 的 libs文件夹下，例如下图：
+下载至具体 BSP 的 libs 文件夹下，例如下图：
 
 ![](./figures/hal_config4-1.png)
 
-同时按照具体路径配置 `SConscript` 脚本文件。
-
-2、**非英飞凌官方开发板步骤**
-
-首先找到 ModusToolbox 安装路径下 `BSP Assistant` 这个软件：
-
-![](./figures/ModusToolbox4.png)
-
-点击 File->New 进行新建项目，按照下图选择目标芯片等：
-
-![](./figures/ModusToolbox5.png)
-
-点击 `Device Configurator 4.0` 后进入图形化配置界面进行外设配置：
-
-![](./figures/ModusToolbox6.png)
-
-引脚部分，swd 的引脚配置是必须的，保持默认即可
-
-![](./figures/ModusToolbox7.png)
-
-时钟相关配置，最初保持默认即可：
-
-![](./figures/ModusToolbox8.png)
-
-全部都配置好后，在界面中按 `ctrl+s ` 即可自动生成配置文件，然后拷贝其中的内容到 RT-Thread 具体 BSP 的 libs文件夹下，例如下图：
-
-![](./figures/hal_config4-1.png)
-
-同时按照具体路径配置 `SConscript` 脚本文件。
-
 ### 3.5 修改工程构建相关文件
 
 接下来需要修改用于构建工程相关的文件。

bsp/Infineon/libraries/HAL_Drivers/SConscript

@@ -29,9 +29,6 @@ if GetDepend(['RT_USING_I2C']):
 if GetDepend(['BSP_USING_SDIO1']):
     src += Glob('drv_sdio.c')
 
-if GetDepend(['BSP_USING_SDCARD']):
-    src += Glob('drv_sdcard.c')
-
 if GetDepend(['BSP_USING_PWM']):
     src += ['drv_pwm.c']
 

bsp/Infineon/libraries/HAL_Drivers/drv_adc.c

@@ -57,7 +57,7 @@ static rt_err_t ifx_adc_enabled(struct rt_adc_device *device, rt_uint32_t channe
 
         if (result != RT_EOK)
         {
-            LOG_E("ADC initialization failed. Error: %u\n", result);
+            LOG_E("ADC initialization failed. Error: %ld\n", (long unsigned int)result);
             return -RT_ENOSYS;
         }
 
@@ -67,7 +67,7 @@ static rt_err_t ifx_adc_enabled(struct rt_adc_device *device, rt_uint32_t channe
 
         if (result != RT_EOK)
         {
-            LOG_E("ADC single ended channel initialization failed. Error: %u\n", result);
+            LOG_E("ADC single ended channel initialization failed. Error: %ld\n", (long unsigned int)result);
             return -RT_ENOSYS;
         }
 
@@ -76,7 +76,7 @@ static rt_err_t ifx_adc_enabled(struct rt_adc_device *device, rt_uint32_t channe
 
         if (result != RT_EOK)
         {
-            printf("ADC configuration update failed. Error: %u\n", result);
+            printf("ADC configuration update failed. Error: %ld\n", (long unsigned int)result);
             return -RT_ENOSYS;
         }
     }

bsp/Infineon/libraries/HAL_Drivers/drv_gpio.c

@@ -19,8 +19,6 @@
 
 #define PIN_IFXPORT_MAX     __IFX_PORT_MAX
 
-static cyhal_gpio_callback_data_t irq_cb_data[PIN_IFXPORT_MAX];
-
 static const struct pin_irq_map pin_irq_map[] =
 {
     {CYHAL_PORT_0,  ioss_interrupts_gpio_0_IRQn},
@@ -68,8 +66,6 @@ static struct rt_pin_irq_hdr pin_irq_handler_tab[] =
 
 rt_inline void pin_irq_handler(int irqno)
 {
-    Cy_GPIO_ClearInterrupt(CYHAL_GET_PORTADDR(irqno), CYHAL_GET_PIN(irqno));
-
     if (pin_irq_handler_tab[irqno].hdr)
     {
         pin_irq_handler_tab[irqno].hdr(pin_irq_handler_tab[irqno].args);
@@ -97,7 +93,9 @@ static void irq_callback(void *callback_arg, cyhal_gpio_event_t event)
     rt_interrupt_leave();
 }
 
-static void ifx_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
+cyhal_gpio_callback_data_t irq_cb_data;
+
+static void ifx_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
 {
     rt_uint16_t gpio_pin;
 
@@ -134,7 +132,7 @@ static void ifx_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
     }
 }
 
-static void ifx_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
+static void ifx_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
 {
     rt_uint16_t gpio_pin;
 
@@ -150,7 +148,7 @@ static void ifx_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
     cyhal_gpio_write(gpio_pin, value);
 }
 
-static rt_int8_t ifx_pin_read(struct rt_device *device, rt_base_t pin)
+static int ifx_pin_read(rt_device_t dev, rt_base_t pin)
 {
     rt_uint16_t gpio_pin;
 
@@ -166,8 +164,8 @@ static rt_int8_t ifx_pin_read(struct rt_device *device, rt_base_t pin)
     return cyhal_gpio_read(gpio_pin);
 }
 
-static rt_err_t ifx_pin_attach_irq(struct rt_device *device, rt_base_t pin,
-                                   rt_uint8_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t ifx_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                                   rt_uint32_t mode, void (*hdr)(void *args), void *args)
 {
     rt_uint16_t gpio_port;
     rt_uint16_t gpio_pin;
@@ -197,7 +195,7 @@ static rt_err_t ifx_pin_attach_irq(struct rt_device *device, rt_base_t pin,
     if (pin_irq_handler_tab[gpio_port].pin != -1)
     {
         rt_hw_interrupt_enable(level);
-        return -RT_EBUSY;
+        return RT_EBUSY;
     }
 
     pin_irq_handler_tab[gpio_port].pin = pin;
@@ -209,7 +207,7 @@ static rt_err_t ifx_pin_attach_irq(struct rt_device *device, rt_base_t pin,
     return RT_EOK;
 }
 
-static rt_err_t ifx_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
+static rt_err_t ifx_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
 {
     rt_uint16_t gpio_port;
     rt_uint16_t gpio_pin;
@@ -243,12 +241,13 @@ static rt_err_t ifx_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
 }
 
 static rt_err_t ifx_pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                                   rt_uint8_t enabled)
+                                   rt_uint32_t enabled)
 {
     rt_uint16_t gpio_port;
     rt_uint16_t gpio_pin;
     rt_base_t level;
     rt_uint8_t pin_irq_mode;
+
     const struct pin_irq_map *irqmap;
 
     if (PORT_GET(pin) < PIN_IFXPORT_MAX)
@@ -273,13 +272,10 @@ static rt_err_t ifx_pin_irq_enable(struct rt_device *device, rt_base_t pin,
 
         irqmap = &pin_irq_map[gpio_port];
 
-#if !defined(COMPONENT_CAT1C)
-        IRQn_Type irqn = (IRQn_Type)(irqmap->irqno + PORT_GET(irqmap->port));
-#endif
-        irq_cb_data[irqn].callback = irq_callback;
-        irq_cb_data[irqn].callback_arg = (rt_uint16_t *)&pin_irq_map[gpio_port].port;
+        irq_cb_data.callback = irq_callback;
+        irq_cb_data.callback_arg = (rt_uint16_t *)&pin_irq_map[gpio_port].port;
 
-        cyhal_gpio_register_callback(gpio_pin, &irq_cb_data[irqn]);
+        cyhal_gpio_register_callback(gpio_pin, &irq_cb_data);
 
         Cy_GPIO_ClearInterrupt(CYHAL_GET_PORTADDR(gpio_pin), CYHAL_GET_PIN(gpio_pin));
 

bsp/Infineon/libraries/HAL_Drivers/drv_gpio.h

@@ -14,7 +14,8 @@
 #include <rthw.h>
 #include <rtdevice.h>
 #include "drv_common.h"
-#include "cyhal_irq_impl.h"
+
+#include "cyhal_irq_psoc.h"
 
 #define GPIO_INTERRUPT_PRIORITY (7u)
 

bsp/Infineon/libraries/HAL_Drivers/drv_hwtimer.c

@@ -198,7 +198,7 @@ static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
         if (result != CY_RSLT_SUCCESS)
         {
             LOG_E("cyhal_timer_set_frequency error\r\n");
-            return -RT_ERROR;
+            return RT_ERROR;
         }
     }
     break;
@@ -301,7 +301,7 @@ int hwtimer_sample()
     if (hw_dev == RT_NULL)
     {
         rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME);
-        return -RT_ERROR;
+        return RT_ERROR;
     }
 
     ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR);
@@ -329,7 +329,7 @@ int hwtimer_sample()
     if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s))
     {
         rt_kprintf("set timeout value failed\n");
-        return -RT_ERROR;
+        return RT_ERROR;
     }
 
     while (1)

bsp/Infineon/libraries/HAL_Drivers/drv_pwm.c

@@ -31,8 +31,8 @@ struct ifx_pwm
 
 static struct ifx_pwm ifx_pwm_obj[] =
 {
-#ifdef BSP_USING_PWM0_PORT0
-    PWM0_CH0_PORT0_CONFIG,
+#ifdef BSP_USING_PWM0_PORT13
+    PWM0_CH3_PORT13_CONFIG,
 #endif
 
 #ifdef BSP_USING_PWM0_PORT2
@@ -58,10 +58,6 @@ static struct ifx_pwm ifx_pwm_obj[] =
 #ifdef BSP_USING_PWM0_PORT12
     PWM0_CH7_PORT12_CONFIG,
 #endif
-
-#ifdef BSP_USING_PWM0_PORT13
-    PWM0_CH3_PORT13_CONFIG,
-#endif
 };
 
 static rt_err_t drv_pwm_enable(cyhal_pwm_t *htim, struct rt_pwm_configuration *configuration, rt_bool_t enable)
@@ -157,7 +153,7 @@ static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg
         return drv_pwm_get(htim, configuration);
 
     default:
-        return -RT_EINVAL;
+        return RT_EINVAL;
     }
 }
 
@@ -169,13 +165,26 @@ static rt_err_t ifx_hw_pwm_init(struct ifx_pwm *device)
 
     RT_ASSERT(device != RT_NULL);
 
-    if (cyhal_pwm_init_adv(device->pwm_obj, device->gpio, NC, CYHAL_PWM_LEFT_ALIGN, true, 0u, false, RT_NULL) != RT_EOK)
+    /* config pwm channel */
+    if (device->channel == 0x03)
     {
-        LOG_E("%s channel%d config failed", device->name, device->channel);
-        result = -RT_ERROR;
-        goto __exit;
+        if (cyhal_pwm_init_adv(device->pwm_obj, device->gpio, NC, CYHAL_PWM_LEFT_ALIGN, true, 0u, false, RT_NULL) != RT_EOK)
+        {
+            LOG_E("%s channel3 config failed", device->name);
+            result = -RT_ERROR;
+            goto __exit;
+        }
+    }
+    /* config pwm channel */
+    if (device->channel == 0x07)
+    {
+        if (cyhal_pwm_init_adv(device->pwm_obj, device->gpio, NC, CYHAL_PWM_LEFT_ALIGN, true, 0u, false, RT_NULL) != RT_EOK)
+        {
+            LOG_E("%s channel7 config failed", device->name);
+            result = -RT_ERROR;
+            goto __exit;
+        }
     }
-
 __exit:
     return result;
 }
@@ -234,7 +243,7 @@ static int pwm_sample(int argc, char *argv[])
     if (pwm_dev == RT_NULL)
     {
         rt_kprintf("pwm sample run failed! can't find %s device!\n", PWM_DEV_NAME);
-        return -RT_ERROR;
+        return RT_ERROR;
     }
 
     rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse);

bsp/Infineon/libraries/HAL_Drivers/drv_pwm.h

@@ -22,12 +22,12 @@ extern "C"
 #define MAX_PERIOD 65535
 
 #ifdef BSP_USING_PWM0
-#ifndef PWM0_CH0_PORT0_CONFIG
-#define PWM0_CH0_PORT0_CONFIG       \
+#ifndef PWM0_CH3_PORT13_CONFIG
+#define PWM0_CH3_PORT13_CONFIG      \
     {                               \
         .name = "pwm0",             \
-        .channel = 0,               \
-        .gpio = GET_PIN(0, 0),      \
+        .channel = 3,               \
+        .gpio = GET_PIN(13, 7),     \
     }
 #endif /* PWM0_CH7_PORT2_CONFIG */
 
@@ -84,15 +84,6 @@ extern "C"
         .gpio = GET_PIN(12, 6),     \
     }
 #endif /* PWM0_CH7_PORT12_CONFIG */
-
-#ifndef PWM0_CH3_PORT13_CONFIG
-#define PWM0_CH3_PORT13_CONFIG      \
-    {                               \
-        .name = "pwm0",             \
-        .channel = 3,               \
-        .gpio = GET_PIN(13, 7),     \
-    }
-#endif /* PWM0_CH3_PORT13_CONFIG */
 #endif /* BSP_USING_PWM0 */
 
 #ifdef __cplusplus

bsp/Infineon/libraries/HAL_Drivers/drv_rtc.c

@@ -153,7 +153,7 @@ static int rt_hw_rtc_init(void)
     if (rt_hw_rtc_register(&ifx32_rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR, RT_NULL) != RT_EOK)
     {
         LOG_E("rtc init failed");
-        result = -RT_ERROR;
+        result = RT_ERROR;
     }
     else
     {

bsp/Infineon/libraries/HAL_Drivers/drv_sdcard.c

@@ -1,360 +0,0 @@
-/*
- * Copyright (c) 2006-2023, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2023-05-05     vandoul      first
- */
-
-#include <rtthread.h>
-#include "cy_gpio.h"
-#include "cyhal_gpio.h"
-#include "cyhal_sdhc.h"
-
-#ifdef BSP_USING_SDCARD
-
-//#define DRV_DEBUG
-#define LOG_TAG             "drv.sdio"
-#include <drv_log.h>
-
-#define SDIO_BLOCK_SIZE                         (512)
-
-#if BSP_USING_SDCARD_LED_CTRL_ENANBLE
-#define SDCARD_LED_CTRL_ENABLE           true
-#else
-#define SDCARD_LED_CTRL_ENABLE           false
-#endif
-#if BSP_USING_SDCARD_EMMC_ENANBLE
-#define SDCARD_EMMC_ENABLE           true
-#else
-#define SDCARD_EMMC_ENABLE           false
-#endif
-
-struct _cy_sdio_pin_and_name_config
-{
-    const char *name;
-    cyhal_gpio_t cmd;               /**< The pin connected to the command signal. */
-    cyhal_gpio_t clk;               /**< The pin connected to the clock signal. */
-    cyhal_gpio_t data0;             /**< The pin connected to the data0 signal. */
-    cyhal_gpio_t data1;             /**< The pin connected to the data1 signal. */
-    cyhal_gpio_t data2;             /**< The pin connected to the data2 signal. */
-    cyhal_gpio_t data3;             /**< The pin connected to the data3 signal. */
-    cyhal_gpio_t data4;             /**< The pin connected to the data4 signal; pass NC when unused. */
-    cyhal_gpio_t data5;             /**< The pin connected to the data5 signal; pass NC when unused. */
-    cyhal_gpio_t data6;             /**< The pin connected to the data6 signal; pass NC when unused. */
-    cyhal_gpio_t data7;             /**< The pin connected to the data7 signal; pass NC when unused. */
-    cyhal_gpio_t card_detect;       /**< The pin connected to the card detect signal. */
-    cyhal_gpio_t io_volt_sel;       /**< The pin connected to the voltage select signal. */
-    cyhal_gpio_t card_if_pwr_en;    /**< The pin connected to the card interface power enable signal. */
-    cyhal_gpio_t card_mech_write_prot; /**< The pin connected to the write protect signal. */
-    cyhal_gpio_t led_ctrl;          /**< The pin connected to the LED control signal. */
-    cyhal_gpio_t card_emmc_reset;   /**< The pin connected to the eMMC card reset signal. */
-};
-
-static const struct _cy_sdio_pin_and_name_config _sdcard_config =
-{
-    .name = "sd0",
-    .cmd                  = BSP_USING_SDCARD_CMD_PIN,
-    .clk                  = BSP_USING_SDCARD_CLK_PIN,
-    .data0                = BSP_USING_SDCARD_DAT0_PIN,
-    .data1                = BSP_USING_SDCARD_DAT1_PIN,
-    .data2                = BSP_USING_SDCARD_DAT2_PIN,
-    .data3                = BSP_USING_SDCARD_DAT3_PIN,
-    .data4                = BSP_USING_SDCARD_DAT4_PIN,
-    .data5                = BSP_USING_SDCARD_DAT5_PIN,
-    .data6                = BSP_USING_SDCARD_DAT6_PIN,
-    .data7                = BSP_USING_SDCARD_DAT7_PIN,
-    .card_detect          = BSP_USING_SDCARD_DETECT_PIN,
-    .io_volt_sel          = BSP_USING_SDCARD_IO_VOLT_SEL_PIN,
-    .card_if_pwr_en       = BSP_USING_SDCARD_CARD_IF_PWR_EN_PIN,
-    .card_mech_write_prot = BSP_USING_SDCARD_CARD_MECH_WRITE_PROT_PIN,
-    #if BSP_USING_SDCARD_LED_CTRL_PIN
-    .led_ctrl             = BSP_USING_SDCARD_LED_CTRL_PIN,
-    #else
-    .led_ctrl             = -1,
-    #endif
-    .card_emmc_reset      = BSP_USING_SDCARD_CARD_EMMC_RESET_PIN,
-};
-
-#include <dfs_fs.h>
-#include <drivers/mmcsd_core.h>
-#include <drivers/gpt.h>
-struct rthw_sdio
-{
-    struct rt_device parent;
-    cyhal_sdhc_t sdhc_obj; /**< Object for use with the SDHC HAL driver. */
-    cyhal_sdhc_config_t sdhc_config; /**< Card configuration structure to be passed to the HAL driver. */
-    const struct _cy_sdio_pin_config *pins_cfg;
-    struct dfs_partition part;
-    struct rt_device_blk_geometry geometry;
-};
-static rt_err_t rt_mmcsd_init(rt_device_t dev)
-{
-    return RT_EOK;
-}
-
-static rt_err_t rt_mmcsd_open(rt_device_t dev, rt_uint16_t oflag)
-{
-    return RT_EOK;
-}
-
-static rt_err_t rt_mmcsd_close(rt_device_t dev)
-{
-    return RT_EOK;
-}
-
-static rt_err_t rt_mmcsd_control(rt_device_t dev, int cmd, void *args)
-{
-    struct rthw_sdio *sdio = (struct rthw_sdio *)dev;
-    struct dfs_partition *part = &sdio->part;
-    struct rt_device_blk_geometry *geometry = &sdio->geometry;
-    struct mmcsd_blk_device *blk_dev = (struct mmcsd_blk_device *)dev->user_data;
-    switch (cmd)
-    {
-    case RT_DEVICE_CTRL_BLK_GETGEOME:
-        rt_memcpy(args, geometry, sizeof(struct rt_device_blk_geometry));
-        break;
-    case RT_DEVICE_CTRL_BLK_PARTITION:
-        rt_memcpy(args, part, sizeof(struct dfs_partition));
-    default:
-        break;
-    }
-    return RT_EOK;
-}
-
-static rt_ssize_t rt_mmcsd_read(rt_device_t dev,
-                               rt_off_t    pos,
-                               void       *buffer,
-                               rt_size_t   size)
-{
-    rt_err_t err = 0;
-    void *rd_ptr = (void *)buffer;
-    struct rthw_sdio *sdio = (struct rthw_sdio *)dev;
-    cyhal_sdhc_t *hw_sdio = &sdio->sdhc_obj;
-    off_t offset = sdio->part.offset;
-
-    LOG_D("mmc read: off:%d pos:%d size:%d", offset, pos, size);
-    if (dev == RT_NULL)
-    {
-        rt_set_errno(-RT_EINVAL);
-        return 0;
-    }
-
-    rt_sem_take(sdio->part.lock, RT_WAITING_FOREVER);
-    do {
-        size_t block_count =  size;
-        uint32_t addr = (offset + pos);
-        cy_rslt_t result = cyhal_sdhc_read_async(hw_sdio, addr, buffer, &block_count);
-        if(CY_RSLT_SUCCESS != result)
-        {
-            err = -RT_ERROR;
-            break;
-        }
-        /* Waits on a semaphore until the transfer completes, when RTOS_AWARE component is defined. */
-        result = cyhal_sdhc_wait_transfer_complete(hw_sdio);
-        if(CY_RSLT_SUCCESS != result)
-        {
-            err = -RT_ERROR;
-            break;
-        }
-    }while(0);
-    rt_sem_release(sdio->part.lock);
-
-    /* the length of reading must align to SECTOR SIZE */
-    if (err)
-    {
-        rt_set_errno(-RT_EIO);
-        return 0;
-    }
-    return size;
-}
-
-static rt_ssize_t rt_mmcsd_write(rt_device_t dev,
-                                rt_off_t    pos,
-                                const void *buffer,
-                                rt_size_t   size)
-{
-    rt_err_t err = 0;
-    void *rd_ptr = (void *)buffer;
-    struct rthw_sdio *sdio = (struct rthw_sdio *)dev;
-    cyhal_sdhc_t *hw_sdio = &sdio->sdhc_obj;
-    off_t offset = sdio->part.offset;
-
-    LOG_D("mmc write: off:%d pos:%d size:%d", offset, pos, size);
-    if (dev == RT_NULL)
-    {
-        rt_set_errno(-RT_EINVAL);
-        return 0;
-    }
-
-    rt_sem_take(sdio->part.lock, RT_WAITING_FOREVER);
-    do {
-        size_t block_count =  size ;
-        uint32_t addr = (offset + pos);
-        cy_rslt_t result = cyhal_sdhc_write_async(hw_sdio, addr, buffer, &block_count);
-        if(CY_RSLT_SUCCESS != result)
-        {
-            err = -RT_ERROR;
-            break;
-        }
-        /* Waits on a semaphore until the transfer completes, when RTOS_AWARE component is defined. */
-        result = cyhal_sdhc_wait_transfer_complete(hw_sdio);
-        if(CY_RSLT_SUCCESS != result)
-        {
-            err = -RT_ERROR;
-            break;
-        }
-    }while(0);
-    rt_sem_release(sdio->part.lock);
-
-    /* the length of reading must align to SECTOR SIZE */
-    if (err)
-    {
-        rt_set_errno(-RT_EIO);
-        return 0;
-    }
-    return size;
-}
-#ifdef RT_USING_DEVICE_OPS
-const static struct rt_device_ops mmcsd_blk_ops =
-{
-    rt_mmcsd_init,
-    rt_mmcsd_open,
-    rt_mmcsd_close,
-    rt_mmcsd_read,
-    rt_mmcsd_write,
-    rt_mmcsd_control
-};
-#endif
-int rt_hw_sdio_init(void)
-{
-    struct rthw_sdio *sdio = RT_NULL;
-    struct _cy_sdio_pin_config *pins_cfg;
-    char sname[16];
-
-    sdio = rt_malloc(sizeof(struct rthw_sdio));
-    if (sdio == RT_NULL)
-    {
-        LOG_E("malloc rthw_sdio fail");
-        return RT_NULL;
-    }
-    rt_memset(sdio, 0, sizeof(struct rthw_sdio));
-
-    LOG_D("sdio pins: cmd=%d,clk=%d,d0=%d,d1=%d,d2=%d,d3=%d,d4=%d,d5=%d,d6=%d,d7=%d",
-        _sdio1_pins_and_name.cmd,   _sdio1_pins_and_name.clk,
-        _sdio1_pins_and_name.data0, _sdio1_pins_and_name.data1, _sdio1_pins_and_name.data2, _sdio1_pins_and_name.data3,
-        _sdio1_pins_and_name.data4, _sdio1_pins_and_name.data5, _sdio1_pins_and_name.data6, _sdio1_pins_and_name.data7
-    );
-    LOG_D("\tdetect=%d,volt_sel=%d,pwr_en=%d,write_prot=%d,led_ctrl=%d,emmc_reset=%d",
-        _sdio1_pins_and_name.card_detect,          _sdio1_pins_and_name.io_volt_sel, _sdio1_pins_and_name.card_if_pwr_en,
-        _sdio1_pins_and_name.card_mech_write_prot, _sdio1_pins_and_name.led_ctrl,    _sdio1_pins_and_name.card_emmc_reset
-    );
-    /* register mmcsd device */
-    sdio->parent.type  = RT_Device_Class_Block;
-#ifdef RT_USING_DEVICE_OPS
-    sdio->parent.ops  = &mmcsd_blk_ops;
-#else
-    sdio->parent.init = rt_mmcsd_init;
-    sdio->parent.open = rt_mmcsd_open;
-    sdio->parent.close = rt_mmcsd_close;
-    sdio->parent.read = rt_mmcsd_read;
-    sdio->parent.write = rt_mmcsd_write;
-    sdio->parent.control = rt_mmcsd_control;
-#endif
-
-    do {
-        sdio->sdhc_config.enableLedControl = SDCARD_LED_CTRL_ENABLE;
-        sdio->sdhc_config.isEmmc = SDCARD_EMMC_ENABLE;
-        sdio->sdhc_config.lowVoltageSignaling = false;
-        sdio->sdhc_config.busWidth = BSP_USING_SDCARD_BUS_WIDTH;
-        /* Initialize the SD Card interface. */
-        int rslt = cyhal_sdhc_init_hw(&sdio->sdhc_obj, &sdio->sdhc_config, _sdcard_config.cmd,   _sdcard_config.clk,
-                                 _sdcard_config.data0,  _sdcard_config.data1, _sdcard_config.data2, _sdcard_config.data3,
-                                 _sdcard_config.data4,  _sdcard_config.data5, _sdcard_config.data6, _sdcard_config.data7,
-                                 _sdcard_config.card_detect, _sdcard_config.io_volt_sel, _sdcard_config.card_if_pwr_en,
-                                 _sdcard_config.card_mech_write_prot, _sdcard_config.led_ctrl, _sdcard_config.card_emmc_reset, RT_NULL);
-        if(rslt != CY_RSLT_SUCCESS)
-        {
-            LOG_E("sdhc hw init fail: (0x%x)", rslt);
-            break;
-        }
-
-        rslt = cyhal_sdhc_init_card(&sdio->sdhc_obj);
-        if(rslt != CY_RSLT_SUCCESS)
-        {
-            LOG_E("sdhc init fail: (0x%x)", rslt);
-            break;
-        }
-
-        rt_uint32_t block_count;
-        rslt = cyhal_sdhc_get_block_count(&sdio->sdhc_obj, &block_count);
-        if(rslt != CY_RSLT_SUCCESS)
-        {
-            LOG_E("get block count fail: (0x%x)", rslt);
-            break;
-        }
-        LOG_D("block count:%d(0x%x)", block_count, block_count);
-
-        sdio->geometry.bytes_per_sector = 512;
-        sdio->geometry.block_size = 512;
-        sdio->geometry.sector_count = block_count;
-
-        rt_snprintf(sname, sizeof(sname) - 1, "sem_%s%d", _sdcard_config.name, 0);
-        sdio->part.lock = rt_sem_create(sname, 1, RT_IPC_FLAG_FIFO);
-        if(sdio->part.lock == RT_NULL)
-        {
-            LOG_E("create part.lock fail");
-            break;
-        }
-
-        rt_uint8_t *sector = rt_malloc(512);
-        if(sector == RT_NULL)
-        {
-            LOG_E("malloc sector fail");
-            break;
-        }
-        if(rt_mmcsd_read(&sdio->parent, 0, sector, 1) < 0)
-        {
-            LOG_E("rt_mmcsd_read fail");
-            rt_free(sector);
-            break;
-        }
-        rslt = dfs_filesystem_get_partition(&sdio->part, sector, 0);
-        rt_free(sector);
-        if(rslt != RT_EOK)
-        {
-            LOG_E("partition not found!");
-            break;
-        }
-
-        rslt = rt_device_register(&(sdio->parent), _sdcard_config.name,
-                       RT_DEVICE_FLAG_RDWR);
-
-        if(rslt != RT_EOK)
-        {
-            LOG_E("register device fail!");
-            break;
-        }
-
-        return RT_EOK;
-
-    }while(0);
-
-    if(sdio)
-    {
-        cyhal_sdhc_free(&sdio->sdhc_obj);
-        if(sdio->part.lock)
-        {
-            rt_sem_delete(sdio->part.lock);
-        }
-        rt_free(sdio);
-    }
-
-    return -RT_ERROR;
-}
-INIT_DEVICE_EXPORT(rt_hw_sdio_init);
-
-#endif
-

bsp/Infineon/libraries/HAL_Drivers/drv_spi.c

@@ -6,7 +6,6 @@
  * Change Logs:
  * Date           Author       Notes
  * 2022-07-18     Rbb666       first version
- * 2023-03-30     Rbb666       update spi driver
  */
 
 #include <drv_spi.h>
@@ -22,49 +21,31 @@
 #endif /* DRV_DEBUG */
 #include <rtdbg.h>
 
-#ifdef BSP_USING_SPI0
-    static struct rt_spi_bus spi_bus0;
-#endif
+struct ifx_sw_spi_cs
+{
+    rt_uint32_t pin;
+};
+
 #ifdef BSP_USING_SPI3
     static struct rt_spi_bus spi_bus3;
 #endif
-#ifdef BSP_USING_SPI6
-    static struct rt_spi_bus spi_bus6;
-#endif
 
-static struct ifx_spi_handle spi_bus_obj[] =
+static struct ifx_spi spi_bus_obj[] =
 {
-#if defined(BSP_USING_SPI0)
-    {
-        .bus_name = "spi0",
-        .sck_pin = GET_PIN(0, 4),
-        .miso_pin = GET_PIN(0, 3),
-        .mosi_pin = GET_PIN(0, 2),
-    },
-#endif
-#if defined(BSP_USING_SPI3)
+    #ifdef BSP_USING_SPI3
     {
         .bus_name = "spi3",
+        .spi_bus = &spi_bus3,
         .sck_pin = GET_PIN(6, 2),
         .miso_pin = GET_PIN(6, 1),
         .mosi_pin = GET_PIN(6, 0),
     },
-#endif
-#if defined(BSP_USING_SPI6)
-    {
-        .bus_name = "spi6",
-        .sck_pin = GET_PIN(12, 2),
-        .miso_pin = GET_PIN(12, 1),
-        .mosi_pin = GET_PIN(12, 0),
-    },
-#endif
+    #endif
 };
 
-static struct ifx_spi spi_config[sizeof(spi_bus_obj) / sizeof(spi_bus_obj[0])] = {0};
-
 /* private rt-thread spi ops function */
 static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration);
-static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message);
+static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message);
 
 static struct rt_spi_ops ifx_spi_ops =
 {
@@ -72,102 +53,68 @@ static struct rt_spi_ops ifx_spi_ops =
     .xfer = spixfer,
 };
 
-static void spi_interrupt_callback(void *arg, cyhal_spi_event_t event)
+static void ifx_spi_init(struct ifx_spi *ifx_spi)
 {
-    struct ifx_spi *spi_drv = (struct ifx_spi *)arg;
+    int result = RT_EOK;
 
-    rt_interrupt_enter();
+    result = cyhal_spi_init(ifx_spi->spi_obj, ifx_spi->mosi_pin, ifx_spi->miso_pin, ifx_spi->sck_pin,
+                            NC, NULL, ifx_spi->spi_obj->data_bits, ifx_spi->spi_obj->mode, false);
 
-    if ((event & CYHAL_SPI_IRQ_DONE) != 0u)
-    {
-        /* Transmission is complete. Handle Event */
-        rt_completion_done(&spi_drv->cpt);
-    }
+    RT_ASSERT(result != RT_ERROR);
 
-    rt_interrupt_leave();
-}
+    rt_kprintf("[%s] Freq:[%d]HZ\n", ifx_spi->bus_name, ifx_spi->freq);
 
-static void ifx_spi_init(struct ifx_spi *spi_device)
-{
-    RT_ASSERT(spi_device != RT_NULL);
+    result = cyhal_spi_set_frequency(ifx_spi->spi_obj, ifx_spi->freq);
 
-    rt_err_t result = RT_EOK;
-
-    static uint8_t init_flag = 1;
-
-    if (init_flag)
-    {
-        result = cyhal_spi_init(spi_device->spi_handle_t->spi_obj, spi_device->spi_handle_t->mosi_pin, spi_device->spi_handle_t->miso_pin,
-                                spi_device->spi_handle_t->sck_pin, NC, NULL, spi_device->spi_handle_t->spi_obj->data_bits,
-                                spi_device->spi_handle_t->spi_obj->mode, false);
-        if (result != RT_EOK)
-        {
-            LOG_E("spi%s init fail", spi_device->spi_handle_t->bus_name);
-            return;
-        }
-
-        result = cyhal_spi_set_frequency(spi_device->spi_handle_t->spi_obj, spi_device->spi_handle_t->freq);
-        if (result == CYHAL_SPI_RSLT_CLOCK_ERROR)
-        {
-            LOG_E("%s set frequency fail", spi_device->spi_handle_t->bus_name);
-            return;
-        }
-        LOG_I("[%s] freq:[%d]HZ\n", spi_device->spi_handle_t->bus_name, spi_device->spi_handle_t->freq);
-
-        /* Register a callback function to be called when the interrupt fires */
-        cyhal_spi_register_callback(spi_device->spi_handle_t->spi_obj, spi_interrupt_callback, spi_device);
-
-        /* Enable the events that will trigger the call back function */
-        cyhal_spi_enable_event(spi_device->spi_handle_t->spi_obj, CYHAL_SPI_IRQ_DONE, 4, true);
-    }
-
-    init_flag = 0;
+    RT_ASSERT(result != CYHAL_SPI_RSLT_CLOCK_ERROR);
 }
 
 static rt_err_t spi_configure(struct rt_spi_device *device,
                               struct rt_spi_configuration *configuration)
 {
+    struct rt_spi_bus *spi_bus = (struct rt_spi_bus *)device->bus;
+    struct ifx_spi *spi_device = (struct ifx_spi *)spi_bus->parent.user_data;
+
     RT_ASSERT(device != RT_NULL);
     RT_ASSERT(configuration != RT_NULL);
 
-    struct ifx_spi *spi_device = rt_container_of(device->bus, struct ifx_spi, spi_bus);
-
     /* data_width */
     if (configuration->data_width <= 8)
     {
-        spi_device->spi_handle_t->spi_obj->data_bits = 8;
+        spi_device->spi_obj->data_bits = 8;
     }
     else if (configuration->data_width <= 16)
     {
-        spi_device->spi_handle_t->spi_obj->data_bits = 16;
+        spi_device->spi_obj->data_bits = 16;
     }
     else
     {
-        return -RT_EIO;
+        return RT_EIO;
     }
 
     uint32_t max_hz;
     max_hz = configuration->max_hz;
-    spi_device->spi_handle_t->freq = max_hz;
+
+    spi_device->freq = max_hz;
 
     /* MSB or LSB */
     switch (configuration->mode & RT_SPI_MODE_3)
     {
-    case RT_SPI_MODE_0:
-        spi_device->spi_handle_t->spi_obj->mode = CYHAL_SPI_MODE_00_MSB;
-        break;
+        case RT_SPI_MODE_0:
+            spi_device->spi_obj->mode = CYHAL_SPI_MODE_00_MSB;
+            break;
 
-    case RT_SPI_MODE_1:
-        spi_device->spi_handle_t->spi_obj->mode = CYHAL_SPI_MODE_01_MSB;
-        break;
+        case RT_SPI_MODE_1:
+            spi_device->spi_obj->mode = CYHAL_SPI_MODE_01_MSB;
+            break;
 
-    case RT_SPI_MODE_2:
-        spi_device->spi_handle_t->spi_obj->mode = CYHAL_SPI_MODE_10_MSB;
-        break;
+        case RT_SPI_MODE_2:
+            spi_device->spi_obj->mode = CYHAL_SPI_MODE_10_MSB;
+            break;
 
-    case RT_SPI_MODE_3:
-        spi_device->spi_handle_t->spi_obj->mode = CYHAL_SPI_MODE_11_MSB;
-        break;
+        case RT_SPI_MODE_3:
+            spi_device->spi_obj->mode = CYHAL_SPI_MODE_11_MSB;
+            break;
     }
 
     ifx_spi_init(spi_device);
@@ -175,24 +122,21 @@ static rt_err_t spi_configure(struct rt_spi_device *device,
     return RT_EOK;
 }
 
-static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
+static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
 {
     RT_ASSERT(device != NULL);
     RT_ASSERT(message != NULL);
 
-    struct ifx_spi *spi_device = rt_container_of(device->bus, struct ifx_spi, spi_bus);
+    struct rt_spi_bus *spi_bus = (struct rt_spi_bus *)device->bus;
+    struct ifx_spi *spi_device = (struct ifx_spi *)spi_bus->parent.user_data;
+
+    struct rt_spi_configuration *config = &device->config;
+    struct ifx_sw_spi_cs *cs = device->parent.user_data;
 
     /* take CS */
-    if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE))
+    if (message->cs_take)
     {
-        if (device->config.mode & RT_SPI_CS_HIGH)
-        {
-            cyhal_gpio_write(device->cs_pin, PIN_HIGH);
-        }
-        else
-        {
-            cyhal_gpio_write(device->cs_pin, PIN_LOW);
-        }
+        cyhal_gpio_write(cs->pin, PIN_LOW);
         LOG_D("spi take cs\n");
     }
 
@@ -203,38 +147,32 @@ static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *m
         if (message->send_buf == RT_NULL && message->recv_buf != RT_NULL)
         {
             /**< receive message */
-            result = cyhal_spi_transfer(spi_device->spi_handle_t->spi_obj, RT_NULL, 0x00, message->recv_buf, message->length, 0x00);
+            result = cyhal_spi_transfer(spi_device->spi_obj, RT_NULL, 0x00, message->recv_buf, message->length, 0x00);
         }
         else if (message->send_buf != RT_NULL && message->recv_buf == RT_NULL)
         {
             /**< send message */
-            result = cyhal_spi_transfer(spi_device->spi_handle_t->spi_obj, message->send_buf, message->length, RT_NULL, 0x00, 0x00);
+            result = cyhal_spi_transfer(spi_device->spi_obj, message->send_buf, message->length, RT_NULL, 0x00, 0x00);
         }
         else if (message->send_buf != RT_NULL && message->recv_buf != RT_NULL)
         {
             /**< send and receive message */
-            result = cyhal_spi_transfer(spi_device->spi_handle_t->spi_obj, message->send_buf, message->length, message->recv_buf, message->length, 0x00);
+            result = cyhal_spi_transfer(spi_device->spi_obj, message->send_buf, message->length, message->recv_buf, message->length, 0x00);
         }
-
-        /* blocking the thread,and the other tasks can run */
-        rt_completion_wait(&spi_device->cpt, RT_WAITING_FOREVER);
     }
 
-    if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE))
+    if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS))
     {
         if (device->config.mode & RT_SPI_CS_HIGH)
-            cyhal_gpio_write(device->cs_pin, PIN_LOW);
+            cyhal_gpio_write(cs->pin, PIN_LOW);
         else
-            cyhal_gpio_write(device->cs_pin, PIN_HIGH);
+            cyhal_gpio_write(cs->pin, PIN_HIGH);
     }
 
     return message->length;
 }
 
-/**
-  * Attach the spi device to SPI bus, this function must be used after initialization.
-  */
-rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin)
+rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, uint16_t cs_gpio_pin)
 {
     RT_ASSERT(bus_name != RT_NULL);
     RT_ASSERT(device_name != RT_NULL);
@@ -242,19 +180,24 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name,
     rt_err_t result;
     struct rt_spi_device *spi_device;
 
-    /* attach the device to spi bus*/
+    /* attach the device to spi bus */
     spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
     RT_ASSERT(spi_device != RT_NULL);
+    struct ifx_sw_spi_cs *cs_pin = (struct ifx_sw_spi_cs *)rt_malloc(sizeof(struct ifx_sw_spi_cs));
+    RT_ASSERT(cs_pin != RT_NULL);
 
-    result = rt_spi_bus_attach_device_cspin(spi_device, device_name, bus_name, cs_pin, RT_NULL);
-    if (result != RT_EOK)
+    cs_pin->pin = cs_gpio_pin;
+
+    if (cs_pin->pin != 0x00)
     {
-        LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result);
+        /* initialize the cs pin & select the slave*/
+        cyhal_gpio_init(cs_pin->pin, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_STRONG, 1);
+        cyhal_gpio_write(cs_pin->pin, PIN_HIGH);
     }
 
-    RT_ASSERT(result == RT_EOK);
+    result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
 
-    LOG_D("%s attach to %s done", device_name, bus_name);
+    RT_ASSERT(spi_device != RT_NULL);
 
     return result;
 }
@@ -263,26 +206,23 @@ int rt_hw_spi_init(void)
 {
     int result = RT_EOK;
 
-    for (int spi_index = 0; spi_index < sizeof(spi_bus_obj) / sizeof(spi_bus_obj[0]); spi_index++)
+    for (int i = 0; i < sizeof(spi_bus_obj) / sizeof(spi_bus_obj[0]); i++)
     {
-        spi_bus_obj[spi_index].spi_obj = rt_malloc(sizeof(cyhal_spi_t));
-        RT_ASSERT(spi_bus_obj[spi_index].spi_obj != RT_NULL);
+        spi_bus_obj[i].spi_obj = rt_malloc(sizeof(cyhal_spi_t));
 
-        spi_config[spi_index].spi_handle_t = &spi_bus_obj[spi_index];
+        RT_ASSERT(spi_bus_obj[i].spi_obj != RT_NULL);
 
-        rt_err_t err = rt_spi_bus_register(&spi_config[spi_index].spi_bus, spi_bus_obj[spi_index].bus_name, &ifx_spi_ops);
-        if (RT_EOK != err)
-        {
-            LOG_E("%s bus register failed.", spi_config[spi_index].spi_handle_t->bus_name);
-            return -RT_ERROR;
-        }
+        spi_bus_obj[i].spi_bus->parent.user_data = (void *)&spi_bus_obj[i];
+
+        result = rt_spi_bus_register(spi_bus_obj[i].spi_bus, spi_bus_obj[i].bus_name, &ifx_spi_ops);
+
+        RT_ASSERT(result == RT_EOK);
+
+        LOG_D("%s bus init done", spi_bus_obj[i].bus_name);
 
         LOG_D("MOSI PIN:[%d], MISO PIN[%d], CLK PIN[%d]\n",
-              spi_bus_obj[spi_index].mosi_pin, spi_bus_obj[spi_index].miso_pin,
-              spi_bus_obj[spi_index].sck_pin);
-
-        /* initialize completion object */
-        rt_completion_init(&spi_config[spi_index].cpt);
+              spi_bus_obj[i].mosi_pin, spi_bus_obj[i].miso_pin,
+              spi_bus_obj[i].sck_pin);
     }
 
     return result;

bsp/Infineon/libraries/HAL_Drivers/drv_spi.h

@@ -16,9 +16,13 @@
 
 #include "drv_gpio.h"
 
-struct ifx_spi_handle
+#define SPI_FREQ_HZ         (10000000UL)
+
+/* gd32 spi dirver class */
+struct ifx_spi
 {
-    const char *bus_name;
+    char *bus_name;
+    struct rt_spi_bus *spi_bus;
     cyhal_spi_t *spi_obj;
 
     uint16_t sck_pin;
@@ -27,18 +31,6 @@ struct ifx_spi_handle
     uint32_t freq;
 };
 
-/* ifx spi dirver class */
-struct ifx_spi
-{
-    rt_uint32_t cs_pin;
-
-    struct ifx_spi_handle       *spi_handle_t;
-    struct rt_spi_configuration *rt_spi_cfg_t;
-    struct rt_spi_bus spi_bus;
-
-    struct rt_completion cpt;
-};
-
-rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin);
+rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, uint16_t cs_gpio_pin);
 
 #endif

bsp/Infineon/libraries/HAL_Drivers/drv_uart.c

@@ -34,9 +34,6 @@ enum
 #ifdef BSP_USING_UART5
     UART5_INDEX,
 #endif
-#ifdef BSP_USING_UART6
-    UART6_INDEX,
-#endif
 };
 
 static struct ifx_uart_config uart_config[] =
@@ -59,9 +56,6 @@ static struct ifx_uart_config uart_config[] =
 #ifdef BSP_USING_UART5
     UART5_CONFIG,
 #endif
-#ifdef BSP_USING_UART6
-    UART6_CONFIG,
-#endif
 };
 
 static struct ifx_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
@@ -160,19 +154,6 @@ void uart5_isr_callback(void)
 }
 #endif
 
-#ifdef BSP_USING_UART6
-/* UART5 Interrupt Hanlder */
-void uart6_isr_callback(void)
-{
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    uart_isr(&uart_obj[UART6_INDEX].serial);
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-#endif
 /*
  * UARTHS interface
  */
@@ -201,7 +182,7 @@ static rt_err_t ifx_configure(struct rt_serial_device *serial, struct serial_con
         result = cyhal_uart_set_baud(uart->config->uart_obj, cfg->baud_rate, NULL);
     }
 
-    RT_ASSERT(result == RT_EOK);
+    RT_ASSERT(result != RT_ERROR);
 
     return RT_EOK;
 }

bsp/Infineon/libraries/HAL_Drivers/drv_wdt.c

@@ -60,7 +60,7 @@ static rt_err_t wdt_control(rt_watchdog_t *wdt_device, int cmd, void *arg)
             /* Initialize the WDT */
             int result = cyhal_wdt_init(cfg->WDTx, (rt_uint32_t)timeout_ms);
             /* WDT initialization failed. Stop program execution */
-            RT_ASSERT(result == RT_EOK);
+            RT_ASSERT(result != RT_ERROR);
         }
         break;
 

bsp/Infineon/libraries/HAL_Drivers/uart_config.h

@@ -68,14 +68,6 @@ extern "C"
     };
 #endif
 
-#ifdef BSP_USING_UART6
-    /* UART6 device driver structure */
-    cy_stc_sysint_t UART6_SCB_IRQ_cfg =
-        {
-            .intrSrc = (IRQn_Type)scb_6_interrupt_IRQn,
-            .intrPriority = (7u),
-    };
-#endif
 #if defined(BSP_USING_UART0)
 #ifndef UART0_CONFIG
 #define UART0_CONFIG                            \
@@ -185,21 +177,6 @@ extern "C"
 #endif /* UART5_CONFIG */
 #endif /* BSP_USING_UART5 */
 
-#if defined(BSP_USING_UART6)
-#ifndef UART6_CONFIG
-#define UART6_CONFIG                            \
-    {                                           \
-        .name = "uart6",                        \
-        .tx_pin = P6_5,                         \
-        .rx_pin = P6_4,                         \
-        .usart_x = SCB6,                        \
-        .intrSrc = scb_6_interrupt_IRQn,        \
-        .userIsr = uart_isr_callback(uart6),    \
-        .UART_SCB_IRQ_cfg = &UART6_SCB_IRQ_cfg, \
-    }
-    void uart6_isr_callback(void);
-#endif /* UART6_CONFIG */
-#endif /* BSP_USING_UART6 */
 #ifdef __cplusplus
 }
 #endif

bsp/Infineon/libraries/IFX_PSOC6_HAL/SConscript

@@ -16,10 +16,10 @@ src = Split('''
             mtb-hal-cat1/source/cyhal_gpio.c
             mtb-hal-cat1/source/cyhal_scb_common.c
             mtb-hal-cat1/source/cyhal_interconnect.c
+            mtb-hal-cat1/source/cyhal_utils_psoc.c
             mtb-hal-cat1/source/cyhal_utils.c
             mtb-hal-cat1/source/cyhal_lptimer.c
-            mtb-hal-cat1/source/cyhal_utils_impl.c
-            mtb-hal-cat1/source/cyhal_irq_impl.c
+            mtb-hal-cat1/source/cyhal_irq_psoc.c
             mtb-pdl-cat1/drivers/source/cy_sysclk.c
             mtb-pdl-cat1/drivers/source/cy_systick.c
             mtb-pdl-cat1/drivers/source/cy_gpio.c

bsp/Infineon/libraries/IFX_PSOC6_HAL/capsense/.cyignore

@@ -1 +0,0 @@
-docs

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble.h

@@ -6,7 +6,7 @@
 *
 ********************************************************************************
 * \copyright
-* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
+* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 *
 * SPDX-License-Identifier: Apache-2.0

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.h

@@ -6,7 +6,7 @@
 *
 ********************************************************************************
 * \copyright
-* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
+* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 *
 * SPDX-License-Identifier: Apache-2.0

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages/cyhal_psoc6_01_116_bga_ble.h

@@ -6,7 +6,7 @@
 *
 ********************************************************************************
 * \copyright
-* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
+* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 *
 * SPDX-License-Identifier: Apache-2.0

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages/cyhal_psoc6_01_116_bga_usb.h

@@ -6,7 +6,7 @@
 *
 ********************************************************************************
 * \copyright
-* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
+* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 *
 * SPDX-License-Identifier: Apache-2.0

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages/cyhal_psoc6_01_124_bga.h

@@ -6,7 +6,7 @@
 *
 ********************************************************************************
 * \copyright
-* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
+* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 *
 * SPDX-License-Identifier: Apache-2.0

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages/cyhal_psoc6_01_124_bga_sip.h

@@ -6,7 +6,7 @@
 *
 ********************************************************************************
 * \copyright
-* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
+* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 *
 * SPDX-License-Identifier: Apache-2.0

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages/cyhal_psoc6_01_68_qfn_ble.h

@@ -6,7 +6,7 @@
 *
 ********************************************************************************
 * \copyright
-* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
+* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 *
 * SPDX-License-Identifier: Apache-2.0