forked from OSchip/UnityChipVerification
225 lines
15 KiB
Systemverilog
225 lines
15 KiB
Systemverilog
// Generated by CIRCT firtool-1.62.0
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// Standard header to adapt well known macros for register randomization.
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_MEM_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_MEM_INIT
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`endif // not def RANDOMIZE
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_REG_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_REG_INIT
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`endif // not def RANDOMIZE
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// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
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`ifndef RANDOM
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`define RANDOM $random
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`endif // not def RANDOM
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// Users can define INIT_RANDOM as general code that gets injected into the
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// initializer block for modules with registers.
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`ifndef INIT_RANDOM
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`define INIT_RANDOM
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`endif // not def INIT_RANDOM
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// If using random initialization, you can also define RANDOMIZE_DELAY to
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// customize the delay used, otherwise 0.002 is used.
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`ifndef RANDOMIZE_DELAY
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`define RANDOMIZE_DELAY 0.002
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`endif // not def RANDOMIZE_DELAY
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// Define INIT_RANDOM_PROLOG_ for use in our modules below.
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`ifndef INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE
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`ifdef VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
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`else // VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
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`endif // VERILATOR
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`else // RANDOMIZE
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`define INIT_RANDOM_PROLOG_
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`endif // RANDOMIZE
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`endif // not def INIT_RANDOM_PROLOG_
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// Include register initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_REG_
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`define ENABLE_INITIAL_REG_
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`endif // not def ENABLE_INITIAL_REG_
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`endif // not def SYNTHESIS
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// Include rmemory initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_MEM_
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`define ENABLE_INITIAL_MEM_
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`endif // not def ENABLE_INITIAL_MEM_
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`endif // not def SYNTHESIS
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module FoldedSRAMTemplate( // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7]
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input clock, // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7]
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input reset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7]
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output io_r_req_ready, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14]
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input io_r_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14]
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input [10:0] io_r_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14]
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output io_r_resp_data_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14]
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output io_r_resp_data_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14]
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input io_w_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14]
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input [10:0] io_w_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14]
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input io_w_req_bits_data_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14]
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input io_w_req_bits_data_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14]
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input [1:0] io_w_req_bits_waymask, // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14]
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input extra_reset // @[utility/src/main/scala/utility/SRAMTemplate.scala:237:44]
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);
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wire _array_io_r_resp_data_0; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21]
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wire _array_io_r_resp_data_1; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21]
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wire _array_io_r_resp_data_2; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21]
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wire _array_io_r_resp_data_3; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21]
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wire _array_io_r_resp_data_4; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21]
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wire _array_io_r_resp_data_5; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21]
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wire _array_io_r_resp_data_6; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21]
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wire _array_io_r_resp_data_7; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21]
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wire _array_io_r_resp_data_8; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21]
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wire _array_io_r_resp_data_9; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21]
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wire _array_io_r_resp_data_10; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21]
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wire _array_io_r_resp_data_11; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21]
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wire _array_io_r_resp_data_12; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21]
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wire _array_io_r_resp_data_13; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21]
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wire _array_io_r_resp_data_14; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21]
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wire _array_io_r_resp_data_15; // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21]
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reg [2:0] ridx; // @[utility/src/main/scala/utility/SRAMTemplate.scala:258:23]
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reg holdRidx_last_r; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22]
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reg [2:0] holdRidx_hold_data; // @[utility/src/main/scala/utility/Hold.scala:24:82]
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wire [2:0] holdRidx = holdRidx_last_r ? ridx : holdRidx_hold_data; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:258:23]
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reg holdRidx_last_r_1; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22]
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reg [2:0] holdRidx_hold_data_1; // @[utility/src/main/scala/utility/Hold.scala:24:82]
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wire [2:0] holdRidx_1 = holdRidx_last_r_1 ? ridx : holdRidx_hold_data_1; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:258:23]
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wire _wmask_T_3 = io_w_req_bits_setIdx[2:0] == 3'h0; // @[utility/src/main/scala/utility/SRAMTemplate.scala:275:54, :279:69]
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wire _wmask_T_9 = io_w_req_bits_setIdx[2:0] == 3'h1; // @[utility/src/main/scala/utility/SRAMTemplate.scala:275:54, :279:69]
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wire _wmask_T_15 = io_w_req_bits_setIdx[2:0] == 3'h2; // @[utility/src/main/scala/utility/SRAMTemplate.scala:275:54, :279:69]
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wire _wmask_T_21 = io_w_req_bits_setIdx[2:0] == 3'h3; // @[utility/src/main/scala/utility/SRAMTemplate.scala:275:54, :279:69]
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wire _wmask_T_27 = io_w_req_bits_setIdx[2:0] == 3'h4; // @[utility/src/main/scala/utility/SRAMTemplate.scala:275:54, :279:69]
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wire _wmask_T_33 = io_w_req_bits_setIdx[2:0] == 3'h5; // @[utility/src/main/scala/utility/SRAMTemplate.scala:275:54, :279:69]
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wire _wmask_T_39 = io_w_req_bits_setIdx[2:0] == 3'h6; // @[utility/src/main/scala/utility/SRAMTemplate.scala:275:54, :279:69]
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always @(posedge clock) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7]
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if (io_r_req_valid) // @[utility/src/main/scala/utility/SRAMTemplate.scala:233:14]
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ridx <= io_r_req_bits_setIdx[2:0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:258:{23,60}]
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if (holdRidx_last_r) // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22]
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holdRidx_hold_data <= ridx; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:258:23]
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if (holdRidx_last_r_1) // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22]
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holdRidx_hold_data_1 <= ridx; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:258:23]
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end // always @(posedge)
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always @(posedge clock or posedge reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7]
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if (reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7]
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holdRidx_last_r <= 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:227:7]
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holdRidx_last_r_1 <= 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:227:7]
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end
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else begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7]
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if (io_r_req_valid | holdRidx_last_r) // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:{22,40}]
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holdRidx_last_r <= io_r_req_valid; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22]
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if (io_r_req_valid | holdRidx_last_r_1) // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:{22,40}]
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holdRidx_last_r_1 <= io_r_req_valid; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22]
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end
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end // always @(posedge, posedge)
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`ifdef ENABLE_INITIAL_REG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7]
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`ifdef FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7]
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`FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7]
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`endif // FIRRTL_BEFORE_INITIAL
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logic [31:0] _RANDOM[0:0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7]
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initial begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7]
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`ifdef INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7]
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`INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7]
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`endif // INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE_REG_INIT // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7]
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_RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7]
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ridx = _RANDOM[/*Zero width*/ 1'b0][2:0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :258:23]
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holdRidx_last_r = _RANDOM[/*Zero width*/ 1'b0][3]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :258:23]
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holdRidx_hold_data = _RANDOM[/*Zero width*/ 1'b0][6:4]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :258:23]
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holdRidx_last_r_1 = _RANDOM[/*Zero width*/ 1'b0][7]; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :258:23]
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holdRidx_hold_data_1 = _RANDOM[/*Zero width*/ 1'b0][10:8]; // @[utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :258:23]
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`endif // RANDOMIZE_REG_INIT
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if (reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7]
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holdRidx_last_r = 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:227:7]
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holdRidx_last_r_1 = 1'h0; // @[utility/src/main/scala/utility/ClockGatedReg.scala:25:22, utility/src/main/scala/utility/SRAMTemplate.scala:227:7]
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end
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end // initial
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`ifdef FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7]
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`FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:227:7]
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`endif // FIRRTL_AFTER_INITIAL
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`endif // ENABLE_INITIAL_REG_
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SRAMTemplate_14 array ( // @[utility/src/main/scala/utility/SRAMTemplate.scala:247:21]
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.clock (clock),
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.reset (reset),
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.io_r_req_ready (io_r_req_ready),
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.io_r_req_valid (io_r_req_valid),
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.io_r_req_bits_setIdx (io_r_req_bits_setIdx[10:3]), // @[utility/src/main/scala/utility/SRAMTemplate.scala:257:36]
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.io_r_resp_data_0 (_array_io_r_resp_data_0),
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.io_r_resp_data_1 (_array_io_r_resp_data_1),
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.io_r_resp_data_2 (_array_io_r_resp_data_2),
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.io_r_resp_data_3 (_array_io_r_resp_data_3),
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.io_r_resp_data_4 (_array_io_r_resp_data_4),
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.io_r_resp_data_5 (_array_io_r_resp_data_5),
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.io_r_resp_data_6 (_array_io_r_resp_data_6),
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.io_r_resp_data_7 (_array_io_r_resp_data_7),
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.io_r_resp_data_8 (_array_io_r_resp_data_8),
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.io_r_resp_data_9 (_array_io_r_resp_data_9),
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.io_r_resp_data_10 (_array_io_r_resp_data_10),
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.io_r_resp_data_11 (_array_io_r_resp_data_11),
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.io_r_resp_data_12 (_array_io_r_resp_data_12),
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.io_r_resp_data_13 (_array_io_r_resp_data_13),
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.io_r_resp_data_14 (_array_io_r_resp_data_14),
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.io_r_resp_data_15 (_array_io_r_resp_data_15),
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.io_w_req_valid (io_w_req_valid),
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.io_w_req_bits_setIdx (io_w_req_bits_setIdx[10:3]), // @[utility/src/main/scala/utility/SRAMTemplate.scala:274:36]
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.io_w_req_bits_data_0 (io_w_req_bits_data_0),
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.io_w_req_bits_data_1 (io_w_req_bits_data_1),
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.io_w_req_bits_data_2 (io_w_req_bits_data_0),
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.io_w_req_bits_data_3 (io_w_req_bits_data_1),
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.io_w_req_bits_data_4 (io_w_req_bits_data_0),
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.io_w_req_bits_data_5 (io_w_req_bits_data_1),
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.io_w_req_bits_data_6 (io_w_req_bits_data_0),
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.io_w_req_bits_data_7 (io_w_req_bits_data_1),
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.io_w_req_bits_data_8 (io_w_req_bits_data_0),
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.io_w_req_bits_data_9 (io_w_req_bits_data_1),
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.io_w_req_bits_data_10 (io_w_req_bits_data_0),
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.io_w_req_bits_data_11 (io_w_req_bits_data_1),
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.io_w_req_bits_data_12 (io_w_req_bits_data_0),
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.io_w_req_bits_data_13 (io_w_req_bits_data_1),
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.io_w_req_bits_data_14 (io_w_req_bits_data_0),
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.io_w_req_bits_data_15 (io_w_req_bits_data_1),
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.io_w_req_bits_waymask
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({(&(io_w_req_bits_setIdx[2:0])) & io_w_req_bits_waymask[1],
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(&(io_w_req_bits_setIdx[2:0])) & io_w_req_bits_waymask[0],
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_wmask_T_39 & io_w_req_bits_waymask[1],
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_wmask_T_39 & io_w_req_bits_waymask[0],
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_wmask_T_33 & io_w_req_bits_waymask[1],
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_wmask_T_33 & io_w_req_bits_waymask[0],
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_wmask_T_27 & io_w_req_bits_waymask[1],
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_wmask_T_27 & io_w_req_bits_waymask[0],
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_wmask_T_21 & io_w_req_bits_waymask[1],
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_wmask_T_21 & io_w_req_bits_waymask[0],
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_wmask_T_15 & io_w_req_bits_waymask[1],
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_wmask_T_15 & io_w_req_bits_waymask[0],
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_wmask_T_9 & io_w_req_bits_waymask[1],
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_wmask_T_9 & io_w_req_bits_waymask[0],
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_wmask_T_3 & io_w_req_bits_waymask[1],
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_wmask_T_3 & io_w_req_bits_waymask[0]}), // @[utility/src/main/scala/utility/SRAMTemplate.scala:275:54, :279:{69,82,110,122}]
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.extra_reset (extra_reset)
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);
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assign io_r_resp_data_0 =
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holdRidx == 3'h0 & _array_io_r_resp_data_0 | holdRidx == 3'h1
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& _array_io_r_resp_data_2 | holdRidx == 3'h2 & _array_io_r_resp_data_4
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| holdRidx == 3'h3 & _array_io_r_resp_data_6 | holdRidx == 3'h4
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& _array_io_r_resp_data_8 | holdRidx == 3'h5 & _array_io_r_resp_data_10
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| holdRidx == 3'h6 & _array_io_r_resp_data_12 | (&holdRidx)
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& _array_io_r_resp_data_14; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :247:21, :279:69]
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assign io_r_resp_data_1 =
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holdRidx_1 == 3'h0 & _array_io_r_resp_data_1 | holdRidx_1 == 3'h1
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& _array_io_r_resp_data_3 | holdRidx_1 == 3'h2 & _array_io_r_resp_data_5
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| holdRidx_1 == 3'h3 & _array_io_r_resp_data_7 | holdRidx_1 == 3'h4
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& _array_io_r_resp_data_9 | holdRidx_1 == 3'h5 & _array_io_r_resp_data_11
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| holdRidx_1 == 3'h6 & _array_io_r_resp_data_13 | (&holdRidx_1)
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& _array_io_r_resp_data_15; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:227:7, :247:21, :279:69]
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endmodule
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