### Details:
- If kv caches are reallocated and copied at one time, there will be a
memory peak at that inference.
- Distributed kv cahce allocation period to prevent that issue as a
temporal quick solution
### Tickets:
- 128982
### Details:
- Extend Gather op with String support for data input
(agreed to do it within the same op version, existing reference
implementation is common for GatherBase and ready to handle strings, ref
changes are not needed, just evaluate supported types updated)
- Enable fallback to the reference implementation from CPU plugin
- Extend Template and CPU plugin operator tests with string validation
(most of the changes are tests related)
### Tickets:
- 130688
### Details:
- Refactor executor config structure:
1.Change some properties into private. Related PR should be changed in
[openvino_contrib
PR856](https://github.com/openvinotoolkit/openvino_contrib/pull/856)
2.Suggest setting executor config property by
`ov::threading::IStreamsExecutor::Config()` constructor.
3.Update make_default_multi_threaded() based on MT 2.0
- Threading property migration to OV API 2.0
([PR#21487](https://github.com/openvinotoolkit/openvino/pull/21487))
### Tickets:
- *130373*
### Details:
- *Check model header validity in `ModelDeserializer`*
- *Header's data has intra-dependency, if number not match, throw
exception*
### Tickets:
- *CVS-126392*
### Details:
- The main models of LLMs use `SwiGLU(Swish-Gated Linear Unit)` instead
of `ReLU` for FFN. and it's necessary to fuse SwiGLU decomposition with
SwiGLU internal op
- Add internal SwiGLU op and related transformation which fuse SwiGLU
decomposition with SwiGLU activation op
- Add primitive, kernel selector, and kernel for SwiGLU activation
- Add subgraph func test and unit tests for SwiGLU activation
### Tickets:
- 128820
---------
Signed-off-by: Andrew Park <andrew.park@intel.com>
### Details:
- *Remove const folding for Gather's input weights*
- *Fuse scale and zeropoint to Gather*
- *Upgrade Gather, only process the case with fused zp and scale*
### Tickets:
- *128360*
### Details:
- *Migrate to onednn 3.3*
- *Enable brgconv on avx2. Fall back on jit legacy zp when having input
zp(even per-tenson) to fix perf regression*
### Tickets:
- *129816*
[CPU] fix issue - a static TI node with dynamic subgraph
### Details:
- *When the TI node is a static node and its subgraph is a dynamic
function, the dynamic backedge will resize the corresponding input
memory of subgraph. But this memory primitive is kept by the first
mappers which is not aware of the backedge mapper change. When next
inference executes the original input portmap, memory crashes.*
- *...*
### Tickets:
- *126207*
---------
Co-authored-by: Maksim Kutakov <maxim.kutakov@gmail.com>
* init
* check parentNode
* move the check in FuseConvolutionSumAndConvolutionSumActivation
* force f16 everywhere (rollback this commit before merge)
* force f32 deconv and reference on arm
* force f32 in reference node for all float types
* revert changes in reference node and
* remove hardcode
* rename fuse map
* bring f16 infer back
* remove f16 infer prec hardcode
* [CPU]BF16 MultiQuery Init Support
* [CPU]SKIP test if there is no amx
* [CPU]Fix bug with avx512_bf16
* [CPU]fix throw macro
* [CPU]Fix name typos
* [CPU]Fix unit test compilation
* [CPU]Skip bf16 sdpa test when platform doesn't support bf16
* [CPU]Derive attn_mask precision from template T
* [CPU]brgemm's multi-query only supports BF16
* [CPU]apply review comments
* [CPU]fix brgemm unit test.
* [CPU]Move brgemm kernel under x64
* [CPU]SDPA enables bf16 only when platform supports
* Hetero does not pass CACHE_DIR to the CPU plugin
* ov::CoreImpl::query_model filters out ov::cache_dir
* clang format
* clang format
* add a mode to ICore::get_supported_property which is responsible for query_model or compile_model behavior
* add test casse for get_supported_property_test
* clang format
* clang format
* disable failed test on SPR
Signed-off-by: HU Yuan2 <yuan2.hu@intel.com>
* narrow down the f16 test case
Signed-off-by: HU Yuan2 <yuan2.hu@intel.com>
* disable anther f16 test case
Signed-off-by: HU Yuan2 <yuan2.hu@intel.com>
---------
Signed-off-by: HU Yuan2 <yuan2.hu@intel.com>
Taylor Yeonbok Lee