[CPU] [ARM] JIT HSwish (#24089)
### Details: - *[CPU] [ARM] jit hswish* ### Tickets: - *CVS-136940*
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@ -391,6 +391,67 @@ std::set<std::vector<element::Type>> jit_exp_emitter::get_supported_precisions(c
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return {{element::f32}};
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}
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/// HARD_SWISH ///
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jit_hswish_emitter::jit_hswish_emitter(dnnl::impl::cpu::aarch64::jit_generator* host,
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dnnl::impl::cpu::aarch64::cpu_isa_t host_isa,
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const std::shared_ptr<ov::Node>& node)
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: jit_emitter(host, host_isa, node, get_arithmetic_binary_exec_precision(node)) {
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prepare_table();
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}
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jit_hswish_emitter::jit_hswish_emitter(dnnl::impl::cpu::aarch64::jit_generator* host,
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dnnl::impl::cpu::aarch64::cpu_isa_t host_isa,
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const ov::element::Type exec_prc) : jit_emitter(host, host_isa, exec_prc) {
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prepare_table();
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}
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size_t jit_hswish_emitter::get_inputs_count() const { return 1; }
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size_t jit_hswish_emitter::get_aux_vecs_count() const { return 2; }
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size_t jit_hswish_emitter::get_aux_gprs_count() const { return 1; }
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void jit_hswish_emitter::emit_impl(const std::vector<size_t> &in_vec_idxs, const std::vector<size_t> &out_vec_idxs) const {
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if (host_isa_ == dnnl::impl::cpu::aarch64::asimd) {
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emit_isa<dnnl::impl::cpu::aarch64::asimd>(in_vec_idxs, out_vec_idxs);
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} else {
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OV_CPU_JIT_EMITTER_THROW("Can't create jit eltwise kernel");
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}
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}
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template <dnnl::impl::cpu::aarch64::cpu_isa_t isa>
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void jit_hswish_emitter::emit_isa(const std::vector<size_t> &in_vec_idxs, const std::vector<size_t> &out_vec_idxs) const {
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OV_CPU_JIT_EMITTER_ASSERT(exec_prc_ == ov::element::f32, "unsupported precision: " + exec_prc_.to_string());
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using TReg = typename dnnl::impl::cpu::aarch64::cpu_isa_traits<isa>::TReg;
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TReg src = TReg(in_vec_idxs[0]);
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TReg dst = TReg(out_vec_idxs[0]);
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TReg aux0 = TReg(aux_vec_idxs[0]);
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TReg aux1 = TReg(aux_vec_idxs[1]);
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// result = (x * min(max(x + 3, 0), 6)) / 6
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h->ld1r(aux0.s, table_val2("three"));
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h->fadd(aux0.s, src.s, aux0.s);
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h->ld1r(aux1.s, table_val2("zero"));
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h->fmaxnm(aux0.s, aux0.s, aux1.s);
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h->ld1r(aux1.s, table_val2("six"));
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h->fminnm(aux0.s, aux0.s, aux1.s);
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h->fmul(aux0.s, aux0.s, src.s);
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h->ld1r(aux1.s, table_val2("one_sixth"));
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h->fmul(dst.s, aux0.s, aux1.s);
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}
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void jit_hswish_emitter::register_table_entries() {
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push_arg_entry_of("zero", 0x00000000, true);
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push_arg_entry_of("three", 0x40400000, true);
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push_arg_entry_of("six", 0x40c00000, true);
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push_arg_entry_of("one_sixth", dnnl::impl::float2int(1.f/6.f), true);
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}
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std::set<std::vector<element::Type>> jit_hswish_emitter::get_supported_precisions(const std::shared_ptr<ov::Node>& node) {
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return {{element::f32}};
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}
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/// MUL_ADD ///
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jit_mul_add_emitter::jit_mul_add_emitter(dnnl::impl::cpu::aarch64::jit_generator* host,
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dnnl::impl::cpu::aarch64::cpu_isa_t host_isa,
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@ -160,6 +160,32 @@ private:
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void emit_isa(const std::vector<size_t> &in_vec_idxs, const std::vector<size_t> &out_vec_idxs) const;
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};
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class jit_hswish_emitter : public jit_emitter {
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public:
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jit_hswish_emitter(dnnl::impl::cpu::aarch64::jit_generator *host,
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dnnl::impl::cpu::aarch64::cpu_isa_t host_isa,
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const ov::element::Type exec_prc = ov::element::f32);
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jit_hswish_emitter(dnnl::impl::cpu::aarch64::jit_generator *host,
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dnnl::impl::cpu::aarch64::cpu_isa_t host_isa,
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const std::shared_ptr<ov::Node>& node);
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size_t get_inputs_count() const override;
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size_t get_aux_vecs_count() const override;
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size_t get_aux_gprs_count() const override;
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void register_table_entries() override;
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static std::set<std::vector<element::Type>> get_supported_precisions(const std::shared_ptr<ov::Node>& node = nullptr);
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private:
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void emit_impl(const std::vector<size_t> &in_vec_idxs, const std::vector<size_t> &out_vec_idxs) const override;
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template <dnnl::impl::cpu::aarch64::cpu_isa_t isa>
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void emit_isa(const std::vector<size_t> &in_vec_idxs, const std::vector<size_t> &out_vec_idxs) const;
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};
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class jit_mul_add_emitter : public jit_emitter {
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public:
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@ -24,6 +24,7 @@ bool JitEltwiseExecutor::isSupported(
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Algorithm::EltwiseDivide,
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Algorithm::EltwiseEqual,
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Algorithm::EltwiseExp,
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Algorithm::EltwiseHswish,
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Algorithm::EltwiseMultiply,
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Algorithm::EltwiseMulAdd,
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Algorithm::EltwisePowerStatic,
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@ -625,6 +625,7 @@ std::shared_ptr<jit_emitter> jit_uni_eltwise_generic<isa>::create_eltwise_emitte
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OV_CASE(Algorithm::EltwiseDivide, ov::intel_cpu::aarch64::jit_divide_emitter),
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OV_CASE(Algorithm::EltwiseEqual, ov::intel_cpu::aarch64::jit_equal_emitter),
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OV_CASE(Algorithm::EltwiseExp, ov::intel_cpu::aarch64::jit_exp_emitter),
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OV_CASE(Algorithm::EltwiseHswish, ov::intel_cpu::aarch64::jit_hswish_emitter),
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OV_CASE(Algorithm::EltwiseMulAdd, ov::intel_cpu::aarch64::jit_mul_add_emitter),
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OV_CASE(Algorithm::EltwiseMultiply, ov::intel_cpu::aarch64::jit_multiply_emitter),
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OV_CASE(Algorithm::EltwisePowerStatic, ov::intel_cpu::aarch64::jit_power_static_emitter),
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@ -786,6 +787,7 @@ std::set<std::vector<element::Type>> eltwise_precision_helper::get_supported_pre
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OV_CASE(Algorithm::EltwiseDivide, jit_divide_emitter),
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OV_CASE(Algorithm::EltwiseEqual, jit_equal_emitter),
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OV_CASE(Algorithm::EltwiseExp, jit_exp_emitter),
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OV_CASE(Algorithm::EltwiseHswish, jit_hswish_emitter),
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OV_CASE(Algorithm::EltwiseMulAdd, jit_mul_add_emitter),
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OV_CASE(Algorithm::EltwiseMultiply, jit_multiply_emitter),
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OV_CASE(Algorithm::EltwisePrelu, jit_prelu_emitter),
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@ -155,6 +155,7 @@ std::string ActivationLayerCPUTest::getPrimitiveType(const utils::ActivationType
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if ((element_type == ov::element::f32) &&
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((activation_type == utils::ActivationTypes::Clamp) ||
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(activation_type == utils::ActivationTypes::Exp) ||
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(activation_type == utils::ActivationTypes::HSwish) ||
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(activation_type == utils::ActivationTypes::Relu) ||
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(activation_type == utils::ActivationTypes::Sigmoid) ||
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(activation_type == utils::ActivationTypes::Swish) ||
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