[CPU][ARM] Enable NHWC in Reduce (#23108)
NHWC was disabled because of accuracy issue: https://github.com/ARM-software/ComputeLibrary/issues/1044 CVS-114403 --------- Co-authored-by: eshoguli <edward.shogulin@intel.com>
This commit is contained in:
Aleksandr Voron
GitHub
parent
f5c3fc3330
commit
4e6ee7f15e
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@ -36,24 +36,36 @@ bool AclReduceExecutor::init(const ReduceAttrs& reduceAttrs,
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this->reduceAttrs = reduceAttrs;
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auto srcDims = srcDescs[0]->getShape().getStaticDims();
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auto dstDims = dstDescs[0]->getShape().getStaticDims();
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const auto& srcDims = srcDescs[0]->getShape().getStaticDims();
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const auto& dstDims = dstDescs[0]->getShape().getStaticDims();
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bool hasSrcNspcLayout = srcDescs[0]->hasLayoutType(LayoutType::nspc);
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bool hasDstNspcLayout = dstDescs[0]->hasLayoutType(LayoutType::nspc);
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auto srcShape = shapeCast(srcDims);
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auto dstShape = shapeCast(dstDims);
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if (hasSrcNspcLayout && hasDstNspcLayout) {
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changeLayoutToNH_C({&srcShape, &dstShape});
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}
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TensorInfo srcTensorInfo = TensorInfo(shapeCast(srcDims), 1,
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TensorInfo srcTensorInfo = TensorInfo(srcShape, 1,
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precisionToAclDataType(srcDescs[0]->getPrecision()), getAclDataLayoutByMemoryDesc(srcDescs[0]));
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TensorInfo dstTensorInfo = TensorInfo(shapeCast(dstDims), 1,
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TensorInfo dstTensorInfo = TensorInfo(dstShape, 1,
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precisionToAclDataType(dstDescs[0]->getPrecision()), getAclDataLayoutByMemoryDesc(dstDescs[0]));
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srcTensor.allocator()->init(srcTensorInfo);
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dstTensor.allocator()->init(dstTensorInfo);
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std::function<std::unique_ptr<IFunction>(void)> exec_func;
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std::vector<int> castedAxes;
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for (size_t i = 0; i < reduceAttrs.axes.size(); ++i) {
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int axis = axisCast(reduceAttrs.axes[i], srcDims.size(), hasSrcNspcLayout ? NHWC_TO_NCHW : NO_LAYOUT_CONVERSION);
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if (hasSrcNspcLayout && axis == -1) return false;
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castedAxes.push_back(axis);
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}
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switch (reduceAttrs.operation) {
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case Algorithm::ReduceMean: {
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for (size_t i = 0; i < reduceAttrs.axes.size(); ++i) {
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auto axe = axisCast(reduceAttrs.axes[i], srcDims.size());
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auto pos = axisCast(i, reduceAttrs.axes.size());
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axesMean.set(pos, axe);
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axesMean.set(pos, castedAxes[i]);
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}
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Status reduceMeanStatus = NEReduceMean::validate(&srcTensorInfo, axesMean, reduceAttrs.keepDims, &dstTensorInfo);
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if (!reduceMeanStatus) {
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@ -71,15 +83,15 @@ bool AclReduceExecutor::init(const ReduceAttrs& reduceAttrs,
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case Algorithm::ReduceMin:
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case Algorithm::ReduceSum:
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case Algorithm::ReduceProd: {
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Status reductionOperationStatus = NEReductionOperation::validate(&srcTensorInfo, &dstTensorInfo, axisCast(reduceAttrs.axes[0], srcDims.size()),
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Status reductionOperationStatus = NEReductionOperation::validate(&srcTensorInfo, &dstTensorInfo, castedAxes[0],
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getAclReductionOperationByAlgorithm(reduceAttrs.operation), reduceAttrs.keepDims);
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if (!reductionOperationStatus) {
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DEBUG_LOG("NEReductionOperation validation with indices failed: ", reductionOperationStatus.error_description());
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return false;
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}
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exec_func = [this, srcDims]() -> std::unique_ptr<IFunction> {
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exec_func = [this, castedAxes]() -> std::unique_ptr<IFunction> {
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auto acl_op = std::make_unique<arm_compute::NEReductionOperation>();
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acl_op->configure(&srcTensor, &dstTensor, axisCast(this->reduceAttrs.axes[0], srcDims.size()),
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acl_op->configure(&srcTensor, &dstTensor, castedAxes[0],
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getAclReductionOperationByAlgorithm(this->reduceAttrs.operation), this->reduceAttrs.keepDims);
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return acl_op;
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};
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@ -103,4 +115,4 @@ void AclReduceExecutor::exec(const std::vector<MemoryCPtr>& src, const std::vect
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}
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} // namespace intel_cpu
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} // namespace ov
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} // namespace ov
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@ -67,8 +67,33 @@ inline arm_compute::TensorShape shapeCast(const VectorDims& dims) {
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return tensorShape;
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}
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inline std::size_t axisCast(const std::size_t axis, const std::size_t shapeSize) {
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return shapeSize - axis - 1;
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enum ACLAxisCastMode {
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NO_LAYOUT_CONVERSION,
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NHWC_TO_NCHW,
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NCHW_TO_NHWC
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};
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/**
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* @brief Return reverted axis used in ACL. If axis cast mode is
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* @param axis axis that needs to be converted
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* @param shapeSize size of the shape, which axis needs to be converted
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* @param axisCastMode specifies whether layout conversion is required or not
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* @return reverted axis
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*/
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inline int axisCast(const std::size_t axis, const std::size_t shapeSize, ACLAxisCastMode axisCastMode = NO_LAYOUT_CONVERSION) {
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// CWHN (reverted NHWC) (0, 1, 2, 3) into WHCN (reverted NCHW) (1, 2, 0, 3)
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static std::vector<size_t> nhwcToNchw = {1, 2, 0, 3};
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// WHCN (reverted NCHW) (0, 1, 2, 3) into CWHN (reverted NHWC) (2, 0, 1, 3)
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static std::vector<size_t> nchwToNhwc = {2, 0, 1, 3};
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size_t revertedAxis = shapeSize - axis - 1;
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switch (axisCastMode) {
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case NHWC_TO_NCHW:
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return revertedAxis > 3 ? -1 : nhwcToNchw[revertedAxis];
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case NCHW_TO_NHWC:
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return revertedAxis > 3 ? -1 : nchwToNhwc[revertedAxis];
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default:
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return revertedAxis;
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}
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}
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inline Dim vectorProduct(const VectorDims& vec, size_t size) {
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@ -1992,8 +1992,7 @@ void Reduce::initSupportedPrimitiveDescriptors() {
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if (axis < 0)
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axis += static_cast<int>(getInputShapeAtPort(REDUCE_DATA).getRank());
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}
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// TODO: Per-channel layout is disabled due to accuracy issue in ACL Reduce Executor
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// pushDesc(LayoutType::nspc, LayoutType::nspc, input_prec, output_prec, undef, true);
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pushDesc(LayoutType::nspc, LayoutType::nspc, input_prec, output_prec, impl_desc_type::undef, true);
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pushDesc(LayoutType::ncsp, LayoutType::ncsp, input_prec, output_prec, impl_desc_type::undef, true);
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canUseAclExecutor = !supportedPrimitiveDescriptors.empty();
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if (canUseAclExecutor)
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@ -0,0 +1,38 @@
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// Copyright (C) 2020-2024 Intel Corporation
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// SPDX-License-Identifier: Apache-2.0
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#include "convert_reduce_no_keep_dims.hpp"
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#include "openvino/core/rt_info.hpp"
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#include "openvino/opsets/opset8.hpp"
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template <class T>
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ov::matcher_pass_callback ov::intel_cpu::ConvertReduceNoKeepDimsBase::convert_reduce() {
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return [&](ov::pass::pattern::Matcher& m) {
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auto reduce = std::dynamic_pointer_cast<T>(m.get_match_root());
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if (!reduce || reduce->get_keep_dims()) {
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return false;
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}
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reduce->set_keep_dims(true);
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const auto reduce_new = reduce->clone_with_new_inputs({reduce->input_value(0), reduce->input_value(1)});
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std::shared_ptr<ov::Node> squeeze = std::make_shared<ov::op::v0::Squeeze>(reduce_new, reduce->input_value(1));
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squeeze->set_friendly_name(reduce_new->get_friendly_name());
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ov::copy_runtime_info(reduce, {reduce_new, squeeze});
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ov::replace_node(reduce, squeeze);
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return true;
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};
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}
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template <typename ReductionType>
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ov::intel_cpu::ConvertReduction<ReductionType>::ConvertReduction() {
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auto m = std::make_shared<ov::pass::pattern::Matcher>(
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ov::pass::pattern::wrap_type<ReductionType>({ov::pass::pattern::any_input(),
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ov::pass::pattern::wrap_type<ov::opset8::Constant>()}), "ConvertReduction");
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register_matcher(m, convert_reduce<ReductionType>());
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}
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template class ov::intel_cpu::ConvertReduction<ov::op::util::LogicalReductionKeepDims>;
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template class ov::intel_cpu::ConvertReduction<ov::op::util::ArithmeticReductionKeepDims>;
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@ -0,0 +1,71 @@
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// Copyright (C) 2020-2024 Intel Corporation
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// SPDX-License-Identifier: Apache-2.0
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#pragma once
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#include "openvino/pass/pattern/op/wrap_type.hpp"
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#include "openvino/pass/graph_rewrite.hpp"
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#include "openvino/op/util/arithmetic_reductions_keep_dims.hpp"
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#include "openvino/op/util/logical_reduction_keep_dims.hpp"
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/*
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* Description:
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* ConvertReduceNoKeepDimsBase detects Reduce operations with keepDims = false.
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* Such Reduce operation is replaced with Reduce operation with keepDims = true and Squeeze
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* which removes undesired dimensions.
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*
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* Before:
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*
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* +--------------+ +-----------------+
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* | Data | | Axes tensor |
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* +-----------+--+ +-+---------------+
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* | |
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* +---------------------------+
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* | Reduce (keepDims = false) |
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* +---------------------------+
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*
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* After:
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*
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* +--------------+ +-----------------+
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* | Data | | Axes tensor |
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* +-----------+--+ +-+------------+--+
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* | | |
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* +---------------------------+ |
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* | Reduce (keepDims = true) | |
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* +-----------------------+---+ |
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* | |
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* +--------v------v-+
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* | Squeeze |
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* +-----------------+
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*
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*/
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namespace ov {
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namespace intel_cpu {
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class ConvertReduceNoKeepDimsBase: public ov::pass::MatcherPass {
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public:
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OPENVINO_RTTI("ConvertReduceNoKeepDims", "0");
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template <class T>
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ov::matcher_pass_callback convert_reduce();
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};
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template <typename ReductionType>
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class ConvertReduction: public ConvertReduceNoKeepDimsBase {
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public:
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OPENVINO_RTTI("ConvertReduction", "0");
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ConvertReduction();
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};
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class ConvertReduceNoKeepDims: public ov::pass::GraphRewrite {
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public:
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OPENVINO_RTTI("ConvertReduceNoKeepDims", "0");
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ConvertReduceNoKeepDims() {
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add_matcher<ConvertReduction<ov::op::util::LogicalReductionKeepDims>>();
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add_matcher<ConvertReduction<ov::op::util::ArithmeticReductionKeepDims>>();
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}
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};
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} // namespace intel_cpu
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} // namespace ov
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@ -122,6 +122,7 @@
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#include "transformations/cpu_opset/arm/pass/convert_group_conv1d.hpp"
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#include "transformations/cpu_opset/arm/pass/convert_reduce_multi_axis.hpp"
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#include "transformations/cpu_opset/arm/pass/mish_decomposition.hpp"
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#include "transformations/cpu_opset/arm/pass/convert_reduce_no_keep_dims.hpp"
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#include "transformations/cpu_opset/common/pass/decompose_integer_divide.hpp"
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#include "transformations/cpu_opset/common/pass/convert_fq_rnn_to_quantized_rnn.hpp"
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#include "transformations/cpu_opset/common/pass/insert_convert_after_extension.hpp"
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@ -432,6 +433,7 @@ void Transformations::PreLpt(const std::vector<ov::element::Type>& defaultPrecis
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CPU_REGISTER_PASS_COMMON(manager, SwapConvertTranspose);
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CPU_REGISTER_PASS_X64(manager, ConvertToInteraction);
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CPU_REGISTER_PASS_X64(manager, ConvertInteractionInt8);
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CPU_REGISTER_PASS_ARM(manager, ConvertReduceNoKeepDims);
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CPU_REGISTER_PASS_ARM(manager, ConvertReduceMultiAxis);
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CPU_REGISTER_PASS_ARM32(manager, MishDecomposition);
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CPU_REGISTER_PASS_ARM(manager, ConvertConv1D);
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@ -46,10 +46,7 @@ std::vector<std::vector<ov::test::InputShape>> inputShapes_SingleBatch = {
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std::vector<CPUSpecificParams> cpuParams_4D = {
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CPUSpecificParams({nchw}, {nchw}, {}, {}),
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//NHWC layout is disabled on ARM due to accuracy issue: https://github.com/ARM-software/ComputeLibrary/issues/1044
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#if defined(OPENVINO_ARCH_X86) || defined(OPENVINO_ARCH_X86_64)
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CPUSpecificParams({nhwc}, {nhwc}, {}, {}),
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#endif
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};
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/* ================================ 1.1 No fusion - Arithmetic ================================ */
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@ -160,4 +157,4 @@ INSTANTIATE_TEST_SUITE_P(
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} // namespace Reduce
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} // namespace test
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} // namespace ov
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} // namespace ov
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@ -0,0 +1,91 @@
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// Copyright (C) 2018-2024 Intel Corporation
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// SPDX-License-Identifier: Apache-2.0
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//
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#include <gtest/gtest.h>
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#include <openvino/opsets/opset1.hpp>
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#include <transformations/cpu_opset/arm/pass/convert_reduce_no_keep_dims.hpp>
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#include "common_test_utils/ov_test_utils.hpp"
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using namespace ov::intel_cpu;
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template <class T>
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class ConvertReduceNoKeepDimsTest : public testing::Test {};
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template <class T>
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static std::shared_ptr<ov::Model> createInitGraph(std::shared_ptr<ov::opset1::Parameter> param) {
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auto axes = ov::opset1::Constant::create(ov::element::i64, ov::Shape{2}, {0, 1});
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auto reduce = std::make_shared<T>(param, axes, false);
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return std::make_shared<ov::Model>(ov::NodeVector{ reduce }, ov::ParameterVector{ param });
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}
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template <class T>
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static std::shared_ptr<ov::Model> createRefGraph(std::shared_ptr<ov::opset1::Parameter> param) {
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auto axes = ov::opset1::Constant::create(ov::element::i64, ov::Shape{2}, {0, 1});
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auto reduce = std::make_shared<T>(param, axes, true);
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auto squeeze = std::make_shared<ov::opset1::Squeeze>(reduce, axes);
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return std::make_shared<ov::Model>(ov::NodeVector{ squeeze }, ov::ParameterVector{ param });
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}
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template <class T>
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static bool registerAndRunReducePass(std::shared_ptr<ov::Model> model) {
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ov::pass::Manager manager;
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if (std::is_base_of<ov::op::util::LogicalReductionKeepDims, T>::value) {
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manager.register_pass<ConvertReduction<ov::op::util::LogicalReductionKeepDims>>();
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} else if (std::is_base_of<ov::op::util::ArithmeticReductionKeepDims, T>::value) {
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manager.register_pass<ConvertReduction<ov::op::util::ArithmeticReductionKeepDims>>();
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} else {
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return false;
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}
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manager.run_passes(model);
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return true;
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}
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static ov::Shape static_param_shape = ov::Shape{2, 19, 2, 9};
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static ov::PartialShape dynamic_param_shape = ov::PartialShape{2, -1, 2, 9};
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TYPED_TEST_SUITE_P(ConvertReduceNoKeepDimsTest);
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TYPED_TEST_P(ConvertReduceNoKeepDimsTest, CheckConvertReduceTransformationIsAppliedForStaticShapes) {
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ov::element::Type_t dataType = std::is_base_of<ov::op::util::LogicalReductionKeepDims, TypeParam>::value ?
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ov::element::boolean : ov::element::f32;
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auto param = std::make_shared<ov::opset1::Parameter>(dataType, static_param_shape);
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auto model = createInitGraph<TypeParam>(param);
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auto model_ref = createRefGraph<TypeParam>(param);
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if (!registerAndRunReducePass<TypeParam>(model)) {
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FAIL() << "Reduce pass is not registered.";
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}
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auto res = compare_functions(model, model_ref);
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ASSERT_TRUE(res.first) << res.second;
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}
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TYPED_TEST_P(ConvertReduceNoKeepDimsTest, CheckConvertReduceTransformationIsAppliedForDynaimcShapes) {
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ov::element::Type_t dataType = std::is_base_of<ov::op::util::LogicalReductionKeepDims, TypeParam>::value ?
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ov::element::boolean : ov::element::f32;
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auto param = std::make_shared<ov::opset1::Parameter>(dataType, dynamic_param_shape);
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auto model = createInitGraph<TypeParam>(param);
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auto model_ref = createRefGraph<TypeParam>(param);
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if (!registerAndRunReducePass<TypeParam>(model)) {
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FAIL() << "Reduce pass is not registered.";
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}
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auto res = compare_functions(model, model_ref);
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ASSERT_TRUE(res.first) << res.second;
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}
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REGISTER_TYPED_TEST_SUITE_P(ConvertReduceNoKeepDimsTest,
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CheckConvertReduceTransformationIsAppliedForStaticShapes,
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CheckConvertReduceTransformationIsAppliedForDynaimcShapes);
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using reduceTypes = ::testing::Types<ov::opset1::ReduceMin,
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ov::opset1::ReduceMax,
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ov::opset1::ReduceSum,
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ov::opset1::ReduceProd,
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ov::opset1::ReduceMean,
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ov::opset1::ReduceLogicalAnd,
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ov::opset1::ReduceLogicalOr>;
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INSTANTIATE_TYPED_TEST_SUITE_P(ConvertReduce, ConvertReduceNoKeepDimsTest, reduceTypes);
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