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[CPU] fix most performance regression of some models on Atom (#23179) 

### Details:
- *when input channel of convolution is 2, there are extra reorders
inserted into graph, add descriptor nCsp8c->nCsp8c to fix it*


### Tickets:
 - *CVS-125793*

---------

Signed-off-by: HU Yuan2 <yuan2.hu@intel.com>
This commit is contained in:
Yuan Hu 2024-03-05 20:57:04 +08:00 committed by GitHub
parent ac206454d7
commit 4502e45046
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
3 changed files with 33 additions and 12 deletions
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13
src/plugins/intel_cpu/src/nodes/conv.cpp
View File

@ -557,13 +557,14 @@ void Convolution::getSupportedDescriptors() {
in_candidate = std::make_shared<DnnlBlockedMemoryDesc>(inputShape, inputDataType, ncsp);
out_candidate = std::make_shared<DnnlBlockedMemoryDesc>(outputShape, outputDataType, ncsp);
createDescriptor({ in_candidate }, { out_candidate });
} else if (IC < 4) {
in_candidate = std::make_shared<DnnlBlockedMemoryDesc>(inputShape, inputDataType, ncsp);
out_candidate = std::make_shared<DnnlBlockedMemoryDesc>(outputShape, outputDataType, nCsp16c);
createDescriptor({ in_candidate }, { out_candidate });
out_candidate = std::make_shared<DnnlBlockedMemoryDesc>(outputShape, outputDataType, nCsp8c);
createDescriptor({ in_candidate }, { out_candidate });
} else {
if (IC < 4) {
in_candidate = std::make_shared<DnnlBlockedMemoryDesc>(inputShape, inputDataType, ncsp);
out_candidate = std::make_shared<DnnlBlockedMemoryDesc>(outputShape, outputDataType, nCsp16c);
createDescriptor({ in_candidate }, { out_candidate });
out_candidate = std::make_shared<DnnlBlockedMemoryDesc>(outputShape, outputDataType, nCsp8c);
createDescriptor({ in_candidate }, { out_candidate });
}
in_candidate = std::make_shared<DnnlBlockedMemoryDesc>(inputShape, inputDataType, nCsp16c);
out_candidate = std::make_shared<DnnlBlockedMemoryDesc>(outputShape, outputDataType, nCsp16c);
createDescriptor({ in_candidate }, { out_candidate });

30
src/plugins/intel_cpu/tests/functional/shared_tests_instances/snippets/fake_quantize_decomposition_test.cpp
View File

@ -6,6 +6,7 @@
#include <vector>
#include "snippets/fake_quantize_decomposition_test.hpp"
#include "ie_system_conf.h"
using namespace LayerTestsDefinitions;
using namespace ngraph;
@ -80,7 +81,7 @@ INSTANTIATE_TEST_SUITE_P(
namespace legacyFuse {
const std::vector<TestValues> testValuesLegacyFuse = {
const std::vector<TestValues> testValuesLegacyFuse_binary_post = {
{
ov::element::f32,
ngraph::Shape{1, 3, 16, 16},
@ -100,14 +101,17 @@ const std::vector<TestValues> testValuesLegacyFuse = {
ngraph::Shape{1, 3, 16, 16},
ov::element::f32,
1.f,
{{}, {}, {}, {}}
{{1, 3, 1, 1}, {1, 3, 1, 1}, {1, 3, 1, 1}, {1, 3, 1, 1}}
},
};
const std::vector<TestValues> testValuesLegacyFuse = {
{
ov::element::f32,
ngraph::Shape{1, 3, 16, 16},
ov::element::f32,
1.f,
{{1, 3, 1, 1}, {1, 3, 1, 1}, {1, 3, 1, 1}, {1, 3, 1, 1}}
{{}, {}, {}, {}}
},
};
@ -121,8 +125,24 @@ INSTANTIATE_TEST_SUITE_P(
::testing::Combine(
::testing::ValuesIn(testValuesLegacyFuse),
::testing::ValuesIn(operations),
// reorder (nChw[16|8]c) + MaxPool + reorder(nhwc) + reorder(ABcd16b16a) + Convolution + reorder(nchw)
::testing::Values(std::pair<size_t, size_t>{6, 0}),
// if ISA has avx512, conv node will use brgconv, there will be a extra reorder(nhwc)
// for brg, reorder (nChw[16|8]c) + MaxPool + reorder(nhwc) + reorder(Acdb16a) + Convolution(nhwc) + reorder(nchw)
// for no brg, reorder (nChw[16|8]c) + MaxPool + reorder(ABcd8b8a) + Convolution(nchw8c) + reorder(nchw)
::testing::Values(InferenceEngine::with_cpu_x86_avx512_core() ? std::pair<size_t, size_t>{6, 0} : std::pair<size_t, size_t>{5, 0}),
::testing::Values(CommonTestUtils::DEVICE_CPU)),
FakeQuantizeDecompositionTest::getTestCaseName);
INSTANTIATE_TEST_SUITE_P(
smoke_Snippets_binary_post,
FakeQuantizeDecompositionTest,
::testing::Combine(
::testing::ValuesIn(testValuesLegacyFuse_binary_post),
::testing::ValuesIn(operations),
// if ISA has avx512_amx, conv node will use brgconv, there will be a extra reorder(nhwc).
// if it's avx512 + binary_post ops, conv node will not use brgconv.
// for brg, reorder (nChw[16|8]c) + MaxPool + reorder(nhwc) + reorder(Acdb16a) + Convolution(nhwc) + reorder(nchw)
// for no brg, reorder (nChw[16|8]c) + MaxPool + reorder(ABcd8b8a) + Convolution(nChw8c) + reorder(nchw)
::testing::Values(InferenceEngine::with_cpu_x86_avx512_core_amx() ? std::pair<size_t, size_t>{6, 0} : std::pair<size_t, size_t>{5, 0}),
::testing::Values(CommonTestUtils::DEVICE_CPU)),
FakeQuantizeDecompositionTest::getTestCaseName);

2
src/plugins/intel_cpu/thirdparty/onednn vendored

@ -1 +1 @@
Subproject commit 44de3c3698b687c26e487fc8f0213fa487e8fe2c
Subproject commit a3a2be6cf6d9ce466cc1a7c2597e01843d8bb551