From 2bd1a444371c0617631fd5a4f53ef0a9664ecfae Mon Sep 17 00:00:00 2001 From: Fredrik Osterlind Date: Mon, 12 Mar 2012 14:41:44 +0100 Subject: [PATCH 1/2] turn off radio and stop transmitting at reset --- se/sics/mspsim/chip/CC2420.java | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/se/sics/mspsim/chip/CC2420.java b/se/sics/mspsim/chip/CC2420.java index 1b86bf1..a041818 100644 --- a/se/sics/mspsim/chip/CC2420.java +++ b/se/sics/mspsim/chip/CC2420.java @@ -1318,6 +1318,13 @@ public class CC2420 extends Chip implements USARTListener, RFListener, RFSource this.cl = cl; } + public void notifyReset() { + super.notifyReset(); + setChipSelect(false); + status &= ~STATUS_TX_ACTIVE; + setVRegOn(false); + } + public void setVRegOn(boolean newOn) { if(on == newOn) return; From a4f2fbf314d0444069a375e182760eec40211b21 Mon Sep 17 00:00:00 2001 From: Niclas Finne Date: Fri, 16 Mar 2012 00:33:25 +0100 Subject: [PATCH 2/2] Bug fix: indexed address mode overflow/underflow inspired by patch from Ben Ransford --- se/sics/mspsim/core/MSP430Core.java | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/se/sics/mspsim/core/MSP430Core.java b/se/sics/mspsim/core/MSP430Core.java index a419b18..f3194b2 100644 --- a/se/sics/mspsim/core/MSP430Core.java +++ b/se/sics/mspsim/core/MSP430Core.java @@ -1774,16 +1774,30 @@ public class MSP430Core extends Chip implements MSP430Constants { } break; - case AM_INDEX: - // Indexed if reg != PC & CG1/CG2 - will PC be incremented? - srcAddress = readRegisterCG(srcRegister, as) + read(pc, MODE_WORD); -// memory[pc] + (memory[pc + 1] << 8); + case AM_INDEX: { + // Indexed if reg != PC & CG1/CG2 - will PC be incremented? + int sval = readRegisterCG(srcRegister, as); + + /* Support for MSP430X and below / above 64 KB */ + /* if register is pointing to <64KB then it needs to be truncated to below 64 */ + if (sval < 0xffff) { + srcAddress = (sval + read(pc, MODE_WORD)) & 0xffff; + } else { + srcAddress = read(pc, MODE_WORD); + if ((srcAddress & 0x8000) > 0) { + // Negative index + srcAddress |= 0xf0000; + } + srcAddress += sval; + srcAddress &= 0xfffff; + } + // When is PC incremented - assuming immediately after "read"? - - - incRegister(PC, 2); + + incRegister(PC, 2); cycles += dstRegMode ? 3 : 6; break; + } // Indirect register case AM_IND_REG: srcAddress = readRegister(srcRegister);