fixed bug on PUSH + RETI + CALL timing

git-svn-id: https://mspsim.svn.sourceforge.net/svnroot/mspsim/mspsim@474 23d1a52b-0c3c-0410-b72d-8f29ab48fe35

CHANGE_LOG.txt

@@ -1,4 +1,5 @@
 0.97
+- fixed some cycle timing bugs of instruction set execution
 - added stack trace for misalignment warnings if MSP430 Core is in log mode
 - added MSP430 Core as a loggable
 - added emulation of DS2411 for generating MAC addresses

se/sics/mspsim/chip/CC2420.java

@@ -1083,8 +1083,6 @@ public class CC2420 extends Chip implements USARTListener, RFListener, RFSource
   }
 
   public void stateChanged(int state) {
-    // TODO Auto-generated method stub
-    
   }
   
 } // CC2420

se/sics/mspsim/core/MSP430Core.java

@@ -857,12 +857,11 @@ public class MSP430Core extends Chip implements MSP430Constants {
             dstAddress = readRegister(PC);
             pc += 2;
             writeRegister(PC, pc);
-            cycles += 5;
           } else {
             dstAddress = readRegister(dstRegister);
             writeRegister(dstRegister, dstAddress + (word ? 2 : 1));
-            cycles += 3;
           }
+          cycles += 3;
           break;
 	}
       }
@@ -927,6 +926,8 @@ public class MSP430Core extends Chip implements MSP430Constants {
 	cycles += (ad == AM_REG || ad == AM_IND_AUTOINC) ? 2 : 1;
 	write = false;
 	updateStatus = false;
+        System.out.println("Cycles on PUSH: " + (cycles - startCycles));
+
 	break;
       case CALL:
 	// store current PC on stack... (current PC points to next instr.)
@@ -954,10 +955,12 @@ public class MSP430Core extends Chip implements MSP430Constants {
 	write = false;
 	updateStatus = false;
 
+	cycles += 4;
+	
 	if (debugInterrupts) {
 	  System.out.println("### RETI at " + pc + " => " + reg[PC] +
 			     " SP after: " + reg[SP]);
-	}
+	}        
 
 	// This assumes that all interrupts will get back using RETI!
 	handlePendingInterrupts();