mirror of https://github.com/contiki-ng/mspsim
merge of latest MSP430X code for mspsim
This commit is contained in:
Joakim Eriksson
parent
a7deb906e7
commit
1b3aa68fba
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@ -42,24 +42,24 @@
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package se.sics.mspsim.core;
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import se.sics.mspsim.util.Utils;
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public class BasicClockModule extends IOUnit {
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public class BasicClockModule extends ClockSystem {
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public static final int DCOCTL = 0x56; // 0x60
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public static final int BCSCTL1 = 0x57; // 0x84
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public static final int BCSCTL2 = 0x58;
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private static final int DCOCTL = 0x56; // 0x60
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private static final int BCSCTL1 = 0x57; // 0x84
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private static final int BCSCTL2 = 0x58;
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public static final int ACLK_FRQ = 32768;
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private static final int ACLK_FRQ = 32768;
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// DCO_FRQ what default frq is the DCO running at???
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public static final int DCO_FRQ = 2500000;
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private static final int DCO_FRQ = 2500000;
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// What frequency steps to take for the DCO?
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// We have 8 bits + 3 => 11 bits => 2048 combinations...
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// => What is lowest frq??? (zero)
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// Max speed is 8Mhz (CPU limits it) - is max DCO 8Mhz?
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// Based on the scatterweb code it looks like less than
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// 5Mhz is more correct...
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public static final int MAX_DCO_FRQ = 4915200;
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public static final int MIN_DCO_FRQ = 1000;
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public static final int DCO_FACTOR = (MAX_DCO_FRQ - MIN_DCO_FRQ) / 2048;
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private static final int MAX_DCO_FRQ = 4915200;
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private static final int MIN_DCO_FRQ = 1000;
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private static final int DCO_FACTOR = (MAX_DCO_FRQ - MIN_DCO_FRQ) / 2048;
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private MSP430Core core;
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@ -87,7 +87,19 @@ public class BasicClockModule extends IOUnit {
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super("BasicClockModule", memory, offset);
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this.core = core;
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this.timers = timers;
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reset(0);
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// reset(0);
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}
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public int getMaxDCOFrequency() {
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return MAX_DCO_FRQ;
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}
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public int getAddressRangeMin() {
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return DCOCTL;
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}
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public int getAddressRangeMax() {
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return BCSCTL2;
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}
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public void reset(int type) {
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@ -0,0 +1,54 @@
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/**
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* Copyright (c) 2011, Swedish Institute of Computer Science.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* This file is part of MSPSim.
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*
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* $Id$
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*
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* -----------------------------------------------------------------
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*
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* ClockSystem
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*
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* Author : Joakim Eriksson
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* Created : Sun Oct 21 22:00:00 2007
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* Updated : $Date$
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* $Revision$
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*/
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package se.sics.mspsim.core;
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public abstract class ClockSystem extends IOUnit {
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public abstract int getMaxDCOFrequency();
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public abstract int getAddressRangeMin();
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public abstract int getAddressRangeMax();
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public ClockSystem(String type, int[] memory, int offset) {
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super(type, memory, offset);
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}
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}
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@ -27,12 +27,16 @@
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*
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* This file is part of MSPSim.
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*
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* $Id$
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*
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* -----------------------------------------------------------------
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*
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* MSP430Core
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*
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* Author : Joakim Eriksson
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* Created : Sun Oct 21 22:00:00 2007
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* Updated : $Date$
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* $Revision$
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*/
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package se.sics.mspsim.core;
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@ -132,7 +136,9 @@ public class MSP430Core extends Chip implements MSP430Constants {
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private Flash flash;
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boolean isFlashBusy;
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ClockSystem bcs;
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public void setIO(int adr, IOUnit io, boolean word) {
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memOut[adr] = io;
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memIn[adr] = io;
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@ -224,13 +230,19 @@ public class MSP430Core extends Chip implements MSP430Constants {
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timers[i] = t;
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}
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BasicClockModule bcs = new BasicClockModule(this, memory, 0, timers);
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for (int i = 0x56, n = 0x59; i < n; i++) {
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// XXX this should be handled by the config, but we do it here to
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// avoid changing too much of the mspsim architecture for now
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if (MSP430XArch) {
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bcs = new UnifiedClockSystem(this, memory, 0, timers);
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} else {
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bcs = new BasicClockModule(this, memory, 0, timers);
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}
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for (int i = bcs.getAddressRangeMin(), n = bcs.getAddressRangeMax();
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i <= n; i++) {
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memOut[i] = bcs;
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memIn[i] = bcs;
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}
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// SFR and Basic clock system.
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ioUnits.add(sfr);
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ioUnits.add(bcs);
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@ -247,6 +259,8 @@ public class MSP430Core extends Chip implements MSP430Constants {
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memIn[config.watchdogOffset] = watchdog;
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ioUnits.add(watchdog);
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bcs.reset(0);
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}
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public Profiler getProfiler() {
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@ -349,7 +363,7 @@ public class MSP430Core extends Chip implements MSP430Constants {
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@Deprecated
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public boolean hasBreakPoint(int address) {
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return watchPoints[address] != null;
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return watchPoints[address] != null;
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}
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@Deprecated
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@ -470,7 +484,7 @@ public class MSP430Core extends Chip implements MSP430Constants {
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public int incRegister(int r, int value) {
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CPUMonitor rm = regReadMonitors[r];
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if (rm != null) {
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rm.cpuAction(CPUMonitor.REGISTER_READ, r, reg[r]);
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rm.cpuAction(CPUMonitor.REGISTER_READ, r, reg[r]);
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}
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rm = regWriteMonitors[r];
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if (rm != null) {
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@ -491,11 +505,11 @@ public class MSP430Core extends Chip implements MSP430Constants {
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lastVTime = getTime();
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lastCyclesTime = cycles;
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lastMicrosDelta = 0;
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currentDCOFactor = 1.0 * BasicClockModule.MAX_DCO_FRQ / frequency;
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// System.out.println("*** DCO: MAX:" + BasicClockModule.MAX_DCO_FRQ +
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// " current: " + frequency + " DCO_FAC = " + currentDCOFactor);
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currentDCOFactor = 1.0 * bcs.getMaxDCOFrequency() / frequency;
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/* System.out.println("*** DCO: MAX:" + bcs.getMaxDCOFrequency() +
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" current: " + frequency + " DCO_FAC = " + currentDCOFactor);*/
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if (DEBUG)
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log("Set smclkFrq: " + smclkFrq);
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dcoReset();
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@ -521,7 +535,7 @@ public class MSP430Core extends Chip implements MSP430Constants {
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// get elapsed time in seconds
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public double getTimeMillis() {
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return 1000.0 * getTime() / BasicClockModule.MAX_DCO_FRQ;
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return 1000.0 * getTime() / bcs.getMaxDCOFrequency();
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}
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private void executeEvents() {
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@ -610,7 +624,8 @@ public class MSP430Core extends Chip implements MSP430Constants {
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* @param time
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*/
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public long scheduleTimeEventMillis(TimeEvent event, double msec) {
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long time = (long) (getTime() + msec / 1000 * BasicClockModule.MAX_DCO_FRQ);
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/* System.out.println("MAX_DCO " + bcs.getMaxDCOFrequency());*/
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long time = (long) (getTime() + msec / 1000 * bcs.getMaxDCOFrequency());
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// System.out.println("Scheduling at: " + time + " (" + msec + ") getTime: " + getTime());
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scheduleTimeEvent(event, time);
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return time;
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@ -786,7 +801,7 @@ public class MSP430Core extends Chip implements MSP430Constants {
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dstAddress %= MAX_MEM;
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}
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CPUMonitor wp = watchPoints[dstAddress];
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CPUMonitor wp = watchPoints[dstAddress];
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if (wp != null) {
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wp.cpuAction(CPUMonitor.MEMORY_WRITE, dstAddress, dst);
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}
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@ -824,7 +839,6 @@ public class MSP430Core extends Chip implements MSP430Constants {
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if (wp != null) {
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wp.cpuAction(CPUMonitor.MEMORY_WRITE, dstAddress, dst);
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}
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}
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void profileCall(int dst, int pc) {
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@ -981,7 +995,7 @@ public class MSP430Core extends Chip implements MSP430Constants {
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CPUMonitor wp = watchPoints[pc];
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if (wp != null) {
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if (breakpointActive) {
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wp.cpuAction(CPUMonitor.EXECUTE, pc, 0);
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wp.cpuAction(CPUMonitor.EXECUTE, pc, 0);
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breakpointActive = false;
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return -1;
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}
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@ -992,15 +1006,33 @@ public class MSP430Core extends Chip implements MSP430Constants {
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if (wp != null) {
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wp.cpuAction(CPUMonitor.EXECUTE, pc, 0);
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}
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int pcBefore = pc;
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instruction = read(pc, MODE_WORD);
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int ext3_0 = 0;
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boolean repeatsInDstReg = false;
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boolean wordx20 = false;
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/* check for extension words */
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if ((instruction & 0xf800) == 0x1800) {
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extWord = instruction;
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ext3_0 = instruction & 0xf; /* bit 3 - 0 - either repeat count or dest 19-16 */
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pc += 2;
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// Bit 7 in the extension word indicates that the number of
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// repeats is found in the register pointed to by ext3_0. If
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// the bit is 0, ext3_0 contains the number of repeats. If the
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// bit is 1, ext3_0 contains the register number that holds
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// the number of repeats.
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if ((instruction & 0x80) == 0x80) {
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repeatsInDstReg = true;
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}
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// Bit 6 indicates whether or not the data length mode should
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// be 20 bits. A one means traditional MSP430 mode; a zero
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// indicates 20 bit mode. (XXX: there is a reserved data
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// length mode if this bit is zero and the MSP430 instruction
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// that follows the extension word also has a zero bit data
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// length mode.)
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wordx20 = (instruction & 0x40) == 0;
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instruction = read(pc, MODE_WORD);
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// System.out.println("*** Extension word!!! " + Utils.hex16(extWord) +
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// " read the instruction too: " + Utils.hex16(instruction) + " at " + Utils.hex16(pc - 2));
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@ -1016,6 +1048,7 @@ public class MSP430Core extends Chip implements MSP430Constants {
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boolean zeroCarry = false; /* msp430X can zero carry in repeats */
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boolean word = (instruction & 0x40) == 0;
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// Destination vars
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int dstRegister = 0;
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int dstAddress = -1;
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@ -1040,25 +1073,14 @@ public class MSP430Core extends Chip implements MSP430Constants {
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int srcData = (instruction & 0x0f00) >> 8;
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int dstData = (instruction & 0x000f);
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boolean rrword = true;
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switch(op) {
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// 20 bit register write
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case MOVA_IMM2REG:
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src = read(pc, MODE_WORD);
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writeRegister(PC, pc += 2);
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dst = src + (srcData << 16);
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// System.out.println("*** Writing $" + getAddressAsString(dst) + " to reg: " + dstData);
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writeRegister(dstData, dst);
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updateStatus = false;
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break;
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case MOVA_ABS2REG:
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src = read(pc, MODE_WORD);
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writeRegister(PC, pc += 2);
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dst = src + (srcData << 16);
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//System.out.println(Utils.hex20(pc) + " MOVA &ABS Reading from $" + getAddressAsString(dst) + " to reg: " + dstData);
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dst = read(dst, MODE_WORD20);
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//System.out.println(" => $" + getAddressAsString(dst));
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writeRegister(dstData, dst);
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case MOVA_IND:
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/* Read from address in src register, move to destination register. */
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writeRegister(dstData, readRegister(srcData));
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updateStatus = false;
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cycles += 3;
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break;
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case MOVA_IND_AUTOINC:
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if (profiler != null && instruction == 0x0110) {
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@ -1075,52 +1097,203 @@ public class MSP430Core extends Chip implements MSP430Constants {
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// System.out.println("*** Writing $" + getAddressAsString(dst) + " to reg: " + dstData);
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writeRegister(dstData, dst);
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updateStatus = false;
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cycles += 3;
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break;
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// case CMPA_IMM:
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// break;
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// case CMPA_REG:
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// break;
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// case ADDA_IMM - TODO - make both ADDA use the same code.
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case ADDA_REG:
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src = readRegister(srcData);
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dst = readRegister(dstData);
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int tmp = (src ^ dst) & 0x80000;
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dst = src + dst;
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int nxtCarry = (dst & 0x100000) > 0 ? CARRY : 0; /* bit 20 */
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dst &= 0xfffff;
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case MOVA_ABS2REG:
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src = read(pc, MODE_WORD);
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writeRegister(PC, pc += 2);
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dst = src + (srcData << 16);
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//System.out.println(Utils.hex20(pc) + " MOVA &ABS Reading from $" + getAddressAsString(dst) + " to reg: " + dstData);
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dst = read(dst, MODE_WORD20);
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//System.out.println(" => $" + getAddressAsString(dst));
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writeRegister(dstData, dst);
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sr = readRegister(SR);
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sr = sr & ~(NEGATIVE | OVERFLOW | CARRY | ZERO);
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// If tmp == 0 and currenly not the same sign for src & dst
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if (tmp == 0 && ((src ^ dst) & 0x80000) != 0) {
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sr |= OVERFLOW;
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// System.out.println("OVERFLOW - ADD/SUB " + Utils.hex16(src)
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// + " + " + Utils.hex16(tmpDst));
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}
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sr = sr | nxtCarry | (dst == 0 ? ZERO : 0) | ((dst & 0x80000) > 0 ? NEGATIVE : 0);
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writeRegister(SR, sr);
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updateStatus = false;
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cycles += 4;
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break;
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case MOVA_INDX2REG:
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/* Read data from address in memory, indexed by source
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* register, and place into destination register. */
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int index = read(pc, MODE_WORD);
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int indexModifier = readRegister(srcData);
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if(index > 0x8000) {
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index = -(0x10000 - index);
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}
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if(indexModifier > 0x8000) {
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indexModifier = -(0x10000 - indexModifier);
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}
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writeRegister(dstData, read(indexModifier + index, MODE_WORD20));
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writeRegister(PC, pc += 2);
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updateStatus = false;
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cycles += 4;
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break;
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case MOVA_REG2ABS:
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dst = read(pc, MODE_WORD);
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writeRegister(PC, pc += 2);
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write(dst + (dstData << 16), readRegister(srcData), MODE_WORD20);
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updateStatus = false;
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cycles += 4;
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break;
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case MOVA_REG2INDX:
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/* Read data from register, write to address in memory,
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* indexed by source register. */
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index = read(pc, MODE_WORD);
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indexModifier = readRegister(dstData);
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if(index > 0x8000) {
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index = -(0x10000 - index);
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}
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if(indexModifier > 0x8000) {
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indexModifier = -(0x10000 - indexModifier);
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}
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write(indexModifier + index, readRegister(srcData), MODE_WORD20);
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writeRegister(PC, pc += 2);
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updateStatus = false;
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cycles += 4;
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break;
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case MOVA_IMM2REG:
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src = read(pc, MODE_WORD);
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writeRegister(PC, pc += 2);
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dst = src + (srcData << 16);
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// System.out.println("*** Writing $" + getAddressAsString(dst) + " to reg: " + dstData);
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writeRegister(dstData, dst);
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updateStatus = false;
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cycles += 2;
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break;
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case ADDA_IMM:
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// For all immediate instructions, the data low 16 bits of
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// the data is stored in the following word (PC + 2) and
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// the high 4 bits in the instruction word, which we have
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// masked out as srcData.
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int immData = read(pc, MODE_WORD) + (srcData << 16);
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writeRegister(PC, pc += 2);
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dst = readRegister(dstData) + immData;
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writeRegister(dstData, dst);
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cycles += 3;
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break;
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case CMPA_IMM:
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/* Status Bits N: Set if result is negative (src > dst), reset if positive (src ≤ dst)
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Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst)
|
||||
C: Set if there is a carry from the MSB, reset otherwise
|
||||
V: Set if the subtraction of a negative source operand from a positive destination
|
||||
operand delivers a negative result, or if the subtraction of a positive source
|
||||
operand from a negative destination operand delivers a positive result, reset
|
||||
otherwise (no overflow) */
|
||||
immData = read(pc, MODE_WORD) + (srcData << 16);
|
||||
writeRegister(PC, pc += 2);
|
||||
sr = readRegister(SR);
|
||||
sr &= ~(NEGATIVE | ZERO | CARRY | OVERFLOW);
|
||||
if (readRegister(dstData) >= immData) {
|
||||
sr |= CARRY;
|
||||
}
|
||||
if (readRegister(dstData) < immData) {
|
||||
sr |= NEGATIVE;
|
||||
}
|
||||
if (readRegister(dstData) == immData) {
|
||||
sr |= ZERO;
|
||||
}
|
||||
|
||||
int cmpTmp = readRegister(dstData) - immData;
|
||||
int b = 0x80000; // CMPA always use 20 bit data length
|
||||
|
||||
if (((readRegister(dstData) ^ cmpTmp) & b) == 0 &&
|
||||
(((readRegister(dstData) ^ immData) & b) != 0)) {
|
||||
sr |= OVERFLOW;
|
||||
}
|
||||
|
||||
writeRegister(SR, sr);
|
||||
updateStatus = false;
|
||||
cycles += 3;
|
||||
break;
|
||||
|
||||
case SUBA_IMM:
|
||||
immData = read(pc, MODE_WORD) + (srcData << 16);
|
||||
writeRegister(PC, pc += 2);
|
||||
dst = readRegister(dstData) - immData;
|
||||
writeRegister(dstData, dst);
|
||||
cycles += 3;
|
||||
break;
|
||||
|
||||
case MOVA_REG:
|
||||
cycles += 1;
|
||||
writeRegister(dstData, readRegister(srcData));
|
||||
break;
|
||||
|
||||
case CMPA_REG:
|
||||
sr = readRegister(SR);
|
||||
sr &= ~(NEGATIVE | ZERO | CARRY | OVERFLOW);
|
||||
if (readRegister(dstData) >= readRegister(srcData)) {
|
||||
sr |= CARRY;
|
||||
}
|
||||
if (readRegister(dstData) < readRegister(srcData)) {
|
||||
sr |= NEGATIVE;
|
||||
}
|
||||
if (readRegister(dstData) == readRegister(srcData)) {
|
||||
sr |= ZERO;
|
||||
}
|
||||
|
||||
cmpTmp = readRegister(dstData) - readRegister(srcData);
|
||||
b = 0x80000; // CMPA always use 20 bit data length
|
||||
|
||||
if (((readRegister(dstData) ^ cmpTmp) & b) == 0 &&
|
||||
(((readRegister(dstData) ^ readRegister(srcData)) & b) != 0)) {
|
||||
sr |= OVERFLOW;
|
||||
}
|
||||
|
||||
writeRegister(SR, sr);
|
||||
updateStatus = false;
|
||||
cycles += 1;
|
||||
break;
|
||||
|
||||
case ADDA_REG:
|
||||
dst = readRegister(dstData) + readRegister(srcData);
|
||||
writeRegister(dstData, dst);
|
||||
cycles += 1;
|
||||
break;
|
||||
case SUBA_REG:
|
||||
dst = readRegister(dstData) - readRegister(srcData);
|
||||
writeRegister(dstData, dst);
|
||||
cycles += 1;
|
||||
break;
|
||||
|
||||
case RRXX_ADDR:
|
||||
rrword = false;
|
||||
case RRXX_WORD:
|
||||
int count = 1 + (instruction >> 10)& 0x03;
|
||||
int count = ((instruction >> 10) & 0x03) + 1;
|
||||
dst = readRegister(dstData);
|
||||
nxtCarry = 0;
|
||||
int nxtCarry = 0;
|
||||
int carry = (readRegister(SR) & CARRY) > 0? 1: 0;
|
||||
if (rrword) {
|
||||
dst = dst & 0xffff;
|
||||
}
|
||||
cycles += 1 + count;
|
||||
switch(instruction & RRMASK) {
|
||||
/* if word zero anything above */
|
||||
case RRCM:
|
||||
System.out.println("*** RRCM!!! not implemented");
|
||||
throw new EmulationException("**** RRCM!! not implemented");
|
||||
// break;
|
||||
/* if (rrword): Rotate right through carry the 16-bit CPU register content
|
||||
if (!rrword): Rotate right through carry the 20-bit CPU register content */
|
||||
|
||||
/* Pull the (count) lowest bits from dst - those will
|
||||
* be placed in the (count) high bits of dst after the
|
||||
* instruction is complete. */
|
||||
int dst_low = dst & ((1 << count) - 1);
|
||||
|
||||
/* Grab the bit that wlil be in the carry flag when instruction completes. */
|
||||
nxtCarry = (dst & (1 << (count + 1))) > 0? CARRY: 0;
|
||||
|
||||
/* Rotate dst. */
|
||||
dst = dst >> (count);
|
||||
|
||||
/* Rotate the high bits, insert into dst. */
|
||||
if (rrword) {
|
||||
dst |= (dst_low << (17 - count)) | (carry << (16 - count));
|
||||
} else {
|
||||
dst |= (dst_low << (21 - count)) | (carry << (20 - count));
|
||||
}
|
||||
break;
|
||||
case RRAM:
|
||||
// System.out.println("RRAM executing");
|
||||
/* roll in MSB from above */
|
||||
|
|
@ -1134,12 +1307,14 @@ public class MSP430Core extends Chip implements MSP430Constants {
|
|||
dst = dst >> 1;
|
||||
break;
|
||||
case RLAM:
|
||||
// System.out.println("RLAM executing at " + pc);
|
||||
/* just roll in "zeroes" from left */
|
||||
dst = dst << (count - 1);
|
||||
nxtCarry = (dst & (rrword ? 0x8000 : 0x80000)) > 0 ? CARRY : 0;
|
||||
dst = dst << 1;
|
||||
break;
|
||||
case RRUM:
|
||||
//System.out.println("RRUM executing");
|
||||
/* just roll in "zeroes" from right */
|
||||
dst = dst >> (count - 1);
|
||||
nxtCarry = (dst & 1) > 0 ? CARRY : 0;
|
||||
|
|
@ -1152,9 +1327,12 @@ public class MSP430Core extends Chip implements MSP430Constants {
|
|||
writeRegister(dstData, dst);
|
||||
break;
|
||||
default:
|
||||
System.out.println("MSP430X instructions not yet supported: " +
|
||||
Utils.hex16(instruction));
|
||||
throw new EmulationException("MSP430X instructions not yet supported...");
|
||||
System.out.println("MSP430X instruction not yet supported: " +
|
||||
Utils.hex16(instruction) +
|
||||
" op " + Utils.hex16(op));
|
||||
throw new EmulationException("Found unsupported MSP430X instruction " +
|
||||
Utils.hex16(instruction) +
|
||||
" op " + Utils.hex16(op));
|
||||
}
|
||||
|
||||
break;
|
||||
|
|
@ -1177,14 +1355,14 @@ public class MSP430Core extends Chip implements MSP430Constants {
|
|||
case CALLA_IMM:
|
||||
dst = (dstRegister << 16) | read(pc, MODE_WORD);
|
||||
pc += 2;
|
||||
cycles += 4;
|
||||
cycles += 5;
|
||||
break;
|
||||
case CALLA_ABS:
|
||||
/* read the address of where the address to call is */
|
||||
dst = (dstRegister << 16) | read(pc, MODE_WORD);
|
||||
dst = read(dst, MODE_WORD20);
|
||||
pc += 2;
|
||||
cycles += 4;
|
||||
cycles += 7;
|
||||
break;
|
||||
default:
|
||||
int type = MODE_WORD;
|
||||
|
|
@ -1195,6 +1373,7 @@ public class MSP430Core extends Chip implements MSP430Constants {
|
|||
case PUSHM_A:
|
||||
type = MODE_WORD20;
|
||||
size = 4;
|
||||
cycles += 2;
|
||||
case PUSHM_W:
|
||||
int n = 1 + ((instruction >> 4) & 0x0f);
|
||||
int regNo = instruction & 0x0f;
|
||||
|
|
@ -1205,6 +1384,7 @@ public class MSP430Core extends Chip implements MSP430Constants {
|
|||
/* decrease stack pointer and write n times */
|
||||
for(int i = 0; i < n; i++) {
|
||||
sp -= size;
|
||||
cycles += 2;
|
||||
write(sp, this.reg[regNo--], type);
|
||||
// System.out.println("Saved reg: " + (regNo + 1) + " was " + reg[regNo + 1]);
|
||||
|
||||
|
|
@ -1216,6 +1396,7 @@ public class MSP430Core extends Chip implements MSP430Constants {
|
|||
case POPM_A:
|
||||
type = MODE_WORD20;
|
||||
size = 4;
|
||||
cycles += 2;
|
||||
case POPM_W:
|
||||
n = 1 + ((instruction >> 4) & 0x0f);
|
||||
regNo = instruction & 0x0f;
|
||||
|
|
@ -1224,6 +1405,7 @@ public class MSP430Core extends Chip implements MSP430Constants {
|
|||
|
||||
/* read and increase stack pointer n times */
|
||||
for(int i = 0; i < n; i++) {
|
||||
cycles += 2;
|
||||
this.reg[regNo++] = read(sp, type);
|
||||
// System.out.println("Restored reg: " + (regNo - 1) + " to " + reg[regNo - 1]);
|
||||
sp += size;
|
||||
|
|
@ -1305,7 +1487,7 @@ public class MSP430Core extends Chip implements MSP430Constants {
|
|||
break;
|
||||
// Bugfix suggested by Matt Thompson
|
||||
case AM_IND_AUTOINC:
|
||||
if(dstRegister == PC) {
|
||||
if (dstRegister == PC) {
|
||||
dstAddress = readRegister(PC);
|
||||
pc += 2;
|
||||
writeRegister(PC, pc);
|
||||
|
|
@ -1322,15 +1504,19 @@ public class MSP430Core extends Chip implements MSP430Constants {
|
|||
if (dstRegMode) {
|
||||
dst = readRegisterCG(dstRegister, ad);
|
||||
|
||||
if (!word) {
|
||||
if (word) {
|
||||
dst &= 0xffff;
|
||||
} else if (wordx20) {
|
||||
dst &= 0xfffff;
|
||||
} else {
|
||||
dst &= 0xff;
|
||||
}
|
||||
/* set the repeat here! */
|
||||
if ((extWord & EXTWORD_REPEAT) > 0) {
|
||||
repeats = 1 + readRegister(ext3_0) & 0xf;
|
||||
} else {
|
||||
repeats = 1 + ext3_0;
|
||||
}
|
||||
if (repeatsInDstReg) {
|
||||
repeats = 1 + readRegister(ext3_0);
|
||||
} else {
|
||||
repeats = 1 + ext3_0;
|
||||
}
|
||||
zeroCarry = (extWord & EXTWORD_ZC) > 0;
|
||||
|
||||
// if (repeats > 1) {
|
||||
|
|
@ -1357,9 +1543,12 @@ public class MSP430Core extends Chip implements MSP430Constants {
|
|||
dst = dst >> 1;
|
||||
if (word) {
|
||||
dst |= (sr & CARRY) > 0 ? 0x8000 : 0;
|
||||
} else if (wordx20) {
|
||||
dst |= (sr & CARRY) > 0 ? 0x80000 : 0;
|
||||
} else {
|
||||
dst |= (sr & CARRY) > 0 ? 0x80 : 0;
|
||||
}
|
||||
|
||||
// Indicate write to memory!!
|
||||
write = true;
|
||||
// Set the next carry!
|
||||
|
|
@ -1374,6 +1563,8 @@ public class MSP430Core extends Chip implements MSP430Constants {
|
|||
nxtCarry = (dst & 1) > 0 ? CARRY : 0;
|
||||
if (word) {
|
||||
dst = (dst & 0x8000) | (dst >> 1);
|
||||
} else if (wordx20) {
|
||||
dst = (dst & 0x80000) | (dst >> 1);
|
||||
} else {
|
||||
dst = (dst & 0x80) | (dst >> 1);
|
||||
}
|
||||
|
|
@ -1382,7 +1573,7 @@ public class MSP430Core extends Chip implements MSP430Constants {
|
|||
break;
|
||||
case SXT:
|
||||
// Extend Sign (bit 8-15 => same as bit 7)
|
||||
dst = (dst & 0x80) > 0 ? dst | 0xff00 : dst & 0x7f;
|
||||
dst = (dst & 0x80) > 0 ? dst | 0xfff00 : dst & 0x7f;
|
||||
write = true;
|
||||
sr = sr & ~(CARRY | OVERFLOW);
|
||||
if (dst != 0) {
|
||||
|
|
@ -1461,10 +1652,12 @@ public class MSP430Core extends Chip implements MSP430Constants {
|
|||
Utils.hex16(instruction));
|
||||
}
|
||||
if (repeats > 0) {
|
||||
if (!word) {
|
||||
dst &= 0xff;
|
||||
if (word) {
|
||||
dst &= 0xffff;
|
||||
} else if (wordx20) {
|
||||
dst &= 0xfffff;
|
||||
} else {
|
||||
dst &= 0xffff;
|
||||
dst &= 0xff;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1534,7 +1727,11 @@ public class MSP430Core extends Chip implements MSP430Constants {
|
|||
// Some CGs should be handled as registry reads only...
|
||||
if ((srcRegister == CG1 && as > AM_INDEX) || srcRegister == CG2) {
|
||||
src = CREG_VALUES[srcRegister - 2][as];
|
||||
if (!word) {
|
||||
if (word) {
|
||||
src &= 0xffff;
|
||||
} else if (wordx20) {
|
||||
src &= 0xfffff;
|
||||
} else {
|
||||
src &= 0xff;
|
||||
}
|
||||
cycles += dstRegMode ? 1 : 4;
|
||||
|
|
@ -1544,8 +1741,12 @@ public class MSP430Core extends Chip implements MSP430Constants {
|
|||
case AM_REG:
|
||||
// CG handled above!
|
||||
src = readRegister(srcRegister);
|
||||
if (!word) {
|
||||
src &= 0xff;
|
||||
if (word) {
|
||||
src &= 0xffff;
|
||||
} else if (wordx20) {
|
||||
src &= 0xfffff;
|
||||
} else {
|
||||
src &= 0xff;
|
||||
}
|
||||
cycles += dstRegMode ? 1 : 4;
|
||||
/* add cycle if destination register = PC */
|
||||
|
|
@ -1554,11 +1755,12 @@ public class MSP430Core extends Chip implements MSP430Constants {
|
|||
if (dstRegMode) {
|
||||
/* possible to have repeat, etc... */
|
||||
/* TODO: decode the # also */
|
||||
if ((extWord & EXTWORD_REPEAT) > 0) {
|
||||
repeats = 1 + readRegister(ext3_0) & 0xf;
|
||||
} else {
|
||||
repeats = 1 + ext3_0;
|
||||
}
|
||||
if (repeatsInDstReg) {
|
||||
repeats = 1 + readRegister(ext3_0);
|
||||
} else {
|
||||
repeats = 1 + ext3_0;
|
||||
}
|
||||
|
||||
zeroCarry = (extWord & EXTWORD_ZC) > 0;
|
||||
}
|
||||
|
||||
|
|
@ -1602,9 +1804,13 @@ public class MSP430Core extends Chip implements MSP430Constants {
|
|||
if (dstRegMode) {
|
||||
if (op != MOV) {
|
||||
dst = readRegister(dstRegister);
|
||||
if (!word) {
|
||||
dst &= 0xff;
|
||||
}
|
||||
if (word) {
|
||||
dst &= 0xffff;
|
||||
} else if (wordx20) {
|
||||
dst &= 0xfffff;
|
||||
} else {
|
||||
dst &= 0xff;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
// PC Could have changed above!
|
||||
|
|
@ -1689,17 +1895,17 @@ public class MSP430Core extends Chip implements MSP430Constants {
|
|||
case ADD: // ADD
|
||||
// Tmp gives zero if same sign! if sign is different after -> overf.
|
||||
sr &= ~(OVERFLOW | CARRY);
|
||||
|
||||
tmp = (src ^ dst) & (word ? 0x8000 : 0x80);
|
||||
int b = word ? 0x8000 : (wordx20 ? 0x80000 : 0x80);
|
||||
tmp = (src ^ dst) & b;
|
||||
// Includes carry if carry should be added...
|
||||
|
||||
dst = dst + src + tmpAdd;
|
||||
|
||||
if (dst > (word ? 0xffff : 0xff)) {
|
||||
int b2 = word ? 0xffff : (wordx20 ? 0xfffff : 0xff);
|
||||
if (dst > b2) {
|
||||
sr |= CARRY;
|
||||
}
|
||||
// If tmp == 0 and currenly not the same sign for src & dst
|
||||
if (tmp == 0 && ((src ^ dst) & (word ? 0x8000 : 0x80)) != 0) {
|
||||
if (tmp == 0 && ((src ^ dst) & b) != 0) {
|
||||
sr |= OVERFLOW;
|
||||
// System.out.println("OVERFLOW - ADD/SUB " + Utils.hex16(src)
|
||||
// + " + " + Utils.hex16(tmpDst));
|
||||
|
|
@ -1712,7 +1918,7 @@ public class MSP430Core extends Chip implements MSP430Constants {
|
|||
break;
|
||||
case CMP: // CMP
|
||||
// Set CARRY if A >= B, and it's clear if A < B
|
||||
int b = word ? 0x8000 : 0x80;
|
||||
b = word ? 0x8000 : (wordx20 ? 0x80000 : 0x80);
|
||||
sr = (sr & ~(CARRY | OVERFLOW)) | (dst >= src ? CARRY : 0);
|
||||
|
||||
tmp = (dst - src);
|
||||
|
|
@ -1760,7 +1966,8 @@ public class MSP430Core extends Chip implements MSP430Constants {
|
|||
break;
|
||||
case XOR: // XOR
|
||||
sr = sr & ~(CARRY | OVERFLOW);
|
||||
if ((src & (word ? 0x8000 : 0x80)) != 0 && (dst & (word ? 0x8000 : 0x80)) != 0) {
|
||||
b = word ? 0x8000 : (wordx20 ? 0x80000 : 0x80);
|
||||
if ((src & b) != 0 && (dst & b) != 0) {
|
||||
sr |= OVERFLOW;
|
||||
}
|
||||
dst = src ^ dst;
|
||||
|
|
@ -1790,12 +1997,14 @@ public class MSP430Core extends Chip implements MSP430Constants {
|
|||
/* If we have the same register as dst and src then copy here to get input
|
||||
* in next loop
|
||||
*/
|
||||
if(repeats > 0 && srcRegister == dstRegister) {
|
||||
if (repeats > 0 && srcRegister == dstRegister) {
|
||||
src = dst;
|
||||
if (!word) {
|
||||
src &= 0xff;
|
||||
if (word) {
|
||||
src &= 0xffff;
|
||||
} else if (wordx20) {
|
||||
src &= 0xfffff;
|
||||
} else {
|
||||
src &= 0xffff;
|
||||
src &= 0xff;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1804,6 +2013,8 @@ public class MSP430Core extends Chip implements MSP430Constants {
|
|||
/* Processing after each instruction */
|
||||
if (word) {
|
||||
dst &= 0xffff;
|
||||
} else if (wordx20) {
|
||||
dst &= 0xfffff;
|
||||
} else {
|
||||
dst &= 0xff;
|
||||
}
|
||||
|
|
@ -1822,7 +2033,8 @@ public class MSP430Core extends Chip implements MSP430Constants {
|
|||
sr = (sr & ~(ZERO | NEGATIVE)) |
|
||||
((dst == 0) ? ZERO : 0) |
|
||||
(word ? ((dst & 0x8000) > 0 ? NEGATIVE : 0) :
|
||||
((dst & 0x80) > 0 ? NEGATIVE : 0));
|
||||
(wordx20 ? ((dst & 0x80000) > 0 ? NEGATIVE : 0) :
|
||||
((dst & 0x80) > 0 ? NEGATIVE : 0)));
|
||||
writeRegister(SR, sr);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,396 @@
|
|||
/**
|
||||
* Copyright (c) 2007, Swedish Institute of Computer Science.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the Institute nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* This file is part of MSPSim.
|
||||
*
|
||||
* $Id$
|
||||
*
|
||||
* -----------------------------------------------------------------
|
||||
*
|
||||
* UnifiedClockSystem
|
||||
*
|
||||
* Author : Joakim Eriksson
|
||||
* Author : Adam Dunkels
|
||||
* Created : Sun Oct 21 22:00:00 2007
|
||||
* Updated : $Date$
|
||||
* $Revision$
|
||||
*/
|
||||
|
||||
package se.sics.mspsim.core;
|
||||
import se.sics.mspsim.util.Utils;
|
||||
|
||||
public class UnifiedClockSystem extends ClockSystem {
|
||||
|
||||
private static final int UCSCTL0 = 0x0160;
|
||||
private static final int UCSCTL1 = 0x0162;
|
||||
private static final int UCSCTL2 = 0x0164;
|
||||
private static final int UCSCTL3 = 0x0166;
|
||||
private static final int UCSCTL4 = 0x0168;
|
||||
private static final int UCSCTL5 = 0x016a;
|
||||
private static final int UCSCTL6 = 0x016c;
|
||||
private static final int UCSCTL7 = 0x016e;
|
||||
private static final int UCSCTL8 = 0x0170;
|
||||
|
||||
/* UCSCTL0 Control Bits */
|
||||
// private static final int RESERVED = 0x0001; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0002; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0004; /* RESERVED */
|
||||
private static final int MOD_BITPOS = 3;
|
||||
private static final int MOD_BITWIDTH = 5;
|
||||
private static final int MOD0 = 0x0008; /* Modulation Bit Counter Bit : 0 */
|
||||
private static final int MOD1 = 0x0010; /* Modulation Bit Counter Bit : 1 */
|
||||
private static final int MOD2 = 0x0020; /* Modulation Bit Counter Bit : 2 */
|
||||
private static final int MOD3 = 0x0040; /* Modulation Bit Counter Bit : 3 */
|
||||
private static final int MOD4 = 0x0080; /* Modulation Bit Counter Bit : 4 */
|
||||
|
||||
private static final int DCO_BITPOS = 8;
|
||||
private static final int DCO_BITWIDTH = 5;
|
||||
private static final int DCO0 = 0x0100; /* DCO TAP Bit : 0 */
|
||||
private static final int DCO1 = 0x0200; /* DCO TAP Bit : 1 */
|
||||
private static final int DCO2 = 0x0400; /* DCO TAP Bit : 2 */
|
||||
private static final int DCO3 = 0x0800; /* DCO TAP Bit : 3 */
|
||||
private static final int DCO4 = 0x1000; /* DCO TAP Bit : 4 */
|
||||
// private static final int RESERVED = 0x2000; /* RESERVED */
|
||||
// private static final int RESERVED = 0x4000; /* RESERVED */
|
||||
// private static final int RESERVED = 0x8000; /* RESERVED */
|
||||
|
||||
|
||||
/* UCSCTL1 Control Bits */
|
||||
private static final int DISMOD = 0x0001; /* Disable Modulation */
|
||||
// private static final int RESERVED = 0x0002; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0004; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0008; /* RESERVED */
|
||||
private static final int DCORSEL_BITPOS = 4;
|
||||
private static final int DCORSEL_BITWIDTH = 3;
|
||||
private static final int DCORSEL0 = 0x0010; /* DCO Freq. Range Select Bit : 0 */
|
||||
private static final int DCORSEL1 = 0x0020; /* DCO Freq. Range Select Bit : 1 */
|
||||
private static final int DCORSEL2 = 0x0040; /* DCO Freq. Range Select Bit : 2 */
|
||||
// private static final int RESERVED = 0x0080; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0100; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0200; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0400; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0800; /* RESERVED */
|
||||
// private static final int RESERVED = 0x1000; /* RESERVED */
|
||||
// private static final int RESERVED = 0x2000; /* RESERVED */
|
||||
// private static final int RESERVED = 0x4000; /* RESERVED */
|
||||
// private static final int RESERVED = 0x8000; /* RESERVED */
|
||||
|
||||
|
||||
/* UCSCTL2 Control Bits */
|
||||
private static final int FLLN_BITPOS = 0;
|
||||
private static final int FLLN_BITWIDTH = 10;
|
||||
private static final int FLLN0 = 0x0001; /* FLL Multipier Bit : 0 */
|
||||
private static final int FLLN1 = 0x0002; /* FLL Multipier Bit : 1 */
|
||||
private static final int FLLN2 = 0x0004; /* FLL Multipier Bit : 2 */
|
||||
private static final int FLLN3 = 0x0008; /* FLL Multipier Bit : 3 */
|
||||
private static final int FLLN4 = 0x0010; /* FLL Multipier Bit : 4 */
|
||||
private static final int FLLN5 = 0x0020; /* FLL Multipier Bit : 5 */
|
||||
private static final int FLLN6 = 0x0040; /* FLL Multipier Bit : 6 */
|
||||
private static final int FLLN7 = 0x0080; /* FLL Multipier Bit : 7 */
|
||||
private static final int FLLN8 = 0x0100; /* FLL Multipier Bit : 8 */
|
||||
private static final int FLLN9 = 0x0200; /* FLL Multipier Bit : 9 */
|
||||
// private static final int RESERVED = 0x0400; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0800; /* RESERVED */
|
||||
private static final int FLLD_BITPOS = 12;
|
||||
private static final int FLLD_BITWIDTH = 3;
|
||||
private static final int FLLD0 = 0x1000; /* Loop Divider Bit : 0 */
|
||||
private static final int FLLD1 = 0x2000; /* Loop Divider Bit : 1 */
|
||||
private static final int FLLD2 = 0x4000; /* Loop Divider Bit : 1 */
|
||||
// private static final int RESERVED = 0x8000; /* RESERVED */
|
||||
|
||||
|
||||
/* UCSCTL3 Control Bits */
|
||||
private static final int FLLREFDIV_BITPOS = 0;
|
||||
private static final int FLLREFDIV_BITWIDTH = 3;
|
||||
private static final int FLLREFDIV0 = 0x0001; /* Reference Divider Bit : 0 */
|
||||
private static final int FLLREFDIV1 = 0x0002; /* Reference Divider Bit : 1 */
|
||||
private static final int FLLREFDIV2 = 0x0004; /* Reference Divider Bit : 2 */
|
||||
// private static final int RESERVED = 0x0008; /* RESERVED */
|
||||
private static final int SELREF_BITPOS = 4;
|
||||
private static final int SELREF_BITWIDTH = 3;
|
||||
private static final int SELREF0 = 0x0010; /* FLL Reference Clock Select Bit : 0 */
|
||||
private static final int SELREF1 = 0x0020; /* FLL Reference Clock Select Bit : 1 */
|
||||
private static final int SELREF2 = 0x0040; /* FLL Reference Clock Select Bit : 2 */
|
||||
// private static final int RESERVED = 0x0080; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0100; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0200; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0400; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0800; /* RESERVED */
|
||||
// private static final int RESERVED = 0x1000; /* RESERVED */
|
||||
// private static final int RESERVED = 0x2000; /* RESERVED */
|
||||
// private static final int RESERVED = 0x4000; /* RESERVED */
|
||||
// private static final int RESERVED = 0x8000; /* RESERVED */
|
||||
|
||||
/* UCSCTL3 Control Bits */
|
||||
|
||||
private static final int FLLREFDIV_0 = 0x0000; /* Reference Divider: f(LFCLK);/1 */
|
||||
private static final int FLLREFDIV_1 = 0x0001; /* Reference Divider: f(LFCLK);/2 */
|
||||
private static final int FLLREFDIV_2 = 0x0002; /* Reference Divider: f(LFCLK);/4 */
|
||||
private static final int FLLREFDIV_3 = 0x0003; /* Reference Divider: f(LFCLK);/8 */
|
||||
private static final int FLLREFDIV_4 = 0x0004; /* Reference Divider: f(LFCLK);/12 */
|
||||
private static final int FLLREFDIV_5 = 0x0005; /* Reference Divider: f(LFCLK);/16 */
|
||||
private static final int FLLREFDIV_6 = 0x0006; /* Reference Divider: f(LFCLK);/16 */
|
||||
private static final int FLLREFDIV_7 = 0x0007; /* Reference Divider: f(LFCLK);/16 */
|
||||
private static final int FLLREFDIV__1 = 0x0000; /* Reference Divider: f(LFCLK);/1 */
|
||||
private static final int FLLREFDIV__2 = 0x0001; /* Reference Divider: f(LFCLK);/2 */
|
||||
private static final int FLLREFDIV__4 = 0x0002; /* Reference Divider: f(LFCLK);/4 */
|
||||
private static final int FLLREFDIV__8 = 0x0003; /* Reference Divider: f(LFCLK);/8 */
|
||||
private static final int FLLREFDIV__12 = 0x0004; /* Reference Divider: f(LFCLK);/12 */
|
||||
private static final int FLLREFDIV__16 = 0x0005; /* Reference Divider: f(LFCLK);/16 */
|
||||
private static final int SELREF_0 = 0x0000; /* FLL Reference Clock Select 0 */
|
||||
private static final int SELREF_1 = 0x0010; /* FLL Reference Clock Select 1 */
|
||||
private static final int SELREF_2 = 0x0020; /* FLL Reference Clock Select 2 */
|
||||
private static final int SELREF_3 = 0x0030; /* FLL Reference Clock Select 3 */
|
||||
private static final int SELREF_4 = 0x0040; /* FLL Reference Clock Select 4 */
|
||||
private static final int SELREF_5 = 0x0050; /* FLL Reference Clock Select 5 */
|
||||
private static final int SELREF_6 = 0x0060; /* FLL Reference Clock Select 6 */
|
||||
private static final int SELREF_7 = 0x0070; /* FLL Reference Clock Select 7 */
|
||||
private static final int SELREF__XT1CLK = 0x0000; /* Multiply Selected Loop Freq. By XT1CLK */
|
||||
private static final int SELREF__REFOCLK = 0x0020; /* Multiply Selected Loop Freq. By REFOCLK */
|
||||
private static final int SELREF__XT2CLK = 0x0050; /* Multiply Selected Loop Freq. By XT2CLK */
|
||||
|
||||
/* UCSCTL4 Control Bits */
|
||||
private static final int SELM0 = 0x0001; /* MCLK Source Select Bit: 0 */
|
||||
private static final int SELM1 = 0x0002; /* MCLK Source Select Bit: 1 */
|
||||
private static final int SELM2 = 0x0004; /* MCLK Source Select Bit: 2 */
|
||||
// private static final int RESERVED = 0x0008; /* RESERVED */
|
||||
private static final int SELS0 = 0x0010; /* SMCLK Source Select Bit: 0 */
|
||||
private static final int SELS1 = 0x0020; /* SMCLK Source Select Bit: 1 */
|
||||
private static final int SELS2 = 0x0040; /* SMCLK Source Select Bit: 2 */
|
||||
// private static final int RESERVED = 0x0080; /* RESERVED */
|
||||
private static final int SELA0 = 0x0100; /* ACLK Source Select Bit: 0 */
|
||||
private static final int SELA1 = 0x0200; /* ACLK Source Select Bit: 1 */
|
||||
private static final int SELA2 = 0x0400; /* ACLK Source Select Bit: 2 */
|
||||
// private static final int RESERVED = 0x0800; /* RESERVED */
|
||||
// private static final int RESERVED = 0x1000; /* RESERVED */
|
||||
// private static final int RESERVED = 0x2000; /* RESERVED */
|
||||
// private static final int RESERVED = 0x4000; /* RESERVED */
|
||||
// private static final int RESERVED = 0x8000; /* RESERVED */
|
||||
|
||||
/* UCSCTL4 Control Bits */
|
||||
private static final int SELM__XT1CLK = 0x0000; /* MCLK Source Select XT1CLK */
|
||||
private static final int SELM__VLOCLK = 0x0001; /* MCLK Source Select VLOCLK */
|
||||
private static final int SELM__REFOCLK = 0x0002; /* MCLK Source Select REFOCLK */
|
||||
private static final int SELM__DCOCLK = 0x0003; /* MCLK Source Select DCOCLK */
|
||||
private static final int SELM__DCOCLKDIV = 0x0004; /* MCLK Source Select DCOCLKDIV */
|
||||
private static final int SELM__XT2CLK = 0x0005; /* MCLK Source Select XT2CLK */
|
||||
|
||||
private static final int SELS__XT1CLK = 0x0000; /* SMCLK Source Select XT1CLK */
|
||||
private static final int SELS__VLOCLK = 0x0010; /* SMCLK Source Select VLOCLK */
|
||||
private static final int SELS__REFOCLK = 0x0020; /* SMCLK Source Select REFOCLK */
|
||||
private static final int SELS__DCOCLK = 0x0030; /* SMCLK Source Select DCOCLK */
|
||||
private static final int SELS__DCOCLKDIV = 0x0040; /* SMCLK Source Select DCOCLKDIV */
|
||||
private static final int SELS__XT2CLK = 0x0050; /* SMCLK Source Select XT2CLK */
|
||||
|
||||
private static final int SELA__XT1CLK = 0x0000; /* ACLK Source Select XT1CLK */
|
||||
private static final int SELA__VLOCLK = 0x0100; /* ACLK Source Select VLOCLK */
|
||||
private static final int SELA__REFOCLK = 0x0200; /* ACLK Source Select REFOCLK */
|
||||
private static final int SELA__DCOCLK = 0x0300; /* ACLK Source Select DCOCLK */
|
||||
private static final int SELA__DCOCLKDIV = 0x0400; /* ACLK Source Select DCOCLKDIV */
|
||||
private static final int SELA__XT2CLK = 0x0500; /* ACLK Source Select XT2CLK */
|
||||
|
||||
/* UCSCTL5 Control Bits */
|
||||
private static final int DIVM0 = 0x0001; /* MCLK Divider Bit: 0 */
|
||||
private static final int DIVM1 = 0x0002; /* MCLK Divider Bit: 1 */
|
||||
private static final int DIVM2 = 0x0004; /* MCLK Divider Bit: 2 */
|
||||
// private static final int RESERVED = 0x0008; /* RESERVED */
|
||||
private static final int DIVS_BITPOS = 4;
|
||||
private static final int DIVS_BITWIDTH = 3;
|
||||
private static final int DIVS0 = 0x0010; /* SMCLK Divider Bit: 0 */
|
||||
private static final int DIVS1 = 0x0020; /* SMCLK Divider Bit: 1 */
|
||||
private static final int DIVS2 = 0x0040; /* SMCLK Divider Bit: 2 */
|
||||
// private static final int RESERVED = 0x0080; /* RESERVED */
|
||||
private static final int DIVA0 = 0x0100; /* ACLK Divider Bit: 0 */
|
||||
private static final int DIVA1 = 0x0200; /* ACLK Divider Bit: 1 */
|
||||
private static final int DIVA2 = 0x0400; /* ACLK Divider Bit: 2 */
|
||||
// private static final int RESERVED = 0x0800; /* RESERVED */
|
||||
private static final int DIVPA0 = 0x1000; /* ACLK from Pin Divider Bit: 0 */
|
||||
private static final int DIVPA1 = 0x2000; /* ACLK from Pin Divider Bit: 1 */
|
||||
private static final int DIVPA2 = 0x4000; /* ACLK from Pin Divider Bit: 2 */
|
||||
// private static final int RESERVED = 0x8000; /* RESERVED */
|
||||
|
||||
/* UCSCTL6 Control Bits */
|
||||
private static final int XT1OFF = 0x0001; /* High Frequency Oscillator 1 (XT1); disable */
|
||||
private static final int SMCLKOFF = 0x0002; /* SMCLK Off */
|
||||
private static final int XCAP0 = 0x0004; /* XIN/XOUT Cap Bit: 0 */
|
||||
private static final int XCAP1 = 0x0008; /* XIN/XOUT Cap Bit: 1 */
|
||||
private static final int XT1BYPASS = 0x0010; /* XT1 bypass mode : 0: internal 1:sourced from external pin */
|
||||
private static final int XTS = 0x0020; /* 1: Selects high-freq. oscillator */
|
||||
private static final int XT1DRIVE0 = 0x0040; /* XT1 Drive Level mode Bit 0 */
|
||||
private static final int XT1DRIVE1 = 0x0080; /* XT1 Drive Level mode Bit 1 */
|
||||
private static final int XT2OFF = 0x0100; /* High Frequency Oscillator 2 (XT2); disable */
|
||||
// private static final int RESERVED = 0x0200; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0400; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0800; /* RESERVED */
|
||||
private static final int XT2BYPASS = 0x1000; /* XT2 bypass mode : 0: internal 1:sourced from external pin */
|
||||
// private static final int RESERVED = 0x2000; /* RESERVED */
|
||||
private static final int XT2DRIVE0 = 0x4000; /* XT2 Drive Level mode Bit 0 */
|
||||
private static final int XT2DRIVE1 = 0x8000; /* XT2 Drive Level mode Bit 1 */
|
||||
|
||||
/* UCSCTL7 Control Bits */
|
||||
private static final int DCOFFG = 0x0001; /* DCO Fault Flag */
|
||||
private static final int XT1LFOFFG = 0x0002; /* XT1 Low Frequency Oscillator Fault Flag */
|
||||
private static final int XT1HFOFFG = 0x0004; /* XT1 High Frequency Oscillator 1 Fault Flag */
|
||||
private static final int XT2OFFG = 0x0008; /* High Frequency Oscillator 2 Fault Flag */
|
||||
// private static final int RESERVED = 0x0010; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0020; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0040; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0080; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0100; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0200; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0400; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0800; /* RESERVED */
|
||||
// private static final int RESERVED = 0x1000; /* RESERVED */
|
||||
// private static final int RESERVED = 0x2000; /* RESERVED */
|
||||
// private static final int RESERVED = 0x4000; /* RESERVED */
|
||||
// private static final int RESERVED = 0x8000; /* RESERVED */
|
||||
|
||||
/* UCSCTL8 Control Bits */
|
||||
private static final int ACLKREQEN = 0x0001; /* ACLK Clock Request Enable */
|
||||
private static final int MCLKREQEN = 0x0002; /* MCLK Clock Request Enable */
|
||||
private static final int SMCLKREQEN = 0x0004; /* SMCLK Clock Request Enable */
|
||||
private static final int MODOSCREQEN = 0x0008; /* MODOSC Clock Request Enable */
|
||||
// private static final int RESERVED = 0x0010; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0020; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0040; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0080; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0100; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0200; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0400; /* RESERVED */
|
||||
// private static final int RESERVED = 0x0800; /* RESERVED */
|
||||
// private static final int RESERVED = 0x1000; /* RESERVED */
|
||||
// private static final int RESERVED = 0x2000; /* RESERVED */
|
||||
// private static final int RESERVED = 0x4000; /* RESERVED */
|
||||
// private static final int RESERVED = 0x8000; /* RESERVED */
|
||||
|
||||
|
||||
private static final int ACLK_FRQ = 32768;
|
||||
private static final int MAX_DCO_FRQ = 16000000;
|
||||
|
||||
|
||||
private MSP430Core core;
|
||||
private Timer[] timers;
|
||||
|
||||
private int currentDcoFrequency;
|
||||
|
||||
/**
|
||||
* Creates a new <code>UnifiedClockSystem</code> instance.
|
||||
*
|
||||
*/
|
||||
public UnifiedClockSystem(MSP430Core core, int[] memory, int offset, Timer[] timers) {
|
||||
super("UnifiedClockSystem", memory, offset);
|
||||
this.core = core;
|
||||
this.timers = timers;
|
||||
}
|
||||
|
||||
public int getMaxDCOFrequency() {
|
||||
return MAX_DCO_FRQ;
|
||||
}
|
||||
|
||||
public int getAddressRangeMin() {
|
||||
return UCSCTL0;
|
||||
}
|
||||
|
||||
public int getAddressRangeMax() {
|
||||
return UCSCTL8;
|
||||
}
|
||||
|
||||
public void reset(int type) {
|
||||
// Set the reset states, according to the SLAU208h data sheet.
|
||||
write(UCSCTL0, 0x0000, true, core.cycles);
|
||||
write(UCSCTL1, 0x0020, true, core.cycles);
|
||||
write(UCSCTL2, 0x101f, true, core.cycles);
|
||||
write(UCSCTL3, 0x0000, true, core.cycles);
|
||||
write(UCSCTL4, 0x0044, true, core.cycles);
|
||||
write(UCSCTL5, 0x0000, true, core.cycles);
|
||||
write(UCSCTL6, 0xc1cd, true, core.cycles);
|
||||
write(UCSCTL7, 0x0703, true, core.cycles);
|
||||
write(UCSCTL8, 0x0707, true, core.cycles);
|
||||
}
|
||||
|
||||
// do nothing?
|
||||
public int read(int address, boolean word, long cycles) {
|
||||
int val = memory[address];
|
||||
if (word) {
|
||||
val |= memory[(address + 1) & 0xffff] << 8;
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
public void write(int address, int data, boolean word, long cycles) {
|
||||
// Currently ignores the word flag...
|
||||
if (DEBUG) log("Write to UnifiedClockSystem: " +
|
||||
Utils.hex16(address) + " => " + Utils.hex16(data));
|
||||
|
||||
memory[address] = data & 0xff;
|
||||
if (word) memory[address + 1] = (data >> 8) & 0xff;
|
||||
|
||||
setConfiguration(cycles);
|
||||
}
|
||||
|
||||
public void interruptServiced(int vector) {
|
||||
}
|
||||
|
||||
|
||||
private void setConfiguration(long cycles) {
|
||||
// Read a configuration from the UCSCTL* registers and compute the timer setup
|
||||
|
||||
// Read Modulation counter and DCO TAP from UCSCTL0 (currently unused)
|
||||
int modulationBitCounter = ((read(UCSCTL0, true, cycles) >> MOD_BITPOS) & ((1 << MOD_BITWIDTH) - 1));
|
||||
int dcoTap = ((read(UCSCTL0, true, cycles) >> DCO_BITPOS) & ((1 << DCO_BITWIDTH) - 1));
|
||||
|
||||
// Read modulation disable bit (currently unused)
|
||||
int disableModulation = ((read(UCSCTL1, true, cycles) & DISMOD));
|
||||
|
||||
// Read DCO range selection from UCSCTL1 register
|
||||
int dcoRange = ((read(UCSCTL1, true, cycles) >> DCORSEL_BITPOS) & ((1 << DCORSEL_BITWIDTH) - 1));
|
||||
|
||||
// Read DCO FLL multiplier and loop divider from the UCSCTL2 register
|
||||
int dcoFLLMultiplier = (read(UCSCTL2, true, cycles) >> FLLN_BITPOS) & ((1 << FLLN_BITWIDTH) - 1);
|
||||
int dcoLoopDivider = (read(UCSCTL2, true, cycles) >> FLLD_BITPOS) & ((1 << FLLD_BITWIDTH) - 1);
|
||||
|
||||
// FLL reference clock divider and selection from UCSCTL3 (currently unused)
|
||||
int fllRefDiv = (read(UCSCTL3, true, cycles) >> FLLREFDIV_BITPOS) & ((1 << FLLREFDIV_BITWIDTH) - 1);
|
||||
int selRef = (read(UCSCTL3, true, cycles) >> SELREF_BITPOS) & ((1 << SELREF_BITWIDTH) - 1);
|
||||
|
||||
// SMCLK divisor
|
||||
int divSMclk = (read(UCSCTL5, true, cycles) >> DIVS_BITPOS) & ((1 << DIVS_BITWIDTH) - 1);
|
||||
|
||||
int newDcoFrequency = (dcoFLLMultiplier + 1) * ACLK_FRQ;
|
||||
|
||||
if (newDcoFrequency != currentDcoFrequency) {
|
||||
currentDcoFrequency = newDcoFrequency;
|
||||
core.setDCOFrq(currentDcoFrequency, currentDcoFrequency / (1 << divSMclk));
|
||||
|
||||
if (timers != null) {
|
||||
for(int i = 0; i < timers.length; i++) {
|
||||
timers[i].resetCounter(cycles);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -27,12 +27,16 @@
|
|||
*
|
||||
* This file is part of MSPSim.
|
||||
*
|
||||
* $Id$
|
||||
*
|
||||
* -----------------------------------------------------------------
|
||||
*
|
||||
* MapTable
|
||||
*
|
||||
* Author : Joakim Eriksson
|
||||
* Created : Sun Oct 21 22:00:00 2007
|
||||
* Updated : $Date$
|
||||
* $Revision$
|
||||
*/
|
||||
|
||||
package se.sics.mspsim.util;
|
||||
|
|
@ -261,7 +265,7 @@ public class MapTable {
|
|||
int totsize = 0;
|
||||
int totdata = map.dataFill, totbss = map.bssFill;
|
||||
int totmemory = totdata + totbss;
|
||||
System.out.printf("%7s %7s %7s %4s %s\n",
|
||||
System.out.printf("%6s %6s %6s %4s %s\n",
|
||||
"text", "data", "bss", "addr", "name");
|
||||
for (int i = 0; i < map.modules.size(); i++) {
|
||||
MapEntry module = map.modules.get(i);
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ public class StackMonitor implements CPUMonitor {
|
|||
|
||||
public StackMonitor(MSP430 cpu) {
|
||||
this.cpu = cpu;
|
||||
this.cpu.addRegisterWriteMonitor(MSP430.SP, this);
|
||||
this.cpu.setRegisterWriteMonitor(MSP430.SP, this);
|
||||
Object p = cpu.getRegistry().getComponent("profiler");
|
||||
if (p instanceof SimpleProfiler) {
|
||||
((SimpleProfiler) p).setStackMonitor(this);
|
||||
|
|
|
|||
Loading…
Reference in New Issue