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Add cast transdata operators register format.

This commit is contained in:
liangchenghui 2021-11-29 11:22:55 +08:00
parent 274444b4a0
commit 10a648081c
2 changed files with 3 additions and 0 deletions
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1
mindspore/ops/_op_impl/aicpu/cast.py
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@ -104,6 +104,7 @@ cast_op_info = AiCPURegOp("Cast") \
.dtype_format(DataType.I32_Default, DataType.F32_Default) \
.dtype_format(DataType.I32_Default, DataType.F64_Default) \
.dtype_format(DataType.I32_Default, DataType.BOOL_Default) \
.dtype_format(DataType.I32_5HD, DataType.I64_5HD) \
.dtype_format(DataType.I64_Default, DataType.U8_Default) \
.dtype_format(DataType.I64_Default, DataType.U16_Default) \
.dtype_format(DataType.I64_Default, DataType.U32_Default) \

2
mindspore/ops/_op_impl/aicpu/trans_data.py
View File

@ -24,6 +24,8 @@ trans_data_op_info = AiCPURegOp("TransData") \
.attr("dst_format", "str") \
.dtype_format(DataType.U16_Default, DataType.U16_5HD) \
.dtype_format(DataType.U16_5HD, DataType.U16_Default) \
.dtype_format(DataType.I64_5HD, DataType.I64_Default) \
.dtype_format(DataType.I32_5HD, DataType.I32_Default) \
.get_op_info()
@op_info_register(trans_data_op_info)