forked from XS-MLVP/UnityChipForXiangShan
397 lines
17 KiB
Python
397 lines
17 KiB
Python
import toffee
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import os
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import pytest
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import ctypes
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import datetime
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import toffee.funcov as fc
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from dut.predecode.UT_PreDecode import *
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from dut.decodestage.UT_DecodeStage import *
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from comm import get_out_dir, get_root_dir, debug, UT_FCOV, get_file_logger
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from dut.rvcexpander.UT_RVCExpander import *
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from toffee_test.reporter import set_func_coverage
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from toffee_test.reporter import set_line_coverage
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g = fc.CovGroup(UT_FCOV("INT", parent=-2))
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def init_function_coverage(g):
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# Add decoder module test point content: ToDO
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pass
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toffee.setup_logging(toffee.ERROR)
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class PreDecodeWrapper(toffee.Bundle):
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def __init__(self, dut: DUTPreDecode):
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super().__init__()
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self.dut = dut
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self.input_instrution = toffee.Bundle.from_prefix("io_in_bits_", dut)
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self.output_instrution = toffee.Bundle.from_prefix("io_out_", dut)
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self.bind(dut)
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def predecode(self, instr, need_step=1):
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if not isinstance(instr, list):
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instr = [instr]
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predecoded_inst = []
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for i in range(0, len(instr), 16):
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sub_list = instr[i:i+16]
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for j, inst in enumerate(sub_list):
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self.input_instrution[f"data_%d"%j].value = inst
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self.dut.Step(need_step)
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predecoded_inst.extend([self.output_instrution["instr_%d"%k].value for k in range(16)])
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return predecoded_inst
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class DecodeWrapper(toffee.Bundle):
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def __init__(self, dut: DUTDecodeStage):
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super().__init__()
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self.dut = dut
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for i in range(6):
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setattr(self, f"in_data_{i}", toffee.Bundle.from_prefix(f"io_in_{i}_", dut))
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setattr(self, f"out_data_{i}", toffee.Bundle.from_prefix(f"io_out_{i}_", dut))
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self.input_inst = [getattr(self, f"in_data_{i}") for i in range(6)]
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self.output_instrution = [getattr(self, f"out_data_{i}") for i in range(6)]
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self.bind(dut)
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def SetDefaultValue(self):
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########## set default sinput ignal value ###############
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self.dut.io_redirect.value = 0b0
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######### set instruction releated signals
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for i in range(6):
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self.input_inst[i].valid.value = 0
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self.input_inst[i].bits_instr.value = 0
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self.input_inst[i].bits_foldpc.value = 0
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self.input_inst[i].bits_isFetchMalAddr = 0
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self.input_inst[i].bits_trigger.value = 0
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self.input_inst[i].bits_preDecodeInfo_isRVC.value = 0
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self.input_inst[i].bits_preDecodeInfo_brType.value = 0
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self.input_inst[i].bits_pred_taken.value = 0
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self.input_inst[i].bits_crossPageIPFFix.value = 0
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self.input_inst[i].bits_ftqPtr_flag.value = 0
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self.input_inst[i].bits_ftqPtr_value.value = 0
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self.input_inst[i].bits_ftqOffset.value = 0
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for j in range(24):
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setattr(self.dut, f'io_in_{i}_bits_exceptionVec_{j}', 0)
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########## set req ready signals from rename stage #######
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self.dut.io_out_0_ready.value = 0b1
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self.dut.io_out_1_ready.value = 0b1
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self.dut.io_out_2_ready.value = 0b1
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self.dut.io_out_3_ready.value = 0b1
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self.dut.io_out_4_ready.value = 0b1
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self.dut.io_out_5_ready.value = 0b1
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########## singlestep signal temporarily set to 0 (Because it may be hard to compare with ref model)
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self.dut.io_csrCtrl_singlestep.value = 0b0
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########## fromCSR #######################################
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self.dut.io_fromCSR_illegalInst_sfenceVMA.value = 0
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self.dut.io_fromCSR_illegalInst_sfencePart.value = 0
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self.dut.io_fromCSR_illegalInst_hfenceGVMA.value = 0
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self.dut.io_fromCSR_illegalInst_hfenceVVMA.value = 0
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self.dut.io_fromCSR_illegalInst_hlsv.value = 0
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self.dut.io_fromCSR_illegalInst_fsIsOff.value = 0
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self.dut.io_fromCSR_illegalInst_vsIsOff.value = 0
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self.dut.io_fromCSR_illegalInst_wfi.value = 0
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self.dut.io_fromCSR_illegalInst_frm.value = 0
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self.dut.io_fromCSR_virtualInst_sfenceVMA.value = 0
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self.dut.io_fromCSR_virtualInst_sfencePart.value = 0
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self.dut.io_fromCSR_virtualInst_hfence.value = 0
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self.dut.io_fromCSR_virtualInst_hlsv.value = 0
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self.dut.io_fromCSR_virtualInst_wfi.value = 0
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######### fusion no use ##################################
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self.dut.io_fusion_0.value = 0b0
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self.dut.io_fusion_1.value = 0b0
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self.dut.io_fusion_2.value = 0b0
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########## VType signals temporarily set to 0 (Because it may be hard to compare with ref model)
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self.dut.io_fromRob_isResumeVType.value = 0b0
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self.dut.io_fromRob_commitVType_vtype_valid.value = 0b0
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self.dut.io_fromRob_commitVType_vtype_bits_illegal.value = 0b0
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self.dut.io_fromRob_commitVType_vtype_bits_vma.value = 0b0
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self.dut.io_fromRob_commitVType_vtype_bits_vta.value = 0b0
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self.dut.io_fromRob_commitVType_vtype_bits_vsew.value = 0b0
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self.dut.io_fromRob_commitVType_vtype_bits_vlmul.value = 0b0
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self.dut.io_fromRob_commitVType_hasVsetvl.value = 0b0
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self.dut.io_fromRob_walkVType_valid.value = 0b0
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self.dut.io_fromRob_walkVType_bits_illegal.value = 0b0
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self.dut.io_fromRob_walkVType_bits_vma.value = 0b0
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self.dut.io_fromRob_walkVType_bits_vta.value = 0b0
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self.dut.io_fromRob_walkVType_bits_vsew.value = 0
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self.dut.io_fromRob_walkVType_bits_vlmul.value = 0
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self.dut.io_vsetvlVType_illegal.value = 0b0
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self.dut.io_vsetvlVType_vma.value = 0b0
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self.dut.io_vsetvlVType_vta.value = 0b0
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self.dut.io_vsetvlVType_vsew.value = 0
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self.dut.io_vsetvlVType_vlmul.value = 0
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self.dut.io_vstart.value = 0
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def Reset(self):
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self.dut.reset.value = 0
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self.dut.Step(1)
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self.dut.reset.value = 1
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self.dut.Step(2)
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self.dut.reset.value = 0
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self.dut.Step(1)
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def Input_instruction(self, i, valid, instr, isRVC, brType, isCall, isRet, pred_taken, instr_ex):
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self.input_inst[i].valid.value = valid
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self.input_inst[i].bits_instr.value = instr
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self.input_inst[i].bits_foldpc.value = 0
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self.input_inst[i].bits_exceptionVec_2.value = instr_ex
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for j in range(24):
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setattr(self.dut, f'io_in_{i}_bits_exceptionVec_{j}', 0)
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self.input_inst[i].bits_trigger.value = 0
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self.input_inst[i].bits_preDecodeInfo_isRVC.value = isRVC
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self.input_inst[i].bits_preDecodeInfo_brType.value = brType
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self.input_inst[i].bits_pred_taken.value = pred_taken
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self.input_inst[i].bits_crossPageIPFFix.value = 0
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self.input_inst[i].bits_ftqPtr_flag.value = 0
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self.input_inst[i].bits_ftqPtr_value.value = 0
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self.input_inst[i].bits_ftqOffset.value = 0
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def FromCSR_illegalInst(self, sfenceVMA, sfencePart, hfenceGVMA, hfenceVVMA, hlsv, fsIsOff, vsIsOff, wfi, frm):
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self.dut.io_fromCSR_illegalInst_sfenceVMA.value = sfenceVMA
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self.dut.io_fromCSR_illegalInst_sfencePart.value = sfencePart
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self.dut.io_fromCSR_illegalInst_hfenceGVMA.value = hfenceGVMA
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self.dut.io_fromCSR_illegalInst_hfenceVVMA.value = hfenceVVMA
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self.dut.io_fromCSR_illegalInst_hlsv.value = hlsv
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self.dut.io_fromCSR_illegalInst_fsIsOff.value = fsIsOff
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self.dut.io_fromCSR_illegalInst_vsIsOff.value = vsIsOff
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self.dut.io_fromCSR_illegalInst_wfi.value = wfi
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self.dut.io_fromCSR_illegalInst_frm.value = frm
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def FromCSR_virtualInst(self, sfenceVMA, sfencePart, hfence, hlsv, wfi):
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self.dut.io_fromCSR_virtualInst_sfenceVMA.value = sfenceVMA
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self.dut.io_fromCSR_virtualInst_sfencePart.value = sfencePart
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self.dut.io_fromCSR_virtualInst_hfence.value = hfence
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self.dut.io_fromCSR_virtualInst_hlsv.value = hlsv
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self.dut.io_fromCSR_virtualInst_wfi.value = wfi
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def Get_input_ready(self, i):
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return self.input_inst[i].ready.value
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def Get_allow_input_number(self):
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cnt = 0
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for i in range(6):
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if self.input_inst[i].ready.value == 1:
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cnt = i + 1
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else:
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break
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return cnt
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def Input_instruction_list(self, insts, valid):
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for i in range(6):
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self.Input_instruction(i, 0, 0, 0, 0, 0, 0, 0,0)
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for i, inst in enumerate(insts):
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self.Input_instruction(i, valid, inst[0], 0, 0, 0, 0, 0,inst[3])
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def Get_decode_result(self):
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insts_result = []
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num = 0
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for i in range(6):
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if self.output_instrution[i].valid.value == 1 and self.output_instrution[i].bits_lastUop.value == 1:
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insts_result.append((self.output_instrution[i].bits_instr.value, self.output_instrution[i].bits_exceptionVec_2.value or self.output_instrution[i].bits_exceptionVec_22.value, self.output_instrution[i].bits_firstUop.value))
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num = num + 1
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return num, insts_result
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@pytest.fixture()
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def decoder_fixture(request):
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# before test
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init_function_coverage(g)
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func_name = request.node.name
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# If the output directory does not exist, create it
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output_dir_path = get_out_dir("decoder/log")
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os.makedirs(output_dir_path, exist_ok=True)
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decoder = DecodeWrapper(DUTDecodeStage(
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waveform_filename=get_out_dir("decoder/decode_%s.fst"%func_name),
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coverage_filename=get_out_dir("decoder/decode_%s.dat"%func_name),
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))
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decoder.dut.InitClock("clock")
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decoder.dut.StepRis(lambda x: g.sample())
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# decoder.dut.io_in_0_valid.AsImmWrite()
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# decoder.dut.io_in_0_bits_instr.AsImmWrite()
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yield decoder
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# after test
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decoder.dut.Finish()
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coverage_file = get_out_dir("decoder/decode_%s.dat"%func_name)
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if not os.path.exists(coverage_file):
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raise FileNotFoundError(f"File not found: {coverage_file}")
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set_line_coverage(request, coverage_file, get_root_dir("scripts/backend_ctrlblock_decode"))
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set_func_coverage(request, g)
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g.clear()
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def comapre_result(ref_value_list, dut_value_list, num):
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if num == 0:
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return
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else:
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for i in range(num):
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if ref_value_list[i][1] != dut_value_list[i][1]:
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debug("================================")
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debug(ref_value_list[i])
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debug(dut_value_list[i])
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log_all_info_file = None
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log_err_info_file = None
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def open_log_file(name):
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global log_all_info_file
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global log_err_info_file
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# Obtain the current time and format it
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current_time = datetime.datetime.now().strftime("%Y-%m-%d_%H-%M-%S")
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output_dir = get_out_dir("decoder/log/log")
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# Create a file name
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if name is not None:
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filename_all = output_dir + f"_all_{name}.txt"
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filename_err = output_dir + f"_err_{name}.txt"
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else:
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filename_all = output_dir + f"_all_{current_time}.txt"
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filename_err = output_dir + f"_err_{current_time}.txt"
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log_all_info_file = get_file_logger(filename_all, format=None)
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log_err_info_file = get_file_logger(filename_err, format=None)
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def close_log_file():
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global log_all_info_file
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global log_err_info_file
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if log_all_info_file is not None:
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log_all_info_file = None
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if log_err_info_file is not None:
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log_err_info_file = None
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def write_all_info_to_file(info):
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if log_all_info_file is not None:
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log_all_info_file.info(info)
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else:
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debug("remember open_log_file , close_log_file")
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def write_err_info_to_file(info):
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if log_err_info_file is not None:
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log_err_info_file.info(info)
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else:
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debug("remember open_log_file , close_log_file")
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# Write the comparison results to a file
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# ref_value_list[i][0] = Decimal display of instructions, ref_value_list[i][1] = The reference results are used to determine whether the instruction is illegal,
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# ref_value_list[i][2] = Disassembly result of the instruction, ref_value_list[i][3] = Preliminary screening for illegal instructions is conducted through the RVCExpander module
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# dut_value_list[i][0] = Decimal representation of the instructions output by the Decoder module,
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# dut_value_list[i][1] = The output results from the Decoder are used to determine whether anomalies exist,
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# dut_value_list[i][2] = The output results from the Decoder are used to determine whether the instruction is a complex instruction
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def comapre_result_in_text(ref_value_list, dut_value_list, num):
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if num == 0:
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return
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else:
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for i in range(num):
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# Do not change to assert for now. First, focus on implementing the functionality. Assert directly stops execution.。
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if (ref_value_list[i][2] == 0 or (ref_value_list[i][0] == dut_value_list[i][0])) and (ref_value_list[i][1] == dut_value_list[i][1]):
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# print("Meets expectations:（￣︶￣）↗")
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good_info = f"good ----- ref: {ref_value_list[i][0]}, {ref_value_list[i][1]}, {ref_value_list[i][2]}, {ref_value_list[i][3]}"
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write_all_info_to_file(good_info)
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else:
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# print("Not meeting expectations: <(_ _)>")
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bad_info = f"bad ----- ref: {ref_value_list[i][0]}, {ref_value_list[i][1]}, {ref_value_list[i][2]}, {ref_value_list[i][3]}, old inst: {ref_value_list[i][4]}, dut: {dut_value_list[i][0]}, {dut_value_list[i][1]}, complex: {dut_value_list[i][2] == 0}"
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write_all_info_to_file(bad_info)
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if(ref_value_list[i][2][0] != 'v'):
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write_err_info_to_file(bad_info)
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# Filter out certain cases where exception can be identified through instruction itself,
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# Supplement with the exception detection situation of the reference model.
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def instr_filter(insn_disasm_text):
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instr_opcode = insn_disasm_text.split(' ')[0]
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is_except = 0
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if (instr_opcode == "c.lwsp" or instr_opcode == "c.ldsp" or instr_opcode == "c.addiw"):
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dst = insn_disasm_text.split()[1].split(',')[0]
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if dst == "zero":
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is_except = 1
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elif (instr_opcode == "c.addi4spn"):
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imm = insn_disasm_text.split()[3]
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if imm == "0":
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is_except = 1
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elif (instr_opcode == "c.addi16sp"):
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imm = insn_disasm_text.split()[2]
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if imm == "0":
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is_except = 1
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elif (instr_opcode == "c.lui"):
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imm = insn_disasm_text.split()[2]
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if imm == "0x0":
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is_except = 1
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elif (instr_opcode == "c.jr"):
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rs1 = insn_disasm_text.split()[1]
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if rs1 == "zero":
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is_except = 1
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elif (instr_opcode == "c.unimp"):
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is_except = 1
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return is_except
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# Disassemble the instruction and send it to the rvc_expand module for decoding of compressed instructions
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def convert_reference_format(ref_insts, need_expand, disasm_func, disasm_free_func, disasm_arg = 0):
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rvc_expand = DUTRVCExpander()
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rvc_expand.io_in.AsImmWrite()
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inst_list = []
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for insn in ref_insts:
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c_void_ptr = disasm_func(ctypes.c_uint64(insn), disasm_arg)
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insn_disasm = ctypes.cast(c_void_ptr, ctypes.c_char_p).value.decode('utf-8')
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disasm_free_func(c_void_ptr)
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if need_expand == True:
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rvc_expand.io_in.value = insn
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rvc_expand.RefreshComb()
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instr_ex = rvc_expand.io_ill.value
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instr_bits = rvc_expand.io_out_bits.value
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else:
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instr_ex = 0
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instr_bits = insn
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if insn_disasm == "unknown":
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inst_list.append((instr_bits, 1, insn_disasm, instr_ex, insn))
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else:
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is_excpet = instr_filter(insn_disasm)
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inst_list.append((instr_bits, is_excpet, insn_disasm, instr_ex, insn))
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return inst_list
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# The main part of the test environment
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def decode_run(decoder, inst_list, need_log_file, log_file_name = None):
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if need_log_file == True:
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open_log_file(log_file_name)
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decoder.SetDefaultValue()
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decoder.Reset()
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pos = 0
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detect_pos = 0
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insts_length = len(inst_list)
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sub_valid = 1
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sub_list = inst_list[pos:pos+6]
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while True:
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decoder.Input_instruction_list(sub_list,sub_valid)
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decoder.dut.Step(1)
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allow_number = decoder.Get_allow_input_number()
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if allow_number > 0:
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pos = pos + allow_number
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sub_list = inst_list[pos:pos+allow_number]
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sub_valid = 1
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num, step_result_list = decoder.Get_decode_result()
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if num > 0:
|
|
if need_log_file == True:
|
|
comapre_result_in_text(inst_list[detect_pos:detect_pos+num], step_result_list, num)
|
|
else:
|
|
comapre_result(inst_list[detect_pos:detect_pos+num], step_result_list, num)
|
|
detect_pos = detect_pos + num
|
|
if pos >= insts_length:
|
|
break
|
|
decoder.dut.Step(10)
|
|
close_log_file()
|