UnityChipForXiangShan/scripts/mem_block_lsq_uncache_queue/internal.yaml

LoadQueueUncache:
  - "wire mmioReq_ready"
  - "wire _pipelineReg_4_io_in_ready"
  - "wire _pipelineReg_3_io_in_ready"
  - "wire _pipelineReg_1_io_in_ready"
  - "wire _pipelineReg_io_in_ready"
  - "wire _ncReqArb_io_in_0_ready"
  - "wire _ncReqArb_io_in_1_ready"
  - "wire _ncReqArb_io_in_2_ready"
  - "wire _ncReqArb_io_in_3_ready"
  - "wire _ncReqArb_io_out_valid"
  - "wire [47:0] _ncReqArb_io_out_bits_addr"
  - "wire [49:0] _ncReqArb_io_out_bits_vaddr"
  - "wire [7:0] _ncReqArb_io_out_bits_mask"
  - "wire [6:0] _ncReqArb_io_out_bits_id"
  - "wire _ncReqArb_io_out_bits_nc"
  - "wire _ncReqArb_io_out_bits_memBackTypeMM"
  - "wire [1:0] _freeList_io_allocateSlot_0"
  - "wire [1:0] _freeList_io_allocateSlot_1"
  - "wire [1:0] _freeList_io_allocateSlot_2"
  - "wire _freeList_io_canAllocate_0"
  - "wire _freeList_io_canAllocate_1"
  - "wire _freeList_io_canAllocate_2"
  - "wire _entries_3_io_flush"
  - "wire _entries_3_io_mmioSelect"
  - "wire _entries_3_io_mmioOut_valid"
  - "wire _entries_3_io_mmioOut_bits_uop_exceptionVec_3"
  - "wire _entries_3_io_mmioOut_bits_uop_exceptionVec_4"
  - "wire _entries_3_io_mmioOut_bits_uop_exceptionVec_5"
  - "wire _entries_3_io_mmioOut_bits_uop_exceptionVec_13"
  - "wire _entries_3_io_mmioOut_bits_uop_exceptionVec_19"
  - "wire _entries_3_io_mmioOut_bits_uop_exceptionVec_21"
  - "wire [3:0] _entries_3_io_mmioOut_bits_uop_trigger"
  - "wire _entries_3_io_mmioOut_bits_uop_preDecodeInfo_isRVC"
  - "wire _entries_3_io_mmioOut_bits_uop_ftqPtr_flag"
  - "wire [5:0] _entries_3_io_mmioOut_bits_uop_ftqPtr_value"
  - "wire [3:0] _entries_3_io_mmioOut_bits_uop_ftqOffset"
  - "wire [8:0] _entries_3_io_mmioOut_bits_uop_fuOpType"
  - "wire _entries_3_io_mmioOut_bits_uop_rfWen"
  - "wire _entries_3_io_mmioOut_bits_uop_fpWen"
  - "wire _entries_3_io_mmioOut_bits_uop_flushPipe"
  - "wire [7:0] _entries_3_io_mmioOut_bits_uop_vpu_vstart"
  - "wire [1:0] _entries_3_io_mmioOut_bits_uop_vpu_veew"
  - "wire [6:0] _entries_3_io_mmioOut_bits_uop_uopIdx"
  - "wire [7:0] _entries_3_io_mmioOut_bits_uop_pdest"
  - "wire _entries_3_io_mmioOut_bits_uop_robIdx_flag"
  - "wire [7:0] _entries_3_io_mmioOut_bits_uop_robIdx_value"
  - "wire _entries_3_io_mmioOut_bits_uop_storeSetHit"
  - "wire _entries_3_io_mmioOut_bits_uop_waitForRobIdx_flag"
  - "wire [7:0] _entries_3_io_mmioOut_bits_uop_waitForRobIdx_value"
  - "wire _entries_3_io_mmioOut_bits_uop_loadWaitBit"
  - "wire _entries_3_io_mmioOut_bits_uop_loadWaitStrict"
  - "wire _entries_3_io_mmioOut_bits_uop_lqIdx_flag"
  - "wire [6:0] _entries_3_io_mmioOut_bits_uop_lqIdx_value"
  - "wire _entries_3_io_mmioOut_bits_uop_sqIdx_flag"
  - "wire [5:0] _entries_3_io_mmioOut_bits_uop_sqIdx_value"
  - "wire _entries_3_io_mmioOut_bits_uop_replayInst"
  - "wire [63:0] _entries_3_io_mmioRawData_lqData"
  - "wire [8:0] _entries_3_io_mmioRawData_uop_fuOpType"
  - "wire _entries_3_io_mmioRawData_uop_fpWen"
  - "wire [2:0] _entries_3_io_mmioRawData_addrOffset"
  - "wire _entries_3_io_ncOut_valid"
  - "wire _entries_3_io_ncOut_bits_uop_exceptionVec_4"
  - "wire _entries_3_io_ncOut_bits_uop_exceptionVec_19"
  - "wire _entries_3_io_ncOut_bits_uop_preDecodeInfo_isRVC"
  - "wire _entries_3_io_ncOut_bits_uop_ftqPtr_flag"
  - "wire [5:0] _entries_3_io_ncOut_bits_uop_ftqPtr_value"
  - "wire [3:0] _entries_3_io_ncOut_bits_uop_ftqOffset"
  - "wire [8:0] _entries_3_io_ncOut_bits_uop_fuOpType"
  - "wire _entries_3_io_ncOut_bits_uop_rfWen"
  - "wire _entries_3_io_ncOut_bits_uop_fpWen"
  - "wire [7:0] _entries_3_io_ncOut_bits_uop_vpu_vstart"
  - "wire [1:0] _entries_3_io_ncOut_bits_uop_vpu_veew"
  - "wire [6:0] _entries_3_io_ncOut_bits_uop_uopIdx"
  - "wire [7:0] _entries_3_io_ncOut_bits_uop_pdest"
  - "wire _entries_3_io_ncOut_bits_uop_robIdx_flag"
  - "wire [7:0] _entries_3_io_ncOut_bits_uop_robIdx_value"
  - "wire _entries_3_io_ncOut_bits_uop_storeSetHit"
  - "wire _entries_3_io_ncOut_bits_uop_waitForRobIdx_flag"
  - "wire [7:0] _entries_3_io_ncOut_bits_uop_waitForRobIdx_value"
  - "wire _entries_3_io_ncOut_bits_uop_loadWaitBit"
  - "wire _entries_3_io_ncOut_bits_uop_loadWaitStrict"
  - "wire _entries_3_io_ncOut_bits_uop_lqIdx_flag"
  - "wire [6:0] _entries_3_io_ncOut_bits_uop_lqIdx_value"
  - "wire _entries_3_io_ncOut_bits_uop_sqIdx_flag"
  - "wire [5:0] _entries_3_io_ncOut_bits_uop_sqIdx_value"
  - "wire [49:0] _entries_3_io_ncOut_bits_vaddr"
  - "wire [47:0] _entries_3_io_ncOut_bits_paddr"
  - "wire [128:0] _entries_3_io_ncOut_bits_data"
  - "wire _entries_3_io_ncOut_bits_isvec"
  - "wire _entries_3_io_ncOut_bits_is128bit"
  - "wire _entries_3_io_ncOut_bits_vecActive"
  - "wire [6:0] _entries_3_io_ncOut_bits_schedIndex"
  - "wire _entries_3_io_uncache_req_valid"
  - "wire [47:0] _entries_3_io_uncache_req_bits_addr"
  - "wire [49:0] _entries_3_io_uncache_req_bits_vaddr"
  - "wire [7:0] _entries_3_io_uncache_req_bits_mask"
  - "wire _entries_3_io_uncache_req_bits_nc"
  - "wire _entries_3_io_uncache_req_bits_memBackTypeMM"
  - "wire _entries_3_io_exception_valid"
  - "wire _entries_3_io_exception_bits_uop_exceptionVec_3"
  - "wire _entries_3_io_exception_bits_uop_exceptionVec_4"
  - "wire _entries_3_io_exception_bits_uop_exceptionVec_5"
  - "wire _entries_3_io_exception_bits_uop_exceptionVec_13"
  - "wire _entries_3_io_exception_bits_uop_exceptionVec_19"
  - "wire _entries_3_io_exception_bits_uop_exceptionVec_21"
  - "wire [6:0] _entries_3_io_exception_bits_uop_uopIdx"
  - "wire _entries_3_io_exception_bits_uop_robIdx_flag"
  - "wire [7:0] _entries_3_io_exception_bits_uop_robIdx_value"
  - "wire [63:0] _entries_3_io_exception_bits_fullva"
  - "wire _entries_3_io_exception_bits_isHyper"
  - "wire [63:0] _entries_3_io_exception_bits_gpaddr"
  - "wire _entries_3_io_exception_bits_isForVSnonLeafPTE"
  - "wire _entries_2_io_flush"
  - "wire _entries_2_io_mmioSelect"
  - "wire _entries_2_io_mmioOut_valid"
  - "wire _entries_2_io_mmioOut_bits_uop_exceptionVec_3"
  - "wire _entries_2_io_mmioOut_bits_uop_exceptionVec_4"
  - "wire _entries_2_io_mmioOut_bits_uop_exceptionVec_5"
  - "wire _entries_2_io_mmioOut_bits_uop_exceptionVec_13"
  - "wire _entries_2_io_mmioOut_bits_uop_exceptionVec_19"
  - "wire _entries_2_io_mmioOut_bits_uop_exceptionVec_21"
  - "wire [3:0] _entries_2_io_mmioOut_bits_uop_trigger"
  - "wire _entries_2_io_mmioOut_bits_uop_preDecodeInfo_isRVC"
  - "wire _entries_2_io_mmioOut_bits_uop_ftqPtr_flag"
  - "wire [5:0] _entries_2_io_mmioOut_bits_uop_ftqPtr_value"
  - "wire [3:0] _entries_2_io_mmioOut_bits_uop_ftqOffset"
  - "wire [8:0] _entries_2_io_mmioOut_bits_uop_fuOpType"
  - "wire _entries_2_io_mmioOut_bits_uop_rfWen"
  - "wire _entries_2_io_mmioOut_bits_uop_fpWen"
  - "wire _entries_2_io_mmioOut_bits_uop_flushPipe"
  - "wire [7:0] _entries_2_io_mmioOut_bits_uop_vpu_vstart"
  - "wire [1:0] _entries_2_io_mmioOut_bits_uop_vpu_veew"
  - "wire [6:0] _entries_2_io_mmioOut_bits_uop_uopIdx"
  - "wire [7:0] _entries_2_io_mmioOut_bits_uop_pdest"
  - "wire _entries_2_io_mmioOut_bits_uop_robIdx_flag"
  - "wire [7:0] _entries_2_io_mmioOut_bits_uop_robIdx_value"
  - "wire _entries_2_io_mmioOut_bits_uop_storeSetHit"
  - "wire _entries_2_io_mmioOut_bits_uop_waitForRobIdx_flag"
  - "wire [7:0] _entries_2_io_mmioOut_bits_uop_waitForRobIdx_value"
  - "wire _entries_2_io_mmioOut_bits_uop_loadWaitBit"
  - "wire _entries_2_io_mmioOut_bits_uop_loadWaitStrict"
  - "wire _entries_2_io_mmioOut_bits_uop_lqIdx_flag"
  - "wire [6:0] _entries_2_io_mmioOut_bits_uop_lqIdx_value"
  - "wire _entries_2_io_mmioOut_bits_uop_sqIdx_flag"
  - "wire [5:0] _entries_2_io_mmioOut_bits_uop_sqIdx_value"
  - "wire _entries_2_io_mmioOut_bits_uop_replayInst"
  - "wire [63:0] _entries_2_io_mmioRawData_lqData"
  - "wire [8:0] _entries_2_io_mmioRawData_uop_fuOpType"
  - "wire _entries_2_io_mmioRawData_uop_fpWen"
  - "wire [2:0] _entries_2_io_mmioRawData_addrOffset"
  - "wire _entries_2_io_ncOut_valid"
  - "wire _entries_2_io_ncOut_bits_uop_exceptionVec_4"
  - "wire _entries_2_io_ncOut_bits_uop_exceptionVec_19"
  - "wire _entries_2_io_ncOut_bits_uop_preDecodeInfo_isRVC"
  - "wire _entries_2_io_ncOut_bits_uop_ftqPtr_flag"
  - "wire [5:0] _entries_2_io_ncOut_bits_uop_ftqPtr_value"
  - "wire [3:0] _entries_2_io_ncOut_bits_uop_ftqOffset"
  - "wire [8:0] _entries_2_io_ncOut_bits_uop_fuOpType"
  - "wire _entries_2_io_ncOut_bits_uop_rfWen"
  - "wire _entries_2_io_ncOut_bits_uop_fpWen"
  - "wire [7:0] _entries_2_io_ncOut_bits_uop_vpu_vstart"
  - "wire [1:0] _entries_2_io_ncOut_bits_uop_vpu_veew"
  - "wire [6:0] _entries_2_io_ncOut_bits_uop_uopIdx"
  - "wire [7:0] _entries_2_io_ncOut_bits_uop_pdest"
  - "wire _entries_2_io_ncOut_bits_uop_robIdx_flag"
  - "wire [7:0] _entries_2_io_ncOut_bits_uop_robIdx_value"
  - "wire _entries_2_io_ncOut_bits_uop_storeSetHit"
  - "wire _entries_2_io_ncOut_bits_uop_waitForRobIdx_flag"
  - "wire [7:0] _entries_2_io_ncOut_bits_uop_waitForRobIdx_value"
  - "wire _entries_2_io_ncOut_bits_uop_loadWaitBit"
  - "wire _entries_2_io_ncOut_bits_uop_loadWaitStrict"
  - "wire _entries_2_io_ncOut_bits_uop_lqIdx_flag"
  - "wire [6:0] _entries_2_io_ncOut_bits_uop_lqIdx_value"
  - "wire _entries_2_io_ncOut_bits_uop_sqIdx_flag"
  - "wire [5:0] _entries_2_io_ncOut_bits_uop_sqIdx_value"
  - "wire [49:0] _entries_2_io_ncOut_bits_vaddr"
  - "wire [47:0] _entries_2_io_ncOut_bits_paddr"
  - "wire [128:0] _entries_2_io_ncOut_bits_data"
  - "wire _entries_2_io_ncOut_bits_isvec"
  - "wire _entries_2_io_ncOut_bits_is128bit"
  - "wire _entries_2_io_ncOut_bits_vecActive"
  - "wire [6:0] _entries_2_io_ncOut_bits_schedIndex"
  - "wire _entries_2_io_uncache_req_valid"
  - "wire [47:0] _entries_2_io_uncache_req_bits_addr"
  - "wire [49:0] _entries_2_io_uncache_req_bits_vaddr"
  - "wire [7:0] _entries_2_io_uncache_req_bits_mask"
  - "wire _entries_2_io_uncache_req_bits_nc"
  - "wire _entries_2_io_uncache_req_bits_memBackTypeMM"
  - "wire _entries_2_io_exception_valid"
  - "wire _entries_2_io_exception_bits_uop_exceptionVec_3"
  - "wire _entries_2_io_exception_bits_uop_exceptionVec_4"
  - "wire _entries_2_io_exception_bits_uop_exceptionVec_5"
  - "wire _entries_2_io_exception_bits_uop_exceptionVec_13"
  - "wire _entries_2_io_exception_bits_uop_exceptionVec_19"
  - "wire _entries_2_io_exception_bits_uop_exceptionVec_21"
  - "wire [6:0] _entries_2_io_exception_bits_uop_uopIdx"
  - "wire _entries_2_io_exception_bits_uop_robIdx_flag"
  - "wire [7:0] _entries_2_io_exception_bits_uop_robIdx_value"
  - "wire [63:0] _entries_2_io_exception_bits_fullva"
  - "wire _entries_2_io_exception_bits_isHyper"
  - "wire [63:0] _entries_2_io_exception_bits_gpaddr"
  - "wire _entries_2_io_exception_bits_isForVSnonLeafPTE"
  - "wire _entries_1_io_flush"
  - "wire _entries_1_io_mmioSelect"
  - "wire _entries_1_io_mmioOut_valid"
  - "wire _entries_1_io_mmioOut_bits_uop_exceptionVec_3"
  - "wire _entries_1_io_mmioOut_bits_uop_exceptionVec_4"
  - "wire _entries_1_io_mmioOut_bits_uop_exceptionVec_5"
  - "wire _entries_1_io_mmioOut_bits_uop_exceptionVec_13"
  - "wire _entries_1_io_mmioOut_bits_uop_exceptionVec_19"
  - "wire _entries_1_io_mmioOut_bits_uop_exceptionVec_21"
  - "wire [3:0] _entries_1_io_mmioOut_bits_uop_trigger"
  - "wire _entries_1_io_mmioOut_bits_uop_preDecodeInfo_isRVC"
  - "wire _entries_1_io_mmioOut_bits_uop_ftqPtr_flag"
  - "wire [5:0] _entries_1_io_mmioOut_bits_uop_ftqPtr_value"
  - "wire [3:0] _entries_1_io_mmioOut_bits_uop_ftqOffset"
  - "wire [8:0] _entries_1_io_mmioOut_bits_uop_fuOpType"
  - "wire _entries_1_io_mmioOut_bits_uop_rfWen"
  - "wire _entries_1_io_mmioOut_bits_uop_fpWen"
  - "wire _entries_1_io_mmioOut_bits_uop_flushPipe"
  - "wire [7:0] _entries_1_io_mmioOut_bits_uop_vpu_vstart"
  - "wire [1:0] _entries_1_io_mmioOut_bits_uop_vpu_veew"
  - "wire [6:0] _entries_1_io_mmioOut_bits_uop_uopIdx"
  - "wire [7:0] _entries_1_io_mmioOut_bits_uop_pdest"
  - "wire _entries_1_io_mmioOut_bits_uop_robIdx_flag"
  - "wire [7:0] _entries_1_io_mmioOut_bits_uop_robIdx_value"
  - "wire _entries_1_io_mmioOut_bits_uop_storeSetHit"
  - "wire _entries_1_io_mmioOut_bits_uop_waitForRobIdx_flag"
  - "wire [7:0] _entries_1_io_mmioOut_bits_uop_waitForRobIdx_value"
  - "wire _entries_1_io_mmioOut_bits_uop_loadWaitBit"
  - "wire _entries_1_io_mmioOut_bits_uop_loadWaitStrict"
  - "wire _entries_1_io_mmioOut_bits_uop_lqIdx_flag"
  - "wire [6:0] _entries_1_io_mmioOut_bits_uop_lqIdx_value"
  - "wire _entries_1_io_mmioOut_bits_uop_sqIdx_flag"
  - "wire [5:0] _entries_1_io_mmioOut_bits_uop_sqIdx_value"
  - "wire _entries_1_io_mmioOut_bits_uop_replayInst"
  - "wire [63:0] _entries_1_io_mmioRawData_lqData"
  - "wire [8:0] _entries_1_io_mmioRawData_uop_fuOpType"
  - "wire _entries_1_io_mmioRawData_uop_fpWen"
  - "wire [2:0] _entries_1_io_mmioRawData_addrOffset"
  - "wire _entries_1_io_ncOut_valid"
  - "wire _entries_1_io_ncOut_bits_uop_exceptionVec_4"
  - "wire _entries_1_io_ncOut_bits_uop_exceptionVec_19"
  - "wire _entries_1_io_ncOut_bits_uop_preDecodeInfo_isRVC"
  - "wire _entries_1_io_ncOut_bits_uop_ftqPtr_flag"
  - "wire [5:0] _entries_1_io_ncOut_bits_uop_ftqPtr_value"
  - "wire [3:0] _entries_1_io_ncOut_bits_uop_ftqOffset"
  - "wire [8:0] _entries_1_io_ncOut_bits_uop_fuOpType"
  - "wire _entries_1_io_ncOut_bits_uop_rfWen"
  - "wire _entries_1_io_ncOut_bits_uop_fpWen"
  - "wire [7:0] _entries_1_io_ncOut_bits_uop_vpu_vstart"
  - "wire [1:0] _entries_1_io_ncOut_bits_uop_vpu_veew"
  - "wire [6:0] _entries_1_io_ncOut_bits_uop_uopIdx"
  - "wire [7:0] _entries_1_io_ncOut_bits_uop_pdest"
  - "wire _entries_1_io_ncOut_bits_uop_robIdx_flag"
  - "wire [7:0] _entries_1_io_ncOut_bits_uop_robIdx_value"
  - "wire _entries_1_io_ncOut_bits_uop_storeSetHit"
  - "wire _entries_1_io_ncOut_bits_uop_waitForRobIdx_flag"
  - "wire [7:0] _entries_1_io_ncOut_bits_uop_waitForRobIdx_value"
  - "wire _entries_1_io_ncOut_bits_uop_loadWaitBit"
  - "wire _entries_1_io_ncOut_bits_uop_loadWaitStrict"
  - "wire _entries_1_io_ncOut_bits_uop_lqIdx_flag"
  - "wire [6:0] _entries_1_io_ncOut_bits_uop_lqIdx_value"
  - "wire _entries_1_io_ncOut_bits_uop_sqIdx_flag"
  - "wire [5:0] _entries_1_io_ncOut_bits_uop_sqIdx_value"
  - "wire [49:0] _entries_1_io_ncOut_bits_vaddr"
  - "wire [47:0] _entries_1_io_ncOut_bits_paddr"
  - "wire [128:0] _entries_1_io_ncOut_bits_data"
  - "wire _entries_1_io_ncOut_bits_isvec"
  - "wire _entries_1_io_ncOut_bits_is128bit"
  - "wire _entries_1_io_ncOut_bits_vecActive"
  - "wire [6:0] _entries_1_io_ncOut_bits_schedIndex"
  - "wire _entries_1_io_uncache_req_valid"
  - "wire [47:0] _entries_1_io_uncache_req_bits_addr"
  - "wire [49:0] _entries_1_io_uncache_req_bits_vaddr"
  - "wire [7:0] _entries_1_io_uncache_req_bits_mask"
  - "wire _entries_1_io_uncache_req_bits_nc"
  - "wire _entries_1_io_uncache_req_bits_memBackTypeMM"
  - "wire _entries_1_io_exception_valid"
  - "wire _entries_1_io_exception_bits_uop_exceptionVec_3"
  - "wire _entries_1_io_exception_bits_uop_exceptionVec_4"
  - "wire _entries_1_io_exception_bits_uop_exceptionVec_5"
  - "wire _entries_1_io_exception_bits_uop_exceptionVec_13"
  - "wire _entries_1_io_exception_bits_uop_exceptionVec_19"
  - "wire _entries_1_io_exception_bits_uop_exceptionVec_21"
  - "wire [6:0] _entries_1_io_exception_bits_uop_uopIdx"
  - "wire _entries_1_io_exception_bits_uop_robIdx_flag"
  - "wire [7:0] _entries_1_io_exception_bits_uop_robIdx_value"
  - "wire [63:0] _entries_1_io_exception_bits_fullva"
  - "wire _entries_1_io_exception_bits_isHyper"
  - "wire [63:0] _entries_1_io_exception_bits_gpaddr"
  - "wire _entries_1_io_exception_bits_isForVSnonLeafPTE"
  - "wire _entries_0_io_flush"
  - "wire _entries_0_io_mmioSelect"
  - "wire _entries_0_io_mmioOut_valid"
  - "wire _entries_0_io_mmioOut_bits_uop_exceptionVec_3"
  - "wire _entries_0_io_mmioOut_bits_uop_exceptionVec_4"
  - "wire _entries_0_io_mmioOut_bits_uop_exceptionVec_5"
  - "wire _entries_0_io_mmioOut_bits_uop_exceptionVec_13"
  - "wire _entries_0_io_mmioOut_bits_uop_exceptionVec_19"
  - "wire _entries_0_io_mmioOut_bits_uop_exceptionVec_21"
  - "wire [3:0] _entries_0_io_mmioOut_bits_uop_trigger"
  - "wire _entries_0_io_mmioOut_bits_uop_preDecodeInfo_isRVC"
  - "wire _entries_0_io_mmioOut_bits_uop_ftqPtr_flag"
  - "wire [5:0] _entries_0_io_mmioOut_bits_uop_ftqPtr_value"
  - "wire [3:0] _entries_0_io_mmioOut_bits_uop_ftqOffset"
  - "wire [8:0] _entries_0_io_mmioOut_bits_uop_fuOpType"
  - "wire _entries_0_io_mmioOut_bits_uop_rfWen"
  - "wire _entries_0_io_mmioOut_bits_uop_fpWen"
  - "wire _entries_0_io_mmioOut_bits_uop_flushPipe"
  - "wire [7:0] _entries_0_io_mmioOut_bits_uop_vpu_vstart"
  - "wire [1:0] _entries_0_io_mmioOut_bits_uop_vpu_veew"
  - "wire [6:0] _entries_0_io_mmioOut_bits_uop_uopIdx"
  - "wire [7:0] _entries_0_io_mmioOut_bits_uop_pdest"
  - "wire _entries_0_io_mmioOut_bits_uop_robIdx_flag"
  - "wire [7:0] _entries_0_io_mmioOut_bits_uop_robIdx_value"
  - "wire _entries_0_io_mmioOut_bits_uop_storeSetHit"
  - "wire _entries_0_io_mmioOut_bits_uop_waitForRobIdx_flag"
  - "wire [7:0] _entries_0_io_mmioOut_bits_uop_waitForRobIdx_value"
  - "wire _entries_0_io_mmioOut_bits_uop_loadWaitBit"
  - "wire _entries_0_io_mmioOut_bits_uop_loadWaitStrict"
  - "wire _entries_0_io_mmioOut_bits_uop_lqIdx_flag"
  - "wire [6:0] _entries_0_io_mmioOut_bits_uop_lqIdx_value"
  - "wire _entries_0_io_mmioOut_bits_uop_sqIdx_flag"
  - "wire [5:0] _entries_0_io_mmioOut_bits_uop_sqIdx_value"
  - "wire _entries_0_io_mmioOut_bits_uop_replayInst"
  - "wire [63:0] _entries_0_io_mmioRawData_lqData"
  - "wire [8:0] _entries_0_io_mmioRawData_uop_fuOpType"
  - "wire _entries_0_io_mmioRawData_uop_fpWen"
  - "wire [2:0] _entries_0_io_mmioRawData_addrOffset"
  - "wire _entries_0_io_ncOut_valid"
  - "wire _entries_0_io_ncOut_bits_uop_exceptionVec_4"
  - "wire _entries_0_io_ncOut_bits_uop_exceptionVec_19"
  - "wire _entries_0_io_ncOut_bits_uop_preDecodeInfo_isRVC"
  - "wire _entries_0_io_ncOut_bits_uop_ftqPtr_flag"
  - "wire [5:0] _entries_0_io_ncOut_bits_uop_ftqPtr_value"
  - "wire [3:0] _entries_0_io_ncOut_bits_uop_ftqOffset"
  - "wire [8:0] _entries_0_io_ncOut_bits_uop_fuOpType"
  - "wire _entries_0_io_ncOut_bits_uop_rfWen"
  - "wire _entries_0_io_ncOut_bits_uop_fpWen"
  - "wire [7:0] _entries_0_io_ncOut_bits_uop_vpu_vstart"
  - "wire [1:0] _entries_0_io_ncOut_bits_uop_vpu_veew"
  - "wire [6:0] _entries_0_io_ncOut_bits_uop_uopIdx"
  - "wire [7:0] _entries_0_io_ncOut_bits_uop_pdest"
  - "wire _entries_0_io_ncOut_bits_uop_robIdx_flag"
  - "wire [7:0] _entries_0_io_ncOut_bits_uop_robIdx_value"
  - "wire _entries_0_io_ncOut_bits_uop_storeSetHit"
  - "wire _entries_0_io_ncOut_bits_uop_waitForRobIdx_flag"
  - "wire [7:0] _entries_0_io_ncOut_bits_uop_waitForRobIdx_value"
  - "wire _entries_0_io_ncOut_bits_uop_loadWaitBit"
  - "wire _entries_0_io_ncOut_bits_uop_loadWaitStrict"
  - "wire _entries_0_io_ncOut_bits_uop_lqIdx_flag"
  - "wire [6:0] _entries_0_io_ncOut_bits_uop_lqIdx_value"
  - "wire _entries_0_io_ncOut_bits_uop_sqIdx_flag"
  - "wire [5:0] _entries_0_io_ncOut_bits_uop_sqIdx_value"
  - "wire [49:0] _entries_0_io_ncOut_bits_vaddr"
  - "wire [47:0] _entries_0_io_ncOut_bits_paddr"
  - "wire [128:0] _entries_0_io_ncOut_bits_data"
  - "wire _entries_0_io_ncOut_bits_isvec"
  - "wire _entries_0_io_ncOut_bits_is128bit"
  - "wire _entries_0_io_ncOut_bits_vecActive"
  - "wire [6:0] _entries_0_io_ncOut_bits_schedIndex"
  - "wire _entries_0_io_uncache_req_valid"
  - "wire [47:0] _entries_0_io_uncache_req_bits_addr"
  - "wire [49:0] _entries_0_io_uncache_req_bits_vaddr"
  - "wire [7:0] _entries_0_io_uncache_req_bits_mask"
  - "wire _entries_0_io_uncache_req_bits_nc"
  - "wire _entries_0_io_uncache_req_bits_memBackTypeMM"
  - "wire _entries_0_io_exception_valid"
  - "wire _entries_0_io_exception_bits_uop_exceptionVec_3"
  - "wire _entries_0_io_exception_bits_uop_exceptionVec_4"
  - "wire _entries_0_io_exception_bits_uop_exceptionVec_5"
  - "wire _entries_0_io_exception_bits_uop_exceptionVec_13"
  - "wire _entries_0_io_exception_bits_uop_exceptionVec_19"
  - "wire _entries_0_io_exception_bits_uop_exceptionVec_21"
  - "wire [6:0] _entries_0_io_exception_bits_uop_uopIdx"
  - "wire _entries_0_io_exception_bits_uop_robIdx_flag"
  - "wire [7:0] _entries_0_io_exception_bits_uop_robIdx_value"
  - "wire [63:0] _entries_0_io_exception_bits_fullva"
  - "wire _entries_0_io_exception_bits_isHyper"
  - "wire [63:0] _entries_0_io_exception_bits_gpaddr"
  - "wire _entries_0_io_exception_bits_isForVSnonLeafPTE"
  - "logic s2_req_0_uop_exceptionVec_3"
  - "logic s2_req_0_uop_exceptionVec_4"
  - "logic s2_req_0_uop_exceptionVec_5"
  - "logic s2_req_0_uop_exceptionVec_13"
  - "logic s2_req_0_uop_exceptionVec_21"
  - "logic [3:0] s2_req_0_uop_trigger"
  - "logic s2_req_0_uop_preDecodeInfo_isRVC"
  - "logic s2_req_0_uop_ftqPtr_flag"
  - "logic [5:0] s2_req_0_uop_ftqPtr_value"
  - "logic [3:0] s2_req_0_uop_ftqOffset"
  - "logic [8:0] s2_req_0_uop_fuOpType"
  - "logic s2_req_0_uop_rfWen"
  - "logic s2_req_0_uop_fpWen"
  - "logic [7:0] s2_req_0_uop_vpu_vstart"
  - "logic [1:0] s2_req_0_uop_vpu_veew"
  - "logic [6:0] s2_req_0_uop_uopIdx"
  - "logic [7:0] s2_req_0_uop_pdest"
  - "logic s2_req_0_uop_robIdx_flag"
  - "logic [7:0] s2_req_0_uop_robIdx_value"
  - "logic s2_req_0_uop_storeSetHit"
  - "logic s2_req_0_uop_waitForRobIdx_flag"
  - "logic [7:0] s2_req_0_uop_waitForRobIdx_value"
  - "logic s2_req_0_uop_loadWaitBit"
  - "logic s2_req_0_uop_loadWaitStrict"
  - "logic s2_req_0_uop_lqIdx_flag"
  - "logic [6:0] s2_req_0_uop_lqIdx_value"
  - "logic s2_req_0_uop_sqIdx_flag"
  - "logic [5:0] s2_req_0_uop_sqIdx_value"
  - "logic [49:0] s2_req_0_vaddr"
  - "logic [63:0] s2_req_0_fullva"
  - "logic s2_req_0_isHyper"
  - "logic [47:0] s2_req_0_paddr"
  - "logic [63:0] s2_req_0_gpaddr"
  - "logic s2_req_0_isForVSnonLeafPTE"
  - "logic [15:0] s2_req_0_mask"
  - "logic s2_req_0_nc"
  - "logic s2_req_0_mmio"
  - "logic s2_req_0_memBackTypeMM"
  - "logic s2_req_0_isvec"
  - "logic s2_req_0_is128bit"
  - "logic s2_req_0_vecActive"
  - "logic [6:0] s2_req_0_schedIndex"
  - "logic s2_req_0_rep_info_cause_0"
  - "logic s2_req_0_rep_info_cause_1"
  - "logic s2_req_0_rep_info_cause_2"
  - "logic s2_req_0_rep_info_cause_3"
  - "logic s2_req_0_rep_info_cause_4"
  - "logic s2_req_0_rep_info_cause_5"
  - "logic s2_req_0_rep_info_cause_6"
  - "logic s2_req_0_rep_info_cause_7"
  - "logic s2_req_0_rep_info_cause_8"
  - "logic s2_req_0_rep_info_cause_9"
  - "logic s2_req_0_rep_info_cause_10"
  - "logic s2_req_1_uop_exceptionVec_3"
  - "logic s2_req_1_uop_exceptionVec_4"
  - "logic s2_req_1_uop_exceptionVec_5"
  - "logic s2_req_1_uop_exceptionVec_13"
  - "logic s2_req_1_uop_exceptionVec_21"
  - "logic [3:0] s2_req_1_uop_trigger"
  - "logic s2_req_1_uop_preDecodeInfo_isRVC"
  - "logic s2_req_1_uop_ftqPtr_flag"
  - "logic [5:0] s2_req_1_uop_ftqPtr_value"
  - "logic [3:0] s2_req_1_uop_ftqOffset"
  - "logic [8:0] s2_req_1_uop_fuOpType"
  - "logic s2_req_1_uop_rfWen"
  - "logic s2_req_1_uop_fpWen"
  - "logic [7:0] s2_req_1_uop_vpu_vstart"
  - "logic [1:0] s2_req_1_uop_vpu_veew"
  - "logic [6:0] s2_req_1_uop_uopIdx"
  - "logic [7:0] s2_req_1_uop_pdest"
  - "logic s2_req_1_uop_robIdx_flag"
  - "logic [7:0] s2_req_1_uop_robIdx_value"
  - "logic s2_req_1_uop_storeSetHit"
  - "logic s2_req_1_uop_waitForRobIdx_flag"
  - "logic [7:0] s2_req_1_uop_waitForRobIdx_value"
  - "logic s2_req_1_uop_loadWaitBit"
  - "logic s2_req_1_uop_loadWaitStrict"
  - "logic s2_req_1_uop_lqIdx_flag"
  - "logic [6:0] s2_req_1_uop_lqIdx_value"
  - "logic s2_req_1_uop_sqIdx_flag"
  - "logic [5:0] s2_req_1_uop_sqIdx_value"
  - "logic [49:0] s2_req_1_vaddr"
  - "logic [63:0] s2_req_1_fullva"
  - "logic s2_req_1_isHyper"
  - "logic [47:0] s2_req_1_paddr"
  - "logic [63:0] s2_req_1_gpaddr"
  - "logic s2_req_1_isForVSnonLeafPTE"
  - "logic [15:0] s2_req_1_mask"
  - "logic s2_req_1_nc"
  - "logic s2_req_1_mmio"
  - "logic s2_req_1_memBackTypeMM"
  - "logic s2_req_1_isvec"
  - "logic s2_req_1_is128bit"
  - "logic s2_req_1_vecActive"
  - "logic [6:0] s2_req_1_schedIndex"
  - "logic s2_req_1_rep_info_cause_0"
  - "logic s2_req_1_rep_info_cause_1"
  - "logic s2_req_1_rep_info_cause_2"
  - "logic s2_req_1_rep_info_cause_3"
  - "logic s2_req_1_rep_info_cause_4"
  - "logic s2_req_1_rep_info_cause_5"
  - "logic s2_req_1_rep_info_cause_6"
  - "logic s2_req_1_rep_info_cause_7"
  - "logic s2_req_1_rep_info_cause_8"
  - "logic s2_req_1_rep_info_cause_9"
  - "logic s2_req_1_rep_info_cause_10"
  - "logic s2_req_2_uop_exceptionVec_3"
  - "logic s2_req_2_uop_exceptionVec_4"
  - "logic s2_req_2_uop_exceptionVec_5"
  - "logic s2_req_2_uop_exceptionVec_13"
  - "logic s2_req_2_uop_exceptionVec_21"
  - "logic [3:0] s2_req_2_uop_trigger"
  - "logic s2_req_2_uop_preDecodeInfo_isRVC"
  - "logic s2_req_2_uop_ftqPtr_flag"
  - "logic [5:0] s2_req_2_uop_ftqPtr_value"
  - "logic [3:0] s2_req_2_uop_ftqOffset"
  - "logic [8:0] s2_req_2_uop_fuOpType"
  - "logic s2_req_2_uop_rfWen"
  - "logic s2_req_2_uop_fpWen"
  - "logic [7:0] s2_req_2_uop_vpu_vstart"
  - "logic [1:0] s2_req_2_uop_vpu_veew"
  - "logic [6:0] s2_req_2_uop_uopIdx"
  - "logic [7:0] s2_req_2_uop_pdest"
  - "logic s2_req_2_uop_robIdx_flag"
  - "logic [7:0] s2_req_2_uop_robIdx_value"
  - "logic s2_req_2_uop_storeSetHit"
  - "logic s2_req_2_uop_waitForRobIdx_flag"
  - "logic [7:0] s2_req_2_uop_waitForRobIdx_value"
  - "logic s2_req_2_uop_loadWaitBit"
  - "logic s2_req_2_uop_loadWaitStrict"
  - "logic s2_req_2_uop_lqIdx_flag"
  - "logic [6:0] s2_req_2_uop_lqIdx_value"
  - "logic s2_req_2_uop_sqIdx_flag"
  - "logic [5:0] s2_req_2_uop_sqIdx_value"
  - "logic [49:0] s2_req_2_vaddr"
  - "logic [63:0] s2_req_2_fullva"
  - "logic s2_req_2_isHyper"
  - "logic [47:0] s2_req_2_paddr"
  - "logic [63:0] s2_req_2_gpaddr"
  - "logic s2_req_2_isForVSnonLeafPTE"
  - "logic [15:0] s2_req_2_mask"
  - "logic s2_req_2_nc"
  - "logic s2_req_2_mmio"
  - "logic s2_req_2_memBackTypeMM"
  - "logic s2_req_2_isvec"
  - "logic s2_req_2_is128bit"
  - "logic s2_req_2_vecActive"
  - "logic [6:0] s2_req_2_schedIndex"
  - "logic s2_req_2_rep_info_cause_0"
  - "logic s2_req_2_rep_info_cause_1"
  - "logic s2_req_2_rep_info_cause_2"
  - "logic s2_req_2_rep_info_cause_3"
  - "logic s2_req_2_rep_info_cause_4"
  - "logic s2_req_2_rep_info_cause_5"
  - "logic s2_req_2_rep_info_cause_6"
  - "logic s2_req_2_rep_info_cause_7"
  - "logic s2_req_2_rep_info_cause_8"
  - "logic s2_req_2_rep_info_cause_9"
  - "logic s2_req_2_rep_info_cause_10"
  - "logic s2_valid_REG"
  - "logic s2_valid_REG_1_valid"
  - "logic s2_valid_REG_1_bits_robIdx_flag"
  - "logic [7:0] s2_valid_REG_1_bits_robIdx_value"
  - "logic s2_valid_REG_1_bits_level"
  - "wire [8:0] _s2_valid_flushItself_T_5"
  - "wire [8:0] _io_rollback_valid_flushItself_T_2"
  - "logic s2_valid_REG_2"
  - "logic s2_valid_REG_3_valid"
  - "logic s2_valid_REG_3_bits_robIdx_flag"
  - "logic [7:0] s2_valid_REG_3_bits_robIdx_value"
  - "logic s2_valid_REG_3_bits_level"
  - "wire [8:0] _s2_valid_flushItself_T_13"
  - "logic s2_valid_REG_4"
  - "logic s2_valid_REG_5_valid"
  - "logic s2_valid_REG_5_bits_robIdx_flag"
  - "logic [7:0] s2_valid_REG_5_bits_robIdx_value"
  - "logic s2_valid_REG_5_bits_level"
  - "wire [8:0] _s2_valid_flushItself_T_21"
  - "wire s2_enqueue_0"
  - "wire s2_enqueue_1"
  - "wire s2_enqueue_2"
  - "wire s2_enqValidVec_0"
  - "wire [1:0] _GEN"
  - "wire [3:0] _GEN_0"
  - "wire s2_enqValidVec_1"
  - "wire [1:0] offset"
  - "wire s2_enqValidVec_2"
  - "wire mmioSelect"
  - "wire _GEN_2"
  - "wire _GEN_3"
  - "wire _GEN_4"
  - "wire ncOutValid"
  - "wire _GEN_5"
  - "wire _GEN_6"
  - "wire _GEN_7"
  - "wire _GEN_8"
  - "wire _GEN_9"
  - "wire ncOutValid_2"
  - "wire _GEN_10"
  - "wire _GEN_11"
  - "wire ncOutValid_3"
  - "wire _GEN_12"
  - "wire _GEN_13"
  - "wire _GEN_14"
  - "wire _GEN_15"
  - "wire _GEN_16"
  - "wire _GEN_17"
  - "wire ncOutValid_4"
  - "wire _GEN_18"
  - "wire _GEN_19"
  - "wire _GEN_20"
  - "wire _GEN_21"
  - "wire _GEN_22"
  - "wire _GEN_23"
  - "wire mmioOut_valid"
  - "wire ncOutValid_6"
  - "wire _GEN_24"
  - "wire _GEN_25"
  - "wire ncOutValid_7"
  - "wire _GEN_26"
  - "wire _GEN_27"
  - "wire _GEN_28"
  - "logic [63:0] io_mmioRawData_2_r_lqData"
  - "logic [8:0] io_mmioRawData_2_r_uop_fuOpType"
  - "logic io_mmioRawData_2_r_uop_fpWen"
  - "logic [2:0] io_mmioRawData_2_r_addrOffset"
  - "wire _io_exception_bits_T"
  - "logic io_rob_mmio_0_REG"
  - "logic [7:0] io_rob_uop_0_r_robIdx_value"
  - "logic io_rob_mmio_1_REG"
  - "logic [7:0] io_rob_uop_1_r_robIdx_value"
  - "logic io_rob_mmio_2_REG"
  - "logic [7:0] io_rob_uop_2_r_robIdx_value"
  - "wire reqNeedCheck_0"
  - "wire reqNeedCheck_1"
  - "wire reqNeedCheck_2"
  - "wire oldestOneHot_compareVec_1_0"
  - "wire oldestOneHot_compareVec_2_0"
  - "wire oldestOneHot_compareVec_2_1"
  - "wire [2:0] _oldestOneHot_resultOnehot_T_6"
  - "wire [2:0] _oldestOneHot_resultOnehot_T_13"
  - "wire [2:0] _oldestOneHot_resultOnehot_T_19"
  - "wire [7:0] _oldestRedirect_T_439"
  - "wire _oldestRedirect_T_444"
  - "wire _oldestRedirect_T_454"
  - "logic lastCycleRedirect_valid_REG"
  - "logic lastCycleRedirect_bits_r_robIdx_flag"
  - "logic [7:0] lastCycleRedirect_bits_r_robIdx_value"
  - "logic lastCycleRedirect_bits_r_level"
  - "logic lastLastCycleRedirect_valid_REG"
  - "logic lastLastCycleRedirect_bits_r_robIdx_flag"
  - "logic [7:0] lastLastCycleRedirect_bits_r_robIdx_value"
  - "logic lastLastCycleRedirect_bits_r_level"
  - "logic io_rollback_valid_last_REG"
  - "logic io_rollback_bits_r_isRVC"
  - "logic io_rollback_bits_r_robIdx_flag"
  - "logic [7:0] io_rollback_bits_r_robIdx_value"
  - "logic io_rollback_bits_r_ftqIdx_flag"
  - "logic [5:0] io_rollback_bits_r_ftqIdx_value"
  - "logic [3:0] io_rollback_bits_r_ftqOffset"
  - "logic io_rollback_bits_r_level"
  - "wire s1_sortedVec_tmp0_swap"
  - "wire s1_sortedVec_tmp0_0_valid"
  - "wire s1_sortedVec_tmp0_0_ptr_flag"
  - "wire [7:0] s1_sortedVec_tmp0_0_ptr_value"
  - "wire s1_sortedVec_tmp0_0_bits_uop_exceptionVec_3"
  - "wire s1_sortedVec_tmp0_0_bits_uop_exceptionVec_4"
  - "wire s1_sortedVec_tmp0_0_bits_uop_exceptionVec_5"
  - "wire s1_sortedVec_tmp0_0_bits_uop_exceptionVec_13"
  - "wire s1_sortedVec_tmp0_0_bits_uop_exceptionVec_21"
  - "wire [3:0] s1_sortedVec_tmp0_0_bits_uop_trigger"
  - "wire s1_sortedVec_tmp0_0_bits_uop_preDecodeInfo_isRVC"
  - "wire s1_sortedVec_tmp0_0_bits_uop_ftqPtr_flag"
  - "wire [5:0] s1_sortedVec_tmp0_0_bits_uop_ftqPtr_value"
  - "wire [3:0] s1_sortedVec_tmp0_0_bits_uop_ftqOffset"
  - "wire [8:0] s1_sortedVec_tmp0_0_bits_uop_fuOpType"
  - "wire s1_sortedVec_tmp0_0_bits_uop_rfWen"
  - "wire s1_sortedVec_tmp0_0_bits_uop_fpWen"
  - "wire [7:0] s1_sortedVec_tmp0_0_bits_uop_vpu_vstart"
  - "wire [1:0] s1_sortedVec_tmp0_0_bits_uop_vpu_veew"
  - "wire [6:0] s1_sortedVec_tmp0_0_bits_uop_uopIdx"
  - "wire [7:0] s1_sortedVec_tmp0_0_bits_uop_pdest"
  - "wire s1_sortedVec_tmp0_0_bits_uop_storeSetHit"
  - "wire s1_sortedVec_tmp0_0_bits_uop_waitForRobIdx_flag"
  - "wire [7:0] s1_sortedVec_tmp0_0_bits_uop_waitForRobIdx_value"
  - "wire s1_sortedVec_tmp0_0_bits_uop_loadWaitBit"
  - "wire s1_sortedVec_tmp0_0_bits_uop_loadWaitStrict"
  - "wire s1_sortedVec_tmp0_0_bits_uop_lqIdx_flag"
  - "wire [6:0] s1_sortedVec_tmp0_0_bits_uop_lqIdx_value"
  - "wire s1_sortedVec_tmp0_0_bits_uop_sqIdx_flag"
  - "wire [5:0] s1_sortedVec_tmp0_0_bits_uop_sqIdx_value"
  - "wire [49:0] s1_sortedVec_tmp0_0_bits_vaddr"
  - "wire [63:0] s1_sortedVec_tmp0_0_bits_fullva"
  - "wire s1_sortedVec_tmp0_0_bits_isHyper"
  - "wire [47:0] s1_sortedVec_tmp0_0_bits_paddr"
  - "wire [63:0] s1_sortedVec_tmp0_0_bits_gpaddr"
  - "wire s1_sortedVec_tmp0_0_bits_isForVSnonLeafPTE"
  - "wire [15:0] s1_sortedVec_tmp0_0_bits_mask"
  - "wire s1_sortedVec_tmp0_0_bits_nc"
  - "wire s1_sortedVec_tmp0_0_bits_mmio"
  - "wire s1_sortedVec_tmp0_0_bits_memBackTypeMM"
  - "wire s1_sortedVec_tmp0_0_bits_isvec"
  - "wire s1_sortedVec_tmp0_0_bits_is128bit"
  - "wire s1_sortedVec_tmp0_0_bits_vecActive"
  - "wire [6:0] s1_sortedVec_tmp0_0_bits_schedIndex"
  - "wire s1_sortedVec_tmp0_0_bits_rep_info_cause_0"
  - "wire s1_sortedVec_tmp0_0_bits_rep_info_cause_1"
  - "wire s1_sortedVec_tmp0_0_bits_rep_info_cause_2"
  - "wire s1_sortedVec_tmp0_0_bits_rep_info_cause_3"
  - "wire s1_sortedVec_tmp0_0_bits_rep_info_cause_4"
  - "wire s1_sortedVec_tmp0_0_bits_rep_info_cause_5"
  - "wire s1_sortedVec_tmp0_0_bits_rep_info_cause_6"
  - "wire s1_sortedVec_tmp0_0_bits_rep_info_cause_7"
  - "wire s1_sortedVec_tmp0_0_bits_rep_info_cause_8"
  - "wire s1_sortedVec_tmp0_0_bits_rep_info_cause_9"
  - "wire s1_sortedVec_tmp0_0_bits_rep_info_cause_10"
  - "wire s1_sortedVec_tmp0_1_valid"
  - "wire s1_sortedVec_tmp0_1_ptr_flag"
  - "wire [7:0] s1_sortedVec_tmp0_1_ptr_value"
  - "wire s1_sortedVec_tmp0_1_bits_uop_exceptionVec_3"
  - "wire s1_sortedVec_tmp0_1_bits_uop_exceptionVec_4"
  - "wire s1_sortedVec_tmp0_1_bits_uop_exceptionVec_5"
  - "wire s1_sortedVec_tmp0_1_bits_uop_exceptionVec_13"
  - "wire s1_sortedVec_tmp0_1_bits_uop_exceptionVec_21"
  - "wire [3:0] s1_sortedVec_tmp0_1_bits_uop_trigger"
  - "wire s1_sortedVec_tmp0_1_bits_uop_preDecodeInfo_isRVC"
  - "wire s1_sortedVec_tmp0_1_bits_uop_ftqPtr_flag"
  - "wire [5:0] s1_sortedVec_tmp0_1_bits_uop_ftqPtr_value"
  - "wire [3:0] s1_sortedVec_tmp0_1_bits_uop_ftqOffset"
  - "wire [8:0] s1_sortedVec_tmp0_1_bits_uop_fuOpType"
  - "wire s1_sortedVec_tmp0_1_bits_uop_rfWen"
  - "wire s1_sortedVec_tmp0_1_bits_uop_fpWen"
  - "wire [7:0] s1_sortedVec_tmp0_1_bits_uop_vpu_vstart"
  - "wire [1:0] s1_sortedVec_tmp0_1_bits_uop_vpu_veew"
  - "wire [6:0] s1_sortedVec_tmp0_1_bits_uop_uopIdx"
  - "wire [7:0] s1_sortedVec_tmp0_1_bits_uop_pdest"
  - "wire s1_sortedVec_tmp0_1_bits_uop_storeSetHit"
  - "wire s1_sortedVec_tmp0_1_bits_uop_waitForRobIdx_flag"
  - "wire [7:0] s1_sortedVec_tmp0_1_bits_uop_waitForRobIdx_value"
  - "wire s1_sortedVec_tmp0_1_bits_uop_loadWaitBit"
  - "wire s1_sortedVec_tmp0_1_bits_uop_loadWaitStrict"
  - "wire s1_sortedVec_tmp0_1_bits_uop_lqIdx_flag"
  - "wire [6:0] s1_sortedVec_tmp0_1_bits_uop_lqIdx_value"
  - "wire s1_sortedVec_tmp0_1_bits_uop_sqIdx_flag"
  - "wire [5:0] s1_sortedVec_tmp0_1_bits_uop_sqIdx_value"
  - "wire [49:0] s1_sortedVec_tmp0_1_bits_vaddr"
  - "wire [63:0] s1_sortedVec_tmp0_1_bits_fullva"
  - "wire s1_sortedVec_tmp0_1_bits_isHyper"
  - "wire [47:0] s1_sortedVec_tmp0_1_bits_paddr"
  - "wire [63:0] s1_sortedVec_tmp0_1_bits_gpaddr"
  - "wire s1_sortedVec_tmp0_1_bits_isForVSnonLeafPTE"
  - "wire [15:0] s1_sortedVec_tmp0_1_bits_mask"
  - "wire s1_sortedVec_tmp0_1_bits_nc"
  - "wire s1_sortedVec_tmp0_1_bits_mmio"
  - "wire s1_sortedVec_tmp0_1_bits_memBackTypeMM"
  - "wire s1_sortedVec_tmp0_1_bits_isvec"
  - "wire s1_sortedVec_tmp0_1_bits_is128bit"
  - "wire s1_sortedVec_tmp0_1_bits_vecActive"
  - "wire [6:0] s1_sortedVec_tmp0_1_bits_schedIndex"
  - "wire s1_sortedVec_tmp0_1_bits_rep_info_cause_0"
  - "wire s1_sortedVec_tmp0_1_bits_rep_info_cause_1"
  - "wire s1_sortedVec_tmp0_1_bits_rep_info_cause_2"
  - "wire s1_sortedVec_tmp0_1_bits_rep_info_cause_3"
  - "wire s1_sortedVec_tmp0_1_bits_rep_info_cause_4"
  - "wire s1_sortedVec_tmp0_1_bits_rep_info_cause_5"
  - "wire s1_sortedVec_tmp0_1_bits_rep_info_cause_6"
  - "wire s1_sortedVec_tmp0_1_bits_rep_info_cause_7"
  - "wire s1_sortedVec_tmp0_1_bits_rep_info_cause_8"
  - "wire s1_sortedVec_tmp0_1_bits_rep_info_cause_9"
  - "wire s1_sortedVec_tmp0_1_bits_rep_info_cause_10"
  - "wire s1_sortedVec_tmp1_swap"
  - "wire s1_sortedVec_tmp1_0_valid"
  - "wire s1_sortedVec_tmp1_0_bits_uop_exceptionVec_3"
  - "wire s1_sortedVec_tmp1_0_bits_uop_exceptionVec_4"
  - "wire s1_sortedVec_tmp1_0_bits_uop_exceptionVec_5"
  - "wire s1_sortedVec_tmp1_0_bits_uop_exceptionVec_13"
  - "wire s1_sortedVec_tmp1_0_bits_uop_exceptionVec_21"
  - "wire [3:0] s1_sortedVec_tmp1_0_bits_uop_trigger"
  - "wire s1_sortedVec_tmp1_0_bits_uop_preDecodeInfo_isRVC"
  - "wire s1_sortedVec_tmp1_0_bits_uop_ftqPtr_flag"
  - "wire [5:0] s1_sortedVec_tmp1_0_bits_uop_ftqPtr_value"
  - "wire [3:0] s1_sortedVec_tmp1_0_bits_uop_ftqOffset"
  - "wire [8:0] s1_sortedVec_tmp1_0_bits_uop_fuOpType"
  - "wire s1_sortedVec_tmp1_0_bits_uop_rfWen"
  - "wire s1_sortedVec_tmp1_0_bits_uop_fpWen"
  - "wire [7:0] s1_sortedVec_tmp1_0_bits_uop_vpu_vstart"
  - "wire [1:0] s1_sortedVec_tmp1_0_bits_uop_vpu_veew"
  - "wire [6:0] s1_sortedVec_tmp1_0_bits_uop_uopIdx"
  - "wire [7:0] s1_sortedVec_tmp1_0_bits_uop_pdest"
  - "wire s1_sortedVec_tmp1_0_bits_uop_robIdx_flag"
  - "wire [7:0] s1_sortedVec_tmp1_0_bits_uop_robIdx_value"
  - "wire s1_sortedVec_tmp1_0_bits_uop_storeSetHit"
  - "wire s1_sortedVec_tmp1_0_bits_uop_waitForRobIdx_flag"
  - "wire [7:0] s1_sortedVec_tmp1_0_bits_uop_waitForRobIdx_value"
  - "wire s1_sortedVec_tmp1_0_bits_uop_loadWaitBit"
  - "wire s1_sortedVec_tmp1_0_bits_uop_loadWaitStrict"
  - "wire s1_sortedVec_tmp1_0_bits_uop_lqIdx_flag"
  - "wire [6:0] s1_sortedVec_tmp1_0_bits_uop_lqIdx_value"
  - "wire s1_sortedVec_tmp1_0_bits_uop_sqIdx_flag"
  - "wire [5:0] s1_sortedVec_tmp1_0_bits_uop_sqIdx_value"
  - "wire [49:0] s1_sortedVec_tmp1_0_bits_vaddr"
  - "wire [63:0] s1_sortedVec_tmp1_0_bits_fullva"
  - "wire s1_sortedVec_tmp1_0_bits_isHyper"
  - "wire [47:0] s1_sortedVec_tmp1_0_bits_paddr"
  - "wire [63:0] s1_sortedVec_tmp1_0_bits_gpaddr"
  - "wire s1_sortedVec_tmp1_0_bits_isForVSnonLeafPTE"
  - "wire [15:0] s1_sortedVec_tmp1_0_bits_mask"
  - "wire s1_sortedVec_tmp1_0_bits_nc"
  - "wire s1_sortedVec_tmp1_0_bits_mmio"
  - "wire s1_sortedVec_tmp1_0_bits_memBackTypeMM"
  - "wire s1_sortedVec_tmp1_0_bits_isvec"
  - "wire s1_sortedVec_tmp1_0_bits_is128bit"
  - "wire s1_sortedVec_tmp1_0_bits_vecActive"
  - "wire [6:0] s1_sortedVec_tmp1_0_bits_schedIndex"
  - "wire s1_sortedVec_tmp1_0_bits_rep_info_cause_0"
  - "wire s1_sortedVec_tmp1_0_bits_rep_info_cause_1"
  - "wire s1_sortedVec_tmp1_0_bits_rep_info_cause_2"
  - "wire s1_sortedVec_tmp1_0_bits_rep_info_cause_3"
  - "wire s1_sortedVec_tmp1_0_bits_rep_info_cause_4"
  - "wire s1_sortedVec_tmp1_0_bits_rep_info_cause_5"
  - "wire s1_sortedVec_tmp1_0_bits_rep_info_cause_6"
  - "wire s1_sortedVec_tmp1_0_bits_rep_info_cause_7"
  - "wire s1_sortedVec_tmp1_0_bits_rep_info_cause_8"
  - "wire s1_sortedVec_tmp1_0_bits_rep_info_cause_9"
  - "wire s1_sortedVec_tmp1_0_bits_rep_info_cause_10"
  - "wire s1_valid_2"
  - "wire s1_req_2_mmio"
  - "wire s1_sortedVec_tmp2_swap"
  - "wire s1_valid_0"
  - "wire s1_req_0_mmio"
  - "wire s1_valid_1"
  - "wire s1_req_1_mmio"
  - "wire [7:0] s1_req_0_uop_robIdx_value"
  - "wire [7:0] s1_req_1_uop_robIdx_value"
  - "wire [7:0] s1_req_2_uop_robIdx_value"
  - "wire [8:0] _io_rollback_valid_flushItself_T_9"