[ROBOT] add robot framework and yunshenchu j60 support
This commit is contained in:
张超杰
parent
ef42543c3a
commit
14669a96de
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SRC_FILES := main.c
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include $(KERNEL_ROOT)/compiler.mk
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# 构建矽璓工业物联操作系统：机器人控制代码
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## 目录结构
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| 名称 | 说明 |
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| -- | -- |
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| configure | 电机配置 |
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| motor_control_algo | 算法包 |
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| protocol | 上层接口协议 |
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### 电机配置：
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| 目前支持电机型号：|
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| -- |
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| 云深处J60-6 |
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| 云深处J60-10 |
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| 智元R86-3 with STM32F405外挂板 |
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### 算法包：
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| 目前支持的电机算法：|
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| -- |
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| 自研FOC |
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| ODRIVE |
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### 上层接口协议
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| 目前支持的协议：|
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| -- |
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| 云深处协议 |
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## 使用方法
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TODO：
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/* USER CODE BEGIN Header */
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/**
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******************************************************************************
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* @file : main.c
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* @brief : Main program body
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2025 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* USER CODE END Header */
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/* Includes ------------------------------------------------------------------*/
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#include "xizi.h"
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/* Private includes ----------------------------------------------------------*/
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/* USER CODE BEGIN Includes */
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#include "foc.h"
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#include "conf.h"
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#include "arm_math.h"
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struct MotorDriver motor_driver;
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void set_pwm_duty(float d_u, float d_v, float d_w)
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{
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// duty 限幅 [0, 0.9]
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d_u = min(d_u, 0.9);
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d_v = min(d_v, 0.9);
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d_w = min(d_w, 0.9);
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struct BusBlockWriteParam write_param;
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float duty[3] = {d_u, d_v, d_w};
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write_param.buffer = (void *)duty;
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BusDevWriteData(motor_driver.motor_control.dev, &write_param);
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}
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uint16_t angles[1000] = {0};
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static int speed_calc_task = -1;
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void speed_calc_entry(void *parameter)
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{
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// 10 ticks = 1 ms
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static uint16_t motor_speed_calc_delay = 5000;
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static uint16_t motor_speed_calc_freq = 1000;
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// static float last_position = 0;
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while (1)
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{
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x_ticks_t start = CurrentTicksGain();
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struct BusBlockReadParam read_param;
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uint16_t read_data;
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read_param.buffer = (void *)&read_data;
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read_param.size = 1;
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BusDevReadData(motor_driver.motor_encoder.dev, &read_param);
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g_encoder_angle = (read_data) * RAW_TO_RAD;
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static float encoder_angle_last = 0;
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static int once = 1;
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if (once) {
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once = 0;
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encoder_angle_last = g_encoder_angle;
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}
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float diff_angle = cycle_diff(g_encoder_angle - encoder_angle_last, 2 * PI);
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encoder_angle_last = g_encoder_angle;
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// 更新电机逻辑角度
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g_motor_logic_angle = cycle_diff(g_motor_logic_angle + diff_angle, mult_position_cycle);
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float _motor_speed = diff_angle * motor_speed_calc_freq;
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float filter_alpha_speed = 0.1f;
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g_motor_logic_speed = low_pass_filter(_motor_speed, g_motor_logic_speed, filter_alpha_speed);
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g_motor_speed = g_motor_logic_speed / Reduction_Ratio;
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// if ((int)last_position != (int)g_motor_logic_angle)
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// {
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// last_position = g_motor_logic_angle;
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// KPrintf("logic angle: %d \r\n", (int)(g_motor_logic_angle * 100));
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// /* code */
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// }
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x_ticks_t end = CurrentTicksGain();
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MdelayKTask(motor_speed_calc_delay - (end - start));
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}
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// static float last_angle = 0;
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// float angle_diff = cycle_diff(g_motor_logic_angle - last_angle, 2 * PI);
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// g_motor_speed = angle_diff / (SAMPLE_TIME_MS / 1000.0f); // rad/s
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// last_angle = g_motor_logic_angle;
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}
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void __FOC_START(void) {
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BusDevOpen(motor_driver.motor_control.dev);
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if(speed_calc_task == -1)
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speed_calc_task = KTaskCreate("speed_calc", speed_calc_entry, NONE, 2048, 30);
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if (speed_calc_task != -1)
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StartupKTask(speed_calc_task);
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}
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void __FOC_STOP(void) {
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BusDevClose(motor_driver.motor_control.dev);
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if (speed_calc_task != NONE)
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KTaskDelete(speed_calc_task);
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speed_calc_task = -1;
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}
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void __FOC_BREAK(void) {
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}
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//todo 角度计算
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void motor_angle_calc(){
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}
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// 上电校准函数
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void calibrate_current_offset(void)
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{
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uint32_t sum_u = 0, sum_v = 0, sum_w = 0;
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int SAMPLE_COUNT = 10;
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for (int i = 0; i < SAMPLE_COUNT; i++)
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{
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// 启动 ADC 注入转换
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adc_software_trigger_enable(ADC0, ADC_INSERTED_CHANNEL);
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adc_software_trigger_enable(ADC1, ADC_INSERTED_CHANNEL);
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adc_software_trigger_enable(ADC2, ADC_INSERTED_CHANNEL);
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// 等待转换完成（可用中断方式，这里简单轮询）
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while(!adc_flag_get(ADC0, ADC_FLAG_EOIC));
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while(!adc_flag_get(ADC1, ADC_FLAG_EOIC));
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while(!adc_flag_get(ADC2, ADC_FLAG_EOIC));
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// 读取注入通道数据
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uint16_t adc_u = adc_inserted_data_read(ADC0, ADC_INSERTED_CHANNEL_0);
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uint16_t adc_v = adc_inserted_data_read(ADC1, ADC_INSERTED_CHANNEL_0);
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uint16_t adc_w = adc_inserted_data_read(ADC2, ADC_INSERTED_CHANNEL_0);
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sum_u += adc_u;
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sum_v += adc_v;
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sum_w += adc_w;
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}
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// 求平均
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float avg_u = sum_u / (float)SAMPLE_COUNT;
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float avg_v = sum_v / (float)SAMPLE_COUNT;
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float avg_w = sum_w / (float)SAMPLE_COUNT;
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// 转换为电压偏置
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i_offset_u1 = avg_u / ((1 << ADC_BITS) - 1) * ADC_REFERENCE_VOLT;
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i_offset_u2 = avg_v / ((1 << ADC_BITS) - 1) * ADC_REFERENCE_VOLT;
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i_offset_u3 = avg_w / ((1 << ADC_BITS) - 1) * ADC_REFERENCE_VOLT;
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// printf("i_offset_u1 = %.3f\r\n", i_offset_u1);
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// printf("i_offset_u2 = %.3f\r\n", i_offset_u2);
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// printf("i_offset_u3 = %.3f\r\n", i_offset_u3);
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}
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// adc callback in interrupt
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void foc_loop(){
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float u_1 = (ADC_REFERENCE_VOLT * (float)adc_inserted_data_read(ADC0, ADC_INSERTED_CHANNEL_0) / ((1 << ADC_BITS) - 1)) - i_offset_u1;
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float u_2 = (ADC_REFERENCE_VOLT * (float)adc_inserted_data_read(ADC1, ADC_INSERTED_CHANNEL_0) / ((1 << ADC_BITS) - 1)) - i_offset_u2;
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float u_3 = (ADC_REFERENCE_VOLT * (float)adc_inserted_data_read(ADC2, ADC_INSERTED_CHANNEL_0) / ((1 << ADC_BITS) - 1)) - i_offset_u3;
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float i_1 = u_1 / (R_SHUNT * OP_GAIN);
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float i_2 = u_2 / (R_SHUNT * OP_GAIN);
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float i_3 = u_3 / (R_SHUNT * OP_GAIN);
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// Clarke 输入：i_u, i_v
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g_motor_i_u = -i_2;
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g_motor_i_v = -i_3;
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g_motor_i_w = (i_2 + i_3);
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//printf("ADC_IRQHandler\r\n");
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// Clarke 变换
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float i_alpha = g_motor_i_u;
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float i_beta = (g_motor_i_u + 2.0f * g_motor_i_v) * 0.57735026919f; // 1/sqrt(3)
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// Park 变换
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float sin_value = sinf(rotor_logic_angle);
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float cos_value = cosf(rotor_logic_angle);
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float w_e = g_motor_logic_speed * POLE_PAIRS; // rad/s 机械转速=>电角速度
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float _motor_i_d = i_alpha * cos_value + i_beta * sin_value;
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float _motor_i_q = -i_alpha * sin_value + i_beta * cos_value;
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// 归一化
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float motor_i_d_norm = _motor_i_d;
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float motor_i_q_norm = _motor_i_q;
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static float i_d_hat = 0.0f;
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static float i_q_hat = 0.0f;
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float i_d_dot = (_motor_i_d - 0.54 * i_d_hat + w_e * 0.00034 * i_q_hat) / 0.00034;
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float i_q_dot = (_motor_i_q - 0.54 * i_q_hat - w_e * 0.00034 * i_d_hat - w_e * 0.1283) / 0.00034;
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// 更新观测电流
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i_d_hat += 1.0f/20000.0f*5.0f * (i_d_dot + 200.0f * (0 - i_d_hat)); // 无电流传感器 → 期望电流为0的补偿
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i_q_hat += 1.0f/20000.0f*5.0f * (i_q_dot + 200.0f * (0 - i_q_hat));
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// 一阶低通滤波
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float filter_alpha_i_d = 0.3f;
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float filter_alpha_i_q = 0.3f;
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g_motor_i_d = low_pass_filter(motor_i_d_norm, g_motor_i_d, filter_alpha_i_d);
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g_motor_i_q = low_pass_filter(motor_i_q_norm, g_motor_i_q, filter_alpha_i_q);
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float motor_control_torque_i = g_motor_i_q * (1.3473f * MAX_CURRENT * 1.3);
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float motor_control_torque_o = -1.5f * POLE_PAIRS * 0.1283 * i_q_hat / 28;
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//motor_control_torque = fabs(motor_control_torque_i) > fabs(motor_control_torque_o) ? motor_control_torque_i : 0;
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g_motor_control_torque = motor_control_torque_i;
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// g_motor_control_torque = addValue(&ADC_Iq_filter, g_motor_control_torque);
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g_motor_i_q = g_motor_control_torque / (1.3473f * MAX_CURRENT);
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// 控制类型调度
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switch (motor_control_context.type)
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{
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case control_type_position:
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lib_position_control(motor_control_context.position);
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break;
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case control_type_speed:
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lib_speed_control(motor_control_context.speed);
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break;
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case control_type_torque:
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lib_torque_control(motor_control_context.torque_norm_d, motor_control_context.torque_norm_q);
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break;
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case control_type_speed_torque:
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lib_speed_torque_control(motor_control_context.speed);
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break;
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case control_type_position_speed_torque:
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lib_position_speed_torque_control(motor_control_context.position);
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break;
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case control_type_mit_control:
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// lib_mit_control(0, 0, 0, 0, 1.5);
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// lib_mit_control(
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// ctrl_params.position,
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// ctrl_params.speed,
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// ctrl_params.kp,
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// ctrl_params.kd,
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// ctrl_params.torque
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// );
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break;
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default:
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break;
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}
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}
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void CanProtocalHandler(void){
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}
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void CanMsgReceived(void){
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struct BusBlockReadParam read_param;
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struct BusBlockWriteParam write_param;
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uint32_t can_id = 4;
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uint8_t recv_buf[8];
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*(uint32_t *)recv_buf = can_id; //temp id
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read_param.buffer = (void *)recv_buf;
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read_param.size = 8;
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BusDevReadData(motor_driver.motor_encoder.dev, &read_param);
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// process can message
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uint8_t send_buf[12];
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uint8 can_dlc;
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write_param.buffer = (void *)send_buf;
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handleCanMessage(can_id, read_param.size, recv_buf, &can_id, send_buf + 4, &can_dlc);
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*(uint32_t *)send_buf = can_id;
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write_param.size = can_dlc + 4;
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BusDevWriteData(motor_driver.motor_can_protocal.dev, &write_param);
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}
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int InitHwMotor(void)
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{
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motor_driver.motor_control.bus = BusFind(HWTIMER_BUS_NAME);
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motor_driver.motor_control.dev = BusFindDevice(motor_driver.motor_control.bus, HWTIMER_DEVICE1_NAME);
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motor_driver.motor_control.drv = BusFindDriver(motor_driver.motor_control.bus, HWTIMER_DRIVER_NAME);
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struct BusConfigureInfo configure_info;
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configure_info.configure_cmd = OPE_INT;
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BusDrvConfigure(motor_driver.motor_control.drv, &configure_info);
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struct BusBlockReadParam read_param;
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motor_driver.motor_encoder.bus = BusFind(SPI_BUS_NAME);
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motor_driver.motor_encoder.dev = BusFindDevice(motor_driver.motor_encoder.bus, SPI_DEVICE_NAME);
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motor_driver.motor_encoder.drv = BusFindDriver(motor_driver.motor_encoder.bus, SPI_DRV_NAME);
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// struct BusConfigureInfo configure_info;
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configure_info.configure_cmd = OPE_INT;
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BusDrvConfigure(motor_driver.motor_encoder.drv, &configure_info);
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// read once encoder data
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BusDevOpen(motor_driver.motor_encoder.dev);
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uint16_t read_data = 0;
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read_param.buffer = (void *)&read_data;
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read_param.size = 1;
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BusDevReadData(motor_driver.motor_encoder.dev, &read_param);
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motor_driver.motor_can_protocal.bus = BusFind(CAN_BUS_NAME);
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motor_driver.motor_can_protocal.dev = BusFindDevice(motor_driver.motor_can_protocal.bus, CAN_DEVICE_NAME);
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motor_driver.motor_can_protocal.drv = BusFindDriver(motor_driver.motor_can_protocal.bus, CAN_DRIVER_NAME);
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BusDevOpen(motor_driver.motor_can_protocal.dev);
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struct CanDriverConfigure can_config;
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can_config.brp = 5;
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can_config.mode = 0;
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can_config.tbs1 = 4;
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can_config.tbs2 = 3;
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can_config.tsjw = 0;
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configure_info.configure_cmd = OPE_INT;
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configure_info.private_data = (void *)&can_config;
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BusDrvConfigure(motor_driver.motor_can_protocal.drv, &configure_info);
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}
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int MotorStart(void)
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{
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set_motor_pid(
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2, 0, 0,
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0, 0, 0,
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0, 0, 0,
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0, 0, 0);
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foc_start();
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g_encoder_init_angle = g_encoder_angle;
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set_pwm_duty(0.2, 0, 0); // d轴强拖，形成SVPWM模型中的基础矢量1，即对应转子零度位置
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MdelayKTask(1000); // 等待电机转到零位
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g_rotor_zero_angle = g_encoder_angle;
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set_pwm_duty(0, 0, 0); // 松开电机
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MdelayKTask(1000); // 等待电机转到零位
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// delay_1ms(100);
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motor_control_context.type = control_type_mit_control;
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x_err_t flag;
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MdelayKTask(1);
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}
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SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN),
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m, MotorStart, motor start function);
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SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN),
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s, foc_stop, motor stop function);
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@ -0,0 +1,53 @@
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/*
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* Copyright (c) 2020 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file connect_adc.h
|
||||
* @brief define stm32f446ret6 adc function and struct
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2025-7-31
|
||||
*/
|
||||
|
||||
#ifndef CONNECT_MOTOR_H
|
||||
#define CONNECT_MOTOR_H
|
||||
|
||||
#include <device.h>
|
||||
|
||||
|
||||
struct XiZiCommonDevice
|
||||
{
|
||||
struct Bus *bus;
|
||||
struct HardwareDev *dev;
|
||||
struct Driver *drv;
|
||||
};
|
||||
|
||||
struct MotorDriver
|
||||
{
|
||||
struct XiZiCommonDevice motor_control;
|
||||
struct XiZiCommonDevice motor_encoder;
|
||||
struct XiZiCommonDevice motor_can_protocal;
|
||||
|
||||
int type; // 控制类型
|
||||
float position; // 位置控制目标 (rad)
|
||||
float speed; // 速度控制目标 (rad/s)
|
||||
float torque_norm_d; // 力矩控制目标 d 轴分量 (归一化)
|
||||
float torque_norm_q; // 力矩控制目标 q 轴分量 (归一化)
|
||||
float mit_torque; // MIT 控制目标力矩 (Nm)
|
||||
};
|
||||
|
||||
|
||||
int InitHwMotor(void);
|
||||
int MotorStart(void);
|
||||
void CanMsgReceived(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
int main(void)
|
||||
{
|
||||
printf("\nHello, Robot!\n");
|
||||
RobotInit();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
|
||||
|
||||
int algo_register()
|
||||
{
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,400 @@
|
|||
#include "foc.h"
|
||||
#include "motor_runtime_param.h"
|
||||
#include <stdbool.h>
|
||||
#include "math.h"
|
||||
|
||||
|
||||
void arm_inv_park_f32( float Id,
|
||||
float Iq,
|
||||
float * pIalpha,
|
||||
float * pIbeta,
|
||||
float sinVal,
|
||||
float cosVal)
|
||||
{
|
||||
/* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
|
||||
*pIalpha = Id * cosVal - Iq * sinVal;
|
||||
|
||||
/* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
|
||||
*pIbeta = Id * sinVal + Iq * cosVal;
|
||||
}
|
||||
|
||||
|
||||
motor_control_context_t motor_control_context;
|
||||
motor_status_e motor_status = motor_idle;
|
||||
|
||||
//interface function weak implement
|
||||
__attribute__((weak)) void set_pwm_duty(float d_u, float d_v, float d_w)
|
||||
{
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
|
||||
__attribute__((weak)) void __FOC_START()
|
||||
{
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
__attribute__((weak)) void __FOC_STOP()
|
||||
{
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
__attribute__((weak)) void __FOC_BREAK()
|
||||
{
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
|
||||
void foc_start(){
|
||||
__FOC_START();
|
||||
motor_status = motor_running;
|
||||
}
|
||||
|
||||
void foc_stop(){
|
||||
__FOC_STOP();
|
||||
motor_status = motor_idle;
|
||||
}
|
||||
|
||||
void foc_break(){
|
||||
__FOC_BREAK();
|
||||
motor_status = motor_break;
|
||||
}
|
||||
|
||||
static void svpwm(float phi, float d, float q, float *d_u, float *d_v, float *d_w)
|
||||
{
|
||||
d = min(d, 1);
|
||||
d = max(d, -1);
|
||||
q = min(q, 1);
|
||||
q = max(q, -1);
|
||||
const int v[6][3] = {{1, 0, 0}, {1, 1, 0}, {0, 1, 0}, {0, 1, 1}, {0, 0, 1}, {1, 0, 1}};
|
||||
const int K_to_sector[] = {4, 6, 5, 5, 3, 1, 2, 2};
|
||||
float sin_phi = sinf(phi);
|
||||
float cos_phi = cosf(phi);
|
||||
float alpha = 0;
|
||||
float beta = 0;
|
||||
arm_inv_park_f32(d, q, &alpha, &beta, sin_phi, cos_phi);
|
||||
|
||||
bool A = beta > 0;
|
||||
bool B = fabs(beta) > SQRT3 * fabs(alpha);
|
||||
bool C = alpha > 0;
|
||||
|
||||
int K = 4 * A + 2 * B + C;
|
||||
int sector = K_to_sector[K];
|
||||
|
||||
float t_m = sinf(sector * rad60) * alpha - cosf(sector * rad60) * beta;
|
||||
float t_n = beta * cosf(sector * rad60 - rad60) - alpha * sinf(sector * rad60 - rad60);
|
||||
float t_0 = 1 - t_m - t_n;
|
||||
|
||||
*d_u = t_m * v[sector - 1][0] + t_n * v[sector % 6][0] + t_0 / 2;
|
||||
*d_v = t_m * v[sector - 1][1] + t_n * v[sector % 6][1] + t_0 / 2;
|
||||
*d_w = t_m * v[sector - 1][2] + t_n * v[sector % 6][2] + t_0 / 2;
|
||||
motor_control_context.pwm_u = *d_u;
|
||||
}
|
||||
|
||||
void foc_forward(float d, float q, float rotor_rad)
|
||||
{
|
||||
float d_u = 0;
|
||||
float d_v = 0;
|
||||
float d_w = 0;
|
||||
svpwm(rotor_rad, d, q, &d_u, &d_v, &d_w);
|
||||
set_pwm_duty(d_u, d_v, d_w);
|
||||
}
|
||||
|
||||
float cycle_diff(float diff, float cycle)
|
||||
{
|
||||
if (diff > (cycle / 2))
|
||||
diff -= cycle;
|
||||
else if (diff < (-cycle / 2))
|
||||
diff += cycle;
|
||||
return diff;
|
||||
}
|
||||
|
||||
float low_pass_filter(float input, float last_output, float alpha)
|
||||
{
|
||||
return alpha * input + (1.0 - alpha) * last_output;
|
||||
}
|
||||
|
||||
// pid control implementation
|
||||
PID_t pid_position;
|
||||
PID_t pid_speed;
|
||||
PID_t pid_torque_d;
|
||||
PID_t pid_torque_q;
|
||||
void set_motor_pid(
|
||||
float position_p, float position_i, float position_d,
|
||||
float speed_p, float speed_i, float speed_d,
|
||||
float torque_d_p, float torque_d_i, float torque_d_d,
|
||||
float torque_q_p, float torque_q_i, float torque_q_d)
|
||||
{
|
||||
PID_Init(&pid_position, position_p, position_i, position_d, MAX_SPEED);
|
||||
PID_Init(&pid_speed, speed_p, speed_i, speed_d, MAX_CURRENT);
|
||||
PID_Init(&pid_torque_d, torque_d_p, torque_d_i, torque_d_d, 1.0f);
|
||||
PID_Init(&pid_torque_q, torque_q_p, torque_q_i, torque_q_d, 1.0f);
|
||||
}
|
||||
|
||||
static float position_loop(float rad)
|
||||
{
|
||||
float diff = rad - g_motor_logic_angle;
|
||||
return PID_Update(&pid_position, diff);
|
||||
}
|
||||
|
||||
void lib_position_control(float rad)
|
||||
{
|
||||
float d = 0;
|
||||
float q = position_loop(rad);
|
||||
foc_forward(d, q, rotor_logic_angle);
|
||||
}
|
||||
|
||||
|
||||
static float speed_loop(float speed_rad)
|
||||
{
|
||||
float diff = speed_rad - g_motor_speed;
|
||||
return PID_Update(&pid_speed, diff);
|
||||
}
|
||||
|
||||
|
||||
void lib_speed_control(float speed)
|
||||
{
|
||||
float d = 0;
|
||||
float q = speed_loop(speed);
|
||||
foc_forward(d, q, rotor_logic_angle);
|
||||
}
|
||||
|
||||
|
||||
static float torque_d_loop(float d)
|
||||
{
|
||||
float diff = d - g_motor_i_d / MAX_CURRENT;
|
||||
return PID_Update(&pid_torque_d, diff);
|
||||
}
|
||||
|
||||
static float torque_q_loop(float q)
|
||||
{
|
||||
float diff = q - g_motor_i_q / Nm_PER_A / MAX_CURRENT;
|
||||
return PID_Update(&pid_torque_q, diff);
|
||||
}
|
||||
|
||||
|
||||
void lib_torque_control(float torque_norm_d, float torque_norm_q)
|
||||
{
|
||||
float torque = torque_norm_q;
|
||||
float diff = torque - g_motor_i_q * Nm_PER_A * MAX_CURRENT;
|
||||
float q = g_motor_i_q + PID_Update(&pid_torque_q, diff);
|
||||
float d = 0;
|
||||
foc_forward(d, q, rotor_logic_angle);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
void lib_speed_torque_control(float speed_rad)
|
||||
{
|
||||
float torque_cmd = speed_loop(speed_rad);
|
||||
float d = 0;
|
||||
float q = torque_q_loop(torque_cmd);
|
||||
foc_forward(d, q, rotor_logic_angle);
|
||||
}
|
||||
|
||||
|
||||
void lib_position_speed_torque_control(float position_rad)
|
||||
{
|
||||
float speed_cmd = position_loop(position_rad);
|
||||
float torque_cmd = speed_loop(speed_cmd);
|
||||
float d = 0;
|
||||
float q = torque_q_loop(torque_cmd);
|
||||
foc_forward(d, q, rotor_logic_angle);
|
||||
}
|
||||
|
||||
|
||||
|
||||
void lib_position_to_target(float target_rad, float max_speed)
|
||||
{
|
||||
float speed_cmd = position_loop(target_rad);
|
||||
|
||||
if (speed_cmd > max_speed) speed_cmd = max_speed;
|
||||
else if (speed_cmd < -max_speed) speed_cmd = -max_speed;
|
||||
|
||||
float torque_cmd = speed_loop(speed_cmd);
|
||||
|
||||
float d = 0;
|
||||
float q = PID_Update(&pid_torque_q, torque_cmd - g_motor_i_q);
|
||||
foc_forward(d, q, rotor_logic_angle);
|
||||
}
|
||||
|
||||
|
||||
void PID_Init(PID_t *pid, float kp, float ki, float kd, float limit) {
|
||||
pid->kp = kp;
|
||||
pid->ki = ki;
|
||||
pid->kd = kd;
|
||||
pid->integral = 0.0f;
|
||||
pid->prev_error = 0.0f;
|
||||
pid->output_limit = limit;
|
||||
}
|
||||
|
||||
float PID_Update(PID_t *pid, float error) {
|
||||
pid->integral += error * dt;
|
||||
float derivative = (error - pid->prev_error) / dt;
|
||||
float output = pid->kp * error + pid->ki * pid->integral + pid->kd * derivative;
|
||||
|
||||
// <20><EFBFBD>
|
||||
if (output > pid->output_limit) output = pid->output_limit;
|
||||
else if (output < -pid->output_limit) output = -pid->output_limit;
|
||||
|
||||
pid->prev_error = error;
|
||||
return output;
|
||||
}
|
||||
|
||||
/*************************************************************
|
||||
* MIT 控制器 (Impedance Control)
|
||||
* 公式: τ_cmd = Kp * (q_d - q) + Kd * (qd_d - qd) + τ_ff
|
||||
* 其中：
|
||||
* q_d = 目标位置 (rad)
|
||||
* q = 当前电机位置 (rad)
|
||||
* qd_d = 目标速度 (rad/s)
|
||||
* qd = 当前电机速度 (rad/s)
|
||||
* τ_ff = 力矩前馈 (Nm)
|
||||
* τ_cmd = 目标力矩 (Nm)
|
||||
*
|
||||
* 核心流程：
|
||||
* 1. 读当前位置/速度
|
||||
* 2. 计算位置误差、速度误差
|
||||
* 3. 阻抗模型生成目标力矩 τ_cmd
|
||||
* 4. τ_cmd -> 目标电流 Iq -> 归一化 [-1,1]
|
||||
* 5. 走 FOC：svpwm -> set_pwm_duty
|
||||
*************************************************************/
|
||||
|
||||
typedef struct {
|
||||
float Kt_Nm_per_A; // 电机力矩常数 (Nm/A)，电机参数，例：0.08
|
||||
float torque_limit; // 力矩限幅 (Nm)，防止电机过载
|
||||
float iq_norm_limit; // 归一化电流限幅 [-1,1]，通常 <=1.0
|
||||
float vel_limit; // 速度限幅 (rad/s)，保护电机
|
||||
float pos_cycle; // 位置一圈的周期 (rad)，通常 2π
|
||||
float friction_comp; // 摩擦补偿力矩 (Nm)，可选
|
||||
float out_pos_limit; //输出软限位
|
||||
float current_loop_Ts;
|
||||
} MIT_Param_t;
|
||||
|
||||
// 默认参数（可以运行时通过 MIT_SetParams() 修改）
|
||||
static MIT_Param_t mit_param = {
|
||||
.Kt_Nm_per_A = 1.3473f, // 电机力矩常数 Nm/A
|
||||
.torque_limit = 9.58f, // 峰值扭矩 (Nm)
|
||||
.iq_norm_limit = 1.0f, // 电流归一化上限 (假设 1.0 = 最大电流 30A)
|
||||
.vel_limit = 40.0f, // 最大机械角速度 (rad/s)
|
||||
.pos_cycle = 2.0f * PI * Reduction_Ratio, // 一圈 2π rad 1：18的减速比
|
||||
.friction_comp = 0.0f, // 暂时不用摩擦补偿
|
||||
.out_pos_limit = 40.0f * PI, // 输出软限位
|
||||
.current_loop_Ts = 0.00004 //ADC采样周期
|
||||
};
|
||||
/*************************************************************
|
||||
* 参数配置接口
|
||||
*************************************************************/
|
||||
void MIT_SetParams(float Kt, float torque_lim, float iq_norm_lim,
|
||||
float vel_lim, float pos_cycle, float fric_comp)
|
||||
{
|
||||
mit_param.Kt_Nm_per_A = Kt;
|
||||
mit_param.torque_limit = torque_lim;
|
||||
mit_param.iq_norm_limit = (iq_norm_lim > 1.0f) ? 1.0f :
|
||||
(iq_norm_lim < 0.0f ? 0.0f : iq_norm_lim);
|
||||
mit_param.vel_limit = vel_lim;
|
||||
mit_param.pos_cycle = pos_cycle;
|
||||
mit_param.friction_comp = fric_comp;
|
||||
}
|
||||
|
||||
/*************************************************************
|
||||
* MIT 控制函数
|
||||
*
|
||||
* 输入：
|
||||
* pos_des = 目标角度 (rad)
|
||||
* vel_des = 目标速度 (rad/s)
|
||||
* kp = 位置刚度 (Nm/rad)
|
||||
* kd = 速度阻尼 (Nm/(rad/s))
|
||||
* tau_ff = 力矩前馈 (Nm)
|
||||
*
|
||||
* 注意：
|
||||
* 1. 该函数会直接调用 foc_forward() 输出 PWM
|
||||
* 2. motor_logic_angle, motor_speed 需在主程序中更新
|
||||
* 3. motor_status == motor_running 时才执行
|
||||
*************************************************************/
|
||||
void lib_mit_control(float pos_des, float vel_des,
|
||||
float kp, float kd, float tau_ff)
|
||||
{
|
||||
/************* 1. 读取当前状态 *************/
|
||||
float pos_meas = g_motor_logic_angle; // 电机内圈角度 (rad)
|
||||
float vel_meas = g_motor_speed; // 当前电机速度 (rad/s)
|
||||
|
||||
// 速度限幅
|
||||
if (fabsf(vel_meas) > mit_param.vel_limit) {
|
||||
vel_meas = (vel_meas > 0) ? mit_param.vel_limit : -mit_param.vel_limit;
|
||||
}
|
||||
|
||||
// 角度限幅
|
||||
float outer_meas = pos_meas / Reduction_Ratio; //电机外圈角度
|
||||
if (outer_meas > mit_param.out_pos_limit) outer_meas = mit_param.out_pos_limit;
|
||||
if (outer_meas < -mit_param.out_pos_limit) outer_meas = -mit_param.out_pos_limit;
|
||||
pos_meas = outer_meas;
|
||||
|
||||
float outer_des = pos_des / Reduction_Ratio; //电机外圈角度
|
||||
if (outer_des > mit_param.out_pos_limit) outer_des = mit_param.out_pos_limit;
|
||||
if (outer_des < -mit_param.out_pos_limit) outer_des = -mit_param.out_pos_limit;
|
||||
pos_des = outer_des;
|
||||
|
||||
/************* 2. 计算误差 *************/
|
||||
float pos_err = (pos_des - pos_meas);
|
||||
float vel_err = vel_des - vel_meas;
|
||||
|
||||
if (fabsf(pos_err) <= 0.01f)
|
||||
motor_control_context.position_reached_flag = 1;
|
||||
else
|
||||
motor_control_context.position_reached_flag = 0;
|
||||
|
||||
/************* 3. 力矩前馈（位置/速度环输出） *************/
|
||||
float tau_cmd = kp * pos_err + kd * vel_err + tau_ff;
|
||||
|
||||
// 摩擦补偿
|
||||
if (mit_param.friction_comp > 0.0f) {
|
||||
if (vel_meas > 1e-4f) tau_cmd += mit_param.friction_comp;
|
||||
if (vel_meas < -1e-4f) tau_cmd -= mit_param.friction_comp;
|
||||
}
|
||||
|
||||
// 力矩限幅
|
||||
if (tau_cmd > mit_param.torque_limit) tau_cmd = mit_param.torque_limit;
|
||||
if (tau_cmd < -mit_param.torque_limit) tau_cmd = -mit_param.torque_limit;
|
||||
|
||||
/************* 4. 电流参考 (归一化) *************/
|
||||
float iq_ref = tau_cmd / (mit_param.Kt_Nm_per_A + 1e-9f) / MAX_CURRENT / 1.3;
|
||||
|
||||
// 限幅
|
||||
if (iq_ref > mit_param.iq_norm_limit) iq_ref = mit_param.iq_norm_limit;
|
||||
if (iq_ref < -mit_param.iq_norm_limit) iq_ref = -mit_param.iq_norm_limit;
|
||||
|
||||
/************* 5. Q轴 PI 控制 *************/
|
||||
static float iq_integral = 0; // 静态变量保存积分
|
||||
float iq_meas = g_motor_i_q; // 归一化 q 轴电流
|
||||
float iq_err = iq_ref - iq_meas;
|
||||
// PI 增益
|
||||
float Kp_iq = 2.0f; // P 增益，可调
|
||||
float Ki_iq = 0.5f; // I 增益，可调
|
||||
float Ts = mit_param.current_loop_Ts > 0 ? mit_param.current_loop_Ts : 0.00004f; // 电流环采样周期
|
||||
|
||||
// 积分更新
|
||||
iq_integral += Ki_iq * iq_err * Ts;
|
||||
if (iq_integral > 0.9f) iq_integral = 0.9f;
|
||||
if (iq_integral < -0.9f) iq_integral = -0.9f;
|
||||
|
||||
// 输出电压归一化 [-vdq_max, vdq_max]
|
||||
float vdq_max = 0.95f;
|
||||
float v_q = 0;
|
||||
if(fabs(tau_ff) > 2.5){
|
||||
v_q = Kp_iq * iq_err + iq_integral;
|
||||
} else {
|
||||
v_q = iq_ref;
|
||||
}
|
||||
// float v_q = iq_ref;
|
||||
|
||||
if (v_q > vdq_max) v_q = vdq_max;
|
||||
if (v_q < -vdq_max) v_q = -vdq_max;
|
||||
/************* 6. D轴保持 0 *************/
|
||||
float v_d = 0.0f;
|
||||
|
||||
/************* 7. 发送到 FOC *************/
|
||||
foc_forward(v_d, v_q, rotor_logic_angle);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,329 @@
|
|||
#include "controller_functions.h"
|
||||
#include "fast_math_functions.h"
|
||||
|
||||
float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1] = {
|
||||
0.00000000f, 0.01227154f, 0.02454123f, 0.03680722f, 0.04906767f, 0.06132074f,
|
||||
0.07356456f, 0.08579731f, 0.09801714f, 0.11022221f, 0.12241068f, 0.13458071f,
|
||||
0.14673047f, 0.15885814f, 0.17096189f, 0.18303989f, 0.19509032f, 0.20711138f,
|
||||
0.21910124f, 0.23105811f, 0.24298018f, 0.25486566f, 0.26671276f, 0.27851969f,
|
||||
0.29028468f, 0.30200595f, 0.31368174f, 0.32531029f, 0.33688985f, 0.34841868f,
|
||||
0.35989504f, 0.37131719f, 0.38268343f, 0.39399204f, 0.40524131f, 0.41642956f,
|
||||
0.42755509f, 0.43861624f, 0.44961133f, 0.46053871f, 0.47139674f, 0.48218377f,
|
||||
0.49289819f, 0.50353838f, 0.51410274f, 0.52458968f, 0.53499762f, 0.54532499f,
|
||||
0.55557023f, 0.56573181f, 0.57580819f, 0.58579786f, 0.59569930f, 0.60551104f,
|
||||
0.61523159f, 0.62485949f, 0.63439328f, 0.64383154f, 0.65317284f, 0.66241578f,
|
||||
0.67155895f, 0.68060100f, 0.68954054f, 0.69837625f, 0.70710678f, 0.71573083f,
|
||||
0.72424708f, 0.73265427f, 0.74095113f, 0.74913639f, 0.75720885f, 0.76516727f,
|
||||
0.77301045f, 0.78073723f, 0.78834643f, 0.79583690f, 0.80320753f, 0.81045720f,
|
||||
0.81758481f, 0.82458930f, 0.83146961f, 0.83822471f, 0.84485357f, 0.85135519f,
|
||||
0.85772861f, 0.86397286f, 0.87008699f, 0.87607009f, 0.88192126f, 0.88763962f,
|
||||
0.89322430f, 0.89867447f, 0.90398929f, 0.90916798f, 0.91420976f, 0.91911385f,
|
||||
0.92387953f, 0.92850608f, 0.93299280f, 0.93733901f, 0.94154407f, 0.94560733f,
|
||||
0.94952818f, 0.95330604f, 0.95694034f, 0.96043052f, 0.96377607f, 0.96697647f,
|
||||
0.97003125f, 0.97293995f, 0.97570213f, 0.97831737f, 0.98078528f, 0.98310549f,
|
||||
0.98527764f, 0.98730142f, 0.98917651f, 0.99090264f, 0.99247953f, 0.99390697f,
|
||||
0.99518473f, 0.99631261f, 0.99729046f, 0.99811811f, 0.99879546f, 0.99932238f,
|
||||
0.99969882f, 0.99992470f, 1.00000000f, 0.99992470f, 0.99969882f, 0.99932238f,
|
||||
0.99879546f, 0.99811811f, 0.99729046f, 0.99631261f, 0.99518473f, 0.99390697f,
|
||||
0.99247953f, 0.99090264f, 0.98917651f, 0.98730142f, 0.98527764f, 0.98310549f,
|
||||
0.98078528f, 0.97831737f, 0.97570213f, 0.97293995f, 0.97003125f, 0.96697647f,
|
||||
0.96377607f, 0.96043052f, 0.95694034f, 0.95330604f, 0.94952818f, 0.94560733f,
|
||||
0.94154407f, 0.93733901f, 0.93299280f, 0.92850608f, 0.92387953f, 0.91911385f,
|
||||
0.91420976f, 0.90916798f, 0.90398929f, 0.89867447f, 0.89322430f, 0.88763962f,
|
||||
0.88192126f, 0.87607009f, 0.87008699f, 0.86397286f, 0.85772861f, 0.85135519f,
|
||||
0.84485357f, 0.83822471f, 0.83146961f, 0.82458930f, 0.81758481f, 0.81045720f,
|
||||
0.80320753f, 0.79583690f, 0.78834643f, 0.78073723f, 0.77301045f, 0.76516727f,
|
||||
0.75720885f, 0.74913639f, 0.74095113f, 0.73265427f, 0.72424708f, 0.71573083f,
|
||||
0.70710678f, 0.69837625f, 0.68954054f, 0.68060100f, 0.67155895f, 0.66241578f,
|
||||
0.65317284f, 0.64383154f, 0.63439328f, 0.62485949f, 0.61523159f, 0.60551104f,
|
||||
0.59569930f, 0.58579786f, 0.57580819f, 0.56573181f, 0.55557023f, 0.54532499f,
|
||||
0.53499762f, 0.52458968f, 0.51410274f, 0.50353838f, 0.49289819f, 0.48218377f,
|
||||
0.47139674f, 0.46053871f, 0.44961133f, 0.43861624f, 0.42755509f, 0.41642956f,
|
||||
0.40524131f, 0.39399204f, 0.38268343f, 0.37131719f, 0.35989504f, 0.34841868f,
|
||||
0.33688985f, 0.32531029f, 0.31368174f, 0.30200595f, 0.29028468f, 0.27851969f,
|
||||
0.26671276f, 0.25486566f, 0.24298018f, 0.23105811f, 0.21910124f, 0.20711138f,
|
||||
0.19509032f, 0.18303989f, 0.17096189f, 0.15885814f, 0.14673047f, 0.13458071f,
|
||||
0.12241068f, 0.11022221f, 0.09801714f, 0.08579731f, 0.07356456f, 0.06132074f,
|
||||
0.04906767f, 0.03680722f, 0.02454123f, 0.01227154f, 0.00000000f, -0.01227154f,
|
||||
-0.02454123f, -0.03680722f, -0.04906767f, -0.06132074f, -0.07356456f,
|
||||
-0.08579731f, -0.09801714f, -0.11022221f, -0.12241068f, -0.13458071f,
|
||||
-0.14673047f, -0.15885814f, -0.17096189f, -0.18303989f, -0.19509032f,
|
||||
-0.20711138f, -0.21910124f, -0.23105811f, -0.24298018f, -0.25486566f,
|
||||
-0.26671276f, -0.27851969f, -0.29028468f, -0.30200595f, -0.31368174f,
|
||||
-0.32531029f, -0.33688985f, -0.34841868f, -0.35989504f, -0.37131719f,
|
||||
-0.38268343f, -0.39399204f, -0.40524131f, -0.41642956f, -0.42755509f,
|
||||
-0.43861624f, -0.44961133f, -0.46053871f, -0.47139674f, -0.48218377f,
|
||||
-0.49289819f, -0.50353838f, -0.51410274f, -0.52458968f, -0.53499762f,
|
||||
-0.54532499f, -0.55557023f, -0.56573181f, -0.57580819f, -0.58579786f,
|
||||
-0.59569930f, -0.60551104f, -0.61523159f, -0.62485949f, -0.63439328f,
|
||||
-0.64383154f, -0.65317284f, -0.66241578f, -0.67155895f, -0.68060100f,
|
||||
-0.68954054f, -0.69837625f, -0.70710678f, -0.71573083f, -0.72424708f,
|
||||
-0.73265427f, -0.74095113f, -0.74913639f, -0.75720885f, -0.76516727f,
|
||||
-0.77301045f, -0.78073723f, -0.78834643f, -0.79583690f, -0.80320753f,
|
||||
-0.81045720f, -0.81758481f, -0.82458930f, -0.83146961f, -0.83822471f,
|
||||
-0.84485357f, -0.85135519f, -0.85772861f, -0.86397286f, -0.87008699f,
|
||||
-0.87607009f, -0.88192126f, -0.88763962f, -0.89322430f, -0.89867447f,
|
||||
-0.90398929f, -0.90916798f, -0.91420976f, -0.91911385f, -0.92387953f,
|
||||
-0.92850608f, -0.93299280f, -0.93733901f, -0.94154407f, -0.94560733f,
|
||||
-0.94952818f, -0.95330604f, -0.95694034f, -0.96043052f, -0.96377607f,
|
||||
-0.96697647f, -0.97003125f, -0.97293995f, -0.97570213f, -0.97831737f,
|
||||
-0.98078528f, -0.98310549f, -0.98527764f, -0.98730142f, -0.98917651f,
|
||||
-0.99090264f, -0.99247953f, -0.99390697f, -0.99518473f, -0.99631261f,
|
||||
-0.99729046f, -0.99811811f, -0.99879546f, -0.99932238f, -0.99969882f,
|
||||
-0.99992470f, -1.00000000f, -0.99992470f, -0.99969882f, -0.99932238f,
|
||||
-0.99879546f, -0.99811811f, -0.99729046f, -0.99631261f, -0.99518473f,
|
||||
-0.99390697f, -0.99247953f, -0.99090264f, -0.98917651f, -0.98730142f,
|
||||
-0.98527764f, -0.98310549f, -0.98078528f, -0.97831737f, -0.97570213f,
|
||||
-0.97293995f, -0.97003125f, -0.96697647f, -0.96377607f, -0.96043052f,
|
||||
-0.95694034f, -0.95330604f, -0.94952818f, -0.94560733f, -0.94154407f,
|
||||
-0.93733901f, -0.93299280f, -0.92850608f, -0.92387953f, -0.91911385f,
|
||||
-0.91420976f, -0.90916798f, -0.90398929f, -0.89867447f, -0.89322430f,
|
||||
-0.88763962f, -0.88192126f, -0.87607009f, -0.87008699f, -0.86397286f,
|
||||
-0.85772861f, -0.85135519f, -0.84485357f, -0.83822471f, -0.83146961f,
|
||||
-0.82458930f, -0.81758481f, -0.81045720f, -0.80320753f, -0.79583690f,
|
||||
-0.78834643f, -0.78073723f, -0.77301045f, -0.76516727f, -0.75720885f,
|
||||
-0.74913639f, -0.74095113f, -0.73265427f, -0.72424708f, -0.71573083f,
|
||||
-0.70710678f, -0.69837625f, -0.68954054f, -0.68060100f, -0.67155895f,
|
||||
-0.66241578f, -0.65317284f, -0.64383154f, -0.63439328f, -0.62485949f,
|
||||
-0.61523159f, -0.60551104f, -0.59569930f, -0.58579786f, -0.57580819f,
|
||||
-0.56573181f, -0.55557023f, -0.54532499f, -0.53499762f, -0.52458968f,
|
||||
-0.51410274f, -0.50353838f, -0.49289819f, -0.48218377f, -0.47139674f,
|
||||
-0.46053871f, -0.44961133f, -0.43861624f, -0.42755509f, -0.41642956f,
|
||||
-0.40524131f, -0.39399204f, -0.38268343f, -0.37131719f, -0.35989504f,
|
||||
-0.34841868f, -0.33688985f, -0.32531029f, -0.31368174f, -0.30200595f,
|
||||
-0.29028468f, -0.27851969f, -0.26671276f, -0.25486566f, -0.24298018f,
|
||||
-0.23105811f, -0.21910124f, -0.20711138f, -0.19509032f, -0.18303989f,
|
||||
-0.17096189f, -0.15885814f, -0.14673047f, -0.13458071f, -0.12241068f,
|
||||
-0.11022221f, -0.09801714f, -0.08579731f, -0.07356456f, -0.06132074f,
|
||||
-0.04906767f, -0.03680722f, -0.02454123f, -0.01227154f, -0.00000000f
|
||||
};
|
||||
/**
|
||||
@addtogroup PID
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@brief Initialization function for the floating-point PID Control.
|
||||
@param[in,out] S points to an instance of the PID structure
|
||||
@param[in] resetStateFlag
|
||||
- value = 0: no change in state
|
||||
- value = 1: reset state
|
||||
@return none
|
||||
|
||||
@par Details
|
||||
The <code>resetStateFlag</code> specifies whether to set state to zero or not. \n
|
||||
The function computes the structure fields: <code>A0</code>, <code>A1</code> <code>A2</code>
|
||||
using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)
|
||||
also sets the state variables to all zeros.
|
||||
*/
|
||||
|
||||
void arm_pid_init_f32(arm_pid_instance_f32 * S,int32_t resetStateFlag)
|
||||
{
|
||||
/* Derived coefficient A0 */
|
||||
S->A0 = S->Kp + S->Ki + S->Kd;
|
||||
|
||||
/* Derived coefficient A1 */
|
||||
S->A1 = (-S->Kp) - ((float32_t) 2.0f * S->Kd);
|
||||
|
||||
/* Derived coefficient A2 */
|
||||
S->A2 = S->Kd;
|
||||
|
||||
/* Check whether state needs reset or not */
|
||||
if (resetStateFlag)
|
||||
{
|
||||
/* Reset state to zero, The size will be always 3 samples */
|
||||
memset(S->state, 0, 3U * sizeof(float32_t));
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
@} end of PID group
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
@ingroup groupFastMath
|
||||
*/
|
||||
|
||||
/**
|
||||
@defgroup sin Sine
|
||||
|
||||
Computes the trigonometric sine function using a combination of table lookup
|
||||
and linear interpolation. There are separate functions for
|
||||
Q15, Q31, and floating-point data types.
|
||||
The input to the floating-point version is in radians while the
|
||||
fixed-point Q15 and Q31 have a scaled input with the range
|
||||
[0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a
|
||||
value of 2*pi wraps around to 0.
|
||||
|
||||
The implementation is based on table lookup using 512 values together with linear interpolation.
|
||||
The steps used are:
|
||||
-# Calculation of the nearest integer table index
|
||||
-# Compute the fractional portion (fract) of the table index.
|
||||
-# The final result equals <code>(1.0f-fract)*a + fract*b;</code>
|
||||
|
||||
where
|
||||
<pre>
|
||||
b = Table[index];
|
||||
c = Table[index+1];
|
||||
</pre>
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup sin
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@brief Fast approximation to the trigonometric sine function for floating-point data.
|
||||
@param[in] x input value in radians.
|
||||
@return sin(x)
|
||||
*/
|
||||
|
||||
float32_t arm_sin_f32(float32_t x)
|
||||
{
|
||||
float32_t sinVal, fract, in; /* Temporary input, output variables */
|
||||
uint16_t index; /* Index variable */
|
||||
float32_t a, b; /* Two nearest output values */
|
||||
int32_t n;
|
||||
float32_t findex;
|
||||
|
||||
/* input x is in radians */
|
||||
/* Scale input to [0 1] range from [0 2*PI] , divide input by 2*pi */
|
||||
in = x * 0.159154943092f;
|
||||
|
||||
/* Calculation of floor value of input */
|
||||
n = (int32_t) in;
|
||||
|
||||
/* Make negative values towards -infinity */
|
||||
if (in < 0.0f)
|
||||
{
|
||||
n--;
|
||||
}
|
||||
|
||||
/* Map input value to [0 1] */
|
||||
in = in - (float32_t) n;
|
||||
|
||||
/* Calculation of index of the table */
|
||||
findex = (float32_t)FAST_MATH_TABLE_SIZE * in;
|
||||
index = (uint16_t)findex;
|
||||
|
||||
/* when "in" is exactly 1, we need to rotate the index down to 0 */
|
||||
if (index >= FAST_MATH_TABLE_SIZE) {
|
||||
index = 0;
|
||||
findex -= (float32_t)FAST_MATH_TABLE_SIZE;
|
||||
}
|
||||
|
||||
/* fractional value calculation */
|
||||
fract = findex - (float32_t) index;
|
||||
|
||||
/* Read two nearest values of input value from the sin table */
|
||||
a = sinTable_f32[index];
|
||||
b = sinTable_f32[index+1];
|
||||
|
||||
/* Linear interpolation process */
|
||||
sinVal = (1.0f - fract) * a + fract * b;
|
||||
|
||||
/* Return output value */
|
||||
return (sinVal);
|
||||
}
|
||||
|
||||
/**
|
||||
@} end of sin group
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
@ingroup groupFastMath
|
||||
*/
|
||||
|
||||
/**
|
||||
@defgroup cos Cosine
|
||||
|
||||
Computes the trigonometric cosine function using a combination of table lookup
|
||||
and linear interpolation. There are separate functions for
|
||||
Q15, Q31, and floating-point data types.
|
||||
The input to the floating-point version is in radians while the
|
||||
fixed-point Q15 and Q31 have a scaled input with the range
|
||||
[0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a
|
||||
value of 2*pi wraps around to 0.
|
||||
|
||||
The implementation is based on table lookup using 512 values together with linear interpolation.
|
||||
The steps used are:
|
||||
-# Calculation of the nearest integer table index
|
||||
-# Compute the fractional portion (fract) of the table index.
|
||||
-# The final result equals <code>(1.0f-fract)*a + fract*b;</code>
|
||||
|
||||
where
|
||||
<pre>
|
||||
a = Table[index];
|
||||
b = Table[index+1];
|
||||
</pre>
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup cos
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@brief Fast approximation to the trigonometric cosine function for floating-point data.
|
||||
@param[in] x input value in radians
|
||||
@return cos(x)
|
||||
*/
|
||||
float32_t arm_cos_f32(float32_t x)
|
||||
{
|
||||
float32_t cosVal, fract, in; /* Temporary input, output variables */
|
||||
uint16_t index; /* Index variable */
|
||||
float32_t a, b; /* Two nearest output values */
|
||||
int32_t n;
|
||||
float32_t findex;
|
||||
|
||||
/* input x is in radians */
|
||||
/* Scale input to [0 1] range from [0 2*PI] , divide input by 2*pi, add 0.25 (pi/2) to read sine table */
|
||||
in = x * 0.159154943092f + 0.25f;
|
||||
|
||||
/* Calculation of floor value of input */
|
||||
n = (int32_t) in;
|
||||
|
||||
/* Make negative values towards -infinity */
|
||||
if (in < 0.0f)
|
||||
{
|
||||
n--;
|
||||
}
|
||||
|
||||
/* Map input value to [0 1] */
|
||||
in = in - (float32_t) n;
|
||||
|
||||
/* Calculation of index of the table */
|
||||
findex = (float32_t)FAST_MATH_TABLE_SIZE * in;
|
||||
index = (uint16_t)findex;
|
||||
|
||||
/* when "in" is exactly 1, we need to rotate the index down to 0 */
|
||||
if (index >= FAST_MATH_TABLE_SIZE) {
|
||||
index = 0;
|
||||
findex -= (float32_t)FAST_MATH_TABLE_SIZE;
|
||||
}
|
||||
|
||||
/* fractional value calculation */
|
||||
fract = findex - (float32_t) index;
|
||||
|
||||
/* Read two nearest values of input value from the cos table */
|
||||
a = sinTable_f32[index];
|
||||
b = sinTable_f32[index+1];
|
||||
|
||||
/* Linear interpolation process */
|
||||
cosVal = (1.0f - fract) * a + fract * b;
|
||||
|
||||
/* Return output value */
|
||||
return (cosVal);
|
||||
}
|
||||
|
||||
/**
|
||||
@} end of cos group
|
||||
*/
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
#pragma once
|
||||
|
||||
#define POLE_PAIRS 7
|
||||
|
||||
#define R_SHUNT 0.02
|
||||
#define OP_GAIN 50
|
||||
#define I_RMS_CONT 5.6f
|
||||
#define I_PEAK_CONT (I_RMS_CONT * 1.41421356f)
|
||||
#define MAX_CURRENT I_PEAK_CONT
|
||||
#define Nm_PER_A 1.3473
|
||||
#define ADC_REFERENCE_VOLT 3.3
|
||||
#define ADC_BITS 12
|
||||
#define MAX_SPEED 15.49
|
||||
#define Reduction_Ratio 18
|
||||
|
||||
#define motor_pwm_freq 20000
|
||||
// #define motor_speed_calc_freq 1000
|
||||
#define dt 0.001
|
||||
|
||||
#define position_cycle Reduction_Ratio*2 *3.14159265358979
|
||||
#define mult_position_cycle 3*Reduction_Ratio*2 *3.14159265358979
|
||||
#ifndef PI
|
||||
#define PI 3.14159265358979
|
||||
#endif
|
||||
#define deg2rad(a) (PI * (a) / 180)
|
||||
#define rad2deg(a) (180 * (a) / PI)
|
||||
#define max(a, b) ((a) > (b) ? (a) : (b))
|
||||
#define min(a, b) ((a) < (b) ? (a) : (b))
|
||||
|
||||
#define RAW_TO_RAD (2.0f * PI / 65536.0f)
|
||||
#define RAW_TO_GRE (360.0f / 65536.0f)
|
||||
|
|
@ -0,0 +1,539 @@
|
|||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_common_tables.h
|
||||
* Description: Extern declaration for common tables
|
||||
*
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_COMMON_TABLES_H
|
||||
#define _ARM_COMMON_TABLES_H
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "dsp/fast_math_functions.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
|
||||
/* Double Precision Float CFFT twiddles */
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024)
|
||||
extern const uint16_t armBitRevTable[1024];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_16)
|
||||
extern const uint64_t twiddleCoefF64_16[32];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_32)
|
||||
extern const uint64_t twiddleCoefF64_32[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_64)
|
||||
extern const uint64_t twiddleCoefF64_64[128];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_128)
|
||||
extern const uint64_t twiddleCoefF64_128[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_256)
|
||||
extern const uint64_t twiddleCoefF64_256[512];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_512)
|
||||
extern const uint64_t twiddleCoefF64_512[1024];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_1024)
|
||||
extern const uint64_t twiddleCoefF64_1024[2048];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_2048)
|
||||
extern const uint64_t twiddleCoefF64_2048[4096];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_4096)
|
||||
extern const uint64_t twiddleCoefF64_4096[8192];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16)
|
||||
extern const float32_t twiddleCoef_16[32];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32)
|
||||
extern const float32_t twiddleCoef_32[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64)
|
||||
extern const float32_t twiddleCoef_64[128];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128)
|
||||
extern const float32_t twiddleCoef_128[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256)
|
||||
extern const float32_t twiddleCoef_256[512];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512)
|
||||
extern const float32_t twiddleCoef_512[1024];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024)
|
||||
extern const float32_t twiddleCoef_1024[2048];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048)
|
||||
extern const float32_t twiddleCoef_2048[4096];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096)
|
||||
extern const float32_t twiddleCoef_4096[8192];
|
||||
#define twiddleCoef twiddleCoef_4096
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
/* Q31 */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16)
|
||||
extern const q31_t twiddleCoef_16_q31[24];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32)
|
||||
extern const q31_t twiddleCoef_32_q31[48];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64)
|
||||
extern const q31_t twiddleCoef_64_q31[96];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128)
|
||||
extern const q31_t twiddleCoef_128_q31[192];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256)
|
||||
extern const q31_t twiddleCoef_256_q31[384];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512)
|
||||
extern const q31_t twiddleCoef_512_q31[768];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024)
|
||||
extern const q31_t twiddleCoef_1024_q31[1536];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)
|
||||
extern const q31_t twiddleCoef_2048_q31[3072];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096)
|
||||
extern const q31_t twiddleCoef_4096_q31[6144];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16)
|
||||
extern const q15_t twiddleCoef_16_q15[24];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32)
|
||||
extern const q15_t twiddleCoef_32_q15[48];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64)
|
||||
extern const q15_t twiddleCoef_64_q15[96];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128)
|
||||
extern const q15_t twiddleCoef_128_q15[192];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256)
|
||||
extern const q15_t twiddleCoef_256_q15[384];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512)
|
||||
extern const q15_t twiddleCoef_512_q15[768];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024)
|
||||
extern const q15_t twiddleCoef_1024_q15[1536];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)
|
||||
extern const q15_t twiddleCoef_2048_q15[3072];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096)
|
||||
extern const q15_t twiddleCoef_4096_q15[6144];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
/* Double Precision Float RFFT twiddles */
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32)
|
||||
extern const uint64_t twiddleCoefF64_rfft_32[32];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64)
|
||||
extern const uint64_t twiddleCoefF64_rfft_64[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128)
|
||||
extern const uint64_t twiddleCoefF64_rfft_128[128];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256)
|
||||
extern const uint64_t twiddleCoefF64_rfft_256[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512)
|
||||
extern const uint64_t twiddleCoefF64_rfft_512[512];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024)
|
||||
extern const uint64_t twiddleCoefF64_rfft_1024[1024];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048)
|
||||
extern const uint64_t twiddleCoefF64_rfft_2048[2048];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096)
|
||||
extern const uint64_t twiddleCoefF64_rfft_4096[4096];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32)
|
||||
extern const float32_t twiddleCoef_rfft_32[32];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64)
|
||||
extern const float32_t twiddleCoef_rfft_64[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128)
|
||||
extern const float32_t twiddleCoef_rfft_128[128];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256)
|
||||
extern const float32_t twiddleCoef_rfft_256[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512)
|
||||
extern const float32_t twiddleCoef_rfft_512[512];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024)
|
||||
extern const float32_t twiddleCoef_rfft_1024[1024];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048)
|
||||
extern const float32_t twiddleCoef_rfft_2048[2048];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096)
|
||||
extern const float32_t twiddleCoef_rfft_4096[4096];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
|
||||
/* Double precision floating-point bit reversal tables */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_16)
|
||||
#define ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH ((uint16_t)12)
|
||||
extern const uint16_t armBitRevIndexTableF64_16[ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_32)
|
||||
#define ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH ((uint16_t)24)
|
||||
extern const uint16_t armBitRevIndexTableF64_32[ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_64)
|
||||
#define ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH ((uint16_t)56)
|
||||
extern const uint16_t armBitRevIndexTableF64_64[ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_128)
|
||||
#define ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH ((uint16_t)112)
|
||||
extern const uint16_t armBitRevIndexTableF64_128[ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_256)
|
||||
#define ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH ((uint16_t)240)
|
||||
extern const uint16_t armBitRevIndexTableF64_256[ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_512)
|
||||
#define ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH ((uint16_t)480)
|
||||
extern const uint16_t armBitRevIndexTableF64_512[ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_1024)
|
||||
#define ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH ((uint16_t)992)
|
||||
extern const uint16_t armBitRevIndexTableF64_1024[ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_2048)
|
||||
#define ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH ((uint16_t)1984)
|
||||
extern const uint16_t armBitRevIndexTableF64_2048[ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_4096)
|
||||
#define ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
extern const uint16_t armBitRevIndexTableF64_4096[ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
/* floating-point bit reversal tables */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16)
|
||||
#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
|
||||
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32)
|
||||
#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
|
||||
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64)
|
||||
#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
|
||||
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128)
|
||||
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
|
||||
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256)
|
||||
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
|
||||
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512)
|
||||
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
|
||||
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024)
|
||||
#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
|
||||
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048)
|
||||
#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
|
||||
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096)
|
||||
#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
|
||||
/* fixed-point bit reversal tables */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32)
|
||||
extern const float32_t realCoefA[8192];
|
||||
extern const float32_t realCoefB[8192];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31)
|
||||
extern const q31_t realCoefAQ31[8192];
|
||||
extern const q31_t realCoefBQ31[8192];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15)
|
||||
extern const q15_t realCoefAQ15[8192];
|
||||
extern const q15_t realCoefBQ15[8192];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128)
|
||||
extern const float32_t Weights_128[256];
|
||||
extern const float32_t cos_factors_128[128];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512)
|
||||
extern const float32_t Weights_512[1024];
|
||||
extern const float32_t cos_factors_512[512];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048)
|
||||
extern const float32_t Weights_2048[4096];
|
||||
extern const float32_t cos_factors_2048[2048];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192)
|
||||
extern const float32_t Weights_8192[16384];
|
||||
extern const float32_t cos_factors_8192[8192];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128)
|
||||
extern const q15_t WeightsQ15_128[256];
|
||||
extern const q15_t cos_factorsQ15_128[128];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512)
|
||||
extern const q15_t WeightsQ15_512[1024];
|
||||
extern const q15_t cos_factorsQ15_512[512];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048)
|
||||
extern const q15_t WeightsQ15_2048[4096];
|
||||
extern const q15_t cos_factorsQ15_2048[2048];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192)
|
||||
extern const q15_t WeightsQ15_8192[16384];
|
||||
extern const q15_t cos_factorsQ15_8192[8192];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128)
|
||||
extern const q31_t WeightsQ31_128[256];
|
||||
extern const q31_t cos_factorsQ31_128[128];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512)
|
||||
extern const q31_t WeightsQ31_512[1024];
|
||||
extern const q31_t cos_factorsQ31_512[512];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048)
|
||||
extern const q31_t WeightsQ31_2048[4096];
|
||||
extern const q31_t cos_factorsQ31_2048[2048];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192)
|
||||
extern const q31_t WeightsQ31_8192[16384];
|
||||
extern const q31_t cos_factorsQ31_8192[8192];
|
||||
#endif
|
||||
|
||||
#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15)
|
||||
extern const q15_t armRecipTableQ15[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31)
|
||||
extern const q31_t armRecipTableQ31[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
|
||||
/* Tables for Fast Math Sine and Cosine */
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32)
|
||||
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31)
|
||||
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15)
|
||||
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
|
||||
/* Fast vector sqrt */
|
||||
#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE)
|
||||
extern const q31_t sqrtTable_Q31[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
#endif
|
||||
|
||||
/* Accurate scalar sqrt */
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q31)
|
||||
extern const q31_t sqrt_initial_lut_q31[32];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q15)
|
||||
extern const q15_t sqrt_initial_lut_q15[16];
|
||||
#endif
|
||||
|
||||
#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE)
|
||||
extern const q15_t sqrtTable_Q15[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
#endif
|
||||
|
||||
#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_TABLES) */
|
||||
|
||||
#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
extern const float32_t exp_tab[8];
|
||||
extern const float32_t __logf_lut_f32[8];
|
||||
#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */
|
||||
|
||||
#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
extern const unsigned char hwLUT[256];
|
||||
#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ARM_COMMON_TABLES_H */
|
||||
|
||||
|
|
@ -0,0 +1,132 @@
|
|||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_common_tables_f16.h
|
||||
* Description: Extern declaration for common tables
|
||||
*
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_COMMON_TABLES_F16_H
|
||||
#define _ARM_COMMON_TABLES_F16_H
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
|
||||
|
||||
/* F16 */
|
||||
#if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED)
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_16)
|
||||
extern const float16_t twiddleCoefF16_16[32];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_32)
|
||||
extern const float16_t twiddleCoefF16_32[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_64)
|
||||
extern const float16_t twiddleCoefF16_64[128];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_128)
|
||||
extern const float16_t twiddleCoefF16_128[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_256)
|
||||
extern const float16_t twiddleCoefF16_256[512];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_512)
|
||||
extern const float16_t twiddleCoefF16_512[1024];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_1024)
|
||||
extern const float16_t twiddleCoefF16_1024[2048];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_2048)
|
||||
extern const float16_t twiddleCoefF16_2048[4096];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_4096)
|
||||
extern const float16_t twiddleCoefF16_4096[8192];
|
||||
#define twiddleCoefF16 twiddleCoefF16_4096
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_32)
|
||||
extern const float16_t twiddleCoefF16_rfft_32[32];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_64)
|
||||
extern const float16_t twiddleCoefF16_rfft_64[64];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_128)
|
||||
extern const float16_t twiddleCoefF16_rfft_128[128];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_256)
|
||||
extern const float16_t twiddleCoefF16_rfft_256[256];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_512)
|
||||
extern const float16_t twiddleCoefF16_rfft_512[512];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_1024)
|
||||
extern const float16_t twiddleCoefF16_rfft_1024[1024];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_2048)
|
||||
extern const float16_t twiddleCoefF16_rfft_2048[2048];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_4096)
|
||||
extern const float16_t twiddleCoefF16_rfft_4096[4096];
|
||||
#endif
|
||||
|
||||
#endif /* ARMAC5 */
|
||||
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
|
||||
|
||||
#if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
extern const float16_t exp_tab_f16[8];
|
||||
extern const float16_t __logf_lut_f16[8];
|
||||
#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ARM_COMMON_TABLES_F16_H */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_const_structs.h
|
||||
* Description: Constant structs that are initialized for user convenience.
|
||||
* For example, some can be given as arguments to the arm_cfft_f32() function.
|
||||
*
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_CONST_STRUCTS_H
|
||||
#define _ARM_CONST_STRUCTS_H
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_common_tables.h"
|
||||
#include "dsp/transform_functions.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len16;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len32;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len64;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len128;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len256;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len512;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len1024;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len2048;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len4096;
|
||||
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_const_structs_f16.h
|
||||
* Description: Constant structs that are initialized for user convenience.
|
||||
* For example, some can be given as arguments to the arm_cfft_f16() function.
|
||||
*
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_CONST_STRUCTS_F16_H
|
||||
#define _ARM_CONST_STRUCTS_F16_H
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_common_tables.h"
|
||||
#include "arm_common_tables_f16.h"
|
||||
#include "dsp/transform_functions_f16.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED)
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_16) && defined(ARM_TABLE_BITREVIDX_FLT_16))
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len16;
|
||||
#endif
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_32) && defined(ARM_TABLE_BITREVIDX_FLT_32))
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len32;
|
||||
#endif
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_64) && defined(ARM_TABLE_BITREVIDX_FLT_64))
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len64;
|
||||
#endif
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_128) && defined(ARM_TABLE_BITREVIDX_FLT_128))
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len128;
|
||||
#endif
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_256) && defined(ARM_TABLE_BITREVIDX_FLT_256))
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len256;
|
||||
#endif
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_512) && defined(ARM_TABLE_BITREVIDX_FLT_512))
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len512;
|
||||
#endif
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024))
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len1024;
|
||||
#endif
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048))
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len2048;
|
||||
#endif
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096))
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len4096;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,753 @@
|
|||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_helium_utils.h
|
||||
* Description: Utility functions for Helium development
|
||||
*
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_UTILS_HELIUM_H_
|
||||
#define _ARM_UTILS_HELIUM_H_
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
/***************************************
|
||||
|
||||
Definitions available for MVEF and MVEI
|
||||
|
||||
***************************************/
|
||||
#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#define INACTIVELANE 0 /* inactive lane content */
|
||||
|
||||
|
||||
#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) */
|
||||
|
||||
/***************************************
|
||||
|
||||
Definitions available for MVEF only
|
||||
|
||||
***************************************/
|
||||
#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
__STATIC_FORCEINLINE float32_t vecAddAcrossF32Mve(float32x4_t in)
|
||||
{
|
||||
float32_t acc;
|
||||
|
||||
acc = vgetq_lane(in, 0) + vgetq_lane(in, 1) +
|
||||
vgetq_lane(in, 2) + vgetq_lane(in, 3);
|
||||
|
||||
return acc;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/* newton initial guess */
|
||||
#define INVSQRT_MAGIC_F32 0x5f3759df
|
||||
#define INV_NEWTON_INIT_F32 0x7EF127EA
|
||||
|
||||
|
||||
#define INVSQRT_NEWTON_MVE_F32(invSqrt, xHalf, xStart)\
|
||||
{ \
|
||||
float32x4_t tmp; \
|
||||
\
|
||||
/* tmp = xhalf * x * x */ \
|
||||
tmp = vmulq(xStart, xStart); \
|
||||
tmp = vmulq(tmp, xHalf); \
|
||||
/* (1.5f - xhalf * x * x) */ \
|
||||
tmp = vsubq(vdupq_n_f32(1.5f), tmp); \
|
||||
/* x = x*(1.5f-xhalf*x*x); */ \
|
||||
invSqrt = vmulq(tmp, xStart); \
|
||||
}
|
||||
#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) */
|
||||
|
||||
|
||||
/***************************************
|
||||
|
||||
Definitions available for f16 datatype with HW acceleration only
|
||||
|
||||
***************************************/
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
#if defined (ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
__STATIC_FORCEINLINE float16_t vecAddAcrossF16Mve(float16x8_t in)
|
||||
{
|
||||
float16x8_t tmpVec;
|
||||
_Float16 acc;
|
||||
|
||||
tmpVec = (float16x8_t) vrev32q_s16((int16x8_t) in);
|
||||
in = vaddq_f16(tmpVec, in);
|
||||
tmpVec = (float16x8_t) vrev64q_s32((int32x4_t) in);
|
||||
in = vaddq_f16(tmpVec, in);
|
||||
acc = (_Float16)vgetq_lane_f16(in, 0) + (_Float16)vgetq_lane_f16(in, 4);
|
||||
|
||||
return acc;
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE float16x8_t __mve_cmplx_sum_intra_vec_f16(
|
||||
float16x8_t vecIn)
|
||||
{
|
||||
float16x8_t vecTmp, vecOut;
|
||||
uint32_t tmp;
|
||||
|
||||
vecTmp = (float16x8_t) vrev64q_s32((int32x4_t) vecIn);
|
||||
// TO TRACK : using canonical addition leads to unefficient code generation for f16
|
||||
// vecTmp = vecTmp + vecAccCpx0;
|
||||
/*
|
||||
* Compute
|
||||
* re0+re1 | im0+im1 | re0+re1 | im0+im1
|
||||
* re2+re3 | im2+im3 | re2+re3 | im2+im3
|
||||
*/
|
||||
vecTmp = vaddq_f16(vecTmp, vecIn);
|
||||
vecOut = vecTmp;
|
||||
/*
|
||||
* shift left, random tmp insertion in bottom
|
||||
*/
|
||||
vecOut = vreinterpretq_f16_s32(vshlcq_s32(vreinterpretq_s32_f16(vecOut) , &tmp, 32));
|
||||
/*
|
||||
* Compute:
|
||||
* DONTCARE | DONTCARE | re0+re1+re0+re1 |im0+im1+im0+im1
|
||||
* re0+re1+re2+re3 | im0+im1+im2+im3 | re2+re3+re2+re3 |im2+im3+im2+im3
|
||||
*/
|
||||
vecOut = vaddq_f16(vecOut, vecTmp);
|
||||
/*
|
||||
* Cmplx sum is in 4rd & 5th f16 elt
|
||||
* return full vector
|
||||
*/
|
||||
return vecOut;
|
||||
}
|
||||
|
||||
|
||||
#define mve_cmplx_sum_intra_r_i_f16(vec, Re, Im) \
|
||||
{ \
|
||||
float16x8_t vecOut = __mve_cmplx_sum_intra_vec_f16(vec); \
|
||||
Re = vgetq_lane(vecOut, 4); \
|
||||
Im = vgetq_lane(vecOut, 5); \
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE void mve_cmplx_sum_intra_vec_f16(
|
||||
float16x8_t vecIn,
|
||||
float16_t *pOut)
|
||||
{
|
||||
float16x8_t vecOut = __mve_cmplx_sum_intra_vec_f16(vecIn);
|
||||
/*
|
||||
* Cmplx sum is in 4rd & 5th f16 elt
|
||||
* use 32-bit extraction
|
||||
*/
|
||||
*(float32_t *) pOut = ((float32x4_t) vecOut)[2];
|
||||
}
|
||||
|
||||
|
||||
#define INVSQRT_MAGIC_F16 0x59ba /* ( 0x1ba = 0x3759df >> 13) */
|
||||
|
||||
/* canonical version of INVSQRT_NEWTON_MVE_F16 leads to bad performance */
|
||||
#define INVSQRT_NEWTON_MVE_F16(invSqrt, xHalf, xStart) \
|
||||
{ \
|
||||
float16x8_t tmp; \
|
||||
\
|
||||
/* tmp = xhalf * x * x */ \
|
||||
tmp = vmulq(xStart, xStart); \
|
||||
tmp = vmulq(tmp, xHalf); \
|
||||
/* (1.5f - xhalf * x * x) */ \
|
||||
tmp = vsubq(vdupq_n_f16((float16_t)1.5), tmp); \
|
||||
/* x = x*(1.5f-xhalf*x*x); */ \
|
||||
invSqrt = vmulq(tmp, xStart); \
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/***************************************
|
||||
|
||||
Definitions available for MVEI and MVEF only
|
||||
|
||||
***************************************/
|
||||
#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
/* Following functions are used to transpose matrix in f32 and q31 cases */
|
||||
__STATIC_INLINE arm_status arm_mat_trans_32bit_2x2_mve(
|
||||
uint32_t * pDataSrc,
|
||||
uint32_t * pDataDest)
|
||||
{
|
||||
static const uint32x4_t vecOffs = { 0, 2, 1, 3 };
|
||||
/*
|
||||
*
|
||||
* | 0 1 | => | 0 2 |
|
||||
* | 2 3 | | 1 3 |
|
||||
*
|
||||
*/
|
||||
uint32x4_t vecIn = vldrwq_u32((uint32_t const *)pDataSrc);
|
||||
vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs, vecIn);
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_32bit_3x3_mve(
|
||||
uint32_t * pDataSrc,
|
||||
uint32_t * pDataDest)
|
||||
{
|
||||
const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
|
||||
const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
|
||||
/*
|
||||
*
|
||||
* | 0 1 2 | | 0 3 6 | 4 x 32 flattened version | 0 3 6 1 |
|
||||
* | 3 4 5 | => | 1 4 7 | => | 4 7 2 5 |
|
||||
* | 6 7 8 | | 2 5 8 | (row major) | 8 . . . |
|
||||
*
|
||||
*/
|
||||
uint32x4_t vecIn1 = vldrwq_u32((uint32_t const *) pDataSrc);
|
||||
uint32x4_t vecIn2 = vldrwq_u32((uint32_t const *) &pDataSrc[4]);
|
||||
|
||||
vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs1, vecIn1);
|
||||
vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs2, vecIn2);
|
||||
|
||||
pDataDest[8] = pDataSrc[8];
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_32bit_4x4_mve(uint32_t * pDataSrc, uint32_t * pDataDest)
|
||||
{
|
||||
/*
|
||||
* 4x4 Matrix transposition
|
||||
* is 4 x de-interleave operation
|
||||
*
|
||||
* 0 1 2 3 0 4 8 12
|
||||
* 4 5 6 7 1 5 9 13
|
||||
* 8 9 10 11 2 6 10 14
|
||||
* 12 13 14 15 3 7 11 15
|
||||
*/
|
||||
|
||||
uint32x4x4_t vecIn;
|
||||
|
||||
vecIn = vld4q((uint32_t const *) pDataSrc);
|
||||
vstrwq(pDataDest, vecIn.val[0]);
|
||||
pDataDest += 4;
|
||||
vstrwq(pDataDest, vecIn.val[1]);
|
||||
pDataDest += 4;
|
||||
vstrwq(pDataDest, vecIn.val[2]);
|
||||
pDataDest += 4;
|
||||
vstrwq(pDataDest, vecIn.val[3]);
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve(
|
||||
uint16_t srcRows,
|
||||
uint16_t srcCols,
|
||||
uint32_t * pDataSrc,
|
||||
uint32_t * pDataDest)
|
||||
{
|
||||
uint32x4_t vecOffs;
|
||||
uint32_t i;
|
||||
uint32_t blkCnt;
|
||||
uint32_t const *pDataC;
|
||||
uint32_t *pDataDestR;
|
||||
uint32x4_t vecIn;
|
||||
|
||||
vecOffs = vidupq_u32((uint32_t)0, 1);
|
||||
vecOffs = vecOffs * srcCols;
|
||||
|
||||
i = srcCols;
|
||||
do
|
||||
{
|
||||
pDataC = (uint32_t const *) pDataSrc;
|
||||
pDataDestR = pDataDest;
|
||||
|
||||
blkCnt = srcRows >> 2;
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs);
|
||||
vstrwq(pDataDestR, vecIn);
|
||||
pDataDestR += 4;
|
||||
pDataC = pDataC + srcCols * 4;
|
||||
/*
|
||||
* Decrement the blockSize loop counter
|
||||
*/
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/*
|
||||
* tail
|
||||
*/
|
||||
blkCnt = srcRows & 3;
|
||||
if (blkCnt > 0U)
|
||||
{
|
||||
mve_pred16_t p0 = vctp32q(blkCnt);
|
||||
vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs);
|
||||
vstrwq_p(pDataDestR, vecIn, p0);
|
||||
}
|
||||
|
||||
pDataSrc += 1;
|
||||
pDataDest += srcRows;
|
||||
}
|
||||
while (--i);
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_cmplx_trans_32bit(
|
||||
uint16_t srcRows,
|
||||
uint16_t srcCols,
|
||||
uint32_t *pDataSrc,
|
||||
uint16_t dstRows,
|
||||
uint16_t dstCols,
|
||||
uint32_t *pDataDest)
|
||||
{
|
||||
uint32_t i;
|
||||
uint32_t const *pDataC;
|
||||
uint32_t *pDataRow;
|
||||
uint32_t *pDataDestR, *pDataDestRow;
|
||||
uint32x4_t vecOffsRef, vecOffsCur;
|
||||
uint32_t blkCnt;
|
||||
uint32x4_t vecIn;
|
||||
|
||||
#ifdef ARM_MATH_MATRIX_CHECK
|
||||
/*
|
||||
* Check for matrix mismatch condition
|
||||
*/
|
||||
if ((srcRows != dstCols) || (srcCols != dstRows))
|
||||
{
|
||||
/*
|
||||
* Set status as ARM_MATH_SIZE_MISMATCH
|
||||
*/
|
||||
return ARM_MATH_SIZE_MISMATCH;
|
||||
}
|
||||
#else
|
||||
(void)dstRows;
|
||||
(void)dstCols;
|
||||
#endif
|
||||
|
||||
/* 2x2, 3x3 and 4x4 specialization to be added */
|
||||
|
||||
vecOffsRef[0] = 0;
|
||||
vecOffsRef[1] = 1;
|
||||
vecOffsRef[2] = srcCols << 1;
|
||||
vecOffsRef[3] = (srcCols << 1) + 1;
|
||||
|
||||
pDataRow = pDataSrc;
|
||||
pDataDestRow = pDataDest;
|
||||
i = srcCols;
|
||||
do
|
||||
{
|
||||
pDataC = (uint32_t const *) pDataRow;
|
||||
pDataDestR = pDataDestRow;
|
||||
vecOffsCur = vecOffsRef;
|
||||
|
||||
blkCnt = (srcRows * CMPLX_DIM) >> 2;
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
vecIn = vldrwq_gather_shifted_offset(pDataC, vecOffsCur);
|
||||
vstrwq(pDataDestR, vecIn);
|
||||
pDataDestR += 4;
|
||||
vecOffsCur = vaddq(vecOffsCur, (srcCols << 2));
|
||||
/*
|
||||
* Decrement the blockSize loop counter
|
||||
*/
|
||||
blkCnt--;
|
||||
}
|
||||
/*
|
||||
* tail
|
||||
* (will be merged thru tail predication)
|
||||
*/
|
||||
blkCnt = (srcRows * CMPLX_DIM) & 3;
|
||||
if (blkCnt > 0U)
|
||||
{
|
||||
mve_pred16_t p0 = vctp32q(blkCnt);
|
||||
vecIn = vldrwq_gather_shifted_offset(pDataC, vecOffsCur);
|
||||
vstrwq_p(pDataDestR, vecIn, p0);
|
||||
}
|
||||
|
||||
pDataRow += CMPLX_DIM;
|
||||
pDataDestRow += (srcRows * CMPLX_DIM);
|
||||
}
|
||||
while (--i);
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_16bit_2x2(uint16_t * pDataSrc, uint16_t * pDataDest)
|
||||
{
|
||||
pDataDest[0] = pDataSrc[0];
|
||||
pDataDest[3] = pDataSrc[3];
|
||||
pDataDest[2] = pDataSrc[1];
|
||||
pDataDest[1] = pDataSrc[2];
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_16bit_3x3_mve(uint16_t * pDataSrc, uint16_t * pDataDest)
|
||||
{
|
||||
static const uint16_t stridesTr33[8] = { 0, 3, 6, 1, 4, 7, 2, 5 };
|
||||
uint16x8_t vecOffs1;
|
||||
uint16x8_t vecIn1;
|
||||
/*
|
||||
*
|
||||
* | 0 1 2 | | 0 3 6 | 8 x 16 flattened version | 0 3 6 1 4 7 2 5 |
|
||||
* | 3 4 5 | => | 1 4 7 | => | 8 . . . . . . . |
|
||||
* | 6 7 8 | | 2 5 8 | (row major)
|
||||
*
|
||||
*/
|
||||
vecOffs1 = vldrhq_u16((uint16_t const *) stridesTr33);
|
||||
vecIn1 = vldrhq_u16((uint16_t const *) pDataSrc);
|
||||
|
||||
vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs1, vecIn1);
|
||||
|
||||
pDataDest[8] = pDataSrc[8];
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_16bit_4x4_mve(uint16_t * pDataSrc, uint16_t * pDataDest)
|
||||
{
|
||||
static const uint16_t stridesTr44_1[8] = { 0, 4, 8, 12, 1, 5, 9, 13 };
|
||||
static const uint16_t stridesTr44_2[8] = { 2, 6, 10, 14, 3, 7, 11, 15 };
|
||||
uint16x8_t vecOffs1, vecOffs2;
|
||||
uint16x8_t vecIn1, vecIn2;
|
||||
uint16_t const * pDataSrcVec = (uint16_t const *) pDataSrc;
|
||||
|
||||
/*
|
||||
* 4x4 Matrix transposition
|
||||
*
|
||||
* | 0 1 2 3 | | 0 4 8 12 | 8 x 16 flattened version
|
||||
* | 4 5 6 7 | => | 1 5 9 13 | => [0 4 8 12 1 5 9 13]
|
||||
* | 8 9 10 11 | | 2 6 10 14 | [2 6 10 14 3 7 11 15]
|
||||
* | 12 13 14 15 | | 3 7 11 15 |
|
||||
*/
|
||||
|
||||
vecOffs1 = vldrhq_u16((uint16_t const *) stridesTr44_1);
|
||||
vecOffs2 = vldrhq_u16((uint16_t const *) stridesTr44_2);
|
||||
vecIn1 = vldrhq_u16(pDataSrcVec);
|
||||
pDataSrcVec += 8;
|
||||
vecIn2 = vldrhq_u16(pDataSrcVec);
|
||||
|
||||
vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs1, vecIn1);
|
||||
vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs2, vecIn2);
|
||||
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_16bit_generic(
|
||||
uint16_t srcRows,
|
||||
uint16_t srcCols,
|
||||
uint16_t * pDataSrc,
|
||||
uint16_t * pDataDest)
|
||||
{
|
||||
uint16x8_t vecOffs;
|
||||
uint32_t i;
|
||||
uint32_t blkCnt;
|
||||
uint16_t const *pDataC;
|
||||
uint16_t *pDataDestR;
|
||||
uint16x8_t vecIn;
|
||||
|
||||
vecOffs = vidupq_u16((uint32_t)0, 1);
|
||||
vecOffs = vecOffs * srcCols;
|
||||
|
||||
i = srcCols;
|
||||
while(i > 0U)
|
||||
{
|
||||
pDataC = (uint16_t const *) pDataSrc;
|
||||
pDataDestR = pDataDest;
|
||||
|
||||
blkCnt = srcRows >> 3;
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
vecIn = vldrhq_gather_shifted_offset_u16(pDataC, vecOffs);
|
||||
vstrhq_u16(pDataDestR, vecIn);
|
||||
pDataDestR += 8;
|
||||
pDataC = pDataC + srcCols * 8;
|
||||
/*
|
||||
* Decrement the blockSize loop counter
|
||||
*/
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/*
|
||||
* tail
|
||||
*/
|
||||
blkCnt = srcRows & 7;
|
||||
if (blkCnt > 0U)
|
||||
{
|
||||
mve_pred16_t p0 = vctp16q(blkCnt);
|
||||
vecIn = vldrhq_gather_shifted_offset_u16(pDataC, vecOffs);
|
||||
vstrhq_p_u16(pDataDestR, vecIn, p0);
|
||||
}
|
||||
pDataSrc += 1;
|
||||
pDataDest += srcRows;
|
||||
i--;
|
||||
}
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_cmplx_trans_16bit(
|
||||
uint16_t srcRows,
|
||||
uint16_t srcCols,
|
||||
uint16_t *pDataSrc,
|
||||
uint16_t dstRows,
|
||||
uint16_t dstCols,
|
||||
uint16_t *pDataDest)
|
||||
{
|
||||
static const uint16_t loadCmplxCol[8] = { 0, 0, 1, 1, 2, 2, 3, 3 };
|
||||
int i;
|
||||
uint16x8_t vecOffsRef, vecOffsCur;
|
||||
uint16_t const *pDataC;
|
||||
uint16_t *pDataRow;
|
||||
uint16_t *pDataDestR, *pDataDestRow;
|
||||
uint32_t blkCnt;
|
||||
uint16x8_t vecIn;
|
||||
|
||||
#ifdef ARM_MATH_MATRIX_CHECK
|
||||
/*
|
||||
* Check for matrix mismatch condition
|
||||
*/
|
||||
if ((srcRows != dstCols) || (srcCols != dstRows))
|
||||
{
|
||||
/*
|
||||
* Set status as ARM_MATH_SIZE_MISMATCH
|
||||
*/
|
||||
return ARM_MATH_SIZE_MISMATCH;
|
||||
}
|
||||
#else
|
||||
(void)dstRows;
|
||||
(void)dstCols;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* 2x2, 3x3 and 4x4 specialization to be added
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* build [0, 1, 2xcol, 2xcol+1, 4xcol, 4xcol+1, 6xcol, 6xcol+1]
|
||||
*/
|
||||
vecOffsRef = vldrhq_u16((uint16_t const *) loadCmplxCol);
|
||||
vecOffsRef = vmulq(vecOffsRef, (uint16_t) (srcCols * CMPLX_DIM))
|
||||
+ viwdupq_u16((uint32_t)0, (uint16_t) 2, 1);
|
||||
|
||||
pDataRow = pDataSrc;
|
||||
pDataDestRow = pDataDest;
|
||||
i = srcCols;
|
||||
do
|
||||
{
|
||||
pDataC = (uint16_t const *) pDataRow;
|
||||
pDataDestR = pDataDestRow;
|
||||
vecOffsCur = vecOffsRef;
|
||||
|
||||
blkCnt = (srcRows * CMPLX_DIM) >> 3;
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
vecIn = vldrhq_gather_shifted_offset(pDataC, vecOffsCur);
|
||||
vstrhq(pDataDestR, vecIn);
|
||||
pDataDestR+= 8; // VEC_LANES_U16
|
||||
vecOffsCur = vaddq(vecOffsCur, (srcCols << 3));
|
||||
/*
|
||||
* Decrement the blockSize loop counter
|
||||
*/
|
||||
blkCnt--;
|
||||
}
|
||||
/*
|
||||
* tail
|
||||
* (will be merged thru tail predication)
|
||||
*/
|
||||
blkCnt = (srcRows * CMPLX_DIM) & 0x7;
|
||||
if (blkCnt > 0U)
|
||||
{
|
||||
mve_pred16_t p0 = vctp16q(blkCnt);
|
||||
vecIn = vldrhq_gather_shifted_offset(pDataC, vecOffsCur);
|
||||
vstrhq_p(pDataDestR, vecIn, p0);
|
||||
}
|
||||
|
||||
pDataRow += CMPLX_DIM;
|
||||
pDataDestRow += (srcRows * CMPLX_DIM);
|
||||
}
|
||||
while (--i);
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
#endif /* MVEF and MVEI */
|
||||
|
||||
/***************************************
|
||||
|
||||
Definitions available for MVEI only
|
||||
|
||||
***************************************/
|
||||
#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#include "arm_common_tables.h"
|
||||
|
||||
#define MVE_ASRL_SAT16(acc, shift) ((sqrshrl_sat48(acc, -(32-shift)) >> 32) & 0xffffffff)
|
||||
#define MVE_ASRL_SAT32(acc, shift) ((sqrshrl(acc, -(32-shift)) >> 32) & 0xffffffff)
|
||||
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE)
|
||||
__STATIC_INLINE q31x4_t FAST_VSQRT_Q31(q31x4_t vecIn)
|
||||
{
|
||||
q63x2_t vecTmpLL;
|
||||
q31x4_t vecTmp0, vecTmp1;
|
||||
q31_t scale;
|
||||
q63_t tmp64;
|
||||
q31x4_t vecNrm, vecDst, vecIdx, vecSignBits;
|
||||
|
||||
|
||||
vecSignBits = vclsq(vecIn);
|
||||
vecSignBits = vbicq_n_s32(vecSignBits, 1);
|
||||
/*
|
||||
* in = in << no_of_sign_bits;
|
||||
*/
|
||||
vecNrm = vshlq(vecIn, vecSignBits);
|
||||
/*
|
||||
* index = in >> 24;
|
||||
*/
|
||||
vecIdx = vecNrm >> 24;
|
||||
vecIdx = vecIdx << 1;
|
||||
|
||||
vecTmp0 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, (uint32x4_t)vecIdx);
|
||||
|
||||
vecIdx = vecIdx + 1;
|
||||
|
||||
vecTmp1 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, (uint32x4_t)vecIdx);
|
||||
|
||||
vecTmp1 = vqrdmulhq(vecTmp1, vecNrm);
|
||||
vecTmp0 = vecTmp0 - vecTmp1;
|
||||
vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0);
|
||||
vecTmp1 = vqrdmulhq(vecNrm, vecTmp1);
|
||||
vecTmp1 = vdupq_n_s32(0x18000000) - vecTmp1;
|
||||
vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1);
|
||||
vecTmpLL = vmullbq_int(vecNrm, vecTmp0);
|
||||
|
||||
/*
|
||||
* scale elements 0, 2
|
||||
*/
|
||||
scale = 26 + (vecSignBits[0] >> 1);
|
||||
tmp64 = asrl(vecTmpLL[0], scale);
|
||||
vecDst[0] = (q31_t) tmp64;
|
||||
|
||||
scale = 26 + (vecSignBits[2] >> 1);
|
||||
tmp64 = asrl(vecTmpLL[1], scale);
|
||||
vecDst[2] = (q31_t) tmp64;
|
||||
|
||||
vecTmpLL = vmulltq_int(vecNrm, vecTmp0);
|
||||
|
||||
/*
|
||||
* scale elements 1, 3
|
||||
*/
|
||||
scale = 26 + (vecSignBits[1] >> 1);
|
||||
tmp64 = asrl(vecTmpLL[0], scale);
|
||||
vecDst[1] = (q31_t) tmp64;
|
||||
|
||||
scale = 26 + (vecSignBits[3] >> 1);
|
||||
tmp64 = asrl(vecTmpLL[1], scale);
|
||||
vecDst[3] = (q31_t) tmp64;
|
||||
/*
|
||||
* set negative values to 0
|
||||
*/
|
||||
vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s32(vecIn, 0));
|
||||
|
||||
return vecDst;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE)
|
||||
__STATIC_INLINE q15x8_t FAST_VSQRT_Q15(q15x8_t vecIn)
|
||||
{
|
||||
q31x4_t vecTmpLev, vecTmpLodd, vecSignL;
|
||||
q15x8_t vecTmp0, vecTmp1;
|
||||
q15x8_t vecNrm, vecDst, vecIdx, vecSignBits;
|
||||
|
||||
vecDst = vuninitializedq_s16();
|
||||
|
||||
vecSignBits = vclsq(vecIn);
|
||||
vecSignBits = vbicq_n_s16(vecSignBits, 1);
|
||||
/*
|
||||
* in = in << no_of_sign_bits;
|
||||
*/
|
||||
vecNrm = vshlq(vecIn, vecSignBits);
|
||||
|
||||
vecIdx = vecNrm >> 8;
|
||||
vecIdx = vecIdx << 1;
|
||||
|
||||
vecTmp0 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, (uint16x8_t)vecIdx);
|
||||
|
||||
vecIdx = vecIdx + 1;
|
||||
|
||||
vecTmp1 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, (uint16x8_t)vecIdx);
|
||||
|
||||
vecTmp1 = vqrdmulhq(vecTmp1, vecNrm);
|
||||
vecTmp0 = vecTmp0 - vecTmp1;
|
||||
vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0);
|
||||
vecTmp1 = vqrdmulhq(vecNrm, vecTmp1);
|
||||
vecTmp1 = vdupq_n_s16(0x1800) - vecTmp1;
|
||||
vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1);
|
||||
|
||||
vecSignBits = vecSignBits >> 1;
|
||||
|
||||
vecTmpLev = vmullbq_int(vecNrm, vecTmp0);
|
||||
vecTmpLodd = vmulltq_int(vecNrm, vecTmp0);
|
||||
|
||||
vecTmp0 = vecSignBits + 10;
|
||||
/*
|
||||
* negate sign to apply register based vshl
|
||||
*/
|
||||
vecTmp0 = -vecTmp0;
|
||||
|
||||
/*
|
||||
* shift even elements
|
||||
*/
|
||||
vecSignL = vmovlbq(vecTmp0);
|
||||
vecTmpLev = vshlq(vecTmpLev, vecSignL);
|
||||
/*
|
||||
* shift odd elements
|
||||
*/
|
||||
vecSignL = vmovltq(vecTmp0);
|
||||
vecTmpLodd = vshlq(vecTmpLodd, vecSignL);
|
||||
/*
|
||||
* merge and narrow odd and even parts
|
||||
*/
|
||||
vecDst = vmovnbq_s32(vecDst, vecTmpLev);
|
||||
vecDst = vmovntq_s32(vecDst, vecTmpLodd);
|
||||
/*
|
||||
* set negative values to 0
|
||||
*/
|
||||
vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s16(vecIn, 0));
|
||||
|
||||
return vecDst;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,236 @@
|
|||
/******************************************************************************
|
||||
* @file arm_math.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
\mainpage CMSIS DSP Software Library
|
||||
*
|
||||
* \section intro Introduction
|
||||
*
|
||||
* This user manual describes the CMSIS DSP software library,
|
||||
* a suite of common signal processing functions for use on Cortex-M and Cortex-A processor
|
||||
* based devices.
|
||||
*
|
||||
* The library is divided into a number of functions each covering a specific category:
|
||||
* - Basic math functions
|
||||
* - Fast math functions
|
||||
* - Complex math functions
|
||||
* - Filtering functions
|
||||
* - Matrix functions
|
||||
* - Transform functions
|
||||
* - Motor control functions
|
||||
* - Statistical functions
|
||||
* - Support functions
|
||||
* - Interpolation functions
|
||||
* - Support Vector Machine functions (SVM)
|
||||
* - Bayes classifier functions
|
||||
* - Distance functions
|
||||
* - Quaternion functions
|
||||
*
|
||||
* The library has generally separate functions for operating on 8-bit integers, 16-bit integers,
|
||||
* 32-bit integer and 32-bit floating-point values.
|
||||
*
|
||||
* The library is providing vectorized versions of most algorthms for Helium
|
||||
* and of most f32 algorithms for Neon.
|
||||
*
|
||||
* When using a vectorized version, provide a little bit of padding after the end of
|
||||
* a buffer (3 words) because the vectorized code may read a little bit after the end
|
||||
* of a buffer. You don't have to modify your buffers but just ensure that the
|
||||
* end of buffer + padding is not outside of a memory region.
|
||||
*
|
||||
* \section using Using the Library
|
||||
*
|
||||
* The library is released in source form. It is strongly advised to compile the library using -Ofast to
|
||||
* have the best performances.
|
||||
*
|
||||
* The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
|
||||
* Simply include this file. If you don't want to include everything, you can also rely
|
||||
* on headers in Include/dsp folder and use only what you need.
|
||||
*
|
||||
* \section example Examples
|
||||
*
|
||||
* The library ships with a number of examples which demonstrate how to use the library functions.
|
||||
*
|
||||
* \section toolchain Toolchain Support
|
||||
*
|
||||
* The library is now tested on Fast Models building with cmake.
|
||||
* Core M0, M4, M7, M33, M55, A32 are tested.
|
||||
*
|
||||
*
|
||||
* \section preprocessor Preprocessor Macros
|
||||
*
|
||||
* Each library project have different preprocessor macros.
|
||||
*
|
||||
* - ARM_MATH_BIG_ENDIAN:
|
||||
*
|
||||
* Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
|
||||
*
|
||||
* - ARM_MATH_MATRIX_CHECK:
|
||||
*
|
||||
* Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
|
||||
*
|
||||
* - ARM_MATH_ROUNDING:
|
||||
*
|
||||
* Define macro ARM_MATH_ROUNDING for rounding on support functions
|
||||
*
|
||||
* - ARM_MATH_LOOPUNROLL:
|
||||
*
|
||||
* Define macro ARM_MATH_LOOPUNROLL to enable manual loop unrolling in DSP functions
|
||||
*
|
||||
* - ARM_MATH_NEON:
|
||||
*
|
||||
* Define macro ARM_MATH_NEON to enable Neon versions of the DSP functions.
|
||||
* It is not enabled by default when Neon is available because performances are
|
||||
* dependent on the compiler and target architecture.
|
||||
*
|
||||
* - ARM_MATH_NEON_EXPERIMENTAL:
|
||||
*
|
||||
* Define macro ARM_MATH_NEON_EXPERIMENTAL to enable experimental Neon versions of
|
||||
* of some DSP functions. Experimental Neon versions currently do not have better
|
||||
* performances than the scalar versions.
|
||||
*
|
||||
* - ARM_MATH_HELIUM:
|
||||
*
|
||||
* It implies the flags ARM_MATH_MVEF and ARM_MATH_MVEI and ARM_MATH_MVE_FLOAT16.
|
||||
*
|
||||
* - ARM_MATH_HELIUM_EXPERIMENTAL:
|
||||
*
|
||||
* Only taken into account when ARM_MATH_MVEF, ARM_MATH_MVEI or ARM_MATH_MVE_FLOAT16 are defined.
|
||||
* Enable some vector versions which may have worse performance than scalar
|
||||
* depending on the core / compiler configuration.
|
||||
*
|
||||
* - ARM_MATH_MVEF:
|
||||
*
|
||||
* Select Helium versions of the f32 algorithms.
|
||||
* It implies ARM_MATH_FLOAT16 and ARM_MATH_MVEI.
|
||||
*
|
||||
* - ARM_MATH_MVEI:
|
||||
*
|
||||
* Select Helium versions of the int and fixed point algorithms.
|
||||
*
|
||||
* - ARM_MATH_MVE_FLOAT16:
|
||||
*
|
||||
* MVE Float16 implementations of some algorithms (Requires MVE extension).
|
||||
*
|
||||
* - DISABLEFLOAT16:
|
||||
*
|
||||
* Disable float16 algorithms when __fp16 is not supported for a
|
||||
* specific compiler / core configuration.
|
||||
* This is only valid for scalar. When vector architecture is
|
||||
* supporting f16 then it can't be disabled.
|
||||
*
|
||||
* - ARM_MATH_AUTOVECTORIZE:
|
||||
*
|
||||
* With Helium or Neon, disable the use of vectorized code with C intrinsics
|
||||
* and use pure C instead. The vectorization is then done by the compiler.
|
||||
*
|
||||
* <hr>
|
||||
* \section pack CMSIS-DSP in ARM::CMSIS Pack
|
||||
*
|
||||
* The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
|
||||
* |File/Folder |Content |
|
||||
* |---------------------------------|------------------------------------------------------------------------|
|
||||
* |\b CMSIS\\Documentation\\DSP | This documentation |
|
||||
* |\b CMSIS\\DSP\\Examples | Example projects demonstrating the usage of the library functions |
|
||||
* |\b CMSIS\\DSP\\Include | DSP_Lib include files for using and building the lib
|
||||
* |\b CMSIS\\DSP\\PrivateInclude | DSP_Lib private include files for building the lib |
|
||||
* |\b CMSIS\\DSP\\Lib | DSP_Lib binaries |
|
||||
* |\b CMSIS\\DSP\\Source | DSP_Lib source files |
|
||||
*
|
||||
* <hr>
|
||||
* \section rev Revision History of CMSIS-DSP
|
||||
* Please refer to \ref ChangeLog_pg.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup groupExamples Examples
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifndef _ARM_MATH_H
|
||||
#define _ARM_MATH_H
|
||||
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#include "dsp/basic_math_functions.h"
|
||||
#include "dsp/interpolation_functions.h"
|
||||
#include "dsp/bayes_functions.h"
|
||||
#include "dsp/matrix_functions.h"
|
||||
#include "dsp/complex_math_functions.h"
|
||||
#include "dsp/statistics_functions.h"
|
||||
#include "dsp/controller_functions.h"
|
||||
#include "dsp/support_functions.h"
|
||||
#include "dsp/distance_functions.h"
|
||||
#include "dsp/svm_functions.h"
|
||||
#include "dsp/fast_math_functions.h"
|
||||
#include "dsp/transform_functions.h"
|
||||
#include "dsp/filtering_functions.h"
|
||||
#include "dsp/quaternion_math_functions.h"
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
//#define TABLE_SPACING_Q31 0x400000
|
||||
//#define TABLE_SPACING_Q15 0x80
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* _ARM_MATH_H */
|
||||
|
||||
/**
|
||||
*
|
||||
* End of file.
|
||||
*/
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/******************************************************************************
|
||||
* @file arm_math_f16.h
|
||||
* @brief Public header file for f16 function of the CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_MATH_F16_H
|
||||
#define _ARM_MATH_F16_H
|
||||
|
||||
#include "arm_math.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
#include "dsp/basic_math_functions_f16.h"
|
||||
#include "dsp/interpolation_functions_f16.h"
|
||||
#include "dsp/bayes_functions_f16.h"
|
||||
#include "dsp/matrix_functions_f16.h"
|
||||
#include "dsp/complex_math_functions_f16.h"
|
||||
#include "dsp/statistics_functions_f16.h"
|
||||
#include "dsp/controller_functions_f16.h"
|
||||
#include "dsp/support_functions_f16.h"
|
||||
#include "dsp/distance_functions_f16.h"
|
||||
#include "dsp/svm_functions_f16.h"
|
||||
#include "dsp/fast_math_functions_f16.h"
|
||||
#include "dsp/transform_functions_f16.h"
|
||||
#include "dsp/filtering_functions_f16.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ARM_MATH_F16_H */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,206 @@
|
|||
/******************************************************************************
|
||||
* @file arm_math_memory.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_MATH_MEMORY_H_
|
||||
|
||||
#define _ARM_MATH_MEMORY_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
@brief definition to read/write two 16 bit values.
|
||||
@deprecated
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#define __SIMD32_TYPE int32_t __packed
|
||||
#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
|
||||
#define __SIMD32_TYPE int32_t
|
||||
#elif defined ( __GNUC__ )
|
||||
#define __SIMD32_TYPE int32_t
|
||||
#elif defined ( __ICCARM__ )
|
||||
#define __SIMD32_TYPE int32_t __packed
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#define __SIMD32_TYPE int32_t
|
||||
#elif defined ( __CSMC__ )
|
||||
#define __SIMD32_TYPE int32_t
|
||||
#elif defined ( __TASKING__ )
|
||||
#define __SIMD32_TYPE __un(aligned) int32_t
|
||||
#elif defined(_MSC_VER )
|
||||
#define __SIMD32_TYPE int32_t
|
||||
#else
|
||||
#error Unknown compiler
|
||||
#endif
|
||||
|
||||
#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
|
||||
#define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr))
|
||||
#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr))
|
||||
#define __SIMD64(addr) (*( int64_t **) & (addr))
|
||||
|
||||
|
||||
/* SIMD replacement */
|
||||
|
||||
|
||||
/**
|
||||
@brief Read 2 Q15 from Q15 pointer.
|
||||
@param[in] pQ15 points to input value
|
||||
@return Q31 value
|
||||
*/
|
||||
__STATIC_FORCEINLINE q31_t read_q15x2 (
|
||||
q15_t const * pQ15)
|
||||
{
|
||||
q31_t val;
|
||||
|
||||
#ifdef __ARM_FEATURE_UNALIGNED
|
||||
memcpy (&val, pQ15, 4);
|
||||
#else
|
||||
val = (pQ15[1] << 16) | (pQ15[0] & 0x0FFFF) ;
|
||||
#endif
|
||||
|
||||
return (val);
|
||||
}
|
||||
|
||||
/**
|
||||
@brief Read 2 Q15 from Q15 pointer and increment pointer afterwards.
|
||||
@param[in] pQ15 points to input value
|
||||
@return Q31 value
|
||||
*/
|
||||
#define read_q15x2_ia(pQ15) read_q15x2((*(pQ15) += 2) - 2)
|
||||
|
||||
/**
|
||||
@brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards.
|
||||
@param[in] pQ15 points to input value
|
||||
@return Q31 value
|
||||
*/
|
||||
#define read_q15x2_da(pQ15) read_q15x2((*(pQ15) -= 2) + 2)
|
||||
|
||||
/**
|
||||
@brief Write 2 Q15 to Q15 pointer and increment pointer afterwards.
|
||||
@param[in] pQ15 points to input value
|
||||
@param[in] value Q31 value
|
||||
@return none
|
||||
*/
|
||||
__STATIC_FORCEINLINE void write_q15x2_ia (
|
||||
q15_t ** pQ15,
|
||||
q31_t value)
|
||||
{
|
||||
q31_t val = value;
|
||||
#ifdef __ARM_FEATURE_UNALIGNED
|
||||
memcpy (*pQ15, &val, 4);
|
||||
#else
|
||||
(*pQ15)[0] = (q15_t)(val & 0x0FFFF);
|
||||
(*pQ15)[1] = (q15_t)((val >> 16) & 0x0FFFF);
|
||||
#endif
|
||||
|
||||
*pQ15 += 2;
|
||||
}
|
||||
|
||||
/**
|
||||
@brief Write 2 Q15 to Q15 pointer.
|
||||
@param[in] pQ15 points to input value
|
||||
@param[in] value Q31 value
|
||||
@return none
|
||||
*/
|
||||
__STATIC_FORCEINLINE void write_q15x2 (
|
||||
q15_t * pQ15,
|
||||
q31_t value)
|
||||
{
|
||||
q31_t val = value;
|
||||
|
||||
#ifdef __ARM_FEATURE_UNALIGNED
|
||||
memcpy (pQ15, &val, 4);
|
||||
#else
|
||||
pQ15[0] = (q15_t)(val & 0x0FFFF);
|
||||
pQ15[1] = (q15_t)(val >> 16);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
@brief Read 4 Q7 from Q7 pointer
|
||||
@param[in] pQ7 points to input value
|
||||
@return Q31 value
|
||||
*/
|
||||
__STATIC_FORCEINLINE q31_t read_q7x4 (
|
||||
q7_t const * pQ7)
|
||||
{
|
||||
q31_t val;
|
||||
|
||||
#ifdef __ARM_FEATURE_UNALIGNED
|
||||
memcpy (&val, pQ7, 4);
|
||||
#else
|
||||
val =((pQ7[3] & 0x0FF) << 24) | ((pQ7[2] & 0x0FF) << 16) | ((pQ7[1] & 0x0FF) << 8) | (pQ7[0] & 0x0FF);
|
||||
#endif
|
||||
return (val);
|
||||
}
|
||||
|
||||
/**
|
||||
@brief Read 4 Q7 from Q7 pointer and increment pointer afterwards.
|
||||
@param[in] pQ7 points to input value
|
||||
@return Q31 value
|
||||
*/
|
||||
#define read_q7x4_ia(pQ7) read_q7x4((*(pQ7) += 4) - 4)
|
||||
|
||||
/**
|
||||
@brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards.
|
||||
@param[in] pQ7 points to input value
|
||||
@return Q31 value
|
||||
*/
|
||||
#define read_q7x4_da(pQ7) read_q7x4((*(pQ7) -= 4) + 4)
|
||||
|
||||
/**
|
||||
@brief Write 4 Q7 to Q7 pointer and increment pointer afterwards.
|
||||
@param[in] pQ7 points to input value
|
||||
@param[in] value Q31 value
|
||||
@return none
|
||||
*/
|
||||
__STATIC_FORCEINLINE void write_q7x4_ia (
|
||||
q7_t ** pQ7,
|
||||
q31_t value)
|
||||
{
|
||||
q31_t val = value;
|
||||
#ifdef __ARM_FEATURE_UNALIGNED
|
||||
memcpy (*pQ7, &val, 4);
|
||||
#else
|
||||
(*pQ7)[0] = (q7_t)(val & 0x0FF);
|
||||
(*pQ7)[1] = (q7_t)((val >> 8) & 0x0FF);
|
||||
(*pQ7)[2] = (q7_t)((val >> 16) & 0x0FF);
|
||||
(*pQ7)[3] = (q7_t)((val >> 24) & 0x0FF);
|
||||
|
||||
#endif
|
||||
*pQ7 += 4;
|
||||
}
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*ifndef _ARM_MATH_MEMORY_H_ */
|
||||
|
|
@ -0,0 +1,616 @@
|
|||
/******************************************************************************
|
||||
* @file arm_math_types.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_MATH_TYPES_H_
|
||||
|
||||
#define _ARM_MATH_TYPES_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Compiler specific diagnostic adjustment */
|
||||
#if defined ( __CC_ARM )
|
||||
|
||||
#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
|
||||
|
||||
#elif defined ( __APPLE_CC__ )
|
||||
#pragma GCC diagnostic ignored "-Wold-style-cast"
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wsign-conversion"
|
||||
#pragma GCC diagnostic ignored "-Wconversion"
|
||||
#pragma GCC diagnostic ignored "-Wunused-parameter"
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
|
||||
#elif defined ( _MSC_VER )
|
||||
|
||||
#else
|
||||
#error Unknown compiler
|
||||
#endif
|
||||
|
||||
|
||||
/* Included for instrinsics definitions */
|
||||
#if defined (_MSC_VER )
|
||||
#include <stdint.h>
|
||||
#define __STATIC_FORCEINLINE static __forceinline
|
||||
#define __STATIC_INLINE static __inline
|
||||
#define __ALIGNED(x) __declspec(align(x))
|
||||
#elif defined ( __APPLE_CC__ )
|
||||
#include <stdint.h>
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#define __STATIC_FORCEINLINE static inline __attribute__((always_inline))
|
||||
#define __STATIC_INLINE static inline
|
||||
#elif defined (__GNUC_PYTHON__)
|
||||
#include <stdint.h>
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#define __STATIC_FORCEINLINE static inline __attribute__((always_inline))
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#else
|
||||
#include "cmsis_compiler.h"
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
#include <float.h>
|
||||
#include <limits.h>
|
||||
|
||||
/* evaluate ARM DSP feature */
|
||||
#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
|
||||
#define ARM_MATH_DSP 1
|
||||
#endif
|
||||
|
||||
#if defined(ARM_MATH_NEON)
|
||||
#if defined(_MSC_VER) && defined(_M_ARM64EC)
|
||||
#include <arm64_neon.h>
|
||||
#else
|
||||
#include <arm_neon.h>
|
||||
#endif
|
||||
#if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
|
||||
#if !defined(ARM_MATH_NEON_FLOAT16)
|
||||
#define ARM_MATH_NEON_FLOAT16
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
|
||||
#if defined(__ARM_FEATURE_MVE)
|
||||
#if __ARM_FEATURE_MVE
|
||||
#if !defined(ARM_MATH_MVEI)
|
||||
#define ARM_MATH_MVEI
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (__ARM_FEATURE_MVE & 2)
|
||||
#if !defined(ARM_MATH_MVEF)
|
||||
#define ARM_MATH_MVEF
|
||||
#endif
|
||||
#if !defined(ARM_MATH_MVE_FLOAT16)
|
||||
#define ARM_MATH_MVE_FLOAT16
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /*defined(__ARM_FEATURE_MVE)*/
|
||||
#endif /*!defined(ARM_MATH_AUTOVECTORIZE)*/
|
||||
|
||||
|
||||
#if defined (ARM_MATH_HELIUM)
|
||||
#if !defined(ARM_MATH_MVEF)
|
||||
#define ARM_MATH_MVEF
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_MATH_MVEI)
|
||||
#define ARM_MATH_MVEI
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_MATH_MVE_FLOAT16)
|
||||
#define ARM_MATH_MVE_FLOAT16
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
/* Enter low optimization region - place directly above function definition */
|
||||
#if defined( __ARM_ARCH_7EM__ )
|
||||
#define LOW_OPTIMIZATION_ENTER \
|
||||
_Pragma ("push") \
|
||||
_Pragma ("O1")
|
||||
#else
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#endif
|
||||
|
||||
/* Exit low optimization region - place directly after end of function definition */
|
||||
#if defined ( __ARM_ARCH_7EM__ )
|
||||
#define LOW_OPTIMIZATION_EXIT \
|
||||
_Pragma ("pop")
|
||||
#else
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
#endif
|
||||
|
||||
/* Enter low optimization region - place directly above function definition */
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
|
||||
/* Exit low optimization region - place directly after end of function definition */
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
|
||||
#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
|
||||
#elif defined ( __APPLE_CC__ )
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#define LOW_OPTIMIZATION_ENTER \
|
||||
__attribute__(( optimize("-O1") ))
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* Enter low optimization region - place directly above function definition */
|
||||
#if defined ( __ARM_ARCH_7EM__ )
|
||||
#define LOW_OPTIMIZATION_ENTER \
|
||||
_Pragma ("optimize=low")
|
||||
#else
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#endif
|
||||
|
||||
/* Exit low optimization region - place directly after end of function definition */
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
|
||||
/* Enter low optimization region - place directly above function definition */
|
||||
#if defined ( __ARM_ARCH_7EM__ )
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
|
||||
_Pragma ("optimize=low")
|
||||
#else
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
#endif
|
||||
|
||||
/* Exit low optimization region - place directly after end of function definition */
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
|
||||
#elif defined ( _MSC_VER ) || defined(__GNUC_PYTHON__)
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* Compiler specific diagnostic adjustment */
|
||||
#if defined ( __CC_ARM )
|
||||
|
||||
#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
|
||||
|
||||
#elif defined ( __APPLE_CC__ )
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic pop
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
|
||||
#elif defined ( _MSC_VER )
|
||||
|
||||
#else
|
||||
#error Unknown compiler
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(__ARM_FEATURE_MVE) && __ARM_FEATURE_MVE
|
||||
#include <arm_mve.h>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional data type in 1.7 format.
|
||||
*/
|
||||
typedef int8_t q7_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional data type in 1.15 format.
|
||||
*/
|
||||
typedef int16_t q15_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional data type in 1.31 format.
|
||||
*/
|
||||
typedef int32_t q31_t;
|
||||
|
||||
/**
|
||||
* @brief 64-bit fractional data type in 1.63 format.
|
||||
*/
|
||||
typedef int64_t q63_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit floating-point type definition.
|
||||
*/
|
||||
#if !defined(__ICCARM__) || !(__ARM_FEATURE_MVE & 2)
|
||||
typedef float float32_t;
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief 64-bit floating-point type definition.
|
||||
*/
|
||||
typedef double float64_t;
|
||||
|
||||
/**
|
||||
* @brief vector types
|
||||
*/
|
||||
#if defined(ARM_MATH_NEON) || (defined (ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE))
|
||||
/**
|
||||
* @brief 64-bit fractional 128-bit vector data type in 1.63 format
|
||||
*/
|
||||
typedef int64x2_t q63x2_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional 128-bit vector data type in 1.31 format.
|
||||
*/
|
||||
typedef int32x4_t q31x4_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional 128-bit vector data type with 16-bit alignment in 1.15 format.
|
||||
*/
|
||||
typedef __ALIGNED(2) int16x8_t q15x8_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional 128-bit vector data type with 8-bit alignment in 1.7 format.
|
||||
*/
|
||||
typedef __ALIGNED(1) int8x16_t q7x16_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional 128-bit vector pair data type in 1.31 format.
|
||||
*/
|
||||
typedef int32x4x2_t q31x4x2_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional 128-bit vector quadruplet data type in 1.31 format.
|
||||
*/
|
||||
typedef int32x4x4_t q31x4x4_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional 128-bit vector pair data type in 1.15 format.
|
||||
*/
|
||||
typedef int16x8x2_t q15x8x2_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional 128-bit vector quadruplet data type in 1.15 format.
|
||||
*/
|
||||
typedef int16x8x4_t q15x8x4_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional 128-bit vector pair data type in 1.7 format.
|
||||
*/
|
||||
typedef int8x16x2_t q7x16x2_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional 128-bit vector quadruplet data type in 1.7 format.
|
||||
*/
|
||||
typedef int8x16x4_t q7x16x4_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional data type in 9.23 format.
|
||||
*/
|
||||
typedef int32_t q23_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional 128-bit vector data type in 9.23 format.
|
||||
*/
|
||||
typedef int32x4_t q23x4_t;
|
||||
|
||||
/**
|
||||
* @brief 64-bit status 128-bit vector data type.
|
||||
*/
|
||||
typedef int64x2_t status64x2_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit status 128-bit vector data type.
|
||||
*/
|
||||
typedef int32x4_t status32x4_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit status 128-bit vector data type.
|
||||
*/
|
||||
typedef int16x8_t status16x8_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit status 128-bit vector data type.
|
||||
*/
|
||||
typedef int8x16_t status8x16_t;
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(ARM_MATH_NEON) || (defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)) /* floating point vector*/
|
||||
/**
|
||||
* @brief 32-bit floating-point 128-bit vector type
|
||||
*/
|
||||
typedef float32x4_t f32x4_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit floating-point 128-bit vector pair data type
|
||||
*/
|
||||
typedef float32x4x2_t f32x4x2_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit floating-point 128-bit vector quadruplet data type
|
||||
*/
|
||||
typedef float32x4x4_t f32x4x4_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit ubiquitous 128-bit vector data type
|
||||
*/
|
||||
typedef union _any32x4_t
|
||||
{
|
||||
float32x4_t f;
|
||||
int32x4_t i;
|
||||
} any32x4_t;
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(ARM_MATH_NEON)
|
||||
/**
|
||||
* @brief 32-bit fractional 64-bit vector data type in 1.31 format.
|
||||
*/
|
||||
typedef int32x2_t q31x2_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional 64-bit vector data type in 1.15 format.
|
||||
*/
|
||||
typedef __ALIGNED(2) int16x4_t q15x4_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional 64-bit vector data type in 1.7 format.
|
||||
*/
|
||||
typedef __ALIGNED(1) int8x8_t q7x8_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit float 64-bit vector data type.
|
||||
*/
|
||||
typedef float32x2_t f32x2_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit floating-point 128-bit vector triplet data type
|
||||
*/
|
||||
typedef float32x4x3_t f32x4x3_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional 128-bit vector triplet data type in 1.31 format
|
||||
*/
|
||||
typedef int32x4x3_t q31x4x3_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional 128-bit vector triplet data type in 1.15 format
|
||||
*/
|
||||
typedef int16x8x3_t q15x8x3_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional 128-bit vector triplet data type in 1.7 format
|
||||
*/
|
||||
typedef int8x16x3_t q7x16x3_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit floating-point 64-bit vector pair data type
|
||||
*/
|
||||
typedef float32x2x2_t f32x2x2_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit floating-point 64-bit vector triplet data type
|
||||
*/
|
||||
typedef float32x2x3_t f32x2x3_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit floating-point 64-bit vector quadruplet data type
|
||||
*/
|
||||
typedef float32x2x4_t f32x2x4_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional 64-bit vector pair data type in 1.31 format
|
||||
*/
|
||||
typedef int32x2x2_t q31x2x2_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional 64-bit vector triplet data type in 1.31 format
|
||||
*/
|
||||
typedef int32x2x3_t q31x2x3_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional 64-bit vector quadruplet data type in 1.31 format
|
||||
*/
|
||||
typedef int32x4x3_t q31x2x4_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional 64-bit vector pair data type in 1.15 format
|
||||
*/
|
||||
typedef int16x4x2_t q15x4x2_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional 64-bit vector triplet data type in 1.15 format
|
||||
*/
|
||||
typedef int16x4x2_t q15x4x3_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional 64-bit vector quadruplet data type in 1.15 format
|
||||
*/
|
||||
typedef int16x4x3_t q15x4x4_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional 64-bit vector pair data type in 1.7 format
|
||||
*/
|
||||
typedef int8x8x2_t q7x8x2_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional 64-bit vector triplet data type in 1.7 format
|
||||
*/
|
||||
typedef int8x8x3_t q7x8x3_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional 64-bit vector quadruplet data type in 1.7 format
|
||||
*/
|
||||
typedef int8x8x4_t q7x8x4_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit ubiquitous 64-bit vector data type
|
||||
*/
|
||||
typedef union _any32x2_t
|
||||
{
|
||||
float32x2_t f;
|
||||
int32x2_t i;
|
||||
} any32x2_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief 32-bit status 64-bit vector data type.
|
||||
*/
|
||||
typedef int32x4_t status32x2_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit status 64-bit vector data type.
|
||||
*/
|
||||
typedef int16x8_t status16x4_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit status 64-bit vector data type.
|
||||
*/
|
||||
typedef int8x16_t status8x8_t;
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define F64_MAX ((float64_t)DBL_MAX)
|
||||
#define F32_MAX ((float32_t)FLT_MAX)
|
||||
|
||||
|
||||
|
||||
#define F64_MIN (-DBL_MAX)
|
||||
#define F32_MIN (-FLT_MAX)
|
||||
|
||||
|
||||
|
||||
#define F64_ABSMAX ((float64_t)DBL_MAX)
|
||||
#define F32_ABSMAX ((float32_t)FLT_MAX)
|
||||
|
||||
|
||||
|
||||
#define F64_ABSMIN ((float64_t)0.0)
|
||||
#define F32_ABSMIN ((float32_t)0.0)
|
||||
|
||||
|
||||
#define Q31_MAX ((q31_t)(0x7FFFFFFFL))
|
||||
#define Q15_MAX ((q15_t)(0x7FFF))
|
||||
#define Q7_MAX ((q7_t)(0x7F))
|
||||
#define Q31_MIN ((q31_t)(0x80000000L))
|
||||
#define Q15_MIN ((q15_t)(0x8000))
|
||||
#define Q7_MIN ((q7_t)(0x80))
|
||||
|
||||
#define Q31_ABSMAX ((q31_t)(0x7FFFFFFFL))
|
||||
#define Q15_ABSMAX ((q15_t)(0x7FFF))
|
||||
#define Q7_ABSMAX ((q7_t)(0x7F))
|
||||
#define Q31_ABSMIN ((q31_t)0)
|
||||
#define Q15_ABSMIN ((q15_t)0)
|
||||
#define Q7_ABSMIN ((q7_t)0)
|
||||
|
||||
/* Dimension C vector space */
|
||||
#define CMPLX_DIM 2
|
||||
|
||||
/**
|
||||
* @brief Error status returned by some functions in the library.
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
ARM_MATH_SUCCESS = 0, /**< No error */
|
||||
ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
|
||||
ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
|
||||
ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */
|
||||
ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
|
||||
ARM_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */
|
||||
ARM_MATH_TEST_FAILURE = -6, /**< Test Failed */
|
||||
ARM_MATH_DECOMPOSITION_FAILURE = -7 /**< Decomposition Failed */
|
||||
} arm_status;
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*ifndef _ARM_MATH_TYPES_H_ */
|
||||
|
|
@ -0,0 +1,163 @@
|
|||
/******************************************************************************
|
||||
* @file arm_math_types_f16.h
|
||||
* @brief Public header file for f16 function of the CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_MATH_TYPES_F16_H
|
||||
#define _ARM_MATH_TYPES_F16_H
|
||||
|
||||
#include "arm_math_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if !defined( __CC_ARM )
|
||||
|
||||
/**
|
||||
* @brief 16-bit floating-point type definition.
|
||||
* This is already defined in arm_mve.h
|
||||
*
|
||||
* This is not fully supported on ARM AC5.
|
||||
*/
|
||||
|
||||
/*
|
||||
|
||||
Check if the type __fp16 is available.
|
||||
If it is not available, f16 version of the kernels
|
||||
won't be built.
|
||||
|
||||
*/
|
||||
#if !(__ARM_FEATURE_MVE & 2)
|
||||
#if !defined(DISABLEFLOAT16)
|
||||
#if defined(__ARM_FP16_FORMAT_IEEE) || defined(__ARM_FP16_FORMAT_ALTERNATIVE)
|
||||
typedef __fp16 float16_t;
|
||||
#define ARM_FLOAT16_SUPPORTED
|
||||
#endif
|
||||
#endif
|
||||
#else
|
||||
/* When Vector float16, this flag is always defined and can't be disabled */
|
||||
#define ARM_FLOAT16_SUPPORTED
|
||||
#endif
|
||||
|
||||
#if defined(ARM_MATH_NEON) || (defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)) /* floating point vector*/
|
||||
|
||||
#if defined(ARM_MATH_MVE_FLOAT16) || defined(ARM_MATH_NEON_FLOAT16)
|
||||
|
||||
/**
|
||||
* @brief 16-bit floating-point 128-bit vector data type
|
||||
*/
|
||||
typedef __ALIGNED(2) float16x8_t f16x8_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit floating-point 128-bit vector pair data type
|
||||
*/
|
||||
typedef float16x8x2_t f16x8x2_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit floating-point 128-bit vector quadruplet data type
|
||||
*/
|
||||
typedef float16x8x4_t f16x8x4_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit ubiquitous 128-bit vector data type
|
||||
*/
|
||||
typedef union _any16x8_t
|
||||
{
|
||||
float16x8_t f;
|
||||
int16x8_t i;
|
||||
} any16x8_t;
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(ARM_MATH_NEON)
|
||||
|
||||
|
||||
#if defined(ARM_MATH_NEON_FLOAT16)
|
||||
/**
|
||||
* @brief 16-bit float 64-bit vector data type.
|
||||
*/
|
||||
typedef __ALIGNED(2) float16x4_t f16x4_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit floating-point 128-bit vector triplet data type
|
||||
*/
|
||||
typedef float16x8x3_t f16x8x3_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit floating-point 64-bit vector pair data type
|
||||
*/
|
||||
typedef float16x4x2_t f16x4x2_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit floating-point 64-bit vector triplet data type
|
||||
*/
|
||||
typedef float16x4x3_t f16x4x3_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit floating-point 64-bit vector quadruplet data type
|
||||
*/
|
||||
typedef float16x4x4_t f16x4x4_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit ubiquitous 64-bit vector data type
|
||||
*/
|
||||
typedef union _any16x4_t
|
||||
{
|
||||
float16x4_t f;
|
||||
int16x4_t i;
|
||||
} any16x4_t;
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
|
||||
#define F16INFINITY ((float16_t) INFINITY)
|
||||
|
||||
#else
|
||||
|
||||
#define F16INFINITY ((float16_t)__builtin_inf())
|
||||
|
||||
#endif
|
||||
|
||||
#define F16_MAX ((float16_t)__FLT16_MAX__)
|
||||
#define F16_MIN (-(_Float16)__FLT16_MAX__)
|
||||
|
||||
#define F16_ABSMAX ((float16_t)__FLT16_MAX__)
|
||||
#define F16_ABSMIN ((float16_t)0.0f16)
|
||||
|
||||
#endif /* ARM_FLOAT16_SUPPORTED*/
|
||||
#endif /* !defined( __CC_ARM ) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ARM_MATH_F16_H */
|
||||
|
|
@ -0,0 +1,231 @@
|
|||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_mve_tables.h
|
||||
* Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc
|
||||
* used for MVE implementation only
|
||||
*
|
||||
* @version V1.10.0
|
||||
* @date 04 October 2021
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_MVE_TABLES_H
|
||||
#define _ARM_MVE_TABLES_H
|
||||
|
||||
#include "arm_math_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) || defined(ARM_TABLE_TWIDDLECOEF_F32_32)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f32[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f32[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f32[2];
|
||||
extern float32_t rearranged_twiddle_stride1_16_f32[8];
|
||||
extern float32_t rearranged_twiddle_stride2_16_f32[8];
|
||||
extern float32_t rearranged_twiddle_stride3_16_f32[8];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) || defined(ARM_TABLE_TWIDDLECOEF_F32_128)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f32[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f32[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f32[3];
|
||||
extern float32_t rearranged_twiddle_stride1_64_f32[40];
|
||||
extern float32_t rearranged_twiddle_stride2_64_f32[40];
|
||||
extern float32_t rearranged_twiddle_stride3_64_f32[40];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) || defined(ARM_TABLE_TWIDDLECOEF_F32_512)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f32[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f32[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f32[4];
|
||||
extern float32_t rearranged_twiddle_stride1_256_f32[168];
|
||||
extern float32_t rearranged_twiddle_stride2_256_f32[168];
|
||||
extern float32_t rearranged_twiddle_stride3_256_f32[168];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f32[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f32[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f32[5];
|
||||
extern float32_t rearranged_twiddle_stride1_1024_f32[680];
|
||||
extern float32_t rearranged_twiddle_stride2_1024_f32[680];
|
||||
extern float32_t rearranged_twiddle_stride3_1024_f32[680];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) || defined(ARM_TABLE_TWIDDLECOEF_F32_8192)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f32[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f32[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f32[6];
|
||||
extern float32_t rearranged_twiddle_stride1_4096_f32[2728];
|
||||
extern float32_t rearranged_twiddle_stride2_4096_f32[2728];
|
||||
extern float32_t rearranged_twiddle_stride3_4096_f32[2728];
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
|
||||
|
||||
#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */
|
||||
|
||||
|
||||
|
||||
#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q31[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q31[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q31[2];
|
||||
extern q31_t rearranged_twiddle_stride1_16_q31[8];
|
||||
extern q31_t rearranged_twiddle_stride2_16_q31[8];
|
||||
extern q31_t rearranged_twiddle_stride3_16_q31[8];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q31[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q31[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q31[3];
|
||||
extern q31_t rearranged_twiddle_stride1_64_q31[40];
|
||||
extern q31_t rearranged_twiddle_stride2_64_q31[40];
|
||||
extern q31_t rearranged_twiddle_stride3_64_q31[40];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q31[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q31[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q31[4];
|
||||
extern q31_t rearranged_twiddle_stride1_256_q31[168];
|
||||
extern q31_t rearranged_twiddle_stride2_256_q31[168];
|
||||
extern q31_t rearranged_twiddle_stride3_256_q31[168];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q31[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q31[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q31[5];
|
||||
extern q31_t rearranged_twiddle_stride1_1024_q31[680];
|
||||
extern q31_t rearranged_twiddle_stride2_1024_q31[680];
|
||||
extern q31_t rearranged_twiddle_stride3_1024_q31[680];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q31_8192)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q31[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q31[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q31[6];
|
||||
extern q31_t rearranged_twiddle_stride1_4096_q31[2728];
|
||||
extern q31_t rearranged_twiddle_stride2_4096_q31[2728];
|
||||
extern q31_t rearranged_twiddle_stride3_4096_q31[2728];
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
|
||||
|
||||
#endif /* defined(ARM_MATH_MVEI) */
|
||||
|
||||
|
||||
|
||||
#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q15[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q15[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q15[2];
|
||||
extern q15_t rearranged_twiddle_stride1_16_q15[8];
|
||||
extern q15_t rearranged_twiddle_stride2_16_q15[8];
|
||||
extern q15_t rearranged_twiddle_stride3_16_q15[8];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q15[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q15[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q15[3];
|
||||
extern q15_t rearranged_twiddle_stride1_64_q15[40];
|
||||
extern q15_t rearranged_twiddle_stride2_64_q15[40];
|
||||
extern q15_t rearranged_twiddle_stride3_64_q15[40];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q15[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q15[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q15[4];
|
||||
extern q15_t rearranged_twiddle_stride1_256_q15[168];
|
||||
extern q15_t rearranged_twiddle_stride2_256_q15[168];
|
||||
extern q15_t rearranged_twiddle_stride3_256_q15[168];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q15[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q15[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q15[5];
|
||||
extern q15_t rearranged_twiddle_stride1_1024_q15[680];
|
||||
extern q15_t rearranged_twiddle_stride2_1024_q15[680];
|
||||
extern q15_t rearranged_twiddle_stride3_1024_q15[680];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q15_8192)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q15[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q15[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q15[6];
|
||||
extern q15_t rearranged_twiddle_stride1_4096_q15[2728];
|
||||
extern q15_t rearranged_twiddle_stride2_4096_q15[2728];
|
||||
extern q15_t rearranged_twiddle_stride3_4096_q15[2728];
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
|
||||
|
||||
#endif /* defined(ARM_MATH_MVEI) */
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*_ARM_MVE_TABLES_H*/
|
||||
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_mve_tables_f16.h
|
||||
* Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc
|
||||
* used for MVE implementation only
|
||||
*
|
||||
* @version V1.10.0
|
||||
* @date 04 October 2021
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_MVE_TABLES_F16_H
|
||||
#define _ARM_MVE_TABLES_F16_H
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_16) || defined(ARM_TABLE_TWIDDLECOEF_F16_32)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f16[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f16[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f16[2];
|
||||
extern float16_t rearranged_twiddle_stride1_16_f16[8];
|
||||
extern float16_t rearranged_twiddle_stride2_16_f16[8];
|
||||
extern float16_t rearranged_twiddle_stride3_16_f16[8];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_64) || defined(ARM_TABLE_TWIDDLECOEF_F16_128)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f16[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f16[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f16[3];
|
||||
extern float16_t rearranged_twiddle_stride1_64_f16[40];
|
||||
extern float16_t rearranged_twiddle_stride2_64_f16[40];
|
||||
extern float16_t rearranged_twiddle_stride3_64_f16[40];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_256) || defined(ARM_TABLE_TWIDDLECOEF_F16_512)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f16[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f16[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f16[4];
|
||||
extern float16_t rearranged_twiddle_stride1_256_f16[168];
|
||||
extern float16_t rearranged_twiddle_stride2_256_f16[168];
|
||||
extern float16_t rearranged_twiddle_stride3_256_f16[168];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_1024) || defined(ARM_TABLE_TWIDDLECOEF_F16_2048)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f16[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f16[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f16[5];
|
||||
extern float16_t rearranged_twiddle_stride1_1024_f16[680];
|
||||
extern float16_t rearranged_twiddle_stride2_1024_f16[680];
|
||||
extern float16_t rearranged_twiddle_stride3_1024_f16[680];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_4096) || defined(ARM_TABLE_TWIDDLECOEF_F16_8192)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f16[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f16[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f16[6];
|
||||
extern float16_t rearranged_twiddle_stride1_4096_f16[2728];
|
||||
extern float16_t rearranged_twiddle_stride2_4096_f16[2728];
|
||||
extern float16_t rearranged_twiddle_stride3_4096_f16[2728];
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
|
||||
|
||||
#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*_ARM_MVE_TABLES_F16_H*/
|
||||
|
||||
|
|
@ -0,0 +1,373 @@
|
|||
/******************************************************************************
|
||||
* @file arm_vec_math.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_VEC_MATH_H
|
||||
#define _ARM_VEC_MATH_H
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_common_tables.h"
|
||||
#include "arm_helium_utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#define INV_NEWTON_INIT_F32 0x7EF127EA
|
||||
|
||||
static const float32_t __logf_rng_f32=0.693147180f;
|
||||
|
||||
|
||||
/* fast inverse approximation (3x newton) */
|
||||
__STATIC_INLINE f32x4_t vrecip_medprec_f32(
|
||||
f32x4_t x)
|
||||
{
|
||||
q31x4_t m;
|
||||
f32x4_t b;
|
||||
any32x4_t xinv;
|
||||
f32x4_t ax = vabsq(x);
|
||||
|
||||
xinv.f = ax;
|
||||
m = 0x3F800000 - (xinv.i & 0x7F800000);
|
||||
xinv.i = xinv.i + m;
|
||||
xinv.f = 1.41176471f - 0.47058824f * xinv.f;
|
||||
xinv.i = xinv.i + m;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f));
|
||||
/*
|
||||
* restore sign
|
||||
*/
|
||||
xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f));
|
||||
|
||||
return xinv.f;
|
||||
}
|
||||
|
||||
/* fast inverse approximation (4x newton) */
|
||||
__STATIC_INLINE f32x4_t vrecip_hiprec_f32(
|
||||
f32x4_t x)
|
||||
{
|
||||
q31x4_t m;
|
||||
f32x4_t b;
|
||||
any32x4_t xinv;
|
||||
f32x4_t ax = vabsq(x);
|
||||
|
||||
xinv.f = ax;
|
||||
|
||||
m = 0x3F800000 - (xinv.i & 0x7F800000);
|
||||
xinv.i = xinv.i + m;
|
||||
xinv.f = 1.41176471f - 0.47058824f * xinv.f;
|
||||
xinv.i = xinv.i + m;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f));
|
||||
/*
|
||||
* restore sign
|
||||
*/
|
||||
xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f));
|
||||
|
||||
return xinv.f;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vdiv_f32(
|
||||
f32x4_t num, f32x4_t den)
|
||||
{
|
||||
return vmulq(num, vrecip_hiprec_f32(den));
|
||||
}
|
||||
|
||||
/**
|
||||
@brief Single-precision taylor dev.
|
||||
@param[in] x f32 quad vector input
|
||||
@param[in] coeffs f32 quad vector coeffs
|
||||
@return destination f32 quad vector
|
||||
*/
|
||||
|
||||
__STATIC_INLINE f32x4_t vtaylor_polyq_f32(
|
||||
f32x4_t x,
|
||||
const float32_t * coeffs)
|
||||
{
|
||||
f32x4_t A = vfmasq(vdupq_n_f32(coeffs[4]), x, coeffs[0]);
|
||||
f32x4_t B = vfmasq(vdupq_n_f32(coeffs[6]), x, coeffs[2]);
|
||||
f32x4_t C = vfmasq(vdupq_n_f32(coeffs[5]), x, coeffs[1]);
|
||||
f32x4_t D = vfmasq(vdupq_n_f32(coeffs[7]), x, coeffs[3]);
|
||||
f32x4_t x2 = vmulq(x, x);
|
||||
f32x4_t x4 = vmulq(x2, x2);
|
||||
f32x4_t res = vfmaq(vfmaq_f32(A, B, x2), vfmaq_f32(C, D, x2), x4);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vmant_exp_f32(
|
||||
f32x4_t x,
|
||||
int32x4_t * e)
|
||||
{
|
||||
any32x4_t r;
|
||||
int32x4_t n;
|
||||
|
||||
r.f = x;
|
||||
n = r.i >> 23;
|
||||
n = n - 127;
|
||||
r.i = r.i - (n << 23);
|
||||
|
||||
*e = n;
|
||||
return r.f;
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE f32x4_t vlogq_f32(f32x4_t vecIn)
|
||||
{
|
||||
q31x4_t vecExpUnBiased;
|
||||
f32x4_t vecTmpFlt0, vecTmpFlt1;
|
||||
f32x4_t vecAcc0, vecAcc1, vecAcc2, vecAcc3;
|
||||
f32x4_t vecExpUnBiasedFlt;
|
||||
|
||||
/*
|
||||
* extract exponent
|
||||
*/
|
||||
vecTmpFlt1 = vmant_exp_f32(vecIn, &vecExpUnBiased);
|
||||
|
||||
vecTmpFlt0 = vecTmpFlt1 * vecTmpFlt1;
|
||||
/*
|
||||
* a = (__logf_lut_f32[4] * r.f) + (__logf_lut_f32[0]);
|
||||
*/
|
||||
vecAcc0 = vdupq_n_f32(__logf_lut_f32[0]);
|
||||
vecAcc0 = vfmaq(vecAcc0, vecTmpFlt1, __logf_lut_f32[4]);
|
||||
/*
|
||||
* b = (__logf_lut_f32[6] * r.f) + (__logf_lut_f32[2]);
|
||||
*/
|
||||
vecAcc1 = vdupq_n_f32(__logf_lut_f32[2]);
|
||||
vecAcc1 = vfmaq(vecAcc1, vecTmpFlt1, __logf_lut_f32[6]);
|
||||
/*
|
||||
* c = (__logf_lut_f32[5] * r.f) + (__logf_lut_f32[1]);
|
||||
*/
|
||||
vecAcc2 = vdupq_n_f32(__logf_lut_f32[1]);
|
||||
vecAcc2 = vfmaq(vecAcc2, vecTmpFlt1, __logf_lut_f32[5]);
|
||||
/*
|
||||
* d = (__logf_lut_f32[7] * r.f) + (__logf_lut_f32[3]);
|
||||
*/
|
||||
vecAcc3 = vdupq_n_f32(__logf_lut_f32[3]);
|
||||
vecAcc3 = vfmaq(vecAcc3, vecTmpFlt1, __logf_lut_f32[7]);
|
||||
/*
|
||||
* a = a + b * xx;
|
||||
*/
|
||||
vecAcc0 = vfmaq(vecAcc0, vecAcc1, vecTmpFlt0);
|
||||
/*
|
||||
* c = c + d * xx;
|
||||
*/
|
||||
vecAcc2 = vfmaq(vecAcc2, vecAcc3, vecTmpFlt0);
|
||||
/*
|
||||
* xx = xx * xx;
|
||||
*/
|
||||
vecTmpFlt0 = vecTmpFlt0 * vecTmpFlt0;
|
||||
vecExpUnBiasedFlt = vcvtq_f32_s32(vecExpUnBiased);
|
||||
/*
|
||||
* r.f = a + c * xx;
|
||||
*/
|
||||
vecAcc0 = vfmaq(vecAcc0, vecAcc2, vecTmpFlt0);
|
||||
/*
|
||||
* add exponent
|
||||
* r.f = r.f + ((float32_t) m) * __logf_rng_f32;
|
||||
*/
|
||||
vecAcc0 = vfmaq(vecAcc0, vecExpUnBiasedFlt, __logf_rng_f32);
|
||||
// set log0 down to -inf
|
||||
vecAcc0 = vdupq_m(vecAcc0, -INFINITY, vcmpeqq(vecIn, 0.0f));
|
||||
return vecAcc0;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vexpq_f32(
|
||||
f32x4_t x)
|
||||
{
|
||||
// Perform range reduction [-log(2),log(2)]
|
||||
int32x4_t m = vcvtq_s32_f32(vmulq_n_f32(x, 1.4426950408f));
|
||||
f32x4_t val = vfmsq_f32(x, vcvtq_f32_s32(m), vdupq_n_f32(0.6931471805f));
|
||||
|
||||
// Polynomial Approximation
|
||||
f32x4_t poly = vtaylor_polyq_f32(val, exp_tab);
|
||||
|
||||
// Reconstruct
|
||||
poly = (f32x4_t) (vqaddq_s32((q31x4_t) (poly), vqshlq_n_s32(m, 23)));
|
||||
|
||||
poly = vdupq_m(poly, 0.0f, vcmpltq_n_s32(m, -126));
|
||||
return poly;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t arm_vec_exponent_f32(f32x4_t x, int32_t nb)
|
||||
{
|
||||
f32x4_t r = x;
|
||||
nb--;
|
||||
while (nb > 0) {
|
||||
r = vmulq(r, x);
|
||||
nb--;
|
||||
}
|
||||
return (r);
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vrecip_f32(f32x4_t vecIn)
|
||||
{
|
||||
f32x4_t vecSx, vecW, vecTmp;
|
||||
any32x4_t v;
|
||||
|
||||
vecSx = vabsq(vecIn);
|
||||
|
||||
v.f = vecIn;
|
||||
v.i = vsubq(vdupq_n_s32(INV_NEWTON_INIT_F32), v.i);
|
||||
|
||||
vecW = vmulq(vecSx, v.f);
|
||||
|
||||
// v.f = v.f * (8 + w * (-28 + w * (56 + w * (-70 + w *(56 + w * (-28 + w * (8 - w)))))));
|
||||
vecTmp = vsubq(vdupq_n_f32(8.0f), vecW);
|
||||
vecTmp = vfmasq(vecW, vecTmp, -28.0f);
|
||||
vecTmp = vfmasq(vecW, vecTmp, 56.0f);
|
||||
vecTmp = vfmasq(vecW, vecTmp, -70.0f);
|
||||
vecTmp = vfmasq(vecW, vecTmp, 56.0f);
|
||||
vecTmp = vfmasq(vecW, vecTmp, -28.0f);
|
||||
vecTmp = vfmasq(vecW, vecTmp, 8.0f);
|
||||
v.f = vmulq(v.f, vecTmp);
|
||||
|
||||
v.f = vdupq_m(v.f, INFINITY, vcmpeqq(vecIn, 0.0f));
|
||||
/*
|
||||
* restore sign
|
||||
*/
|
||||
v.f = vnegq_m(v.f, v.f, vcmpltq(vecIn, 0.0f));
|
||||
return v.f;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vtanhq_f32(
|
||||
f32x4_t val)
|
||||
{
|
||||
f32x4_t x =
|
||||
vminnmq_f32(vmaxnmq_f32(val, vdupq_n_f32(-10.f)), vdupq_n_f32(10.0f));
|
||||
f32x4_t exp2x = vexpq_f32(vmulq_n_f32(x, 2.f));
|
||||
f32x4_t num = vsubq_n_f32(exp2x, 1.f);
|
||||
f32x4_t den = vaddq_n_f32(exp2x, 1.f);
|
||||
f32x4_t tanh = vmulq_f32(num, vrecip_f32(den));
|
||||
return tanh;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vpowq_f32(
|
||||
f32x4_t val,
|
||||
f32x4_t n)
|
||||
{
|
||||
return vexpq_f32(vmulq_f32(n, vlogq_f32(val)));
|
||||
}
|
||||
|
||||
#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/
|
||||
|
||||
#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */
|
||||
|
||||
#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#include "NEMath.h"
|
||||
/**
|
||||
* @brief Vectorized integer exponentiation
|
||||
* @param[in] x value
|
||||
* @param[in] nb integer exponent >= 1
|
||||
* @return x^nb
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE float32x4_t arm_vec_exponent_f32(float32x4_t x, int32_t nb)
|
||||
{
|
||||
float32x4_t r = x;
|
||||
nb --;
|
||||
while(nb > 0)
|
||||
{
|
||||
r = vmulq_f32(r , x);
|
||||
nb--;
|
||||
}
|
||||
return(r);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x)
|
||||
{
|
||||
float32x4_t x1 = vmaxq_f32(x, vdupq_n_f32(FLT_MIN));
|
||||
float32x4_t e = vrsqrteq_f32(x1);
|
||||
e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e);
|
||||
e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e);
|
||||
return vmulq_f32(x, e);
|
||||
}
|
||||
|
||||
__STATIC_INLINE int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec)
|
||||
{
|
||||
float32x4_t tempF;
|
||||
int32x4_t tempHI,tempLO;
|
||||
|
||||
tempLO = vmovl_s16(vget_low_s16(vec));
|
||||
tempF = vcvtq_n_f32_s32(tempLO,15);
|
||||
tempF = __arm_vec_sqrt_f32_neon(tempF);
|
||||
tempLO = vcvtq_n_s32_f32(tempF,15);
|
||||
|
||||
tempHI = vmovl_s16(vget_high_s16(vec));
|
||||
tempF = vcvtq_n_f32_s32(tempHI,15);
|
||||
tempF = __arm_vec_sqrt_f32_neon(tempF);
|
||||
tempHI = vcvtq_n_s32_f32(tempF,15);
|
||||
|
||||
return(vcombine_s16(vqmovn_s32(tempLO),vqmovn_s32(tempHI)));
|
||||
}
|
||||
|
||||
__STATIC_INLINE int32x4_t __arm_vec_sqrt_q31_neon(int32x4_t vec)
|
||||
{
|
||||
float32x4_t temp;
|
||||
|
||||
temp = vcvtq_n_f32_s32(vec,31);
|
||||
temp = __arm_vec_sqrt_f32_neon(temp);
|
||||
return(vcvtq_n_s32_f32(temp,31));
|
||||
}
|
||||
|
||||
#endif /* (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* _ARM_VEC_MATH_H */
|
||||
|
||||
/**
|
||||
*
|
||||
* End of file.
|
||||
*/
|
||||
|
|
@ -0,0 +1,312 @@
|
|||
/******************************************************************************
|
||||
* @file arm_vec_math_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_VEC_MATH_F16_H
|
||||
#define _ARM_VEC_MATH_F16_H
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_common_tables_f16.h"
|
||||
#include "arm_helium_utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
|
||||
#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
|
||||
static const float16_t __logf_rng_f16=0.693147180f16;
|
||||
|
||||
/* fast inverse approximation (3x newton) */
|
||||
__STATIC_INLINE f16x8_t vrecip_medprec_f16(
|
||||
f16x8_t x)
|
||||
{
|
||||
q15x8_t m;
|
||||
f16x8_t b;
|
||||
any16x8_t xinv;
|
||||
f16x8_t ax = vabsq(x);
|
||||
|
||||
xinv.f = ax;
|
||||
|
||||
m = 0x03c00 - (xinv.i & 0x07c00);
|
||||
xinv.i = xinv.i + m;
|
||||
xinv.f = 1.41176471f16 - 0.47058824f16 * xinv.f;
|
||||
xinv.i = xinv.i + m;
|
||||
|
||||
b = 2.0f16 - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f16 - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f16 - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
xinv.f = vdupq_m_n_f16(xinv.f, F16INFINITY, vcmpeqq_n_f16(x, 0.0f));
|
||||
/*
|
||||
* restore sign
|
||||
*/
|
||||
xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq_n_f16(x, 0.0f));
|
||||
|
||||
return xinv.f;
|
||||
}
|
||||
|
||||
/* fast inverse approximation (4x newton) */
|
||||
__STATIC_INLINE f16x8_t vrecip_hiprec_f16(
|
||||
f16x8_t x)
|
||||
{
|
||||
q15x8_t m;
|
||||
f16x8_t b;
|
||||
any16x8_t xinv;
|
||||
f16x8_t ax = vabsq(x);
|
||||
|
||||
xinv.f = ax;
|
||||
|
||||
m = 0x03c00 - (xinv.i & 0x07c00);
|
||||
xinv.i = xinv.i + m;
|
||||
xinv.f = 1.41176471f16 - 0.47058824f16 * xinv.f;
|
||||
xinv.i = xinv.i + m;
|
||||
|
||||
b = 2.0f16 - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f16 - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f16 - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f16 - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
xinv.f = vdupq_m_n_f16(xinv.f, F16INFINITY, vcmpeqq_n_f16(x, 0.0f));
|
||||
/*
|
||||
* restore sign
|
||||
*/
|
||||
xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq_n_f16(x, 0.0f));
|
||||
|
||||
return xinv.f;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f16x8_t vdiv_f16(
|
||||
f16x8_t num, f16x8_t den)
|
||||
{
|
||||
return vmulq(num, vrecip_hiprec_f16(den));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
@brief Single-precision taylor dev.
|
||||
@param[in] x f16 vector input
|
||||
@param[in] coeffs f16 vector coeffs
|
||||
@return destination f16 vector
|
||||
*/
|
||||
|
||||
__STATIC_INLINE float16x8_t vtaylor_polyq_f16(
|
||||
float16x8_t x,
|
||||
const float16_t * coeffs)
|
||||
{
|
||||
float16x8_t A = vfmasq(vdupq_n_f16(coeffs[4]), x, coeffs[0]);
|
||||
float16x8_t B = vfmasq(vdupq_n_f16(coeffs[6]), x, coeffs[2]);
|
||||
float16x8_t C = vfmasq(vdupq_n_f16(coeffs[5]), x, coeffs[1]);
|
||||
float16x8_t D = vfmasq(vdupq_n_f16(coeffs[7]), x, coeffs[3]);
|
||||
float16x8_t x2 = vmulq(x, x);
|
||||
float16x8_t x4 = vmulq(x2, x2);
|
||||
float16x8_t res = vfmaq(vfmaq_f16(A, B, x2), vfmaq_f16(C, D, x2), x4);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
#define VMANT_EXP_F16(x) \
|
||||
any16x8_t r; \
|
||||
int16x8_t n; \
|
||||
\
|
||||
r.f = x; \
|
||||
n = r.i >> 10; \
|
||||
n = n - 15; \
|
||||
r.i = r.i - (n << 10);\
|
||||
\
|
||||
vecExpUnBiased = n; \
|
||||
vecTmpFlt1 = r.f;
|
||||
|
||||
__STATIC_INLINE float16x8_t vlogq_f16(float16x8_t vecIn)
|
||||
{
|
||||
q15x8_t vecExpUnBiased;
|
||||
float16x8_t vecTmpFlt0, vecTmpFlt1;
|
||||
float16x8_t vecAcc0, vecAcc1, vecAcc2, vecAcc3;
|
||||
float16x8_t vecExpUnBiasedFlt;
|
||||
|
||||
/*
|
||||
* extract exponent
|
||||
*/
|
||||
VMANT_EXP_F16(vecIn);
|
||||
|
||||
vecTmpFlt0 = vecTmpFlt1 * vecTmpFlt1;
|
||||
/*
|
||||
* a = (__logf_lut_f16[4] * r.f) + (__logf_lut_f16[0]);
|
||||
*/
|
||||
vecAcc0 = vdupq_n_f16(__logf_lut_f16[0]);
|
||||
vecAcc0 = vfmaq(vecAcc0, vecTmpFlt1, __logf_lut_f16[4]);
|
||||
/*
|
||||
* b = (__logf_lut_f16[6] * r.f) + (__logf_lut_f16[2]);
|
||||
*/
|
||||
vecAcc1 = vdupq_n_f16(__logf_lut_f16[2]);
|
||||
vecAcc1 = vfmaq(vecAcc1, vecTmpFlt1, __logf_lut_f16[6]);
|
||||
/*
|
||||
* c = (__logf_lut_f16[5] * r.f) + (__logf_lut_f16[1]);
|
||||
*/
|
||||
vecAcc2 = vdupq_n_f16(__logf_lut_f16[1]);
|
||||
vecAcc2 = vfmaq(vecAcc2, vecTmpFlt1, __logf_lut_f16[5]);
|
||||
/*
|
||||
* d = (__logf_lut_f16[7] * r.f) + (__logf_lut_f16[3]);
|
||||
*/
|
||||
vecAcc3 = vdupq_n_f16(__logf_lut_f16[3]);
|
||||
vecAcc3 = vfmaq(vecAcc3, vecTmpFlt1, __logf_lut_f16[7]);
|
||||
/*
|
||||
* a = a + b * xx;
|
||||
*/
|
||||
vecAcc0 = vfmaq(vecAcc0, vecAcc1, vecTmpFlt0);
|
||||
/*
|
||||
* c = c + d * xx;
|
||||
*/
|
||||
vecAcc2 = vfmaq(vecAcc2, vecAcc3, vecTmpFlt0);
|
||||
/*
|
||||
* xx = xx * xx;
|
||||
*/
|
||||
vecTmpFlt0 = vecTmpFlt0 * vecTmpFlt0;
|
||||
vecExpUnBiasedFlt = vcvtq_f16_s16(vecExpUnBiased);
|
||||
/*
|
||||
* r.f = a + c * xx;
|
||||
*/
|
||||
vecAcc0 = vfmaq(vecAcc0, vecAcc2, vecTmpFlt0);
|
||||
/*
|
||||
* add exponent
|
||||
* r.f = r.f + ((float32_t) m) * __logf_rng_f16;
|
||||
*/
|
||||
vecAcc0 = vfmaq(vecAcc0, vecExpUnBiasedFlt, __logf_rng_f16);
|
||||
// set log0 down to -inf
|
||||
vecAcc0 = vdupq_m_n_f16(vecAcc0, -(_Float16)F16INFINITY, vcmpeqq_n_f16(vecIn, 0.0f));
|
||||
return vecAcc0;
|
||||
}
|
||||
|
||||
__STATIC_INLINE float16x8_t vexpq_f16(
|
||||
float16x8_t x)
|
||||
{
|
||||
// Perform range reduction [-log(2),log(2)]
|
||||
int16x8_t m = vcvtq_s16_f16(vmulq_n_f16(x, 1.4426950408f16));
|
||||
float16x8_t val = vfmsq_f16(x, vcvtq_f16_s16(m), vdupq_n_f16(0.6931471805f16));
|
||||
|
||||
// Polynomial Approximation
|
||||
float16x8_t poly = vtaylor_polyq_f16(val, exp_tab_f16);
|
||||
|
||||
// Reconstruct
|
||||
poly = (float16x8_t) (vqaddq_s16((int16x8_t) (poly), vqshlq_n_s16(m, 10)));
|
||||
|
||||
poly = vdupq_m_n_f16(poly, 0.0f16, vcmpltq_n_s16(m, -14));
|
||||
return poly;
|
||||
}
|
||||
|
||||
__STATIC_INLINE float16x8_t arm_vec_exponent_f16(float16x8_t x, int16_t nb)
|
||||
{
|
||||
float16x8_t r = x;
|
||||
nb--;
|
||||
while (nb > 0) {
|
||||
r = vmulq(r, x);
|
||||
nb--;
|
||||
}
|
||||
return (r);
|
||||
}
|
||||
|
||||
__STATIC_INLINE f16x8_t vpowq_f16(
|
||||
f16x8_t val,
|
||||
f16x8_t n)
|
||||
{
|
||||
return vexpq_f16(vmulq_f16(n, vlogq_f16(val)));
|
||||
}
|
||||
|
||||
#define INV_NEWTON_INIT_F16 0x7773
|
||||
|
||||
__STATIC_INLINE f16x8_t vrecip_f16(f16x8_t vecIn)
|
||||
{
|
||||
f16x8_t vecSx, vecW, vecTmp;
|
||||
any16x8_t v;
|
||||
|
||||
vecSx = vabsq(vecIn);
|
||||
|
||||
v.f = vecIn;
|
||||
v.i = vsubq(vdupq_n_s16(INV_NEWTON_INIT_F16), v.i);
|
||||
|
||||
vecW = vmulq(vecSx, v.f);
|
||||
|
||||
// v.f = v.f * (8 + w * (-28 + w * (56 + w * (-70 + w *(56 + w * (-28 + w * (8 - w)))))));
|
||||
vecTmp = vsubq(vdupq_n_f16(8.0f16), vecW);
|
||||
vecTmp = vfmasq_n_f16(vecW, vecTmp, -28.0f16);
|
||||
vecTmp = vfmasq_n_f16(vecW, vecTmp, 56.0f16);
|
||||
vecTmp = vfmasq_n_f16(vecW, vecTmp, -70.0f16);
|
||||
vecTmp = vfmasq_n_f16(vecW, vecTmp, 56.0f16);
|
||||
vecTmp = vfmasq_n_f16(vecW, vecTmp, -28.0f16);
|
||||
vecTmp = vfmasq_n_f16(vecW, vecTmp, 8.0f16);
|
||||
v.f = vmulq(v.f, vecTmp);
|
||||
|
||||
v.f = vdupq_m_n_f16(v.f, F16INFINITY, vcmpeqq_n_f16(vecIn, 0.0f));
|
||||
/*
|
||||
* restore sign
|
||||
*/
|
||||
v.f = vnegq_m(v.f, v.f, vcmpltq_n_f16(vecIn, 0.0f));
|
||||
return v.f;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f16x8_t vtanhq_f16(
|
||||
f16x8_t val)
|
||||
{
|
||||
f16x8_t x =
|
||||
vminnmq_f16(vmaxnmq_f16(val, vdupq_n_f16(-10.f16)), vdupq_n_f16(10.0f16));
|
||||
f16x8_t exp2x = vexpq_f16(vmulq_n_f16(x, 2.f16));
|
||||
f16x8_t num = vsubq_n_f16(exp2x, 1.f16);
|
||||
f16x8_t den = vaddq_n_f16(exp2x, 1.f16);
|
||||
f16x8_t tanh = vmulq_f16(num, vrecip_f16(den));
|
||||
return tanh;
|
||||
}
|
||||
|
||||
#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)*/
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ARM FLOAT16 SUPPORTED */
|
||||
|
||||
#endif /* _ARM_VEC_MATH_F16_H */
|
||||
|
||||
/**
|
||||
*
|
||||
* End of file.
|
||||
*/
|
||||
|
|
@ -0,0 +1,880 @@
|
|||
/******************************************************************************
|
||||
* @file basic_math_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _BASIC_MATH_FUNCTIONS_H_
|
||||
#define _BASIC_MATH_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @defgroup groupMath Basic Math Functions
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Q7 vector multiplication.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_mult_q7(
|
||||
const q7_t * pSrcA,
|
||||
const q7_t * pSrcB,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q15 vector multiplication.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_mult_q15(
|
||||
const q15_t * pSrcA,
|
||||
const q15_t * pSrcB,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q31 vector multiplication.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_mult_q31(
|
||||
const q31_t * pSrcA,
|
||||
const q31_t * pSrcB,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point vector multiplication.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_mult_f32(
|
||||
const float32_t * pSrcA,
|
||||
const float32_t * pSrcB,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point vector multiplication.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_mult_f64(
|
||||
const float64_t * pSrcA,
|
||||
const float64_t * pSrcB,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point vector addition.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_add_f32(
|
||||
const float32_t * pSrcA,
|
||||
const float32_t * pSrcB,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point vector addition.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_add_f64(
|
||||
const float64_t * pSrcA,
|
||||
const float64_t * pSrcB,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q7 vector addition.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_add_q7(
|
||||
const q7_t * pSrcA,
|
||||
const q7_t * pSrcB,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q15 vector addition.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_add_q15(
|
||||
const q15_t * pSrcA,
|
||||
const q15_t * pSrcB,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q31 vector addition.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_add_q31(
|
||||
const q31_t * pSrcA,
|
||||
const q31_t * pSrcB,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point vector subtraction.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_sub_f32(
|
||||
const float32_t * pSrcA,
|
||||
const float32_t * pSrcB,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point vector subtraction.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_sub_f64(
|
||||
const float64_t * pSrcA,
|
||||
const float64_t * pSrcB,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q7 vector subtraction.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_sub_q7(
|
||||
const q7_t * pSrcA,
|
||||
const q7_t * pSrcB,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q15 vector subtraction.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_sub_q15(
|
||||
const q15_t * pSrcA,
|
||||
const q15_t * pSrcB,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q31 vector subtraction.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_sub_q31(
|
||||
const q31_t * pSrcA,
|
||||
const q31_t * pSrcB,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Multiplies a floating-point vector by a scalar.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] scale scale factor to be applied
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_scale_f32(
|
||||
const float32_t * pSrc,
|
||||
float32_t scale,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Multiplies a floating-point vector by a scalar.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] scale scale factor to be applied
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_scale_f64(
|
||||
const float64_t * pSrc,
|
||||
float64_t scale,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Multiplies a Q7 vector by a scalar.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] scaleFract fractional portion of the scale value
|
||||
* @param[in] shift number of bits to shift the result by
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_scale_q7(
|
||||
const q7_t * pSrc,
|
||||
q7_t scaleFract,
|
||||
int8_t shift,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Multiplies a Q15 vector by a scalar.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] scaleFract fractional portion of the scale value
|
||||
* @param[in] shift number of bits to shift the result by
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_scale_q15(
|
||||
const q15_t * pSrc,
|
||||
q15_t scaleFract,
|
||||
int8_t shift,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Multiplies a Q31 vector by a scalar.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] scaleFract fractional portion of the scale value
|
||||
* @param[in] shift number of bits to shift the result by
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_scale_q31(
|
||||
const q31_t * pSrc,
|
||||
q31_t scaleFract,
|
||||
int8_t shift,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q7 vector absolute value.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[out] pDst points to the output buffer
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_abs_q7(
|
||||
const q7_t * pSrc,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point vector absolute value.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[out] pDst points to the output buffer
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_abs_f32(
|
||||
const float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point vector absolute value.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[out] pDst points to the output buffer
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_abs_f64(
|
||||
const float64_t * pSrc,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q15 vector absolute value.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[out] pDst points to the output buffer
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_abs_q15(
|
||||
const q15_t * pSrc,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q31 vector absolute value.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[out] pDst points to the output buffer
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_abs_q31(
|
||||
const q31_t * pSrc,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Dot product of floating-point vectors.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @param[out] result output result returned here
|
||||
*/
|
||||
void arm_dot_prod_f32(
|
||||
const float32_t * pSrcA,
|
||||
const float32_t * pSrcB,
|
||||
uint32_t blockSize,
|
||||
float32_t * result);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Dot product of floating-point vectors.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @param[out] result output result returned here
|
||||
*/
|
||||
void arm_dot_prod_f64(
|
||||
const float64_t * pSrcA,
|
||||
const float64_t * pSrcB,
|
||||
uint32_t blockSize,
|
||||
float64_t * result);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Dot product of Q7 vectors.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @param[out] result output result returned here
|
||||
*/
|
||||
void arm_dot_prod_q7(
|
||||
const q7_t * pSrcA,
|
||||
const q7_t * pSrcB,
|
||||
uint32_t blockSize,
|
||||
q31_t * result);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Dot product of Q15 vectors.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @param[out] result output result returned here
|
||||
*/
|
||||
void arm_dot_prod_q15(
|
||||
const q15_t * pSrcA,
|
||||
const q15_t * pSrcB,
|
||||
uint32_t blockSize,
|
||||
q63_t * result);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Dot product of Q31 vectors.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @param[out] result output result returned here
|
||||
*/
|
||||
void arm_dot_prod_q31(
|
||||
const q31_t * pSrcA,
|
||||
const q31_t * pSrcB,
|
||||
uint32_t blockSize,
|
||||
q63_t * result);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Shifts the elements of a Q7 vector a specified number of bits.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_shift_q7(
|
||||
const q7_t * pSrc,
|
||||
int8_t shiftBits,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Shifts the elements of a Q15 vector a specified number of bits.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_shift_q15(
|
||||
const q15_t * pSrc,
|
||||
int8_t shiftBits,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Shifts the elements of a Q31 vector a specified number of bits.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_shift_q31(
|
||||
const q31_t * pSrc,
|
||||
int8_t shiftBits,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Adds a constant offset to a floating-point vector.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] offset is the offset to be added
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_offset_f64(
|
||||
const float64_t * pSrc,
|
||||
float64_t offset,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Adds a constant offset to a floating-point vector.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] offset is the offset to be added
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_offset_f32(
|
||||
const float32_t * pSrc,
|
||||
float32_t offset,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Adds a constant offset to a Q7 vector.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] offset is the offset to be added
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_offset_q7(
|
||||
const q7_t * pSrc,
|
||||
q7_t offset,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Adds a constant offset to a Q15 vector.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] offset is the offset to be added
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_offset_q15(
|
||||
const q15_t * pSrc,
|
||||
q15_t offset,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Adds a constant offset to a Q31 vector.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] offset is the offset to be added
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_offset_q31(
|
||||
const q31_t * pSrc,
|
||||
q31_t offset,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Negates the elements of a floating-point vector.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_negate_f32(
|
||||
const float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Negates the elements of a floating-point vector.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_negate_f64(
|
||||
const float64_t * pSrc,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Negates the elements of a Q7 vector.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_negate_q7(
|
||||
const q7_t * pSrc,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Negates the elements of a Q15 vector.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_negate_q15(
|
||||
const q15_t * pSrc,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Negates the elements of a Q31 vector.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_negate_q31(
|
||||
const q31_t * pSrc,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Compute the logical bitwise AND of two fixed-point vectors.
|
||||
* @param[in] pSrcA points to input vector A
|
||||
* @param[in] pSrcB points to input vector B
|
||||
* @param[out] pDst points to output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_and_u16(
|
||||
const uint16_t * pSrcA,
|
||||
const uint16_t * pSrcB,
|
||||
uint16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Compute the logical bitwise AND of two fixed-point vectors.
|
||||
* @param[in] pSrcA points to input vector A
|
||||
* @param[in] pSrcB points to input vector B
|
||||
* @param[out] pDst points to output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_and_u32(
|
||||
const uint32_t * pSrcA,
|
||||
const uint32_t * pSrcB,
|
||||
uint32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Compute the logical bitwise AND of two fixed-point vectors.
|
||||
* @param[in] pSrcA points to input vector A
|
||||
* @param[in] pSrcB points to input vector B
|
||||
* @param[out] pDst points to output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_and_u8(
|
||||
const uint8_t * pSrcA,
|
||||
const uint8_t * pSrcB,
|
||||
uint8_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Compute the logical bitwise OR of two fixed-point vectors.
|
||||
* @param[in] pSrcA points to input vector A
|
||||
* @param[in] pSrcB points to input vector B
|
||||
* @param[out] pDst points to output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_or_u16(
|
||||
const uint16_t * pSrcA,
|
||||
const uint16_t * pSrcB,
|
||||
uint16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Compute the logical bitwise OR of two fixed-point vectors.
|
||||
* @param[in] pSrcA points to input vector A
|
||||
* @param[in] pSrcB points to input vector B
|
||||
* @param[out] pDst points to output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_or_u32(
|
||||
const uint32_t * pSrcA,
|
||||
const uint32_t * pSrcB,
|
||||
uint32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Compute the logical bitwise OR of two fixed-point vectors.
|
||||
* @param[in] pSrcA points to input vector A
|
||||
* @param[in] pSrcB points to input vector B
|
||||
* @param[out] pDst points to output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_or_u8(
|
||||
const uint8_t * pSrcA,
|
||||
const uint8_t * pSrcB,
|
||||
uint8_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Compute the logical bitwise NOT of a fixed-point vector.
|
||||
* @param[in] pSrc points to input vector
|
||||
* @param[out] pDst points to output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_not_u16(
|
||||
const uint16_t * pSrc,
|
||||
uint16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Compute the logical bitwise NOT of a fixed-point vector.
|
||||
* @param[in] pSrc points to input vector
|
||||
* @param[out] pDst points to output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_not_u32(
|
||||
const uint32_t * pSrc,
|
||||
uint32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Compute the logical bitwise NOT of a fixed-point vector.
|
||||
* @param[in] pSrc points to input vector
|
||||
* @param[out] pDst points to output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_not_u8(
|
||||
const uint8_t * pSrc,
|
||||
uint8_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Compute the logical bitwise XOR of two fixed-point vectors.
|
||||
* @param[in] pSrcA points to input vector A
|
||||
* @param[in] pSrcB points to input vector B
|
||||
* @param[out] pDst points to output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_xor_u16(
|
||||
const uint16_t * pSrcA,
|
||||
const uint16_t * pSrcB,
|
||||
uint16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Compute the logical bitwise XOR of two fixed-point vectors.
|
||||
* @param[in] pSrcA points to input vector A
|
||||
* @param[in] pSrcB points to input vector B
|
||||
* @param[out] pDst points to output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_xor_u32(
|
||||
const uint32_t * pSrcA,
|
||||
const uint32_t * pSrcB,
|
||||
uint32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Compute the logical bitwise XOR of two fixed-point vectors.
|
||||
* @param[in] pSrcA points to input vector A
|
||||
* @param[in] pSrcB points to input vector B
|
||||
* @param[out] pDst points to output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_xor_u8(
|
||||
const uint8_t * pSrcA,
|
||||
const uint8_t * pSrcB,
|
||||
uint8_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
@brief Elementwise floating-point clipping
|
||||
@param[in] pSrc points to input values
|
||||
@param[out] pDst points to output clipped values
|
||||
@param[in] low lower bound
|
||||
@param[in] high higher bound
|
||||
@param[in] numSamples number of samples to clip
|
||||
@return none
|
||||
*/
|
||||
|
||||
void arm_clip_f32(const float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
float32_t low,
|
||||
float32_t high,
|
||||
uint32_t numSamples);
|
||||
|
||||
/**
|
||||
@brief Elementwise fixed-point clipping
|
||||
@param[in] pSrc points to input values
|
||||
@param[out] pDst points to output clipped values
|
||||
@param[in] low lower bound
|
||||
@param[in] high higher bound
|
||||
@param[in] numSamples number of samples to clip
|
||||
@return none
|
||||
*/
|
||||
|
||||
void arm_clip_q31(const q31_t * pSrc,
|
||||
q31_t * pDst,
|
||||
q31_t low,
|
||||
q31_t high,
|
||||
uint32_t numSamples);
|
||||
|
||||
/**
|
||||
@brief Elementwise fixed-point clipping
|
||||
@param[in] pSrc points to input values
|
||||
@param[out] pDst points to output clipped values
|
||||
@param[in] low lower bound
|
||||
@param[in] high higher bound
|
||||
@param[in] numSamples number of samples to clip
|
||||
@return none
|
||||
*/
|
||||
|
||||
void arm_clip_q15(const q15_t * pSrc,
|
||||
q15_t * pDst,
|
||||
q15_t low,
|
||||
q15_t high,
|
||||
uint32_t numSamples);
|
||||
|
||||
/**
|
||||
@brief Elementwise fixed-point clipping
|
||||
@param[in] pSrc points to input values
|
||||
@param[out] pDst points to output clipped values
|
||||
@param[in] low lower bound
|
||||
@param[in] high higher bound
|
||||
@param[in] numSamples number of samples to clip
|
||||
@return none
|
||||
*/
|
||||
|
||||
void arm_clip_q7(const q7_t * pSrc,
|
||||
q7_t * pDst,
|
||||
q7_t low,
|
||||
q7_t high,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _BASIC_MATH_FUNCTIONS_H_ */
|
||||
|
|
@ -0,0 +1,168 @@
|
|||
/******************************************************************************
|
||||
* @file basic_math_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _BASIC_MATH_FUNCTIONS_F16_H_
|
||||
#define _BASIC_MATH_FUNCTIONS_F16_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point vector addition.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_add_f16(
|
||||
const float16_t * pSrcA,
|
||||
const float16_t * pSrcB,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Floating-point vector subtraction.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_sub_f16(
|
||||
const float16_t * pSrcA,
|
||||
const float16_t * pSrcB,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Multiplies a floating-point vector by a scalar.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] scale scale factor to be applied
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_scale_f16(
|
||||
const float16_t * pSrc,
|
||||
float16_t scale,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Floating-point vector absolute value.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[out] pDst points to the output buffer
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_abs_f16(
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Adds a constant offset to a floating-point vector.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] offset is the offset to be added
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_offset_f16(
|
||||
const float16_t * pSrc,
|
||||
float16_t offset,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Dot product of floating-point vectors.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @param[out] result output result returned here
|
||||
*/
|
||||
void arm_dot_prod_f16(
|
||||
const float16_t * pSrcA,
|
||||
const float16_t * pSrcB,
|
||||
uint32_t blockSize,
|
||||
float16_t * result);
|
||||
|
||||
/**
|
||||
* @brief Floating-point vector multiplication.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_mult_f16(
|
||||
const float16_t * pSrcA,
|
||||
const float16_t * pSrcB,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Negates the elements of a floating-point vector.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_negate_f16(
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
@brief Elementwise floating-point clipping
|
||||
@param[in] pSrc points to input values
|
||||
@param[out] pDst points to output clipped values
|
||||
@param[in] low lower bound
|
||||
@param[in] high higher bound
|
||||
@param[in] numSamples number of samples to clip
|
||||
@return none
|
||||
*/
|
||||
|
||||
void arm_clip_f16(const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
float16_t low,
|
||||
float16_t high,
|
||||
uint32_t numSamples);
|
||||
|
||||
#endif /* defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _BASIC_MATH_FUNCTIONS_F16_H_ */
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/******************************************************************************
|
||||
* @file bayes_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _BAYES_FUNCTIONS_H_
|
||||
#define _BAYES_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#include "dsp/statistics_functions.h"
|
||||
|
||||
/**
|
||||
* @defgroup groupBayes Bayesian estimators
|
||||
*
|
||||
* Implement the naive gaussian Bayes estimator.
|
||||
* The training must be done from scikit-learn.
|
||||
*
|
||||
* The parameters can be easily
|
||||
* generated from the scikit-learn object. Some examples are given in
|
||||
* DSP/Testing/PatternGeneration/Bayes.py
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Instance structure for Naive Gaussian Bayesian estimator.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t vectorDimension; /**< Dimension of vector space */
|
||||
uint32_t numberOfClasses; /**< Number of different classes */
|
||||
const float32_t *theta; /**< Mean values for the Gaussians */
|
||||
const float32_t *sigma; /**< Variances for the Gaussians */
|
||||
const float32_t *classPriors; /**< Class prior probabilities */
|
||||
float32_t epsilon; /**< Additive value to variances */
|
||||
} arm_gaussian_naive_bayes_instance_f32;
|
||||
|
||||
/**
|
||||
* @brief Naive Gaussian Bayesian Estimator
|
||||
*
|
||||
* @param[in] S points to a naive bayes instance structure
|
||||
* @param[in] in points to the elements of the input vector.
|
||||
* @param[out] *pOutputProbabilities points to a buffer of length numberOfClasses containing estimated probabilities
|
||||
* @param[out] *pBufferB points to a temporary buffer of length numberOfClasses
|
||||
* @return The predicted class
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S,
|
||||
const float32_t * in,
|
||||
float32_t *pOutputProbabilities,
|
||||
float32_t *pBufferB);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _BAYES_FUNCTIONS_H_ */
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
/******************************************************************************
|
||||
* @file bayes_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _BAYES_FUNCTIONS_F16_H_
|
||||
#define _BAYES_FUNCTIONS_F16_H_
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#include "dsp/statistics_functions_f16.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
/**
|
||||
* @brief Instance structure for Naive Gaussian Bayesian estimator.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t vectorDimension; /**< Dimension of vector space */
|
||||
uint32_t numberOfClasses; /**< Number of different classes */
|
||||
const float16_t *theta; /**< Mean values for the Gaussians */
|
||||
const float16_t *sigma; /**< Variances for the Gaussians */
|
||||
const float16_t *classPriors; /**< Class prior probabilities */
|
||||
float16_t epsilon; /**< Additive value to variances */
|
||||
} arm_gaussian_naive_bayes_instance_f16;
|
||||
|
||||
/**
|
||||
* @brief Naive Gaussian Bayesian Estimator
|
||||
*
|
||||
* @param[in] S points to a naive bayes instance structure
|
||||
* @param[in] in points to the elements of the input vector.
|
||||
* @param[out] *pOutputProbabilities points to a buffer of length numberOfClasses containing estimated probabilities
|
||||
* @param[out] *pBufferB points to a temporary buffer of length numberOfClasses
|
||||
* @return The predicted class
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
uint32_t arm_gaussian_naive_bayes_predict_f16(const arm_gaussian_naive_bayes_instance_f16 *S,
|
||||
const float16_t * in,
|
||||
float16_t *pOutputProbabilities,
|
||||
float16_t *pBufferB);
|
||||
|
||||
#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _BAYES_FUNCTIONS_F16_H_ */
|
||||
|
|
@ -0,0 +1,322 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "core_cm4.h"
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
//#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
|
|
@ -0,0 +1,345 @@
|
|||
/******************************************************************************
|
||||
* @file complex_math_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _COMPLEX_MATH_FUNCTIONS_H_
|
||||
#define _COMPLEX_MATH_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
#include "dsp/fast_math_functions.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @defgroup groupCmplxMath Complex Math Functions
|
||||
* This set of functions operates on complex data vectors.
|
||||
* The data in the complex arrays is stored in an interleaved fashion
|
||||
* (real, imag, real, imag, ...).
|
||||
* In the API functions, the number of samples in a complex array refers
|
||||
* to the number of complex values; the array contains twice this number of
|
||||
* real values.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex conjugate.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
*/
|
||||
void arm_cmplx_conj_f32(
|
||||
const float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
/**
|
||||
* @brief Q31 complex conjugate.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
*/
|
||||
void arm_cmplx_conj_q31(
|
||||
const q31_t * pSrc,
|
||||
q31_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q15 complex conjugate.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
*/
|
||||
void arm_cmplx_conj_q15(
|
||||
const q15_t * pSrc,
|
||||
q15_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex magnitude squared
|
||||
* @param[in] pSrc points to the complex input vector
|
||||
* @param[out] pDst points to the real output vector
|
||||
* @param[in] numSamples number of complex samples in the input vector
|
||||
*/
|
||||
void arm_cmplx_mag_squared_f32(
|
||||
const float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex magnitude squared
|
||||
* @param[in] pSrc points to the complex input vector
|
||||
* @param[out] pDst points to the real output vector
|
||||
* @param[in] numSamples number of complex samples in the input vector
|
||||
*/
|
||||
void arm_cmplx_mag_squared_f64(
|
||||
const float64_t * pSrc,
|
||||
float64_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q31 complex magnitude squared
|
||||
* @param[in] pSrc points to the complex input vector
|
||||
* @param[out] pDst points to the real output vector
|
||||
* @param[in] numSamples number of complex samples in the input vector
|
||||
*/
|
||||
void arm_cmplx_mag_squared_q31(
|
||||
const q31_t * pSrc,
|
||||
q31_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q15 complex magnitude squared
|
||||
* @param[in] pSrc points to the complex input vector
|
||||
* @param[out] pDst points to the real output vector
|
||||
* @param[in] numSamples number of complex samples in the input vector
|
||||
*/
|
||||
void arm_cmplx_mag_squared_q15(
|
||||
const q15_t * pSrc,
|
||||
q15_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex magnitude
|
||||
* @param[in] pSrc points to the complex input vector
|
||||
* @param[out] pDst points to the real output vector
|
||||
* @param[in] numSamples number of complex samples in the input vector
|
||||
*/
|
||||
void arm_cmplx_mag_f32(
|
||||
const float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex magnitude
|
||||
* @param[in] pSrc points to the complex input vector
|
||||
* @param[out] pDst points to the real output vector
|
||||
* @param[in] numSamples number of complex samples in the input vector
|
||||
*/
|
||||
void arm_cmplx_mag_f64(
|
||||
const float64_t * pSrc,
|
||||
float64_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q31 complex magnitude
|
||||
* @param[in] pSrc points to the complex input vector
|
||||
* @param[out] pDst points to the real output vector
|
||||
* @param[in] numSamples number of complex samples in the input vector
|
||||
*/
|
||||
void arm_cmplx_mag_q31(
|
||||
const q31_t * pSrc,
|
||||
q31_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q15 complex magnitude
|
||||
* @param[in] pSrc points to the complex input vector
|
||||
* @param[out] pDst points to the real output vector
|
||||
* @param[in] numSamples number of complex samples in the input vector
|
||||
*/
|
||||
void arm_cmplx_mag_q15(
|
||||
const q15_t * pSrc,
|
||||
q15_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
/**
|
||||
* @brief Q15 complex magnitude
|
||||
* @param[in] pSrc points to the complex input vector
|
||||
* @param[out] pDst points to the real output vector
|
||||
* @param[in] numSamples number of complex samples in the input vector
|
||||
*/
|
||||
void arm_cmplx_mag_fast_q15(
|
||||
const q15_t * pSrc,
|
||||
q15_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q15 complex dot product
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
* @param[out] realResult real part of the result returned here
|
||||
* @param[out] imagResult imaginary part of the result returned here
|
||||
*/
|
||||
void arm_cmplx_dot_prod_q15(
|
||||
const q15_t * pSrcA,
|
||||
const q15_t * pSrcB,
|
||||
uint32_t numSamples,
|
||||
q31_t * realResult,
|
||||
q31_t * imagResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q31 complex dot product
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
* @param[out] realResult real part of the result returned here
|
||||
* @param[out] imagResult imaginary part of the result returned here
|
||||
*/
|
||||
void arm_cmplx_dot_prod_q31(
|
||||
const q31_t * pSrcA,
|
||||
const q31_t * pSrcB,
|
||||
uint32_t numSamples,
|
||||
q63_t * realResult,
|
||||
q63_t * imagResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex dot product
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
* @param[out] realResult real part of the result returned here
|
||||
* @param[out] imagResult imaginary part of the result returned here
|
||||
*/
|
||||
void arm_cmplx_dot_prod_f32(
|
||||
const float32_t * pSrcA,
|
||||
const float32_t * pSrcB,
|
||||
uint32_t numSamples,
|
||||
float32_t * realResult,
|
||||
float32_t * imagResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q15 complex-by-real multiplication
|
||||
* @param[in] pSrcCmplx points to the complex input vector
|
||||
* @param[in] pSrcReal points to the real input vector
|
||||
* @param[out] pCmplxDst points to the complex output vector
|
||||
* @param[in] numSamples number of samples in each vector
|
||||
*/
|
||||
void arm_cmplx_mult_real_q15(
|
||||
const q15_t * pSrcCmplx,
|
||||
const q15_t * pSrcReal,
|
||||
q15_t * pCmplxDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q31 complex-by-real multiplication
|
||||
* @param[in] pSrcCmplx points to the complex input vector
|
||||
* @param[in] pSrcReal points to the real input vector
|
||||
* @param[out] pCmplxDst points to the complex output vector
|
||||
* @param[in] numSamples number of samples in each vector
|
||||
*/
|
||||
void arm_cmplx_mult_real_q31(
|
||||
const q31_t * pSrcCmplx,
|
||||
const q31_t * pSrcReal,
|
||||
q31_t * pCmplxDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex-by-real multiplication
|
||||
* @param[in] pSrcCmplx points to the complex input vector
|
||||
* @param[in] pSrcReal points to the real input vector
|
||||
* @param[out] pCmplxDst points to the complex output vector
|
||||
* @param[in] numSamples number of samples in each vector
|
||||
*/
|
||||
void arm_cmplx_mult_real_f32(
|
||||
const float32_t * pSrcCmplx,
|
||||
const float32_t * pSrcReal,
|
||||
float32_t * pCmplxDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
/**
|
||||
* @brief Q15 complex-by-complex multiplication
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
*/
|
||||
void arm_cmplx_mult_cmplx_q15(
|
||||
const q15_t * pSrcA,
|
||||
const q15_t * pSrcB,
|
||||
q15_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q31 complex-by-complex multiplication
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
*/
|
||||
void arm_cmplx_mult_cmplx_q31(
|
||||
const q31_t * pSrcA,
|
||||
const q31_t * pSrcB,
|
||||
q31_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex-by-complex multiplication
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
*/
|
||||
void arm_cmplx_mult_cmplx_f32(
|
||||
const float32_t * pSrcA,
|
||||
const float32_t * pSrcB,
|
||||
float32_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex-by-complex multiplication
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
*/
|
||||
void arm_cmplx_mult_cmplx_f64(
|
||||
const float64_t * pSrcA,
|
||||
const float64_t * pSrcB,
|
||||
float64_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _COMPLEX_MATH_FUNCTIONS_H_ */
|
||||
|
|
@ -0,0 +1,123 @@
|
|||
/******************************************************************************
|
||||
* @file complex_math_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _COMPLEX_MATH_FUNCTIONS_F16_H_
|
||||
#define _COMPLEX_MATH_FUNCTIONS_F16_H_
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
#include "dsp/fast_math_functions_f16.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex conjugate.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
*/
|
||||
void arm_cmplx_conj_f16(
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex magnitude squared
|
||||
* @param[in] pSrc points to the complex input vector
|
||||
* @param[out] pDst points to the real output vector
|
||||
* @param[in] numSamples number of complex samples in the input vector
|
||||
*/
|
||||
void arm_cmplx_mag_squared_f16(
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex magnitude
|
||||
* @param[in] pSrc points to the complex input vector
|
||||
* @param[out] pDst points to the real output vector
|
||||
* @param[in] numSamples number of complex samples in the input vector
|
||||
*/
|
||||
void arm_cmplx_mag_f16(
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex dot product
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
* @param[out] realResult real part of the result returned here
|
||||
* @param[out] imagResult imaginary part of the result returned here
|
||||
*/
|
||||
void arm_cmplx_dot_prod_f16(
|
||||
const float16_t * pSrcA,
|
||||
const float16_t * pSrcB,
|
||||
uint32_t numSamples,
|
||||
float16_t * realResult,
|
||||
float16_t * imagResult);
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex-by-real multiplication
|
||||
* @param[in] pSrcCmplx points to the complex input vector
|
||||
* @param[in] pSrcReal points to the real input vector
|
||||
* @param[out] pCmplxDst points to the complex output vector
|
||||
* @param[in] numSamples number of samples in each vector
|
||||
*/
|
||||
void arm_cmplx_mult_real_f16(
|
||||
const float16_t * pSrcCmplx,
|
||||
const float16_t * pSrcReal,
|
||||
float16_t * pCmplxDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex-by-complex multiplication
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
*/
|
||||
void arm_cmplx_mult_cmplx_f16(
|
||||
const float16_t * pSrcA,
|
||||
const float16_t * pSrcB,
|
||||
float16_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _COMPLEX_MATH_FUNCTIONS_F16_H_ */
|
||||
|
|
@ -0,0 +1,791 @@
|
|||
/******************************************************************************
|
||||
* @file controller_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _CONTROLLER_FUNCTIONS_H_
|
||||
#define _CONTROLLER_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Macros required for SINE and COSINE Controller functions
|
||||
*/
|
||||
|
||||
#define CONTROLLER_Q31_SHIFT (32 - 9)
|
||||
/* 1.31(q31) Fixed value of 2/360 */
|
||||
/* -1 to +1 is divided into 360 values so total spacing is (2/360) */
|
||||
#define INPUT_SPACING 0xB60B61
|
||||
|
||||
/**
|
||||
* @defgroup groupController Controller Functions
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup groupController
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup SinCos
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Floating-point sin_cos function.
|
||||
* @param[in] theta input value in degrees
|
||||
* @param[out] pSinVal points to the processed sine output.
|
||||
* @param[out] pCosVal points to the processed cos output.
|
||||
*/
|
||||
void arm_sin_cos_f32(
|
||||
float32_t theta,
|
||||
float32_t * pSinVal,
|
||||
float32_t * pCosVal);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q31 sin_cos function.
|
||||
* @param[in] theta scaled input value in degrees
|
||||
* @param[out] pSinVal points to the processed sine output.
|
||||
* @param[out] pCosVal points to the processed cosine output.
|
||||
*/
|
||||
void arm_sin_cos_q31(
|
||||
q31_t theta,
|
||||
q31_t * pSinVal,
|
||||
q31_t * pCosVal);
|
||||
|
||||
/**
|
||||
* @} end of SinCos group
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup groupController
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PID PID Motor Control
|
||||
*
|
||||
* A Proportional Integral Derivative (PID) controller is a generic feedback control
|
||||
* loop mechanism widely used in industrial control systems.
|
||||
* A PID controller is the most commonly used type of feedback controller.
|
||||
*
|
||||
* This set of functions implements (PID) controllers
|
||||
* for Q15, Q31, and floating-point data types. The functions operate on a single sample
|
||||
* of data and each call to the function returns a single processed value.
|
||||
* <code>S</code> points to an instance of the PID control data structure. <code>in</code>
|
||||
* is the input sample value. The functions return the output value.
|
||||
*
|
||||
* \par Algorithm:
|
||||
* <pre>
|
||||
* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
|
||||
* A0 = Kp + Ki + Kd
|
||||
* A1 = (-Kp ) - (2 * Kd )
|
||||
* A2 = Kd
|
||||
* </pre>
|
||||
*
|
||||
* \par
|
||||
* where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
|
||||
*
|
||||
* \par
|
||||
* \image html PID.gif "Proportional Integral Derivative Controller"
|
||||
*
|
||||
* \par
|
||||
* The PID controller calculates an "error" value as the difference between
|
||||
* the measured output and the reference input.
|
||||
* The controller attempts to minimize the error by adjusting the process control inputs.
|
||||
* The proportional value determines the reaction to the current error,
|
||||
* the integral value determines the reaction based on the sum of recent errors,
|
||||
* and the derivative value determines the reaction based on the rate at which the error has been changing.
|
||||
*
|
||||
* \par Instance Structure
|
||||
* The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
|
||||
* A separate instance structure must be defined for each PID Controller.
|
||||
* There are separate instance structure declarations for each of the 3 supported data types.
|
||||
*
|
||||
* \par Reset Functions
|
||||
* There is also an associated reset function for each data type which clears the state array.
|
||||
*
|
||||
* \par Initialization Functions
|
||||
* There is also an associated initialization function for each data type.
|
||||
* The initialization function performs the following operations:
|
||||
* - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
|
||||
* - Zeros out the values in the state buffer.
|
||||
*
|
||||
* \par
|
||||
* Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
|
||||
*
|
||||
* \par Fixed-Point Behavior
|
||||
* Care must be taken when using the fixed-point versions of the PID Controller functions.
|
||||
* In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
|
||||
* Refer to the function specific documentation below for usage guidelines.
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Q15 PID Control.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
|
||||
#if !defined (ARM_MATH_DSP)
|
||||
q15_t A1; /**< The derived gain A1 = -Kp - 2Kd */
|
||||
q15_t A2; /**< The derived gain A1 = Kd. */
|
||||
#else
|
||||
q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
|
||||
#endif
|
||||
q15_t state[3]; /**< The state array of length 3. */
|
||||
q15_t Kp; /**< The proportional gain. */
|
||||
q15_t Ki; /**< The integral gain. */
|
||||
q15_t Kd; /**< The derivative gain. */
|
||||
} arm_pid_instance_q15;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Q31 PID Control.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
|
||||
q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
|
||||
q31_t A2; /**< The derived gain, A2 = Kd . */
|
||||
q31_t state[3]; /**< The state array of length 3. */
|
||||
q31_t Kp; /**< The proportional gain. */
|
||||
q31_t Ki; /**< The integral gain. */
|
||||
q31_t Kd; /**< The derivative gain. */
|
||||
} arm_pid_instance_q31;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point PID Control.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
|
||||
float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
|
||||
float32_t A2; /**< The derived gain, A2 = Kd . */
|
||||
float32_t state[3]; /**< The state array of length 3. */
|
||||
float32_t Kp; /**< The proportional gain. */
|
||||
float32_t Ki; /**< The integral gain. */
|
||||
float32_t Kd; /**< The derivative gain. */
|
||||
} arm_pid_instance_f32;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initialization function for the floating-point PID Control.
|
||||
* @param[in,out] S points to an instance of the PID structure.
|
||||
* @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
|
||||
*/
|
||||
void arm_pid_init_f32(
|
||||
arm_pid_instance_f32 * S,
|
||||
int32_t resetStateFlag);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Reset function for the floating-point PID Control.
|
||||
* @param[in,out] S is an instance of the floating-point PID Control structure
|
||||
*/
|
||||
void arm_pid_reset_f32(
|
||||
arm_pid_instance_f32 * S);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initialization function for the Q31 PID Control.
|
||||
* @param[in,out] S points to an instance of the Q15 PID structure.
|
||||
* @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
|
||||
*/
|
||||
void arm_pid_init_q31(
|
||||
arm_pid_instance_q31 * S,
|
||||
int32_t resetStateFlag);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Reset function for the Q31 PID Control.
|
||||
* @param[in,out] S points to an instance of the Q31 PID Control structure
|
||||
*/
|
||||
|
||||
void arm_pid_reset_q31(
|
||||
arm_pid_instance_q31 * S);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initialization function for the Q15 PID Control.
|
||||
* @param[in,out] S points to an instance of the Q15 PID structure.
|
||||
* @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
|
||||
*/
|
||||
void arm_pid_init_q15(
|
||||
arm_pid_instance_q15 * S,
|
||||
int32_t resetStateFlag);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Reset function for the Q15 PID Control.
|
||||
* @param[in,out] S points to an instance of the q15 PID Control structure
|
||||
*/
|
||||
void arm_pid_reset_q15(
|
||||
arm_pid_instance_q15 * S);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @addtogroup PID
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Process function for the floating-point PID Control.
|
||||
* @param[in,out] S is an instance of the floating-point PID Control structure
|
||||
* @param[in] in input sample to process
|
||||
* @return processed output sample.
|
||||
*/
|
||||
__STATIC_FORCEINLINE float32_t arm_pid_f32(
|
||||
arm_pid_instance_f32 * S,
|
||||
float32_t in)
|
||||
{
|
||||
float32_t out;
|
||||
|
||||
/* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
|
||||
out = (S->A0 * in) +
|
||||
(S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
|
||||
|
||||
/* Update state */
|
||||
S->state[1] = S->state[0];
|
||||
S->state[0] = in;
|
||||
S->state[2] = out;
|
||||
|
||||
/* return to application */
|
||||
return (out);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
@brief Process function for the Q31 PID Control.
|
||||
@param[in,out] S points to an instance of the Q31 PID Control structure
|
||||
@param[in] in input sample to process
|
||||
@return processed output sample.
|
||||
|
||||
\par Scaling and Overflow Behavior
|
||||
The function is implemented using an internal 64-bit accumulator.
|
||||
The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
|
||||
Thus, if the accumulator result overflows it wraps around rather than clip.
|
||||
In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
|
||||
After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
|
||||
*/
|
||||
__STATIC_FORCEINLINE q31_t arm_pid_q31(
|
||||
arm_pid_instance_q31 * S,
|
||||
q31_t in)
|
||||
{
|
||||
q63_t acc;
|
||||
q31_t out;
|
||||
|
||||
/* acc = A0 * x[n] */
|
||||
acc = (q63_t) S->A0 * in;
|
||||
|
||||
/* acc += A1 * x[n-1] */
|
||||
acc += (q63_t) S->A1 * S->state[0];
|
||||
|
||||
/* acc += A2 * x[n-2] */
|
||||
acc += (q63_t) S->A2 * S->state[1];
|
||||
|
||||
/* convert output to 1.31 format to add y[n-1] */
|
||||
out = (q31_t) (acc >> 31U);
|
||||
|
||||
/* out += y[n-1] */
|
||||
out += S->state[2];
|
||||
|
||||
/* Update state */
|
||||
S->state[1] = S->state[0];
|
||||
S->state[0] = in;
|
||||
S->state[2] = out;
|
||||
|
||||
/* return to application */
|
||||
return (out);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
@brief Process function for the Q15 PID Control.
|
||||
@param[in,out] S points to an instance of the Q15 PID Control structure
|
||||
@param[in] in input sample to process
|
||||
@return processed output sample.
|
||||
|
||||
\par Scaling and Overflow Behavior
|
||||
The function is implemented using a 64-bit internal accumulator.
|
||||
Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
|
||||
The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
|
||||
There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
|
||||
After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
|
||||
Lastly, the accumulator is saturated to yield a result in 1.15 format.
|
||||
*/
|
||||
__STATIC_FORCEINLINE q15_t arm_pid_q15(
|
||||
arm_pid_instance_q15 * S,
|
||||
q15_t in)
|
||||
{
|
||||
q63_t acc;
|
||||
q15_t out;
|
||||
|
||||
#if defined (ARM_MATH_DSP)
|
||||
/* Implementation of PID controller */
|
||||
|
||||
/* acc = A0 * x[n] */
|
||||
acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
|
||||
|
||||
/* acc += A1 * x[n-1] + A2 * x[n-2] */
|
||||
acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc);
|
||||
#else
|
||||
/* acc = A0 * x[n] */
|
||||
acc = ((q31_t) S->A0) * in;
|
||||
|
||||
/* acc += A1 * x[n-1] + A2 * x[n-2] */
|
||||
acc += (q31_t) S->A1 * S->state[0];
|
||||
acc += (q31_t) S->A2 * S->state[1];
|
||||
#endif
|
||||
|
||||
/* acc += y[n-1] */
|
||||
acc += (q31_t) S->state[2] << 15;
|
||||
|
||||
/* saturate the output */
|
||||
out = (q15_t) (__SSAT((q31_t)(acc >> 15), 16));
|
||||
|
||||
/* Update state */
|
||||
S->state[1] = S->state[0];
|
||||
S->state[0] = in;
|
||||
S->state[2] = out;
|
||||
|
||||
/* return to application */
|
||||
return (out);
|
||||
}
|
||||
|
||||
/**
|
||||
* @} end of PID group
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup groupController
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup park Vector Park Transform
|
||||
*
|
||||
* Forward Park transform converts the input two-coordinate vector to flux and torque components.
|
||||
* The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
|
||||
* from the stationary to the moving reference frame and control the spatial relationship between
|
||||
* the stator vector current and rotor flux vector.
|
||||
* If we consider the d axis aligned with the rotor flux, the diagram below shows the
|
||||
* current vector and the relationship from the two reference frames:
|
||||
* \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
|
||||
*
|
||||
* The function operates on a single sample of data and each call to the function returns the processed output.
|
||||
* The library provides separate functions for Q31 and floating-point data types.
|
||||
* \par Algorithm
|
||||
* \image html parkFormula.gif
|
||||
* where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
|
||||
* <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
|
||||
* cosine and sine values of theta (rotor flux position).
|
||||
* \par Fixed-Point Behavior
|
||||
* Care must be taken when using the Q31 version of the Park transform.
|
||||
* In particular, the overflow and saturation behavior of the accumulator used must be considered.
|
||||
* Refer to the function specific documentation below for usage guidelines.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup park
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Floating-point Park transform
|
||||
* @param[in] Ialpha input two-phase vector coordinate alpha
|
||||
* @param[in] Ibeta input two-phase vector coordinate beta
|
||||
* @param[out] pId points to output rotor reference frame d
|
||||
* @param[out] pIq points to output rotor reference frame q
|
||||
* @param[in] sinVal sine value of rotation angle theta
|
||||
* @param[in] cosVal cosine value of rotation angle theta
|
||||
* @return none
|
||||
*
|
||||
* The function implements the forward Park transform.
|
||||
*
|
||||
*/
|
||||
__STATIC_FORCEINLINE void arm_park_f32(
|
||||
float32_t Ialpha,
|
||||
float32_t Ibeta,
|
||||
float32_t * pId,
|
||||
float32_t * pIq,
|
||||
float32_t sinVal,
|
||||
float32_t cosVal)
|
||||
{
|
||||
/* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
|
||||
*pId = Ialpha * cosVal + Ibeta * sinVal;
|
||||
|
||||
/* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
|
||||
*pIq = -Ialpha * sinVal + Ibeta * cosVal;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
@brief Park transform for Q31 version
|
||||
@param[in] Ialpha input two-phase vector coordinate alpha
|
||||
@param[in] Ibeta input two-phase vector coordinate beta
|
||||
@param[out] pId points to output rotor reference frame d
|
||||
@param[out] pIq points to output rotor reference frame q
|
||||
@param[in] sinVal sine value of rotation angle theta
|
||||
@param[in] cosVal cosine value of rotation angle theta
|
||||
@return none
|
||||
|
||||
\par Scaling and Overflow Behavior
|
||||
The function is implemented using an internal 32-bit accumulator.
|
||||
The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
|
||||
There is saturation on the addition and subtraction, hence there is no risk of overflow.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void arm_park_q31(
|
||||
q31_t Ialpha,
|
||||
q31_t Ibeta,
|
||||
q31_t * pId,
|
||||
q31_t * pIq,
|
||||
q31_t sinVal,
|
||||
q31_t cosVal)
|
||||
{
|
||||
q31_t product1, product2; /* Temporary variables used to store intermediate results */
|
||||
q31_t product3, product4; /* Temporary variables used to store intermediate results */
|
||||
|
||||
/* Intermediate product is calculated by (Ialpha * cosVal) */
|
||||
product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
|
||||
|
||||
/* Intermediate product is calculated by (Ibeta * sinVal) */
|
||||
product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
|
||||
|
||||
|
||||
/* Intermediate product is calculated by (Ialpha * sinVal) */
|
||||
product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
|
||||
|
||||
/* Intermediate product is calculated by (Ibeta * cosVal) */
|
||||
product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
|
||||
|
||||
/* Calculate pId by adding the two intermediate products 1 and 2 */
|
||||
*pId = __QADD(product1, product2);
|
||||
|
||||
/* Calculate pIq by subtracting the two intermediate products 3 from 4 */
|
||||
*pIq = __QSUB(product4, product3);
|
||||
}
|
||||
|
||||
/**
|
||||
* @} end of park group
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup groupController
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup inv_park Vector Inverse Park transform
|
||||
* Inverse Park transform converts the input flux and torque components to two-coordinate vector.
|
||||
*
|
||||
* The function operates on a single sample of data and each call to the function returns the processed output.
|
||||
* The library provides separate functions for Q31 and floating-point data types.
|
||||
* \par Algorithm
|
||||
* \image html parkInvFormula.gif
|
||||
* where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
|
||||
* <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
|
||||
* cosine and sine values of theta (rotor flux position).
|
||||
* \par Fixed-Point Behavior
|
||||
* Care must be taken when using the Q31 version of the Park transform.
|
||||
* In particular, the overflow and saturation behavior of the accumulator used must be considered.
|
||||
* Refer to the function specific documentation below for usage guidelines.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup inv_park
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Floating-point Inverse Park transform
|
||||
* @param[in] Id input coordinate of rotor reference frame d
|
||||
* @param[in] Iq input coordinate of rotor reference frame q
|
||||
* @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
|
||||
* @param[out] pIbeta points to output two-phase orthogonal vector axis beta
|
||||
* @param[in] sinVal sine value of rotation angle theta
|
||||
* @param[in] cosVal cosine value of rotation angle theta
|
||||
* @return none
|
||||
*/
|
||||
__STATIC_FORCEINLINE void arm_inv_park_f32(
|
||||
float32_t Id,
|
||||
float32_t Iq,
|
||||
float32_t * pIalpha,
|
||||
float32_t * pIbeta,
|
||||
float32_t sinVal,
|
||||
float32_t cosVal)
|
||||
{
|
||||
/* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
|
||||
*pIalpha = Id * cosVal - Iq * sinVal;
|
||||
|
||||
/* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
|
||||
*pIbeta = Id * sinVal + Iq * cosVal;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
@brief Inverse Park transform for Q31 version
|
||||
@param[in] Id input coordinate of rotor reference frame d
|
||||
@param[in] Iq input coordinate of rotor reference frame q
|
||||
@param[out] pIalpha points to output two-phase orthogonal vector axis alpha
|
||||
@param[out] pIbeta points to output two-phase orthogonal vector axis beta
|
||||
@param[in] sinVal sine value of rotation angle theta
|
||||
@param[in] cosVal cosine value of rotation angle theta
|
||||
@return none
|
||||
|
||||
@par Scaling and Overflow Behavior
|
||||
The function is implemented using an internal 32-bit accumulator.
|
||||
The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
|
||||
There is saturation on the addition, hence there is no risk of overflow.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void arm_inv_park_q31(
|
||||
q31_t Id,
|
||||
q31_t Iq,
|
||||
q31_t * pIalpha,
|
||||
q31_t * pIbeta,
|
||||
q31_t sinVal,
|
||||
q31_t cosVal)
|
||||
{
|
||||
q31_t product1, product2; /* Temporary variables used to store intermediate results */
|
||||
q31_t product3, product4; /* Temporary variables used to store intermediate results */
|
||||
|
||||
/* Intermediate product is calculated by (Id * cosVal) */
|
||||
product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
|
||||
|
||||
/* Intermediate product is calculated by (Iq * sinVal) */
|
||||
product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
|
||||
|
||||
|
||||
/* Intermediate product is calculated by (Id * sinVal) */
|
||||
product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
|
||||
|
||||
/* Intermediate product is calculated by (Iq * cosVal) */
|
||||
product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
|
||||
|
||||
/* Calculate pIalpha by using the two intermediate products 1 and 2 */
|
||||
*pIalpha = __QSUB(product1, product2);
|
||||
|
||||
/* Calculate pIbeta by using the two intermediate products 3 and 4 */
|
||||
*pIbeta = __QADD(product4, product3);
|
||||
}
|
||||
|
||||
/**
|
||||
* @} end of Inverse park group
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup groupController
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup clarke Vector Clarke Transform
|
||||
* Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
|
||||
* Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
|
||||
* in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
|
||||
* When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
|
||||
* \image html clarke.gif Stator current space vector and its components in (a,b).
|
||||
* and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
|
||||
* can be calculated using only <code>Ia</code> and <code>Ib</code>.
|
||||
*
|
||||
* The function operates on a single sample of data and each call to the function returns the processed output.
|
||||
* The library provides separate functions for Q31 and floating-point data types.
|
||||
* \par Algorithm
|
||||
* \image html clarkeFormula.gif
|
||||
* where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
|
||||
* <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
|
||||
* \par Fixed-Point Behavior
|
||||
* Care must be taken when using the Q31 version of the Clarke transform.
|
||||
* In particular, the overflow and saturation behavior of the accumulator used must be considered.
|
||||
* Refer to the function specific documentation below for usage guidelines.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup clarke
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief Floating-point Clarke transform
|
||||
* @param[in] Ia input three-phase coordinate <code>a</code>
|
||||
* @param[in] Ib input three-phase coordinate <code>b</code>
|
||||
* @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
|
||||
* @param[out] pIbeta points to output two-phase orthogonal vector axis beta
|
||||
* @return none
|
||||
*/
|
||||
__STATIC_FORCEINLINE void arm_clarke_f32(
|
||||
float32_t Ia,
|
||||
float32_t Ib,
|
||||
float32_t * pIalpha,
|
||||
float32_t * pIbeta)
|
||||
{
|
||||
/* Calculate pIalpha using the equation, pIalpha = Ia */
|
||||
*pIalpha = Ia;
|
||||
|
||||
/* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
|
||||
*pIbeta = (0.57735026919f * Ia + 1.15470053838f * Ib);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
@brief Clarke transform for Q31 version
|
||||
@param[in] Ia input three-phase coordinate <code>a</code>
|
||||
@param[in] Ib input three-phase coordinate <code>b</code>
|
||||
@param[out] pIalpha points to output two-phase orthogonal vector axis alpha
|
||||
@param[out] pIbeta points to output two-phase orthogonal vector axis beta
|
||||
@return none
|
||||
|
||||
\par Scaling and Overflow Behavior
|
||||
The function is implemented using an internal 32-bit accumulator.
|
||||
The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
|
||||
There is saturation on the addition, hence there is no risk of overflow.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void arm_clarke_q31(
|
||||
q31_t Ia,
|
||||
q31_t Ib,
|
||||
q31_t * pIalpha,
|
||||
q31_t * pIbeta)
|
||||
{
|
||||
q31_t product1, product2; /* Temporary variables used to store intermediate results */
|
||||
|
||||
/* Calculating pIalpha from Ia by equation pIalpha = Ia */
|
||||
*pIalpha = Ia;
|
||||
|
||||
/* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
|
||||
product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
|
||||
|
||||
/* Intermediate product is calculated by (2/sqrt(3) * Ib) */
|
||||
product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
|
||||
|
||||
/* pIbeta is calculated by adding the intermediate products */
|
||||
*pIbeta = __QADD(product1, product2);
|
||||
}
|
||||
|
||||
/**
|
||||
* @} end of clarke group
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup groupController
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup inv_clarke Vector Inverse Clarke Transform
|
||||
* Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
|
||||
*
|
||||
* The function operates on a single sample of data and each call to the function returns the processed output.
|
||||
* The library provides separate functions for Q31 and floating-point data types.
|
||||
* \par Algorithm
|
||||
* \image html clarkeInvFormula.gif
|
||||
* where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
|
||||
* <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
|
||||
* \par Fixed-Point Behavior
|
||||
* Care must be taken when using the Q31 version of the Clarke transform.
|
||||
* In particular, the overflow and saturation behavior of the accumulator used must be considered.
|
||||
* Refer to the function specific documentation below for usage guidelines.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup inv_clarke
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Floating-point Inverse Clarke transform
|
||||
* @param[in] Ialpha input two-phase orthogonal vector axis alpha
|
||||
* @param[in] Ibeta input two-phase orthogonal vector axis beta
|
||||
* @param[out] pIa points to output three-phase coordinate <code>a</code>
|
||||
* @param[out] pIb points to output three-phase coordinate <code>b</code>
|
||||
* @return none
|
||||
*/
|
||||
__STATIC_FORCEINLINE void arm_inv_clarke_f32(
|
||||
float32_t Ialpha,
|
||||
float32_t Ibeta,
|
||||
float32_t * pIa,
|
||||
float32_t * pIb)
|
||||
{
|
||||
/* Calculating pIa from Ialpha by equation pIa = Ialpha */
|
||||
*pIa = Ialpha;
|
||||
|
||||
/* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
|
||||
*pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
@brief Inverse Clarke transform for Q31 version
|
||||
@param[in] Ialpha input two-phase orthogonal vector axis alpha
|
||||
@param[in] Ibeta input two-phase orthogonal vector axis beta
|
||||
@param[out] pIa points to output three-phase coordinate <code>a</code>
|
||||
@param[out] pIb points to output three-phase coordinate <code>b</code>
|
||||
@return none
|
||||
|
||||
\par Scaling and Overflow Behavior
|
||||
The function is implemented using an internal 32-bit accumulator.
|
||||
The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
|
||||
There is saturation on the subtraction, hence there is no risk of overflow.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void arm_inv_clarke_q31(
|
||||
q31_t Ialpha,
|
||||
q31_t Ibeta,
|
||||
q31_t * pIa,
|
||||
q31_t * pIb)
|
||||
{
|
||||
q31_t product1, product2; /* Temporary variables used to store intermediate results */
|
||||
|
||||
/* Calculating pIa from Ialpha by equation pIa = Ialpha */
|
||||
*pIa = Ialpha;
|
||||
|
||||
/* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
|
||||
product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
|
||||
|
||||
/* Intermediate product is calculated by (1/sqrt(3) * pIb) */
|
||||
product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
|
||||
|
||||
/* pIb is calculated by subtracting the products */
|
||||
*pIb = __QSUB(product2, product1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @} end of inv_clarke group
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _CONTROLLER_FUNCTIONS_H_ */
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/******************************************************************************
|
||||
* @file controller_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _CONTROLLER_FUNCTIONS_F16_H_
|
||||
#define _CONTROLLER_FUNCTIONS_F16_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _CONTROLLER_FUNCTIONS_F16_H_ */
|
||||
|
|
@ -0,0 +1,341 @@
|
|||
/******************************************************************************
|
||||
* @file distance_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _DISTANCE_FUNCTIONS_H_
|
||||
#define _DISTANCE_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#include "dsp/statistics_functions.h"
|
||||
#include "dsp/basic_math_functions.h"
|
||||
#include "dsp/fast_math_functions.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup groupDistance Distance functions
|
||||
*
|
||||
* Distance functions for use with clustering algorithms.
|
||||
* There are distance functions for float vectors and boolean vectors.
|
||||
*
|
||||
*/
|
||||
|
||||
/* 6.14 bug */
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) && (__ARMCC_VERSION < 6150001)
|
||||
|
||||
__attribute__((weak)) float __powisf2(float a, int b);
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Euclidean distance between two vectors
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Euclidean distance between two vectors
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float64_t arm_euclidean_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Bray-Curtis distance between two vectors
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Canberra distance between two vectors
|
||||
*
|
||||
* This function may divide by zero when samples pA[i] and pB[i] are both zero.
|
||||
* The result of the computation will be correct. So the division per zero may be
|
||||
* ignored.
|
||||
*
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Chebyshev distance between two vectors
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Chebyshev distance between two vectors
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
float64_t arm_chebyshev_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Cityblock (Manhattan) distance between two vectors
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Cityblock (Manhattan) distance between two vectors
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
float64_t arm_cityblock_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Correlation distance between two vectors
|
||||
*
|
||||
* The input vectors are modified in place !
|
||||
*
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
float32_t arm_correlation_distance_f32(float32_t *pA,float32_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Cosine distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float32_t arm_cosine_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Cosine distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float64_t arm_cosine_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Jensen-Shannon distance between two vectors
|
||||
*
|
||||
* This function is assuming that elements of second vector are > 0
|
||||
* and 0 only when the corresponding element of first vector is 0.
|
||||
* Otherwise the result of the computation does not make sense
|
||||
* and for speed reasons, the cases returning NaN or Infinity are not
|
||||
* managed.
|
||||
*
|
||||
* When the function is computing x log (x / y) with x 0 and y 0,
|
||||
* it will compute the right value (0) but a division per zero will occur
|
||||
* and shoudl be ignored in client code.
|
||||
*
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB,uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Minkowski distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] n Norm order (>= 2)
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
|
||||
float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Dice distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector of packed booleans
|
||||
* @param[in] pB Second vector of packed booleans
|
||||
* @param[in] order Distance order
|
||||
* @param[in] blockSize Number of samples
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
float32_t arm_dice_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
|
||||
|
||||
/**
|
||||
* @brief Hamming distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector of packed booleans
|
||||
* @param[in] pB Second vector of packed booleans
|
||||
* @param[in] numberOfBools Number of booleans
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float32_t arm_hamming_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
|
||||
|
||||
/**
|
||||
* @brief Jaccard distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector of packed booleans
|
||||
* @param[in] pB Second vector of packed booleans
|
||||
* @param[in] numberOfBools Number of booleans
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float32_t arm_jaccard_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
|
||||
|
||||
/**
|
||||
* @brief Kulsinski distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector of packed booleans
|
||||
* @param[in] pB Second vector of packed booleans
|
||||
* @param[in] numberOfBools Number of booleans
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float32_t arm_kulsinski_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
|
||||
|
||||
/**
|
||||
* @brief Roger Stanimoto distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector of packed booleans
|
||||
* @param[in] pB Second vector of packed booleans
|
||||
* @param[in] numberOfBools Number of booleans
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float32_t arm_rogerstanimoto_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
|
||||
|
||||
/**
|
||||
* @brief Russell-Rao distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector of packed booleans
|
||||
* @param[in] pB Second vector of packed booleans
|
||||
* @param[in] numberOfBools Number of booleans
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float32_t arm_russellrao_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
|
||||
|
||||
/**
|
||||
* @brief Sokal-Michener distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector of packed booleans
|
||||
* @param[in] pB Second vector of packed booleans
|
||||
* @param[in] numberOfBools Number of booleans
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float32_t arm_sokalmichener_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
|
||||
|
||||
/**
|
||||
* @brief Sokal-Sneath distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector of packed booleans
|
||||
* @param[in] pB Second vector of packed booleans
|
||||
* @param[in] numberOfBools Number of booleans
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float32_t arm_sokalsneath_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
|
||||
|
||||
/**
|
||||
* @brief Yule distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector of packed booleans
|
||||
* @param[in] pB Second vector of packed booleans
|
||||
* @param[in] numberOfBools Number of booleans
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float32_t arm_yule_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _DISTANCE_FUNCTIONS_H_ */
|
||||
|
|
@ -0,0 +1,180 @@
|
|||
/******************************************************************************
|
||||
* @file distance_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _DISTANCE_FUNCTIONS_F16_H_
|
||||
#define _DISTANCE_FUNCTIONS_F16_H_
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
/* 6.14 bug */
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) && (__ARMCC_VERSION < 6150001)
|
||||
/* Defined in minkowski_f32 */
|
||||
__attribute__((weak)) float __powisf2(float a, int b);
|
||||
#endif
|
||||
|
||||
#include "dsp/statistics_functions_f16.h"
|
||||
#include "dsp/basic_math_functions_f16.h"
|
||||
|
||||
#include "dsp/fast_math_functions_f16.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
/**
|
||||
* @brief Euclidean distance between two vectors
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float16_t arm_euclidean_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Bray-Curtis distance between two vectors
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
float16_t arm_braycurtis_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Canberra distance between two vectors
|
||||
*
|
||||
* This function may divide by zero when samples pA[i] and pB[i] are both zero.
|
||||
* The result of the computation will be correct. So the division per zero may be
|
||||
* ignored.
|
||||
*
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
float16_t arm_canberra_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Chebyshev distance between two vectors
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
float16_t arm_chebyshev_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Cityblock (Manhattan) distance between two vectors
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
float16_t arm_cityblock_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Correlation distance between two vectors
|
||||
*
|
||||
* The input vectors are modified in place !
|
||||
*
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
float16_t arm_correlation_distance_f16(float16_t *pA,float16_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Cosine distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float16_t arm_cosine_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Jensen-Shannon distance between two vectors
|
||||
*
|
||||
* This function is assuming that elements of second vector are > 0
|
||||
* and 0 only when the corresponding element of first vector is 0.
|
||||
* Otherwise the result of the computation does not make sense
|
||||
* and for speed reasons, the cases returning NaN or Infinity are not
|
||||
* managed.
|
||||
*
|
||||
* When the function is computing x log (x / y) with x 0 and y 0,
|
||||
* it will compute the right value (0) but a division per zero will occur
|
||||
* and shoudl be ignored in client code.
|
||||
*
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float16_t arm_jensenshannon_distance_f16(const float16_t *pA,const float16_t *pB,uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Minkowski distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] n Norm order (>= 2)
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
|
||||
float16_t arm_minkowski_distance_f16(const float16_t *pA,const float16_t *pB, int32_t order, uint32_t blockSize);
|
||||
|
||||
|
||||
#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _DISTANCE_FUNCTIONS_F16_H_ */
|
||||
|
|
@ -0,0 +1,389 @@
|
|||
/******************************************************************************
|
||||
* @file fast_math_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _FAST_MATH_FUNCTIONS_H_
|
||||
#define _FAST_MATH_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#include "dsp/basic_math_functions.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Macros required for SINE and COSINE Fast math approximations
|
||||
*/
|
||||
|
||||
#define FAST_MATH_TABLE_SIZE 512
|
||||
#define FAST_MATH_Q31_SHIFT (32 - 10)
|
||||
#define FAST_MATH_Q15_SHIFT (16 - 10)
|
||||
|
||||
#ifndef PI
|
||||
#define PI 3.14159265358979f
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup groupFastMath Fast Math Functions
|
||||
* This set of functions provides a fast approximation to sine, cosine, and square root.
|
||||
* As compared to most of the other functions in the CMSIS math library, the fast math functions
|
||||
* operate on individual values and not arrays.
|
||||
* There are separate functions for Q15, Q31, and floating-point data.
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup groupFastMath
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
@addtogroup sin
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Fast approximation to the trigonometric sine function for floating-point data.
|
||||
* @param[in] x input value in radians.
|
||||
* @return sin(x).
|
||||
*/
|
||||
float32_t arm_sin_f32(
|
||||
float32_t x);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Fast approximation to the trigonometric sine function for Q31 data.
|
||||
* @param[in] x Scaled input value in radians.
|
||||
* @return sin(x).
|
||||
*/
|
||||
q31_t arm_sin_q31(
|
||||
q31_t x);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Fast approximation to the trigonometric sine function for Q15 data.
|
||||
* @param[in] x Scaled input value in radians.
|
||||
* @return sin(x).
|
||||
*/
|
||||
q15_t arm_sin_q15(
|
||||
q15_t x);
|
||||
|
||||
/**
|
||||
@} end of sin group
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup cos
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Fast approximation to the trigonometric cosine function for floating-point data.
|
||||
* @param[in] x input value in radians.
|
||||
* @return cos(x).
|
||||
*/
|
||||
float32_t arm_cos_f32(
|
||||
float32_t x);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Fast approximation to the trigonometric cosine function for Q31 data.
|
||||
* @param[in] x Scaled input value in radians.
|
||||
* @return cos(x).
|
||||
*/
|
||||
q31_t arm_cos_q31(
|
||||
q31_t x);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Fast approximation to the trigonometric cosine function for Q15 data.
|
||||
* @param[in] x Scaled input value in radians.
|
||||
* @return cos(x).
|
||||
*/
|
||||
q15_t arm_cos_q15(
|
||||
q15_t x);
|
||||
|
||||
/**
|
||||
@} end of cos group
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
@brief Floating-point vector of log values.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[out] pDst points to the output vector
|
||||
@param[in] blockSize number of samples in each vector
|
||||
@return none
|
||||
*/
|
||||
void arm_vlog_f32(
|
||||
const float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
@brief Floating-point vector of log values.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[out] pDst points to the output vector
|
||||
@param[in] blockSize number of samples in each vector
|
||||
@return none
|
||||
*/
|
||||
void arm_vlog_f64(
|
||||
const float64_t * pSrc,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief q31 vector of log values.
|
||||
* @param[in] pSrc points to the input vector in q31
|
||||
* @param[out] pDst points to the output vector in q5.26
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_vlog_q31(const q31_t * pSrc,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief q15 vector of log values.
|
||||
* @param[in] pSrc points to the input vector in q15
|
||||
* @param[out] pDst points to the output vector in q4.11
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_vlog_q15(const q15_t * pSrc,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
@brief Floating-point vector of exp values.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[out] pDst points to the output vector
|
||||
@param[in] blockSize number of samples in each vector
|
||||
@return none
|
||||
*/
|
||||
void arm_vexp_f32(
|
||||
const float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
@brief Floating-point vector of exp values.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[out] pDst points to the output vector
|
||||
@param[in] blockSize number of samples in each vector
|
||||
@return none
|
||||
*/
|
||||
void arm_vexp_f64(
|
||||
const float64_t * pSrc,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup SQRT Square Root
|
||||
*
|
||||
* Computes the square root of a number.
|
||||
* There are separate functions for Q15, Q31, and floating-point data types.
|
||||
* The square root function is computed using the Newton-Raphson algorithm.
|
||||
* This is an iterative algorithm of the form:
|
||||
* <pre>
|
||||
* x1 = x0 - f(x0)/f'(x0)
|
||||
* </pre>
|
||||
* where <code>x1</code> is the current estimate,
|
||||
* <code>x0</code> is the previous estimate, and
|
||||
* <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
|
||||
* For the square root function, the algorithm reduces to:
|
||||
* <pre>
|
||||
* x0 = in/2 [initial guess]
|
||||
* x1 = 1/2 * ( x0 + in / x0) [each iteration]
|
||||
* </pre>
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @addtogroup SQRT
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
@brief Floating-point square root function.
|
||||
@param[in] in input value
|
||||
@param[out] pOut square root of input value
|
||||
@return execution status
|
||||
- \ref ARM_MATH_SUCCESS : input value is positive
|
||||
- \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
|
||||
*/
|
||||
__STATIC_FORCEINLINE arm_status arm_sqrt_f32(
|
||||
const float32_t in,
|
||||
float32_t * pOut)
|
||||
{
|
||||
if (in >= 0.0f)
|
||||
{
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
*pOut = __sqrtf(in);
|
||||
#else
|
||||
*pOut = sqrtf(in);
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
__ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
|
||||
#else
|
||||
*pOut = sqrtf(in);
|
||||
#endif
|
||||
|
||||
#else
|
||||
*pOut = sqrtf(in);
|
||||
#endif
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
else
|
||||
{
|
||||
*pOut = 0.0f;
|
||||
return (ARM_MATH_ARGUMENT_ERROR);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
@brief Q31 square root function.
|
||||
@param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF
|
||||
@param[out] pOut points to square root of input value
|
||||
@return execution status
|
||||
- \ref ARM_MATH_SUCCESS : input value is positive
|
||||
- \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
|
||||
*/
|
||||
arm_status arm_sqrt_q31(
|
||||
q31_t in,
|
||||
q31_t * pOut);
|
||||
|
||||
|
||||
/**
|
||||
@brief Q15 square root function.
|
||||
@param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF
|
||||
@param[out] pOut points to square root of input value
|
||||
@return execution status
|
||||
- \ref ARM_MATH_SUCCESS : input value is positive
|
||||
- \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
|
||||
*/
|
||||
arm_status arm_sqrt_q15(
|
||||
q15_t in,
|
||||
q15_t * pOut);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @} end of SQRT group
|
||||
*/
|
||||
|
||||
/**
|
||||
@brief Fixed point division
|
||||
@param[in] numerator Numerator
|
||||
@param[in] denominator Denominator
|
||||
@param[out] quotient Quotient value normalized between -1.0 and 1.0
|
||||
@param[out] shift Shift left value to get the unnormalized quotient
|
||||
@return error status
|
||||
|
||||
When dividing by 0, an error ARM_MATH_NANINF is returned. And the quotient is forced
|
||||
to the saturated negative or positive value.
|
||||
*/
|
||||
|
||||
arm_status arm_divide_q15(q15_t numerator,
|
||||
q15_t denominator,
|
||||
q15_t *quotient,
|
||||
int16_t *shift);
|
||||
|
||||
/**
|
||||
@brief Fixed point division
|
||||
@param[in] numerator Numerator
|
||||
@param[in] denominator Denominator
|
||||
@param[out] quotient Quotient value normalized between -1.0 and 1.0
|
||||
@param[out] shift Shift left value to get the unnormalized quotient
|
||||
@return error status
|
||||
|
||||
When dividing by 0, an error ARM_MATH_NANINF is returned. And the quotient is forced
|
||||
to the saturated negative or positive value.
|
||||
*/
|
||||
|
||||
arm_status arm_divide_q31(q31_t numerator,
|
||||
q31_t denominator,
|
||||
q31_t *quotient,
|
||||
int16_t *shift);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
@brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant.
|
||||
@param[in] y y coordinate
|
||||
@param[in] x x coordinate
|
||||
@param[out] result Result
|
||||
@return error status.
|
||||
*/
|
||||
arm_status arm_atan2_f32(float32_t y,float32_t x,float32_t *result);
|
||||
|
||||
|
||||
/**
|
||||
@brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant.
|
||||
@param[in] y y coordinate
|
||||
@param[in] x x coordinate
|
||||
@param[out] result Result in Q2.29
|
||||
@return error status.
|
||||
*/
|
||||
arm_status arm_atan2_q31(q31_t y,q31_t x,q31_t *result);
|
||||
|
||||
/**
|
||||
@brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant.
|
||||
@param[in] y y coordinate
|
||||
@param[in] x x coordinate
|
||||
@param[out] result Result in Q2.13
|
||||
@return error status.
|
||||
*/
|
||||
arm_status arm_atan2_q15(q15_t y,q15_t x,q15_t *result);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _FAST_MATH_FUNCTIONS_H_ */
|
||||
|
|
@ -0,0 +1,125 @@
|
|||
/******************************************************************************
|
||||
* @file fast_math_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _FAST_MATH_FUNCTIONS_F16_H_
|
||||
#define _FAST_MATH_FUNCTIONS_F16_H_
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
/* For sqrt_f32 */
|
||||
#include "dsp/fast_math_functions.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
/**
|
||||
* @addtogroup SQRT
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
@brief Floating-point square root function.
|
||||
@param[in] in input value
|
||||
@param[out] pOut square root of input value
|
||||
@return execution status
|
||||
- \ref ARM_MATH_SUCCESS : input value is positive
|
||||
- \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
|
||||
*/
|
||||
__STATIC_FORCEINLINE arm_status arm_sqrt_f16(
|
||||
float16_t in,
|
||||
float16_t * pOut)
|
||||
{
|
||||
float32_t r;
|
||||
arm_status status;
|
||||
status=arm_sqrt_f32((float32_t)in,&r);
|
||||
*pOut=(float16_t)r;
|
||||
return(status);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
@} end of SQRT group
|
||||
*/
|
||||
|
||||
/**
|
||||
@brief Floating-point vector of log values.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[out] pDst points to the output vector
|
||||
@param[in] blockSize number of samples in each vector
|
||||
@return none
|
||||
*/
|
||||
void arm_vlog_f16(
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
@brief Floating-point vector of exp values.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[out] pDst points to the output vector
|
||||
@param[in] blockSize number of samples in each vector
|
||||
@return none
|
||||
*/
|
||||
void arm_vexp_f16(
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
@brief Floating-point vector of inverse values.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[out] pDst points to the output vector
|
||||
@param[in] blockSize number of samples in each vector
|
||||
@return none
|
||||
*/
|
||||
void arm_vinverse_f16(
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
@brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant.
|
||||
@param[in] y y coordinate
|
||||
@param[in] x x coordinate
|
||||
@param[out] result Result
|
||||
@return error status.
|
||||
*/
|
||||
arm_status arm_atan2_f16(float16_t y,float16_t x,float16_t *result);
|
||||
|
||||
#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _FAST_MATH_FUNCTIONS_F16_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,237 @@
|
|||
/******************************************************************************
|
||||
* @file filtering_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _FILTERING_FUNCTIONS_F16_H_
|
||||
#define _FILTERING_FUNCTIONS_F16_H_
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point FIR filter.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t numTaps; /**< number of filter coefficients in the filter. */
|
||||
float16_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
|
||||
const float16_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
|
||||
} arm_fir_instance_f16;
|
||||
|
||||
/**
|
||||
* @brief Initialization function for the floating-point FIR filter.
|
||||
* @param[in,out] S points to an instance of the floating-point FIR filter structure.
|
||||
* @param[in] numTaps Number of filter coefficients in the filter.
|
||||
* @param[in] pCoeffs points to the filter coefficients.
|
||||
* @param[in] pState points to the state buffer.
|
||||
* @param[in] blockSize number of samples that are processed at a time.
|
||||
*/
|
||||
void arm_fir_init_f16(
|
||||
arm_fir_instance_f16 * S,
|
||||
uint16_t numTaps,
|
||||
const float16_t * pCoeffs,
|
||||
float16_t * pState,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Processing function for the floating-point FIR filter.
|
||||
* @param[in] S points to an instance of the floating-point FIR structure.
|
||||
* @param[in] pSrc points to the block of input data.
|
||||
* @param[out] pDst points to the block of output data.
|
||||
* @param[in] blockSize number of samples to process.
|
||||
*/
|
||||
void arm_fir_f16(
|
||||
const arm_fir_instance_f16 * S,
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point Biquad cascade filter.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
|
||||
float16_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
|
||||
const float16_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
|
||||
} arm_biquad_casd_df1_inst_f16;
|
||||
|
||||
#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
/**
|
||||
* @brief Instance structure for the modified Biquad coefs required by vectorized code.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
float16_t coeffs[12][8]; /**< Points to the array of modified coefficients. The array is of length 32. There is one per stage */
|
||||
} arm_biquad_mod_coef_f16;
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Processing function for the floating-point Biquad cascade filter.
|
||||
* @param[in] S points to an instance of the floating-point Biquad cascade structure.
|
||||
* @param[in] pSrc points to the block of input data.
|
||||
* @param[out] pDst points to the block of output data.
|
||||
* @param[in] blockSize number of samples to process.
|
||||
*/
|
||||
void arm_biquad_cascade_df1_f16(
|
||||
const arm_biquad_casd_df1_inst_f16 * S,
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
void arm_biquad_cascade_df1_mve_init_f16(
|
||||
arm_biquad_casd_df1_inst_f16 * S,
|
||||
uint8_t numStages,
|
||||
const float16_t * pCoeffs,
|
||||
arm_biquad_mod_coef_f16 * pCoeffsMod,
|
||||
float16_t * pState);
|
||||
#endif
|
||||
|
||||
void arm_biquad_cascade_df1_init_f16(
|
||||
arm_biquad_casd_df1_inst_f16 * S,
|
||||
uint8_t numStages,
|
||||
const float16_t * pCoeffs,
|
||||
float16_t * pState);
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
|
||||
float16_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
|
||||
const float16_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
|
||||
} arm_biquad_cascade_df2T_instance_f16;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
|
||||
float16_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
|
||||
const float16_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
|
||||
} arm_biquad_cascade_stereo_df2T_instance_f16;
|
||||
|
||||
/**
|
||||
* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
|
||||
* @param[in] S points to an instance of the filter data structure.
|
||||
* @param[in] pSrc points to the block of input data.
|
||||
* @param[out] pDst points to the block of output data
|
||||
* @param[in] blockSize number of samples to process.
|
||||
*/
|
||||
void arm_biquad_cascade_df2T_f16(
|
||||
const arm_biquad_cascade_df2T_instance_f16 * S,
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
|
||||
* @param[in] S points to an instance of the filter data structure.
|
||||
* @param[in] pSrc points to the block of input data.
|
||||
* @param[out] pDst points to the block of output data
|
||||
* @param[in] blockSize number of samples to process.
|
||||
*/
|
||||
void arm_biquad_cascade_stereo_df2T_f16(
|
||||
const arm_biquad_cascade_stereo_df2T_instance_f16 * S,
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
|
||||
* @param[in,out] S points to an instance of the filter data structure.
|
||||
* @param[in] numStages number of 2nd order stages in the filter.
|
||||
* @param[in] pCoeffs points to the filter coefficients.
|
||||
* @param[in] pState points to the state buffer.
|
||||
*/
|
||||
void arm_biquad_cascade_df2T_init_f16(
|
||||
arm_biquad_cascade_df2T_instance_f16 * S,
|
||||
uint8_t numStages,
|
||||
const float16_t * pCoeffs,
|
||||
float16_t * pState);
|
||||
|
||||
/**
|
||||
* @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
|
||||
* @param[in,out] S points to an instance of the filter data structure.
|
||||
* @param[in] numStages number of 2nd order stages in the filter.
|
||||
* @param[in] pCoeffs points to the filter coefficients.
|
||||
* @param[in] pState points to the state buffer.
|
||||
*/
|
||||
void arm_biquad_cascade_stereo_df2T_init_f16(
|
||||
arm_biquad_cascade_stereo_df2T_instance_f16 * S,
|
||||
uint8_t numStages,
|
||||
const float16_t * pCoeffs,
|
||||
float16_t * pState);
|
||||
|
||||
/**
|
||||
* @brief Correlation of floating-point sequences.
|
||||
* @param[in] pSrcA points to the first input sequence.
|
||||
* @param[in] srcALen length of the first input sequence.
|
||||
* @param[in] pSrcB points to the second input sequence.
|
||||
* @param[in] srcBLen length of the second input sequence.
|
||||
* @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
|
||||
*/
|
||||
void arm_correlate_f16(
|
||||
const float16_t * pSrcA,
|
||||
uint32_t srcALen,
|
||||
const float16_t * pSrcB,
|
||||
uint32_t srcBLen,
|
||||
float16_t * pDst);
|
||||
|
||||
|
||||
/**
|
||||
@brief Levinson Durbin
|
||||
@param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1)
|
||||
@param[out] a autoregressive coefficients
|
||||
@param[out] err prediction error (variance)
|
||||
@param[in] nbCoefs number of autoregressive coefficients
|
||||
@return none
|
||||
*/
|
||||
void arm_levinson_durbin_f16(const float16_t *phi,
|
||||
float16_t *a,
|
||||
float16_t *err,
|
||||
int nbCoefs);
|
||||
|
||||
#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _FILTERING_FUNCTIONS_F16_H_ */
|
||||
|
|
@ -0,0 +1,319 @@
|
|||
/******************************************************************************
|
||||
* @file interpolation_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _INTERPOLATION_FUNCTIONS_H_
|
||||
#define _INTERPOLATION_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup groupInterpolation Interpolation Functions
|
||||
* These functions perform 1- and 2-dimensional interpolation of data.
|
||||
* Linear interpolation is used for 1-dimensional data and
|
||||
* bilinear interpolation is used for 2-dimensional data.
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point Linear Interpolate function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t nValues; /**< nValues */
|
||||
float32_t x1; /**< x1 */
|
||||
float32_t xSpacing; /**< xSpacing */
|
||||
float32_t *pYData; /**< pointer to the table of Y values */
|
||||
} arm_linear_interp_instance_f32;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point bilinear interpolation function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t numRows; /**< number of rows in the data table. */
|
||||
uint16_t numCols; /**< number of columns in the data table. */
|
||||
float32_t *pData; /**< points to the data table. */
|
||||
} arm_bilinear_interp_instance_f32;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Q31 bilinear interpolation function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t numRows; /**< number of rows in the data table. */
|
||||
uint16_t numCols; /**< number of columns in the data table. */
|
||||
q31_t *pData; /**< points to the data table. */
|
||||
} arm_bilinear_interp_instance_q31;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Q15 bilinear interpolation function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t numRows; /**< number of rows in the data table. */
|
||||
uint16_t numCols; /**< number of columns in the data table. */
|
||||
q15_t *pData; /**< points to the data table. */
|
||||
} arm_bilinear_interp_instance_q15;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Q15 bilinear interpolation function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t numRows; /**< number of rows in the data table. */
|
||||
uint16_t numCols; /**< number of columns in the data table. */
|
||||
q7_t *pData; /**< points to the data table. */
|
||||
} arm_bilinear_interp_instance_q7;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Struct for specifying cubic spline type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ARM_SPLINE_NATURAL = 0, /**< Natural spline */
|
||||
ARM_SPLINE_PARABOLIC_RUNOUT = 1 /**< Parabolic runout spline */
|
||||
} arm_spline_type;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point cubic spline interpolation.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
arm_spline_type type; /**< Type (boundary conditions) */
|
||||
const float32_t * x; /**< x values */
|
||||
const float32_t * y; /**< y values */
|
||||
uint32_t n_x; /**< Number of known data points */
|
||||
float32_t * coeffs; /**< Coefficients buffer (b,c, and d) */
|
||||
} arm_spline_instance_f32;
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup groupInterpolation
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup SplineInterpolate
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Processing function for the floating-point cubic spline interpolation.
|
||||
* @param[in] S points to an instance of the floating-point spline structure.
|
||||
* @param[in] xq points to the x values ot the interpolated data points.
|
||||
* @param[out] pDst points to the block of output data.
|
||||
* @param[in] blockSize number of samples of output data.
|
||||
*/
|
||||
void arm_spline_f32(
|
||||
arm_spline_instance_f32 * S,
|
||||
const float32_t * xq,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Initialization function for the floating-point cubic spline interpolation.
|
||||
* @param[in,out] S points to an instance of the floating-point spline structure.
|
||||
* @param[in] type type of cubic spline interpolation (boundary conditions)
|
||||
* @param[in] x points to the x values of the known data points.
|
||||
* @param[in] y points to the y values of the known data points.
|
||||
* @param[in] n number of known data points.
|
||||
* @param[in] coeffs coefficients array for b, c, and d
|
||||
* @param[in] tempBuffer buffer array for internal computations
|
||||
*/
|
||||
void arm_spline_init_f32(
|
||||
arm_spline_instance_f32 * S,
|
||||
arm_spline_type type,
|
||||
const float32_t * x,
|
||||
const float32_t * y,
|
||||
uint32_t n,
|
||||
float32_t * coeffs,
|
||||
float32_t * tempBuffer);
|
||||
|
||||
|
||||
/**
|
||||
* @} end of SplineInterpolate group
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @addtogroup LinearInterpolate
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Process function for the floating-point Linear Interpolation Function.
|
||||
* @param[in,out] S is an instance of the floating-point Linear Interpolation structure
|
||||
* @param[in] x input sample to process
|
||||
* @return y processed output sample.
|
||||
*
|
||||
*/
|
||||
float32_t arm_linear_interp_f32(
|
||||
arm_linear_interp_instance_f32 * S,
|
||||
float32_t x);
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief Process function for the Q31 Linear Interpolation Function.
|
||||
* @param[in] pYData pointer to Q31 Linear Interpolation table
|
||||
* @param[in] x input sample to process
|
||||
* @param[in] nValues number of table values
|
||||
* @return y processed output sample.
|
||||
*
|
||||
* \par
|
||||
* Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
|
||||
* This function can support maximum of table size 2^12.
|
||||
*
|
||||
*/
|
||||
q31_t arm_linear_interp_q31(
|
||||
const q31_t * pYData,
|
||||
q31_t x,
|
||||
uint32_t nValues);
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief Process function for the Q15 Linear Interpolation Function.
|
||||
* @param[in] pYData pointer to Q15 Linear Interpolation table
|
||||
* @param[in] x input sample to process
|
||||
* @param[in] nValues number of table values
|
||||
* @return y processed output sample.
|
||||
*
|
||||
* \par
|
||||
* Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
|
||||
* This function can support maximum of table size 2^12.
|
||||
*
|
||||
*/
|
||||
q15_t arm_linear_interp_q15(
|
||||
const q15_t * pYData,
|
||||
q31_t x,
|
||||
uint32_t nValues);
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief Process function for the Q7 Linear Interpolation Function.
|
||||
* @param[in] pYData pointer to Q7 Linear Interpolation table
|
||||
* @param[in] x input sample to process
|
||||
* @param[in] nValues number of table values
|
||||
* @return y processed output sample.
|
||||
*
|
||||
* \par
|
||||
* Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
|
||||
* This function can support maximum of table size 2^12.
|
||||
*/
|
||||
q7_t arm_linear_interp_q7(
|
||||
const q7_t * pYData,
|
||||
q31_t x,
|
||||
uint32_t nValues);
|
||||
|
||||
/**
|
||||
* @} end of LinearInterpolate group
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup groupInterpolation
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @addtogroup BilinearInterpolate
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Floating-point bilinear interpolation.
|
||||
* @param[in,out] S points to an instance of the interpolation structure.
|
||||
* @param[in] X interpolation coordinate.
|
||||
* @param[in] Y interpolation coordinate.
|
||||
* @return out interpolated value.
|
||||
*/
|
||||
float32_t arm_bilinear_interp_f32(
|
||||
const arm_bilinear_interp_instance_f32 * S,
|
||||
float32_t X,
|
||||
float32_t Y);
|
||||
|
||||
/**
|
||||
* @brief Q31 bilinear interpolation.
|
||||
* @param[in,out] S points to an instance of the interpolation structure.
|
||||
* @param[in] X interpolation coordinate in 12.20 format.
|
||||
* @param[in] Y interpolation coordinate in 12.20 format.
|
||||
* @return out interpolated value.
|
||||
*/
|
||||
q31_t arm_bilinear_interp_q31(
|
||||
arm_bilinear_interp_instance_q31 * S,
|
||||
q31_t X,
|
||||
q31_t Y);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q15 bilinear interpolation.
|
||||
* @param[in,out] S points to an instance of the interpolation structure.
|
||||
* @param[in] X interpolation coordinate in 12.20 format.
|
||||
* @param[in] Y interpolation coordinate in 12.20 format.
|
||||
* @return out interpolated value.
|
||||
*/
|
||||
q15_t arm_bilinear_interp_q15(
|
||||
arm_bilinear_interp_instance_q15 * S,
|
||||
q31_t X,
|
||||
q31_t Y);
|
||||
|
||||
/**
|
||||
* @brief Q7 bilinear interpolation.
|
||||
* @param[in,out] S points to an instance of the interpolation structure.
|
||||
* @param[in] X interpolation coordinate in 12.20 format.
|
||||
* @param[in] Y interpolation coordinate in 12.20 format.
|
||||
* @return out interpolated value.
|
||||
*/
|
||||
q7_t arm_bilinear_interp_q7(
|
||||
arm_bilinear_interp_instance_q7 * S,
|
||||
q31_t X,
|
||||
q31_t Y);
|
||||
/**
|
||||
* @} end of BilinearInterpolate group
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _INTERPOLATION_FUNCTIONS_H_ */
|
||||
|
|
@ -0,0 +1,107 @@
|
|||
/******************************************************************************
|
||||
* @file interpolation_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _INTERPOLATION_FUNCTIONS_F16_H_
|
||||
#define _INTERPOLATION_FUNCTIONS_F16_H_
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t nValues; /**< nValues */
|
||||
float16_t x1; /**< x1 */
|
||||
float16_t xSpacing; /**< xSpacing */
|
||||
float16_t *pYData; /**< pointer to the table of Y values */
|
||||
} arm_linear_interp_instance_f16;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point bilinear interpolation function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t numRows;/**< number of rows in the data table. */
|
||||
uint16_t numCols;/**< number of columns in the data table. */
|
||||
float16_t *pData; /**< points to the data table. */
|
||||
} arm_bilinear_interp_instance_f16;
|
||||
|
||||
/**
|
||||
* @addtogroup LinearInterpolate
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Process function for the floating-point Linear Interpolation Function.
|
||||
* @param[in,out] S is an instance of the floating-point Linear Interpolation structure
|
||||
* @param[in] x input sample to process
|
||||
* @return y processed output sample.
|
||||
*
|
||||
*/
|
||||
float16_t arm_linear_interp_f16(
|
||||
arm_linear_interp_instance_f16 * S,
|
||||
float16_t x);
|
||||
|
||||
/**
|
||||
* @} end of LinearInterpolate group
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup BilinearInterpolate
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Floating-point bilinear interpolation.
|
||||
* @param[in,out] S points to an instance of the interpolation structure.
|
||||
* @param[in] X interpolation coordinate.
|
||||
* @param[in] Y interpolation coordinate.
|
||||
* @return out interpolated value.
|
||||
*/
|
||||
float16_t arm_bilinear_interp_f16(
|
||||
const arm_bilinear_interp_instance_f16 * S,
|
||||
float16_t X,
|
||||
float16_t Y);
|
||||
|
||||
|
||||
/**
|
||||
* @} end of BilinearInterpolate group
|
||||
*/
|
||||
#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _INTERPOLATION_FUNCTIONS_F16_H_ */
|
||||
|
|
@ -0,0 +1,757 @@
|
|||
/******************************************************************************
|
||||
* @file matrix_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MATRIX_FUNCTIONS_H_
|
||||
#define _MATRIX_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @defgroup groupMatrix Matrix Functions
|
||||
*
|
||||
* This set of functions provides basic matrix math operations.
|
||||
* The functions operate on matrix data structures. For example,
|
||||
* the type
|
||||
* definition for the floating-point matrix structure is shown
|
||||
* below:
|
||||
* <pre>
|
||||
* typedef struct
|
||||
* {
|
||||
* uint16_t numRows; // number of rows of the matrix.
|
||||
* uint16_t numCols; // number of columns of the matrix.
|
||||
* float32_t *pData; // points to the data of the matrix.
|
||||
* } arm_matrix_instance_f32;
|
||||
* </pre>
|
||||
* There are similar definitions for Q15 and Q31 data types.
|
||||
*
|
||||
* The structure specifies the size of the matrix and then points to
|
||||
* an array of data. The array is of size <code>numRows X numCols</code>
|
||||
* and the values are arranged in row order. That is, the
|
||||
* matrix element (i, j) is stored at:
|
||||
* <pre>
|
||||
* pData[i*numCols + j]
|
||||
* </pre>
|
||||
*
|
||||
* \par Init Functions
|
||||
* There is an associated initialization function for each type of matrix
|
||||
* data structure.
|
||||
* The initialization function sets the values of the internal structure fields.
|
||||
* Refer to \ref arm_mat_init_f32(), \ref arm_mat_init_q31() and \ref arm_mat_init_q15()
|
||||
* for floating-point, Q31 and Q15 types, respectively.
|
||||
*
|
||||
* \par
|
||||
* Use of the initialization function is optional. However, if initialization function is used
|
||||
* then the instance structure cannot be placed into a const data section.
|
||||
* To place the instance structure in a const data
|
||||
* section, manually initialize the data structure. For example:
|
||||
* <pre>
|
||||
* <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
|
||||
* <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
|
||||
* <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
|
||||
* </pre>
|
||||
* where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
|
||||
* specifies the number of columns, and <code>pData</code> points to the
|
||||
* data array.
|
||||
*
|
||||
* \par Size Checking
|
||||
* By default all of the matrix functions perform size checking on the input and
|
||||
* output matrices. For example, the matrix addition function verifies that the
|
||||
* two input matrices and the output matrix all have the same number of rows and
|
||||
* columns. If the size check fails the functions return:
|
||||
* <pre>
|
||||
* ARM_MATH_SIZE_MISMATCH
|
||||
* </pre>
|
||||
* Otherwise the functions return
|
||||
* <pre>
|
||||
* ARM_MATH_SUCCESS
|
||||
* </pre>
|
||||
* There is some overhead associated with this matrix size checking.
|
||||
* The matrix size checking is enabled via the \#define
|
||||
* <pre>
|
||||
* ARM_MATH_MATRIX_CHECK
|
||||
* </pre>
|
||||
* within the library project settings. By default this macro is defined
|
||||
* and size checking is enabled. By changing the project settings and
|
||||
* undefining this macro size checking is eliminated and the functions
|
||||
* run a bit faster. With size checking disabled the functions always
|
||||
* return <code>ARM_MATH_SUCCESS</code>.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point matrix structure.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t numRows; /**< number of rows of the matrix. */
|
||||
uint16_t numCols; /**< number of columns of the matrix. */
|
||||
float32_t *pData; /**< points to the data of the matrix. */
|
||||
} arm_matrix_instance_f32;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point matrix structure.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t numRows; /**< number of rows of the matrix. */
|
||||
uint16_t numCols; /**< number of columns of the matrix. */
|
||||
float64_t *pData; /**< points to the data of the matrix. */
|
||||
} arm_matrix_instance_f64;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Q7 matrix structure.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t numRows; /**< number of rows of the matrix. */
|
||||
uint16_t numCols; /**< number of columns of the matrix. */
|
||||
q7_t *pData; /**< points to the data of the matrix. */
|
||||
} arm_matrix_instance_q7;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Q15 matrix structure.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t numRows; /**< number of rows of the matrix. */
|
||||
uint16_t numCols; /**< number of columns of the matrix. */
|
||||
q15_t *pData; /**< points to the data of the matrix. */
|
||||
} arm_matrix_instance_q15;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Q31 matrix structure.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t numRows; /**< number of rows of the matrix. */
|
||||
uint16_t numCols; /**< number of columns of the matrix. */
|
||||
q31_t *pData; /**< points to the data of the matrix. */
|
||||
} arm_matrix_instance_q31;
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix addition.
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_add_f32(
|
||||
const arm_matrix_instance_f32 * pSrcA,
|
||||
const arm_matrix_instance_f32 * pSrcB,
|
||||
arm_matrix_instance_f32 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q15 matrix addition.
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_add_q15(
|
||||
const arm_matrix_instance_q15 * pSrcA,
|
||||
const arm_matrix_instance_q15 * pSrcB,
|
||||
arm_matrix_instance_q15 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q31 matrix addition.
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_add_q31(
|
||||
const arm_matrix_instance_q31 * pSrcA,
|
||||
const arm_matrix_instance_q31 * pSrcB,
|
||||
arm_matrix_instance_q31 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point, complex, matrix multiplication.
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_cmplx_mult_f32(
|
||||
const arm_matrix_instance_f32 * pSrcA,
|
||||
const arm_matrix_instance_f32 * pSrcB,
|
||||
arm_matrix_instance_f32 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q15, complex, matrix multiplication.
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_cmplx_mult_q15(
|
||||
const arm_matrix_instance_q15 * pSrcA,
|
||||
const arm_matrix_instance_q15 * pSrcB,
|
||||
arm_matrix_instance_q15 * pDst,
|
||||
q15_t * pScratch);
|
||||
|
||||
/**
|
||||
* @brief Q31, complex, matrix multiplication.
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_cmplx_mult_q31(
|
||||
const arm_matrix_instance_q31 * pSrcA,
|
||||
const arm_matrix_instance_q31 * pSrcB,
|
||||
arm_matrix_instance_q31 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix transpose.
|
||||
* @param[in] pSrc points to the input matrix
|
||||
* @param[out] pDst points to the output matrix
|
||||
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
|
||||
* or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_trans_f32(
|
||||
const arm_matrix_instance_f32 * pSrc,
|
||||
arm_matrix_instance_f32 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix transpose.
|
||||
* @param[in] pSrc points to the input matrix
|
||||
* @param[out] pDst points to the output matrix
|
||||
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
|
||||
* or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_trans_f64(
|
||||
const arm_matrix_instance_f64 * pSrc,
|
||||
arm_matrix_instance_f64 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex matrix transpose.
|
||||
* @param[in] pSrc points to the input matrix
|
||||
* @param[out] pDst points to the output matrix
|
||||
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
|
||||
* or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_cmplx_trans_f32(
|
||||
const arm_matrix_instance_f32 * pSrc,
|
||||
arm_matrix_instance_f32 * pDst);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q15 matrix transpose.
|
||||
* @param[in] pSrc points to the input matrix
|
||||
* @param[out] pDst points to the output matrix
|
||||
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
|
||||
* or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_trans_q15(
|
||||
const arm_matrix_instance_q15 * pSrc,
|
||||
arm_matrix_instance_q15 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q15 complex matrix transpose.
|
||||
* @param[in] pSrc points to the input matrix
|
||||
* @param[out] pDst points to the output matrix
|
||||
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
|
||||
* or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_cmplx_trans_q15(
|
||||
const arm_matrix_instance_q15 * pSrc,
|
||||
arm_matrix_instance_q15 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q7 matrix transpose.
|
||||
* @param[in] pSrc points to the input matrix
|
||||
* @param[out] pDst points to the output matrix
|
||||
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
|
||||
* or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_trans_q7(
|
||||
const arm_matrix_instance_q7 * pSrc,
|
||||
arm_matrix_instance_q7 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q31 matrix transpose.
|
||||
* @param[in] pSrc points to the input matrix
|
||||
* @param[out] pDst points to the output matrix
|
||||
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
|
||||
* or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_trans_q31(
|
||||
const arm_matrix_instance_q31 * pSrc,
|
||||
arm_matrix_instance_q31 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q31 complex matrix transpose.
|
||||
* @param[in] pSrc points to the input matrix
|
||||
* @param[out] pDst points to the output matrix
|
||||
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
|
||||
* or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_cmplx_trans_q31(
|
||||
const arm_matrix_instance_q31 * pSrc,
|
||||
arm_matrix_instance_q31 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix multiplication
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_mult_f32(
|
||||
const arm_matrix_instance_f32 * pSrcA,
|
||||
const arm_matrix_instance_f32 * pSrcB,
|
||||
arm_matrix_instance_f32 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix multiplication
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_mult_f64(
|
||||
const arm_matrix_instance_f64 * pSrcA,
|
||||
const arm_matrix_instance_f64 * pSrcB,
|
||||
arm_matrix_instance_f64 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix and vector multiplication
|
||||
* @param[in] pSrcMat points to the input matrix structure
|
||||
* @param[in] pVec points to vector
|
||||
* @param[out] pDst points to output vector
|
||||
*/
|
||||
void arm_mat_vec_mult_f32(
|
||||
const arm_matrix_instance_f32 *pSrcMat,
|
||||
const float32_t *pVec,
|
||||
float32_t *pDst);
|
||||
|
||||
/**
|
||||
* @brief Q7 matrix multiplication
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @param[in] pState points to the array for storing intermediate results
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_mult_q7(
|
||||
const arm_matrix_instance_q7 * pSrcA,
|
||||
const arm_matrix_instance_q7 * pSrcB,
|
||||
arm_matrix_instance_q7 * pDst,
|
||||
q7_t * pState);
|
||||
|
||||
/**
|
||||
* @brief Q7 matrix and vector multiplication
|
||||
* @param[in] pSrcMat points to the input matrix structure
|
||||
* @param[in] pVec points to vector
|
||||
* @param[out] pDst points to output vector
|
||||
*/
|
||||
void arm_mat_vec_mult_q7(
|
||||
const arm_matrix_instance_q7 *pSrcMat,
|
||||
const q7_t *pVec,
|
||||
q7_t *pDst);
|
||||
|
||||
/**
|
||||
* @brief Q15 matrix multiplication
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @param[in] pState points to the array for storing intermediate results
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_mult_q15(
|
||||
const arm_matrix_instance_q15 * pSrcA,
|
||||
const arm_matrix_instance_q15 * pSrcB,
|
||||
arm_matrix_instance_q15 * pDst,
|
||||
q15_t * pState);
|
||||
|
||||
/**
|
||||
* @brief Q15 matrix and vector multiplication
|
||||
* @param[in] pSrcMat points to the input matrix structure
|
||||
* @param[in] pVec points to vector
|
||||
* @param[out] pDst points to output vector
|
||||
*/
|
||||
void arm_mat_vec_mult_q15(
|
||||
const arm_matrix_instance_q15 *pSrcMat,
|
||||
const q15_t *pVec,
|
||||
q15_t *pDst);
|
||||
|
||||
/**
|
||||
* @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @param[in] pState points to the array for storing intermediate results
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_mult_fast_q15(
|
||||
const arm_matrix_instance_q15 * pSrcA,
|
||||
const arm_matrix_instance_q15 * pSrcB,
|
||||
arm_matrix_instance_q15 * pDst,
|
||||
q15_t * pState);
|
||||
|
||||
/**
|
||||
* @brief Q31 matrix multiplication
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_mult_q31(
|
||||
const arm_matrix_instance_q31 * pSrcA,
|
||||
const arm_matrix_instance_q31 * pSrcB,
|
||||
arm_matrix_instance_q31 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q31 matrix multiplication
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @param[in] pState points to the array for storing intermediate results
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_mult_opt_q31(
|
||||
const arm_matrix_instance_q31 * pSrcA,
|
||||
const arm_matrix_instance_q31 * pSrcB,
|
||||
arm_matrix_instance_q31 * pDst,
|
||||
q31_t *pState);
|
||||
|
||||
/**
|
||||
* @brief Q31 matrix and vector multiplication
|
||||
* @param[in] pSrcMat points to the input matrix structure
|
||||
* @param[in] pVec points to vector
|
||||
* @param[out] pDst points to output vector
|
||||
*/
|
||||
void arm_mat_vec_mult_q31(
|
||||
const arm_matrix_instance_q31 *pSrcMat,
|
||||
const q31_t *pVec,
|
||||
q31_t *pDst);
|
||||
|
||||
/**
|
||||
* @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_mult_fast_q31(
|
||||
const arm_matrix_instance_q31 * pSrcA,
|
||||
const arm_matrix_instance_q31 * pSrcB,
|
||||
arm_matrix_instance_q31 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix subtraction
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_sub_f32(
|
||||
const arm_matrix_instance_f32 * pSrcA,
|
||||
const arm_matrix_instance_f32 * pSrcB,
|
||||
arm_matrix_instance_f32 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix subtraction
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_sub_f64(
|
||||
const arm_matrix_instance_f64 * pSrcA,
|
||||
const arm_matrix_instance_f64 * pSrcB,
|
||||
arm_matrix_instance_f64 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q15 matrix subtraction
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_sub_q15(
|
||||
const arm_matrix_instance_q15 * pSrcA,
|
||||
const arm_matrix_instance_q15 * pSrcB,
|
||||
arm_matrix_instance_q15 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q31 matrix subtraction
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_sub_q31(
|
||||
const arm_matrix_instance_q31 * pSrcA,
|
||||
const arm_matrix_instance_q31 * pSrcB,
|
||||
arm_matrix_instance_q31 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix scaling.
|
||||
* @param[in] pSrc points to the input matrix
|
||||
* @param[in] scale scale factor
|
||||
* @param[out] pDst points to the output matrix
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_scale_f32(
|
||||
const arm_matrix_instance_f32 * pSrc,
|
||||
float32_t scale,
|
||||
arm_matrix_instance_f32 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q15 matrix scaling.
|
||||
* @param[in] pSrc points to input matrix
|
||||
* @param[in] scaleFract fractional portion of the scale factor
|
||||
* @param[in] shift number of bits to shift the result by
|
||||
* @param[out] pDst points to output matrix
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_scale_q15(
|
||||
const arm_matrix_instance_q15 * pSrc,
|
||||
q15_t scaleFract,
|
||||
int32_t shift,
|
||||
arm_matrix_instance_q15 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q31 matrix scaling.
|
||||
* @param[in] pSrc points to input matrix
|
||||
* @param[in] scaleFract fractional portion of the scale factor
|
||||
* @param[in] shift number of bits to shift the result by
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_scale_q31(
|
||||
const arm_matrix_instance_q31 * pSrc,
|
||||
q31_t scaleFract,
|
||||
int32_t shift,
|
||||
arm_matrix_instance_q31 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q31 matrix initialization.
|
||||
* @param[in,out] S points to an instance of the floating-point matrix structure.
|
||||
* @param[in] nRows number of rows in the matrix.
|
||||
* @param[in] nColumns number of columns in the matrix.
|
||||
* @param[in] pData points to the matrix data array.
|
||||
*/
|
||||
void arm_mat_init_q31(
|
||||
arm_matrix_instance_q31 * S,
|
||||
uint16_t nRows,
|
||||
uint16_t nColumns,
|
||||
q31_t * pData);
|
||||
|
||||
/**
|
||||
* @brief Q15 matrix initialization.
|
||||
* @param[in,out] S points to an instance of the floating-point matrix structure.
|
||||
* @param[in] nRows number of rows in the matrix.
|
||||
* @param[in] nColumns number of columns in the matrix.
|
||||
* @param[in] pData points to the matrix data array.
|
||||
*/
|
||||
void arm_mat_init_q15(
|
||||
arm_matrix_instance_q15 * S,
|
||||
uint16_t nRows,
|
||||
uint16_t nColumns,
|
||||
q15_t * pData);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix initialization.
|
||||
* @param[in,out] S points to an instance of the floating-point matrix structure.
|
||||
* @param[in] nRows number of rows in the matrix.
|
||||
* @param[in] nColumns number of columns in the matrix.
|
||||
* @param[in] pData points to the matrix data array.
|
||||
*/
|
||||
void arm_mat_init_f32(
|
||||
arm_matrix_instance_f32 * S,
|
||||
uint16_t nRows,
|
||||
uint16_t nColumns,
|
||||
float32_t * pData);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix inverse.
|
||||
* @param[in] src points to the instance of the input floating-point matrix structure.
|
||||
* @param[out] dst points to the instance of the output floating-point matrix structure.
|
||||
* @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
|
||||
* If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
|
||||
*/
|
||||
arm_status arm_mat_inverse_f32(
|
||||
const arm_matrix_instance_f32 * src,
|
||||
arm_matrix_instance_f32 * dst);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix inverse.
|
||||
* @param[in] src points to the instance of the input floating-point matrix structure.
|
||||
* @param[out] dst points to the instance of the output floating-point matrix structure.
|
||||
* @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
|
||||
* If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
|
||||
*/
|
||||
arm_status arm_mat_inverse_f64(
|
||||
const arm_matrix_instance_f64 * src,
|
||||
arm_matrix_instance_f64 * dst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point Cholesky decomposition of Symmetric Positive Definite Matrix.
|
||||
* @param[in] src points to the instance of the input floating-point matrix structure.
|
||||
* @param[out] dst points to the instance of the output floating-point matrix structure.
|
||||
* @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
|
||||
* If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE.
|
||||
* If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition.
|
||||
* The decomposition is returning a lower triangular matrix.
|
||||
*/
|
||||
arm_status arm_mat_cholesky_f64(
|
||||
const arm_matrix_instance_f64 * src,
|
||||
arm_matrix_instance_f64 * dst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point Cholesky decomposition of Symmetric Positive Definite Matrix.
|
||||
* @param[in] src points to the instance of the input floating-point matrix structure.
|
||||
* @param[out] dst points to the instance of the output floating-point matrix structure.
|
||||
* @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
|
||||
* If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE.
|
||||
* If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition.
|
||||
* The decomposition is returning a lower triangular matrix.
|
||||
*/
|
||||
arm_status arm_mat_cholesky_f32(
|
||||
const arm_matrix_instance_f32 * src,
|
||||
arm_matrix_instance_f32 * dst);
|
||||
|
||||
/**
|
||||
* @brief Solve UT . X = A where UT is an upper triangular matrix
|
||||
* @param[in] ut The upper triangular matrix
|
||||
* @param[in] a The matrix a
|
||||
* @param[out] dst The solution X of UT . X = A
|
||||
* @return The function returns ARM_MATH_SINGULAR, if the system can't be solved.
|
||||
*/
|
||||
arm_status arm_mat_solve_upper_triangular_f32(
|
||||
const arm_matrix_instance_f32 * ut,
|
||||
const arm_matrix_instance_f32 * a,
|
||||
arm_matrix_instance_f32 * dst);
|
||||
|
||||
/**
|
||||
* @brief Solve LT . X = A where LT is a lower triangular matrix
|
||||
* @param[in] lt The lower triangular matrix
|
||||
* @param[in] a The matrix a
|
||||
* @param[out] dst The solution X of LT . X = A
|
||||
* @return The function returns ARM_MATH_SINGULAR, if the system can't be solved.
|
||||
*/
|
||||
arm_status arm_mat_solve_lower_triangular_f32(
|
||||
const arm_matrix_instance_f32 * lt,
|
||||
const arm_matrix_instance_f32 * a,
|
||||
arm_matrix_instance_f32 * dst);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Solve UT . X = A where UT is an upper triangular matrix
|
||||
* @param[in] ut The upper triangular matrix
|
||||
* @param[in] a The matrix a
|
||||
* @param[out] dst The solution X of UT . X = A
|
||||
* @return The function returns ARM_MATH_SINGULAR, if the system can't be solved.
|
||||
*/
|
||||
arm_status arm_mat_solve_upper_triangular_f64(
|
||||
const arm_matrix_instance_f64 * ut,
|
||||
const arm_matrix_instance_f64 * a,
|
||||
arm_matrix_instance_f64 * dst);
|
||||
|
||||
/**
|
||||
* @brief Solve LT . X = A where LT is a lower triangular matrix
|
||||
* @param[in] lt The lower triangular matrix
|
||||
* @param[in] a The matrix a
|
||||
* @param[out] dst The solution X of LT . X = A
|
||||
* @return The function returns ARM_MATH_SINGULAR, if the system can't be solved.
|
||||
*/
|
||||
arm_status arm_mat_solve_lower_triangular_f64(
|
||||
const arm_matrix_instance_f64 * lt,
|
||||
const arm_matrix_instance_f64 * a,
|
||||
arm_matrix_instance_f64 * dst);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point LDL decomposition of Symmetric Positive Semi-Definite Matrix.
|
||||
* @param[in] src points to the instance of the input floating-point matrix structure.
|
||||
* @param[out] l points to the instance of the output floating-point triangular matrix structure.
|
||||
* @param[out] d points to the instance of the output floating-point diagonal matrix structure.
|
||||
* @param[out] p points to the instance of the output floating-point permutation vector.
|
||||
* @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
|
||||
* If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE.
|
||||
* The decomposition is returning a lower triangular matrix.
|
||||
*/
|
||||
arm_status arm_mat_ldlt_f32(
|
||||
const arm_matrix_instance_f32 * src,
|
||||
arm_matrix_instance_f32 * l,
|
||||
arm_matrix_instance_f32 * d,
|
||||
uint16_t * pp);
|
||||
|
||||
/**
|
||||
* @brief Floating-point LDL decomposition of Symmetric Positive Semi-Definite Matrix.
|
||||
* @param[in] src points to the instance of the input floating-point matrix structure.
|
||||
* @param[out] l points to the instance of the output floating-point triangular matrix structure.
|
||||
* @param[out] d points to the instance of the output floating-point diagonal matrix structure.
|
||||
* @param[out] p points to the instance of the output floating-point permutation vector.
|
||||
* @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
|
||||
* If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE.
|
||||
* The decomposition is returning a lower triangular matrix.
|
||||
*/
|
||||
arm_status arm_mat_ldlt_f64(
|
||||
const arm_matrix_instance_f64 * src,
|
||||
arm_matrix_instance_f64 * l,
|
||||
arm_matrix_instance_f64 * d,
|
||||
uint16_t * pp);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _MATRIX_FUNCTIONS_H_ */
|
||||
|
|
@ -0,0 +1,221 @@
|
|||
/******************************************************************************
|
||||
* @file matrix_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MATRIX_FUNCTIONS_F16_H_
|
||||
#define _MATRIX_FUNCTIONS_F16_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point matrix structure.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t numRows; /**< number of rows of the matrix. */
|
||||
uint16_t numCols; /**< number of columns of the matrix. */
|
||||
float16_t *pData; /**< points to the data of the matrix. */
|
||||
} arm_matrix_instance_f16;
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix addition.
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_add_f16(
|
||||
const arm_matrix_instance_f16 * pSrcA,
|
||||
const arm_matrix_instance_f16 * pSrcB,
|
||||
arm_matrix_instance_f16 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point, complex, matrix multiplication.
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_cmplx_mult_f16(
|
||||
const arm_matrix_instance_f16 * pSrcA,
|
||||
const arm_matrix_instance_f16 * pSrcB,
|
||||
arm_matrix_instance_f16 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix transpose.
|
||||
* @param[in] pSrc points to the input matrix
|
||||
* @param[out] pDst points to the output matrix
|
||||
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
|
||||
* or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_trans_f16(
|
||||
const arm_matrix_instance_f16 * pSrc,
|
||||
arm_matrix_instance_f16 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex matrix transpose.
|
||||
* @param[in] pSrc points to the input matrix
|
||||
* @param[out] pDst points to the output matrix
|
||||
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
|
||||
* or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_cmplx_trans_f16(
|
||||
const arm_matrix_instance_f16 * pSrc,
|
||||
arm_matrix_instance_f16 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix multiplication
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_mult_f16(
|
||||
const arm_matrix_instance_f16 * pSrcA,
|
||||
const arm_matrix_instance_f16 * pSrcB,
|
||||
arm_matrix_instance_f16 * pDst);
|
||||
/**
|
||||
* @brief Floating-point matrix and vector multiplication
|
||||
* @param[in] pSrcMat points to the input matrix structure
|
||||
* @param[in] pVec points to vector
|
||||
* @param[out] pDst points to output vector
|
||||
*/
|
||||
void arm_mat_vec_mult_f16(
|
||||
const arm_matrix_instance_f16 *pSrcMat,
|
||||
const float16_t *pVec,
|
||||
float16_t *pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix subtraction
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_sub_f16(
|
||||
const arm_matrix_instance_f16 * pSrcA,
|
||||
const arm_matrix_instance_f16 * pSrcB,
|
||||
arm_matrix_instance_f16 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix scaling.
|
||||
* @param[in] pSrc points to the input matrix
|
||||
* @param[in] scale scale factor
|
||||
* @param[out] pDst points to the output matrix
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_scale_f16(
|
||||
const arm_matrix_instance_f16 * pSrc,
|
||||
float16_t scale,
|
||||
arm_matrix_instance_f16 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix initialization.
|
||||
* @param[in,out] S points to an instance of the floating-point matrix structure.
|
||||
* @param[in] nRows number of rows in the matrix.
|
||||
* @param[in] nColumns number of columns in the matrix.
|
||||
* @param[in] pData points to the matrix data array.
|
||||
*/
|
||||
void arm_mat_init_f16(
|
||||
arm_matrix_instance_f16 * S,
|
||||
uint16_t nRows,
|
||||
uint16_t nColumns,
|
||||
float16_t * pData);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix inverse.
|
||||
* @param[in] src points to the instance of the input floating-point matrix structure.
|
||||
* @param[out] dst points to the instance of the output floating-point matrix structure.
|
||||
* @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
|
||||
* If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
|
||||
*/
|
||||
arm_status arm_mat_inverse_f16(
|
||||
const arm_matrix_instance_f16 * src,
|
||||
arm_matrix_instance_f16 * dst);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point Cholesky decomposition of Symmetric Positive Definite Matrix.
|
||||
* @param[in] src points to the instance of the input floating-point matrix structure.
|
||||
* @param[out] dst points to the instance of the output floating-point matrix structure.
|
||||
* @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
|
||||
* If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE.
|
||||
* If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition.
|
||||
* The decomposition is returning a lower triangular matrix.
|
||||
*/
|
||||
arm_status arm_mat_cholesky_f16(
|
||||
const arm_matrix_instance_f16 * src,
|
||||
arm_matrix_instance_f16 * dst);
|
||||
|
||||
/**
|
||||
* @brief Solve UT . X = A where UT is an upper triangular matrix
|
||||
* @param[in] ut The upper triangular matrix
|
||||
* @param[in] a The matrix a
|
||||
* @param[out] dst The solution X of UT . X = A
|
||||
* @return The function returns ARM_MATH_SINGULAR, if the system can't be solved.
|
||||
*/
|
||||
arm_status arm_mat_solve_upper_triangular_f16(
|
||||
const arm_matrix_instance_f16 * ut,
|
||||
const arm_matrix_instance_f16 * a,
|
||||
arm_matrix_instance_f16 * dst);
|
||||
|
||||
/**
|
||||
* @brief Solve LT . X = A where LT is a lower triangular matrix
|
||||
* @param[in] lt The lower triangular matrix
|
||||
* @param[in] a The matrix a
|
||||
* @param[out] dst The solution X of LT . X = A
|
||||
* @return The function returns ARM_MATH_SINGULAR, if the system can't be solved.
|
||||
*/
|
||||
arm_status arm_mat_solve_lower_triangular_f16(
|
||||
const arm_matrix_instance_f16 * lt,
|
||||
const arm_matrix_instance_f16 * a,
|
||||
arm_matrix_instance_f16 * dst);
|
||||
|
||||
|
||||
|
||||
#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _MATRIX_FUNCTIONS_F16_H_ */
|
||||
|
|
@ -0,0 +1,576 @@
|
|||
/******************************************************************************
|
||||
* @file none.h
|
||||
* @brief Intrinsincs when no DSP extension available
|
||||
* @version V1.9.0
|
||||
* @date 20. July 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
|
||||
Definitions in this file are allowing to reuse some versions of the
|
||||
CMSIS-DSP to build on a core (M0 for instance) or a host where
|
||||
DSP extension are not available.
|
||||
|
||||
Ideally a pure C version should have been used instead.
|
||||
But those are not always available or use a restricted set
|
||||
of intrinsics.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef _NONE_H_
|
||||
#define _NONE_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/*
|
||||
|
||||
Normally those kind of definitions are in a compiler file
|
||||
in Core or Core_A.
|
||||
|
||||
But for MSVC compiler it is a bit special. The goal is very specific
|
||||
to CMSIS-DSP and only to allow the use of this library from other
|
||||
systems like Python or Matlab.
|
||||
|
||||
MSVC is not going to be used to cross-compile to ARM. So, having a MSVC
|
||||
compiler file in Core or Core_A would not make sense.
|
||||
|
||||
*/
|
||||
#if defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) || defined(__APPLE_CC__)
|
||||
__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data)
|
||||
{
|
||||
if (data == 0U) { return 32U; }
|
||||
|
||||
uint32_t count = 0U;
|
||||
uint32_t mask = 0x80000000U;
|
||||
|
||||
while ((data & mask) == 0U)
|
||||
{
|
||||
count += 1U;
|
||||
mask = mask >> 1U;
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit)
|
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
\param [in] op1 Value to rotate
|
||||
\param [in] op2 Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
op2 %= 32U;
|
||||
if (op2 == 0U)
|
||||
{
|
||||
return op1;
|
||||
}
|
||||
return (op1 >> op2) | (op1 << (32U - op2));
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Clips Q63 to Q31 values.
|
||||
*/
|
||||
__STATIC_FORCEINLINE q31_t clip_q63_to_q31(
|
||||
q63_t x)
|
||||
{
|
||||
return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
|
||||
((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clips Q63 to Q15 values.
|
||||
*/
|
||||
__STATIC_FORCEINLINE q15_t clip_q63_to_q15(
|
||||
q63_t x)
|
||||
{
|
||||
return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
|
||||
((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clips Q31 to Q7 values.
|
||||
*/
|
||||
__STATIC_FORCEINLINE q7_t clip_q31_to_q7(
|
||||
q31_t x)
|
||||
{
|
||||
return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
|
||||
((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clips Q31 to Q15 values.
|
||||
*/
|
||||
__STATIC_FORCEINLINE q15_t clip_q31_to_q15(
|
||||
q31_t x)
|
||||
{
|
||||
return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
|
||||
((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
|
||||
*/
|
||||
__STATIC_FORCEINLINE q63_t mult32x64(
|
||||
q63_t x,
|
||||
q31_t y)
|
||||
{
|
||||
return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
|
||||
(((q63_t) (x >> 32) * y) ) );
|
||||
}
|
||||
|
||||
/* SMMLAR */
|
||||
#define multAcc_32x32_keep32_R(a, x, y) \
|
||||
a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
|
||||
|
||||
/* SMMLSR */
|
||||
#define multSub_32x32_keep32_R(a, x, y) \
|
||||
a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
|
||||
|
||||
/* SMMULR */
|
||||
#define mult_32x32_keep32_R(a, x, y) \
|
||||
a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
|
||||
|
||||
/* SMMLA */
|
||||
#define multAcc_32x32_keep32(a, x, y) \
|
||||
a += (q31_t) (((q63_t) x * y) >> 32)
|
||||
|
||||
/* SMMLS */
|
||||
#define multSub_32x32_keep32(a, x, y) \
|
||||
a -= (q31_t) (((q63_t) x * y) >> 32)
|
||||
|
||||
/* SMMUL */
|
||||
#define mult_32x32_keep32(a, x, y) \
|
||||
a = (q31_t) (((q63_t) x * y ) >> 32)
|
||||
|
||||
#ifndef ARM_MATH_DSP
|
||||
/**
|
||||
* @brief definition to pack two 16 bit values.
|
||||
*/
|
||||
#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
|
||||
(((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
|
||||
#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
|
||||
(((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief definition to pack four 8 bit values.
|
||||
*/
|
||||
#ifndef ARM_MATH_BIG_ENDIAN
|
||||
#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
|
||||
(((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
|
||||
(((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
|
||||
(((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
|
||||
#else
|
||||
#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
|
||||
(((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
|
||||
(((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
|
||||
(((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined intrinsic functions
|
||||
*/
|
||||
#if !defined (ARM_MATH_DSP)
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined QADD8
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __QADD8(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
q31_t r, s, t, u;
|
||||
|
||||
r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
|
||||
s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
|
||||
t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
|
||||
u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
|
||||
|
||||
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined QSUB8
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __QSUB8(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
q31_t r, s, t, u;
|
||||
|
||||
r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
|
||||
s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
|
||||
t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
|
||||
u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
|
||||
|
||||
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined QADD16
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __QADD16(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
|
||||
q31_t r = 0, s = 0;
|
||||
|
||||
r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
|
||||
s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
|
||||
|
||||
return ((uint32_t)((s << 16) | (r )));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SHADD16
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __SHADD16(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
q31_t r, s;
|
||||
|
||||
r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
|
||||
s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
|
||||
|
||||
return ((uint32_t)((s << 16) | (r )));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined QSUB16
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __QSUB16(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
q31_t r, s;
|
||||
|
||||
r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
|
||||
s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
|
||||
|
||||
return ((uint32_t)((s << 16) | (r )));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SHSUB16
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __SHSUB16(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
q31_t r, s;
|
||||
|
||||
r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
|
||||
s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
|
||||
|
||||
return ((uint32_t)((s << 16) | (r )));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined QASX
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __QASX(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
q31_t r, s;
|
||||
|
||||
r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
|
||||
s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
|
||||
|
||||
return ((uint32_t)((s << 16) | (r )));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SHASX
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __SHASX(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
q31_t r, s;
|
||||
|
||||
r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
|
||||
s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
|
||||
|
||||
return ((uint32_t)((s << 16) | (r )));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined QSAX
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __QSAX(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
q31_t r, s;
|
||||
|
||||
r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
|
||||
s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
|
||||
|
||||
return ((uint32_t)((s << 16) | (r )));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SHSAX
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __SHSAX(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
q31_t r, s;
|
||||
|
||||
r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
|
||||
s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
|
||||
|
||||
return ((uint32_t)((s << 16) | (r )));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SMUSDX
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __SMUSDX(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
|
||||
((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
|
||||
}
|
||||
|
||||
/*
|
||||
* @brief C custom defined SMUADX
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __SMUADX(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
|
||||
((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined QADD
|
||||
*/
|
||||
__STATIC_FORCEINLINE int32_t __QADD(
|
||||
int32_t x,
|
||||
int32_t y)
|
||||
{
|
||||
return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined QSUB
|
||||
*/
|
||||
__STATIC_FORCEINLINE int32_t __QSUB(
|
||||
int32_t x,
|
||||
int32_t y)
|
||||
{
|
||||
return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SMLAD
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __SMLAD(
|
||||
uint32_t x,
|
||||
uint32_t y,
|
||||
uint32_t sum)
|
||||
{
|
||||
return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
|
||||
((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
|
||||
( ((q31_t)sum ) ) ));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SMLADX
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __SMLADX(
|
||||
uint32_t x,
|
||||
uint32_t y,
|
||||
uint32_t sum)
|
||||
{
|
||||
return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
|
||||
((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
|
||||
( ((q31_t)sum ) ) ));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SMLSDX
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __SMLSDX(
|
||||
uint32_t x,
|
||||
uint32_t y,
|
||||
uint32_t sum)
|
||||
{
|
||||
return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
|
||||
((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
|
||||
( ((q31_t)sum ) ) ));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SMLALD
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint64_t __SMLALD(
|
||||
uint32_t x,
|
||||
uint32_t y,
|
||||
uint64_t sum)
|
||||
{
|
||||
/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
|
||||
return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
|
||||
((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
|
||||
( ((q63_t)sum ) ) ));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SMLALDX
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint64_t __SMLALDX(
|
||||
uint32_t x,
|
||||
uint32_t y,
|
||||
uint64_t sum)
|
||||
{
|
||||
/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
|
||||
return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
|
||||
((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
|
||||
( ((q63_t)sum ) ) ));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SMUAD
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __SMUAD(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
|
||||
((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SMUSD
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __SMUSD(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
|
||||
((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SXTB16
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __SXTB16(
|
||||
uint32_t x)
|
||||
{
|
||||
return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
|
||||
((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));
|
||||
}
|
||||
|
||||
/*
|
||||
* @brief C custom defined SMMLA
|
||||
*/
|
||||
__STATIC_FORCEINLINE int32_t __SMMLA(
|
||||
int32_t x,
|
||||
int32_t y,
|
||||
int32_t sum)
|
||||
{
|
||||
return (sum + (int32_t) (((int64_t) x * y) >> 32));
|
||||
}
|
||||
|
||||
#endif /* !defined (ARM_MATH_DSP) */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _TRANSFORM_FUNCTIONS_H_ */
|
||||
|
|
@ -0,0 +1,159 @@
|
|||
/******************************************************************************
|
||||
* @file quaternion_math_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _QUATERNION_MATH_FUNCTIONS_H_
|
||||
#define _QUATERNION_MATH_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @defgroup groupQuaternionMath Quaternion Math Functions
|
||||
* Functions to operates on quaternions and convert between a
|
||||
* rotation and quaternion representation.
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
@brief Floating-point quaternion Norm.
|
||||
@param[in] pInputQuaternions points to the input vector of quaternions
|
||||
@param[out] pNorms points to the output vector of norms
|
||||
@param[in] nbQuaternions number of quaternions in each vector
|
||||
@return none
|
||||
*/
|
||||
|
||||
|
||||
|
||||
void arm_quaternion_norm_f32(const float32_t *pInputQuaternions,
|
||||
float32_t *pNorms,
|
||||
uint32_t nbQuaternions);
|
||||
|
||||
|
||||
/**
|
||||
@brief Floating-point quaternion inverse.
|
||||
@param[in] pInputQuaternions points to the input vector of quaternions
|
||||
@param[out] pInverseQuaternions points to the output vector of inverse quaternions
|
||||
@param[in] nbQuaternions number of quaternions in each vector
|
||||
@return none
|
||||
*/
|
||||
|
||||
void arm_quaternion_inverse_f32(const float32_t *pInputQuaternions,
|
||||
float32_t *pInverseQuaternions,
|
||||
uint32_t nbQuaternions);
|
||||
|
||||
/**
|
||||
@brief Floating-point quaternion conjugates.
|
||||
@param[in] pInputQuaternions points to the input vector of quaternions
|
||||
@param[out] pConjugateQuaternions points to the output vector of conjugate quaternions
|
||||
@param[in] nbQuaternions number of quaternions in each vector
|
||||
@return none
|
||||
*/
|
||||
void arm_quaternion_conjugate_f32(const float32_t *inputQuaternions,
|
||||
float32_t *pConjugateQuaternions,
|
||||
uint32_t nbQuaternions);
|
||||
|
||||
/**
|
||||
@brief Floating-point normalization of quaternions.
|
||||
@param[in] pInputQuaternions points to the input vector of quaternions
|
||||
@param[out] pNormalizedQuaternions points to the output vector of normalized quaternions
|
||||
@param[in] nbQuaternions number of quaternions in each vector
|
||||
@return none
|
||||
*/
|
||||
void arm_quaternion_normalize_f32(const float32_t *inputQuaternions,
|
||||
float32_t *pNormalizedQuaternions,
|
||||
uint32_t nbQuaternions);
|
||||
|
||||
|
||||
/**
|
||||
@brief Floating-point product of two quaternions.
|
||||
@param[in] qa First quaternion
|
||||
@param[in] qb Second quaternion
|
||||
@param[out] r Product of two quaternions
|
||||
@return none
|
||||
*/
|
||||
void arm_quaternion_product_single_f32(const float32_t *qa,
|
||||
const float32_t *qb,
|
||||
float32_t *r);
|
||||
|
||||
/**
|
||||
@brief Floating-point elementwise product two quaternions.
|
||||
@param[in] qa First array of quaternions
|
||||
@param[in] qb Second array of quaternions
|
||||
@param[out] r Elementwise product of quaternions
|
||||
@param[in] nbQuaternions Number of quaternions in the array
|
||||
@return none
|
||||
*/
|
||||
void arm_quaternion_product_f32(const float32_t *qa,
|
||||
const float32_t *qb,
|
||||
float32_t *r,
|
||||
uint32_t nbQuaternions);
|
||||
|
||||
/**
|
||||
* @brief Conversion of quaternion to equivalent rotation matrix.
|
||||
* @param[in] pInputQuaternions points to an array of normalized quaternions
|
||||
* @param[out] pOutputRotations points to an array of 3x3 rotations (in row order)
|
||||
* @param[in] nbQuaternions in the array
|
||||
* @return none.
|
||||
*
|
||||
* <b>Format of rotation matrix</b>
|
||||
* \par
|
||||
* The quaternion a + ib + jc + kd is converted into rotation matrix:
|
||||
* a^2 + b^2 - c^2 - d^2 2bc - 2ad 2bd + 2ac
|
||||
* 2bc + 2ad a^2 - b^2 + c^2 - d^2 2cd - 2ab
|
||||
* 2bd - 2ac 2cd + 2ab a^2 - b^2 - c^2 + d^2
|
||||
*
|
||||
* Rotation matrix is saved in row order : R00 R01 R02 R10 R11 R12 R20 R21 R22
|
||||
*/
|
||||
void arm_quaternion2rotation_f32(const float32_t *pInputQuaternions,
|
||||
float32_t *pOutputRotations,
|
||||
uint32_t nbQuaternions);
|
||||
|
||||
/**
|
||||
* @brief Conversion of a rotation matrix to equivalent quaternion.
|
||||
* @param[in] pInputRotations points to an array 3x3 rotation matrix (in row order)
|
||||
* @param[out] pOutputQuaternions points to an array of quaternions
|
||||
* @param[in] nbQuaternions in the array
|
||||
* @return none.
|
||||
*/
|
||||
void arm_rotation2quaternion_f32(const float32_t *pInputRotations,
|
||||
float32_t *pOutputQuaternions,
|
||||
uint32_t nbQuaternions);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _QUATERNION_MATH_FUNCTIONS_H_ */
|
||||
|
|
@ -0,0 +1,977 @@
|
|||
/******************************************************************************
|
||||
* @file statistics_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _STATISTICS_FUNCTIONS_H_
|
||||
#define _STATISTICS_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#include "dsp/basic_math_functions.h"
|
||||
#include "dsp/fast_math_functions.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup groupStats Statistics Functions
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Computation of the LogSumExp
|
||||
*
|
||||
* In probabilistic computations, the dynamic of the probability values can be very
|
||||
* wide because they come from gaussian functions.
|
||||
* To avoid underflow and overflow issues, the values are represented by their log.
|
||||
* In this representation, multiplying the original exp values is easy : their logs are added.
|
||||
* But adding the original exp values is requiring some special handling and it is the
|
||||
* goal of the LogSumExp function.
|
||||
*
|
||||
* If the values are x1...xn, the function is computing:
|
||||
*
|
||||
* ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that
|
||||
* rounding issues are minimised.
|
||||
*
|
||||
* The max xm of the values is extracted and the function is computing:
|
||||
* xm + ln(exp(x1 - xm) + ... + exp(xn - xm))
|
||||
*
|
||||
* @param[in] *in Pointer to an array of input values.
|
||||
* @param[in] blockSize Number of samples in the input array.
|
||||
* @return LogSumExp
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
float32_t arm_logsumexp_f32(const float32_t *in, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Dot product with log arithmetic
|
||||
*
|
||||
* Vectors are containing the log of the samples
|
||||
*
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @param[in] pTmpBuffer temporary buffer of length blockSize
|
||||
* @return The log of the dot product .
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
float32_t arm_logsumexp_dot_prod_f32(const float32_t * pSrcA,
|
||||
const float32_t * pSrcB,
|
||||
uint32_t blockSize,
|
||||
float32_t *pTmpBuffer);
|
||||
|
||||
/**
|
||||
* @brief Entropy
|
||||
*
|
||||
* @param[in] pSrcA Array of input values.
|
||||
* @param[in] blockSize Number of samples in the input array.
|
||||
* @return Entropy -Sum(p ln p)
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
float32_t arm_entropy_f32(const float32_t * pSrcA,uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Entropy
|
||||
*
|
||||
* @param[in] pSrcA Array of input values.
|
||||
* @param[in] blockSize Number of samples in the input array.
|
||||
* @return Entropy -Sum(p ln p)
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
float64_t arm_entropy_f64(const float64_t * pSrcA, uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Kullback-Leibler
|
||||
*
|
||||
* @param[in] pSrcA Pointer to an array of input values for probability distribution A.
|
||||
* @param[in] pSrcB Pointer to an array of input values for probability distribution B.
|
||||
* @param[in] blockSize Number of samples in the input array.
|
||||
* @return Kullback-Leibler Divergence D(A || B)
|
||||
*
|
||||
*/
|
||||
float32_t arm_kullback_leibler_f32(const float32_t * pSrcA
|
||||
,const float32_t * pSrcB
|
||||
,uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Kullback-Leibler
|
||||
*
|
||||
* @param[in] pSrcA Pointer to an array of input values for probability distribution A.
|
||||
* @param[in] pSrcB Pointer to an array of input values for probability distribution B.
|
||||
* @param[in] blockSize Number of samples in the input array.
|
||||
* @return Kullback-Leibler Divergence D(A || B)
|
||||
*
|
||||
*/
|
||||
float64_t arm_kullback_leibler_f64(const float64_t * pSrcA,
|
||||
const float64_t * pSrcB,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Sum of the squares of the elements of a Q31 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_power_q31(
|
||||
const q31_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q63_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Sum of the squares of the elements of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_power_f32(
|
||||
const float32_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float32_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Sum of the squares of the elements of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_power_f64(
|
||||
const float64_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float64_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Sum of the squares of the elements of a Q15 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_power_q15(
|
||||
const q15_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q63_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Sum of the squares of the elements of a Q7 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_power_q7(
|
||||
const q7_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q31_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Mean value of a Q7 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_mean_q7(
|
||||
const q7_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q7_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Mean value of a Q15 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_mean_q15(
|
||||
const q15_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q15_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Mean value of a Q31 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_mean_q31(
|
||||
const q31_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q31_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Mean value of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_mean_f32(
|
||||
const float32_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float32_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Mean value of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_mean_f64(
|
||||
const float64_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float64_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Variance of the elements of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_var_f32(
|
||||
const float32_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float32_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Variance of the elements of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_var_f64(
|
||||
const float64_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float64_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Variance of the elements of a Q31 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_var_q31(
|
||||
const q31_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q31_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Variance of the elements of a Q15 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_var_q15(
|
||||
const q15_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q15_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Root Mean Square of the elements of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_rms_f32(
|
||||
const float32_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float32_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Root Mean Square of the elements of a Q31 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_rms_q31(
|
||||
const q31_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q31_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Root Mean Square of the elements of a Q15 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_rms_q15(
|
||||
const q15_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q15_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Standard deviation of the elements of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_std_f32(
|
||||
const float32_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float32_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Standard deviation of the elements of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_std_f64(
|
||||
const float64_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float64_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Standard deviation of the elements of a Q31 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_std_q31(
|
||||
const q31_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q31_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Standard deviation of the elements of a Q15 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_std_q15(
|
||||
const q15_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q15_t * pResult);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Minimum value of a Q7 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] result is output pointer
|
||||
* @param[in] index is the array index of the minimum value in the input buffer.
|
||||
*/
|
||||
void arm_min_q7(
|
||||
const q7_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q7_t * result,
|
||||
uint32_t * index);
|
||||
|
||||
/**
|
||||
* @brief Minimum value of absolute values of a Q7 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] result is output pointer
|
||||
* @param[in] index is the array index of the minimum value in the input buffer.
|
||||
*/
|
||||
void arm_absmin_q7(
|
||||
const q7_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q7_t * result,
|
||||
uint32_t * index);
|
||||
|
||||
/**
|
||||
* @brief Minimum value of absolute values of a Q7 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] result is output pointer
|
||||
*/
|
||||
void arm_absmin_no_idx_q7(
|
||||
const q7_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q7_t * result);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Minimum value of a Q15 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output pointer
|
||||
* @param[in] pIndex is the array index of the minimum value in the input buffer.
|
||||
*/
|
||||
void arm_min_q15(
|
||||
const q15_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q15_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Minimum value of absolute values of a Q15 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output pointer
|
||||
* @param[in] pIndex is the array index of the minimum value in the input buffer.
|
||||
*/
|
||||
void arm_absmin_q15(
|
||||
const q15_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q15_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Minimum value of absolute values of a Q15 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output pointer
|
||||
*/
|
||||
void arm_absmin_no_idx_q15(
|
||||
const q15_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q15_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Minimum value of a Q31 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output pointer
|
||||
* @param[out] pIndex is the array index of the minimum value in the input buffer.
|
||||
*/
|
||||
void arm_min_q31(
|
||||
const q31_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q31_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Minimum value of absolute values of a Q31 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output pointer
|
||||
* @param[out] pIndex is the array index of the minimum value in the input buffer.
|
||||
*/
|
||||
void arm_absmin_q31(
|
||||
const q31_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q31_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Minimum value of absolute values of a Q31 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output pointer
|
||||
*/
|
||||
void arm_absmin_no_idx_q31(
|
||||
const q31_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q31_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Minimum value of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output pointer
|
||||
* @param[out] pIndex is the array index of the minimum value in the input buffer.
|
||||
*/
|
||||
void arm_min_f32(
|
||||
const float32_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float32_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Minimum value of absolute values of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output pointer
|
||||
* @param[out] pIndex is the array index of the minimum value in the input buffer.
|
||||
*/
|
||||
void arm_absmin_f32(
|
||||
const float32_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float32_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Minimum value of absolute values of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output pointer
|
||||
*/
|
||||
void arm_absmin_no_idx_f32(
|
||||
const float32_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float32_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Minimum value of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output pointer
|
||||
* @param[out] pIndex is the array index of the minimum value in the input buffer.
|
||||
*/
|
||||
void arm_min_f64(
|
||||
const float64_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float64_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Minimum value of absolute values of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output pointer
|
||||
* @param[out] pIndex is the array index of the minimum value in the input buffer.
|
||||
*/
|
||||
void arm_absmin_f64(
|
||||
const float64_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float64_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Minimum value of absolute values of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output pointer
|
||||
*/
|
||||
void arm_absmin_no_idx_f64(
|
||||
const float64_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float64_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Maximum value of a Q7 vector.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[in] blockSize length of the input vector
|
||||
* @param[out] pResult maximum value returned here
|
||||
* @param[out] pIndex index of maximum value returned here
|
||||
*/
|
||||
void arm_max_q7(
|
||||
const q7_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q7_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Maximum value of absolute values of a Q7 vector.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[in] blockSize length of the input vector
|
||||
* @param[out] pResult maximum value returned here
|
||||
* @param[out] pIndex index of maximum value returned here
|
||||
*/
|
||||
void arm_absmax_q7(
|
||||
const q7_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q7_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Maximum value of absolute values of a Q7 vector.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[in] blockSize length of the input vector
|
||||
* @param[out] pResult maximum value returned here
|
||||
*/
|
||||
void arm_absmax_no_idx_q7(
|
||||
const q7_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q7_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Maximum value of a Q15 vector.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[in] blockSize length of the input vector
|
||||
* @param[out] pResult maximum value returned here
|
||||
* @param[out] pIndex index of maximum value returned here
|
||||
*/
|
||||
void arm_max_q15(
|
||||
const q15_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q15_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Maximum value of absolute values of a Q15 vector.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[in] blockSize length of the input vector
|
||||
* @param[out] pResult maximum value returned here
|
||||
* @param[out] pIndex index of maximum value returned here
|
||||
*/
|
||||
void arm_absmax_q15(
|
||||
const q15_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q15_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Maximum value of absolute values of a Q15 vector.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[in] blockSize length of the input vector
|
||||
* @param[out] pResult maximum value returned here
|
||||
*/
|
||||
void arm_absmax_no_idx_q15(
|
||||
const q15_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q15_t * pResult);
|
||||
|
||||
/**
|
||||
* @brief Maximum value of a Q31 vector.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[in] blockSize length of the input vector
|
||||
* @param[out] pResult maximum value returned here
|
||||
* @param[out] pIndex index of maximum value returned here
|
||||
*/
|
||||
void arm_max_q31(
|
||||
const q31_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q31_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Maximum value of absolute values of a Q31 vector.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[in] blockSize length of the input vector
|
||||
* @param[out] pResult maximum value returned here
|
||||
* @param[out] pIndex index of maximum value returned here
|
||||
*/
|
||||
void arm_absmax_q31(
|
||||
const q31_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q31_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Maximum value of absolute values of a Q31 vector.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[in] blockSize length of the input vector
|
||||
* @param[out] pResult maximum value returned here
|
||||
*/
|
||||
void arm_absmax_no_idx_q31(
|
||||
const q31_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
q31_t * pResult);
|
||||
|
||||
/**
|
||||
* @brief Maximum value of a floating-point vector.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[in] blockSize length of the input vector
|
||||
* @param[out] pResult maximum value returned here
|
||||
* @param[out] pIndex index of maximum value returned here
|
||||
*/
|
||||
void arm_max_f32(
|
||||
const float32_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float32_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Maximum value of absolute values of a floating-point vector.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[in] blockSize length of the input vector
|
||||
* @param[out] pResult maximum value returned here
|
||||
* @param[out] pIndex index of maximum value returned here
|
||||
*/
|
||||
void arm_absmax_f32(
|
||||
const float32_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float32_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Maximum value of absolute values of a floating-point vector.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[in] blockSize length of the input vector
|
||||
* @param[out] pResult maximum value returned here
|
||||
*/
|
||||
void arm_absmax_no_idx_f32(
|
||||
const float32_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float32_t * pResult);
|
||||
|
||||
/**
|
||||
* @brief Maximum value of a floating-point vector.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[in] blockSize length of the input vector
|
||||
* @param[out] pResult maximum value returned here
|
||||
* @param[out] pIndex index of maximum value returned here
|
||||
*/
|
||||
void arm_max_f64(
|
||||
const float64_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float64_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Maximum value of absolute values of a floating-point vector.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[in] blockSize length of the input vector
|
||||
* @param[out] pResult maximum value returned here
|
||||
* @param[out] pIndex index of maximum value returned here
|
||||
*/
|
||||
void arm_absmax_f64(
|
||||
const float64_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float64_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Maximum value of absolute values of a floating-point vector.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[in] blockSize length of the input vector
|
||||
* @param[out] pResult maximum value returned here
|
||||
*/
|
||||
void arm_absmax_no_idx_f64(
|
||||
const float64_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float64_t * pResult);
|
||||
|
||||
/**
|
||||
@brief Maximum value of a floating-point vector.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[in] blockSize number of samples in input vector
|
||||
@param[out] pResult maximum value returned here
|
||||
@return none
|
||||
*/
|
||||
void arm_max_no_idx_f32(
|
||||
const float32_t *pSrc,
|
||||
uint32_t blockSize,
|
||||
float32_t *pResult);
|
||||
|
||||
/**
|
||||
@brief Minimum value of a floating-point vector.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[in] blockSize number of samples in input vector
|
||||
@param[out] pResult minimum value returned here
|
||||
@return none
|
||||
*/
|
||||
void arm_min_no_idx_f32(
|
||||
const float32_t *pSrc,
|
||||
uint32_t blockSize,
|
||||
float32_t *pResult);
|
||||
|
||||
/**
|
||||
@brief Maximum value of a floating-point vector.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[in] blockSize number of samples in input vector
|
||||
@param[out] pResult maximum value returned here
|
||||
@return none
|
||||
*/
|
||||
void arm_max_no_idx_f64(
|
||||
const float64_t *pSrc,
|
||||
uint32_t blockSize,
|
||||
float64_t *pResult);
|
||||
|
||||
/**
|
||||
@brief Maximum value of a q31 vector.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[in] blockSize number of samples in input vector
|
||||
@param[out] pResult maximum value returned here
|
||||
@return none
|
||||
*/
|
||||
void arm_max_no_idx_q31(
|
||||
const q31_t *pSrc,
|
||||
uint32_t blockSize,
|
||||
q31_t *pResult);
|
||||
|
||||
/**
|
||||
@brief Maximum value of a q15 vector.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[in] blockSize number of samples in input vector
|
||||
@param[out] pResult maximum value returned here
|
||||
@return none
|
||||
*/
|
||||
void arm_max_no_idx_q15(
|
||||
const q15_t *pSrc,
|
||||
uint32_t blockSize,
|
||||
q15_t *pResult);
|
||||
|
||||
/**
|
||||
@brief Maximum value of a q7 vector.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[in] blockSize number of samples in input vector
|
||||
@param[out] pResult maximum value returned here
|
||||
@return none
|
||||
*/
|
||||
void arm_max_no_idx_q7(
|
||||
const q7_t *pSrc,
|
||||
uint32_t blockSize,
|
||||
q7_t *pResult);
|
||||
|
||||
/**
|
||||
@brief Minimum value of a floating-point vector.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[in] blockSize number of samples in input vector
|
||||
@param[out] pResult minimum value returned here
|
||||
@return none
|
||||
*/
|
||||
void arm_min_no_idx_f64(
|
||||
const float64_t *pSrc,
|
||||
uint32_t blockSize,
|
||||
float64_t *pResult);
|
||||
|
||||
/**
|
||||
@brief Minimum value of a q31 vector.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[in] blockSize number of samples in input vector
|
||||
@param[out] pResult minimum value returned here
|
||||
@return none
|
||||
*/
|
||||
void arm_min_no_idx_q31(
|
||||
const q31_t *pSrc,
|
||||
uint32_t blockSize,
|
||||
q31_t *pResult);
|
||||
|
||||
/**
|
||||
@brief Minimum value of a q15 vector.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[in] blockSize number of samples in input vector
|
||||
@param[out] pResult minimum value returned here
|
||||
@return none
|
||||
*/
|
||||
void arm_min_no_idx_q15(
|
||||
const q15_t *pSrc,
|
||||
uint32_t blockSize,
|
||||
q15_t *pResult);
|
||||
|
||||
/**
|
||||
@brief Minimum value of a q7 vector.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[in] blockSize number of samples in input vector
|
||||
@param[out] pResult minimum value returned here
|
||||
@return none
|
||||
*/
|
||||
void arm_min_no_idx_q7(
|
||||
const q7_t *pSrc,
|
||||
uint32_t blockSize,
|
||||
q7_t *pResult);
|
||||
|
||||
/**
|
||||
@brief Mean square error between two Q7 vectors.
|
||||
@param[in] pSrcA points to the first input vector
|
||||
@param[in] pSrcB points to the second input vector
|
||||
@param[in] blockSize number of samples in input vector
|
||||
@param[out] pResult mean square error
|
||||
@return none
|
||||
*/
|
||||
|
||||
void arm_mse_q7(
|
||||
const q7_t * pSrcA,
|
||||
const q7_t * pSrcB,
|
||||
uint32_t blockSize,
|
||||
q7_t * pResult);
|
||||
|
||||
/**
|
||||
@brief Mean square error between two Q15 vectors.
|
||||
@param[in] pSrcA points to the first input vector
|
||||
@param[in] pSrcB points to the second input vector
|
||||
@param[in] blockSize number of samples in input vector
|
||||
@param[out] pResult mean square error
|
||||
@return none
|
||||
*/
|
||||
|
||||
void arm_mse_q15(
|
||||
const q15_t * pSrcA,
|
||||
const q15_t * pSrcB,
|
||||
uint32_t blockSize,
|
||||
q15_t * pResult);
|
||||
|
||||
/**
|
||||
@brief Mean square error between two Q31 vectors.
|
||||
@param[in] pSrcA points to the first input vector
|
||||
@param[in] pSrcB points to the second input vector
|
||||
@param[in] blockSize number of samples in input vector
|
||||
@param[out] pResult mean square error
|
||||
@return none
|
||||
*/
|
||||
|
||||
void arm_mse_q31(
|
||||
const q31_t * pSrcA,
|
||||
const q31_t * pSrcB,
|
||||
uint32_t blockSize,
|
||||
q31_t * pResult);
|
||||
|
||||
/**
|
||||
@brief Mean square error between two single precision float vectors.
|
||||
@param[in] pSrcA points to the first input vector
|
||||
@param[in] pSrcB points to the second input vector
|
||||
@param[in] blockSize number of samples in input vector
|
||||
@param[out] pResult mean square error
|
||||
@return none
|
||||
*/
|
||||
|
||||
void arm_mse_f32(
|
||||
const float32_t * pSrcA,
|
||||
const float32_t * pSrcB,
|
||||
uint32_t blockSize,
|
||||
float32_t * pResult);
|
||||
|
||||
/**
|
||||
@brief Mean square error between two double precision float vectors.
|
||||
@param[in] pSrcA points to the first input vector
|
||||
@param[in] pSrcB points to the second input vector
|
||||
@param[in] blockSize number of samples in input vector
|
||||
@param[out] pResult mean square error
|
||||
@return none
|
||||
*/
|
||||
|
||||
void arm_mse_f64(
|
||||
const float64_t * pSrcA,
|
||||
const float64_t * pSrcB,
|
||||
uint32_t blockSize,
|
||||
float64_t * pResult);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _STATISTICS_FUNCTIONS_H_ */
|
||||
|
|
@ -0,0 +1,266 @@
|
|||
/******************************************************************************
|
||||
* @file statistics_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _STATISTICS_FUNCTIONS_F16_H_
|
||||
#define _STATISTICS_FUNCTIONS_F16_H_
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#include "dsp/basic_math_functions_f16.h"
|
||||
#include "dsp/fast_math_functions_f16.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
/**
|
||||
* @brief Sum of the squares of the elements of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_power_f16(
|
||||
const float16_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t * pResult);
|
||||
|
||||
/**
|
||||
* @brief Mean value of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_mean_f16(
|
||||
const float16_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t * pResult);
|
||||
|
||||
/**
|
||||
* @brief Variance of the elements of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_var_f16(
|
||||
const float16_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t * pResult);
|
||||
|
||||
/**
|
||||
* @brief Root Mean Square of the elements of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_rms_f16(
|
||||
const float16_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t * pResult);
|
||||
|
||||
/**
|
||||
* @brief Standard deviation of the elements of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_std_f16(
|
||||
const float16_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t * pResult);
|
||||
|
||||
/**
|
||||
* @brief Minimum value of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output pointer
|
||||
* @param[out] pIndex is the array index of the minimum value in the input buffer.
|
||||
*/
|
||||
void arm_min_f16(
|
||||
const float16_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Minimum value of absolute values of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output pointer
|
||||
* @param[out] pIndex is the array index of the minimum value in the input buffer.
|
||||
*/
|
||||
void arm_absmin_f16(
|
||||
const float16_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Maximum value of a floating-point vector.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[in] blockSize length of the input vector
|
||||
* @param[out] pResult maximum value returned here
|
||||
* @param[out] pIndex index of maximum value returned here
|
||||
*/
|
||||
void arm_max_f16(
|
||||
const float16_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Maximum value of absolute values of a floating-point vector.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[in] blockSize length of the input vector
|
||||
* @param[out] pResult maximum value returned here
|
||||
* @param[out] pIndex index of maximum value returned here
|
||||
*/
|
||||
void arm_absmax_f16(
|
||||
const float16_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Minimum value of absolute values of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output pointer
|
||||
*/
|
||||
void arm_absmin_no_idx_f16(
|
||||
const float16_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t * pResult);
|
||||
|
||||
/**
|
||||
* @brief Maximum value of a floating-point vector.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[in] blockSize length of the input vector
|
||||
* @param[out] pResult maximum value returned here
|
||||
*/
|
||||
void arm_absmax_no_idx_f16(
|
||||
const float16_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Entropy
|
||||
*
|
||||
* @param[in] pSrcA Array of input values.
|
||||
* @param[in] blockSize Number of samples in the input array.
|
||||
* @return Entropy -Sum(p ln p)
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
float16_t arm_entropy_f16(const float16_t * pSrcA,uint32_t blockSize);
|
||||
|
||||
float16_t arm_logsumexp_f16(const float16_t *in, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Dot product with log arithmetic
|
||||
*
|
||||
* Vectors are containing the log of the samples
|
||||
*
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @param[in] pTmpBuffer temporary buffer of length blockSize
|
||||
* @return The log of the dot product .
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
float16_t arm_logsumexp_dot_prod_f16(const float16_t * pSrcA,
|
||||
const float16_t * pSrcB,
|
||||
uint32_t blockSize,
|
||||
float16_t *pTmpBuffer);
|
||||
|
||||
/**
|
||||
* @brief Kullback-Leibler
|
||||
*
|
||||
* @param[in] pSrcA Pointer to an array of input values for probability distribution A.
|
||||
* @param[in] pSrcB Pointer to an array of input values for probability distribution B.
|
||||
* @param[in] blockSize Number of samples in the input array.
|
||||
* @return Kullback-Leibler Divergence D(A || B)
|
||||
*
|
||||
*/
|
||||
float16_t arm_kullback_leibler_f16(const float16_t * pSrcA
|
||||
,const float16_t * pSrcB
|
||||
,uint32_t blockSize);
|
||||
|
||||
/**
|
||||
@brief Maximum value of a floating-point vector.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[in] blockSize number of samples in input vector
|
||||
@param[out] pResult maximum value returned here
|
||||
@return none
|
||||
*/
|
||||
void arm_max_no_idx_f16(
|
||||
const float16_t *pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t *pResult);
|
||||
|
||||
/**
|
||||
@brief Minimum value of a floating-point vector.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[in] blockSize number of samples in input vector
|
||||
@param[out] pResult minimum value returned here
|
||||
@return none
|
||||
*/
|
||||
void arm_min_no_idx_f16(
|
||||
const float16_t *pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t *pResult);
|
||||
|
||||
/**
|
||||
@brief Mean square error between two half precision float vectors.
|
||||
@param[in] pSrcA points to the first input vector
|
||||
@param[in] pSrcB points to the second input vector
|
||||
@param[in] blockSize number of samples in input vector
|
||||
@param[out] pResult mean square error
|
||||
@return none
|
||||
*/
|
||||
|
||||
void arm_mse_f16(
|
||||
const float16_t * pSrcA,
|
||||
const float16_t * pSrcB,
|
||||
uint32_t blockSize,
|
||||
float16_t * pResult);
|
||||
|
||||
#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _STATISTICS_FUNCTIONS_F16_H_ */
|
||||
|
|
@ -0,0 +1,453 @@
|
|||
/******************************************************************************
|
||||
* @file support_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _SUPPORT_FUNCTIONS_H_
|
||||
#define _SUPPORT_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @defgroup groupSupport Support Functions
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the floating-point vector to Q31 vector.
|
||||
* @param[in] pSrc points to the floating-point input vector
|
||||
* @param[out] pDst points to the Q31 output vector
|
||||
* @param[in] blockSize length of the input vector
|
||||
*/
|
||||
void arm_float_to_q31(
|
||||
const float32_t * pSrc,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the floating-point vector to Q15 vector.
|
||||
* @param[in] pSrc points to the floating-point input vector
|
||||
* @param[out] pDst points to the Q15 output vector
|
||||
* @param[in] blockSize length of the input vector
|
||||
*/
|
||||
void arm_float_to_q15(
|
||||
const float32_t * pSrc,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the floating-point vector to Q7 vector.
|
||||
* @param[in] pSrc points to the floating-point input vector
|
||||
* @param[out] pDst points to the Q7 output vector
|
||||
* @param[in] blockSize length of the input vector
|
||||
*/
|
||||
void arm_float_to_q7(
|
||||
const float32_t * pSrc,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the Q31 vector to floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[out] pDst is output pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
*/
|
||||
void arm_q31_to_float(
|
||||
const q31_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the Q31 vector to Q15 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[out] pDst is output pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
*/
|
||||
void arm_q31_to_q15(
|
||||
const q31_t * pSrc,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the Q31 vector to Q7 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[out] pDst is output pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
*/
|
||||
void arm_q31_to_q7(
|
||||
const q31_t * pSrc,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the Q15 vector to floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[out] pDst is output pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
*/
|
||||
void arm_q15_to_float(
|
||||
const q15_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the Q15 vector to Q31 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[out] pDst is output pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
*/
|
||||
void arm_q15_to_q31(
|
||||
const q15_t * pSrc,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the Q15 vector to Q7 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[out] pDst is output pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
*/
|
||||
void arm_q15_to_q7(
|
||||
const q15_t * pSrc,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the Q7 vector to floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[out] pDst is output pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
*/
|
||||
void arm_q7_to_float(
|
||||
const q7_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the Q7 vector to Q31 vector.
|
||||
* @param[in] pSrc input pointer
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_q7_to_q31(
|
||||
const q7_t * pSrc,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the Q7 vector to Q15 vector.
|
||||
* @param[in] pSrc input pointer
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_q7_to_q15(
|
||||
const q7_t * pSrc,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Struct for specifying sorting algorithm
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ARM_SORT_BITONIC = 0,
|
||||
/**< Bitonic sort */
|
||||
ARM_SORT_BUBBLE = 1,
|
||||
/**< Bubble sort */
|
||||
ARM_SORT_HEAP = 2,
|
||||
/**< Heap sort */
|
||||
ARM_SORT_INSERTION = 3,
|
||||
/**< Insertion sort */
|
||||
ARM_SORT_QUICK = 4,
|
||||
/**< Quick sort */
|
||||
ARM_SORT_SELECTION = 5
|
||||
/**< Selection sort */
|
||||
} arm_sort_alg;
|
||||
|
||||
/**
|
||||
* @brief Struct for specifying sorting algorithm
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ARM_SORT_DESCENDING = 0,
|
||||
/**< Descending order (9 to 0) */
|
||||
ARM_SORT_ASCENDING = 1
|
||||
/**< Ascending order (0 to 9) */
|
||||
} arm_sort_dir;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the sorting algorithms.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
arm_sort_alg alg; /**< Sorting algorithm selected */
|
||||
arm_sort_dir dir; /**< Sorting order (direction) */
|
||||
} arm_sort_instance_f32;
|
||||
|
||||
/**
|
||||
* @param[in] S points to an instance of the sorting structure.
|
||||
* @param[in] pSrc points to the block of input data.
|
||||
* @param[out] pDst points to the block of output data.
|
||||
* @param[in] blockSize number of samples to process.
|
||||
*/
|
||||
void arm_sort_f32(
|
||||
const arm_sort_instance_f32 * S,
|
||||
float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @param[in,out] S points to an instance of the sorting structure.
|
||||
* @param[in] alg Selected algorithm.
|
||||
* @param[in] dir Sorting order.
|
||||
*/
|
||||
void arm_sort_init_f32(
|
||||
arm_sort_instance_f32 * S,
|
||||
arm_sort_alg alg,
|
||||
arm_sort_dir dir);
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the sorting algorithms.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
arm_sort_dir dir; /**< Sorting order (direction) */
|
||||
float32_t * buffer; /**< Working buffer */
|
||||
} arm_merge_sort_instance_f32;
|
||||
|
||||
/**
|
||||
* @param[in] S points to an instance of the sorting structure.
|
||||
* @param[in,out] pSrc points to the block of input data.
|
||||
* @param[out] pDst points to the block of output data
|
||||
* @param[in] blockSize number of samples to process.
|
||||
*/
|
||||
void arm_merge_sort_f32(
|
||||
const arm_merge_sort_instance_f32 * S,
|
||||
float32_t *pSrc,
|
||||
float32_t *pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @param[in,out] S points to an instance of the sorting structure.
|
||||
* @param[in] dir Sorting order.
|
||||
* @param[in] buffer Working buffer.
|
||||
*/
|
||||
void arm_merge_sort_init_f32(
|
||||
arm_merge_sort_instance_f32 * S,
|
||||
arm_sort_dir dir,
|
||||
float32_t * buffer);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Copies the elements of a floating-point vector.
|
||||
* @param[in] pSrc input pointer
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_copy_f32(
|
||||
const float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Copies the elements of a floating-point vector.
|
||||
* @param[in] pSrc input pointer
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_copy_f64(
|
||||
const float64_t * pSrc,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Copies the elements of a Q7 vector.
|
||||
* @param[in] pSrc input pointer
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_copy_q7(
|
||||
const q7_t * pSrc,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Copies the elements of a Q15 vector.
|
||||
* @param[in] pSrc input pointer
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_copy_q15(
|
||||
const q15_t * pSrc,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Copies the elements of a Q31 vector.
|
||||
* @param[in] pSrc input pointer
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_copy_q31(
|
||||
const q31_t * pSrc,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Fills a constant value into a floating-point vector.
|
||||
* @param[in] value input value to be filled
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_fill_f32(
|
||||
float32_t value,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Fills a constant value into a floating-point vector.
|
||||
* @param[in] value input value to be filled
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_fill_f64(
|
||||
float64_t value,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Fills a constant value into a Q7 vector.
|
||||
* @param[in] value input value to be filled
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_fill_q7(
|
||||
q7_t value,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Fills a constant value into a Q15 vector.
|
||||
* @param[in] value input value to be filled
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_fill_q15(
|
||||
q15_t value,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Fills a constant value into a Q31 vector.
|
||||
* @param[in] value input value to be filled
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_fill_q31(
|
||||
q31_t value,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Weighted sum
|
||||
*
|
||||
*
|
||||
* @param[in] *in Array of input values.
|
||||
* @param[in] *weigths Weights
|
||||
* @param[in] blockSize Number of samples in the input array.
|
||||
* @return Weighted sum
|
||||
*
|
||||
*/
|
||||
float32_t arm_weighted_sum_f32(const float32_t *in
|
||||
, const float32_t *weigths
|
||||
, uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Barycenter
|
||||
*
|
||||
*
|
||||
* @param[in] in List of vectors
|
||||
* @param[in] weights Weights of the vectors
|
||||
* @param[out] out Barycenter
|
||||
* @param[in] nbVectors Number of vectors
|
||||
* @param[in] vecDim Dimension of space (vector dimension)
|
||||
* @return None
|
||||
*
|
||||
*/
|
||||
void arm_barycenter_f32(const float32_t *in
|
||||
, const float32_t *weights
|
||||
, float32_t *out
|
||||
, uint32_t nbVectors
|
||||
, uint32_t vecDim);
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _SUPPORT_FUNCTIONS_H_ */
|
||||
|
|
@ -0,0 +1,187 @@
|
|||
/******************************************************************************
|
||||
* @file support_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _SUPPORT_FUNCTIONS_F16_H_
|
||||
#define _SUPPORT_FUNCTIONS_F16_H_
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
/**
|
||||
* @brief Copies the elements of a floating-point vector.
|
||||
* @param[in] pSrc input pointer
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_copy_f16(const float16_t * pSrc, float16_t * pDst, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Fills a constant value into a floating-point vector.
|
||||
* @param[in] value input value to be filled
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_fill_f16(float16_t value, float16_t * pDst, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the floating-point vector to Q31 vector.
|
||||
* @param[in] pSrc points to the f16 input vector
|
||||
* @param[out] pDst points to the q15 output vector
|
||||
* @param[in] blockSize length of the input vector
|
||||
*/
|
||||
void arm_f16_to_q15(const float16_t * pSrc, q15_t * pDst, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the floating-point vector to Q31 vector.
|
||||
* @param[in] pSrc points to the q15 input vector
|
||||
* @param[out] pDst points to the f16 output vector
|
||||
* @param[in] blockSize length of the input vector
|
||||
*/
|
||||
void arm_q15_to_f16(const q15_t * pSrc, float16_t * pDst, uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the floating-point vector to Q31 vector.
|
||||
* @param[in] pSrc points to the f32 input vector
|
||||
* @param[out] pDst points to the f16 output vector
|
||||
* @param[in] blockSize length of the input vector
|
||||
*/
|
||||
void arm_float_to_f16(const float32_t * pSrc, float16_t * pDst, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the floating-point vector to Q31 vector.
|
||||
* @param[in] pSrc points to the f16 input vector
|
||||
* @param[out] pDst points to the f32 output vector
|
||||
* @param[in] blockSize length of the input vector
|
||||
*/
|
||||
void arm_f16_to_float(const float16_t * pSrc, float32_t * pDst, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Weighted sum
|
||||
*
|
||||
*
|
||||
* @param[in] *in Array of input values.
|
||||
* @param[in] *weigths Weights
|
||||
* @param[in] blockSize Number of samples in the input array.
|
||||
* @return Weighted sum
|
||||
*
|
||||
*/
|
||||
float16_t arm_weighted_sum_f16(const float16_t *in
|
||||
, const float16_t *weigths
|
||||
, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Barycenter
|
||||
*
|
||||
*
|
||||
* @param[in] in List of vectors
|
||||
* @param[in] weights Weights of the vectors
|
||||
* @param[out] out Barycenter
|
||||
* @param[in] nbVectors Number of vectors
|
||||
* @param[in] vecDim Dimension of space (vector dimension)
|
||||
* @return None
|
||||
*
|
||||
*/
|
||||
void arm_barycenter_f16(const float16_t *in
|
||||
, const float16_t *weights
|
||||
, float16_t *out
|
||||
, uint32_t nbVectors
|
||||
, uint32_t vecDim);
|
||||
|
||||
|
||||
/**
|
||||
@ingroup groupSupport
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup typecast Typecasting
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup typecast
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Interpret a f16 as an s16 value
|
||||
* @param[in] x input value.
|
||||
* @return return value.
|
||||
*
|
||||
* @par Description
|
||||
* It is a typecast. No conversion of the float to int is done.
|
||||
* The memcpy will be optimized out by the compiler.
|
||||
* memcpy is used to prevent type punning issues.
|
||||
* With gcc, -fno-builtins MUST not be used or the
|
||||
* memcpy will not be optimized out.
|
||||
*/
|
||||
__STATIC_INLINE int16_t arm_typecast_s16_f16(float16_t x)
|
||||
{
|
||||
int16_t res;
|
||||
res=*(int16_t*)memcpy((char*)&res,(char*)&x,sizeof(float16_t));
|
||||
return(res);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Interpret an s16 as an f16 value
|
||||
* @param[in] x input value.
|
||||
* @return return value.
|
||||
*
|
||||
* @par Description
|
||||
* It is a typecast. No conversion of the int to float is done.
|
||||
* The memcpy will be optimized out by the compiler.
|
||||
* memcpy is used to prevent type punning issues.
|
||||
* With gcc, -fno-builtins MUST not be used or the
|
||||
* memcpy will not be optimized out.
|
||||
*/
|
||||
__STATIC_INLINE float16_t arm_typecast_f16_s16(int16_t x)
|
||||
{
|
||||
float16_t res;
|
||||
res=*(float16_t*)memcpy((char*)&res,(char*)&x,sizeof(int16_t));
|
||||
return(res);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
@} end of typecast group
|
||||
*/
|
||||
|
||||
|
||||
#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _SUPPORT_FUNCTIONS_F16_H_ */
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
/******************************************************************************
|
||||
* @file svm_defines.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _SVM_DEFINES_H_
|
||||
#define _SVM_DEFINES_H_
|
||||
|
||||
/**
|
||||
* @brief Struct for specifying SVM Kernel
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ARM_ML_KERNEL_LINEAR = 0,
|
||||
/**< Linear kernel */
|
||||
ARM_ML_KERNEL_POLYNOMIAL = 1,
|
||||
/**< Polynomial kernel */
|
||||
ARM_ML_KERNEL_RBF = 2,
|
||||
/**< Radial Basis Function kernel */
|
||||
ARM_ML_KERNEL_SIGMOID = 3
|
||||
/**< Sigmoid kernel */
|
||||
} arm_ml_kernel_type;
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,299 @@
|
|||
/******************************************************************************
|
||||
* @file svm_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _SVM_FUNCTIONS_H_
|
||||
#define _SVM_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
#include "dsp/svm_defines.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#define STEP(x) (x) <= 0 ? 0 : 1
|
||||
|
||||
/**
|
||||
* @defgroup groupSVM SVM Functions
|
||||
* This set of functions is implementing SVM classification on 2 classes.
|
||||
* The training must be done from scikit-learn. The parameters can be easily
|
||||
* generated from the scikit-learn object. Some examples are given in
|
||||
* DSP/Testing/PatternGeneration/SVM.py
|
||||
*
|
||||
* If more than 2 classes are needed, the functions in this folder
|
||||
* will have to be used, as building blocks, to do multi-class classification.
|
||||
*
|
||||
* No multi-class classification is provided in this SVM folder.
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Integer exponentiation
|
||||
* @param[in] x value
|
||||
* @param[in] nb integer exponent >= 1
|
||||
* @return x^nb
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE float32_t arm_exponent_f32(float32_t x, int32_t nb)
|
||||
{
|
||||
float32_t r = x;
|
||||
nb --;
|
||||
while(nb > 0)
|
||||
{
|
||||
r = r * x;
|
||||
nb--;
|
||||
}
|
||||
return(r);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Instance structure for linear SVM prediction function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t nbOfSupportVectors; /**< Number of support vectors */
|
||||
uint32_t vectorDimension; /**< Dimension of vector space */
|
||||
float32_t intercept; /**< Intercept */
|
||||
const float32_t *dualCoefficients; /**< Dual coefficients */
|
||||
const float32_t *supportVectors; /**< Support vectors */
|
||||
const int32_t *classes; /**< The two SVM classes */
|
||||
} arm_svm_linear_instance_f32;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Instance structure for polynomial SVM prediction function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t nbOfSupportVectors; /**< Number of support vectors */
|
||||
uint32_t vectorDimension; /**< Dimension of vector space */
|
||||
float32_t intercept; /**< Intercept */
|
||||
const float32_t *dualCoefficients; /**< Dual coefficients */
|
||||
const float32_t *supportVectors; /**< Support vectors */
|
||||
const int32_t *classes; /**< The two SVM classes */
|
||||
int32_t degree; /**< Polynomial degree */
|
||||
float32_t coef0; /**< Polynomial constant */
|
||||
float32_t gamma; /**< Gamma factor */
|
||||
} arm_svm_polynomial_instance_f32;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for rbf SVM prediction function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t nbOfSupportVectors; /**< Number of support vectors */
|
||||
uint32_t vectorDimension; /**< Dimension of vector space */
|
||||
float32_t intercept; /**< Intercept */
|
||||
const float32_t *dualCoefficients; /**< Dual coefficients */
|
||||
const float32_t *supportVectors; /**< Support vectors */
|
||||
const int32_t *classes; /**< The two SVM classes */
|
||||
float32_t gamma; /**< Gamma factor */
|
||||
} arm_svm_rbf_instance_f32;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for sigmoid SVM prediction function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t nbOfSupportVectors; /**< Number of support vectors */
|
||||
uint32_t vectorDimension; /**< Dimension of vector space */
|
||||
float32_t intercept; /**< Intercept */
|
||||
const float32_t *dualCoefficients; /**< Dual coefficients */
|
||||
const float32_t *supportVectors; /**< Support vectors */
|
||||
const int32_t *classes; /**< The two SVM classes */
|
||||
float32_t coef0; /**< Independent constant */
|
||||
float32_t gamma; /**< Gamma factor */
|
||||
} arm_svm_sigmoid_instance_f32;
|
||||
|
||||
/**
|
||||
* @brief SVM linear instance init function
|
||||
* @param[in] S Parameters for SVM functions
|
||||
* @param[in] nbOfSupportVectors Number of support vectors
|
||||
* @param[in] vectorDimension Dimension of vector space
|
||||
* @param[in] intercept Intercept
|
||||
* @param[in] dualCoefficients Array of dual coefficients
|
||||
* @param[in] supportVectors Array of support vectors
|
||||
* @param[in] classes Array of 2 classes ID
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
void arm_svm_linear_init_f32(arm_svm_linear_instance_f32 *S,
|
||||
uint32_t nbOfSupportVectors,
|
||||
uint32_t vectorDimension,
|
||||
float32_t intercept,
|
||||
const float32_t *dualCoefficients,
|
||||
const float32_t *supportVectors,
|
||||
const int32_t *classes);
|
||||
|
||||
/**
|
||||
* @brief SVM linear prediction
|
||||
* @param[in] S Pointer to an instance of the linear SVM structure.
|
||||
* @param[in] in Pointer to input vector
|
||||
* @param[out] pResult Decision value
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
|
||||
void arm_svm_linear_predict_f32(const arm_svm_linear_instance_f32 *S,
|
||||
const float32_t * in,
|
||||
int32_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief SVM polynomial instance init function
|
||||
* @param[in] S points to an instance of the polynomial SVM structure.
|
||||
* @param[in] nbOfSupportVectors Number of support vectors
|
||||
* @param[in] vectorDimension Dimension of vector space
|
||||
* @param[in] intercept Intercept
|
||||
* @param[in] dualCoefficients Array of dual coefficients
|
||||
* @param[in] supportVectors Array of support vectors
|
||||
* @param[in] classes Array of 2 classes ID
|
||||
* @param[in] degree Polynomial degree
|
||||
* @param[in] coef0 coeff0 (scikit-learn terminology)
|
||||
* @param[in] gamma gamma (scikit-learn terminology)
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
void arm_svm_polynomial_init_f32(arm_svm_polynomial_instance_f32 *S,
|
||||
uint32_t nbOfSupportVectors,
|
||||
uint32_t vectorDimension,
|
||||
float32_t intercept,
|
||||
const float32_t *dualCoefficients,
|
||||
const float32_t *supportVectors,
|
||||
const int32_t *classes,
|
||||
int32_t degree,
|
||||
float32_t coef0,
|
||||
float32_t gamma
|
||||
);
|
||||
|
||||
/**
|
||||
* @brief SVM polynomial prediction
|
||||
* @param[in] S Pointer to an instance of the polynomial SVM structure.
|
||||
* @param[in] in Pointer to input vector
|
||||
* @param[out] pResult Decision value
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
void arm_svm_polynomial_predict_f32(const arm_svm_polynomial_instance_f32 *S,
|
||||
const float32_t * in,
|
||||
int32_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief SVM radial basis function instance init function
|
||||
* @param[in] S points to an instance of the polynomial SVM structure.
|
||||
* @param[in] nbOfSupportVectors Number of support vectors
|
||||
* @param[in] vectorDimension Dimension of vector space
|
||||
* @param[in] intercept Intercept
|
||||
* @param[in] dualCoefficients Array of dual coefficients
|
||||
* @param[in] supportVectors Array of support vectors
|
||||
* @param[in] classes Array of 2 classes ID
|
||||
* @param[in] gamma gamma (scikit-learn terminology)
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
|
||||
void arm_svm_rbf_init_f32(arm_svm_rbf_instance_f32 *S,
|
||||
uint32_t nbOfSupportVectors,
|
||||
uint32_t vectorDimension,
|
||||
float32_t intercept,
|
||||
const float32_t *dualCoefficients,
|
||||
const float32_t *supportVectors,
|
||||
const int32_t *classes,
|
||||
float32_t gamma
|
||||
);
|
||||
|
||||
/**
|
||||
* @brief SVM rbf prediction
|
||||
* @param[in] S Pointer to an instance of the rbf SVM structure.
|
||||
* @param[in] in Pointer to input vector
|
||||
* @param[out] pResult decision value
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
void arm_svm_rbf_predict_f32(const arm_svm_rbf_instance_f32 *S,
|
||||
const float32_t * in,
|
||||
int32_t * pResult);
|
||||
|
||||
/**
|
||||
* @brief SVM sigmoid instance init function
|
||||
* @param[in] S points to an instance of the rbf SVM structure.
|
||||
* @param[in] nbOfSupportVectors Number of support vectors
|
||||
* @param[in] vectorDimension Dimension of vector space
|
||||
* @param[in] intercept Intercept
|
||||
* @param[in] dualCoefficients Array of dual coefficients
|
||||
* @param[in] supportVectors Array of support vectors
|
||||
* @param[in] classes Array of 2 classes ID
|
||||
* @param[in] coef0 coeff0 (scikit-learn terminology)
|
||||
* @param[in] gamma gamma (scikit-learn terminology)
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
|
||||
void arm_svm_sigmoid_init_f32(arm_svm_sigmoid_instance_f32 *S,
|
||||
uint32_t nbOfSupportVectors,
|
||||
uint32_t vectorDimension,
|
||||
float32_t intercept,
|
||||
const float32_t *dualCoefficients,
|
||||
const float32_t *supportVectors,
|
||||
const int32_t *classes,
|
||||
float32_t coef0,
|
||||
float32_t gamma
|
||||
);
|
||||
|
||||
/**
|
||||
* @brief SVM sigmoid prediction
|
||||
* @param[in] S Pointer to an instance of the rbf SVM structure.
|
||||
* @param[in] in Pointer to input vector
|
||||
* @param[out] pResult Decision value
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
void arm_svm_sigmoid_predict_f32(const arm_svm_sigmoid_instance_f32 *S,
|
||||
const float32_t * in,
|
||||
int32_t * pResult);
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _SVM_FUNCTIONS_H_ */
|
||||
|
|
@ -0,0 +1,281 @@
|
|||
/******************************************************************************
|
||||
* @file svm_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _SVM_FUNCTIONS_F16_H_
|
||||
#define _SVM_FUNCTIONS_F16_H_
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
#include "dsp/svm_defines.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
#define STEP(x) (x) <= 0 ? 0 : 1
|
||||
|
||||
/**
|
||||
* @defgroup groupSVM SVM Functions
|
||||
* This set of functions is implementing SVM classification on 2 classes.
|
||||
* The training must be done from scikit-learn. The parameters can be easily
|
||||
* generated from the scikit-learn object. Some examples are given in
|
||||
* DSP/Testing/PatternGeneration/SVM.py
|
||||
*
|
||||
* If more than 2 classes are needed, the functions in this folder
|
||||
* will have to be used, as building blocks, to do multi-class classification.
|
||||
*
|
||||
* No multi-class classification is provided in this SVM folder.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Instance structure for linear SVM prediction function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t nbOfSupportVectors; /**< Number of support vectors */
|
||||
uint32_t vectorDimension; /**< Dimension of vector space */
|
||||
float16_t intercept; /**< Intercept */
|
||||
const float16_t *dualCoefficients; /**< Dual coefficients */
|
||||
const float16_t *supportVectors; /**< Support vectors */
|
||||
const int32_t *classes; /**< The two SVM classes */
|
||||
} arm_svm_linear_instance_f16;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Instance structure for polynomial SVM prediction function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t nbOfSupportVectors; /**< Number of support vectors */
|
||||
uint32_t vectorDimension; /**< Dimension of vector space */
|
||||
float16_t intercept; /**< Intercept */
|
||||
const float16_t *dualCoefficients; /**< Dual coefficients */
|
||||
const float16_t *supportVectors; /**< Support vectors */
|
||||
const int32_t *classes; /**< The two SVM classes */
|
||||
int32_t degree; /**< Polynomial degree */
|
||||
float16_t coef0; /**< Polynomial constant */
|
||||
float16_t gamma; /**< Gamma factor */
|
||||
} arm_svm_polynomial_instance_f16;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for rbf SVM prediction function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t nbOfSupportVectors; /**< Number of support vectors */
|
||||
uint32_t vectorDimension; /**< Dimension of vector space */
|
||||
float16_t intercept; /**< Intercept */
|
||||
const float16_t *dualCoefficients; /**< Dual coefficients */
|
||||
const float16_t *supportVectors; /**< Support vectors */
|
||||
const int32_t *classes; /**< The two SVM classes */
|
||||
float16_t gamma; /**< Gamma factor */
|
||||
} arm_svm_rbf_instance_f16;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for sigmoid SVM prediction function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t nbOfSupportVectors; /**< Number of support vectors */
|
||||
uint32_t vectorDimension; /**< Dimension of vector space */
|
||||
float16_t intercept; /**< Intercept */
|
||||
const float16_t *dualCoefficients; /**< Dual coefficients */
|
||||
const float16_t *supportVectors; /**< Support vectors */
|
||||
const int32_t *classes; /**< The two SVM classes */
|
||||
float16_t coef0; /**< Independent constant */
|
||||
float16_t gamma; /**< Gamma factor */
|
||||
} arm_svm_sigmoid_instance_f16;
|
||||
|
||||
/**
|
||||
* @brief SVM linear instance init function
|
||||
* @param[in] S Parameters for SVM functions
|
||||
* @param[in] nbOfSupportVectors Number of support vectors
|
||||
* @param[in] vectorDimension Dimension of vector space
|
||||
* @param[in] intercept Intercept
|
||||
* @param[in] dualCoefficients Array of dual coefficients
|
||||
* @param[in] supportVectors Array of support vectors
|
||||
* @param[in] classes Array of 2 classes ID
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
void arm_svm_linear_init_f16(arm_svm_linear_instance_f16 *S,
|
||||
uint32_t nbOfSupportVectors,
|
||||
uint32_t vectorDimension,
|
||||
float16_t intercept,
|
||||
const float16_t *dualCoefficients,
|
||||
const float16_t *supportVectors,
|
||||
const int32_t *classes);
|
||||
|
||||
/**
|
||||
* @brief SVM linear prediction
|
||||
* @param[in] S Pointer to an instance of the linear SVM structure.
|
||||
* @param[in] in Pointer to input vector
|
||||
* @param[out] pResult Decision value
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
|
||||
void arm_svm_linear_predict_f16(const arm_svm_linear_instance_f16 *S,
|
||||
const float16_t * in,
|
||||
int32_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief SVM polynomial instance init function
|
||||
* @param[in] S points to an instance of the polynomial SVM structure.
|
||||
* @param[in] nbOfSupportVectors Number of support vectors
|
||||
* @param[in] vectorDimension Dimension of vector space
|
||||
* @param[in] intercept Intercept
|
||||
* @param[in] dualCoefficients Array of dual coefficients
|
||||
* @param[in] supportVectors Array of support vectors
|
||||
* @param[in] classes Array of 2 classes ID
|
||||
* @param[in] degree Polynomial degree
|
||||
* @param[in] coef0 coeff0 (scikit-learn terminology)
|
||||
* @param[in] gamma gamma (scikit-learn terminology)
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
void arm_svm_polynomial_init_f16(arm_svm_polynomial_instance_f16 *S,
|
||||
uint32_t nbOfSupportVectors,
|
||||
uint32_t vectorDimension,
|
||||
float16_t intercept,
|
||||
const float16_t *dualCoefficients,
|
||||
const float16_t *supportVectors,
|
||||
const int32_t *classes,
|
||||
int32_t degree,
|
||||
float16_t coef0,
|
||||
float16_t gamma
|
||||
);
|
||||
|
||||
/**
|
||||
* @brief SVM polynomial prediction
|
||||
* @param[in] S Pointer to an instance of the polynomial SVM structure.
|
||||
* @param[in] in Pointer to input vector
|
||||
* @param[out] pResult Decision value
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
void arm_svm_polynomial_predict_f16(const arm_svm_polynomial_instance_f16 *S,
|
||||
const float16_t * in,
|
||||
int32_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief SVM radial basis function instance init function
|
||||
* @param[in] S points to an instance of the polynomial SVM structure.
|
||||
* @param[in] nbOfSupportVectors Number of support vectors
|
||||
* @param[in] vectorDimension Dimension of vector space
|
||||
* @param[in] intercept Intercept
|
||||
* @param[in] dualCoefficients Array of dual coefficients
|
||||
* @param[in] supportVectors Array of support vectors
|
||||
* @param[in] classes Array of 2 classes ID
|
||||
* @param[in] gamma gamma (scikit-learn terminology)
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
|
||||
void arm_svm_rbf_init_f16(arm_svm_rbf_instance_f16 *S,
|
||||
uint32_t nbOfSupportVectors,
|
||||
uint32_t vectorDimension,
|
||||
float16_t intercept,
|
||||
const float16_t *dualCoefficients,
|
||||
const float16_t *supportVectors,
|
||||
const int32_t *classes,
|
||||
float16_t gamma
|
||||
);
|
||||
|
||||
/**
|
||||
* @brief SVM rbf prediction
|
||||
* @param[in] S Pointer to an instance of the rbf SVM structure.
|
||||
* @param[in] in Pointer to input vector
|
||||
* @param[out] pResult decision value
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
void arm_svm_rbf_predict_f16(const arm_svm_rbf_instance_f16 *S,
|
||||
const float16_t * in,
|
||||
int32_t * pResult);
|
||||
|
||||
/**
|
||||
* @brief SVM sigmoid instance init function
|
||||
* @param[in] S points to an instance of the rbf SVM structure.
|
||||
* @param[in] nbOfSupportVectors Number of support vectors
|
||||
* @param[in] vectorDimension Dimension of vector space
|
||||
* @param[in] intercept Intercept
|
||||
* @param[in] dualCoefficients Array of dual coefficients
|
||||
* @param[in] supportVectors Array of support vectors
|
||||
* @param[in] classes Array of 2 classes ID
|
||||
* @param[in] coef0 coeff0 (scikit-learn terminology)
|
||||
* @param[in] gamma gamma (scikit-learn terminology)
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
|
||||
void arm_svm_sigmoid_init_f16(arm_svm_sigmoid_instance_f16 *S,
|
||||
uint32_t nbOfSupportVectors,
|
||||
uint32_t vectorDimension,
|
||||
float16_t intercept,
|
||||
const float16_t *dualCoefficients,
|
||||
const float16_t *supportVectors,
|
||||
const int32_t *classes,
|
||||
float16_t coef0,
|
||||
float16_t gamma
|
||||
);
|
||||
|
||||
/**
|
||||
* @brief SVM sigmoid prediction
|
||||
* @param[in] S Pointer to an instance of the rbf SVM structure.
|
||||
* @param[in] in Pointer to input vector
|
||||
* @param[out] pResult Decision value
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
void arm_svm_sigmoid_predict_f16(const arm_svm_sigmoid_instance_f16 *S,
|
||||
const float16_t * in,
|
||||
int32_t * pResult);
|
||||
|
||||
|
||||
|
||||
#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _SVM_FUNCTIONS_F16_H_ */
|
||||
|
|
@ -0,0 +1,735 @@
|
|||
/******************************************************************************
|
||||
* @file transform_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _TRANSFORM_FUNCTIONS_H_
|
||||
#define _TRANSFORM_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#include "dsp/basic_math_functions.h"
|
||||
#include "dsp/complex_math_functions.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup groupTransforms Transform Functions
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Q15 CFFT/CIFFT function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t fftLen; /**< length of the FFT. */
|
||||
uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
|
||||
uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
|
||||
const q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
|
||||
const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
|
||||
uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
|
||||
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
|
||||
} arm_cfft_radix2_instance_q15;
|
||||
|
||||
/* Deprecated */
|
||||
arm_status arm_cfft_radix2_init_q15(
|
||||
arm_cfft_radix2_instance_q15 * S,
|
||||
uint16_t fftLen,
|
||||
uint8_t ifftFlag,
|
||||
uint8_t bitReverseFlag);
|
||||
|
||||
/* Deprecated */
|
||||
void arm_cfft_radix2_q15(
|
||||
const arm_cfft_radix2_instance_q15 * S,
|
||||
q15_t * pSrc);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Q15 CFFT/CIFFT function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t fftLen; /**< length of the FFT. */
|
||||
uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
|
||||
uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
|
||||
const q15_t *pTwiddle; /**< points to the twiddle factor table. */
|
||||
const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
|
||||
uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
|
||||
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
|
||||
} arm_cfft_radix4_instance_q15;
|
||||
|
||||
/* Deprecated */
|
||||
arm_status arm_cfft_radix4_init_q15(
|
||||
arm_cfft_radix4_instance_q15 * S,
|
||||
uint16_t fftLen,
|
||||
uint8_t ifftFlag,
|
||||
uint8_t bitReverseFlag);
|
||||
|
||||
/* Deprecated */
|
||||
void arm_cfft_radix4_q15(
|
||||
const arm_cfft_radix4_instance_q15 * S,
|
||||
q15_t * pSrc);
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t fftLen; /**< length of the FFT. */
|
||||
uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
|
||||
uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
|
||||
const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
|
||||
const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
|
||||
uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
|
||||
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
|
||||
} arm_cfft_radix2_instance_q31;
|
||||
|
||||
/* Deprecated */
|
||||
arm_status arm_cfft_radix2_init_q31(
|
||||
arm_cfft_radix2_instance_q31 * S,
|
||||
uint16_t fftLen,
|
||||
uint8_t ifftFlag,
|
||||
uint8_t bitReverseFlag);
|
||||
|
||||
/* Deprecated */
|
||||
void arm_cfft_radix2_q31(
|
||||
const arm_cfft_radix2_instance_q31 * S,
|
||||
q31_t * pSrc);
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Q31 CFFT/CIFFT function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t fftLen; /**< length of the FFT. */
|
||||
uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
|
||||
uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
|
||||
const q31_t *pTwiddle; /**< points to the twiddle factor table. */
|
||||
const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
|
||||
uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
|
||||
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
|
||||
} arm_cfft_radix4_instance_q31;
|
||||
|
||||
/* Deprecated */
|
||||
void arm_cfft_radix4_q31(
|
||||
const arm_cfft_radix4_instance_q31 * S,
|
||||
q31_t * pSrc);
|
||||
|
||||
/* Deprecated */
|
||||
arm_status arm_cfft_radix4_init_q31(
|
||||
arm_cfft_radix4_instance_q31 * S,
|
||||
uint16_t fftLen,
|
||||
uint8_t ifftFlag,
|
||||
uint8_t bitReverseFlag);
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point CFFT/CIFFT function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t fftLen; /**< length of the FFT. */
|
||||
uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
|
||||
uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
|
||||
const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
|
||||
const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
|
||||
uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
|
||||
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
|
||||
float32_t onebyfftLen; /**< value of 1/fftLen. */
|
||||
} arm_cfft_radix2_instance_f32;
|
||||
|
||||
|
||||
/* Deprecated */
|
||||
arm_status arm_cfft_radix2_init_f32(
|
||||
arm_cfft_radix2_instance_f32 * S,
|
||||
uint16_t fftLen,
|
||||
uint8_t ifftFlag,
|
||||
uint8_t bitReverseFlag);
|
||||
|
||||
/* Deprecated */
|
||||
void arm_cfft_radix2_f32(
|
||||
const arm_cfft_radix2_instance_f32 * S,
|
||||
float32_t * pSrc);
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point CFFT/CIFFT function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t fftLen; /**< length of the FFT. */
|
||||
uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
|
||||
uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
|
||||
const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
|
||||
const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
|
||||
uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
|
||||
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
|
||||
float32_t onebyfftLen; /**< value of 1/fftLen. */
|
||||
} arm_cfft_radix4_instance_f32;
|
||||
|
||||
|
||||
|
||||
/* Deprecated */
|
||||
arm_status arm_cfft_radix4_init_f32(
|
||||
arm_cfft_radix4_instance_f32 * S,
|
||||
uint16_t fftLen,
|
||||
uint8_t ifftFlag,
|
||||
uint8_t bitReverseFlag);
|
||||
|
||||
/* Deprecated */
|
||||
void arm_cfft_radix4_f32(
|
||||
const arm_cfft_radix4_instance_f32 * S,
|
||||
float32_t * pSrc);
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the fixed-point CFFT/CIFFT function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t fftLen; /**< length of the FFT. */
|
||||
const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
|
||||
const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
|
||||
uint16_t bitRevLength; /**< bit reversal table length. */
|
||||
#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \
|
||||
const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \
|
||||
const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \
|
||||
const q15_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \
|
||||
const q15_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \
|
||||
const q15_t *rearranged_twiddle_stride3;
|
||||
#endif
|
||||
} arm_cfft_instance_q15;
|
||||
|
||||
arm_status arm_cfft_init_q15(
|
||||
arm_cfft_instance_q15 * S,
|
||||
uint16_t fftLen);
|
||||
|
||||
void arm_cfft_q15(
|
||||
const arm_cfft_instance_q15 * S,
|
||||
q15_t * p1,
|
||||
uint8_t ifftFlag,
|
||||
uint8_t bitReverseFlag);
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the fixed-point CFFT/CIFFT function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t fftLen; /**< length of the FFT. */
|
||||
const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
|
||||
const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
|
||||
uint16_t bitRevLength; /**< bit reversal table length. */
|
||||
#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \
|
||||
const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \
|
||||
const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \
|
||||
const q31_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \
|
||||
const q31_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \
|
||||
const q31_t *rearranged_twiddle_stride3;
|
||||
#endif
|
||||
} arm_cfft_instance_q31;
|
||||
|
||||
arm_status arm_cfft_init_q31(
|
||||
arm_cfft_instance_q31 * S,
|
||||
uint16_t fftLen);
|
||||
|
||||
void arm_cfft_q31(
|
||||
const arm_cfft_instance_q31 * S,
|
||||
q31_t * p1,
|
||||
uint8_t ifftFlag,
|
||||
uint8_t bitReverseFlag);
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point CFFT/CIFFT function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t fftLen; /**< length of the FFT. */
|
||||
const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
|
||||
const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
|
||||
uint16_t bitRevLength; /**< bit reversal table length. */
|
||||
#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \
|
||||
const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \
|
||||
const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \
|
||||
const float32_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \
|
||||
const float32_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \
|
||||
const float32_t *rearranged_twiddle_stride3;
|
||||
#endif
|
||||
} arm_cfft_instance_f32;
|
||||
|
||||
|
||||
|
||||
arm_status arm_cfft_init_f32(
|
||||
arm_cfft_instance_f32 * S,
|
||||
uint16_t fftLen);
|
||||
|
||||
void arm_cfft_f32(
|
||||
const arm_cfft_instance_f32 * S,
|
||||
float32_t * p1,
|
||||
uint8_t ifftFlag,
|
||||
uint8_t bitReverseFlag);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Double Precision Floating-point CFFT/CIFFT function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t fftLen; /**< length of the FFT. */
|
||||
const float64_t *pTwiddle; /**< points to the Twiddle factor table. */
|
||||
const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
|
||||
uint16_t bitRevLength; /**< bit reversal table length. */
|
||||
} arm_cfft_instance_f64;
|
||||
|
||||
arm_status arm_cfft_init_f64(
|
||||
arm_cfft_instance_f64 * S,
|
||||
uint16_t fftLen);
|
||||
|
||||
void arm_cfft_f64(
|
||||
const arm_cfft_instance_f64 * S,
|
||||
float64_t * p1,
|
||||
uint8_t ifftFlag,
|
||||
uint8_t bitReverseFlag);
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Q15 RFFT/RIFFT function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t fftLenReal; /**< length of the real FFT. */
|
||||
uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
|
||||
uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
|
||||
uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
|
||||
const q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
|
||||
const q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
|
||||
#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
arm_cfft_instance_q15 cfftInst;
|
||||
#else
|
||||
const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
|
||||
#endif
|
||||
} arm_rfft_instance_q15;
|
||||
|
||||
arm_status arm_rfft_init_q15(
|
||||
arm_rfft_instance_q15 * S,
|
||||
uint32_t fftLenReal,
|
||||
uint32_t ifftFlagR,
|
||||
uint32_t bitReverseFlag);
|
||||
|
||||
void arm_rfft_q15(
|
||||
const arm_rfft_instance_q15 * S,
|
||||
q15_t * pSrc,
|
||||
q15_t * pDst);
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Q31 RFFT/RIFFT function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t fftLenReal; /**< length of the real FFT. */
|
||||
uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
|
||||
uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
|
||||
uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
|
||||
const q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
|
||||
const q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
|
||||
#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
arm_cfft_instance_q31 cfftInst;
|
||||
#else
|
||||
const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
|
||||
#endif
|
||||
} arm_rfft_instance_q31;
|
||||
|
||||
arm_status arm_rfft_init_q31(
|
||||
arm_rfft_instance_q31 * S,
|
||||
uint32_t fftLenReal,
|
||||
uint32_t ifftFlagR,
|
||||
uint32_t bitReverseFlag);
|
||||
|
||||
void arm_rfft_q31(
|
||||
const arm_rfft_instance_q31 * S,
|
||||
q31_t * pSrc,
|
||||
q31_t * pDst);
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point RFFT/RIFFT function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t fftLenReal; /**< length of the real FFT. */
|
||||
uint16_t fftLenBy2; /**< length of the complex FFT. */
|
||||
uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
|
||||
uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
|
||||
uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
|
||||
const float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
|
||||
const float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
|
||||
arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
|
||||
} arm_rfft_instance_f32;
|
||||
|
||||
arm_status arm_rfft_init_f32(
|
||||
arm_rfft_instance_f32 * S,
|
||||
arm_cfft_radix4_instance_f32 * S_CFFT,
|
||||
uint32_t fftLenReal,
|
||||
uint32_t ifftFlagR,
|
||||
uint32_t bitReverseFlag);
|
||||
|
||||
void arm_rfft_f32(
|
||||
const arm_rfft_instance_f32 * S,
|
||||
float32_t * pSrc,
|
||||
float32_t * pDst);
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Double Precision Floating-point RFFT/RIFFT function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
arm_cfft_instance_f64 Sint; /**< Internal CFFT structure. */
|
||||
uint16_t fftLenRFFT; /**< length of the real sequence */
|
||||
const float64_t * pTwiddleRFFT; /**< Twiddle factors real stage */
|
||||
} arm_rfft_fast_instance_f64 ;
|
||||
|
||||
arm_status arm_rfft_fast_init_f64 (
|
||||
arm_rfft_fast_instance_f64 * S,
|
||||
uint16_t fftLen);
|
||||
|
||||
|
||||
void arm_rfft_fast_f64(
|
||||
arm_rfft_fast_instance_f64 * S,
|
||||
float64_t * p, float64_t * pOut,
|
||||
uint8_t ifftFlag);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point RFFT/RIFFT function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
|
||||
uint16_t fftLenRFFT; /**< length of the real sequence */
|
||||
const float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
|
||||
} arm_rfft_fast_instance_f32 ;
|
||||
|
||||
arm_status arm_rfft_fast_init_f32 (
|
||||
arm_rfft_fast_instance_f32 * S,
|
||||
uint16_t fftLen);
|
||||
|
||||
|
||||
void arm_rfft_fast_f32(
|
||||
const arm_rfft_fast_instance_f32 * S,
|
||||
float32_t * p, float32_t * pOut,
|
||||
uint8_t ifftFlag);
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point DCT4/IDCT4 function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t N; /**< length of the DCT4. */
|
||||
uint16_t Nby2; /**< half of the length of the DCT4. */
|
||||
float32_t normalize; /**< normalizing factor. */
|
||||
const float32_t *pTwiddle; /**< points to the twiddle factor table. */
|
||||
const float32_t *pCosFactor; /**< points to the cosFactor table. */
|
||||
arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
|
||||
arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
|
||||
} arm_dct4_instance_f32;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initialization function for the floating-point DCT4/IDCT4.
|
||||
* @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
|
||||
* @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
|
||||
* @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
|
||||
* @param[in] N length of the DCT4.
|
||||
* @param[in] Nby2 half of the length of the DCT4.
|
||||
* @param[in] normalize normalizing factor.
|
||||
* @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
|
||||
*/
|
||||
arm_status arm_dct4_init_f32(
|
||||
arm_dct4_instance_f32 * S,
|
||||
arm_rfft_instance_f32 * S_RFFT,
|
||||
arm_cfft_radix4_instance_f32 * S_CFFT,
|
||||
uint16_t N,
|
||||
uint16_t Nby2,
|
||||
float32_t normalize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Processing function for the floating-point DCT4/IDCT4.
|
||||
* @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
|
||||
* @param[in] pState points to state buffer.
|
||||
* @param[in,out] pInlineBuffer points to the in-place input and output buffer.
|
||||
*/
|
||||
void arm_dct4_f32(
|
||||
const arm_dct4_instance_f32 * S,
|
||||
float32_t * pState,
|
||||
float32_t * pInlineBuffer);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Q31 DCT4/IDCT4 function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t N; /**< length of the DCT4. */
|
||||
uint16_t Nby2; /**< half of the length of the DCT4. */
|
||||
q31_t normalize; /**< normalizing factor. */
|
||||
const q31_t *pTwiddle; /**< points to the twiddle factor table. */
|
||||
const q31_t *pCosFactor; /**< points to the cosFactor table. */
|
||||
arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
|
||||
arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
|
||||
} arm_dct4_instance_q31;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initialization function for the Q31 DCT4/IDCT4.
|
||||
* @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
|
||||
* @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
|
||||
* @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
|
||||
* @param[in] N length of the DCT4.
|
||||
* @param[in] Nby2 half of the length of the DCT4.
|
||||
* @param[in] normalize normalizing factor.
|
||||
* @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
|
||||
*/
|
||||
arm_status arm_dct4_init_q31(
|
||||
arm_dct4_instance_q31 * S,
|
||||
arm_rfft_instance_q31 * S_RFFT,
|
||||
arm_cfft_radix4_instance_q31 * S_CFFT,
|
||||
uint16_t N,
|
||||
uint16_t Nby2,
|
||||
q31_t normalize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Processing function for the Q31 DCT4/IDCT4.
|
||||
* @param[in] S points to an instance of the Q31 DCT4 structure.
|
||||
* @param[in] pState points to state buffer.
|
||||
* @param[in,out] pInlineBuffer points to the in-place input and output buffer.
|
||||
*/
|
||||
void arm_dct4_q31(
|
||||
const arm_dct4_instance_q31 * S,
|
||||
q31_t * pState,
|
||||
q31_t * pInlineBuffer);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Q15 DCT4/IDCT4 function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t N; /**< length of the DCT4. */
|
||||
uint16_t Nby2; /**< half of the length of the DCT4. */
|
||||
q15_t normalize; /**< normalizing factor. */
|
||||
const q15_t *pTwiddle; /**< points to the twiddle factor table. */
|
||||
const q15_t *pCosFactor; /**< points to the cosFactor table. */
|
||||
arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
|
||||
arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
|
||||
} arm_dct4_instance_q15;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initialization function for the Q15 DCT4/IDCT4.
|
||||
* @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
|
||||
* @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
|
||||
* @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
|
||||
* @param[in] N length of the DCT4.
|
||||
* @param[in] Nby2 half of the length of the DCT4.
|
||||
* @param[in] normalize normalizing factor.
|
||||
* @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
|
||||
*/
|
||||
arm_status arm_dct4_init_q15(
|
||||
arm_dct4_instance_q15 * S,
|
||||
arm_rfft_instance_q15 * S_RFFT,
|
||||
arm_cfft_radix4_instance_q15 * S_CFFT,
|
||||
uint16_t N,
|
||||
uint16_t Nby2,
|
||||
q15_t normalize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Processing function for the Q15 DCT4/IDCT4.
|
||||
* @param[in] S points to an instance of the Q15 DCT4 structure.
|
||||
* @param[in] pState points to state buffer.
|
||||
* @param[in,out] pInlineBuffer points to the in-place input and output buffer.
|
||||
*/
|
||||
void arm_dct4_q15(
|
||||
const arm_dct4_instance_q15 * S,
|
||||
q15_t * pState,
|
||||
q15_t * pInlineBuffer);
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Floating-point MFCC function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
const float32_t *dctCoefs; /**< Internal DCT coefficients */
|
||||
const float32_t *filterCoefs; /**< Internal Mel filter coefficients */
|
||||
const float32_t *windowCoefs; /**< Windowing coefficients */
|
||||
const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */
|
||||
const uint32_t *filterLengths; /**< Internal Mel filter lengths */
|
||||
uint32_t fftLen; /**< FFT length */
|
||||
uint32_t nbMelFilters; /**< Number of Mel filters */
|
||||
uint32_t nbDctOutputs; /**< Number of DCT outputs */
|
||||
#if defined(ARM_MFCC_CFFT_BASED)
|
||||
/* Implementation of the MFCC is using a CFFT */
|
||||
arm_cfft_instance_f32 cfft; /**< Internal CFFT instance */
|
||||
#else
|
||||
/* Implementation of the MFCC is using a RFFT (default) */
|
||||
arm_rfft_fast_instance_f32 rfft;
|
||||
#endif
|
||||
} arm_mfcc_instance_f32 ;
|
||||
|
||||
arm_status arm_mfcc_init_f32(
|
||||
arm_mfcc_instance_f32 * S,
|
||||
uint32_t fftLen,
|
||||
uint32_t nbMelFilters,
|
||||
uint32_t nbDctOutputs,
|
||||
const float32_t *dctCoefs,
|
||||
const uint32_t *filterPos,
|
||||
const uint32_t *filterLengths,
|
||||
const float32_t *filterCoefs,
|
||||
const float32_t *windowCoefs
|
||||
);
|
||||
|
||||
|
||||
/**
|
||||
@brief MFCC F32
|
||||
@param[in] S points to the mfcc instance structure
|
||||
@param[in] pSrc points to the input samples
|
||||
@param[out] pDst points to the output MFCC values
|
||||
@param[inout] pTmp points to a temporary buffer of complex
|
||||
@return none
|
||||
*/
|
||||
void arm_mfcc_f32(
|
||||
const arm_mfcc_instance_f32 * S,
|
||||
float32_t *pSrc,
|
||||
float32_t *pDst,
|
||||
float32_t *pTmp
|
||||
);
|
||||
|
||||
typedef struct
|
||||
{
|
||||
const q31_t *dctCoefs; /**< Internal DCT coefficients */
|
||||
const q31_t *filterCoefs; /**< Internal Mel filter coefficients */
|
||||
const q31_t *windowCoefs; /**< Windowing coefficients */
|
||||
const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */
|
||||
const uint32_t *filterLengths; /**< Internal Mel filter lengths */
|
||||
uint32_t fftLen; /**< FFT length */
|
||||
uint32_t nbMelFilters; /**< Number of Mel filters */
|
||||
uint32_t nbDctOutputs; /**< Number of DCT outputs */
|
||||
#if defined(ARM_MFCC_CFFT_BASED)
|
||||
/* Implementation of the MFCC is using a CFFT */
|
||||
arm_cfft_instance_q31 cfft; /**< Internal CFFT instance */
|
||||
#else
|
||||
/* Implementation of the MFCC is using a RFFT (default) */
|
||||
arm_rfft_instance_q31 rfft;
|
||||
#endif
|
||||
} arm_mfcc_instance_q31 ;
|
||||
|
||||
arm_status arm_mfcc_init_q31(
|
||||
arm_mfcc_instance_q31 * S,
|
||||
uint32_t fftLen,
|
||||
uint32_t nbMelFilters,
|
||||
uint32_t nbDctOutputs,
|
||||
const q31_t *dctCoefs,
|
||||
const uint32_t *filterPos,
|
||||
const uint32_t *filterLengths,
|
||||
const q31_t *filterCoefs,
|
||||
const q31_t *windowCoefs
|
||||
);
|
||||
|
||||
|
||||
/**
|
||||
@brief MFCC Q31
|
||||
@param[in] S points to the mfcc instance structure
|
||||
@param[in] pSrc points to the input samples
|
||||
@param[out] pDst points to the output MFCC values
|
||||
@param[inout] pTmp points to a temporary buffer of complex
|
||||
@return none
|
||||
*/
|
||||
arm_status arm_mfcc_q31(
|
||||
const arm_mfcc_instance_q31 * S,
|
||||
q31_t *pSrc,
|
||||
q31_t *pDst,
|
||||
q31_t *pTmp
|
||||
);
|
||||
|
||||
typedef struct
|
||||
{
|
||||
const q15_t *dctCoefs; /**< Internal DCT coefficients */
|
||||
const q15_t *filterCoefs; /**< Internal Mel filter coefficients */
|
||||
const q15_t *windowCoefs; /**< Windowing coefficients */
|
||||
const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */
|
||||
const uint32_t *filterLengths; /**< Internal Mel filter lengths */
|
||||
uint32_t fftLen; /**< FFT length */
|
||||
uint32_t nbMelFilters; /**< Number of Mel filters */
|
||||
uint32_t nbDctOutputs; /**< Number of DCT outputs */
|
||||
#if defined(ARM_MFCC_CFFT_BASED)
|
||||
/* Implementation of the MFCC is using a CFFT */
|
||||
arm_cfft_instance_q15 cfft; /**< Internal CFFT instance */
|
||||
#else
|
||||
/* Implementation of the MFCC is using a RFFT (default) */
|
||||
arm_rfft_instance_q15 rfft;
|
||||
#endif
|
||||
} arm_mfcc_instance_q15 ;
|
||||
|
||||
arm_status arm_mfcc_init_q15(
|
||||
arm_mfcc_instance_q15 * S,
|
||||
uint32_t fftLen,
|
||||
uint32_t nbMelFilters,
|
||||
uint32_t nbDctOutputs,
|
||||
const q15_t *dctCoefs,
|
||||
const uint32_t *filterPos,
|
||||
const uint32_t *filterLengths,
|
||||
const q15_t *filterCoefs,
|
||||
const q15_t *windowCoefs
|
||||
);
|
||||
|
||||
|
||||
/**
|
||||
@brief MFCC Q15
|
||||
@param[in] S points to the mfcc instance structure
|
||||
@param[in] pSrc points to the input samples
|
||||
@param[out] pDst points to the output MFCC values in q8.7 format
|
||||
@param[inout] pTmp points to a temporary buffer of complex
|
||||
@return error status
|
||||
*/
|
||||
arm_status arm_mfcc_q15(
|
||||
const arm_mfcc_instance_q15 * S,
|
||||
q15_t *pSrc,
|
||||
q15_t *pDst,
|
||||
q31_t *pTmp
|
||||
);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _TRANSFORM_FUNCTIONS_H_ */
|
||||
|
|
@ -0,0 +1,208 @@
|
|||
/******************************************************************************
|
||||
* @file transform_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _TRANSFORM_FUNCTIONS_F16_H_
|
||||
#define _TRANSFORM_FUNCTIONS_F16_H_
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point CFFT/CIFFT function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t fftLen; /**< length of the FFT. */
|
||||
uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
|
||||
uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
|
||||
const float16_t *pTwiddle; /**< points to the Twiddle factor table. */
|
||||
const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
|
||||
uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
|
||||
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
|
||||
float16_t onebyfftLen; /**< value of 1/fftLen. */
|
||||
} arm_cfft_radix2_instance_f16;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point CFFT/CIFFT function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t fftLen; /**< length of the FFT. */
|
||||
uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
|
||||
uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
|
||||
const float16_t *pTwiddle; /**< points to the Twiddle factor table. */
|
||||
const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
|
||||
uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
|
||||
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
|
||||
float16_t onebyfftLen; /**< value of 1/fftLen. */
|
||||
} arm_cfft_radix4_instance_f16;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point CFFT/CIFFT function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t fftLen; /**< length of the FFT. */
|
||||
const float16_t *pTwiddle; /**< points to the Twiddle factor table. */
|
||||
const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
|
||||
uint16_t bitRevLength; /**< bit reversal table length. */
|
||||
#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \
|
||||
const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \
|
||||
const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \
|
||||
const float16_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \
|
||||
const float16_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \
|
||||
const float16_t *rearranged_twiddle_stride3;
|
||||
#endif
|
||||
} arm_cfft_instance_f16;
|
||||
|
||||
|
||||
arm_status arm_cfft_init_f16(
|
||||
arm_cfft_instance_f16 * S,
|
||||
uint16_t fftLen);
|
||||
|
||||
void arm_cfft_f16(
|
||||
const arm_cfft_instance_f16 * S,
|
||||
float16_t * p1,
|
||||
uint8_t ifftFlag,
|
||||
uint8_t bitReverseFlag);
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point RFFT/RIFFT function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
arm_cfft_instance_f16 Sint; /**< Internal CFFT structure. */
|
||||
uint16_t fftLenRFFT; /**< length of the real sequence */
|
||||
const float16_t * pTwiddleRFFT; /**< Twiddle factors real stage */
|
||||
} arm_rfft_fast_instance_f16 ;
|
||||
|
||||
arm_status arm_rfft_fast_init_f16 (
|
||||
arm_rfft_fast_instance_f16 * S,
|
||||
uint16_t fftLen);
|
||||
|
||||
|
||||
void arm_rfft_fast_f16(
|
||||
const arm_rfft_fast_instance_f16 * S,
|
||||
float16_t * p, float16_t * pOut,
|
||||
uint8_t ifftFlag);
|
||||
|
||||
/* Deprecated */
|
||||
arm_status arm_cfft_radix4_init_f16(
|
||||
arm_cfft_radix4_instance_f16 * S,
|
||||
uint16_t fftLen,
|
||||
uint8_t ifftFlag,
|
||||
uint8_t bitReverseFlag);
|
||||
|
||||
/* Deprecated */
|
||||
void arm_cfft_radix4_f16(
|
||||
const arm_cfft_radix4_instance_f16 * S,
|
||||
float16_t * pSrc);
|
||||
|
||||
|
||||
/* Deprecated */
|
||||
arm_status arm_cfft_radix2_init_f16(
|
||||
arm_cfft_radix2_instance_f16 * S,
|
||||
uint16_t fftLen,
|
||||
uint8_t ifftFlag,
|
||||
uint8_t bitReverseFlag);
|
||||
|
||||
/* Deprecated */
|
||||
void arm_cfft_radix2_f16(
|
||||
const arm_cfft_radix2_instance_f16 * S,
|
||||
float16_t * pSrc);
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Floating-point MFCC function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
const float16_t *dctCoefs; /**< Internal DCT coefficients */
|
||||
const float16_t *filterCoefs; /**< Internal Mel filter coefficients */
|
||||
const float16_t *windowCoefs; /**< Windowing coefficients */
|
||||
const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */
|
||||
const uint32_t *filterLengths; /**< Internal Mel filter lengths */
|
||||
uint32_t fftLen; /**< FFT length */
|
||||
uint32_t nbMelFilters; /**< Number of Mel filters */
|
||||
uint32_t nbDctOutputs; /**< Number of DCT outputs */
|
||||
#if defined(ARM_MFCC_CFFT_BASED)
|
||||
/* Implementation of the MFCC is using a CFFT */
|
||||
arm_cfft_instance_f16 cfft; /**< Internal CFFT instance */
|
||||
#else
|
||||
/* Implementation of the MFCC is using a RFFT (default) */
|
||||
arm_rfft_fast_instance_f16 rfft;
|
||||
#endif
|
||||
} arm_mfcc_instance_f16 ;
|
||||
|
||||
arm_status arm_mfcc_init_f16(
|
||||
arm_mfcc_instance_f16 * S,
|
||||
uint32_t fftLen,
|
||||
uint32_t nbMelFilters,
|
||||
uint32_t nbDctOutputs,
|
||||
const float16_t *dctCoefs,
|
||||
const uint32_t *filterPos,
|
||||
const uint32_t *filterLengths,
|
||||
const float16_t *filterCoefs,
|
||||
const float16_t *windowCoefs
|
||||
);
|
||||
|
||||
|
||||
/**
|
||||
@brief MFCC F16
|
||||
@param[in] S points to the mfcc instance structure
|
||||
@param[in] pSrc points to the input samples
|
||||
@param[out] pDst points to the output MFCC values
|
||||
@param[inout] pTmp points to a temporary buffer of complex
|
||||
@return none
|
||||
*/
|
||||
void arm_mfcc_f16(
|
||||
const arm_mfcc_instance_f16 * S,
|
||||
float16_t *pSrc,
|
||||
float16_t *pDst,
|
||||
float16_t *pTmp
|
||||
);
|
||||
|
||||
|
||||
#endif /* defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _TRANSFORM_FUNCTIONS_F16_H_ */
|
||||
|
|
@ -0,0 +1,240 @@
|
|||
/******************************************************************************
|
||||
* @file arm_math_utils.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.9.0
|
||||
* @date 20. July 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_MATH_UTILS_H_
|
||||
|
||||
#define _ARM_MATH_UTILS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Macros required for reciprocal calculation in Normalized LMS
|
||||
*/
|
||||
|
||||
#define INDEX_MASK 0x0000003F
|
||||
|
||||
|
||||
#define SQ(x) ((x) * (x))
|
||||
|
||||
#define ROUND_UP(N, S) ((((N) + (S) - 1) / (S)) * (S))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t arm_recip_q31(
|
||||
q31_t in,
|
||||
q31_t * dst,
|
||||
const q31_t * pRecipTable)
|
||||
{
|
||||
q31_t out;
|
||||
uint32_t tempVal;
|
||||
uint32_t index, i;
|
||||
uint32_t signBits;
|
||||
|
||||
if (in > 0)
|
||||
{
|
||||
signBits = ((uint32_t) (__CLZ( in) - 1));
|
||||
}
|
||||
else
|
||||
{
|
||||
signBits = ((uint32_t) (__CLZ(-in) - 1));
|
||||
}
|
||||
|
||||
/* Convert input sample to 1.31 format */
|
||||
in = (in << signBits);
|
||||
|
||||
/* calculation of index for initial approximated Val */
|
||||
index = (uint32_t)(in >> 24);
|
||||
index = (index & INDEX_MASK);
|
||||
|
||||
/* 1.31 with exp 1 */
|
||||
out = pRecipTable[index];
|
||||
|
||||
/* calculation of reciprocal value */
|
||||
/* running approximation for two iterations */
|
||||
for (i = 0U; i < 2U; i++)
|
||||
{
|
||||
tempVal = (uint32_t) (((q63_t) in * out) >> 31);
|
||||
tempVal = 0x7FFFFFFFu - tempVal;
|
||||
/* 1.31 with exp 1 */
|
||||
/* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
|
||||
out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
|
||||
}
|
||||
|
||||
/* write output */
|
||||
*dst = out;
|
||||
|
||||
/* return num of signbits of out = 1/in value */
|
||||
return (signBits + 1U);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t arm_recip_q15(
|
||||
q15_t in,
|
||||
q15_t * dst,
|
||||
const q15_t * pRecipTable)
|
||||
{
|
||||
q15_t out = 0;
|
||||
uint32_t tempVal = 0;
|
||||
uint32_t index = 0, i = 0;
|
||||
uint32_t signBits = 0;
|
||||
|
||||
if (in > 0)
|
||||
{
|
||||
signBits = ((uint32_t)(__CLZ( in) - 17));
|
||||
}
|
||||
else
|
||||
{
|
||||
signBits = ((uint32_t)(__CLZ(-in) - 17));
|
||||
}
|
||||
|
||||
/* Convert input sample to 1.15 format */
|
||||
in = (in << signBits);
|
||||
|
||||
/* calculation of index for initial approximated Val */
|
||||
index = (uint32_t)(in >> 8);
|
||||
index = (index & INDEX_MASK);
|
||||
|
||||
/* 1.15 with exp 1 */
|
||||
out = pRecipTable[index];
|
||||
|
||||
/* calculation of reciprocal value */
|
||||
/* running approximation for two iterations */
|
||||
for (i = 0U; i < 2U; i++)
|
||||
{
|
||||
tempVal = (uint32_t) (((q31_t) in * out) >> 15);
|
||||
tempVal = 0x7FFFu - tempVal;
|
||||
/* 1.15 with exp 1 */
|
||||
out = (q15_t) (((q31_t) out * tempVal) >> 14);
|
||||
/* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
|
||||
}
|
||||
|
||||
/* write output */
|
||||
*dst = out;
|
||||
|
||||
/* return num of signbits of out = 1/in value */
|
||||
return (signBits + 1);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief 64-bit to 32-bit unsigned normalization
|
||||
* @param[in] in is input unsigned long long value
|
||||
* @param[out] normalized is the 32-bit normalized value
|
||||
* @param[out] norm is norm scale
|
||||
*/
|
||||
__STATIC_INLINE void arm_norm_64_to_32u(uint64_t in, int32_t * normalized, int32_t *norm)
|
||||
{
|
||||
int32_t n1;
|
||||
int32_t hi = (int32_t) (in >> 32);
|
||||
int32_t lo = (int32_t) ((in << 32) >> 32);
|
||||
|
||||
n1 = __CLZ(hi) - 32;
|
||||
if (!n1)
|
||||
{
|
||||
/*
|
||||
* input fits in 32-bit
|
||||
*/
|
||||
n1 = __CLZ(lo);
|
||||
if (!n1)
|
||||
{
|
||||
/*
|
||||
* MSB set, need to scale down by 1
|
||||
*/
|
||||
*norm = -1;
|
||||
*normalized = (((uint32_t) lo) >> 1);
|
||||
} else
|
||||
{
|
||||
if (n1 == 32)
|
||||
{
|
||||
/*
|
||||
* input is zero
|
||||
*/
|
||||
*norm = 0;
|
||||
*normalized = 0;
|
||||
} else
|
||||
{
|
||||
/*
|
||||
* 32-bit normalization
|
||||
*/
|
||||
*norm = n1 - 1;
|
||||
*normalized = lo << *norm;
|
||||
}
|
||||
}
|
||||
} else
|
||||
{
|
||||
/*
|
||||
* input fits in 64-bit
|
||||
*/
|
||||
n1 = 1 - n1;
|
||||
*norm = -n1;
|
||||
/*
|
||||
* 64 bit normalization
|
||||
*/
|
||||
*normalized = (((uint32_t) lo) >> n1) | (hi << (32 - n1));
|
||||
}
|
||||
}
|
||||
|
||||
__STATIC_INLINE q31_t arm_div_q63_to_q31(q63_t num, q31_t den)
|
||||
{
|
||||
q31_t result;
|
||||
uint64_t absNum;
|
||||
int32_t normalized;
|
||||
int32_t norm;
|
||||
|
||||
/*
|
||||
* if sum fits in 32bits
|
||||
* avoid costly 64-bit division
|
||||
*/
|
||||
absNum = num > 0 ? num : -num;
|
||||
arm_norm_64_to_32u(absNum, &normalized, &norm);
|
||||
if (norm > 0)
|
||||
/*
|
||||
* 32-bit division
|
||||
*/
|
||||
result = (q31_t) num / den;
|
||||
else
|
||||
/*
|
||||
* 64-bit division
|
||||
*/
|
||||
result = (q31_t) (num / den);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*ifndef _ARM_MATH_UTILS_H_ */
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
#pragma once
|
||||
|
||||
#define rad60 deg2rad(60)
|
||||
#define SQRT3 1.73205080756887729353
|
||||
#define deg2rad(a) (PI * (a) / 180)
|
||||
#define rad2deg(a) (180 * (a) / PI)
|
||||
#define max(a, b) ((a) > (b) ? (a) : (b))
|
||||
#define min(a, b) ((a) < (b) ? (a) : (b))
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/********************************************
|
||||
* 0 不进行控制
|
||||
* 1 速度环 速度
|
||||
* 2 力矩环 转矩
|
||||
*
|
||||
* 4 位置环 VF
|
||||
* 5 MIT控制 DQ
|
||||
********************************************/
|
||||
typedef enum
|
||||
{
|
||||
control_type_null, // 0不进行控制
|
||||
control_type_speed, // 1速度控制
|
||||
control_type_torque, // 2力矩控制
|
||||
control_type_speed_torque, // 3速度-力矩控制
|
||||
control_type_position, // 4位置控制
|
||||
control_type_mit_control, // 5MIT控制
|
||||
control_type_position_speed_torque, // 位置-速度-力矩控制
|
||||
} motor_control_type;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
motor_idle,
|
||||
motor_running,
|
||||
motor_fault,
|
||||
motor_stall,
|
||||
motor_break
|
||||
} motor_status_e;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
motor_control_type type;
|
||||
float position; // 目标角度，单位度
|
||||
float speed; // 目标速度，单位rad/s
|
||||
float torque_norm_d; // 目标d轴强度，0~1
|
||||
float torque_norm_q; // 目标q轴强度，0~1
|
||||
float max_speed; // 串级控制时的最大速度，单位rad/s
|
||||
float max_torque_norm; // 串级控制时的最大q轴力矩，0~1
|
||||
float pid_value; // PID参数值
|
||||
float mit_kp; //MIT控制kp值
|
||||
float mit_kd; //MIT控制kd值
|
||||
float mit_torque; //MIT控制目标力矩值
|
||||
int control_mode;
|
||||
float pwm_u; //u项占空比
|
||||
int position_reached_flag;
|
||||
int count;
|
||||
} motor_control_context_t;
|
||||
|
||||
extern motor_control_context_t motor_control_context;
|
||||
extern motor_status_e motor_status;
|
||||
|
||||
|
||||
void foc_start();
|
||||
void foc_stop();
|
||||
void foc_break();
|
||||
void foc_loop();
|
||||
float cycle_diff(float diff, float cycle);
|
||||
void foc_forward(float d, float q, float rotor_rad);
|
||||
float cycle_diff(float diff, float cycle);
|
||||
float low_pass_filter(float input, float last_output, float alpha);
|
||||
void TIM_Handler();
|
||||
|
||||
void lib_position_control(float rad);
|
||||
void lib_speed_control(float speed);
|
||||
void lib_torque_control(float torque_norm_d, float torque_norm_q);
|
||||
void lib_speed_torque_control(float speed_rad);
|
||||
void lib_position_speed_torque_control(float position);
|
||||
void lib_mit_control(float pos_des, float vel_des,
|
||||
float kp, float kd, float tau_ff);
|
||||
|
||||
void set_motor_pid(
|
||||
float position_p, float position_i, float position_d,
|
||||
float speed_p, float speed_i, float speed_d,
|
||||
float torque_d_p, float torque_d_i, float torque_d_d,
|
||||
float torque_q_p, float torque_q_i, float torque_q_d);
|
||||
|
||||
|
||||
|
||||
|
||||
typedef struct {
|
||||
float kp;
|
||||
float ki;
|
||||
float kd;
|
||||
float integral;
|
||||
float prev_error;
|
||||
float output_limit;
|
||||
} PID_t;
|
||||
|
||||
// PID 初始化
|
||||
void PID_Init(PID_t *pid, float kp, float ki, float kd, float limit);
|
||||
// PID 计算
|
||||
float PID_Update(PID_t *pid, float error);
|
||||
|
|
@ -5,7 +5,7 @@ MAKEFLAGS += --no-print-directory
|
|||
.PHONY:COMPILE_APP COMPILE_KERNEL
|
||||
|
||||
# search all board support packages
|
||||
support := $(shell find board/ -mindepth 1 -maxdepth 1 -type d -exec basename {} \;)
|
||||
support := $(shell find board* -mindepth 1 -maxdepth 1 -type d -exec basename {} \;)
|
||||
SRC_DIR :=
|
||||
|
||||
export BOARD ?=kd233
|
||||
|
|
@ -17,6 +17,9 @@ $(warning "You should choose board like this:make BOARD=kd233")
|
|||
$(warning "This is what we support:")
|
||||
$(warning "BOARD: $(support)")
|
||||
$(error "break" )
|
||||
else
|
||||
BASE_BOARD_FOLDER := $(shell find board* -mindepth 1 -maxdepth 1 -type d -name $(BOARD) -exec dirname {} \; | head -n 1)
|
||||
BOARD_FOLDER := $(BASE_BOARD_FOLDER)/$(BOARD)
|
||||
endif
|
||||
|
||||
export TARGET
|
||||
|
|
@ -26,10 +29,10 @@ export KERNEL_ROOT ?=$(strip $(shell pwd))
|
|||
MAKEFILES =$(KERNEL_ROOT)/.config
|
||||
-include $(KERNEL_ROOT)/.config
|
||||
|
||||
export BSP_ROOT ?= $(KERNEL_ROOT)/board/$(BOARD)
|
||||
export BSP_ROOT ?= $(KERNEL_ROOT)/$(BOARD_FOLDER)
|
||||
export UBIQUITOUS_ROOT ?= ..
|
||||
include board/$(BOARD)/config.mk
|
||||
export BSP_BUILD_DIR := board/$(BOARD)
|
||||
include $(BOARD_FOLDER)/config.mk
|
||||
export BSP_BUILD_DIR := $(BOARD_FOLDER)
|
||||
export HOSTTOOLS_DIR ?= $(KERNEL_ROOT)/tool/hosttools
|
||||
export CONFIG2H_EXE ?= $(HOSTTOOLS_DIR)/xsconfig.sh
|
||||
|
||||
|
|
@ -38,7 +41,7 @@ export FEATURE2YAML_EXE ?= $(HOSTTOOLS_DIR)/kernel_selector.sh
|
|||
export KSELECTOR_EXE ?= $(HOSTTOOLS_DIR)/kernel_selector.py
|
||||
export CPPPATHS
|
||||
export SRC_APP_DIR := ../../APP_Framework
|
||||
export SRC_KERNEL_DIR := arch board lib fs kernel resources tool
|
||||
export SRC_KERNEL_DIR := arch $(BASE_BOARD_FOLDER) lib fs kernel resources tool
|
||||
export SRC_DIR:= $(SRC_APP_DIR) $(SRC_KERNEL_DIR)
|
||||
export LIBCC
|
||||
export MUSL_DIR := $(KERNEL_ROOT)/lib/musllib
|
||||
|
|
@ -210,4 +213,4 @@ distclean:
|
|||
@rm -f .config*
|
||||
@rm -f $(KERNEL_ROOT)/lib/musllib/libmusl.a
|
||||
@rm -f $(KERNEL_ROOT)/resources/ethernet/LwIP/liblwip.a
|
||||
@rm -f $(KERNEL_ROOT)/board/*/.config
|
||||
@rm -f $(KERNEL_ROOT)/board*/*/.config
|
||||
|
|
|
|||
|
|
@ -50,6 +50,11 @@ SRC_DIR := shared
|
|||
SRC_DIR += cortex-m4
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BOARD_GD32F425RET6),y)
|
||||
SRC_DIR := shared
|
||||
SRC_DIR += cortex-m4
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BOARD_AT32F437VMT7),y)
|
||||
SRC_DIR := shared
|
||||
SRC_DIR += cortex-m4
|
||||
|
|
|
|||
|
|
@ -38,6 +38,10 @@ ifeq ($(CONFIG_BOARD_GD32F415RG), y)
|
|||
SRC_DIR += gd32f415
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BOARD_GD32F425RET6),y)
|
||||
SRC_FILES := gd32f425/interrupt.c boot.S gd32f425/interrupt_vector.S svc_entry.S
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BOARD_AT32F437VMT7), y)
|
||||
SRC_DIR += at32f437vmt7
|
||||
SRC_FILES += svc_entry.S
|
||||
|
|
|
|||
|
|
@ -0,0 +1,114 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file interrupt.c
|
||||
* @brief support arm cortex-m4 interrupt function
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-04-29
|
||||
*/
|
||||
|
||||
#include <xs_base.h>
|
||||
#include <xs_isr.h>
|
||||
// #include <misc.h>
|
||||
#include <gd32f4xx.h>
|
||||
|
||||
extern void _svcall(uintptr_t* contex);
|
||||
|
||||
x_base __attribute__((naked)) DisableLocalInterrupt()
|
||||
{
|
||||
asm volatile ("MRS r0, PRIMASK");
|
||||
asm volatile ("CPSID I");
|
||||
asm volatile ("BX LR ");
|
||||
}
|
||||
|
||||
void __attribute__((naked)) EnableLocalInterrupt(x_base level)
|
||||
{
|
||||
asm volatile ("MSR PRIMASK, r0");
|
||||
asm volatile ("BX LR");
|
||||
}
|
||||
|
||||
int32 ArchEnableHwIrq(uint32 irq_num)
|
||||
{
|
||||
// NVIC_InitTypeDef nvic_init;
|
||||
|
||||
// nvic_init.NVIC_IRQChannel = irq_num;
|
||||
// nvic_init.NVIC_IRQChannelPreemptionPriority = 0;
|
||||
// nvic_init.NVIC_IRQChannelSubPriority = 0;
|
||||
// nvic_init.NVIC_IRQChannelCmd = ENABLE;
|
||||
|
||||
// NVIC_Init(&nvic_init);
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
int32 ArchDisableHwIrq(uint32 irq_num)
|
||||
{
|
||||
// NVIC_InitTypeDef nvic_init;
|
||||
|
||||
// nvic_init.NVIC_IRQChannel = irq_num;
|
||||
// nvic_init.NVIC_IRQChannelPreemptionPriority = 0;
|
||||
// nvic_init.NVIC_IRQChannelSubPriority = 0;
|
||||
// nvic_init.NVIC_IRQChannelCmd = DISABLE;
|
||||
|
||||
// NVIC_Init(&nvic_init);
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
extern void KTaskOsAssignAfterIrq(void *context);
|
||||
|
||||
void IsrEntry()
|
||||
{
|
||||
uint32 ipsr;
|
||||
|
||||
__asm__ volatile("MRS %0, IPSR" : "=r"(ipsr));
|
||||
|
||||
isrManager.done->incCounter();
|
||||
isrManager.done->handleIrq(ipsr);
|
||||
KTaskOsAssignAfterIrq(NONE);
|
||||
isrManager.done->decCounter();
|
||||
|
||||
}
|
||||
|
||||
uintptr_t *Svcall(unsigned int ipsr , uintptr_t* contex )
|
||||
{
|
||||
#ifdef TASK_ISOLATION
|
||||
_svcall(contex);
|
||||
#endif
|
||||
return contex;
|
||||
}
|
||||
|
||||
|
||||
void UsageFault_Handler(int irqn, void *arg)
|
||||
{
|
||||
/* Go to infinite loop when Usage Fault exception occurs */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
void BusFault_Handler(int irqn, void *arg)
|
||||
{
|
||||
/* Go to infinite loop when Bus Fault exception occurs */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
void NMI_Handler(int irqn, void *arg)
|
||||
{
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,171 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32f407xx.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32F407xx Devices vector table for GCC based toolchains.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file interrupt_vector.S
|
||||
* @brief derived from ST standard peripheral library
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-04-25
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: interrupt_vector.S
|
||||
Description: Interrupt Vectors
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2021-04-29
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. take startup_stm32f407xx.s for XiZi kernel
|
||||
*************************************************/
|
||||
|
||||
.globl InterruptVectors
|
||||
|
||||
/******************************************************************************
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type InterruptVectors, %object
|
||||
.size InterruptVectors, .-InterruptVectors
|
||||
|
||||
InterruptVectors:
|
||||
.word __stack_end__
|
||||
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFaultHandler
|
||||
.word MemFaultHandler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word IsrEntry
|
||||
.word IsrEntry
|
||||
.word IsrEntry
|
||||
.word IsrEntry
|
||||
.word SVC_Entry /* SVC */
|
||||
.word IsrEntry /* DebugMon */
|
||||
.word IsrEntry
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler/* SysTick */
|
||||
|
||||
.word IsrEntry /* Window WatchDog */
|
||||
.word IsrEntry /* PVD through EXTI Line detection */
|
||||
.word IsrEntry /* Tamper and TimeStamps through the EXTI line */
|
||||
.word IsrEntry /* RTC Wakeup through the EXTI line */
|
||||
.word IsrEntry /* FLASH */
|
||||
.word IsrEntry /* RCC */
|
||||
.word IsrEntry /* EXTI Line0 */
|
||||
.word IsrEntry /* EXTI Line1 */
|
||||
.word IsrEntry /* EXTI Line2 */
|
||||
.word IsrEntry /* EXTI Line3 */
|
||||
.word IsrEntry /* EXTI Line4 */
|
||||
.word IsrEntry /* DMA1 Stream 0 */
|
||||
.word IsrEntry /* DMA1 Stream 1 */
|
||||
.word IsrEntry /* DMA1 Stream 2 */
|
||||
.word IsrEntry /* DMA1 Stream 3 */
|
||||
.word IsrEntry /* DMA1 Stream 4 */
|
||||
.word IsrEntry /* DMA1 Stream 5 */
|
||||
.word IsrEntry /* DMA1 Stream 6 */
|
||||
.word IsrEntry /* ADC1, ADC2 and ADC3s */
|
||||
.word IsrEntry /* CAN1 TX */
|
||||
.word IsrEntry /* CAN1 RX0 */
|
||||
.word IsrEntry /* CAN1 RX1 */
|
||||
.word IsrEntry /* CAN1 SCE */
|
||||
.word IsrEntry /* External Line[9:5]s */
|
||||
.word IsrEntry /* TIM1 Break and TIM9 */
|
||||
.word IsrEntry /* TIM1 Update and TIM10 */
|
||||
.word IsrEntry//TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
|
||||
.word IsrEntry /* TIM1 Capture Compare */
|
||||
.word IsrEntry /* TIM2 */
|
||||
.word IsrEntry /* TIM3 */
|
||||
.word IsrEntry /* TIM4 */
|
||||
.word IsrEntry /* I2C1 Event */
|
||||
.word IsrEntry /* I2C1 Error */
|
||||
.word IsrEntry /* I2C2 Event */
|
||||
.word IsrEntry /* I2C2 Error */
|
||||
.word IsrEntry /* SPI1 */
|
||||
.word IsrEntry /* SPI2 */
|
||||
.word IsrEntry /* USART1 */
|
||||
.word IsrEntry /* USART2 */
|
||||
.word IsrEntry /* USART3 */
|
||||
.word IsrEntry /* External Line[15:10]s */
|
||||
.word IsrEntry /* RTC Alarm (A and B) through EXTI Line */
|
||||
.word IsrEntry /* USB OTG FS Wakeup through EXTI line */
|
||||
.word IsrEntry /* TIM8 Break and TIM12 */
|
||||
.word IsrEntry /* TIM8 Update and TIM13 */
|
||||
.word IsrEntry /* TIM8 Trigger and Commutation and TIM14 */
|
||||
.word IsrEntry /* TIM8 Capture Compare */
|
||||
.word IsrEntry /* DMA1 Stream7 */
|
||||
.word IsrEntry /* FSMC */
|
||||
.word IsrEntry /* SDIO */
|
||||
.word IsrEntry /* TIM5 */
|
||||
.word IsrEntry /* SPI3 */
|
||||
.word IsrEntry /* UART4 */
|
||||
.word IsrEntry /* UART5 */
|
||||
.word IsrEntry /* TIM6 and DAC1&2 underrun errors */
|
||||
.word IsrEntry /* TIM7 */
|
||||
.word IsrEntry /* DMA2 Stream 0 */
|
||||
.word IsrEntry /* DMA2 Stream 1 */
|
||||
.word IsrEntry /* DMA2 Stream 2 */
|
||||
.word IsrEntry /* DMA2 Stream 3 */
|
||||
.word IsrEntry /* DMA2 Stream 4 */
|
||||
.word IsrEntry /* Ethernet */
|
||||
.word IsrEntry /* Ethernet Wakeup through EXTI line */
|
||||
.word IsrEntry /* CAN2 TX */
|
||||
.word IsrEntry /* CAN2 RX0 */
|
||||
.word IsrEntry /* CAN2 RX1 */
|
||||
.word IsrEntry /* CAN2 SCE */
|
||||
.word IsrEntry /* USB OTG FS */
|
||||
.word IsrEntry /* DMA2 Stream 5 */
|
||||
.word IsrEntry /* DMA2 Stream 6 */
|
||||
.word IsrEntry /* DMA2 Stream 7 */
|
||||
.word IsrEntry /* USART6 */
|
||||
.word IsrEntry /* I2C3 event */
|
||||
.word IsrEntry /* I2C3 error */
|
||||
.word IsrEntry /* USB OTG HS End Point 1 Out */
|
||||
.word IsrEntry /* USB OTG HS End Point 1 In */
|
||||
.word IsrEntry /* USB OTG HS Wakeup through EXTI */
|
||||
.word IsrEntry /* USB OTG HS */
|
||||
.word IsrEntry /* DCMI */
|
||||
.word IsrEntry /* CRYP crypto */
|
||||
.word IsrEntry /* Hash and Rng */
|
||||
.word IsrEntry /* FPU */
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
SRC_DIR := $(BOARD)
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
mainmenu "XiZi_IIoT Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_GD32F425RET6
|
||||
bool
|
||||
select ARCH_ARM
|
||||
default y
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "gd32f425 feature"
|
||||
source "$BSP_DIR/third_party_driver/Kconfig"
|
||||
|
||||
menu "config default board resources"
|
||||
menu "config board app name"
|
||||
config BOARD_APP_NAME
|
||||
string "config board app name"
|
||||
default "/XiUOS_f425_app.bin"
|
||||
endmenu
|
||||
|
||||
menu "config board service table"
|
||||
config SERVICE_TABLE_ADDRESS
|
||||
hex "board service table address"
|
||||
default 0x20000000
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
SRC_FILES := board.c
|
||||
SRC_DIR := third_party_driver
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,225 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file board.c
|
||||
* @brief support stm32f103-nano-board init configure and start-up
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2025-07-10
|
||||
*/
|
||||
|
||||
#include <board.h>
|
||||
#include <xsconfig.h>
|
||||
#include <device.h>
|
||||
#include <arch_interrupt.h>
|
||||
#include <connect_uart.h>
|
||||
#include <connect_adc.h>
|
||||
#include <connect_can.h>
|
||||
#include <connect_spi.h>
|
||||
#include <connect_hwtimer.h>
|
||||
#include <connect_motor.h>
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
#include "gd32f4xx_rcu.h"
|
||||
#include "gd32f4xx_gpio.h"
|
||||
|
||||
|
||||
volatile static uint32_t delay;
|
||||
/* configure systick */
|
||||
void systick_config(void);
|
||||
/*!
|
||||
\brief configure systick
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void systick_config(void)
|
||||
{
|
||||
/* setup systick timer for 1000Hz interrupts */
|
||||
if(SysTick_Config(SystemCoreClock / 1000U)) {
|
||||
/* capture error */
|
||||
while(1) {
|
||||
}
|
||||
}
|
||||
/* configure the systick handler priority */
|
||||
NVIC_SetPriority(SysTick_IRQn, 0x00U);
|
||||
}
|
||||
|
||||
|
||||
|
||||
#define RCU_MODIFY_4(__delay) do{ \
|
||||
volatile uint32_t i, reg; \
|
||||
if(0 != __delay){ \
|
||||
/* Insert a software delay */ \
|
||||
for(i=0; i<__delay; i++){ \
|
||||
} \
|
||||
reg = RCU_CFG0; \
|
||||
reg &= ~(RCU_CFG0_AHBPSC); \
|
||||
reg |= RCU_AHB_CKSYS_DIV2; \
|
||||
/* AHB = SYSCLK/2 */ \
|
||||
RCU_CFG0 = reg; \
|
||||
/* Insert a software delay */ \
|
||||
for(i=0; i<__delay; i++){ \
|
||||
} \
|
||||
reg = RCU_CFG0; \
|
||||
reg &= ~(RCU_CFG0_AHBPSC); \
|
||||
reg |= RCU_AHB_CKSYS_DIV4; \
|
||||
/* AHB = SYSCLK/4 */ \
|
||||
RCU_CFG0 = reg; \
|
||||
/* Insert a software delay */ \
|
||||
for(i=0; i<__delay; i++){ \
|
||||
} \
|
||||
reg = RCU_CFG0; \
|
||||
reg &= ~(RCU_CFG0_AHBPSC); \
|
||||
reg |= RCU_AHB_CKSYS_DIV8; \
|
||||
/* AHB = SYSCLK/8 */ \
|
||||
RCU_CFG0 = reg; \
|
||||
/* Insert a software delay */ \
|
||||
for(i=0; i<__delay; i++){ \
|
||||
} \
|
||||
reg = RCU_CFG0; \
|
||||
reg &= ~(RCU_CFG0_AHBPSC); \
|
||||
reg |= RCU_AHB_CKSYS_DIV16; \
|
||||
/* AHB = SYSCLK/16 */ \
|
||||
RCU_CFG0 = reg; \
|
||||
/* Insert a software delay */ \
|
||||
for(i=0; i<__delay; i++){ \
|
||||
} \
|
||||
} \
|
||||
}while(0)
|
||||
|
||||
|
||||
|
||||
void SysTick_Handler(int irqn, void *arg)
|
||||
{
|
||||
TickAndTaskTimesliceUpdate();
|
||||
}
|
||||
|
||||
|
||||
static void _soft_delay_(uint32_t time)
|
||||
{
|
||||
__IO uint32_t i;
|
||||
for(i=0; i<time*10; i++){
|
||||
}
|
||||
}
|
||||
|
||||
void SystemClock_Config(void)
|
||||
{
|
||||
|
||||
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
__IO uint32_t reg_temp;
|
||||
|
||||
/* 1. 切换系统时钟为 IRC16M, 并复位 RCU 配置 */
|
||||
RCU_MODIFY_4(0x50);
|
||||
rcu_system_clock_source_config(RCU_CKSYSSRC_IRC16M);
|
||||
_soft_delay_(200);
|
||||
rcu_deinit();
|
||||
|
||||
/* 2. 使能 IRC16M */
|
||||
RCU_CTL |= RCU_CTL_IRC16MEN;
|
||||
|
||||
/* 3. 等待 IRC16M 稳定 */
|
||||
do {
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB);
|
||||
} while ((0U == stab_flag) && (timeout != IRC16M_STARTUP_TIMEOUT));
|
||||
|
||||
if (0U == (RCU_CTL & RCU_CTL_IRC16MSTB)) {
|
||||
while (1); /* 启动失败死循环· */
|
||||
}
|
||||
|
||||
/* 4. 配置总线分频 AHB = SYSCLK, APB2 = AHB/2, APB1 = AHB/4 */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; // AHB = 200MHz
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; // APB2 = 100MHz
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; // APB1 = 50MHz
|
||||
|
||||
/* 5. 配置 PLL: 输入 IRC16M = 16MHz, SYSCLK = 200MHz */
|
||||
/* 公式F_PLL = F_IN * N / M / P
|
||||
M = 16, N = 400, P = 2 ¡ú 16*400/16/2 = 200MHz */
|
||||
RCU_PLL = (16U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) | RCU_PLLSRC_IRC16M);
|
||||
|
||||
/* 6.使能 PLL 并等待稳定 */
|
||||
RCU_CTL |= RCU_CTL_PLLEN;
|
||||
while (0U == (RCU_CTL & RCU_CTL_PLLSTB));
|
||||
|
||||
/* 7. 切换系统时钟 PLL */
|
||||
reg_temp = RCU_CFG0;
|
||||
reg_temp &= ~RCU_CFG0_SCS;
|
||||
reg_temp |= RCU_CKSYSSRC_PLLP;
|
||||
RCU_CFG0 = reg_temp;
|
||||
while (0U == (RCU_CFG0 & RCU_SCSS_PLLP));
|
||||
|
||||
/* 8. 更新系统核心时钟变量 */
|
||||
SystemCoreClock = 200000000; // 200 MHz
|
||||
|
||||
}
|
||||
|
||||
static void MX_GPIO_Init(void)
|
||||
{
|
||||
/* 使能时钟 */
|
||||
rcu_periph_clock_enable(RCU_GPIOH);
|
||||
rcu_periph_clock_enable(RCU_GPIOC);
|
||||
rcu_periph_clock_enable(RCU_GPIOA);
|
||||
rcu_periph_clock_enable(RCU_GPIOB);
|
||||
|
||||
// /* 配置PA15: 推挽输出，高速，无上下拉 */
|
||||
// gpio_mode_set(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO_PIN_15);
|
||||
// gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_15);
|
||||
// GPIO_BC(GPIOA) = GPIO_PIN_15; //默认输出低电平
|
||||
// GPIO_BOP(GPIOA) = GPIO_PIN_15;
|
||||
// /* 配置PB6: 推挽输出，低速，无上下拉 */
|
||||
// gpio_mode_set(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO_PIN_6);
|
||||
// gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_6);
|
||||
// GPIO_BC(GPIOB) = GPIO_PIN_6; // 默认输出低电平
|
||||
}
|
||||
|
||||
|
||||
void InitBoardHardware()
|
||||
{
|
||||
|
||||
SystemClock_Config();
|
||||
systick_config();
|
||||
|
||||
InitBoardMemory((void*)HEAP_START, (void*)HEAP_END);
|
||||
MX_GPIO_Init();
|
||||
#ifdef BSP_USING_UART
|
||||
InitHwUart();
|
||||
|
||||
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
|
||||
#endif
|
||||
#ifdef BSP_USING_CAN
|
||||
HwCanInit();
|
||||
#endif
|
||||
#ifdef BSP_USING_SPI
|
||||
HwSpiInit();
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_ADC
|
||||
HwAdcInit();
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_HWTIMER
|
||||
HardwareTimerInit();
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USE_MOTOR
|
||||
InitHwMotor();
|
||||
#ifdef AUTO_START_MOTOR
|
||||
// MotorStart();
|
||||
#endif
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file board.h
|
||||
* @brief define stm32h750 init configure and start-up function
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2025-03-13
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
extern int __stack_end__;
|
||||
|
||||
void InitBoardHardware();
|
||||
|
||||
|
||||
#define HEAP_START (void *)(&__stack_end__)
|
||||
#define HEAP_END 0x2001ffff
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
|
||||
|
||||
export CFLAGS := -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections -Dgcc -Os -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb
|
||||
export AFLAGS := -c -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2
|
||||
export LFLAGS := -mcpu=cortex-m4 -specs=nano.specs -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi-stm32f446ret6.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
|
||||
export CXXFLAGS := -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections -Dgcc -Os -gdwarf-2 -g
|
||||
|
||||
export APPLFLAGS := -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi-app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
|
||||
|
||||
export DEFINES := -DHAVE_CCONFIG_H
|
||||
|
||||
export ARCH = arm
|
||||
export MCU = cortex-m4
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
/*
|
||||
* linker script for STM32F10x with GNU ld
|
||||
*/
|
||||
|
||||
/* Program Entry, set to mark it as "used" and avoid gc */
|
||||
|
||||
__SYSTEM_STACKSIZE__ = 0x4000;
|
||||
MEMORY
|
||||
{
|
||||
flash (rx) : ORIGIN = 0x08000000, LENGTH = 512k /* 512KB flash */
|
||||
sram (rw) : ORIGIN = 0x20000000, LENGTH = 256k /* 256K sram */
|
||||
}
|
||||
OUTPUT_ARCH(arm)
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_stext = ABSOLUTE(.));
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
*(.text .text.*) /* Normal code */
|
||||
*(.rodata .rodata*) /* read-only data (constants) */
|
||||
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
|
||||
/* section information for shell */
|
||||
. = ALIGN(4);
|
||||
_shell_command_start = .;
|
||||
KEEP (*(shellCommand))
|
||||
_shell_command_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* the work i did */
|
||||
PROVIDE(__ctors_start__ = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
PROVIDE(__ctors_end__ = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* the work i did */
|
||||
|
||||
__isrtbl_idx_start = .;
|
||||
KEEP(*(.isrtbl.idx))
|
||||
__isrtbl_start = .;
|
||||
KEEP(*(.isrtbl))
|
||||
__isrtbl_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
PROVIDE(g_service_table_start = ABSOLUTE(.));
|
||||
KEEP(*(.g_service_table))
|
||||
PROVIDE(g_service_table_end = ABSOLUTE(.));
|
||||
|
||||
PROVIDE(_etext = ABSOLUTE(.));
|
||||
} > flash
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
PROVIDE(__exidx_start = ABSOLUTE(.));
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
_sidata = .;
|
||||
PROVIDE(__exidx_end = ABSOLUTE(.));
|
||||
} > flash
|
||||
|
||||
.data : AT(__exidx_end)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_sdata = ABSOLUTE(.));
|
||||
*(.data .data.*)
|
||||
PROVIDE(_edata = ABSOLUTE(.));
|
||||
} > sram
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start = ABSOLUTE(.);
|
||||
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_end = ABSOLUTE(.);
|
||||
} > sram
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE(__stack_start__ = ABSOLUTE(.));
|
||||
/* cpu stack */
|
||||
. = . + __SYSTEM_STACKSIZE__;
|
||||
__stack_tp = .;
|
||||
PROVIDE(__stack_end__ = ABSOLUTE(.));
|
||||
} > sram
|
||||
|
||||
_end = ABSOLUTE(.);
|
||||
}
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
|
||||
choice
|
||||
prompt "MOTOR_SELECT" # 菜单标题
|
||||
default OPTION_B # 默认选择 OPTION_B（可选）
|
||||
|
||||
config BSP_DISABLE_MOTOR
|
||||
bool "DISABLE"
|
||||
help
|
||||
disable motor config
|
||||
|
||||
config BSP_USING_J60_6
|
||||
bool "MOTOR J60-6"
|
||||
select BSP_USING_UART
|
||||
select BSP_USING_CAN
|
||||
select BSP_USING_SPI
|
||||
select BSP_USING_HWTIMER
|
||||
select BSP_USING_ADC
|
||||
select BSP_USE_MOTOR
|
||||
help
|
||||
set motor config for YSC J60-6
|
||||
|
||||
config BSP_USING_J60_10
|
||||
bool "MOTOR J60-10"
|
||||
select BSP_USING_UART
|
||||
select BSP_USING_CAN
|
||||
select BSP_USING_SPI
|
||||
select BSP_USING_HWTIMER
|
||||
select BSP_USING_ADC
|
||||
select BSP_USE_MOTOR
|
||||
help
|
||||
This is option C.
|
||||
endchoice
|
||||
|
||||
|
||||
menu "MOTOR CONFIG"
|
||||
depends on !BSP_DISABLE_MOTOR
|
||||
menuconfig AUTO_START_MOTOR
|
||||
bool "AUTO START MOTOR"
|
||||
default y
|
||||
help
|
||||
enable auto start motor when power on
|
||||
endmenu
|
||||
|
||||
|
||||
menu "BSP select"
|
||||
menuconfig BSP_USING_UART
|
||||
bool "Using UART device"
|
||||
default y
|
||||
select RESOURCES_SERIAL
|
||||
|
||||
menuconfig BSP_USING_SPI
|
||||
bool "Using SPI device"
|
||||
default n
|
||||
select RESOURCES_SPI
|
||||
|
||||
menuconfig BSP_USING_CAN
|
||||
bool "Using CAN device"
|
||||
default n
|
||||
select RESOURCES_CAN
|
||||
|
||||
menuconfig BSP_USING_HWTIMER
|
||||
bool "Using timer device"
|
||||
default n
|
||||
select RESOURCES_HWTIMER
|
||||
|
||||
menuconfig BSP_USING_ADC
|
||||
bool "Using timer device"
|
||||
default n
|
||||
select RESOURCES_ADC
|
||||
|
||||
menuconfig BSP_USE_MOTOR
|
||||
bool "Using timer device"
|
||||
default n
|
||||
select RESOURCES_MOTOR
|
||||
|
||||
if BSP_USING_UART
|
||||
source "$BSP_DIR/third_party_driver/usart/Kconfig"
|
||||
endif
|
||||
if BSP_USING_CAN
|
||||
source "$BSP_DIR/third_party_driver/can/Kconfig"
|
||||
endif
|
||||
if BSP_USING_SPI
|
||||
source "$BSP_DIR/third_party_driver/spi/Kconfig"
|
||||
endif
|
||||
if BSP_USING_HWTIMER
|
||||
source "$BSP_DIR/third_party_driver/timer/Kconfig"
|
||||
endif
|
||||
if BSP_USING_ADC
|
||||
source "$BSP_DIR/third_party_driver/adc/Kconfig"
|
||||
endif
|
||||
endmenu
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
SRC_DIR := libraries
|
||||
|
||||
ifeq ($(CONFIG_BSP_USE_MOTOR),y)
|
||||
SRC_DIR += motor
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_UART),y)
|
||||
SRC_DIR += usart
|
||||
endif
|
||||
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_CAN),y)
|
||||
SRC_DIR += can
|
||||
endif
|
||||
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_SPI),y)
|
||||
SRC_DIR += spi
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_HWTIMER),y)
|
||||
SRC_DIR += timer
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_ADC),y)
|
||||
SRC_DIR += adc
|
||||
endif
|
||||
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
config ADC_BUS_NAME
|
||||
string "adc bus name"
|
||||
default "adc_bus"
|
||||
|
||||
config ADC_DRIVER_NAME
|
||||
string "adc driver name"
|
||||
default "adc_drv"
|
||||
|
||||
menuconfig BSP_USING_ADC1
|
||||
bool "Enable ADC1"
|
||||
default y
|
||||
if BSP_USING_ADC1
|
||||
config ADC1_DEVICE_NAME
|
||||
string "adc1 device name"
|
||||
default "adc1_dev"
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_ADC2
|
||||
bool "Enable ADC2"
|
||||
default y
|
||||
if BSP_USING_ADC2
|
||||
config ADC2_DEVICE_NAME
|
||||
string "adc2 device name"
|
||||
default "adc2_dev"
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_ADC0
|
||||
bool "Enable ADC0"
|
||||
default y
|
||||
if BSP_USING_ADC0
|
||||
config ADC0_DEVICE_NAME
|
||||
string "adc0 device name"
|
||||
default "adc0_dev"
|
||||
endif
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
SRC_FILES := connect_adc.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,437 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file connect_adc.c
|
||||
* @brief support to register ADC pointer and function
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2025-07-31
|
||||
*/
|
||||
|
||||
#include <connect_adc.h>
|
||||
#include "gd32f4xx.h"
|
||||
#include "gd32f4xx_adc.h"
|
||||
#include "gd32f4xx_rcu.h"
|
||||
#include "gd32f4xx_gpio.h"
|
||||
#include "gd32f4xx_misc.h"
|
||||
#include <foc.h>
|
||||
|
||||
|
||||
|
||||
uint32 adc_value[3] = {0};
|
||||
static void AdcInit()
|
||||
{
|
||||
|
||||
#ifdef BSP_USING_ADC0
|
||||
/* 1. 使能时钟 */
|
||||
rcu_periph_clock_enable(RCU_GPIOB);
|
||||
rcu_periph_clock_enable(RCU_ADC0);
|
||||
|
||||
/* 2. 配置 PB0 = ADC0_IN8 (模拟输入) */
|
||||
gpio_mode_set(GPIOB, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO_PIN_0);
|
||||
|
||||
/* 3. ADC 时钟配置 (PCLK2/4) */
|
||||
adc_clock_config(ADC_ADCCK_PCLK2_DIV4);
|
||||
|
||||
/* 4. ADC 去初始化 (复位所有寄存器) */
|
||||
//adc_deinit();
|
||||
|
||||
/* 5. 【修正】ADC 核心模式配置 (之前缺失的部分) */
|
||||
adc_resolution_config(ADC0, ADC_RESOLUTION_12B); // 12位精度
|
||||
adc_data_alignment_config(ADC0, ADC_DATAALIGN_RIGHT); // 数据右对齐
|
||||
adc_special_function_config(ADC0, ADC_SCAN_MODE, DISABLE); // 非扫描模式
|
||||
adc_special_function_config(ADC0, ADC_CONTINUOUS_MODE, DISABLE); // 单次模式
|
||||
|
||||
/* 6. 设置规则通道 */
|
||||
// 【修正】根据您的截图，RSQ2=0x08，说明目标是通道8，但RSQ0=0表示序列未正确指向它。这里明确配置通道8。
|
||||
adc_channel_length_config(ADC0, ADC_INSERTED_CHANNEL, 1);
|
||||
adc_inserted_channel_config(ADC0, 0, ADC_CHANNEL_8, ADC_SAMPLETIME_56); // 【优化】增加采样时间
|
||||
|
||||
/* 7. 使用timer0 trg0触发 */
|
||||
// adc_external_trigger_config(ADC0, ADC_INSERTED_CHANNEL, ADC_EXTTRIG_INSERTED_T0_TRGO);
|
||||
adc_external_trigger_source_config(ADC0,ADC_INSERTED_CHANNEL, ADC_EXTTRIG_INSERTED_T0_TRGO);
|
||||
adc_external_trigger_config(ADC0, ADC_INSERTED_CHANNEL, ENABLE);
|
||||
|
||||
/* 8. 使能 ADC */
|
||||
adc_enable(ADC0);
|
||||
//delay_1ms(1); // 等待 ADC 稳定
|
||||
|
||||
/* 9. 校准 */
|
||||
adc_calibration_enable(ADC0);
|
||||
|
||||
/* 10. 【可选】配置中断 */
|
||||
|
||||
nvic_irq_enable(ADC_IRQn, 3, 0); // 【重要】注意中断向量是ADC0_IRQn
|
||||
adc_interrupt_enable(ADC0, ADC_INT_EOIC);
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
|
||||
/* 1. 使能时钟 */
|
||||
rcu_periph_clock_enable(RCU_GPIOC);
|
||||
rcu_periph_clock_enable(RCU_ADC1);
|
||||
|
||||
/* 2. 配置 PC0 = ADC1_IN10 (模拟输入) */
|
||||
gpio_mode_set(GPIOC, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO_PIN_0);
|
||||
|
||||
/* 3. 配置 ADC 时钟 PCLK2/4 */
|
||||
adc_clock_config(ADC_ADCCK_PCLK2_DIV4);
|
||||
|
||||
/* 4. 复位 ADC1 */
|
||||
//adc_deinit();
|
||||
|
||||
/* 5. 配置 ADC1 参数 */
|
||||
adc_resolution_config(ADC1, ADC_RESOLUTION_12B);
|
||||
adc_data_alignment_config(ADC1, ADC_DATAALIGN_RIGHT);
|
||||
adc_special_function_config(ADC1, ADC_SCAN_MODE, DISABLE);
|
||||
adc_special_function_config(ADC1, ADC_CONTINUOUS_MODE, DISABLE);
|
||||
|
||||
/* 6. 设置规则通道 (通道10) */
|
||||
adc_channel_length_config(ADC1, ADC_INSERTED_CHANNEL, 1);
|
||||
adc_inserted_channel_config(ADC1, 0, ADC_CHANNEL_10, ADC_SAMPLETIME_56); // 【优化】增加采样时间
|
||||
|
||||
/* 7. 禁止外部触发，使用软件触发 */
|
||||
// adc_external_trigger_config(ADC1, ADC_INSERTED_CHANNEL, ADC_EXTTRIG_INSERTED_T0_TRGO);
|
||||
adc_external_trigger_source_config(ADC1,ADC_INSERTED_CHANNEL, ADC_EXTTRIG_INSERTED_T0_TRGO);
|
||||
adc_external_trigger_config(ADC1, ADC_INSERTED_CHANNEL, ENABLE);
|
||||
|
||||
/* 8. 使能 ADC1 */
|
||||
adc_enable(ADC1);
|
||||
//delay_1ms(1);
|
||||
|
||||
/* 9. 校准 ADC1 */
|
||||
adc_calibration_enable(ADC1);
|
||||
|
||||
/* 10. 【可选】配置中断 */
|
||||
nvic_irq_enable(ADC_IRQn, 3, 0);
|
||||
//adc_interrupt_enable(ADC1, ADC_INT_EOC);
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef BSP_USING_ADC2
|
||||
/* 1. 使能时钟 */
|
||||
rcu_periph_clock_enable(RCU_GPIOC);
|
||||
rcu_periph_clock_enable(RCU_ADC2);
|
||||
|
||||
/* 2. 配置 PC1 = ADC2_IN11 (模拟输入) */
|
||||
gpio_mode_set(GPIOC, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO_PIN_1);
|
||||
|
||||
/* 3. 配置 ADC 时钟 PCLK2/4 */
|
||||
adc_clock_config(ADC_ADCCK_PCLK2_DIV4);
|
||||
|
||||
/* 4. 复位 ADC2 */
|
||||
//adc_deinit();
|
||||
|
||||
/* 5. 配置 ADC2 参数 */
|
||||
adc_resolution_config(ADC2, ADC_RESOLUTION_12B);
|
||||
adc_data_alignment_config(ADC2, ADC_DATAALIGN_RIGHT);
|
||||
adc_special_function_config(ADC2, ADC_SCAN_MODE, DISABLE);
|
||||
adc_special_function_config(ADC2, ADC_CONTINUOUS_MODE, DISABLE);
|
||||
|
||||
/* 6. 设置规则通道 */
|
||||
adc_channel_length_config(ADC2, ADC_INSERTED_CHANNEL, 1);
|
||||
adc_inserted_channel_config(ADC2, 0, ADC_CHANNEL_11, ADC_SAMPLETIME_56);
|
||||
|
||||
/* 7. 禁止外部触发，使用软件触发 */
|
||||
// adc_external_trigger_config(ADC2, ADC_INSERTED_CHANNEL, ADC_EXTTRIG_INSERTED_T0_TRGO);
|
||||
adc_external_trigger_source_config(ADC2,ADC_INSERTED_CHANNEL, ADC_EXTTRIG_INSERTED_T0_TRGO);
|
||||
adc_external_trigger_config(ADC2, ADC_INSERTED_CHANNEL, ENABLE);
|
||||
|
||||
/* 8. 使能 ADC2 */
|
||||
adc_enable(ADC2);
|
||||
//delay_1ms(1);
|
||||
|
||||
/* 9. 校准 ADC2 */
|
||||
adc_calibration_enable(ADC2);
|
||||
|
||||
/* 10. 【可选】配置中断 */
|
||||
nvic_irq_enable(ADC_IRQn, 3, 0); //
|
||||
//adc_interrupt_enable(ADC2, ADC_INT_EOC);
|
||||
#endif
|
||||
|
||||
}
|
||||
//adc注入通道开启
|
||||
static uint32 AdcStart(void *dev)
|
||||
{
|
||||
// struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)dev;
|
||||
// struct HwAdc* adc_cfg = (struct HwAdc*)adc_dev->haldev.private_data;
|
||||
// if(ADC0 == adc_cfg->ADCx){
|
||||
|
||||
// }
|
||||
// else if(ADC1 == adc_cfg->ADCx) {
|
||||
|
||||
// }
|
||||
// else if(ADC2 == adc_cfg->ADCx){
|
||||
|
||||
// }
|
||||
// else{
|
||||
// return ERROR;
|
||||
// }
|
||||
return EOK;
|
||||
}
|
||||
//adc注入通道关闭
|
||||
static uint32 AdcStop(void *dev)
|
||||
{
|
||||
// struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)dev;
|
||||
// struct HwAdc* adc_cfg = (struct HwAdc*)adc_dev->haldev.private_data;
|
||||
// if(ADC1 == adc_cfg->ADCx){
|
||||
// HAL_ADCEx_InjectedStop_IT(&hadc1);
|
||||
// }
|
||||
// else if(ADC2 == adc_cfg->ADCx) {
|
||||
// HAL_ADCEx_InjectedStop(&hadc2);
|
||||
// }
|
||||
// else if(ADC3 == adc_cfg->ADCx){
|
||||
// HAL_ADCEx_InjectedStop(&hadc3);
|
||||
// }
|
||||
// else{
|
||||
// return ERROR;
|
||||
// }
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static uint32 AdcRead(void *dev, struct BusBlockReadParam *read_param)
|
||||
{
|
||||
// struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)dev;
|
||||
// struct HwAdc *adc_cfg = (struct HwAdc *)adc_dev->haldev.private_data;
|
||||
|
||||
// uint16 adc_average_value = 0;
|
||||
// uint8 timeout_ms = 100;
|
||||
// uint16 adc_value = 0;
|
||||
// HAL_StatusTypeDef status;
|
||||
|
||||
// status = HAL_ADC_Start(&hadc1);
|
||||
// if (status != HAL_OK) {
|
||||
// KPrintf("ADC Start Error: %d\n", status);
|
||||
// return ERROR;
|
||||
// }
|
||||
|
||||
// status = HAL_ADC_PollForConversion(&hadc1, timeout_ms);
|
||||
// if (status != HAL_OK) {
|
||||
// HAL_ADC_Stop(&hadc1);
|
||||
// KPrintf("ADC Polling Error: %d\n", status);
|
||||
// return ERROR;
|
||||
// }
|
||||
|
||||
// adc_value = HAL_ADC_GetValue(&hadc1);
|
||||
|
||||
// *(uint16 *)read_param->buffer = adc_value;
|
||||
// read_param->read_length = 2;
|
||||
|
||||
// status = HAL_ADC_Stop(&hadc1);
|
||||
// if (status != HAL_OK) {
|
||||
// KPrintf("ADC Stop Error: %d\n", status);
|
||||
// return ERROR;
|
||||
// }
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
|
||||
void ADCHandler(int vector, void *param)
|
||||
{
|
||||
// adc_value[0] = adc_inserted_data_read(ADC0, ADC_INSERTED_CHANNEL_0);
|
||||
x_base lock = 0;
|
||||
lock = DISABLE_INTERRUPT();
|
||||
if (adc_interrupt_flag_get(ADC0, ADC_INT_FLAG_EOIC))
|
||||
{
|
||||
adc_interrupt_flag_clear(ADC0, ADC_INT_FLAG_EOIC);
|
||||
#ifdef BSP_USE_MOTOR
|
||||
foc_loop();
|
||||
#else
|
||||
adc_value[0] = adc_inserted_data_read(ADC0, ADC_INSERTED_CHANNEL_0);
|
||||
adc_value[1] = adc_inserted_data_read(ADC1, ADC_INSERTED_CHANNEL_0);
|
||||
adc_value[2] = adc_inserted_data_read(ADC2, ADC_INSERTED_CHANNEL_0);
|
||||
#endif
|
||||
}
|
||||
if ( adc_interrupt_flag_get(ADC0, ADC_INT_FLAG_WDE))
|
||||
{
|
||||
adc_interrupt_flag_clear(ADC0, ADC_INT_FLAG_WDE);
|
||||
/* code */
|
||||
}
|
||||
|
||||
ENABLE_INTERRUPT(lock);
|
||||
|
||||
}
|
||||
DECLARE_HW_IRQ(ADC_IRQn, ADCHandler, NONE);
|
||||
|
||||
|
||||
static uint32 AdcDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
|
||||
{
|
||||
NULL_PARAM_CHECK(drv);
|
||||
NULL_PARAM_CHECK(configure_info);
|
||||
|
||||
x_err_t ret = EOK;
|
||||
|
||||
switch (configure_info->configure_cmd)
|
||||
{
|
||||
|
||||
case OPE_INT:
|
||||
AdcInit();
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct AdcDevDone dev_done =
|
||||
{
|
||||
AdcStart,
|
||||
AdcStop,
|
||||
NONE,
|
||||
AdcRead,
|
||||
};
|
||||
|
||||
int HwAdcInit(void)
|
||||
{
|
||||
static struct AdcBus adc_bus;
|
||||
static struct AdcDriver adc_drv;
|
||||
|
||||
x_err_t ret = EOK;
|
||||
ret = AdcBusInit(&adc_bus, ADC_BUS_NAME);
|
||||
if (ret != EOK) {
|
||||
KPrintf("ADC3 bus init error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
adc_drv.configure = AdcDrvConfigure;
|
||||
ret = AdcDriverInit(&adc_drv, ADC_DRIVER_NAME);
|
||||
if (ret != EOK) {
|
||||
KPrintf("ADC3 driver init error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
ret = AdcDriverAttachToBus(ADC_DRIVER_NAME, ADC_BUS_NAME);
|
||||
if (ret != EOK) {
|
||||
KPrintf("ADC3 driver attach error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
//adc_drv.configure = AdcDrvConfigure;
|
||||
|
||||
struct BusConfigureInfo configure_info;
|
||||
configure_info.configure_cmd = OPE_INT;
|
||||
ret = BusDrvConfigure(&(adc_drv.driver), &configure_info);
|
||||
if (ret != EOK) {
|
||||
KPrintf("ADC driver Initialize error\n");
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
#ifdef BSP_USING_ADC0
|
||||
|
||||
static struct AdcHardwareDevice adc0_dev;
|
||||
static struct HwAdc adc0_cfg;
|
||||
|
||||
adc0_dev.adc_dev_done = &dev_done;
|
||||
adc0_cfg.ADCx =(void*) ADC0;
|
||||
adc0_cfg.adc_channel = 8;
|
||||
|
||||
ret = AdcDeviceRegister(&adc0_dev, (void *)&adc0_cfg, ADC0_DEVICE_NAME);
|
||||
if (ret != EOK) {
|
||||
KPrintf("ADC1 device register error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
ret = AdcDeviceAttachToBus(ADC0_DEVICE_NAME, ADC_BUS_NAME);
|
||||
if (ret != EOK) {
|
||||
KPrintf("ADC1 device register error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
|
||||
static struct AdcHardwareDevice adc1_dev;
|
||||
static struct HwAdc adc1_cfg;
|
||||
|
||||
adc1_dev.adc_dev_done = &dev_done;
|
||||
adc1_cfg.ADCx =(void*) ADC1;
|
||||
adc1_cfg.adc_channel = 10;
|
||||
|
||||
ret = AdcDeviceRegister(&adc1_dev, (void *)&adc1_cfg, ADC1_DEVICE_NAME);
|
||||
if (ret != EOK) {
|
||||
KPrintf("ADC2 device register error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
ret = AdcDeviceAttachToBus(ADC1_DEVICE_NAME, ADC_BUS_NAME);
|
||||
if (ret != EOK) {
|
||||
KPrintf("ADC2 device register error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef BSP_USING_ADC2
|
||||
static struct AdcHardwareDevice adc2_dev;
|
||||
static struct HwAdc adc2_cfg;
|
||||
|
||||
adc0_dev.adc_dev_done = &dev_done;
|
||||
adc0_cfg.ADCx =(void*) ADC2;
|
||||
adc0_cfg.adc_channel = 11;
|
||||
|
||||
ret = AdcDeviceRegister(&adc2_dev, (void *)&adc2_cfg, ADC2_DEVICE_NAME);
|
||||
if (ret != EOK) {
|
||||
KPrintf("ADC1 device register error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
ret = AdcDeviceAttachToBus(ADC2_DEVICE_NAME, ADC_BUS_NAME);
|
||||
if (ret != EOK) {
|
||||
KPrintf("ADC1 device register error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
#define TESTADC
|
||||
#ifdef TESTADC
|
||||
static struct Bus *bus;
|
||||
static struct HardwareDev *dev;
|
||||
static struct Driver *drv;
|
||||
|
||||
static uint32 TestAdc(void)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
KPrintf("ADC Value: %u, %u, %u\n", adc_value[0], adc_value[1], adc_value[2]);
|
||||
return ret;
|
||||
bus = BusFind(ADC_BUS_NAME);
|
||||
dev = BusFindDevice(bus, ADC1_DEVICE_NAME);
|
||||
drv = BusFindDriver(bus, ADC_DRIVER_NAME);
|
||||
|
||||
//adc驱动初始化
|
||||
struct BusConfigureInfo configure_info;
|
||||
configure_info.configure_cmd = OPE_INT;
|
||||
ret = BusDrvConfigure(drv, &configure_info);
|
||||
if (ret != EOK) {
|
||||
KPrintf("Initialize adc error\n");
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
struct BusBlockReadParam read_param;
|
||||
|
||||
/* 启动ADC ，ADC1，ADC2，ADC3同时开启注入通道*/
|
||||
ret = BusDevOpen(dev);
|
||||
if (ret != EOK) {
|
||||
KPrintf("BusDevOpen error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN),
|
||||
TestAdc, TestAdc, open adc device and read parameters);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
config CAN_BUS_NAME
|
||||
string "can bus name"
|
||||
default "can_bus"
|
||||
|
||||
config CAN_DRIVER_NAME
|
||||
string "can driver name"
|
||||
default "can_drv"
|
||||
|
||||
config CAN_DEVICE_NAME
|
||||
string "can device name"
|
||||
default "can0_dev"
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
SRC_FILES := connect_can.c
|
||||
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,360 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file connect_can.c
|
||||
* @brief support stm32l476 can function and register to bus framework
|
||||
* @version 2.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2025-03-14
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: connect_can.c
|
||||
Description: support stm32l476 can function and register to bus framework
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2025-03-14
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. support stm32l476 can configure, write and read
|
||||
2. support stm32l476 can bus device and driver register
|
||||
*************************************************/
|
||||
#include "can_protocol.h"
|
||||
#include "connect_can.h"
|
||||
#include "gd32f4xx.h"
|
||||
#include "gd32f4xx_can.h"
|
||||
#include "gd32f4xx_rcu.h"
|
||||
#include "gd32f4xx_gpio.h"
|
||||
#include "gd32f4xx_misc.h"
|
||||
#include "connect_motor.h"
|
||||
|
||||
|
||||
#define GET_CAN_BS2_TQ(x) ((x) == 1 ? CAN_BS2_1TQ : (x) == 2 ? CAN_BS2_2TQ : (x) == 3 ? CAN_BS2_3TQ : (x) == 4 ? CAN_BS2_4TQ : \
|
||||
(x) == 5 ? CAN_BS2_5TQ : (x) == 6 ? CAN_BS2_6TQ : (x) == 7 ? CAN_BS2_7TQ : (x) == 8 ? CAN_BS2_8TQ : CAN_BS2_1TQ)
|
||||
|
||||
#define GET_CAN_BS1_TQ(x) ((x) == 1 ? CAN_BS1_1TQ : (x) == 2 ? CAN_BS1_2TQ : (x) == 3 ? CAN_BS1_3TQ : (x) == 4 ? CAN_BS1_4TQ : \
|
||||
(x) == 5 ? CAN_BS1_5TQ : (x) == 6 ? CAN_BS1_6TQ : (x) == 7 ? CAN_BS1_7TQ : (x) == 8 ? CAN_BS1_8TQ : \
|
||||
(x) == 9 ? CAN_BS1_9TQ : (x) == 10 ? CAN_BS1_10TQ : (x) == 11 ? CAN_BS1_11TQ : (x) == 12 ? CAN_BS1_12TQ : \
|
||||
(x) == 13 ? CAN_BS1_13TQ : (x) == 14 ? CAN_BS1_14TQ : (x) == 15 ? CAN_BS1_15TQ : (x) == 16 ? CAN_BS1_16TQ : CAN_BS1_1TQ)
|
||||
|
||||
#define GET_CAN_SJW_TQ(x) ((x) == 1 ? CAN_SJW_1TQ : (x) == 2 ? CAN_SJW_2TQ : (x) == 3 ? CAN_SJW_3TQ : (x) == 4 ? CAN_SJW_4TQ : CAN_SJW_1TQ )
|
||||
#define GET_CAN_MODE(x) ((x) == 0 ? CAN_MODE_NORMAL : (x) == 1 ? CAN_MODE_LOOPBACK : (x) == 2 ? CAN_MODE_SILENT : (x) == 3 ? CAN_MODE_SILENT_LOOPBACK : CAN_MODE_NORMAL )
|
||||
|
||||
|
||||
#define CAN_RX_GPIO_PORT GPIOB
|
||||
#define CAN_RX_GPIO_PIN GPIO_PIN_8
|
||||
#define CAN_RX_GPIO_CLK_ENABLE() rcu_periph_clock_enable(RCU_GPIOB) /* PB口时钟使能 */
|
||||
|
||||
#define CAN_TX_GPIO_PORT GPIOB
|
||||
#define CAN_TX_GPIO_PIN GPIO_PIN_9
|
||||
#define CAN_TX_GPIO_CLK_ENABLE() rcu_periph_clock_enable(RCU_GPIOB) /* PB口时钟使能 */
|
||||
|
||||
|
||||
static void CanInit(struct CanDriverConfigure *can_drv_config)
|
||||
{
|
||||
/* 1. 使能CAN0时钟 */
|
||||
rcu_periph_clock_enable(RCU_CAN0);
|
||||
|
||||
/* 2. GPIO配置 */
|
||||
CAN_RX_GPIO_CLK_ENABLE();
|
||||
CAN_TX_GPIO_CLK_ENABLE();
|
||||
|
||||
gpio_af_set(CAN_RX_GPIO_PORT, GPIO_AF_9, CAN_RX_GPIO_PIN);
|
||||
gpio_af_set(CAN_TX_GPIO_PORT, GPIO_AF_9, CAN_TX_GPIO_PIN);
|
||||
|
||||
gpio_mode_set(CAN_RX_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, CAN_RX_GPIO_PIN);
|
||||
gpio_mode_set(CAN_TX_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, CAN_TX_GPIO_PIN);
|
||||
|
||||
gpio_output_options_set(CAN_RX_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, CAN_RX_GPIO_PIN);
|
||||
gpio_output_options_set(CAN_TX_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, CAN_TX_GPIO_PIN);
|
||||
|
||||
/* 3. CAN初始化 */
|
||||
can_parameter_struct can_initpara;
|
||||
can_deinit(CAN0);
|
||||
can_initpara.working_mode = can_drv_config->mode; // CAN_NORMAL_MODE / CAN_LOOPBACK_MODE
|
||||
can_initpara.resync_jump_width = can_drv_config->tsjw;
|
||||
can_initpara.time_segment_1 = can_drv_config->tbs1;
|
||||
can_initpara.time_segment_2 = can_drv_config->tbs2;
|
||||
can_initpara.prescaler = can_drv_config->brp;
|
||||
can_init(CAN0, &can_initpara);
|
||||
|
||||
/* 4. CAN过滤器配置 */
|
||||
can_filter_parameter_struct can_filter;
|
||||
can_filter.filter_number = 0;
|
||||
can_filter.filter_mode = CAN_FILTERMODE_MASK;
|
||||
can_filter.filter_bits = CAN_FILTERBITS_32BIT; // 修改这里
|
||||
can_filter.filter_list_high = 0x0000;
|
||||
can_filter.filter_list_low = 0x0000;
|
||||
can_filter.filter_mask_high = 0x0000;
|
||||
can_filter.filter_mask_low = 0x0000;
|
||||
can_filter.filter_fifo_number = CAN_FIFO0;
|
||||
can_filter.filter_enable = ENABLE;
|
||||
can_filter_init(&can_filter);
|
||||
|
||||
}
|
||||
|
||||
static uint32 CanOpenDev(void * dev)
|
||||
{
|
||||
can_interrupt_enable(CAN0, CAN_INT_RFNE0); // FIFO0消息挂起中断
|
||||
nvic_irq_enable(CAN0_RX0_IRQn, 1, 0); // 中断优先级
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static uint32 CanCloseDev(void * dev)
|
||||
{
|
||||
// if (HAL_CAN_Stop(&hcan1) != HAL_OK) {
|
||||
// KPrintf("CAN stop failed\n");
|
||||
// }
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
/* CAN句柄结构 */
|
||||
can_trasnmit_message_struct g_canx_txmsg;
|
||||
can_receive_message_struct g_canx_rxmsg;
|
||||
can_parameter_struct g_canx;
|
||||
|
||||
/**
|
||||
* @brief CAN发送数据 (标准ID)
|
||||
* @param stdid: 标准ID (11位)
|
||||
* @param data : 数据指针
|
||||
* @param len : 数据长度 (最大8)
|
||||
* @retval 0:成功, 1:失败
|
||||
* void *dev,struct BusBlockWriteParam *write_param
|
||||
*/
|
||||
uint32 CAN_SendMsg(void *dev,struct BusBlockWriteParam *write_param)
|
||||
{
|
||||
uint8_t *data = (uint8_t *)write_param->buffer;
|
||||
uint32_t stdid = *(uint32_t *)data;
|
||||
data += sizeof(uint32_t);
|
||||
uint8_t len = write_param->size - sizeof(uint32_t);
|
||||
g_canx_txmsg.tx_sfid = stdid; // 标准ID
|
||||
g_canx_txmsg.tx_efid = 0; // 扩展ID不用
|
||||
g_canx_txmsg.tx_ft = CAN_FT_DATA; // 数据帧
|
||||
g_canx_txmsg.tx_ff = CAN_FF_STANDARD; // 标准帧
|
||||
g_canx_txmsg.tx_dlen = len; // 数据长度
|
||||
memcpy(g_canx_txmsg.tx_data, data, len);
|
||||
|
||||
if (can_message_transmit(CAN0, &g_canx_txmsg) != CAN_TRANSMIT_OK)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief CAN接收数据 (标准ID)
|
||||
* @param stdid: 要接收的标准ID (11位)
|
||||
* @param buf : 数据缓存区
|
||||
* @retval 接收到的数据长度，0表示未接收
|
||||
*/
|
||||
uint32 CAN_ReceiveMsg(void *dev, struct BusBlockReadParam *read_param)
|
||||
{
|
||||
uint8_t* buf = read_param->buffer;
|
||||
uint32_t stdid = *(uint32_t *)buf;
|
||||
can_message_receive(CAN0, CAN_FIFO0, &g_canx_rxmsg);
|
||||
if (g_canx_rxmsg.rx_ff != CAN_FF_STANDARD) // 标准帧判断
|
||||
return 0;
|
||||
|
||||
if (g_canx_rxmsg.rx_ft != CAN_FT_DATA) // 数据帧判断
|
||||
return 0;
|
||||
|
||||
if (g_canx_rxmsg.rx_sfid != stdid) // ID判断
|
||||
return 0;
|
||||
|
||||
memcpy(buf, g_canx_rxmsg.rx_data, g_canx_rxmsg.rx_dlen);
|
||||
return g_canx_rxmsg.rx_dlen;
|
||||
}
|
||||
|
||||
|
||||
|
||||
static struct CanDevDone can_dev_done =
|
||||
{
|
||||
.open = CanOpenDev,
|
||||
.close = CanCloseDev,
|
||||
.write = CAN_SendMsg,
|
||||
.read = CAN_ReceiveMsg
|
||||
};
|
||||
|
||||
|
||||
/*************************************************************************************************************
|
||||
* =======================================interrupt handler =============================================== **
|
||||
*************************************************************************************************************/
|
||||
void CAN0_RECIEVED(int irq_num, void *arg)
|
||||
{
|
||||
#ifdef BSP_USE_MOTOR
|
||||
CanMsgReceived();
|
||||
#endif
|
||||
}
|
||||
DECLARE_HW_IRQ(CAN0_RX0_IRQn, CAN0_RECIEVED, NONE);
|
||||
|
||||
|
||||
static uint32 CanDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
NULL_PARAM_CHECK(drv);
|
||||
NULL_PARAM_CHECK(configure_info);
|
||||
struct CanDriverConfigure *can_drv_config;
|
||||
switch (configure_info->configure_cmd)
|
||||
{
|
||||
case OPE_INT: // can basic init
|
||||
can_drv_config = (struct CanDriverConfigure *)configure_info->private_data;
|
||||
CanInit(can_drv_config);
|
||||
break;
|
||||
case OPE_CFG:
|
||||
//CanConfig(configure_info->private_data);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
|
||||
static int BoardCanBusInit(struct CanBus *can_bus, struct CanDriver *can_driver)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
/*Init the can bus */
|
||||
ret = CanBusInit(can_bus, CAN_BUS_NAME);
|
||||
if (EOK != ret) {
|
||||
KPrintf("Board_can_init canBusInit error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/*Init the can driver*/
|
||||
ret = CanDriverInit(can_driver, CAN_DRIVER_NAME);
|
||||
if (EOK != ret) {
|
||||
KPrintf("Board_can_init canDriverInit error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
/*Attach the can driver to the can bus*/
|
||||
ret = CanDriverAttachToBus(CAN_DRIVER_NAME, CAN_BUS_NAME);
|
||||
if (EOK != ret) {
|
||||
KPrintf("Board_can_init CanDriverAttachToBus error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Attach the can device to the can bus*/
|
||||
static int BoardCanDevBend(void)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
static struct CanHardwareDevice can_device;
|
||||
memset(&can_device, 0, sizeof(struct CanHardwareDevice));
|
||||
|
||||
can_device.dev_done = &can_dev_done;
|
||||
|
||||
ret = CanDeviceRegister(&can_device, NONE, CAN_DEVICE_NAME);
|
||||
if (EOK != ret) {
|
||||
KPrintf("board_can_init CanDeviceInit device %s error %d\n", CAN_DEVICE_NAME, ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = CanDeviceAttachToBus(CAN_DEVICE_NAME, CAN_BUS_NAME);
|
||||
if (EOK != ret) {
|
||||
KPrintf("board_can_init CanDeviceAttachToBus device %s error %d\n", CAN_DEVICE_NAME, ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int HwCanInit(void)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
static struct CanBus can_bus;
|
||||
memset(&can_bus, 0, sizeof(struct CanBus));
|
||||
|
||||
static struct CanDriver can_driver;
|
||||
memset(&can_driver, 0, sizeof(struct CanDriver));
|
||||
|
||||
can_driver.configure = &(CanDrvConfigure);
|
||||
|
||||
ret = BoardCanBusInit(&can_bus, &can_driver);
|
||||
if (EOK != ret) {
|
||||
KPrintf(" can_bus_init %s error ret %u\n", CAN_BUS_NAME, ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = BoardCanDevBend();
|
||||
if (EOK != ret) {
|
||||
KPrintf("board_can_init error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
#if 0
|
||||
static struct Bus *bus;
|
||||
static struct HardwareDev *dev;
|
||||
static struct Driver *drv;
|
||||
|
||||
uint32 StartCan(void)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
bus = BusFind(CAN_BUS_NAME);
|
||||
dev = BusFindDevice(bus, CAN_DEVICE_NAME);
|
||||
drv = BusFindDriver(bus, CAN_DRIVER_NAME);
|
||||
|
||||
struct BusConfigureInfo configure_info;
|
||||
struct CanDriverConfigure can_config;
|
||||
can_config.brp = 3;
|
||||
can_config.mode = 0;
|
||||
can_config.tbs1 = 11;
|
||||
can_config.tbs2 = 3;
|
||||
can_config.tsjw = 1;
|
||||
|
||||
configure_info.configure_cmd = OPE_INT;
|
||||
configure_info.private_data = (void *)&can_config;
|
||||
ret = BusDrvConfigure(drv, &configure_info);
|
||||
if (ret != EOK) {
|
||||
KPrintf("configure can error\n");
|
||||
return ERROR;
|
||||
}
|
||||
// ret = BusDevOpen(dev);
|
||||
// if (ret != EOK) {
|
||||
// KPrintf("BusDevOpen error %d\n", ret);
|
||||
// return ERROR;
|
||||
// }
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
|
||||
static uint32 TestCan(void)
|
||||
{
|
||||
uint8_t rxbuf[8];
|
||||
uint8_t len = CAN0_ReceiveMsg(0x000, rxbuf); // 可修改id过滤
|
||||
KPrintf("len is %d\n",len);
|
||||
{
|
||||
uint32_t send_id = 0x100;
|
||||
uint8_t send_buf[8] = {0};
|
||||
uint8_t send_len = 0;
|
||||
|
||||
// handleCanMessage(0x000, len, rxbuf, &send_id, send_buf, &send_len);
|
||||
CAN0_SendMsg(send_id, send_buf, send_len);
|
||||
}
|
||||
|
||||
}
|
||||
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN),
|
||||
TestCan, TestCan, open can device and write_read parameters);
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file connect_adc.h
|
||||
* @brief define stm32f446ret6 adc function and struct
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2025-7-31
|
||||
*/
|
||||
|
||||
#ifndef CONNECT_ADC_H
|
||||
#define CONNECT_ADC_H
|
||||
|
||||
#include <device.h>
|
||||
#include "gd32f4xx.h"
|
||||
#include "gd32f4xx_adc.h"
|
||||
#include "gd32f4xx_gpio.h"
|
||||
|
||||
|
||||
struct HwAdc
|
||||
{
|
||||
void *ADCx;
|
||||
uint8 adc_channel;
|
||||
};
|
||||
|
||||
int HwAdcInit(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* Copyright (c) 2021 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file connect_can.h
|
||||
* @brief define stm32l476 can function and struct
|
||||
* @version 2.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2025-03-14
|
||||
*/
|
||||
|
||||
#ifndef CONNECT_CAN_H
|
||||
#define CONNECT_CAN_H
|
||||
|
||||
#include <device.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
int HwCanInit(void);
|
||||
uint32 StartCan();
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* Copyright (c) 2021 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
/**
|
||||
* @file connect_hwtimer.h
|
||||
* @brief define stm32f446 can function and struct
|
||||
* @version 2.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2025-03-14
|
||||
*/
|
||||
|
||||
#ifndef CONNECT_HWTIMER_H
|
||||
#define CONNECT_HWTIMER_H
|
||||
|
||||
#include <device.h>
|
||||
#include "gd32f4xx_timer.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
int Stm32HwTimerInit(void);
|
||||
int HardwareTimerInit(void);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file connect_adc.h
|
||||
* @brief define stm32f446ret6 adc function and struct
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2025-7-31
|
||||
*/
|
||||
|
||||
#ifndef CONNECT_MOTOR_H
|
||||
#define CONNECT_MOTOR_H
|
||||
|
||||
#include <device.h>
|
||||
|
||||
|
||||
struct XiZiCommonDevice
|
||||
{
|
||||
struct Bus *bus;
|
||||
struct HardwareDev *dev;
|
||||
struct Driver *drv;
|
||||
};
|
||||
|
||||
struct MotorDriver
|
||||
{
|
||||
struct XiZiCommonDevice motor_control;
|
||||
struct XiZiCommonDevice motor_encoder;
|
||||
struct XiZiCommonDevice motor_can_protocal;
|
||||
|
||||
int type; // 控制类型
|
||||
float position; // 位置控制目标 (rad)
|
||||
float speed; // 速度控制目标 (rad/s)
|
||||
float torque_norm_d; // 力矩控制目标 d 轴分量 (归一化)
|
||||
float torque_norm_q; // 力矩控制目标 q 轴分量 (归一化)
|
||||
float mit_torque; // MIT 控制目标力矩 (Nm)
|
||||
};
|
||||
|
||||
|
||||
int InitHwMotor(void);
|
||||
int MotorStart(void);
|
||||
void CanMsgReceived(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file connect_spi.h
|
||||
* @brief define stm32l476 spi function and struct
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2025-03-04
|
||||
*/
|
||||
|
||||
#ifndef CONNECT_SPI_H
|
||||
#define CONNECT_SPI_H
|
||||
|
||||
#include <device.h>
|
||||
#include "gd32f4xx_spi.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
// struct UsartHwCfg
|
||||
// {
|
||||
// SPI_HandleTypeDef *hspi2;
|
||||
// };
|
||||
|
||||
int HwSpiInit(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file connect_uart.h
|
||||
* @brief define gd32f425 uart function and struct
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2025-09-19
|
||||
*/
|
||||
|
||||
#ifndef CONNECT_UART_H
|
||||
#define CONNECT_UART_H
|
||||
|
||||
#include <device.h>
|
||||
#include <gd32f4xx_usart.h>
|
||||
#include <gd32f4xx.h>
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME
|
||||
#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME
|
||||
#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_DEVICE_NAME
|
||||
|
||||
|
||||
|
||||
|
||||
int InitHwUart(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
SRC_DIR := src
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,697 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cm4_simd.h
|
||||
* @brief CMSIS Cortex-M4 SIMD Header File
|
||||
* @version V3.30
|
||||
* @date 17. February 2014
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2014 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM4_SIMD_H
|
||||
#define __CORE_CM4_SIMD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||
((int64_t)(ARG3) << 32) ) >> 32))
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#define __SSAT16(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
#define __USAT16(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||
{
|
||||
union llreg_u{
|
||||
uint32_t w32[2];
|
||||
uint64_t w64;
|
||||
} llr;
|
||||
llr.w64 = acc;
|
||||
|
||||
#ifndef __ARMEB__ // Little endian
|
||||
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||
#else // Big endian
|
||||
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
||||
#endif
|
||||
|
||||
return(llr.w64);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||
{
|
||||
union llreg_u{
|
||||
uint32_t w32[2];
|
||||
uint64_t w64;
|
||||
} llr;
|
||||
llr.w64 = acc;
|
||||
|
||||
#ifndef __ARMEB__ // Little endian
|
||||
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||
#else // Big endian
|
||||
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
||||
#endif
|
||||
|
||||
return(llr.w64);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||
{
|
||||
union llreg_u{
|
||||
uint32_t w32[2];
|
||||
uint64_t w64;
|
||||
} llr;
|
||||
llr.w64 = acc;
|
||||
|
||||
#ifndef __ARMEB__ // Little endian
|
||||
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||
#else // Big endian
|
||||
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
||||
#endif
|
||||
|
||||
return(llr.w64);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||
{
|
||||
union llreg_u{
|
||||
uint32_t w32[2];
|
||||
uint64_t w64;
|
||||
} llr;
|
||||
llr.w64 = acc;
|
||||
|
||||
#ifndef __ARMEB__ // Little endian
|
||||
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||
#else // Big endian
|
||||
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
||||
#endif
|
||||
|
||||
return(llr.w64);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
||||
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
||||
if (ARG3 == 0) \
|
||||
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
|
||||
else \
|
||||
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
/* not yet supported */
|
||||
|
||||
|
||||
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
|
||||
/* Cosmic specific functions */
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM4_SIMD_H */
|
||||
|
|
@ -0,0 +1,616 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmFunc.h
|
||||
* @brief CMSIS Cortex-M Core Function Access Header File
|
||||
* @version V3.01
|
||||
* @date 06. March 2012
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __CORE_CMFUNC_H
|
||||
#define __CORE_CMFUNC_H
|
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
#if (__ARMCC_VERSION < 400677)
|
||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* intrinsic void __enable_irq(); */
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/** \brief Get Control Register
|
||||
|
||||
This function returns the content of the Control Register.
|
||||
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Control Register
|
||||
|
||||
This function writes the given value to the Control Register.
|
||||
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get IPSR Register
|
||||
|
||||
This function returns the content of the IPSR Register.
|
||||
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get APSR Register
|
||||
|
||||
This function returns the content of the APSR Register.
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get xPSR Register
|
||||
|
||||
This function returns the content of the xPSR Register.
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Process Stack Pointer
|
||||
|
||||
This function returns the current value of the Process Stack Pointer (PSP).
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Main Stack Pointer
|
||||
|
||||
This function returns the current value of the Main Stack Pointer (MSP).
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Priority Mask
|
||||
|
||||
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Priority Mask
|
||||
|
||||
This function assigns the given value to the Priority Mask Register.
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/** \brief Disable FIQ
|
||||
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/** \brief Get Base Priority
|
||||
|
||||
This function returns the current value of the Base Priority register.
|
||||
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Base Priority
|
||||
|
||||
This function assigns the given value to the Base Priority register.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xff);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Fault Mask
|
||||
|
||||
This function returns the current value of the Fault Mask register.
|
||||
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Fault Mask
|
||||
|
||||
This function assigns the given value to the Fault Mask register.
|
||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1);
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
This function returns the current value of the Floating Point Status/Control register.
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
|
||||
|
||||
This function assigns the given value to the Floating Point Status/Control register.
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) */
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/** \brief Enable IRQ Interrupts
|
||||
|
||||
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie i");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable IRQ Interrupts
|
||||
|
||||
This function disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid i");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Control Register
|
||||
|
||||
This function returns the content of the Control Register.
|
||||
|
||||
\return Control Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, control" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Control Register
|
||||
|
||||
This function writes the given value to the Control Register.
|
||||
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
__ASM volatile ("MSR control, %0" : : "r" (control) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get IPSR Register
|
||||
|
||||
This function returns the content of the IPSR Register.
|
||||
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get APSR Register
|
||||
|
||||
This function returns the content of the APSR Register.
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get xPSR Register
|
||||
|
||||
This function returns the content of the xPSR Register.
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Process Stack Pointer
|
||||
|
||||
This function returns the current value of the Process Stack Pointer (PSP).
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Main Stack Pointer
|
||||
|
||||
This function returns the current value of the Main Stack Pointer (MSP).
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Priority Mask
|
||||
|
||||
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Priority Mask
|
||||
|
||||
This function assigns the given value to the Priority Mask Register.
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie f");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable FIQ
|
||||
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid f");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Base Priority
|
||||
|
||||
This function returns the current value of the Base Priority register.
|
||||
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Base Priority
|
||||
|
||||
This function assigns the given value to the Base Priority register.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Fault Mask
|
||||
|
||||
This function returns the current value of the Fault Mask register.
|
||||
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Fault Mask
|
||||
|
||||
This function assigns the given value to the Fault Mask register.
|
||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
This function returns the current value of the Floating Point Status/Control register.
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
|
||||
return(result);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
|
||||
|
||||
This function assigns the given value to the Floating Point Status/Control register.
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) */
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
#endif /* __CORE_CMFUNC_H */
|
||||
|
|
@ -0,0 +1,618 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h
|
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||
* @version V3.01
|
||||
* @date 06. March 2012
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __CORE_CMINSTR_H
|
||||
#define __CORE_CMINSTR_H
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
#if (__ARMCC_VERSION < 400677)
|
||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() __isb(0xF)
|
||||
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() __dsb(0xF)
|
||||
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() __dmb(0xF)
|
||||
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
|
||||
/** \brief Rotate Right in unsigned value (32 bit)
|
||||
|
||||
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\param [in] value Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __RBIT __rbit
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive STR command for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive STR command for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive STR command for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
|
||||
{
|
||||
__ASM volatile ("nop");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
|
||||
{
|
||||
__ASM volatile ("wfi");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
|
||||
{
|
||||
__ASM volatile ("wfe");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
|
||||
{
|
||||
__ASM volatile ("sev");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
|
||||
{
|
||||
__ASM volatile ("isb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
|
||||
{
|
||||
__ASM volatile ("dsb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
|
||||
{
|
||||
__ASM volatile ("dmb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Rotate Right in unsigned value (32 bit)
|
||||
|
||||
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\param [in] value Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
|
||||
__ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
|
||||
return(op1);
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
|
||||
{
|
||||
uint8_t result;
|
||||
|
||||
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
|
||||
{
|
||||
uint16_t result;
|
||||
|
||||
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive STR command for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive STR command for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive STR command for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
|
||||
{
|
||||
__ASM volatile ("clrex");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
|
||||
{
|
||||
uint8_t result;
|
||||
|
||||
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
#endif /* __CORE_CMINSTR_H */
|
||||
|
|
@ -0,0 +1,367 @@
|
|||
/*!
|
||||
\file gd32f4xx.h
|
||||
\brief general definitions for GD32F4xx
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_H
|
||||
#define GD32F4XX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* define GD32F4xx */
|
||||
#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) && !defined (GD32F470) && !defined (GD32F425) && !defined (GD32F427)
|
||||
/* #define GD32F450 */
|
||||
/* #define GD32F405 */
|
||||
/* #define GD32F407 */
|
||||
/* #define GD32F470 */
|
||||
/* #define GD32F425 */
|
||||
/* #define GD32F427 */
|
||||
#endif /* define GD32F4xx */
|
||||
|
||||
#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) && !defined (GD32F470) && !defined (GD32F425) && !defined (GD32F427)
|
||||
//#error "Please select the target GD32F4xx device in gd32f4xx.h file"
|
||||
#endif /* undefine GD32F4xx tip */
|
||||
|
||||
/* define value of high speed crystal oscillator (HXTAL) in Hz */
|
||||
#if !defined (HXTAL_VALUE)
|
||||
#define HXTAL_VALUE ((uint32_t)25000000)
|
||||
#endif /* high speed crystal oscillator value */
|
||||
|
||||
/* define startup timeout value of high speed crystal oscillator (HXTAL) */
|
||||
#if !defined (HXTAL_STARTUP_TIMEOUT)
|
||||
#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF)
|
||||
#endif /* high speed crystal oscillator startup timeout */
|
||||
|
||||
/* define value of internal 16MHz RC oscillator (IRC16M) in Hz */
|
||||
#if !defined (IRC16M_VALUE)
|
||||
#define IRC16M_VALUE ((uint32_t)16000000)
|
||||
#endif /* internal 16MHz RC oscillator value */
|
||||
|
||||
/* define startup timeout value of internal 16MHz RC oscillator (IRC16M) */
|
||||
#if !defined (IRC16M_STARTUP_TIMEOUT)
|
||||
#define IRC16M_STARTUP_TIMEOUT ((uint16_t)0x0500)
|
||||
#endif /* internal 16MHz RC oscillator startup timeout */
|
||||
|
||||
/* define value of internal 32KHz RC oscillator(IRC32K) in Hz */
|
||||
#if !defined (IRC32K_VALUE)
|
||||
#define IRC32K_VALUE ((uint32_t)32000)
|
||||
#endif /* internal 32KHz RC oscillator value */
|
||||
|
||||
/* define value of low speed crystal oscillator (LXTAL)in Hz */
|
||||
#if !defined (LXTAL_VALUE)
|
||||
#define LXTAL_VALUE ((uint32_t)32768)
|
||||
#endif /* low speed crystal oscillator value */
|
||||
|
||||
/* I2S external clock in selection */
|
||||
//#define I2S_EXTERNAL_CLOCK_IN (uint32_t)12288000U
|
||||
|
||||
/* GD32F4xx firmware library version number V1.0 */
|
||||
#define __GD32F4xx_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */
|
||||
#define __GD32F4xx_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
|
||||
#define __GD32F4xx_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __GD32F4xx_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __GD32F4xx_STDPERIPH_VERSION ((__GD32F4xx_STDPERIPH_VERSION_MAIN << 24)\
|
||||
|(__GD32F4xx_STDPERIPH_VERSION_SUB1 << 16)\
|
||||
|(__GD32F4xx_STDPERIPH_VERSION_SUB2 << 8)\
|
||||
|(__GD32F4xx_STDPERIPH_VERSION_RC))
|
||||
|
||||
/* configuration of the cortex-M4 processor and core peripherals */
|
||||
#define __CM4_REV 0x0001 /*!< core revision r0p1 */
|
||||
#define __MPU_PRESENT 1 /*!< GD32F4xx provide MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< GD32F4xx uses 4 bits for the priority levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
/* define interrupt number */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/* cortex-M4 processor exceptions numbers */
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 cortex-M4 memory management interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 cortex-M4 bus fault interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 cortex-M4 usage fault interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 cortex-M4 SV call interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 cortex-M4 debug monitor interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 cortex-M4 pend SV interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 cortex-M4 system tick interrupt */
|
||||
/* interruput numbers */
|
||||
WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */
|
||||
LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */
|
||||
TAMPER_STAMP_IRQn = 2, /*!< tamper and timestamp through EXTI line detect */
|
||||
RTC_WKUP_IRQn = 3, /*!< RTC wakeup through EXTI line interrupt */
|
||||
FMC_IRQn = 4, /*!< FMC interrupt */
|
||||
RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */
|
||||
EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */
|
||||
EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */
|
||||
EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */
|
||||
EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */
|
||||
EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */
|
||||
DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 Interrupt */
|
||||
DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 Interrupt */
|
||||
DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */
|
||||
DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */
|
||||
DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */
|
||||
DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */
|
||||
DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */
|
||||
ADC_IRQn = 18, /*!< ADC interrupt */
|
||||
CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupt */
|
||||
CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupt */
|
||||
CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupt */
|
||||
CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupt */
|
||||
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
|
||||
TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */
|
||||
TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */
|
||||
TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */
|
||||
TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */
|
||||
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
|
||||
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
|
||||
TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
|
||||
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
|
||||
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
|
||||
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
|
||||
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
|
||||
SPI0_IRQn = 35, /*!< SPI0 interrupt */
|
||||
SPI1_IRQn = 36, /*!< SPI1 interrupt */
|
||||
USART0_IRQn = 37, /*!< USART0 interrupt */
|
||||
USART1_IRQn = 38, /*!< USART1 interrupt */
|
||||
USART2_IRQn = 39, /*!< USART2 interrupt */
|
||||
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
|
||||
RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
|
||||
USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */
|
||||
TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */
|
||||
TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */
|
||||
TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */
|
||||
TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */
|
||||
DMA0_Channel7_IRQn = 47, /*!< DMA0 channel7 interrupt */
|
||||
|
||||
#if defined (GD32F450) || defined (GD32F470)
|
||||
EXMC_IRQn = 48, /*!< EXMC interrupt */
|
||||
SDIO_IRQn = 49, /*!< SDIO interrupt */
|
||||
TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
|
||||
SPI2_IRQn = 51, /*!< SPI2 interrupt */
|
||||
UART3_IRQn = 52, /*!< UART3 interrupt */
|
||||
UART4_IRQn = 53, /*!< UART4 interrupt */
|
||||
TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */
|
||||
TIMER6_IRQn = 55, /*!< TIMER6 interrupt */
|
||||
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */
|
||||
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */
|
||||
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */
|
||||
DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */
|
||||
DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */
|
||||
ENET_IRQn = 61, /*!< ENET interrupt */
|
||||
ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */
|
||||
CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
|
||||
CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
|
||||
CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
|
||||
CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
|
||||
USBFS_IRQn = 67, /*!< USBFS interrupt */
|
||||
DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */
|
||||
DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */
|
||||
DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */
|
||||
USART5_IRQn = 71, /*!< USART5 interrupt */
|
||||
I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */
|
||||
I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */
|
||||
USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */
|
||||
USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */
|
||||
USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */
|
||||
USBHS_IRQn = 77, /*!< USBHS interrupt */
|
||||
DCI_IRQn = 78, /*!< DCI interrupt */
|
||||
TRNG_IRQn = 80, /*!< TRNG interrupt */
|
||||
FPU_IRQn = 81, /*!< FPU interrupt */
|
||||
UART6_IRQn = 82, /*!< UART6 interrupt */
|
||||
UART7_IRQn = 83, /*!< UART7 interrupt */
|
||||
SPI3_IRQn = 84, /*!< SPI3 interrupt */
|
||||
SPI4_IRQn = 85, /*!< SPI4 interrupt */
|
||||
SPI5_IRQn = 86, /*!< SPI5 interrupt */
|
||||
TLI_IRQn = 88, /*!< TLI interrupt */
|
||||
TLI_ER_IRQn = 89, /*!< TLI error interrupt */
|
||||
IPA_IRQn = 90, /*!< IPA interrupt */
|
||||
#endif /* GD32F450 and GD32F470 */
|
||||
|
||||
#if defined (GD32F405) || defined (GD32F425)
|
||||
SDIO_IRQn = 49, /*!< SDIO interrupt */
|
||||
TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
|
||||
SPI2_IRQn = 51, /*!< SPI2 interrupt */
|
||||
UART3_IRQn = 52, /*!< UART3 interrupt */
|
||||
UART4_IRQn = 53, /*!< UART4 interrupt */
|
||||
TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */
|
||||
TIMER6_IRQn = 55, /*!< TIMER6 interrupt */
|
||||
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */
|
||||
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */
|
||||
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */
|
||||
DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */
|
||||
DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */
|
||||
CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
|
||||
CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
|
||||
CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
|
||||
CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
|
||||
USBFS_IRQn = 67, /*!< USBFS interrupt */
|
||||
DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */
|
||||
DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */
|
||||
DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */
|
||||
USART5_IRQn = 71, /*!< USART5 interrupt */
|
||||
I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */
|
||||
I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */
|
||||
USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 Out interrupt */
|
||||
USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */
|
||||
USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */
|
||||
USBHS_IRQn = 77, /*!< USBHS interrupt */
|
||||
DCI_IRQn = 78, /*!< DCI interrupt */
|
||||
TRNG_IRQn = 80, /*!< TRNG interrupt */
|
||||
FPU_IRQn = 81, /*!< FPU interrupt */
|
||||
#endif /* GD32F405 and GD32F425 */
|
||||
|
||||
#if defined (GD32F407) || defined (GD32F427)
|
||||
EXMC_IRQn = 48, /*!< EXMC interrupt */
|
||||
SDIO_IRQn = 49, /*!< SDIO interrupt */
|
||||
TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
|
||||
SPI2_IRQn = 51, /*!< SPI2 interrupt */
|
||||
UART3_IRQn = 52, /*!< UART3 interrupt */
|
||||
UART4_IRQn = 53, /*!< UART4 interrupt */
|
||||
TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */
|
||||
TIMER6_IRQn = 55, /*!< TIMER6 interrupt */
|
||||
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */
|
||||
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */
|
||||
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */
|
||||
DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */
|
||||
DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */
|
||||
ENET_IRQn = 61, /*!< ENET interrupt */
|
||||
ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */
|
||||
CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
|
||||
CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
|
||||
CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
|
||||
CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
|
||||
USBFS_IRQn = 67, /*!< USBFS interrupt */
|
||||
DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */
|
||||
DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */
|
||||
DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */
|
||||
USART5_IRQn = 71, /*!< USART5 interrupt */
|
||||
I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */
|
||||
I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */
|
||||
USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */
|
||||
USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */
|
||||
USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */
|
||||
USBHS_IRQn = 77, /*!< USBHS interrupt */
|
||||
DCI_IRQn = 78, /*!< DCI interrupt */
|
||||
TRNG_IRQn = 80, /*!< TRNG interrupt */
|
||||
FPU_IRQn = 81, /*!< FPU interrupt */
|
||||
#endif /* GD32F407 and GD32F427 */
|
||||
|
||||
} IRQn_Type;
|
||||
|
||||
/* includes */
|
||||
#include "core_cm4.h"
|
||||
#include "system_gd32f4xx.h"
|
||||
#include <stdint.h>
|
||||
#undef ERROR
|
||||
/* enum definitions */
|
||||
typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
|
||||
typedef enum {RESET = 0, SET = !RESET} FlagStatus;
|
||||
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
|
||||
/* bit operations */
|
||||
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
|
||||
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
|
||||
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
|
||||
#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
|
||||
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
|
||||
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
|
||||
|
||||
/* main flash and SRAM memory map */
|
||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
|
||||
#define TCMSRAM_BASE ((uint32_t)0x10000000U) /*!< TCMSRAM(64KB) base address */
|
||||
#define OPTION_BASE ((uint32_t)0x1FFEC000U) /*!< Option bytes base address */
|
||||
#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */
|
||||
|
||||
/* peripheral memory map */
|
||||
#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
|
||||
#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
|
||||
#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */
|
||||
#define AHB2_BUS_BASE ((uint32_t)0x50000000U) /*!< ahb2 base address */
|
||||
|
||||
/* EXMC memory map */
|
||||
#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */
|
||||
|
||||
/* advanced peripheral bus 1 memory map */
|
||||
#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
|
||||
#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
|
||||
#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
|
||||
#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
|
||||
#define I2S_ADD_BASE (APB1_BUS_BASE + 0x00003400U) /*!< I2S1_add base address */
|
||||
#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
|
||||
#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
|
||||
#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
|
||||
#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */
|
||||
#define CTC_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< CTC base address */
|
||||
#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
|
||||
#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
|
||||
#define IREF_BASE (APB1_BUS_BASE + 0x0000C400U) /*!< IREF base address */
|
||||
|
||||
/* advanced peripheral bus 2 memory map */
|
||||
#define TLI_BASE (APB2_BUS_BASE + 0x00006800U) /*!< TLI base address */
|
||||
#define SYSCFG_BASE (APB2_BUS_BASE + 0x00003800U) /*!< SYSCFG base address */
|
||||
#define EXTI_BASE (APB2_BUS_BASE + 0x00003C00U) /*!< EXTI base address */
|
||||
#define SDIO_BASE (APB2_BUS_BASE + 0x00002C00U) /*!< SDIO base address */
|
||||
#define ADC_BASE (APB2_BUS_BASE + 0x00002000U) /*!< ADC base address */
|
||||
/* advanced high performance bus 1 memory map */
|
||||
#define GPIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< GPIO base address */
|
||||
#define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */
|
||||
#define RCU_BASE (AHB1_BUS_BASE + 0x00003800U) /*!< RCU base address */
|
||||
#define FMC_BASE (AHB1_BUS_BASE + 0x00003C00U) /*!< FMC base address */
|
||||
#define BKPSRAM_BASE (AHB1_BUS_BASE + 0x00004000U) /*!< BKPSRAM base address */
|
||||
#define DMA_BASE (AHB1_BUS_BASE + 0x00006000U) /*!< DMA base address */
|
||||
#define ENET_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< ENET base address */
|
||||
#define IPA_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< IPA base address */
|
||||
#define USBHS_BASE (AHB1_BUS_BASE + 0x00020000U) /*!< USBHS base address */
|
||||
|
||||
/* advanced high performance bus 2 memory map */
|
||||
#define USBFS_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< USBFS base address */
|
||||
#define DCI_BASE (AHB2_BUS_BASE + 0x00050000U) /*!< DCI base address */
|
||||
#define TRNG_BASE (AHB2_BUS_BASE + 0x00060800U) /*!< TRNG base address */
|
||||
/* option byte and debug memory map */
|
||||
#define OB_BASE ((uint32_t)0x1FFEC000U) /*!< OB base address */
|
||||
#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */
|
||||
|
||||
/* define marco USE_STDPERIPH_DRIVER */
|
||||
#if !defined USE_STDPERIPH_DRIVER
|
||||
#define USE_STDPERIPH_DRIVER
|
||||
#endif
|
||||
#ifdef USE_STDPERIPH_DRIVER
|
||||
//#include "gd32f4xx_libopt.h"
|
||||
#endif /* USE_STDPERIPH_DRIVER */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,516 @@
|
|||
/*!
|
||||
\file gd32f4xx_adc.h
|
||||
\brief definitions for the ADC
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_ADC_H
|
||||
#define GD32F4XX_ADC_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* ADC definitions */
|
||||
#define ADC0 ADC_BASE
|
||||
#define ADC1 (ADC_BASE + 0x100U)
|
||||
#define ADC2 (ADC_BASE + 0x200U)
|
||||
|
||||
/* registers definitions */
|
||||
#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */
|
||||
#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */
|
||||
#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */
|
||||
#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */
|
||||
#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */
|
||||
#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */
|
||||
#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */
|
||||
#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */
|
||||
#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */
|
||||
#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */
|
||||
#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */
|
||||
#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC routine sequence register 0 */
|
||||
#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC routine sequence register 1 */
|
||||
#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC routine sequence register 2 */
|
||||
#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */
|
||||
#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */
|
||||
#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */
|
||||
#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */
|
||||
#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */
|
||||
#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC routine data register */
|
||||
#define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x80U) /*!< ADC oversampling control register */
|
||||
#define ADC_SSTAT REG32((ADC_BASE) + 0x300U) /*!< ADC summary status register */
|
||||
#define ADC_SYNCCTL REG32((ADC_BASE) + 0x304U) /*!< ADC synchronization control register */
|
||||
#define ADC_SYNCDATA REG32((ADC_BASE) + 0x308U) /*!< ADC synchronization routine data register */
|
||||
|
||||
/* bits definitions */
|
||||
/* ADC_STAT */
|
||||
#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */
|
||||
#define ADC_STAT_EOC BIT(1) /*!< end of conversion */
|
||||
#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */
|
||||
#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */
|
||||
#define ADC_STAT_STRC BIT(4) /*!< routine channel start flag */
|
||||
#define ADC_STAT_ROVF BIT(5) /*!< routine data register overflow */
|
||||
|
||||
/* ADC_CTL0 */
|
||||
#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */
|
||||
#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */
|
||||
#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */
|
||||
#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */
|
||||
#define ADC_CTL0_SM BIT(8) /*!< scan mode */
|
||||
#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */
|
||||
#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted sequence conversion */
|
||||
#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on routine channels */
|
||||
#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */
|
||||
#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */
|
||||
#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */
|
||||
#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on routine channels */
|
||||
#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */
|
||||
#define ADC_CTL0_ROVFIE BIT(26) /*!< interrupt enable for ROVF */
|
||||
|
||||
/* ADC_CTL1 */
|
||||
#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */
|
||||
#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */
|
||||
#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */
|
||||
#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */
|
||||
#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */
|
||||
#define ADC_CTL1_DDM BIT(9) /*!< DMA disable mode */
|
||||
#define ADC_CTL1_EOCM BIT(10) /*!< end of conversion mode */
|
||||
#define ADC_CTL1_DAL BIT(11) /*!< data alignment */
|
||||
#define ADC_CTL1_ETSIC BITS(16,19) /*!< external event select for inserted sequence */
|
||||
#define ADC_CTL1_ETMIC BITS(20,21) /*!< external trigger conversion mode for inserted channels */
|
||||
#define ADC_CTL1_SWICST BIT(22) /*!< start conversion of inserted channels */
|
||||
#define ADC_CTL1_ETSRC BITS(24,27) /*!< external event select for routine sequence */
|
||||
#define ADC_CTL1_ETMRC BITS(28,29) /*!< external trigger conversion mode for routine channels */
|
||||
#define ADC_CTL1_SWRCST BIT(30) /*!< start conversion of routine channels */
|
||||
|
||||
/* ADC_SAMPTx x=0..1 */
|
||||
#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel x sample time selection */
|
||||
|
||||
/* ADC_IOFFx x=0..3 */
|
||||
#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */
|
||||
|
||||
/* ADC_WDHT */
|
||||
#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */
|
||||
|
||||
/* ADC_WDLT */
|
||||
#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */
|
||||
|
||||
/* ADC_RSQx */
|
||||
#define ADC_RSQX_RSQN BITS(0,4) /*!< x conversion in routine sequence */
|
||||
#define ADC_RSQ0_RL BITS(20,23) /*!< routine channel sequence length */
|
||||
|
||||
/* ADC_ISQ */
|
||||
#define ADC_ISQ_ISQN BITS(0,4) /*!< x conversion in inserted sequence */
|
||||
#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */
|
||||
|
||||
/* ADC_IDATAx x=0..3*/
|
||||
#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data x */
|
||||
|
||||
/* ADC_RDATA */
|
||||
#define ADC_RDATA_RDATA BITS(0,15) /*!< routine data */
|
||||
|
||||
/* ADC_OVSAMPCTL */
|
||||
#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */
|
||||
#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */
|
||||
#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */
|
||||
#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */
|
||||
|
||||
/* ADC_SSTAT */
|
||||
#define ADC_SSTAT_WDE0 BIT(0) /*!< the mirror image of the WDE bit of ADC0 */
|
||||
#define ADC_SSTAT_EOC0 BIT(1) /*!< the mirror image of the EOC bit of ADC0 */
|
||||
#define ADC_SSTAT_EOIC0 BIT(2) /*!< the mirror image of the EOIC bit of ADC0 */
|
||||
#define ADC_SSTAT_STIC0 BIT(3) /*!< the mirror image of the STIC bit of ADC0 */
|
||||
#define ADC_SSTAT_STRC0 BIT(4) /*!< the mirror image of the STRC bit of ADC0 */
|
||||
#define ADC_SSTAT_ROVF0 BIT(5) /*!< the mirror image of the ROVF bit of ADC0 */
|
||||
#define ADC_SSTAT_WDE1 BIT(8) /*!< the mirror image of the WDE bit of ADC1 */
|
||||
#define ADC_SSTAT_EOC1 BIT(9) /*!< the mirror image of the EOC bit of ADC1 */
|
||||
#define ADC_SSTAT_EOIC1 BIT(10) /*!< the mirror image of the EOIC bit of ADC1 */
|
||||
#define ADC_SSTAT_STIC1 BIT(11) /*!< the mirror image of the STIC bit of ADC1 */
|
||||
#define ADC_SSTAT_STRC1 BIT(12) /*!< the mirror image of the STRC bit of ADC1 */
|
||||
#define ADC_SSTAT_ROVF1 BIT(13) /*!< the mirror image of the ROVF bit of ADC1 */
|
||||
#define ADC_SSTAT_WDE2 BIT(16) /*!< the mirror image of the WDE bit of ADC2 */
|
||||
#define ADC_SSTAT_EOC2 BIT(17) /*!< the mirror image of the EOC bit of ADC2 */
|
||||
#define ADC_SSTAT_EOIC2 BIT(18) /*!< the mirror image of the EOIC bit of ADC2 */
|
||||
#define ADC_SSTAT_STIC2 BIT(19) /*!< the mirror image of the STIC bit of ADC2 */
|
||||
#define ADC_SSTAT_STRC2 BIT(20) /*!< the mirror image of the STRC bit of ADC2 */
|
||||
#define ADC_SSTAT_ROVF2 BIT(21) /*!< the mirror image of the ROVF bit of ADC2 */
|
||||
|
||||
/* ADC_SYNCCTL */
|
||||
#define ADC_SYNCCTL_SYNCM BITS(0,4) /*!< ADC synchronization mode */
|
||||
#define ADC_SYNCCTL_SYNCDLY BITS(8,11) /*!< ADC synchronization delay */
|
||||
#define ADC_SYNCCTL_SYNCDDM BIT(13) /*!< ADC synchronization DMA disable mode */
|
||||
#define ADC_SYNCCTL_SYNCDMA BITS(14,15) /*!< ADC synchronization DMA mode selection */
|
||||
#define ADC_SYNCCTL_ADCCK BITS(16,18) /*!< ADC clock */
|
||||
#define ADC_SYNCCTL_VBATEN BIT(22) /*!< channel 18 (1/4 voltate of external battery) enable of ADC0 */
|
||||
#define ADC_SYNCCTL_TSVREN BIT(23) /*!< channel 16 (temperature sensor) and 17 (internal reference voltage) enable of ADC0 */
|
||||
|
||||
/* ADC_SYNCDATA */
|
||||
#define ADC_SYNCDATA_SYNCDATA0 BITS(0,15) /*!< routine data1 in ADC synchronization mode */
|
||||
#define ADC_SYNCDATA_SYNCDATA1 BITS(16,31) /*!< routine data2 in ADC synchronization mode */
|
||||
|
||||
/* constants definitions */
|
||||
/* ADC status flag */
|
||||
#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */
|
||||
#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */
|
||||
#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */
|
||||
#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */
|
||||
#define ADC_FLAG_STRC ADC_STAT_STRC /*!< routine channel start flag */
|
||||
#define ADC_FLAG_ROVF ADC_STAT_ROVF /*!< routine data register overflow */
|
||||
|
||||
/* adc_ctl0 register value */
|
||||
#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */
|
||||
|
||||
/* ADC special function definitions */
|
||||
#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */
|
||||
#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted sequence convert automatically */
|
||||
#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */
|
||||
|
||||
/* temperature sensor channel, internal reference voltage channel, VBAT channel */
|
||||
#define ADC_VBAT_CHANNEL_SWITCH ADC_SYNCCTL_VBATEN /*!< VBAT channel */
|
||||
#define ADC_TEMP_VREF_CHANNEL_SWITCH ADC_SYNCCTL_TSVREN /*!< Vref and Vtemp channel */
|
||||
|
||||
/* ADC synchronization mode */
|
||||
#define SYNCCTL_SYNCM(regval) (BITS(0,4) & ((uint32_t)(regval))) /*!< write value to ADC_CTL0_SYNCM bit field */
|
||||
#define ADC_SYNC_MODE_INDEPENDENT SYNCCTL_SYNCM(0) /*!< ADC synchronization mode disabled.All the ADCs work independently */
|
||||
#define ADC_DAUL_ROUTINE_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(1) /*!< ADC0 and ADC1 work in combined routine parallel & inserted parallel mode. ADC2 works independently */
|
||||
#define ADC_DAUL_ROUTINE_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(2) /*!< ADC0 and ADC1 work in combined routine parallel & trigger rotation mode. ADC2 works independently */
|
||||
#define ADC_DAUL_INSERTED_PARALLEL SYNCCTL_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode. ADC2 works independently */
|
||||
#define ADC_DAUL_ROUTINE_PARALLEL SYNCCTL_SYNCM(6) /*!< ADC0 and ADC1 work in routine parallel mode. ADC2 works independently */
|
||||
#define ADC_DAUL_ROUTINE_FOLLOW_UP SYNCCTL_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up mode. ADC2 works independently */
|
||||
#define ADC_DAUL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode. ADC2 works independently */
|
||||
#define ADC_ALL_ROUTINE_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(17) /*!< all ADCs work in combined routine parallel & inserted parallel mode */
|
||||
#define ADC_ALL_ROUTINE_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(18) /*!< all ADCs work in combined routine parallel & trigger rotation mode */
|
||||
#define ADC_ALL_INSERTED_PARALLEL SYNCCTL_SYNCM(21) /*!< all ADCs work in inserted parallel mode */
|
||||
#define ADC_ALL_ROUTINE_PARALLEL SYNCCTL_SYNCM(22) /*!< all ADCs work in routine parallel mode */
|
||||
#define ADC_ALL_ROUTINE_FOLLOW_UP SYNCCTL_SYNCM(23) /*!< all ADCs work in follow-up mode */
|
||||
#define ADC_ALL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(25) /*!< all ADCs work in trigger rotation mode */
|
||||
|
||||
/* ADC data alignment */
|
||||
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */
|
||||
#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */
|
||||
|
||||
/* external trigger mode for routine and inserted channel */
|
||||
#define EXTERNAL_TRIGGER_DISABLE ((uint32_t)0x00000000U) /*!< external trigger disable */
|
||||
#define EXTERNAL_TRIGGER_RISING ((uint32_t)0x00000001U) /*!< rising edge of external trigger */
|
||||
#define EXTERNAL_TRIGGER_FALLING ((uint32_t)0x00000002U) /*!< falling edge of external trigger */
|
||||
#define EXTERNAL_TRIGGER_RISING_FALLING ((uint32_t)0x00000003U) /*!< rising and falling edge of external trigger */
|
||||
|
||||
/* ADC external trigger select for routine channel */
|
||||
#define CTL1_ETSRC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24))
|
||||
#define ADC_EXTTRIG_ROUTINE_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */
|
||||
#define ADC_EXTTRIG_ROUTINE_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */
|
||||
#define ADC_EXTTRIG_ROUTINE_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */
|
||||
#define ADC_EXTTRIG_ROUTINE_T1_CH1 CTL1_ETSRC(3) /*!< timer 1 CC1 event select */
|
||||
#define ADC_EXTTRIG_ROUTINE_T1_CH2 CTL1_ETSRC(4) /*!< timer 1 CC2 event select */
|
||||
#define ADC_EXTTRIG_ROUTINE_T1_CH3 CTL1_ETSRC(5) /*!< timer 1 CC3 event select */
|
||||
#define ADC_EXTTRIG_ROUTINE_T1_TRGO CTL1_ETSRC(6) /*!< timer 1 TRGO event select */
|
||||
#define ADC_EXTTRIG_ROUTINE_T2_CH0 CTL1_ETSRC(7) /*!< timer 2 CC0 event select */
|
||||
#define ADC_EXTTRIG_ROUTINE_T2_TRGO CTL1_ETSRC(8) /*!< timer 2 TRGO event select */
|
||||
#define ADC_EXTTRIG_ROUTINE_T3_CH3 CTL1_ETSRC(9) /*!< timer 3 CC3 event select */
|
||||
#define ADC_EXTTRIG_ROUTINE_T4_CH0 CTL1_ETSRC(10) /*!< timer 4 CC0 event select */
|
||||
#define ADC_EXTTRIG_ROUTINE_T4_CH1 CTL1_ETSRC(11) /*!< timer 4 CC1 event select */
|
||||
#define ADC_EXTTRIG_ROUTINE_T4_CH2 CTL1_ETSRC(12) /*!< timer 4 CC2 event select */
|
||||
#define ADC_EXTTRIG_ROUTINE_T7_CH0 CTL1_ETSRC(13) /*!< timer 7 CC0 event select */
|
||||
#define ADC_EXTTRIG_ROUTINE_T7_TRGO CTL1_ETSRC(14) /*!< timer 7 TRGO event select */
|
||||
#define ADC_EXTTRIG_ROUTINE_EXTI_11 CTL1_ETSRC(15) /*!< extiline 11 select */
|
||||
|
||||
/* ADC external trigger select for inserted channel */
|
||||
#define CTL1_ETSIC(regval) (BITS(16,19) & ((uint32_t)(regval) << 16))
|
||||
#define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(0) /*!< timer0 capture compare 3 */
|
||||
#define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(1) /*!< timer0 TRGO event */
|
||||
#define ADC_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(2) /*!< timer1 capture compare 0 */
|
||||
#define ADC_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(3) /*!< timer1 TRGO event */
|
||||
#define ADC_EXTTRIG_INSERTED_T2_CH1 CTL1_ETSIC(4) /*!< timer2 capture compare 1 */
|
||||
#define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(5) /*!< timer2 capture compare 3 */
|
||||
#define ADC_EXTTRIG_INSERTED_T3_CH0 CTL1_ETSIC(6) /*!< timer3 capture compare 0 */
|
||||
#define ADC_EXTTRIG_INSERTED_T3_CH1 CTL1_ETSIC(7) /*!< timer3 capture compare 1 */
|
||||
#define ADC_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(8) /*!< timer3 capture compare 2 */
|
||||
#define ADC_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(9) /*!< timer3 capture compare TRGO */
|
||||
#define ADC_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(10) /*!< timer4 capture compare 3 */
|
||||
#define ADC_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(11) /*!< timer4 capture compare TRGO */
|
||||
#define ADC_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(12) /*!< timer7 capture compare 1 */
|
||||
#define ADC_EXTTRIG_INSERTED_T7_CH2 CTL1_ETSIC(13) /*!< timer7 capture compare 2 */
|
||||
#define ADC_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(14) /*!< timer7 capture compare 3 */
|
||||
#define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(15) /*!< external interrupt line 15 */
|
||||
|
||||
/* ADC channel sample time */
|
||||
#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */
|
||||
#define ADC_SAMPLETIME_3 SAMPTX_SPT(0) /*!< 3 sampling cycles */
|
||||
#define ADC_SAMPLETIME_15 SAMPTX_SPT(1) /*!< 15 sampling cycles */
|
||||
#define ADC_SAMPLETIME_28 SAMPTX_SPT(2) /*!< 28 sampling cycles */
|
||||
#define ADC_SAMPLETIME_56 SAMPTX_SPT(3) /*!< 56 sampling cycles */
|
||||
#define ADC_SAMPLETIME_84 SAMPTX_SPT(4) /*!< 84 sampling cycles */
|
||||
#define ADC_SAMPLETIME_112 SAMPTX_SPT(5) /*!< 112 sampling cycles */
|
||||
#define ADC_SAMPLETIME_144 SAMPTX_SPT(6) /*!< 144 sampling cycles */
|
||||
#define ADC_SAMPLETIME_480 SAMPTX_SPT(7) /*!< 480 sampling cycles */
|
||||
|
||||
/* adc_ioffx register value */
|
||||
#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */
|
||||
|
||||
/* adc_wdht register value */
|
||||
#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */
|
||||
|
||||
/* adc_wdlt register value */
|
||||
#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */
|
||||
|
||||
/* adc_rsqx register value */
|
||||
#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */
|
||||
|
||||
/* adc_isq register value */
|
||||
#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */
|
||||
|
||||
/* adc_ovsampctl register value */
|
||||
/* ADC resolution */
|
||||
#define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) /*!< write value to ADC_CTL0_DRES bit field */
|
||||
#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */
|
||||
#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */
|
||||
#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */
|
||||
#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */
|
||||
|
||||
/* oversampling shift */
|
||||
#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */
|
||||
#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */
|
||||
|
||||
/* oversampling ratio */
|
||||
#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */
|
||||
|
||||
/* triggered oversampling */
|
||||
#define ADC_OVERSAMPLING_ALL_CONVERT ((uint32_t)0x00000000U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */
|
||||
#define ADC_OVERSAMPLING_ONE_CONVERT ADC_OVSAMPCTL_TOVS /*!< each oversampled conversion for a channel needs a trigger */
|
||||
|
||||
/* ADC channel sequence definitions */
|
||||
#define ADC_ROUTINE_CHANNEL ((uint8_t)0x01U) /*!< adc routine sequence */
|
||||
#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted sequence */
|
||||
#define ADC_ROUTINE_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both routine and inserted sequence */
|
||||
#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of routine & inserted sequence */
|
||||
|
||||
/* ADC inserted channel definitions */
|
||||
#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */
|
||||
#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */
|
||||
#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */
|
||||
#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */
|
||||
|
||||
/* ADC channel definitions */
|
||||
#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */
|
||||
#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */
|
||||
#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */
|
||||
#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */
|
||||
#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */
|
||||
#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */
|
||||
#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */
|
||||
#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */
|
||||
#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */
|
||||
#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */
|
||||
#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */
|
||||
#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */
|
||||
#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */
|
||||
#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */
|
||||
#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */
|
||||
#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */
|
||||
#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */
|
||||
#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */
|
||||
#define ADC_CHANNEL_18 ((uint8_t)0x12U) /*!< ADC channel 18 */
|
||||
|
||||
/* ADC interrupt flag */
|
||||
#define ADC_INT_WDE ADC_CTL0_WDEIE /*!< analog watchdog event interrupt */
|
||||
#define ADC_INT_EOC ADC_CTL0_EOCIE /*!< end of sequence conversion interrupt */
|
||||
#define ADC_INT_EOIC ADC_CTL0_EOICIE /*!< end of inserted sequence conversion interrupt */
|
||||
#define ADC_INT_ROVF ADC_CTL0_ROVFIE /*!< routine data register overflow */
|
||||
|
||||
/* ADC interrupt flag */
|
||||
#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */
|
||||
#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of sequence conversion interrupt */
|
||||
#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted sequence conversion interrupt */
|
||||
#define ADC_INT_FLAG_ROVF ADC_STAT_ROVF /*!< routine data register overflow */
|
||||
|
||||
/* configure the ADC clock for all the ADCs */
|
||||
#define SYNCCTL_ADCCK(regval) (BITS(16,18) & ((uint32_t)(regval) << 16))
|
||||
#define ADC_ADCCK_PCLK2_DIV2 SYNCCTL_ADCCK(0) /*!< PCLK2 div2 */
|
||||
#define ADC_ADCCK_PCLK2_DIV4 SYNCCTL_ADCCK(1) /*!< PCLK2 div4 */
|
||||
#define ADC_ADCCK_PCLK2_DIV6 SYNCCTL_ADCCK(2) /*!< PCLK2 div6 */
|
||||
#define ADC_ADCCK_PCLK2_DIV8 SYNCCTL_ADCCK(3) /*!< PCLK2 div8 */
|
||||
#define ADC_ADCCK_HCLK_DIV5 SYNCCTL_ADCCK(4) /*!< HCLK div5 */
|
||||
#define ADC_ADCCK_HCLK_DIV6 SYNCCTL_ADCCK(5) /*!< HCLK div6 */
|
||||
#define ADC_ADCCK_HCLK_DIV10 SYNCCTL_ADCCK(6) /*!< HCLK div10 */
|
||||
#define ADC_ADCCK_HCLK_DIV20 SYNCCTL_ADCCK(7) /*!< HCLK div20 */
|
||||
|
||||
/* ADC synchronization delay */
|
||||
#define ADC_SYNC_DELAY_5CYCLE ((uint32_t)0x00000000U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 5 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_6CYCLE ((uint32_t)0x00000100U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 6 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_7CYCLE ((uint32_t)0x00000200U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 7 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_8CYCLE ((uint32_t)0x00000300U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 8 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_9CYCLE ((uint32_t)0x00000400U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 9 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_10CYCLE ((uint32_t)0x00000500U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 10 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_11CYCLE ((uint32_t)0x00000600U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 11 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_12CYCLE ((uint32_t)0x00000700U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 12 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_13CYCLE ((uint32_t)0x00000800U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 13 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_14CYCLE ((uint32_t)0x00000900U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 14 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_15CYCLE ((uint32_t)0x00000A00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 15 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_16CYCLE ((uint32_t)0x00000B00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 16 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_17CYCLE ((uint32_t)0x00000C00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 17 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_18CYCLE ((uint32_t)0x00000D00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 18 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_19CYCLE ((uint32_t)0x00000E00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 19 ADC clock cycles. */
|
||||
#define ADC_SYNC_DELAY_20CYCLE ((uint32_t)0x00000F00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 20 ADC clock cycles. */
|
||||
|
||||
/* ADC synchronization DMA mode selection */
|
||||
#define ADC_SYNC_DMA_DISABLE ((uint32_t)0x00000000U) /*!< ADC synchronization DMA disabled */
|
||||
#define ADC_SYNC_DMA_MODE0 ((uint32_t)0x00004000U) /*!< ADC synchronization DMA mode 0 */
|
||||
#define ADC_SYNC_DMA_MODE1 ((uint32_t)0x00008000U) /*!< ADC synchronization DMA mode 1 */
|
||||
|
||||
/* end of conversion mode */
|
||||
#define ADC_EOC_SET_SEQUENCE ((uint8_t)0x00U) /*!< only at the end of a sequence of routine conversions, the EOC bit is set */
|
||||
#define ADC_EOC_SET_CONVERSION ((uint8_t)0x01U) /*!< at the end of each routine conversion, the EOC bit is set */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization config */
|
||||
/* reset ADC */
|
||||
void adc_deinit(void);
|
||||
/* configure the ADC clock for all the ADCs */
|
||||
void adc_clock_config(uint32_t prescaler);
|
||||
/* enable or disable ADC special function */
|
||||
void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue);
|
||||
/* configure ADC data alignment */
|
||||
void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment);
|
||||
/* enable ADC interface */
|
||||
void adc_enable(uint32_t adc_periph);
|
||||
/* disable ADC interface */
|
||||
void adc_disable(uint32_t adc_periph);
|
||||
/* ADC calibration and reset calibration */
|
||||
void adc_calibration_enable(uint32_t adc_periph);
|
||||
/* configure temperature sensor and internal reference voltage channel or VBAT channel function */
|
||||
void adc_channel_16_to_18(uint32_t function, ControlStatus newvalue);
|
||||
/* configure ADC resolution */
|
||||
void adc_resolution_config(uint32_t adc_periph, uint32_t resolution);
|
||||
/* configure ADC oversample mode */
|
||||
void adc_oversample_mode_config(uint32_t adc_periph, uint32_t mode, uint16_t shift, uint8_t ratio);
|
||||
/* enable ADC oversample mode */
|
||||
void adc_oversample_mode_enable(uint32_t adc_periph);
|
||||
/* disable ADC oversample mode */
|
||||
void adc_oversample_mode_disable(uint32_t adc_periph);
|
||||
|
||||
/* DMA config */
|
||||
/* enable DMA request */
|
||||
void adc_dma_mode_enable(uint32_t adc_periph);
|
||||
/* disable DMA request */
|
||||
void adc_dma_mode_disable(uint32_t adc_periph);
|
||||
/* when DMA=1, the DMA engine issues a request at end of each routine conversion */
|
||||
void adc_dma_request_after_last_enable(uint32_t adc_periph);
|
||||
/* the DMA engine is disabled after the end of transfer signal from DMA controller is detected */
|
||||
void adc_dma_request_after_last_disable(uint32_t adc_periph);
|
||||
|
||||
/* routine sequence and inserted sequence config */
|
||||
/* configure ADC discontinuous mode */
|
||||
void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_sequence , uint8_t length);
|
||||
/* configure the length of routine sequence or inserted sequence */
|
||||
void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_sequence , uint32_t length);
|
||||
/* configure ADC routine channel */
|
||||
void adc_routine_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time);
|
||||
/* configure ADC inserted channel */
|
||||
void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time);
|
||||
/* configure ADC inserted channel offset */
|
||||
void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset);
|
||||
/* configure ADC external trigger source */
|
||||
void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_sequence , uint32_t external_trigger_source);
|
||||
/* enable ADC external trigger */
|
||||
void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_sequence , uint32_t trigger_mode);
|
||||
/* enable ADC software trigger */
|
||||
void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_sequence);
|
||||
/* configure end of conversion mode */
|
||||
void adc_end_of_conversion_config(uint32_t adc_periph , uint8_t end_selection);
|
||||
|
||||
/* get channel data */
|
||||
/* read ADC routine data register */
|
||||
uint16_t adc_routine_data_read(uint32_t adc_periph);
|
||||
/* read ADC inserted data register */
|
||||
uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel);
|
||||
|
||||
/* watchdog config */
|
||||
/* disable ADC analog watchdog single channel */
|
||||
void adc_watchdog_single_channel_disable(uint32_t adc_periph );
|
||||
/* enable ADC analog watchdog single channel */
|
||||
void adc_watchdog_single_channel_enable(uint32_t adc_periph , uint8_t adc_channel);
|
||||
/* configure ADC analog watchdog sequence */
|
||||
void adc_watchdog_sequence_channel_enable(uint32_t adc_periph , uint8_t adc_sequence);
|
||||
/* disable ADC analog watchdog */
|
||||
void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_sequence);
|
||||
/* configure ADC analog watchdog threshold */
|
||||
void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* get the ADC flag bits */
|
||||
FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag);
|
||||
/* clear the ADC flag bits */
|
||||
void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag);
|
||||
/* get the bit state of ADCx software start conversion */
|
||||
FlagStatus adc_routine_software_startconv_flag_get(uint32_t adc_periph);
|
||||
/* get the bit state of ADCx software inserted channel start conversion */
|
||||
FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph);
|
||||
/* get the ADC interrupt bits */
|
||||
FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt);
|
||||
/* clear the ADC flag */
|
||||
void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt);
|
||||
/* enable ADC interrupt */
|
||||
void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt);
|
||||
/* disable ADC interrupt */
|
||||
void adc_interrupt_disable(uint32_t adc_periph , uint32_t adc_interrupt);
|
||||
|
||||
/* ADC synchronization */
|
||||
/* configure the ADC sync mode */
|
||||
void adc_sync_mode_config(uint32_t sync_mode);
|
||||
/* configure the delay between 2 sampling phases in ADC sync modes */
|
||||
void adc_sync_delay_config(uint32_t sample_delay);
|
||||
/* configure ADC sync DMA mode selection */
|
||||
void adc_sync_dma_config(uint32_t dma_mode );
|
||||
/* configure ADC sync DMA engine is disabled after the end of transfer signal from DMA controller is detected */
|
||||
void adc_sync_dma_request_after_last_enable(void);
|
||||
/* configure ADC sync DMA engine issues requests according to the SYNCDMA bits */
|
||||
void adc_sync_dma_request_after_last_disable(void);
|
||||
/* read ADC sync routine data register */
|
||||
uint32_t adc_sync_routine_data_read(void);
|
||||
|
||||
#endif /* GD32F4XX_ADC_H */
|
||||
|
|
@ -0,0 +1,750 @@
|
|||
/*!
|
||||
\file gd32f4xx_can.h
|
||||
\brief definitions for the CAN
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2019-11-27, V2.0.1, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef GD32F4XX_CAN_H
|
||||
#define GD32F4XX_CAN_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* CAN definitions */
|
||||
#define CAN0 CAN_BASE /*!< CAN0 base address */
|
||||
#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define CAN_CTL(canx) REG32((canx) + 0x00000000U) /*!< CAN control register */
|
||||
#define CAN_STAT(canx) REG32((canx) + 0x00000004U) /*!< CAN status register */
|
||||
#define CAN_TSTAT(canx) REG32((canx) + 0x00000008U) /*!< CAN transmit status register*/
|
||||
#define CAN_RFIFO0(canx) REG32((canx) + 0x0000000CU) /*!< CAN receive FIFO0 register */
|
||||
#define CAN_RFIFO1(canx) REG32((canx) + 0x00000010U) /*!< CAN receive FIFO1 register */
|
||||
#define CAN_INTEN(canx) REG32((canx) + 0x00000014U) /*!< CAN interrupt enable register */
|
||||
#define CAN_ERR(canx) REG32((canx) + 0x00000018U) /*!< CAN error register */
|
||||
#define CAN_BT(canx) REG32((canx) + 0x0000001CU) /*!< CAN bit timing register */
|
||||
#define CAN_TMI0(canx) REG32((canx) + 0x00000180U) /*!< CAN transmit mailbox0 identifier register */
|
||||
#define CAN_TMP0(canx) REG32((canx) + 0x00000184U) /*!< CAN transmit mailbox0 property register */
|
||||
#define CAN_TMDATA00(canx) REG32((canx) + 0x00000188U) /*!< CAN transmit mailbox0 data0 register */
|
||||
#define CAN_TMDATA10(canx) REG32((canx) + 0x0000018CU) /*!< CAN transmit mailbox0 data1 register */
|
||||
#define CAN_TMI1(canx) REG32((canx) + 0x00000190U) /*!< CAN transmit mailbox1 identifier register */
|
||||
#define CAN_TMP1(canx) REG32((canx) + 0x00000194U) /*!< CAN transmit mailbox1 property register */
|
||||
#define CAN_TMDATA01(canx) REG32((canx) + 0x00000198U) /*!< CAN transmit mailbox1 data0 register */
|
||||
#define CAN_TMDATA11(canx) REG32((canx) + 0x0000019CU) /*!< CAN transmit mailbox1 data1 register */
|
||||
#define CAN_TMI2(canx) REG32((canx) + 0x000001A0U) /*!< CAN transmit mailbox2 identifier register */
|
||||
#define CAN_TMP2(canx) REG32((canx) + 0x000001A4U) /*!< CAN transmit mailbox2 property register */
|
||||
#define CAN_TMDATA02(canx) REG32((canx) + 0x000001A8U) /*!< CAN transmit mailbox2 data0 register */
|
||||
#define CAN_TMDATA12(canx) REG32((canx) + 0x000001ACU) /*!< CAN transmit mailbox2 data1 register */
|
||||
#define CAN_RFIFOMI0(canx) REG32((canx) + 0x000001B0U) /*!< CAN receive FIFO0 mailbox identifier register */
|
||||
#define CAN_RFIFOMP0(canx) REG32((canx) + 0x000001B4U) /*!< CAN receive FIFO0 mailbox property register */
|
||||
#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x000001B8U) /*!< CAN receive FIFO0 mailbox data0 register */
|
||||
#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x000001BCU) /*!< CAN receive FIFO0 mailbox data1 register */
|
||||
#define CAN_RFIFOMI1(canx) REG32((canx) + 0x000001C0U) /*!< CAN receive FIFO1 mailbox identifier register */
|
||||
#define CAN_RFIFOMP1(canx) REG32((canx) + 0x000001C4U) /*!< CAN receive FIFO1 mailbox property register */
|
||||
#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x000001C8U) /*!< CAN receive FIFO1 mailbox data0 register */
|
||||
#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x000001CCU) /*!< CAN receive FIFO1 mailbox data1 register */
|
||||
#define CAN_FCTL(canx) REG32((canx) + 0x00000200U) /*!< CAN filter control register */
|
||||
#define CAN_FMCFG(canx) REG32((canx) + 0x00000204U) /*!< CAN filter mode register */
|
||||
#define CAN_FSCFG(canx) REG32((canx) + 0x0000020CU) /*!< CAN filter scale register */
|
||||
#define CAN_FAFIFO(canx) REG32((canx) + 0x00000214U) /*!< CAN filter associated FIFO register */
|
||||
#define CAN_FW(canx) REG32((canx) + 0x0000021CU) /*!< CAN filter working register */
|
||||
#define CAN_F0DATA0(canx) REG32((canx) + 0x00000240U) /*!< CAN filter 0 data 0 register */
|
||||
#define CAN_F1DATA0(canx) REG32((canx) + 0x00000248U) /*!< CAN filter 1 data 0 register */
|
||||
#define CAN_F2DATA0(canx) REG32((canx) + 0x00000250U) /*!< CAN filter 2 data 0 register */
|
||||
#define CAN_F3DATA0(canx) REG32((canx) + 0x00000258U) /*!< CAN filter 3 data 0 register */
|
||||
#define CAN_F4DATA0(canx) REG32((canx) + 0x00000260U) /*!< CAN filter 4 data 0 register */
|
||||
#define CAN_F5DATA0(canx) REG32((canx) + 0x00000268U) /*!< CAN filter 5 data 0 register */
|
||||
#define CAN_F6DATA0(canx) REG32((canx) + 0x00000270U) /*!< CAN filter 6 data 0 register */
|
||||
#define CAN_F7DATA0(canx) REG32((canx) + 0x00000278U) /*!< CAN filter 7 data 0 register */
|
||||
#define CAN_F8DATA0(canx) REG32((canx) + 0x00000280U) /*!< CAN filter 8 data 0 register */
|
||||
#define CAN_F9DATA0(canx) REG32((canx) + 0x00000288U) /*!< CAN filter 9 data 0 register */
|
||||
#define CAN_F10DATA0(canx) REG32((canx) + 0x00000290U) /*!< CAN filter 10 data 0 register */
|
||||
#define CAN_F11DATA0(canx) REG32((canx) + 0x00000298U) /*!< CAN filter 11 data 0 register */
|
||||
#define CAN_F12DATA0(canx) REG32((canx) + 0x000002A0U) /*!< CAN filter 12 data 0 register */
|
||||
#define CAN_F13DATA0(canx) REG32((canx) + 0x000002A8U) /*!< CAN filter 13 data 0 register */
|
||||
#define CAN_F14DATA0(canx) REG32((canx) + 0x000002B0U) /*!< CAN filter 14 data 0 register */
|
||||
#define CAN_F15DATA0(canx) REG32((canx) + 0x000002B8U) /*!< CAN filter 15 data 0 register */
|
||||
#define CAN_F16DATA0(canx) REG32((canx) + 0x000002C0U) /*!< CAN filter 16 data 0 register */
|
||||
#define CAN_F17DATA0(canx) REG32((canx) + 0x000002C8U) /*!< CAN filter 17 data 0 register */
|
||||
#define CAN_F18DATA0(canx) REG32((canx) + 0x000002D0U) /*!< CAN filter 18 data 0 register */
|
||||
#define CAN_F19DATA0(canx) REG32((canx) + 0x000002D8U) /*!< CAN filter 19 data 0 register */
|
||||
#define CAN_F20DATA0(canx) REG32((canx) + 0x000002E0U) /*!< CAN filter 20 data 0 register */
|
||||
#define CAN_F21DATA0(canx) REG32((canx) + 0x000002E8U) /*!< CAN filter 21 data 0 register */
|
||||
#define CAN_F22DATA0(canx) REG32((canx) + 0x000002F0U) /*!< CAN filter 22 data 0 register */
|
||||
#define CAN_F23DATA0(canx) REG32((canx) + 0x000003F8U) /*!< CAN filter 23 data 0 register */
|
||||
#define CAN_F24DATA0(canx) REG32((canx) + 0x00000300U) /*!< CAN filter 24 data 0 register */
|
||||
#define CAN_F25DATA0(canx) REG32((canx) + 0x00000308U) /*!< CAN filter 25 data 0 register */
|
||||
#define CAN_F26DATA0(canx) REG32((canx) + 0x00000310U) /*!< CAN filter 26 data 0 register */
|
||||
#define CAN_F27DATA0(canx) REG32((canx) + 0x00000318U) /*!< CAN filter 27 data 0 register */
|
||||
#define CAN_F0DATA1(canx) REG32((canx) + 0x00000244U) /*!< CAN filter 0 data 1 register */
|
||||
#define CAN_F1DATA1(canx) REG32((canx) + 0x0000024CU) /*!< CAN filter 1 data 1 register */
|
||||
#define CAN_F2DATA1(canx) REG32((canx) + 0x00000254U) /*!< CAN filter 2 data 1 register */
|
||||
#define CAN_F3DATA1(canx) REG32((canx) + 0x0000025CU) /*!< CAN filter 3 data 1 register */
|
||||
#define CAN_F4DATA1(canx) REG32((canx) + 0x00000264U) /*!< CAN filter 4 data 1 register */
|
||||
#define CAN_F5DATA1(canx) REG32((canx) + 0x0000026CU) /*!< CAN filter 5 data 1 register */
|
||||
#define CAN_F6DATA1(canx) REG32((canx) + 0x00000274U) /*!< CAN filter 6 data 1 register */
|
||||
#define CAN_F7DATA1(canx) REG32((canx) + 0x0000027CU) /*!< CAN filter 7 data 1 register */
|
||||
#define CAN_F8DATA1(canx) REG32((canx) + 0x00000284U) /*!< CAN filter 8 data 1 register */
|
||||
#define CAN_F9DATA1(canx) REG32((canx) + 0x0000028CU) /*!< CAN filter 9 data 1 register */
|
||||
#define CAN_F10DATA1(canx) REG32((canx) + 0x00000294U) /*!< CAN filter 10 data 1 register */
|
||||
#define CAN_F11DATA1(canx) REG32((canx) + 0x0000029CU) /*!< CAN filter 11 data 1 register */
|
||||
#define CAN_F12DATA1(canx) REG32((canx) + 0x000002A4U) /*!< CAN filter 12 data 1 register */
|
||||
#define CAN_F13DATA1(canx) REG32((canx) + 0x000002ACU) /*!< CAN filter 13 data 1 register */
|
||||
#define CAN_F14DATA1(canx) REG32((canx) + 0x000002B4U) /*!< CAN filter 14 data 1 register */
|
||||
#define CAN_F15DATA1(canx) REG32((canx) + 0x000002BCU) /*!< CAN filter 15 data 1 register */
|
||||
#define CAN_F16DATA1(canx) REG32((canx) + 0x000002C4U) /*!< CAN filter 16 data 1 register */
|
||||
#define CAN_F17DATA1(canx) REG32((canx) + 0x0000024CU) /*!< CAN filter 17 data 1 register */
|
||||
#define CAN_F18DATA1(canx) REG32((canx) + 0x000002D4U) /*!< CAN filter 18 data 1 register */
|
||||
#define CAN_F19DATA1(canx) REG32((canx) + 0x000002DCU) /*!< CAN filter 19 data 1 register */
|
||||
#define CAN_F20DATA1(canx) REG32((canx) + 0x000002E4U) /*!< CAN filter 20 data 1 register */
|
||||
#define CAN_F21DATA1(canx) REG32((canx) + 0x000002ECU) /*!< CAN filter 21 data 1 register */
|
||||
#define CAN_F22DATA1(canx) REG32((canx) + 0x000002F4U) /*!< CAN filter 22 data 1 register */
|
||||
#define CAN_F23DATA1(canx) REG32((canx) + 0x000002FCU) /*!< CAN filter 23 data 1 register */
|
||||
#define CAN_F24DATA1(canx) REG32((canx) + 0x00000304U) /*!< CAN filter 24 data 1 register */
|
||||
#define CAN_F25DATA1(canx) REG32((canx) + 0x0000030CU) /*!< CAN filter 25 data 1 register */
|
||||
#define CAN_F26DATA1(canx) REG32((canx) + 0x00000314U) /*!< CAN filter 26 data 1 register */
|
||||
#define CAN_F27DATA1(canx) REG32((canx) + 0x0000031CU) /*!< CAN filter 27 data 1 register */
|
||||
|
||||
/* CAN transmit mailbox bank */
|
||||
#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */
|
||||
#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */
|
||||
#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */
|
||||
#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */
|
||||
|
||||
/* CAN filter bank */
|
||||
#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */
|
||||
#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */
|
||||
|
||||
/* CAN receive FIFO mailbox bank */
|
||||
#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */
|
||||
#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */
|
||||
#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */
|
||||
#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */
|
||||
|
||||
/* bits definitions */
|
||||
/* CAN_CTL */
|
||||
#define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */
|
||||
#define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */
|
||||
#define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */
|
||||
#define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */
|
||||
#define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */
|
||||
#define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */
|
||||
#define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */
|
||||
#define CAN_CTL_TTC BIT(7) /*!< time triggered communication */
|
||||
#define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */
|
||||
#define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */
|
||||
|
||||
/* CAN_STAT */
|
||||
#define CAN_STAT_IWS BIT(0) /*!< initial working state */
|
||||
#define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */
|
||||
#define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/
|
||||
#define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */
|
||||
#define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */
|
||||
#define CAN_STAT_TS BIT(8) /*!< transmitting state */
|
||||
#define CAN_STAT_RS BIT(9) /*!< receiving state */
|
||||
#define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */
|
||||
#define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */
|
||||
|
||||
/* CAN_TSTAT */
|
||||
#define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */
|
||||
#define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */
|
||||
#define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */
|
||||
#define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */
|
||||
#define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */
|
||||
#define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */
|
||||
#define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */
|
||||
#define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */
|
||||
#define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */
|
||||
#define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */
|
||||
#define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */
|
||||
#define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */
|
||||
#define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */
|
||||
#define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */
|
||||
#define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */
|
||||
#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */
|
||||
#define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */
|
||||
#define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */
|
||||
#define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */
|
||||
#define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */
|
||||
#define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */
|
||||
#define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */
|
||||
|
||||
/* CAN_RFIFO0 */
|
||||
#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */
|
||||
#define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */
|
||||
#define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */
|
||||
#define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */
|
||||
|
||||
/* CAN_RFIFO1 */
|
||||
#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */
|
||||
#define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */
|
||||
#define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */
|
||||
#define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */
|
||||
|
||||
/* CAN_INTEN */
|
||||
#define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */
|
||||
#define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */
|
||||
#define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */
|
||||
#define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */
|
||||
#define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */
|
||||
#define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */
|
||||
#define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */
|
||||
#define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */
|
||||
#define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */
|
||||
#define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */
|
||||
#define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */
|
||||
#define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */
|
||||
#define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */
|
||||
#define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */
|
||||
|
||||
/* CAN_ERR */
|
||||
#define CAN_ERR_WERR BIT(0) /*!< warning error */
|
||||
#define CAN_ERR_PERR BIT(1) /*!< passive error */
|
||||
#define CAN_ERR_BOERR BIT(2) /*!< bus-off error */
|
||||
#define CAN_ERR_ERRN BITS(4,6) /*!< error number */
|
||||
#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */
|
||||
#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */
|
||||
|
||||
/* CAN_BT */
|
||||
#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */
|
||||
#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */
|
||||
#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */
|
||||
#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */
|
||||
#define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */
|
||||
#define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */
|
||||
|
||||
/* CAN_TMIx */
|
||||
#define CAN_TMI_TEN BIT(0) /*!< transmit enable */
|
||||
#define CAN_TMI_FT BIT(1) /*!< frame type */
|
||||
#define CAN_TMI_FF BIT(2) /*!< frame format */
|
||||
#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */
|
||||
#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */
|
||||
|
||||
/* CAN_TMPx */
|
||||
#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */
|
||||
#define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */
|
||||
#define CAN_TMP_TS BITS(16,31) /*!< time stamp */
|
||||
|
||||
/* CAN_TMDATA0x */
|
||||
#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */
|
||||
#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */
|
||||
#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */
|
||||
#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */
|
||||
|
||||
/* CAN_TMDATA1x */
|
||||
#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */
|
||||
#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */
|
||||
#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */
|
||||
#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */
|
||||
|
||||
/* CAN_RFIFOMIx */
|
||||
#define CAN_RFIFOMI_FT BIT(1) /*!< frame type */
|
||||
#define CAN_RFIFOMI_FF BIT(2) /*!< frame format */
|
||||
#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */
|
||||
#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */
|
||||
|
||||
/* CAN_RFIFOMPx */
|
||||
#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */
|
||||
#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */
|
||||
#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */
|
||||
|
||||
/* CAN_RFIFOMDATA0x */
|
||||
#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */
|
||||
#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */
|
||||
#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */
|
||||
#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */
|
||||
|
||||
/* CAN_RFIFOMDATA1x */
|
||||
#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */
|
||||
#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */
|
||||
#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */
|
||||
#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */
|
||||
|
||||
/* CAN_FCTL */
|
||||
#define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */
|
||||
#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */
|
||||
|
||||
/* CAN_FMCFG */
|
||||
#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask */
|
||||
|
||||
/* CAN_FSCFG */
|
||||
#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits */
|
||||
|
||||
/* CAN_FAFIFO */
|
||||
#define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */
|
||||
|
||||
/* CAN_FW */
|
||||
#define CAN_FW_FW(regval) BIT(regval) /*!< filter working */
|
||||
|
||||
/* CAN_FxDATAy */
|
||||
#define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */
|
||||
|
||||
/* constants definitions */
|
||||
/* define the CAN bit position and its register index offset */
|
||||
#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
||||
#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6)))
|
||||
#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
|
||||
|
||||
#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))
|
||||
#define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12)))
|
||||
#define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU)
|
||||
#define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU)
|
||||
|
||||
/* register offset */
|
||||
#define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */
|
||||
#define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */
|
||||
#define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */
|
||||
#define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */
|
||||
#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */
|
||||
|
||||
/* CAN flags */
|
||||
typedef enum {
|
||||
/* flags in STAT register */
|
||||
CAN_FLAG_RXL = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< RX level */
|
||||
CAN_FLAG_LASTRX = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< last sample value of RX pin */
|
||||
CAN_FLAG_RS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 9U), /*!< receiving state */
|
||||
CAN_FLAG_TS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 8U), /*!< transmitting state */
|
||||
CAN_FLAG_SLPIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< status change flag of entering sleep working mode */
|
||||
CAN_FLAG_WUIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< status change flag of wakeup from sleep working mode */
|
||||
CAN_FLAG_ERRIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< error flag */
|
||||
CAN_FLAG_SLPWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< sleep working state */
|
||||
CAN_FLAG_IWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< initial working state */
|
||||
/* flags in TSTAT register */
|
||||
CAN_FLAG_TMLS2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 31U), /*!< transmit mailbox 2 last sending in TX FIFO */
|
||||
CAN_FLAG_TMLS1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 30U), /*!< transmit mailbox 1 last sending in TX FIFO */
|
||||
CAN_FLAG_TMLS0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 29U), /*!< transmit mailbox 0 last sending in TX FIFO */
|
||||
CAN_FLAG_TME2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 28U), /*!< transmit mailbox 2 empty */
|
||||
CAN_FLAG_TME1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 27U), /*!< transmit mailbox 1 empty */
|
||||
CAN_FLAG_TME0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 26U), /*!< transmit mailbox 0 empty */
|
||||
CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */
|
||||
CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */
|
||||
CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */
|
||||
CAN_FLAG_MAL2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 18U), /*!< mailbox 2 arbitration lost */
|
||||
CAN_FLAG_MAL1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 10U), /*!< mailbox 1 arbitration lost */
|
||||
CAN_FLAG_MAL0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 2U), /*!< mailbox 0 arbitration lost */
|
||||
CAN_FLAG_MTFNERR2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 17U), /*!< mailbox 2 transmit finished with no error */
|
||||
CAN_FLAG_MTFNERR1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 9U), /*!< mailbox 1 transmit finished with no error */
|
||||
CAN_FLAG_MTFNERR0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 1U), /*!< mailbox 0 transmit finished with no error */
|
||||
CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */
|
||||
CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */
|
||||
CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */
|
||||
/* flags in RFIFO0 register */
|
||||
CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */
|
||||
CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */
|
||||
/* flags in RFIFO1 register */
|
||||
CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */
|
||||
CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */
|
||||
/* flags in ERR register */
|
||||
CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */
|
||||
CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */
|
||||
CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */
|
||||
} can_flag_enum;
|
||||
|
||||
/* CAN interrupt flags */
|
||||
typedef enum {
|
||||
/* interrupt flags in STAT register */
|
||||
CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */
|
||||
CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */
|
||||
CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */
|
||||
/* interrupt flags in TSTAT register */
|
||||
CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */
|
||||
CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */
|
||||
CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */
|
||||
/* interrupt flags in RFIFO0 register */
|
||||
CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */
|
||||
CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */
|
||||
CAN_INT_FLAG_RFL0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 2U, 1U), /*!< receive FIFO0 not empty interrupt flag */
|
||||
/* interrupt flags in RFIFO0 register */
|
||||
CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */
|
||||
CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */
|
||||
CAN_INT_FLAG_RFL1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 2U, 4U), /*!< receive FIFO1 not empty interrupt flag */
|
||||
/* interrupt flags in ERR register */
|
||||
CAN_INT_FLAG_ERRN = CAN_REGIDX_BITS(ERR_REG_OFFSET, 3U, 11U), /*!< error number interrupt flag */
|
||||
CAN_INT_FLAG_BOERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 2U, 10U), /*!< bus-off error interrupt flag */
|
||||
CAN_INT_FLAG_PERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 1U, 9U), /*!< passive error interrupt flag */
|
||||
CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */
|
||||
} can_interrupt_flag_enum;
|
||||
|
||||
/* CAN initiliaze parameters structure */
|
||||
typedef struct {
|
||||
uint8_t working_mode; /*!< CAN working mode */
|
||||
uint8_t resync_jump_width; /*!< CAN resynchronization jump width */
|
||||
uint8_t time_segment_1; /*!< time segment 1 */
|
||||
uint8_t time_segment_2; /*!< time segment 2 */
|
||||
ControlStatus time_triggered; /*!< time triggered communication mode */
|
||||
ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */
|
||||
ControlStatus auto_wake_up; /*!< automatic wake-up mode */
|
||||
ControlStatus auto_retrans; /*!< automatic retransmission mode */
|
||||
ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */
|
||||
ControlStatus trans_fifo_order; /*!< transmit FIFO order */
|
||||
uint16_t prescaler; /*!< baudrate prescaler */
|
||||
} can_parameter_struct;
|
||||
|
||||
/* CAN transmit message structure */
|
||||
typedef struct {
|
||||
uint32_t tx_sfid; /*!< standard format frame identifier */
|
||||
uint32_t tx_efid; /*!< extended format frame identifier */
|
||||
uint8_t tx_ff; /*!< format of frame, standard or extended format */
|
||||
uint8_t tx_ft; /*!< type of frame, data or remote */
|
||||
uint8_t tx_dlen; /*!< data length */
|
||||
uint8_t tx_data[8]; /*!< transmit data */
|
||||
} can_trasnmit_message_struct;
|
||||
|
||||
/* CAN receive message structure */
|
||||
typedef struct {
|
||||
uint32_t rx_sfid; /*!< standard format frame identifier */
|
||||
uint32_t rx_efid; /*!< extended format frame identifier */
|
||||
uint8_t rx_ff; /*!< format of frame, standard or extended format */
|
||||
uint8_t rx_ft; /*!< type of frame, data or remote */
|
||||
uint8_t rx_dlen; /*!< data length */
|
||||
uint8_t rx_data[8]; /*!< receive data */
|
||||
uint8_t rx_fi; /*!< filtering index */
|
||||
} can_receive_message_struct;
|
||||
|
||||
/* CAN filter parameters structure */
|
||||
typedef struct {
|
||||
uint16_t filter_list_high; /*!< filter list number high bits */
|
||||
uint16_t filter_list_low; /*!< filter list number low bits */
|
||||
uint16_t filter_mask_high; /*!< filter mask number high bits */
|
||||
uint16_t filter_mask_low; /*!< filter mask number low bits */
|
||||
uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */
|
||||
uint16_t filter_number; /*!< filter number */
|
||||
uint16_t filter_mode; /*!< filter mode, list or mask */
|
||||
uint16_t filter_bits; /*!< filter scale */
|
||||
ControlStatus filter_enable; /*!< filter work or not */
|
||||
} can_filter_parameter_struct;
|
||||
|
||||
/* CAN errors */
|
||||
typedef enum {
|
||||
CAN_ERROR_NONE = 0, /*!< no error */
|
||||
CAN_ERROR_FILL, /*!< fill error */
|
||||
CAN_ERROR_FORMATE, /*!< format error */
|
||||
CAN_ERROR_ACK, /*!< ACK error */
|
||||
CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */
|
||||
CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */
|
||||
CAN_ERROR_CRC, /*!< CRC error */
|
||||
CAN_ERROR_SOFTWARECFG, /*!< software configure */
|
||||
} can_error_enum;
|
||||
|
||||
/* transmit states */
|
||||
typedef enum {
|
||||
CAN_TRANSMIT_FAILED = 0U, /*!< CAN transmitted failure */
|
||||
CAN_TRANSMIT_OK = 1U, /*!< CAN transmitted success */
|
||||
CAN_TRANSMIT_PENDING = 2U, /*!< CAN transmitted pending */
|
||||
CAN_TRANSMIT_NOMAILBOX = 4U, /*!< no empty mailbox to be used for CAN */
|
||||
} can_transmit_state_enum;
|
||||
|
||||
typedef enum {
|
||||
CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */
|
||||
CAN_FILTER_STRUCT, /* CAN filter parameters struct */
|
||||
CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */
|
||||
CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */
|
||||
} can_struct_type_enum;
|
||||
|
||||
/* CAN baudrate prescaler */
|
||||
#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* CAN bit segment 1 */
|
||||
#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16))
|
||||
|
||||
/* CAN bit segment 2 */
|
||||
#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20))
|
||||
|
||||
/* CAN resynchronization jump width */
|
||||
#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24))
|
||||
|
||||
/* CAN communication mode */
|
||||
#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30))
|
||||
|
||||
/* CAN FDATA high 16 bits */
|
||||
#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16))
|
||||
|
||||
/* CAN FDATA low 16 bits */
|
||||
#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* CAN1 filter start bank_number */
|
||||
#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8))
|
||||
|
||||
/* CAN transmit mailbox extended identifier */
|
||||
#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3))
|
||||
|
||||
/* CAN transmit mailbox standard identifier */
|
||||
#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21))
|
||||
|
||||
/* transmit data byte 0 */
|
||||
#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* transmit data byte 1 */
|
||||
#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8))
|
||||
|
||||
/* transmit data byte 2 */
|
||||
#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16))
|
||||
|
||||
/* transmit data byte 3 */
|
||||
#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24))
|
||||
|
||||
/* transmit data byte 4 */
|
||||
#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* transmit data byte 5 */
|
||||
#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8))
|
||||
|
||||
/* transmit data byte 6 */
|
||||
#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16))
|
||||
|
||||
/* transmit data byte 7 */
|
||||
#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24))
|
||||
|
||||
/* receive mailbox extended identifier */
|
||||
#define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3U, 31U)
|
||||
|
||||
/* receive mailbox standard identifier */
|
||||
#define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21U, 31U)
|
||||
|
||||
/* receive data length */
|
||||
#define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0U, 3U)
|
||||
|
||||
/* the index of the filter by which the frame is passed */
|
||||
#define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8U, 15U)
|
||||
|
||||
/* receive data byte 0 */
|
||||
#define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0U, 7U)
|
||||
|
||||
/* receive data byte 1 */
|
||||
#define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8U, 15U)
|
||||
|
||||
/* receive data byte 2 */
|
||||
#define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16U, 23U)
|
||||
|
||||
/* receive data byte 3 */
|
||||
#define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24U, 31U)
|
||||
|
||||
/* receive data byte 4 */
|
||||
#define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0U, 7U)
|
||||
|
||||
/* receive data byte 5 */
|
||||
#define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8U, 15U)
|
||||
|
||||
/* receive data byte 6 */
|
||||
#define GET_RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16U, 23U)
|
||||
|
||||
/* receive data byte 7 */
|
||||
#define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24U, 31U)
|
||||
|
||||
/* error number */
|
||||
#define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4U, 6U)
|
||||
|
||||
/* transmit error count */
|
||||
#define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16U, 23U)
|
||||
|
||||
/* receive error count */
|
||||
#define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24U, 31U)
|
||||
|
||||
/* CAN errors */
|
||||
#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4))
|
||||
#define CAN_ERRN_0 ERR_ERRN(0U) /*!< no error */
|
||||
#define CAN_ERRN_1 ERR_ERRN(1U) /*!< fill error */
|
||||
#define CAN_ERRN_2 ERR_ERRN(2U) /*!< format error */
|
||||
#define CAN_ERRN_3 ERR_ERRN(3U) /*!< ACK error */
|
||||
#define CAN_ERRN_4 ERR_ERRN(4U) /*!< bit recessive error */
|
||||
#define CAN_ERRN_5 ERR_ERRN(5U) /*!< bit dominant error */
|
||||
#define CAN_ERRN_6 ERR_ERRN(6U) /*!< CRC error */
|
||||
#define CAN_ERRN_7 ERR_ERRN(7U) /*!< software error */
|
||||
|
||||
#define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */
|
||||
|
||||
/* CAN communication mode */
|
||||
#define CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */
|
||||
#define CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */
|
||||
#define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */
|
||||
#define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */
|
||||
|
||||
/* CAN resynchronisation jump width */
|
||||
#define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */
|
||||
#define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */
|
||||
#define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */
|
||||
#define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */
|
||||
|
||||
/* CAN time segment 1 */
|
||||
#define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */
|
||||
#define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */
|
||||
#define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */
|
||||
#define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */
|
||||
#define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */
|
||||
#define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */
|
||||
#define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */
|
||||
#define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */
|
||||
#define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */
|
||||
#define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */
|
||||
#define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */
|
||||
#define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */
|
||||
#define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */
|
||||
#define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */
|
||||
#define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */
|
||||
#define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */
|
||||
|
||||
/* CAN time segment 2 */
|
||||
#define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */
|
||||
#define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */
|
||||
#define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */
|
||||
#define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */
|
||||
#define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */
|
||||
#define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */
|
||||
#define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */
|
||||
#define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */
|
||||
|
||||
/* CAN mailbox number */
|
||||
#define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */
|
||||
#define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */
|
||||
#define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */
|
||||
#define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */
|
||||
|
||||
/* CAN frame format */
|
||||
#define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */
|
||||
#define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */
|
||||
|
||||
/* CAN receive FIFO */
|
||||
#define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */
|
||||
#define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */
|
||||
|
||||
/* frame number of receive FIFO */
|
||||
#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */
|
||||
|
||||
#define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */
|
||||
#define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */
|
||||
|
||||
/* CAN working mode */
|
||||
#define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */
|
||||
#define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */
|
||||
#define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */
|
||||
|
||||
/* filter bits */
|
||||
#define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */
|
||||
#define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */
|
||||
|
||||
/* filter mode */
|
||||
#define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */
|
||||
#define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */
|
||||
|
||||
/* filter 16 bits mask */
|
||||
#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) /*!< can filter 16 bits mask */
|
||||
|
||||
/* frame type */
|
||||
#define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */
|
||||
#define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */
|
||||
|
||||
/* CAN timeout */
|
||||
#define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */
|
||||
|
||||
/* interrupt enable bits */
|
||||
#define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */
|
||||
#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */
|
||||
#define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */
|
||||
#define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */
|
||||
#define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */
|
||||
#define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */
|
||||
#define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */
|
||||
#define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */
|
||||
#define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */
|
||||
#define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */
|
||||
#define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */
|
||||
#define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */
|
||||
#define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */
|
||||
#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* deinitialize CAN */
|
||||
void can_deinit(uint32_t can_periph);
|
||||
/* initialize CAN structure */
|
||||
void can_struct_para_init(can_struct_type_enum type, void *p_struct);
|
||||
/* initialize CAN */
|
||||
ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init);
|
||||
/* CAN filter initialization */
|
||||
void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init);
|
||||
|
||||
/* function configuration */
|
||||
/* set can1 filter start bank number */
|
||||
void can1_filter_start_bank(uint8_t start_bank);
|
||||
/* enable functions */
|
||||
/* CAN debug freeze enable */
|
||||
void can_debug_freeze_enable(uint32_t can_periph);
|
||||
/* CAN debug freeze disable */
|
||||
void can_debug_freeze_disable(uint32_t can_periph);
|
||||
/* CAN time trigger mode enable */
|
||||
void can_time_trigger_mode_enable(uint32_t can_periph);
|
||||
/* CAN time trigger mode disable */
|
||||
void can_time_trigger_mode_disable(uint32_t can_periph);
|
||||
|
||||
/* transmit functions */
|
||||
/* transmit CAN message */
|
||||
uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message);
|
||||
/* get CAN transmit state */
|
||||
can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number);
|
||||
/* stop CAN transmission */
|
||||
void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number);
|
||||
/* CAN receive message */
|
||||
void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message);
|
||||
/* CAN release FIFO */
|
||||
void can_fifo_release(uint32_t can_periph, uint8_t fifo_number);
|
||||
/* CAN receive message length */
|
||||
uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number);
|
||||
/* CAN working mode */
|
||||
ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode);
|
||||
/* CAN wakeup from sleep mode */
|
||||
ErrStatus can_wakeup(uint32_t can_periph);
|
||||
|
||||
/* CAN get error type */
|
||||
can_error_enum can_error_get(uint32_t can_periph);
|
||||
/* get CAN receive error number */
|
||||
uint8_t can_receive_error_number_get(uint32_t can_periph);
|
||||
/* get CAN transmit error number */
|
||||
uint8_t can_transmit_error_number_get(uint32_t can_periph);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* CAN get flag state */
|
||||
FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag);
|
||||
/* CAN clear flag state */
|
||||
void can_flag_clear(uint32_t can_periph, can_flag_enum flag);
|
||||
/* CAN interrupt enable */
|
||||
void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt);
|
||||
/* CAN interrupt disable */
|
||||
void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt);
|
||||
/* CAN get interrupt flag state */
|
||||
FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag);
|
||||
/* CAN clear interrupt flag state */
|
||||
void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag);
|
||||
|
||||
#endif /* GD32F4XX_CAN_H */
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
/*!
|
||||
\file gd32f4xx_crc.h
|
||||
\brief definitions for the CRC
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_CRC_H
|
||||
#define GD32F4XX_CRC_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* CRC definitions */
|
||||
#define CRC CRC_BASE /*!< CRC base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define CRC_DATA REG32(CRC + 0x00000000U) /*!< CRC data register */
|
||||
#define CRC_FDATA REG32(CRC + 0x00000004U) /*!< CRC free data register */
|
||||
#define CRC_CTL REG32(CRC + 0x00000008U) /*!< CRC control register */
|
||||
|
||||
/* bits definitions */
|
||||
/* CRC_DATA */
|
||||
#define CRC_DATA_DATA BITS(0,31) /*!< CRC calculation result bits */
|
||||
|
||||
/* CRC_FDATA */
|
||||
#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */
|
||||
|
||||
/* CRC_CTL */
|
||||
#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */
|
||||
|
||||
|
||||
/* function declarations */
|
||||
/* deinit CRC calculation unit */
|
||||
void crc_deinit(void);
|
||||
|
||||
/* reset data register(CRC_DATA) to the value of 0xFFFFFFFF */
|
||||
void crc_data_register_reset(void);
|
||||
/* read the value of the data register */
|
||||
uint32_t crc_data_register_read(void);
|
||||
|
||||
/* read the value of the free data register */
|
||||
uint8_t crc_free_data_register_read(void);
|
||||
/* write data to the free data register */
|
||||
void crc_free_data_register_write(uint8_t free_data);
|
||||
|
||||
/* calculate the CRC value of a 32-bit data */
|
||||
uint32_t crc_single_data_calculate(uint32_t sdata);
|
||||
/* calculate the CRC value of an array of 32-bit values */
|
||||
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size);
|
||||
|
||||
#endif /* GD32F4XX_CRC_H */
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
/*!
|
||||
\file gd32f4xx_ctc.h
|
||||
\brief definitions for the CTC
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_CTC_H
|
||||
#define GD32F4XX_CTC_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* CTC definitions */
|
||||
#define CTC CTC_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define CTC_CTL0 REG32((CTC) + 0x00U) /*!< CTC control register 0 */
|
||||
#define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */
|
||||
#define CTC_STAT REG32((CTC) + 0x08U) /*!< CTC status register */
|
||||
#define CTC_INTC REG32((CTC) + 0x0CU) /*!< CTC interrupt clear register */
|
||||
|
||||
/* bits definitions */
|
||||
/* CTC_CTL0 */
|
||||
#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */
|
||||
#define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */
|
||||
#define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */
|
||||
#define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */
|
||||
#define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */
|
||||
#define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */
|
||||
#define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */
|
||||
#define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */
|
||||
|
||||
/* CTC_CTL1 */
|
||||
#define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */
|
||||
#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */
|
||||
#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */
|
||||
#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */
|
||||
#define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */
|
||||
|
||||
/* CTC_STAT */
|
||||
#define CTC_STAT_CKOKIF BIT(0) /*!< clock trim OK interrupt flag */
|
||||
#define CTC_STAT_CKWARNIF BIT(1) /*!< clock trim warning interrupt flag */
|
||||
#define CTC_STAT_ERRIF BIT(2) /*!< error interrupt flag */
|
||||
#define CTC_STAT_EREFIF BIT(3) /*!< expect reference interrupt flag */
|
||||
#define CTC_STAT_CKERR BIT(8) /*!< clock trim error bit */
|
||||
#define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */
|
||||
#define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */
|
||||
#define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */
|
||||
#define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */
|
||||
|
||||
/* CTC_INTC */
|
||||
#define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */
|
||||
#define CTC_INTC_CKWARNIC BIT(1) /*!< CKWARNIF interrupt clear bit */
|
||||
#define CTC_INTC_ERRIC BIT(2) /*!< ERRIF interrupt clear bit */
|
||||
#define CTC_INTC_EREFIC BIT(3) /*!< EREFIF interrupt clear bit */
|
||||
|
||||
/* constants definitions */
|
||||
/* hardware automatically trim mode definitions */
|
||||
#define CTC_HARDWARE_TRIM_MODE_ENABLE CTC_CTL0_AUTOTRIM /*!< hardware automatically trim mode enable*/
|
||||
#define CTC_HARDWARE_TRIM_MODE_DISABLE ((uint32_t)0x00000000U) /*!< hardware automatically trim mode disable*/
|
||||
|
||||
/* reference signal source polarity definitions */
|
||||
#define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/
|
||||
#define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/
|
||||
|
||||
/* reference signal source selection definitions */
|
||||
#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
|
||||
#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */
|
||||
#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is clock selected */
|
||||
|
||||
/* reference signal source prescaler definitions */
|
||||
#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
|
||||
#define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */
|
||||
#define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */
|
||||
#define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */
|
||||
#define CTC_REFSOURCE_PSC_DIV8 CTL1_REFPSC(3) /*!< reference signal divided by 8 */
|
||||
#define CTC_REFSOURCE_PSC_DIV16 CTL1_REFPSC(4) /*!< reference signal divided by 16 */
|
||||
#define CTC_REFSOURCE_PSC_DIV32 CTL1_REFPSC(5) /*!< reference signal divided by 32 */
|
||||
#define CTC_REFSOURCE_PSC_DIV64 CTL1_REFPSC(6) /*!< reference signal divided by 64 */
|
||||
#define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7) /*!< reference signal divided by 128 */
|
||||
|
||||
/* CTC interrupt enable definitions */
|
||||
#define CTC_INT_CKOK CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */
|
||||
#define CTC_INT_CKWARN CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */
|
||||
#define CTC_INT_ERR CTC_CTL0_ERRIE /*!< error interrupt enable */
|
||||
#define CTC_INT_EREF CTC_CTL0_EREFIE /*!< expect reference interrupt enable */
|
||||
|
||||
/* CTC interrupt source definitions */
|
||||
#define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */
|
||||
#define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */
|
||||
#define CTC_INT_FLAG_ERR CTC_STAT_ERRIF /*!< error interrupt flag */
|
||||
#define CTC_INT_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */
|
||||
#define CTC_INT_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */
|
||||
#define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */
|
||||
#define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */
|
||||
|
||||
/* CTC flag definitions */
|
||||
#define CTC_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK flag */
|
||||
#define CTC_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning flag */
|
||||
#define CTC_FLAG_ERR CTC_STAT_ERRIF /*!< error flag */
|
||||
#define CTC_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference flag */
|
||||
#define CTC_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */
|
||||
#define CTC_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */
|
||||
#define CTC_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error bit */
|
||||
|
||||
/* function declarations */
|
||||
/* reset ctc clock trim controller */
|
||||
void ctc_deinit(void);
|
||||
/* enable CTC trim counter */
|
||||
void ctc_counter_enable(void);
|
||||
/* disable CTC trim counter */
|
||||
void ctc_counter_disable(void);
|
||||
|
||||
/* configure the IRC48M trim value */
|
||||
void ctc_irc48m_trim_value_config(uint8_t trim_value);
|
||||
/* generate software reference source sync pulse */
|
||||
void ctc_software_refsource_pulse_generate(void);
|
||||
/* configure hardware automatically trim mode */
|
||||
void ctc_hardware_trim_mode_config(uint32_t hardmode);
|
||||
|
||||
/* configure reference signal source polarity */
|
||||
void ctc_refsource_polarity_config(uint32_t polarity);
|
||||
/* select reference signal source */
|
||||
void ctc_refsource_signal_select(uint32_t refs);
|
||||
/* configure reference signal source prescaler */
|
||||
void ctc_refsource_prescaler_config(uint32_t prescaler);
|
||||
/* configure clock trim base limit value */
|
||||
void ctc_clock_limit_value_config(uint8_t limit_value);
|
||||
/* configure CTC counter reload value */
|
||||
void ctc_counter_reload_value_config(uint16_t reload_value);
|
||||
|
||||
/* read CTC counter capture value when reference sync pulse occurred */
|
||||
uint16_t ctc_counter_capture_value_read(void);
|
||||
/* read CTC trim counter direction when reference sync pulse occurred */
|
||||
FlagStatus ctc_counter_direction_read(void);
|
||||
/* read CTC counter reload value */
|
||||
uint16_t ctc_counter_reload_value_read(void);
|
||||
/* read the IRC48M trim value */
|
||||
uint8_t ctc_irc48m_trim_value_read(void);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* enable the CTC interrupt */
|
||||
void ctc_interrupt_enable(uint32_t interrupt);
|
||||
/* disable the CTC interrupt */
|
||||
void ctc_interrupt_disable(uint32_t interrupt);
|
||||
/* get CTC interrupt flag */
|
||||
FlagStatus ctc_interrupt_flag_get(uint32_t int_flag);
|
||||
/* clear CTC interrupt flag */
|
||||
void ctc_interrupt_flag_clear(uint32_t int_flag);
|
||||
/* get CTC flag */
|
||||
FlagStatus ctc_flag_get(uint32_t flag);
|
||||
/* clear CTC flag */
|
||||
void ctc_flag_clear(uint32_t flag);
|
||||
|
||||
#endif /* GD32F4XX_CTC_H */
|
||||
|
|
@ -0,0 +1,271 @@
|
|||
/*!
|
||||
\file gd32f4xx_dac.h
|
||||
\brief definitions for the DAC
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_DAC_H
|
||||
#define GD32F4XX_DAC_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* DACx(x=0,1) definitions */
|
||||
#define DAC DAC_BASE
|
||||
#define DAC0 0U
|
||||
#define DAC1 1U
|
||||
|
||||
/* registers definitions */
|
||||
#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */
|
||||
#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */
|
||||
#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */
|
||||
#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */
|
||||
#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */
|
||||
#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */
|
||||
#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */
|
||||
#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */
|
||||
#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */
|
||||
#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */
|
||||
#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */
|
||||
#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */
|
||||
#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */
|
||||
#define DAC_STAT REG32(DAC + 0x34U) /*!< DAC status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* DAC_CTL */
|
||||
#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */
|
||||
#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */
|
||||
#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */
|
||||
#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */
|
||||
#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */
|
||||
#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */
|
||||
#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */
|
||||
#define DAC_CTL_DDUDRIE0 BIT(13) /*!< DAC0 DMA underrun interrupt enable/disable bit */
|
||||
#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */
|
||||
#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */
|
||||
#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */
|
||||
#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */
|
||||
#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */
|
||||
#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */
|
||||
#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */
|
||||
#define DAC_CTL_DDUDRIE1 BIT(29) /*!< DAC1 DMA underrun interrupt enable/disable bit */
|
||||
|
||||
/* DAC_SWT */
|
||||
#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */
|
||||
#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */
|
||||
|
||||
/* DAC0_R12DH */
|
||||
#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */
|
||||
|
||||
/* DAC0_L12DH */
|
||||
#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */
|
||||
|
||||
/* DAC0_R8DH */
|
||||
#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */
|
||||
|
||||
/* DAC1_R12DH */
|
||||
#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */
|
||||
|
||||
/* DAC1_L12DH */
|
||||
#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */
|
||||
|
||||
/* DAC1_R8DH */
|
||||
#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */
|
||||
|
||||
/* DACC_R12DH */
|
||||
#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */
|
||||
#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */
|
||||
|
||||
/* DACC_L12DH */
|
||||
#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */
|
||||
#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */
|
||||
|
||||
/* DACC_R8DH */
|
||||
#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */
|
||||
#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */
|
||||
|
||||
/* DAC0_DO */
|
||||
#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */
|
||||
|
||||
/* DAC1_DO */
|
||||
#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */
|
||||
|
||||
/* DAC_STAT */
|
||||
#define DAC_STAT_DDUDR0 BIT(13) /*!< DAC0 DMA underrun flag */
|
||||
#define DAC_STAT_DDUDR1 BIT(29) /*!< DAC1 DMA underrun flag */
|
||||
|
||||
/* constants definitions */
|
||||
/* DAC trigger source */
|
||||
#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
|
||||
#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */
|
||||
#define DAC_TRIGGER_T7_TRGO CTL_DTSEL(1) /*!< TIMER7 TRGO */
|
||||
#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */
|
||||
#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */
|
||||
#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */
|
||||
#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */
|
||||
#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */
|
||||
#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */
|
||||
|
||||
/* DAC noise wave mode */
|
||||
#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
|
||||
#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */
|
||||
#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */
|
||||
#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */
|
||||
|
||||
/* DAC noise wave bit width */
|
||||
#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
|
||||
#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */
|
||||
#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */
|
||||
#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */
|
||||
#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */
|
||||
#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */
|
||||
#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */
|
||||
#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */
|
||||
#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */
|
||||
#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */
|
||||
#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */
|
||||
#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */
|
||||
#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */
|
||||
|
||||
/* unmask LFSR bits in DAC LFSR noise mode */
|
||||
#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */
|
||||
#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */
|
||||
#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */
|
||||
#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */
|
||||
#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */
|
||||
#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */
|
||||
#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */
|
||||
#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */
|
||||
#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */
|
||||
#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */
|
||||
#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */
|
||||
#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */
|
||||
|
||||
/* DAC data alignment */
|
||||
#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12 bit alignment */
|
||||
#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12 bit alignment */
|
||||
#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8 bit alignment */
|
||||
|
||||
/* triangle amplitude in DAC triangle noise mode */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* deinitialize DAC */
|
||||
void dac_deinit(void);
|
||||
/* enable DAC */
|
||||
void dac_enable(uint32_t dac_periph);
|
||||
/* disable DAC */
|
||||
void dac_disable(uint32_t dac_periph);
|
||||
/* enable DAC DMA */
|
||||
void dac_dma_enable(uint32_t dac_periph);
|
||||
/* disable DAC DMA */
|
||||
void dac_dma_disable(uint32_t dac_periph);
|
||||
/* enable DAC output buffer */
|
||||
void dac_output_buffer_enable(uint32_t dac_periph);
|
||||
/* disable DAC output buffer */
|
||||
void dac_output_buffer_disable(uint32_t dac_periph);
|
||||
/* get the last data output value */
|
||||
uint16_t dac_output_value_get(uint32_t dac_periph);
|
||||
/* set DAC data holding register value */
|
||||
void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data);
|
||||
|
||||
/* DAC trigger configuration */
|
||||
/* enable DAC trigger */
|
||||
void dac_trigger_enable(uint32_t dac_periph);
|
||||
/* disable DAC trigger */
|
||||
void dac_trigger_disable(uint32_t dac_periph);
|
||||
/* configure DAC trigger source */
|
||||
void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource);
|
||||
/* enable DAC software trigger */
|
||||
void dac_software_trigger_enable(uint32_t dac_periph);
|
||||
/* disable DAC software trigger */
|
||||
void dac_software_trigger_disable(uint32_t dac_periph);
|
||||
|
||||
/* DAC wave mode configuration */
|
||||
/* configure DAC wave mode */
|
||||
void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode);
|
||||
/* configure DAC wave bit width */
|
||||
void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width);
|
||||
/* configure DAC LFSR noise mode */
|
||||
void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits);
|
||||
/* configure DAC triangle noise mode */
|
||||
void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude);
|
||||
|
||||
/* DAC concurrent mode configuration */
|
||||
/* enable DAC concurrent mode */
|
||||
void dac_concurrent_enable(void);
|
||||
/* disable DAC concurrent mode */
|
||||
void dac_concurrent_disable(void);
|
||||
/* enable DAC concurrent software trigger */
|
||||
void dac_concurrent_software_trigger_enable(void);
|
||||
/* disable DAC concurrent software trigger */
|
||||
void dac_concurrent_software_trigger_disable(void);
|
||||
/* enable DAC concurrent buffer function */
|
||||
void dac_concurrent_output_buffer_enable(void);
|
||||
/* disable DAC concurrent buffer function */
|
||||
void dac_concurrent_output_buffer_disable(void);
|
||||
/* set DAC concurrent mode data holding register value */
|
||||
void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1);
|
||||
/* enable DAC concurrent interrupt */
|
||||
void dac_concurrent_interrupt_enable(void);
|
||||
/* disable DAC concurrent interrupt */
|
||||
void dac_concurrent_interrupt_disable(void);
|
||||
|
||||
/* DAC interrupt configuration */
|
||||
/* get the specified DAC flag(DAC DMA underrun flag) */
|
||||
FlagStatus dac_flag_get(uint32_t dac_periph);
|
||||
/* clear the specified DAC flag(DAC DMA underrun flag) */
|
||||
void dac_flag_clear(uint32_t dac_periph);
|
||||
/* enable DAC interrupt(DAC DMA underrun interrupt) */
|
||||
void dac_interrupt_enable(uint32_t dac_periph);
|
||||
/* disable DAC interrupt(DAC DMA underrun interrupt) */
|
||||
void dac_interrupt_disable(uint32_t dac_periph);
|
||||
/* get the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */
|
||||
FlagStatus dac_interrupt_flag_get(uint32_t dac_periph);
|
||||
/* clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */
|
||||
void dac_interrupt_flag_clear(uint32_t dac_periph);
|
||||
|
||||
#endif /* GD32F4XX_DAC_H */
|
||||
|
|
@ -0,0 +1,153 @@
|
|||
/*!
|
||||
\file gd32f4xx_dbg.h
|
||||
\brief definitions for the DBG
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_DBG_H
|
||||
#define GD32F4XX_DBG_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* DBG definitions */
|
||||
#define DBG DBG_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */
|
||||
#define DBG_CTL0 REG32(DBG + 0x04U) /*!< DBG control register 0 */
|
||||
#define DBG_CTL1 REG32(DBG + 0x08U) /*!< DBG control register 1 */
|
||||
#define DBG_CTL2 REG32(DBG + 0x0CU) /*!< DBG control register 2 */
|
||||
|
||||
/* bits definitions */
|
||||
/* DBG_ID */
|
||||
#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */
|
||||
|
||||
/* DBG_CTL0 */
|
||||
#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
|
||||
#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
|
||||
#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
|
||||
#define DBG_CTL0_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */
|
||||
|
||||
/* DBG_CTL1 */
|
||||
#define DBG_CTL1_TIMER1_HOLD BIT(0) /*!< hold TIMER1 counter when core is halted */
|
||||
#define DBG_CTL1_TIMER2_HOLD BIT(1) /*!< hold TIMER2 counter when core is halted */
|
||||
#define DBG_CTL1_TIMER3_HOLD BIT(2) /*!< hold TIMER3 counter when core is halted */
|
||||
#define DBG_CTL1_TIMER4_HOLD BIT(3) /*!< hold TIMER4 counter when core is halted */
|
||||
#define DBG_CTL1_TIMER5_HOLD BIT(4) /*!< hold TIMER5 counter when core is halted */
|
||||
#define DBG_CTL1_TIMER6_HOLD BIT(5) /*!< hold TIMER6 counter when core is halted */
|
||||
#define DBG_CTL1_TIMER11_HOLD BIT(6) /*!< hold TIMER11 counter when core is halted */
|
||||
#define DBG_CTL1_TIMER12_HOLD BIT(7) /*!< hold TIMER12 counter when core is halted */
|
||||
#define DBG_CTL1_TIMER13_HOLD BIT(8) /*!< hold TIMER13 counter when core is halted */
|
||||
#define DBG_CTL1_RTC_HOLD BIT(10) /*!< hold RTC calendar and wakeup counter when core is halted */
|
||||
#define DBG_CTL1_WWDGT_HOLD BIT(11) /*!< debug WWDGT kept when core is halted */
|
||||
#define DBG_CTL1_FWDGT_HOLD BIT(12) /*!< debug FWDGT kept when core is halted */
|
||||
#define DBG_CTL1_I2C0_HOLD BIT(21) /*!< hold I2C0 smbus when core is halted */
|
||||
#define DBG_CTL1_I2C1_HOLD BIT(22) /*!< hold I2C1 smbus when core is halted */
|
||||
#define DBG_CTL1_I2C2_HOLD BIT(23) /*!< hold I2C2 smbus when core is halted */
|
||||
#define DBG_CTL1_CAN0_HOLD BIT(25) /*!< debug CAN0 kept when core is halted */
|
||||
#define DBG_CTL1_CAN1_HOLD BIT(26) /*!< debug CAN1 kept when core is halted */
|
||||
|
||||
/* DBG_CTL2 */
|
||||
#define DBG_CTL2_TIMER0_HOLD BIT(0) /*!< hold TIMER0 counter when core is halted */
|
||||
#define DBG_CTL2_TIMER7_HOLD BIT(1) /*!< hold TIMER7 counter when core is halted */
|
||||
#define DBG_CTL2_TIMER8_HOLD BIT(16) /*!< hold TIMER8 counter when core is halted */
|
||||
#define DBG_CTL2_TIMER9_HOLD BIT(17) /*!< hold TIMER9 counter when core is halted */
|
||||
#define DBG_CTL2_TIMER10_HOLD BIT(18) /*!< hold TIMER10 counter when core is halted */
|
||||
|
||||
/* constants definitions */
|
||||
#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */
|
||||
#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
|
||||
#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */
|
||||
|
||||
/* define the peripheral debug hold bit position and its register index offset */
|
||||
#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos))
|
||||
#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6)))
|
||||
#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
|
||||
|
||||
/* register index */
|
||||
enum dbg_reg_idx
|
||||
{
|
||||
DBG_IDX_CTL0 = 0x04U,
|
||||
DBG_IDX_CTL1 = 0x08U,
|
||||
DBG_IDX_CTL2 = 0x0CU
|
||||
};
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 0U), /*!< hold TIMER1 counter when core is halted */
|
||||
DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 1U), /*!< hold TIMER2 counter when core is halted */
|
||||
DBG_TIMER3_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 2U), /*!< hold TIMER3 counter when core is halted */
|
||||
DBG_TIMER4_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 3U), /*!< hold TIMER4 counter when core is halted */
|
||||
DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 4U), /*!< hold TIMER5 counter when core is halted */
|
||||
DBG_TIMER6_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 5U), /*!< hold TIMER6 counter when core is halted */
|
||||
DBG_TIMER11_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 6U), /*!< hold TIMER11 counter when core is halted */
|
||||
DBG_TIMER12_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 7U), /*!< hold TIMER12 counter when core is halted */
|
||||
DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 8U), /*!< hold TIMER13 counter when core is halted */
|
||||
DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U), /*!< hold RTC calendar and wakeup counter when core is halted */
|
||||
DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 11U), /*!< debug WWDGT kept when core is halted */
|
||||
DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 12U), /*!< debug FWDGT kept when core is halted */
|
||||
DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 21U), /*!< hold I2C0 smbus when core is halted */
|
||||
DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 22U), /*!< hold I2C1 smbus when core is halted */
|
||||
DBG_I2C2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 23U), /*!< hold I2C2 smbus when core is halted */
|
||||
DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 25U), /*!< debug CAN0 kept when core is halted */
|
||||
DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 26U), /*!< debug CAN1 kept when core is halted */
|
||||
DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 0U), /*!< hold TIMER0 counter when core is halted */
|
||||
DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 1U), /*!< hold TIMER7 counter when core is halted */
|
||||
DBG_TIMER8_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 16U), /*!< hold TIMER8 counter when core is halted */
|
||||
DBG_TIMER9_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 17U), /*!< hold TIMER9 counter when core is halted */
|
||||
DBG_TIMER10_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 18U) /*!< hold TIMER10 counter when core is halted */
|
||||
}dbg_periph_enum;
|
||||
|
||||
/* function declarations */
|
||||
/* deinitialize the DBG */
|
||||
void dbg_deinit(void);
|
||||
/* read DBG_ID code register */
|
||||
uint32_t dbg_id_get(void);
|
||||
|
||||
/* enable low power behavior when the MCU is in debug mode */
|
||||
void dbg_low_power_enable(uint32_t dbg_low_power);
|
||||
/* disable low power behavior when the MCU is in debug mode */
|
||||
void dbg_low_power_disable(uint32_t dbg_low_power);
|
||||
|
||||
/* enable peripheral behavior when the MCU is in debug mode */
|
||||
void dbg_periph_enable(dbg_periph_enum dbg_periph);
|
||||
/* disable peripheral behavior when the MCU is in debug mode */
|
||||
void dbg_periph_disable(dbg_periph_enum dbg_periph);
|
||||
|
||||
/* enable trace pin assignment */
|
||||
void dbg_trace_pin_enable(void);
|
||||
/* disable trace pin assignment */
|
||||
void dbg_trace_pin_disable(void);
|
||||
|
||||
#endif /* GD32F4XX_DBG_H */
|
||||
|
|
@ -0,0 +1,239 @@
|
|||
/*!
|
||||
\file gd32f4xx_dci.h
|
||||
\brief definitions for the DCI
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_DCI_H
|
||||
#define GD32F4XX_DCI_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* DCI definitions */
|
||||
#define DCI DCI_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define DCI_CTL REG32(DCI + 0x00U) /*!< DCI control register */
|
||||
#define DCI_STAT0 REG32(DCI + 0x04U) /*!< DCI status register 0 */
|
||||
#define DCI_STAT1 REG32(DCI + 0x08U) /*!< DCI status register 1 */
|
||||
#define DCI_INTEN REG32(DCI + 0x0CU) /*!< DCI interrupt enable register */
|
||||
#define DCI_INTF REG32(DCI + 0x10U) /*!< DCI interrupt flag register */
|
||||
#define DCI_INTC REG32(DCI + 0x14U) /*!< DCI interrupt clear register */
|
||||
#define DCI_SC REG32(DCI + 0x18U) /*!< DCI synchronization codes register */
|
||||
#define DCI_SCUMSK REG32(DCI + 0x1CU) /*!< DCI synchronization codes unmask register */
|
||||
#define DCI_CWSPOS REG32(DCI + 0x20U) /*!< DCI cropping window start position register */
|
||||
#define DCI_CWSZ REG32(DCI + 0x24U) /*!< DCI cropping window size register */
|
||||
#define DCI_DATA REG32(DCI + 0x28U) /*!< DCI data register */
|
||||
|
||||
/* bits definitions */
|
||||
/* DCI_CTL */
|
||||
#define DCI_CTL_CAP BIT(0) /*!< capture enable */
|
||||
#define DCI_CTL_SNAP BIT(1) /*!< snapshot mode */
|
||||
#define DCI_CTL_WDEN BIT(2) /*!< window enable */
|
||||
#define DCI_CTL_JM BIT(3) /*!< JPEG mode */
|
||||
#define DCI_CTL_ESM BIT(4) /*!< embedded synchronous mode */
|
||||
#define DCI_CTL_CKS BIT(5) /*!< clock polarity selection */
|
||||
#define DCI_CTL_HPS BIT(6) /*!< horizontal polarity selection */
|
||||
#define DCI_CTL_VPS BIT(7) /*!< vertical polarity selection */
|
||||
#define DCI_CTL_FR BITS(8,9) /*!< frame rate */
|
||||
#define DCI_CTL_DCIF BITS(10,11) /*!< digital camera interface format */
|
||||
#define DCI_CTL_DCIEN BIT(14) /*!< DCI enable */
|
||||
|
||||
/* DCI_STAT0 */
|
||||
#define DCI_STAT0_HS BIT(0) /*!< HS line status */
|
||||
#define DCI_STAT0_VS BIT(1) /*!< VS line status */
|
||||
#define DCI_STAT0_FV BIT(2) /*!< FIFO valid */
|
||||
|
||||
/* DCI_STAT1 */
|
||||
#define DCI_STAT1_EFF BIT(0) /*!< end of frame flag */
|
||||
#define DCI_STAT1_OVRF BIT(1) /*!< FIFO overrun flag */
|
||||
#define DCI_STAT1_ESEF BIT(2) /*!< embedded synchronous error flag */
|
||||
#define DCI_STAT1_VSF BIT(3) /*!< vsync flag */
|
||||
#define DCI_STAT1_ELF BIT(4) /*!< end of line flag */
|
||||
|
||||
/* DCI_INTEN */
|
||||
#define DCI_INTEN_EFIE BIT(0) /*!< end of frame interrupt enable */
|
||||
#define DCI_INTEN_OVRIE BIT(1) /*!< FIFO overrun interrupt enable */
|
||||
#define DCI_INTEN_ESEIE BIT(2) /*!< embedded synchronous error interrupt enable */
|
||||
#define DCI_INTEN_VSIE BIT(3) /*!< vsync interrupt enable */
|
||||
#define DCI_INTEN_ELIE BIT(4) /*!< end of line interrupt enable */
|
||||
|
||||
/* DCI_INTF */
|
||||
#define DCI_INTF_EFIF BIT(0) /*!< end of frame interrupt flag */
|
||||
#define DCI_INTF_OVRIF BIT(1) /*!< FIFO overrun interrupt flag */
|
||||
#define DCI_INTF_ESEIF BIT(2) /*!< embedded synchronous error interrupt flag */
|
||||
#define DCI_INTF_VSIF BIT(3) /*!< vsync interrupt flag */
|
||||
#define DCI_INTF_ELIF BIT(4) /*!< end of line interrupt flag */
|
||||
|
||||
/* DCI_INTC */
|
||||
#define DCI_INTC_EFFC BIT(0) /*!< clear end of frame flag */
|
||||
#define DCI_INTC_OVRFC BIT(1) /*!< clear FIFO overrun flag */
|
||||
#define DCI_INTC_ESEFC BIT(2) /*!< clear embedded synchronous error flag */
|
||||
#define DCI_INTC_VSFC BIT(3) /*!< vsync flag clear */
|
||||
#define DCI_INTC_ELFC BIT(4) /*!< end of line flag clear */
|
||||
|
||||
/* DCI_SC */
|
||||
#define DCI_SC_FS BITS(0,7) /*!< frame start code in embedded synchronous mode */
|
||||
#define DCI_SC_LS BITS(8,15) /*!< line start code in embedded synchronous mode */
|
||||
#define DCI_SC_LE BITS(16,23) /*!< line end code in embedded synchronous mode */
|
||||
#define DCI_SC_FE BITS(24,31) /*!< frame end code in embedded synchronous mode */
|
||||
|
||||
/* DCI_SCUNMSK */
|
||||
#define DCI_SCUMSK_FSM BITS(0,7) /*!< frame start code unmask bits in embedded synchronous mode */
|
||||
#define DCI_SCUMSK_LSM BITS(8,15) /*!< line start code unmask bits in embedded synchronous mode */
|
||||
#define DCI_SCUMSK_LEM BITS(16,23) /*!< line end code unmask bits in embedded synchronous mode */
|
||||
#define DCI_SCUMSK_FEM BITS(24,31) /*!< frame end code unmask bits in embedded synchronous mode */
|
||||
|
||||
/* DCI_CWSPOS */
|
||||
#define DCI_CWSPOS_WHSP BITS(0,13) /*!< window horizontal start position */
|
||||
#define DCI_CWSPOS_WVSP BITS(16,28) /*!< window vertical start position */
|
||||
|
||||
/* DCI_CWSZ */
|
||||
#define DCI_CWSZ_WHSZ BITS(0,13) /*!< window horizontal size */
|
||||
#define DCI_CWSZ_WVSZ BITS(16,29) /*!< window vertical size */
|
||||
|
||||
/* constants definitions */
|
||||
/* DCI parameter structure definitions */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t capture_mode; /*!< DCI capture mode: continuous or snapshot */
|
||||
uint32_t clock_polarity; /*!< clock polarity selection */
|
||||
uint32_t hsync_polarity; /*!< horizontal polarity selection */
|
||||
uint32_t vsync_polarity; /*!< vertical polarity selection */
|
||||
uint32_t frame_rate; /*!< frame capture rate */
|
||||
uint32_t interface_format; /*!< digital camera interface format */
|
||||
}dci_parameter_struct;
|
||||
|
||||
#define DCI_CAPTURE_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< continuous capture mode */
|
||||
#define DCI_CAPTURE_MODE_SNAPSHOT DCI_CTL_SNAP /*!< snapshot capture mode */
|
||||
|
||||
#define DCI_CK_POLARITY_FALLING ((uint32_t)0x00000000U) /*!< capture at falling edge */
|
||||
#define DCI_CK_POLARITY_RISING DCI_CTL_CKS /*!< capture at rising edge */
|
||||
|
||||
#define DCI_HSYNC_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level during blanking period */
|
||||
#define DCI_HSYNC_POLARITY_HIGH DCI_CTL_HPS /*!< high level during blanking period */
|
||||
|
||||
#define DCI_VSYNC_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level during blanking period */
|
||||
#define DCI_VSYNC_POLARITY_HIGH DCI_CTL_VPS /*!< high level during blanking period*/
|
||||
|
||||
#define CTL_FR(regval) (BITS(8,9)&((uint32_t)(regval) << 8U))
|
||||
#define DCI_FRAME_RATE_ALL CTL_FR(0) /*!< capture all frames */
|
||||
#define DCI_FRAME_RATE_1_2 CTL_FR(1) /*!< capture one in 2 frames */
|
||||
#define DCI_FRAME_RATE_1_4 CTL_FR(2) /*!< capture one in 4 frames */
|
||||
|
||||
#define CTL_DCIF(regval) (BITS(10,11)&((uint32_t)(regval) << 10U))
|
||||
#define DCI_INTERFACE_FORMAT_8BITS CTL_DCIF(0) /*!< 8-bit data on every pixel clock */
|
||||
#define DCI_INTERFACE_FORMAT_10BITS CTL_DCIF(1) /*!< 10-bit data on every pixel clock */
|
||||
#define DCI_INTERFACE_FORMAT_12BITS CTL_DCIF(2) /*!< 12-bit data on every pixel clock */
|
||||
#define DCI_INTERFACE_FORMAT_14BITS CTL_DCIF(3) /*!< 14-bit data on every pixel clock */
|
||||
|
||||
/* DCI interrupt constants definitions */
|
||||
#define DCI_INT_EF BIT(0) /*!< end of frame interrupt */
|
||||
#define DCI_INT_OVR BIT(1) /*!< FIFO overrun interrupt */
|
||||
#define DCI_INT_ESE BIT(2) /*!< embedded synchronous error interrupt */
|
||||
#define DCI_INT_VSYNC BIT(3) /*!< vsync interrupt */
|
||||
#define DCI_INT_EL BIT(4) /*!< end of line interrupt */
|
||||
|
||||
/* DCI interrupt flag definitions */
|
||||
#define DCI_INT_FLAG_EF BIT(0) /*!< end of frame interrupt flag */
|
||||
#define DCI_INT_FLAG_OVR BIT(1) /*!< FIFO overrun interrupt flag */
|
||||
#define DCI_INT_FLAG_ESE BIT(2) /*!< embedded synchronous error interrupt flag */
|
||||
#define DCI_INT_FLAG_VSYNC BIT(3) /*!< vsync interrupt flag */
|
||||
#define DCI_INT_FLAG_EL BIT(4) /*!< end of line interrupt flag */
|
||||
|
||||
/* DCI flag definitions */
|
||||
#define DCI_FLAG_HS DCI_STAT0_HS /*!< HS line status */
|
||||
#define DCI_FLAG_VS DCI_STAT0_VS /*!< VS line status */
|
||||
#define DCI_FLAG_FV DCI_STAT0_FV /*!< FIFO valid */
|
||||
#define DCI_FLAG_EF (DCI_STAT1_EFF | BIT(31)) /*!< end of frame flag */
|
||||
#define DCI_FLAG_OVR (DCI_STAT1_OVRF | BIT(31)) /*!< FIFO overrun flag */
|
||||
#define DCI_FLAG_ESE (DCI_STAT1_ESEF | BIT(31)) /*!< embedded synchronous error flag */
|
||||
#define DCI_FLAG_VSYNC (DCI_STAT1_VSF | BIT(31)) /*!< vsync flag */
|
||||
#define DCI_FLAG_EL (DCI_STAT1_ELF | BIT(31)) /*!< end of line flag */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* DCI deinit */
|
||||
void dci_deinit(void);
|
||||
/* initialize DCI registers */
|
||||
void dci_init(dci_parameter_struct* dci_struct);
|
||||
|
||||
/* enable DCI function */
|
||||
void dci_enable(void);
|
||||
/* disable DCI function */
|
||||
void dci_disable(void);
|
||||
/* enable DCI capture */
|
||||
void dci_capture_enable(void);
|
||||
/* disable DCI capture */
|
||||
void dci_capture_disable(void);
|
||||
/* enable DCI jpeg mode */
|
||||
void dci_jpeg_enable(void);
|
||||
/* disable DCI jpeg mode */
|
||||
void dci_jpeg_disable(void);
|
||||
|
||||
/* function configuration */
|
||||
/* enable cropping window function */
|
||||
void dci_crop_window_enable(void);
|
||||
/* disable cropping window function */
|
||||
void dci_crop_window_disable(void);
|
||||
/* configure DCI cropping window */
|
||||
void dci_crop_window_config(uint16_t start_x, uint16_t start_y, uint16_t size_width, uint16_t size_height);
|
||||
|
||||
/* enable embedded synchronous mode */
|
||||
void dci_embedded_sync_enable(void);
|
||||
/* disable embedded synchronous mode */
|
||||
void dci_embedded_sync_disable(void);
|
||||
/* configure synchronous codes in embedded synchronous mode */
|
||||
void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end);
|
||||
/* configure synchronous codes unmask in embedded synchronous mode */
|
||||
void dci_sync_codes_unmask_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end);
|
||||
|
||||
/* read DCI data register */
|
||||
uint32_t dci_data_read(void);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* get specified flag */
|
||||
FlagStatus dci_flag_get(uint32_t flag);
|
||||
/* enable specified DCI interrupt */
|
||||
void dci_interrupt_enable(uint32_t interrupt);
|
||||
/* disable specified DCI interrupt */
|
||||
void dci_interrupt_disable(uint32_t interrupt);
|
||||
|
||||
|
||||
/* get specified interrupt flag */
|
||||
FlagStatus dci_interrupt_flag_get(uint32_t int_flag);
|
||||
/* clear specified interrupt flag */
|
||||
void dci_interrupt_flag_clear(uint32_t int_flag);
|
||||
|
||||
#endif /* GD32F4XX_DCI_H */
|
||||
|
|
@ -0,0 +1,428 @@
|
|||
/*!
|
||||
\file gd32f4xx_dma.h
|
||||
\brief definitions for the DMA
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_DMA_H
|
||||
#define GD32F4XX_DMA_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* DMA definitions */
|
||||
#define DMA0 (DMA_BASE) /*!< DMA0 base address */
|
||||
#define DMA1 (DMA_BASE + 0x00000400U) /*!< DMA1 base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define DMA_INTF0(dmax) REG32((dmax) + 0x00000000U) /*!< DMA interrupt flag register 0 */
|
||||
#define DMA_INTF1(dmax) REG32((dmax) + 0x00000004U) /*!< DMA interrupt flag register 1 */
|
||||
#define DMA_INTC0(dmax) REG32((dmax) + 0x00000008U) /*!< DMA interrupt flag clear register 0 */
|
||||
#define DMA_INTC1(dmax) REG32((dmax) + 0x0000000CU) /*!< DMA interrupt flag clear register 1 */
|
||||
|
||||
#define DMA_CH0CTL(dmax) REG32((dmax) + 0x00000010U) /*!< DMA channel 0 control register */
|
||||
#define DMA_CH0CNT(dmax) REG32((dmax) + 0x00000014U) /*!< DMA channel 0 counter register */
|
||||
#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x00000018U) /*!< DMA channel 0 peripheral base address register */
|
||||
#define DMA_CH0M0ADDR(dmax) REG32((dmax) + 0x0000001CU) /*!< DMA channel 0 memory 0 base address register */
|
||||
#define DMA_CH0M1ADDR(dmax) REG32((dmax) + 0x00000020U) /*!< DMA channel 0 memory 1 base address register */
|
||||
#define DMA_CH0FCTL(dmax) REG32((dmax) + 0x00000024U) /*!< DMA channel 0 FIFO control register */
|
||||
|
||||
#define DMA_CH1CTL(dmax) REG32((dmax) + 0x00000028U) /*!< DMA channel 1 control register */
|
||||
#define DMA_CH1CNT(dmax) REG32((dmax) + 0x0000002CU) /*!< DMA channel 1 counter register */
|
||||
#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x00000030U) /*!< DMA channel 1 peripheral base address register */
|
||||
#define DMA_CH1M0ADDR(dmax) REG32((dmax) + 0x00000034U) /*!< DMA channel 1 memory 0 base address register */
|
||||
#define DMA_CH1M1ADDR(dmax) REG32((dmax) + 0x00000038U) /*!< DMA channel 1 memory 1 base address register */
|
||||
#define DMA_CH1FCTL(dmax) REG32((dmax) + 0x0000003CU) /*!< DMA channel 1 FIFO control register */
|
||||
|
||||
#define DMA_CH2CTL(dmax) REG32((dmax) + 0x00000040U) /*!< DMA channel 2 control register */
|
||||
#define DMA_CH2CNT(dmax) REG32((dmax) + 0x00000044U) /*!< DMA channel 2 counter register */
|
||||
#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x00000048U) /*!< DMA channel 2 peripheral base address register */
|
||||
#define DMA_CH2M0ADDR(dmax) REG32((dmax) + 0x0000004CU) /*!< DMA channel 2 memory 0 base address register */
|
||||
#define DMA_CH2M1ADDR(dmax) REG32((dmax) + 0x00000050U) /*!< DMA channel 2 memory 1 base address register */
|
||||
#define DMA_CH2FCTL(dmax) REG32((dmax) + 0x00000054U) /*!< DMA channel 2 FIFO control register */
|
||||
|
||||
#define DMA_CH3CTL(dmax) REG32((dmax) + 0x00000058U) /*!< DMA channel 3 control register */
|
||||
#define DMA_CH3CNT(dmax) REG32((dmax) + 0x0000005CU) /*!< DMA channel 3 counter register */
|
||||
#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x00000060U) /*!< DMA channel 3 peripheral base address register */
|
||||
#define DMA_CH3M0ADDR(dmax) REG32((dmax) + 0x00000064U) /*!< DMA channel 3 memory 0 base address register */
|
||||
#define DMA_CH3M1ADDR(dmax) REG32((dmax) + 0x00000068U) /*!< DMA channel 3 memory 1 base address register */
|
||||
#define DMA_CH3FCTL(dmax) REG32((dmax) + 0x0000006CU) /*!< DMA channel 3 FIFO control register */
|
||||
|
||||
#define DMA_CH4CTL(dmax) REG32((dmax) + 0x00000070U) /*!< DMA channel 4 control register */
|
||||
#define DMA_CH4CNT(dmax) REG32((dmax) + 0x00000074U) /*!< DMA channel 4 counter register */
|
||||
#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x00000078U) /*!< DMA channel 4 peripheral base address register */
|
||||
#define DMA_CH4M0ADDR(dmax) REG32((dmax) + 0x0000007CU) /*!< DMA channel 4 memory 0 base address register */
|
||||
#define DMA_CH4M1ADDR(dmax) REG32((dmax) + 0x00000080U) /*!< DMA channel 4 memory 1 base address register */
|
||||
#define DMA_CH4FCTL(dmax) REG32((dmax) + 0x00000084U) /*!< DMA channel 4 FIFO control register */
|
||||
|
||||
#define DMA_CH5CTL(dmax) REG32((dmax) + 0x00000088U) /*!< DMA channel 5 control register */
|
||||
#define DMA_CH5CNT(dmax) REG32((dmax) + 0x0000008CU) /*!< DMA channel 5 counter register */
|
||||
#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x00000090U) /*!< DMA channel 5 peripheral base address register */
|
||||
#define DMA_CH5M0ADDR(dmax) REG32((dmax) + 0x00000094U) /*!< DMA channel 5 memory 0 base address register */
|
||||
#define DMA_CH5M1ADDR(dmax) REG32((dmax) + 0x00000098U) /*!< DMA channel 5 memory 1 base address register */
|
||||
#define DMA_CH5FCTL(dmax) REG32((dmax) + 0x0000009CU) /*!< DMA channel 5 FIFO control register */
|
||||
|
||||
#define DMA_CH6CTL(dmax) REG32((dmax) + 0x000000A0U) /*!< DMA channel 6 control register */
|
||||
#define DMA_CH6CNT(dmax) REG32((dmax) + 0x000000A4U) /*!< DMA channel 6 counter register */
|
||||
#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x000000A8U) /*!< DMA channel 6 peripheral base address register */
|
||||
#define DMA_CH6M0ADDR(dmax) REG32((dmax) + 0x000000ACU) /*!< DMA channel 6 memory 0 base address register */
|
||||
#define DMA_CH6M1ADDR(dmax) REG32((dmax) + 0x000000B0U) /*!< DMA channel 6 memory 1 base address register */
|
||||
#define DMA_CH6FCTL(dmax) REG32((dmax) + 0x000000B4U) /*!< DMA channel 6 FIFO control register */
|
||||
|
||||
#define DMA_CH7CTL(dmax) REG32((dmax) + 0x000000B8U) /*!< DMA channel 7 control register */
|
||||
#define DMA_CH7CNT(dmax) REG32((dmax) + 0x000000BCU) /*!< DMA channel 7 counter register */
|
||||
#define DMA_CH7PADDR(dmax) REG32((dmax) + 0x000000C0U) /*!< DMA channel 7 peripheral base address register */
|
||||
#define DMA_CH7M0ADDR(dmax) REG32((dmax) + 0x000000C4U) /*!< DMA channel 7 memory 0 base address register */
|
||||
#define DMA_CH7M1ADDR(dmax) REG32((dmax) + 0x000000C8U) /*!< DMA channel 7 memory 1 base address register */
|
||||
#define DMA_CH7FCTL(dmax) REG32((dmax) + 0x000000CCU) /*!< DMA channel 7 FIFO control register */
|
||||
|
||||
/* bits definitions */
|
||||
/* DMA_INTF */
|
||||
#define DMA_INTF_FEEIF BIT(0) /*!< FIFO error and exception flag */
|
||||
#define DMA_INTF_SDEIF BIT(2) /*!< single data mode exception flag */
|
||||
#define DMA_INTF_TAEIF BIT(3) /*!< transfer access error flag */
|
||||
#define DMA_INTF_HTFIF BIT(4) /*!< half transfer finish flag */
|
||||
#define DMA_INTF_FTFIF BIT(5) /*!< full transger finish flag */
|
||||
|
||||
/* DMA_INTC */
|
||||
#define DMA_INTC_FEEIFC BIT(0) /*!< clear FIFO error and exception flag */
|
||||
#define DMA_INTC_SDEIFC BIT(2) /*!< clear single data mode exception flag */
|
||||
#define DMA_INTC_TAEIFC BIT(3) /*!< clear single data mode exception flag */
|
||||
#define DMA_INTC_HTFIFC BIT(4) /*!< clear half transfer finish flag */
|
||||
#define DMA_INTC_FTFIFC BIT(5) /*!< clear full transger finish flag */
|
||||
|
||||
/* DMA_CHxCTL,x=0..7 */
|
||||
#define DMA_CHXCTL_CHEN BIT(0) /*!< channel x enable */
|
||||
#define DMA_CHXCTL_SDEIE BIT(1) /*!< enable bit for channel x single data mode exception interrupt */
|
||||
#define DMA_CHXCTL_TAEIE BIT(2) /*!< enable bit for channel x tranfer access error interrupt */
|
||||
#define DMA_CHXCTL_HTFIE BIT(3) /*!< enable bit for channel x half transfer finish interrupt */
|
||||
#define DMA_CHXCTL_FTFIE BIT(4) /*!< enable bit for channel x full transfer finish interrupt */
|
||||
#define DMA_CHXCTL_TFCS BIT(5) /*!< transfer flow controller select */
|
||||
#define DMA_CHXCTL_TM BITS(6,7) /*!< transfer mode */
|
||||
#define DMA_CHXCTL_CMEN BIT(8) /*!< circulation mode */
|
||||
#define DMA_CHXCTL_PNAGA BIT(9) /*!< next address generation algorithm of peripheral */
|
||||
#define DMA_CHXCTL_MNAGA BIT(10) /*!< next address generation algorithm of memory */
|
||||
#define DMA_CHXCTL_PWIDTH BITS(11,12) /*!< transfer width of peipheral */
|
||||
#define DMA_CHXCTL_MWIDTH BITS(13,14) /*!< transfer width of memory */
|
||||
#define DMA_CHXCTL_PAIF BIT(15) /*!< peripheral address increment fixed */
|
||||
#define DMA_CHXCTL_PRIO BITS(16,17) /*!< priority level */
|
||||
#define DMA_CHXCTL_SBMEN BIT(18) /*!< switch-buffer mode enable */
|
||||
#define DMA_CHXCTL_MBS BIT(19) /*!< memory buffer select */
|
||||
#define DMA_CHXCTL_PBURST BITS(21,22) /*!< transfer burst type of peripheral */
|
||||
#define DMA_CHXCTL_MBURST BITS(23,24) /*!< transfer burst type of memory */
|
||||
#define DMA_CHXCTL_PERIEN BITS(25,27) /*!< peripheral enable */
|
||||
|
||||
/* DMA_CHxCNT,x=0..7 */
|
||||
#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */
|
||||
|
||||
/* DMA_CHxPADDR,x=0..7 */
|
||||
#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */
|
||||
|
||||
/* DMA_CHxM0ADDR,x=0..7 */
|
||||
#define DMA_CHXM0ADDR_M0ADDR BITS(0,31) /*!< memory 0 base address */
|
||||
|
||||
/* DMA_CHxM1ADDR,x=0..7 */
|
||||
#define DMA_CHXM1ADDR_M0ADDR BITS(0,31) /*!< memory 1 base address */
|
||||
|
||||
/* DMA_CHxFCTL,x=0..7 */
|
||||
#define DMA_CHXFCTL_FCCV BITS(0,1) /*!< FIFO counter critical value */
|
||||
#define DMA_CHXFCTL_MDMEN BIT(2) /*!< multi-data mode enable */
|
||||
#define DMA_CHXFCTL_FCNT BITS(3,5) /*!< FIFO counter */
|
||||
#define DMA_CHXFCTL_FEEIE BIT(7) /*!< FIFO exception interrupt enable */
|
||||
|
||||
/* constants definitions */
|
||||
/* DMA channel select */
|
||||
typedef enum
|
||||
{
|
||||
DMA_CH0 = 0, /*!< DMA Channel 0 */
|
||||
DMA_CH1, /*!< DMA Channel 1 */
|
||||
DMA_CH2, /*!< DMA Channel 2 */
|
||||
DMA_CH3, /*!< DMA Channel 3 */
|
||||
DMA_CH4, /*!< DMA Channel 4 */
|
||||
DMA_CH5, /*!< DMA Channel 5 */
|
||||
DMA_CH6, /*!< DMA Channel 6 */
|
||||
DMA_CH7 /*!< DMA Channel 7 */
|
||||
} dma_channel_enum;
|
||||
|
||||
/* DMA peripheral select */
|
||||
typedef enum
|
||||
{
|
||||
DMA_SUBPERI0 = 0, /*!< DMA Peripheral 0 */
|
||||
DMA_SUBPERI1, /*!< DMA Peripheral 1 */
|
||||
DMA_SUBPERI2, /*!< DMA Peripheral 2 */
|
||||
DMA_SUBPERI3, /*!< DMA Peripheral 3 */
|
||||
DMA_SUBPERI4, /*!< DMA Peripheral 4 */
|
||||
DMA_SUBPERI5, /*!< DMA Peripheral 5 */
|
||||
DMA_SUBPERI6, /*!< DMA Peripheral 6 */
|
||||
DMA_SUBPERI7 /*!< DMA Peripheral 7 */
|
||||
} dma_subperipheral_enum;
|
||||
|
||||
/* DMA multidata mode initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t periph_addr; /*!< peripheral base address */
|
||||
uint32_t periph_width; /*!< transfer data size of peripheral */
|
||||
uint32_t periph_inc; /*!< peripheral increasing mode */
|
||||
|
||||
uint32_t memory0_addr; /*!< memory 0 base address */
|
||||
uint32_t memory_width; /*!< transfer data size of memory */
|
||||
uint32_t memory_inc; /*!< memory increasing mode */
|
||||
|
||||
uint32_t memory_burst_width; /*!< multi data mode enable */
|
||||
uint32_t periph_burst_width; /*!< multi data mode enable */
|
||||
uint32_t critical_value; /*!< FIFO critical */
|
||||
|
||||
uint32_t circular_mode; /*!< DMA circular mode */
|
||||
uint32_t direction; /*!< channel data transfer direction */
|
||||
uint32_t number; /*!< channel transfer number */
|
||||
uint32_t priority; /*!< channel priority level */
|
||||
}dma_multi_data_parameter_struct;
|
||||
|
||||
/* DMA singledata mode initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t periph_addr; /*!< peripheral base address */
|
||||
uint32_t periph_inc; /*!< peripheral increasing mode */
|
||||
|
||||
uint32_t memory0_addr; /*!< memory 0 base address */
|
||||
uint32_t memory_inc; /*!< memory increasing mode */
|
||||
|
||||
uint32_t periph_memory_width; /*!< transfer data size of peripheral */
|
||||
|
||||
uint32_t circular_mode; /*!< DMA circular mode */
|
||||
uint32_t direction; /*!< channel data transfer direction */
|
||||
uint32_t number; /*!< channel transfer number */
|
||||
uint32_t priority; /*!< channel priority level */
|
||||
} dma_single_data_parameter_struct;
|
||||
|
||||
#define DMA_FLAG_ADD(flag,channel) ((uint32_t)((flag)<<((((uint32_t)(channel)*6U))+((uint32_t)(((uint32_t)(channel)) >> 1U)&0x01U)*4U))) /*!< DMA channel flag shift */
|
||||
|
||||
/* DMA_register address */
|
||||
#define DMA_CHCTL(dma,channel) REG32(((dma) + 0x10U) + 0x18U*(channel)) /*!< the address of DMA channel CHXCTL register */
|
||||
#define DMA_CHCNT(dma,channel) REG32(((dma) + 0x14U) + 0x18U*(channel)) /*!< the address of DMA channel CHXCNT register */
|
||||
#define DMA_CHPADDR(dma,channel) REG32(((dma) + 0x18U) + 0x18U*(channel)) /*!< the address of DMA channel CHXPADDR register */
|
||||
#define DMA_CHM0ADDR(dma,channel) REG32(((dma) + 0x1CU) + 0x18U*(channel)) /*!< the address of DMA channel CHXM0ADDR register */
|
||||
#define DMA_CHM1ADDR(dma,channel) REG32(((dma) + 0x20U) + 0x18U*(channel)) /*!< the address of DMA channel CHXM1ADDR register */
|
||||
#define DMA_CHFCTL(dma,channel) REG32(((dma) + 0x24U) + 0x18U*(channel)) /*!< the address of DMA channel CHXMADDR register */
|
||||
|
||||
/* peripheral select */
|
||||
#define CHCTL_PERIEN(regval) (BITS(25,27) & ((uint32_t)(regval) << 25))
|
||||
#define DMA_PERIPH_0_SELECT CHCTL_PERIEN(0) /*!< peripheral 0 select */
|
||||
#define DMA_PERIPH_1_SELECT CHCTL_PERIEN(1) /*!< peripheral 1 select */
|
||||
#define DMA_PERIPH_2_SELECT CHCTL_PERIEN(2) /*!< peripheral 2 select */
|
||||
#define DMA_PERIPH_3_SELECT CHCTL_PERIEN(3) /*!< peripheral 3 select */
|
||||
#define DMA_PERIPH_4_SELECT CHCTL_PERIEN(4) /*!< peripheral 4 select */
|
||||
#define DMA_PERIPH_5_SELECT CHCTL_PERIEN(5) /*!< peripheral 5 select */
|
||||
#define DMA_PERIPH_6_SELECT CHCTL_PERIEN(6) /*!< peripheral 6 select */
|
||||
#define DMA_PERIPH_7_SELECT CHCTL_PERIEN(7) /*!< peripheral 7 select */
|
||||
|
||||
/* burst type of memory */
|
||||
#define CHCTL_MBURST(regval) (BITS(23,24) & ((uint32_t)(regval) << 23))
|
||||
#define DMA_MEMORY_BURST_SINGLE CHCTL_MBURST(0) /*!< single burst */
|
||||
#define DMA_MEMORY_BURST_4_BEAT CHCTL_MBURST(1) /*!< 4-beat burst */
|
||||
#define DMA_MEMORY_BURST_8_BEAT CHCTL_MBURST(2) /*!< 8-beat burst */
|
||||
#define DMA_MEMORY_BURST_16_BEAT CHCTL_MBURST(3) /*!< 16-beat burst */
|
||||
|
||||
/* burst type of peripheral */
|
||||
#define CHCTL_PBURST(regval) (BITS(21,22) & ((uint32_t)(regval) << 21))
|
||||
#define DMA_PERIPH_BURST_SINGLE CHCTL_PBURST(0) /*!< single burst */
|
||||
#define DMA_PERIPH_BURST_4_BEAT CHCTL_PBURST(1) /*!< 4-beat burst */
|
||||
#define DMA_PERIPH_BURST_8_BEAT CHCTL_PBURST(2) /*!< 8-beat burst */
|
||||
#define DMA_PERIPH_BURST_16_BEAT CHCTL_PBURST(3) /*!< 16-beat burst */
|
||||
|
||||
/* channel priority level */
|
||||
#define CHCTL_PRIO(regval) (BITS(16,17) & ((uint32_t)(regval) << 16))
|
||||
#define DMA_PRIORITY_LOW CHCTL_PRIO(0) /*!< low priority */
|
||||
#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1) /*!< medium priority */
|
||||
#define DMA_PRIORITY_HIGH CHCTL_PRIO(2) /*!< high priority */
|
||||
#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3) /*!< ultra high priority */
|
||||
|
||||
/* transfer data width of memory */
|
||||
#define CHCTL_MWIDTH(regval) (BITS(13,14) & ((uint32_t)(regval) << 13))
|
||||
#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0) /*!< transfer data width of memory is 8-bit */
|
||||
#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1) /*!< transfer data width of memory is 16-bit */
|
||||
#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2) /*!< transfer data width of memory is 32-bit */
|
||||
|
||||
/* transfer data width of peripheral */
|
||||
#define CHCTL_PWIDTH(regval) (BITS(11,12) & ((uint32_t)(regval) << 11))
|
||||
#define DMA_PERIPH_WIDTH_8BIT CHCTL_PWIDTH(0) /*!< transfer data width of peripheral is 8-bit */
|
||||
#define DMA_PERIPH_WIDTH_16BIT CHCTL_PWIDTH(1) /*!< transfer data width of peripheral is 16-bit */
|
||||
#define DMA_PERIPH_WIDTH_32BIT CHCTL_PWIDTH(2) /*!< transfer data width of peripheral is 32-bit */
|
||||
|
||||
/* channel transfer mode */
|
||||
#define CHCTL_TM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
|
||||
#define DMA_PERIPH_TO_MEMORY CHCTL_TM(0) /*!< read from peripheral and write to memory */
|
||||
#define DMA_MEMORY_TO_PERIPH CHCTL_TM(1) /*!< read from memory and write to peripheral */
|
||||
#define DMA_MEMORY_TO_MEMORY CHCTL_TM(2) /*!< read from memory and write to memory */
|
||||
|
||||
/* FIFO counter critical value */
|
||||
#define CHFCTL_FCCV(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define DMA_FIFO_1_WORD CHFCTL_FCCV(0) /*!< critical value 1 word */
|
||||
#define DMA_FIFO_2_WORD CHFCTL_FCCV(1) /*!< critical value 2 word */
|
||||
#define DMA_FIFO_3_WORD CHFCTL_FCCV(2) /*!< critical value 3 word */
|
||||
#define DMA_FIFO_4_WORD CHFCTL_FCCV(3) /*!< critical value 4 word */
|
||||
|
||||
/* memory select */
|
||||
#define DMA_MEMORY_0 ((uint32_t)0x00000000U) /*!< select memory 0 */
|
||||
#define DMA_MEMORY_1 ((uint32_t)0x00000001U) /*!< select memory 1 */
|
||||
|
||||
/* DMA circular mode */
|
||||
#define DMA_CIRCULAR_MODE_ENABLE ((uint32_t)0x00000000U) /*!< circular mode enable */
|
||||
#define DMA_CIRCULAR_MODE_DISABLE ((uint32_t)0x00000001U) /*!< circular mode disable */
|
||||
|
||||
/* DMA flow controller select */
|
||||
#define DMA_FLOW_CONTROLLER_DMA ((uint32_t)0x00000000U) /*!< DMA is the flow controler */
|
||||
#define DMA_FLOW_CONTROLLER_PERI ((uint32_t)0x00000001U) /*!< peripheral is the flow controler */
|
||||
|
||||
/* peripheral increasing mode */
|
||||
#define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000000U) /*!< next address of peripheral is increasing address mode */
|
||||
#define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000001U) /*!< next address of peripheral is fixed address mode */
|
||||
#define DMA_PERIPH_INCREASE_FIX ((uint32_t)0x00000002U) /*!< next address of peripheral is increasing fixed */
|
||||
|
||||
/* memory increasing mode */
|
||||
#define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000000U) /*!< next address of memory is increasing address mode */
|
||||
#define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000001U) /*!< next address of memory is fixed address mode */
|
||||
|
||||
/* FIFO status */
|
||||
#define DMA_FIFO_STATUS_NODATA ((uint32_t)0x00000000U) /*!< the data in the FIFO less than 1 word */
|
||||
#define DMA_FIFO_STATUS_1_WORD ((uint32_t)0x00000001U) /*!< the data in the FIFO more than 1 word, less than 2 words */
|
||||
#define DMA_FIFO_STATUS_2_WORD ((uint32_t)0x00000002U) /*!< the data in the FIFO more than 2 word, less than 3 words */
|
||||
#define DMA_FIFO_STATUS_3_WORD ((uint32_t)0x00000003U) /*!< the data in the FIFO more than 3 word, less than 4 words */
|
||||
#define DMA_FIFO_STATUS_EMPTY ((uint32_t)0x00000004U) /*!< the data in the FIFO is empty */
|
||||
#define DMA_FIFO_STATUS_FULL ((uint32_t)0x00000005U) /*!< the data in the FIFO is full */
|
||||
|
||||
/* DMA reset value */
|
||||
#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */
|
||||
#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */
|
||||
#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */
|
||||
#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */
|
||||
#define DMA_CHINTF_RESET_VALUE ((uint32_t)0x0000003DU) /*!< clear DMA channel CHXINTFS register */
|
||||
#define DMA_CHFCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXFCTL register */
|
||||
|
||||
/* DMA_INTF register */
|
||||
/* interrupt flag bits */
|
||||
#define DMA_INT_FLAG_FEE DMA_INTF_FEEIF /*!< FIFO error and exception flag */
|
||||
#define DMA_INT_FLAG_SDE DMA_INTF_SDEIF /*!< single data mode exception flag */
|
||||
#define DMA_INT_FLAG_TAE DMA_INTF_TAEIF /*!< transfer access error flag */
|
||||
#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag */
|
||||
#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag */
|
||||
|
||||
/* flag bits */
|
||||
#define DMA_FLAG_FEE DMA_INTF_FEEIF /*!< FIFO error and exception flag */
|
||||
#define DMA_FLAG_SDE DMA_INTF_SDEIF /*!< single data mode exception flag */
|
||||
#define DMA_FLAG_TAE DMA_INTF_TAEIF /*!< transfer access error flag */
|
||||
#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag */
|
||||
#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag */
|
||||
|
||||
|
||||
/* function declarations */
|
||||
/* DMA deinitialization and initialization functions */
|
||||
/* deinitialize DMA a channel registers */
|
||||
void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* initialize the DMA single data mode parameters struct with the default values */
|
||||
void dma_single_data_para_struct_init(dma_single_data_parameter_struct* init_struct);
|
||||
/* initialize the DMA multi data mode parameters struct with the default values */
|
||||
void dma_multi_data_para_struct_init(dma_multi_data_parameter_struct* init_struct);
|
||||
/* DMA single data mode initialize */
|
||||
void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_single_data_parameter_struct* init_struct);
|
||||
/* DMA multi data mode initialize */
|
||||
void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_multi_data_parameter_struct* init_struct);
|
||||
|
||||
/* DMA configuration functions */
|
||||
/* set DMA peripheral base address */
|
||||
void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
|
||||
/* set DMA Memory base address */
|
||||
void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t memory_flag, uint32_t address);
|
||||
|
||||
/* set the number of remaining data to be transferred by the DMA */
|
||||
void dma_transfer_number_config(uint32_t dma_periph,dma_channel_enum channelx, uint32_t number);
|
||||
/* get the number of remaining data to be transferred by the DMA */
|
||||
uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
|
||||
/* configure priority level of DMA channel */
|
||||
void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority);
|
||||
|
||||
/* configure transfer burst beats of memory */
|
||||
void dma_memory_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mbeat);
|
||||
/* configure transfer burst beats of peripheral */
|
||||
void dma_periph_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pbeat);
|
||||
/* configure transfer data size of memory */
|
||||
void dma_memory_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t msize);
|
||||
/* configure transfer data size of peripheral */
|
||||
void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t psize);
|
||||
|
||||
/* configure next address increasement algorithm of memory */
|
||||
void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm);
|
||||
/* configure next address increasement algorithm of peripheral */
|
||||
void dma_peripheral_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm);
|
||||
|
||||
/* enable DMA circulation mode */
|
||||
void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* disable DMA circulation mode */
|
||||
void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* enable DMA channel */
|
||||
void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* disable DMA channel */
|
||||
void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
|
||||
/* configure the direction of data transfer on the channel */
|
||||
void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction);
|
||||
|
||||
/* DMA switch buffer mode config */
|
||||
void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t memory1_addr, uint32_t memory_select);
|
||||
/* DMA using memory get */
|
||||
uint32_t dma_using_memory_get(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
|
||||
/* DMA channel peripheral select */
|
||||
void dma_channel_subperipheral_select(uint32_t dma_periph, dma_channel_enum channelx, dma_subperipheral_enum sub_periph);
|
||||
/* DMA flow controller configure */
|
||||
void dma_flow_controller_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t controller);
|
||||
/* DMA flow controller enable */
|
||||
void dma_switch_buffer_mode_enable(uint32_t dma_periph, dma_channel_enum channelx, ControlStatus newvalue);
|
||||
/* DMA FIFO status get */
|
||||
uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
|
||||
/* flag and interrupt functions */
|
||||
/* check DMA flag is set or not */
|
||||
FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
||||
/* clear DMA a channel flag */
|
||||
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
||||
/* enable DMA interrupt */
|
||||
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
|
||||
/* disable DMA interrupt */
|
||||
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
|
||||
/* check DMA flag is set or not */
|
||||
FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt);
|
||||
/* clear DMA a channel flag */
|
||||
void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt);
|
||||
|
||||
#endif /* GD32F4XX_DMA_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,814 @@
|
|||
/*!
|
||||
\file gd32f4xx_exmc.h
|
||||
\brief definitions for the EXMC
|
||||
|
||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||
\version 2022-06-08, V3.0.1, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F4XX_EXMC_H
|
||||
#define GD32F4XX_EXMC_H
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
|
||||
/* EXMC definitions */
|
||||
#define EXMC (EXMC_BASE) /*!< EXMC register base address */
|
||||
#define EXMC_NOR_PSRAM (EXMC_BASE - 0x40000000) /*!< EXMC NOR/PSRAM base address */
|
||||
#define EXMC_NAND (EXMC_BASE - 0x30000000) /*!< EXMC NAND base address */
|
||||
#define EXMC_PCCARD (EXMC_BASE - 0x10000000) /*!< EXMC PC card base address */
|
||||
#define EXMC_SDRAM (EXMC_BASE + 0x20000000) /*!< EXMC SDRAM base address */
|
||||
|
||||
/* registers definitions */
|
||||
/* NOR/PSRAM */
|
||||
#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register for region0 */
|
||||
#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register for region0 */
|
||||
#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register for region0 */
|
||||
|
||||
#define EXMC_SNCTL1 REG32(EXMC + 0x08U) /*!< EXMC SRAM/NOR flash control register for region1 */
|
||||
#define EXMC_SNTCFG1 REG32(EXMC + 0x0CU) /*!< EXMC SRAM/NOR flash timing configuration register for region1 */
|
||||
#define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU) /*!< EXMC SRAM/NOR flash write timing configuration register for region1 */
|
||||
|
||||
#define EXMC_SNCTL2 REG32(EXMC + 0x10U) /*!< EXMC SRAM/NOR flash control register for region2 */
|
||||
#define EXMC_SNTCFG2 REG32(EXMC + 0x14U) /*!< EXMC SRAM/NOR flash timing configuration register for region2 */
|
||||
#define EXMC_SNWTCFG2 REG32(EXMC + 0x114U) /*!< EXMC SRAM/NOR flash write timing configuration register for region2 */
|
||||
|
||||
#define EXMC_SNCTL3 REG32(EXMC + 0x18U) /*!< EXMC SRAM/NOR flash control register for region3 */
|
||||
#define EXMC_SNTCFG3 REG32(EXMC + 0x1CU) /*!< EXMC SRAM/NOR flash timing configuration register for region3 */
|
||||
#define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU) /*!< EXMC SRAM/NOR flash write timing configuration register for region3 */
|
||||
|
||||
/* NAND/PC card */
|
||||
#define EXMC_NPCTL1 REG32(EXMC + 0x60U) /*!< EXMC NAND/PC card control register for bank1 */
|
||||
#define EXMC_NPINTEN1 REG32(EXMC + 0x64U) /*!< EXMC NAND/PC card interrupt enable register for bank1 */
|
||||
#define EXMC_NPCTCFG1 REG32(EXMC + 0x68U) /*!< EXMC NAND/PC card common space timing configuration register for bank1 */
|
||||
#define EXMC_NPATCFG1 REG32(EXMC + 0x6CU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank1 */
|
||||
#define EXMC_NECC1 REG32(EXMC + 0x74U) /*!< EXMC NAND ECC register */
|
||||
|
||||
#define EXMC_NPCTL2 REG32(EXMC + 0x80U) /*!< EXMC NAND/PC card control register for bank2 */
|
||||
#define EXMC_NPINTEN2 REG32(EXMC + 0x84U) /*!< EXMC NAND/PC card interrupt enable register for bank2 */
|
||||
#define EXMC_NPCTCFG2 REG32(EXMC + 0x88U) /*!< EXMC NAND/PC card common space timing configuration register for bank2 */
|
||||
#define EXMC_NPATCFG2 REG32(EXMC + 0x8CU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank2 */
|
||||
#define EXMC_NECC2 REG32(EXMC + 0x94U) /*!< EXMC NAND ECC register */
|
||||
|
||||
#define EXMC_NPCTL3 REG32(EXMC + 0xA0U) /*!< EXMC NAND/PC card control register for bank3 */
|
||||
#define EXMC_NPINTEN3 REG32(EXMC + 0xA4U) /*!< EXMC NAND/PC card interrupt enable register for bank3 */
|
||||
#define EXMC_NPCTCFG3 REG32(EXMC + 0xA8U) /*!< EXMC NAND/PC card common space timing configuration register for bank3 */
|
||||
#define EXMC_NPATCFG3 REG32(EXMC + 0xACU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank3 */
|
||||
#define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U) /*!< EXMC PC card I/O space timing configuration register for bank3 */
|
||||
|
||||
/* SDRAM */
|
||||
#define EXMC_SDCTL0 REG32(EXMC + 0x140U) /*!< EXMC SDRAM control register for device0 */
|
||||
#define EXMC_SDTCFG0 REG32(EXMC + 0x148U) /*!< EXMC SDRAM timing configuration register register for device0 */
|
||||
|
||||
#define EXMC_SDCTL1 REG32(EXMC + 0x144U) /*!< EXMC SDRAM control register for device1 */
|
||||
#define EXMC_SDTCFG1 REG32(EXMC + 0x14CU) /*!< EXMC SDRAM timing configuration register register for device1 */
|
||||
|
||||
#define EXMC_SDCMD REG32(EXMC + 0x150U) /*!< EXMC SDRAM command register */
|
||||
#define EXMC_SDARI REG32(EXMC + 0x154U) /*!< EXMC SDRAM auto-refresh interval register */
|
||||
#define EXMC_SDSTAT REG32(EXMC + 0x158U) /*!< EXMC SDRAM status register */
|
||||
#define EXMC_SDRSCTL REG32(EXMC + 0x180U) /*!< EXMC SDRAM read sample control register */
|
||||
|
||||
/* SQPI PSRAM */
|
||||
#define EXMC_SINIT REG32(EXMC + 0x310U) /*!< EXMC SPI initialization register */
|
||||
#define EXMC_SRCMD REG32(EXMC + 0x320U) /*!< EXMC SPI read command register */
|
||||
#define EXMC_SWCMD REG32(EXMC + 0x330U) /*!< EXMC SPI write command register */
|
||||
#define EXMC_SIDL REG32(EXMC + 0x340U) /*!< EXMC SPI ID low register */
|
||||
#define EXMC_SIDH REG32(EXMC + 0x350U) /*!< EXMC SPI ID high register */
|
||||
|
||||
/* bits definitions */
|
||||
/* EXMC_SNCTLx,x=0..3 */
|
||||
#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */
|
||||
#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing enable */
|
||||
#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */
|
||||
#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */
|
||||
#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */
|
||||
#define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */
|
||||
#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */
|
||||
#define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */
|
||||
#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */
|
||||
#define EXMC_SNCTL_WEN BIT(12) /*!< write enable */
|
||||
#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */
|
||||
#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */
|
||||
#define EXMC_SNCTL_ASYNCWTEN BIT(15) /*!< asynchronous wait enable */
|
||||
#define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */
|
||||
#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write configuration */
|
||||
#define EXMC_SNCTL_CCK BIT(20) /*!< consecutive clock configuration */
|
||||
|
||||
/* EXMC_SNTCFGx,x=0..3 */
|
||||
#define EXMC_SNTCFG_ASET BITS(0,3) /*!< asynchronous address setup time */
|
||||
#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< asynchronous address hold time */
|
||||
#define EXMC_SNTCFG_DSET BITS(8,15) /*!< asynchronous data setup time */
|
||||
#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */
|
||||
#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */
|
||||
#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< synchronous data latency for NOR flash */
|
||||
#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */
|
||||
|
||||
/* EXMC_SNWTCFGx,x=0..3 */
|
||||
#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< asynchronous address setup time */
|
||||
#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< asynchronous address hold time */
|
||||
#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< asynchronous data setup time */
|
||||
#define EXMC_SNWTCFG_WBUSLAT BITS(16,19) /*!< bus latency */
|
||||
#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */
|
||||
|
||||
/* EXMC_NPCTLx,x=1..3 */
|
||||
#define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */
|
||||
#define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */
|
||||
#define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */
|
||||
#define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */
|
||||
#define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */
|
||||
#define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */
|
||||
#define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */
|
||||
#define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */
|
||||
|
||||
/* EXMC_NPINTENx,x=1..3 */
|
||||
#define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */
|
||||
#define EXMC_NPINTEN_INTHS BIT(1) /*!< interrupt high-level status */
|
||||
#define EXMC_NPINTEN_INTFS BIT(2) /*!< interrupt falling edge status */
|
||||
#define EXMC_NPINTEN_INTREN BIT(3) /*!< interrupt rising edge detection enable */
|
||||
#define EXMC_NPINTEN_INTHEN BIT(4) /*!< interrupt high-level detection enable */
|
||||
#define EXMC_NPINTEN_INTFEN BIT(5) /*!< interrupt falling edge detection enable */
|
||||
#define EXMC_NPINTEN_FFEPT BIT(6) /*!< FIFO empty flag */
|
||||
|
||||
/* EXMC_NPCTCFGx,x=1..3 */
|
||||
#define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory setup time */
|
||||
#define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory wait time */
|
||||
#define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory hold time */
|
||||
#define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory data bus HiZ time */
|
||||
|
||||
/* EXMC_NPATCFGx,x=1..3 */
|
||||
#define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory setup time */
|
||||
#define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory wait time */
|
||||
#define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory hold time */
|
||||
#define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory data bus HiZ time */
|
||||
|
||||
/* EXMC_PIOTCFG3 */
|
||||
#define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space setup time */
|
||||
#define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space wait time */
|
||||
#define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space hold time */
|
||||
#define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space data bus HiZ time */
|
||||
|
||||
/* EXMC_NECCx,x=1..2 */
|
||||
#define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */
|
||||
|
||||
/* EXMC_SDCTLx,x=0..1 */
|
||||
#define EXMC_SDCTL_CAW BITS(0,1) /*!< column address bit width */
|
||||
#define EXMC_SDCTL_RAW BITS(2,3) /*!< row address bit width */
|
||||
#define EXMC_SDCTL_SDW BITS(4,5) /*!< SDRAM data bus width */
|
||||
#define EXMC_SDCTL_NBK BIT(6) /*!< number of banks */
|
||||
#define EXMC_SDCTL_CL BIT(7,8) /*!< CAS Latency */
|
||||
#define EXMC_SDCTL_WPEN BIT(9) /*!< write protection enable */
|
||||
#define EXMC_SDCTL_SDCLK BITS(10,11) /*!< SDRAM clock configuration */
|
||||
#define EXMC_SDCTL_BRSTRD BIT(12) /*!< burst read enable */
|
||||
#define EXMC_SDCTL_PIPED BITS(13,14) /*!< pipeline delay */
|
||||
|
||||
/* EXMC_SDTCFGx,x=0..1 */
|
||||
#define EXMC_SDTCFG_LMRD BITS(0,3) /*!< load mode register delay */
|
||||
#define EXMC_SDTCFG_XSRD BITS(4,7) /*!< exit self-refresh delay */
|
||||
#define EXMC_SDTCFG_RASD BITS(8,11) /*!< row address select delay */
|
||||
#define EXMC_SDTCFG_ARFD BITS(12,15) /*!< auto refresh delay */
|
||||
#define EXMC_SDTCFG_WRD BITS(16,19) /*!< write recovery delay */
|
||||
#define EXMC_SDTCFG_RPD BITS(20,23) /*!< row precharge delay */
|
||||
#define EXMC_SDTCFG_RCD BITS(24,27) /*!< row to column delay */
|
||||
|
||||
/* EXMC_SDCMD */
|
||||
#define EXMC_SDCMD_CMD BITS(0,2) /*!< command */
|
||||
#define EXMC_SDCMD_DS1 BIT(3) /*!< select device1 */
|
||||
#define EXMC_SDCMD_DS0 BIT(4) /*!< select device0 */
|
||||
#define EXMC_SDCMD_NARF BITS(5,8) /*!< number of successive auto-refresh */
|
||||
#define EXMC_SDCMD_MRC BITS(9,21) /*!< mode register content */
|
||||
|
||||
/* EXMC_SDARI */
|
||||
#define EXMC_SDARI_REC BIT(0) /*!< refresh error flag clear */
|
||||
#define EXMC_SDARI_ARINTV BITS(1,13) /*!< auto-refresh interval */
|
||||
#define EXMC_SDARI_REIE BIT(14) /*!< refresh error interrupt enable */
|
||||
|
||||
/* EXMC_SDSTAT */
|
||||
#define EXMC_SDSDAT_REIF BIT(0) /*!< refresh error interrupt flag */
|
||||
#define EXMC_SDSDAT_STA0 BITS(1,2) /*!< device0 status */
|
||||
#define EXMC_SDSDAT_STA1 BITS(3,4) /*!< device1 status */
|
||||
#define EXMC_SDSDAT_NRDY BIT(5) /*!< not ready status */
|
||||
|
||||
/* EXMC_SDRSCTL */
|
||||
#define EXMC_SDRSCTL_RSEN BIT(0) /*!< read sample enable */
|
||||
#define EXMC_SDRSCTL_SSCR BIT(1) /*!< select sample cycle of read data */
|
||||
#define EXMC_SDRSCTL_SDSC BITS(4,7) /*!< select the delayed sample clock of read data */
|
||||
|
||||
/* EXMC_SINIT */
|
||||
#define EXMC_SINIT_CMDBIT BITS(16,17) /*!< bit number of SPI PSRAM command phase */
|
||||
#define EXMC_SINIT_ARDBIT BITS(24,28) /*!< bit number of SPI PSRAM address phase */
|
||||
#define EXMC_SINIT_IDL BITS(29,30) /*!< SPI PSRAM ID length */
|
||||
#define EXMC_SINIT_POL BIT(31) /*!< read data sample polarity */
|
||||
|
||||
/* EXMC_SRCMD */
|
||||
#define EXMC_SRCMD_RCMD BITS(0,15) /*!< SPI read command for AHB read transfer */
|
||||
#define EXMC_SRCMD_RWAITCYCLE BITS(16,19) /*!< SPI read wait cycle number after address phase */
|
||||
#define EXMC_SRCMD_RMODE BITS(20,21) /*!< SPI PSRAM read command mode */
|
||||
#define EXMC_SRCMD_RDID BIT(31) /*!< send SPI read ID command */
|
||||
|
||||
/* EXMC_SWCMD */
|
||||
#define EXMC_SWCMD_WCMD BITS(0,15) /*!< SPI write command for AHB write transfer */
|
||||
#define EXMC_SWCMD_WWAITCYCLE BITS(16,19) /*!< SPI write wait cycle number after address phase */
|
||||
#define EXMC_SWCMD_WMODE BITS(20,21) /*!< SPI PSRAM write command mode */
|
||||
#define EXMC_SWCMD_SC BIT(31) /*!< send SPI special command */
|
||||
|
||||
/* EXMC_SIDL */
|
||||
#define EXMC_SIDL_SIDL BITS(0,31) /*!< ID low data saved for SPI read ID command */
|
||||
|
||||
/* EXMC_SIDH */
|
||||
#define EXMC_SIDL_SIDH BITS(0,31) /*!< ID high Data saved for SPI read ID command */
|
||||
|
||||
/* constants definitions */
|
||||
/* EXMC NOR/SRAM timing initialize structure */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t asyn_access_mode; /*!< asynchronous access mode */
|
||||
uint32_t syn_data_latency; /*!< configure the data latency */
|
||||
uint32_t syn_clk_division; /*!< configure the clock divide ratio */
|
||||
uint32_t bus_latency; /*!< configure the bus latency */
|
||||
uint32_t asyn_data_setuptime; /*!< configure the data setup time, asynchronous access mode valid */
|
||||
uint32_t asyn_address_holdtime; /*!< configure the address hold time, asynchronous access mode valid */
|
||||
uint32_t asyn_address_setuptime; /*!< configure the address setup time, asynchronous access mode valid */
|
||||
}exmc_norsram_timing_parameter_struct;
|
||||
|
||||
/* EXMC NOR/SRAM initialize structure */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */
|
||||
uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */
|
||||
uint32_t extended_mode; /*!< enable or disable the extended mode */
|
||||
uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */
|
||||
uint32_t nwait_signal; /*!< enable or disable the NWAIT signal while in synchronous bust mode */
|
||||
uint32_t memory_write; /*!< enable or disable the write operation */
|
||||
uint32_t nwait_config; /*!< NWAIT signal configuration */
|
||||
uint32_t wrap_burst_mode; /*!< enable or disable the wrap burst mode */
|
||||
uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */
|
||||
uint32_t burst_mode; /*!< enable or disable the burst mode */
|
||||
uint32_t databus_width; /*!< specifies the databus width of external memory */
|
||||
uint32_t memory_type; /*!< specifies the type of external memory */
|
||||
uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */
|
||||
exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extendedmode is not used or the timing
|
||||
parameters for read if the extendedmode is used. */
|
||||
exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extendedmode is used. */
|
||||
}exmc_norsram_parameter_struct;
|
||||
|
||||
/* EXMC NAND/PC card timing initialize structure */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */
|
||||
uint32_t holdtime; /*!< configure the address hold time(or the data hold time for write operation) */
|
||||
uint32_t waittime; /*!< configure the minimum wait time */
|
||||
uint32_t setuptime; /*!< configure the address setup time */
|
||||
}exmc_nand_pccard_timing_parameter_struct;
|
||||
|
||||
/* EXMC NAND initialize structure */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t nand_bank; /*!< select the bank of NAND */
|
||||
uint32_t ecc_size; /*!< the page size for the ECC calculation */
|
||||
uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */
|
||||
uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */
|
||||
uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */
|
||||
uint32_t databus_width; /*!< the NAND flash databus width */
|
||||
uint32_t wait_feature; /*!< enable or disable the wait feature */
|
||||
exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */
|
||||
exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */
|
||||
}exmc_nand_parameter_struct;
|
||||
|
||||
/* EXMC PC card initialize structure */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */
|
||||
uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */
|
||||
uint32_t wait_feature; /*!< enable or disable the wait feature */
|
||||
exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for PC card common space */
|
||||
exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for PC card attribute space */
|
||||
exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for PC card IO space */
|
||||
}exmc_pccard_parameter_struct;
|
||||
|
||||
/* EXMC SDRAM timing initialize structure */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t row_to_column_delay; /*!< configure the row to column delay */
|
||||
uint32_t row_precharge_delay; /*!< configure the row precharge delay */
|
||||
uint32_t write_recovery_delay; /*!< configure the write recovery delay */
|
||||
uint32_t auto_refresh_delay; /*!< configure the auto refresh delay */
|
||||
uint32_t row_address_select_delay; /*!< configure the row address select delay */
|
||||
uint32_t exit_selfrefresh_delay; /*!< configure the exit self-refresh delay */
|
||||
uint32_t load_mode_register_delay; /*!< configure the load mode register delay */
|
||||
}exmc_sdram_timing_parameter_struct;
|
||||
|
||||
/* EXMC SDRAM initialize structure */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t sdram_device; /*!< device of SDRAM */
|
||||
uint32_t pipeline_read_delay; /*!< the delay for reading data after CAS latency in HCLK clock cycles */
|
||||
uint32_t burst_read_switch; /*!< enable or disable the burst read */
|
||||
uint32_t sdclock_config; /*!< the SDCLK memory clock for both SDRAM banks */
|
||||
uint32_t write_protection; /*!< enable or disable SDRAM bank write protection function */
|
||||
uint32_t cas_latency; /*!< configure the SDRAM CAS latency */
|
||||
uint32_t internal_bank_number; /*!< the number of internal bank */
|
||||
uint32_t data_width; /*!< the databus width of SDRAM memory */
|
||||
uint32_t row_address_width; /*!< the bit width of a row address */
|
||||
uint32_t column_address_width; /*!< the bit width of a column address */
|
||||
exmc_sdram_timing_parameter_struct* timing; /*!< the timing parameters for write and read SDRAM */
|
||||
}exmc_sdram_parameter_struct;
|
||||
|
||||
/* EXMC SDRAM command initialize structure */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t mode_register_content; /*!< the SDRAM mode register content */
|
||||
uint32_t auto_refresh_number; /*!< the number of successive auto-refresh cycles will be send when CMD = 011 */
|
||||
uint32_t bank_select; /*!< the bank which command will be sent to */
|
||||
uint32_t command; /*!< the commands that will be sent to SDRAM */
|
||||
}exmc_sdram_command_parameter_struct;
|
||||
|
||||
/* EXMC SQPISRAM initialize structure */
|
||||
typedef struct{
|
||||
uint32_t sample_polarity; /*!< read data sample polarity */
|
||||
uint32_t id_length; /*!< SPI PSRAM ID length */
|
||||
uint32_t address_bits; /*!< bit number of SPI PSRAM address phase */
|
||||
uint32_t command_bits; /*!< bit number of SPI PSRAM command phase */
|
||||
}exmc_sqpipsram_parameter_struct;
|
||||
|
||||
/* EXMC register address */
|
||||
#define EXMC_SNCTL(region) REG32(EXMC + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash control registers, region = 0,1,2,3 */
|
||||
#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash timing configuration registers, region = 0,1,2,3 */
|
||||
#define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash write timing configuration registers, region = 0,1,2,3 */
|
||||
|
||||
#define EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card control registers, bank = 1,2,3 */
|
||||
#define EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card interrupt enable registers, bank = 1,2,3 */
|
||||
#define EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card common space timing configuration registers, bank = 1,2,3 */
|
||||
#define EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card attribute space timing configuration registers, bank = 1,2,3 */
|
||||
#define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND ECC registers, bank = 1,2 */
|
||||
|
||||
#define EXMC_SDCTL(device) REG32(EXMC + 0x140U + 0x4U*(((uint32_t)(device)) - 0x4U)) /*!< EXMC SDRAM control registers,device = 0,1 */
|
||||
#define EXMC_SDTCFG(device) REG32(EXMC + 0x148U + 0x4U*(((uint32_t)(device)) - 0x4U)) /*!< EXMC SDRAM timing configuration registers,device = 0,1 */
|
||||
|
||||
/* CRAM page size */
|
||||
#define SNCTL_CPS(regval) (BITS(16,18) & ((uint32_t)(regval) << 16))
|
||||
#define EXMC_CRAM_AUTO_SPLIT SNCTL_CPS(0) /*!< automatic burst split on page boundary crossing */
|
||||
#define EXMC_CRAM_PAGE_SIZE_128_BYTES SNCTL_CPS(1) /*!< page size is 128 bytes */
|
||||
#define EXMC_CRAM_PAGE_SIZE_256_BYTES SNCTL_CPS(2) /*!< page size is 256 bytes */
|
||||
#define EXMC_CRAM_PAGE_SIZE_512_BYTES SNCTL_CPS(3) /*!< page size is 512 bytes */
|
||||
#define EXMC_CRAM_PAGE_SIZE_1024_BYTES SNCTL_CPS(4) /*!< page size is 1024 bytes */
|
||||
|
||||
/* NOR bank memory data bus width */
|
||||
#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
|
||||
#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width is 8 bits */
|
||||
#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width is 16 bits */
|
||||
|
||||
/* NOR bank memory type */
|
||||
#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
|
||||
#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */
|
||||
#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */
|
||||
#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */
|
||||
|
||||
/* asynchronous access mode */
|
||||
#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
|
||||
#define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */
|
||||
#define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */
|
||||
#define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */
|
||||
#define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */
|
||||
|
||||
/* data latency for NOR flash */
|
||||
#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24))
|
||||
#define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency of first burst access is 2 EXMC_CLK */
|
||||
#define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency of first burst access is 3 EXMC_CLK */
|
||||
#define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency of first burst access is 4 EXMC_CLK */
|
||||
#define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency of first burst access is 5 EXMC_CLK */
|
||||
#define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency of first burst access is 6 EXMC_CLK */
|
||||
#define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency of first burst access is 7 EXMC_CLK */
|
||||
#define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency of first burst access is 8 EXMC_CLK */
|
||||
#define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency of first burst access is 9 EXMC_CLK */
|
||||
#define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency of first burst access is 10 EXMC_CLK */
|
||||
#define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency of first burst access is 11 EXMC_CLK */
|
||||
#define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency of first burst access is 12 EXMC_CLK */
|
||||
#define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency of first burst access is 13 EXMC_CLK */
|
||||
#define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency of first burst access is 14 EXMC_CLK */
|
||||
#define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency of first burst access is 15 EXMC_CLK */
|
||||
#define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency of first burst access is 16 EXMC_CLK */
|
||||
#define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency of first burst access is 17 EXMC_CLK */
|
||||
|
||||
/* synchronous clock divide ratio */
|
||||
#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20))
|
||||
#define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */
|
||||
#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = 5*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = 6*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = 7*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = 8*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = 9*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = 10*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK*/
|
||||
#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */
|
||||
#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */
|
||||
|
||||
/* ECC size */
|
||||
#define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17))
|
||||
#define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* ECC size is 256 bytes */
|
||||
#define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* ECC size is 512 bytes */
|
||||
#define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* ECC size is 1024 bytes */
|
||||
#define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* ECC size is 2048 bytes */
|
||||
#define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* ECC size is 4096 bytes */
|
||||
#define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* ECC size is 8192 bytes */
|
||||
|
||||
/* ALE to RE delay */
|
||||
#define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13))
|
||||
#define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */
|
||||
|
||||
/* CLE to RE delay */
|
||||
#define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9))
|
||||
#define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */
|
||||
|
||||
/* NAND bank memory data bus width */
|
||||
#define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
|
||||
#define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width is 8 bits */
|
||||
#define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width is 16 bits */
|
||||
|
||||
/* SDRAM pipeline delay */
|
||||
#define SDCTL_PIPED(regval) (BITS(13,14) & ((uint32_t)(regval) << 13))
|
||||
#define EXMC_PIPELINE_DELAY_0_HCLK SDCTL_PIPED(0) /*!< 0 HCLK clock cycle delay */
|
||||
#define EXMC_PIPELINE_DELAY_1_HCLK SDCTL_PIPED(1) /*!< 1 HCLK clock cycle delay */
|
||||
#define EXMC_PIPELINE_DELAY_2_HCLK SDCTL_PIPED(2) /*!< 2 HCLK clock cycle delay */
|
||||
|
||||
/* SDRAM clock configuration */
|
||||
#define SDCTL_SDCLK(regval) (BITS(10,11) & ((uint32_t)(regval) << 10))
|
||||
#define EXMC_SDCLK_DISABLE SDCTL_SDCLK(0) /*!< SDCLK memory clock disabled */
|
||||
#define EXMC_SDCLK_PERIODS_2_HCLK SDCTL_SDCLK(2) /*!< SDCLK memory period = 2*HCLK */
|
||||
#define EXMC_SDCLK_PERIODS_3_HCLK SDCTL_SDCLK(3) /*!< SDCLK memory period = 3*HCLK */
|
||||
|
||||
/* CAS latency */
|
||||
#define SDCTL_CL(regval) (BITS(7,8) & ((uint32_t)(regval) << 7))
|
||||
#define EXMC_CAS_LATENCY_1_SDCLK SDCTL_CL(1) /*!< CAS latency is 1 memory clock cycle */
|
||||
#define EXMC_CAS_LATENCY_2_SDCLK SDCTL_CL(2) /*!< CAS latency is 2 memory clock cycle */
|
||||
#define EXMC_CAS_LATENCY_3_SDCLK SDCTL_CL(3) /*!< CAS latency is 3 memory clock cycle */
|
||||
|
||||
/* SDRAM data bus width */
|
||||
#define SDCTL_SDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
|
||||
#define EXMC_SDRAM_DATABUS_WIDTH_8B SDCTL_SDW(0) /*!< SDRAM data width 8 bits */
|
||||
#define EXMC_SDRAM_DATABUS_WIDTH_16B SDCTL_SDW(1) /*!< SDRAM data width 16 bits */
|
||||
#define EXMC_SDRAM_DATABUS_WIDTH_32B SDCTL_SDW(2) /*!< SDRAM data width 32 bits */
|
||||
|
||||
/* SDRAM row address bit width */
|
||||
#define SDCTL_RAW(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
|
||||
#define EXMC_SDRAM_ROW_ADDRESS_11 SDCTL_RAW(0) /*!< row address bit width is 11 bits */
|
||||
#define EXMC_SDRAM_ROW_ADDRESS_12 SDCTL_RAW(1) /*!< row address bit width is 12 bits */
|
||||
#define EXMC_SDRAM_ROW_ADDRESS_13 SDCTL_RAW(2) /*!< row address bit width is 13 bits */
|
||||
|
||||
/* SDRAM column address bit width */
|
||||
#define SDCTL_CAW(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define EXMC_SDRAM_COW_ADDRESS_8 SDCTL_CAW(0) /*!< column address bit width is 8 bits */
|
||||
#define EXMC_SDRAM_COW_ADDRESS_9 SDCTL_CAW(1) /*!< column address bit width is 9 bits */
|
||||
#define EXMC_SDRAM_COW_ADDRESS_10 SDCTL_CAW(2) /*!< column address bit width is 10 bits */
|
||||
#define EXMC_SDRAM_COW_ADDRESS_11 SDCTL_CAW(3) /*!< column address bit width is 11 bits */
|
||||
|
||||
/* SDRAM number of successive auto-refresh */
|
||||
#define SDCMD_NARF(regval) (BITS(5,8) & ((uint32_t)(regval) << 5))
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_1_SDCLK SDCMD_NARF(0) /*!< 1 auto-refresh cycle */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_2_SDCLK SDCMD_NARF(1) /*!< 2 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_3_SDCLK SDCMD_NARF(2) /*!< 3 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_4_SDCLK SDCMD_NARF(3) /*!< 4 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_5_SDCLK SDCMD_NARF(4) /*!< 5 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_6_SDCLK SDCMD_NARF(5) /*!< 6 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_7_SDCLK SDCMD_NARF(6) /*!< 7 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_8_SDCLK SDCMD_NARF(7) /*!< 8 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_9_SDCLK SDCMD_NARF(8) /*!< 9 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_10_SDCLK SDCMD_NARF(9) /*!< 10 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_11_SDCLK SDCMD_NARF(10) /*!< 11 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_12_SDCLK SDCMD_NARF(11) /*!< 12 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_13_SDCLK SDCMD_NARF(12) /*!< 13 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_14_SDCLK SDCMD_NARF(13) /*!< 14 auto-refresh cycles */
|
||||
#define EXMC_SDRAM_AUTO_REFLESH_15_SDCLK SDCMD_NARF(14) /*!< 15 auto-refresh cycles */
|
||||
|
||||
/* SDRAM command selection */
|
||||
#define SDCMD_CMD(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
|
||||
#define EXMC_SDRAM_NORMAL_OPERATION SDCMD_CMD(0) /*!< normal operation command */
|
||||
#define EXMC_SDRAM_CLOCK_ENABLE SDCMD_CMD(1) /*!< clock enable command */
|
||||
#define EXMC_SDRAM_PRECHARGE_ALL SDCMD_CMD(2) /*!< precharge all command */
|
||||
#define EXMC_SDRAM_AUTO_REFRESH SDCMD_CMD(3) /*!< auto-refresh command */
|
||||
#define EXMC_SDRAM_LOAD_MODE_REGISTER SDCMD_CMD(4) /*!< load mode register command */
|
||||
#define EXMC_SDRAM_SELF_REFRESH SDCMD_CMD(5) /*!< self-refresh command */
|
||||
#define EXMC_SDRAM_POWERDOWN_ENTRY SDCMD_CMD(6) /*!< power-down entry command */
|
||||
|
||||
/* SDRAM the delayed sample clock of read data */
|
||||
#define SDRSCTL_SDSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
|
||||
#define EXMC_SDRAM_0_DELAY_CELL SDRSCTL_SDSC(0) /*!< select the clock after 0 delay cell */
|
||||
#define EXMC_SDRAM_1_DELAY_CELL SDRSCTL_SDSC(1) /*!< select the clock after 1 delay cell */
|
||||
#define EXMC_SDRAM_2_DELAY_CELL SDRSCTL_SDSC(2) /*!< select the clock after 2 delay cell */
|
||||
#define EXMC_SDRAM_3_DELAY_CELL SDRSCTL_SDSC(3) /*!< select the clock after 3 delay cell */
|
||||
#define EXMC_SDRAM_4_DELAY_CELL SDRSCTL_SDSC(4) /*!< select the clock after 4 delay cell */
|
||||
#define EXMC_SDRAM_5_DELAY_CELL SDRSCTL_SDSC(5) /*!< select the clock after 5 delay cell */
|
||||
#define EXMC_SDRAM_6_DELAY_CELL SDRSCTL_SDSC(6) /*!< select the clock after 6 delay cell */
|
||||
#define EXMC_SDRAM_7_DELAY_CELL SDRSCTL_SDSC(7) /*!< select the clock after 7 delay cell */
|
||||
#define EXMC_SDRAM_8_DELAY_CELL SDRSCTL_SDSC(8) /*!< select the clock after 8 delay cell */
|
||||
#define EXMC_SDRAM_9_DELAY_CELL SDRSCTL_SDSC(9) /*!< select the clock after 9 delay cell */
|
||||
#define EXMC_SDRAM_10_DELAY_CELL SDRSCTL_SDSC(10) /*!< select the clock after 10 delay cell */
|
||||
#define EXMC_SDRAM_11_DELAY_CELL SDRSCTL_SDSC(11) /*!< select the clock after 11 delay cell */
|
||||
#define EXMC_SDRAM_12_DELAY_CELL SDRSCTL_SDSC(12) /*!< select the clock after 12 delay cell */
|
||||
#define EXMC_SDRAM_13_DELAY_CELL SDRSCTL_SDSC(13) /*!< select the clock after 13 delay cell */
|
||||
#define EXMC_SDRAM_14_DELAY_CELL SDRSCTL_SDSC(14) /*!< select the clock after 14 delay cell */
|
||||
#define EXMC_SDRAM_15_DELAY_CELL SDRSCTL_SDSC(15) /*!< select the clock after 15 delay cell */
|
||||
|
||||
/* SPI PSRAM ID length */
|
||||
#define SINIT_IDL(regval) (BITS(29,30) & ((uint32_t)(regval) << 29))
|
||||
#define EXMC_SQPIPSRAM_ID_LENGTH_64B SINIT_IDL(0) /*!< SPI PSRAM ID length is 64 bits */
|
||||
#define EXMC_SQPIPSRAM_ID_LENGTH_32B SINIT_IDL(1) /*!< SPI PSRAM ID length is 32 bits */
|
||||
#define EXMC_SQPIPSRAM_ID_LENGTH_16B SINIT_IDL(2) /*!< SPI PSRAM ID length is 16 bits */
|
||||
#define EXMC_SQPIPSRAM_ID_LENGTH_8B SINIT_IDL(3) /*!< SPI PSRAM ID length is 8 bits */
|
||||
|
||||
/* SPI PSRAM bit number of address phase */
|
||||
#define SINIT_ADRBIT(regval) (BITS(24,28) & ((uint32_t)(regval) << 24))
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_1B SINIT_ADRBIT(1) /*!< SPI PSRAM address is 1 bit */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_2B SINIT_ADRBIT(2) /*!< SPI PSRAM address is 2 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_3B SINIT_ADRBIT(3) /*!< SPI PSRAM address is 3 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_4B SINIT_ADRBIT(4) /*!< SPI PSRAM address is 4 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_5B SINIT_ADRBIT(5) /*!< SPI PSRAM address is 5 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_6B SINIT_ADRBIT(6) /*!< SPI PSRAM address is 6 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_7B SINIT_ADRBIT(7) /*!< SPI PSRAM address is 7 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_8B SINIT_ADRBIT(8) /*!< SPI PSRAM address is 8 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_9B SINIT_ADRBIT(9) /*!< SPI PSRAM address is 9 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_10B SINIT_ADRBIT(10) /*!< SPI PSRAM address is 10 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_11B SINIT_ADRBIT(11) /*!< SPI PSRAM address is 11 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_12B SINIT_ADRBIT(12) /*!< SPI PSRAM address is 12 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_13B SINIT_ADRBIT(13) /*!< SPI PSRAM address is 13 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_14B SINIT_ADRBIT(14) /*!< SPI PSRAM address is 14 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_15B SINIT_ADRBIT(15) /*!< SPI PSRAM address is 15 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_16B SINIT_ADRBIT(16) /*!< SPI PSRAM address is 16 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_17B SINIT_ADRBIT(17) /*!< SPI PSRAM address is 17 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_18B SINIT_ADRBIT(18) /*!< SPI PSRAM address is 18 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_19B SINIT_ADRBIT(19) /*!< SPI PSRAM address is 19 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_20B SINIT_ADRBIT(20) /*!< SPI PSRAM address is 20 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_21B SINIT_ADRBIT(21) /*!< SPI PSRAM address is 21 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_22B SINIT_ADRBIT(22) /*!< SPI PSRAM address is 22 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_23B SINIT_ADRBIT(23) /*!< SPI PSRAM address is 23 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_24B SINIT_ADRBIT(24) /*!< SPI PSRAM address is 24 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_25B SINIT_ADRBIT(25) /*!< SPI PSRAM address is 25 bits */
|
||||
#define EXMC_SQPIPSRAM_ADDR_LENGTH_26B SINIT_ADRBIT(26) /*!< SPI PSRAM address is 26 bits */
|
||||
|
||||
/* SPI PSRAM bit number of command phase */
|
||||
#define SINIT_CMDBIT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16))
|
||||
#define EXMC_SQPIPSRAM_COMMAND_LENGTH_4B SINIT_CMDBIT(0) /*!< SPI PSRAM command is 4 bits */
|
||||
#define EXMC_SQPIPSRAM_COMMAND_LENGTH_8B SINIT_CMDBIT(1) /*!< SPI PSRAM command is 8 bits */
|
||||
#define EXMC_SQPIPSRAM_COMMAND_LENGTH_16B SINIT_CMDBIT(2) /*!< SPI PSRAM command is 16 bits */
|
||||
|
||||
/* SPI PSRAM read command mode */
|
||||
#define SRCMD_RMODE(regval) (BITS(20,21) & ((uint32_t)(regval) << 20))
|
||||
#define EXMC_SQPIPSRAM_READ_MODE_DISABLE SRCMD_RMODE(0) /*!< not SPI mode */
|
||||
#define EXMC_SQPIPSRAM_READ_MODE_SPI SRCMD_RMODE(1) /*!< SPI mode */
|
||||
#define EXMC_SQPIPSRAM_READ_MODE_SQPI SRCMD_RMODE(2) /*!< SQPI mode */
|
||||
#define EXMC_SQPIPSRAM_READ_MODE_QPI SRCMD_RMODE(3) /*!< QPI mode */
|
||||
|
||||
/* SPI PSRAM write command mode */
|
||||
#define SRCMD_WMODE(regval) (BITS(20,21) & ((uint32_t)(regval) << 20))
|
||||
#define EXMC_SQPIPSRAM_WRITE_MODE_DISABLE SRCMD_WMODE(0) /*!< not SPI mode */
|
||||
#define EXMC_SQPIPSRAM_WRITE_MODE_SPI SRCMD_WMODE(1) /*!< SPI mode */
|
||||
#define EXMC_SQPIPSRAM_WRITE_MODE_SQPI SRCMD_WMODE(2) /*!< SQPI mode */
|
||||
#define EXMC_SQPIPSRAM_WRITE_MODE_QPI SRCMD_WMODE(3) /*!< QPI mode */
|
||||
|
||||
/* EXMC NOR/SRAM bank region definition */
|
||||
#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */
|
||||
#define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U) /*!< bank0 NOR/SRAM region1 */
|
||||
#define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U) /*!< bank0 NOR/SRAM region2 */
|
||||
#define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U) /*!< bank0 NOR/SRAM region3 */
|
||||
|
||||
/* EXMC consecutive clock */
|
||||
#define EXMC_CLOCK_SYN_MODE ((uint32_t)0x00000000U) /*!< EXMC_CLK is generated only during synchronous access */
|
||||
#define EXMC_CLOCK_UNCONDITIONALLY EXMC_SNCTL_CCK /*!< EXMC_CLK is generated unconditionally */
|
||||
|
||||
/* EXMC NOR/SRAM write mode */
|
||||
#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */
|
||||
#define EXMC_SYN_WRITE EXMC_SNCTL_SYNCWR /*!< synchronous write mode */
|
||||
|
||||
/* EXMC NWAIT signal configuration */
|
||||
#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */
|
||||
#define EXMC_NWAIT_CONFIG_DURING EXMC_SNCTL_NRWTCFG /*!< NWAIT signal is active during wait state */
|
||||
|
||||
/* EXMC NWAIT signal polarity configuration */
|
||||
#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */
|
||||
#define EXMC_NWAIT_POLARITY_HIGH EXMC_SNCTL_NRWTPOL /*!< high level is active of NWAIT */
|
||||
|
||||
/* EXMC NAND/PC card bank definition */
|
||||
#define EXMC_BANK1_NAND ((uint32_t)0x00000001U) /*!< NAND flash bank1 */
|
||||
#define EXMC_BANK2_NAND ((uint32_t)0x00000002U) /*!< NAND flash bank2 */
|
||||
#define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U) /*!< PC card bank3 */
|
||||
|
||||
/* EXMC SDRAM bank definition */
|
||||
#define EXMC_SDRAM_DEVICE0 ((uint32_t)0x00000004U) /*!< SDRAM device0 */
|
||||
#define EXMC_SDRAM_DEVICE1 ((uint32_t)0x00000005U) /*!< SDRAM device1 */
|
||||
|
||||
/* EXMC SDRAM internal banks */
|
||||
#define EXMC_SDRAM_2_INTER_BANK ((uint32_t)0x00000000U) /*!< 2 internal banks */
|
||||
#define EXMC_SDRAM_4_INTER_BANK EXMC_SDCTL_NBK /*!< 4 internal banks */
|
||||
|
||||
/* SDRAM device0 selection */
|
||||
#define EXMC_SDRAM_DEVICE0_UNSELECT ((uint32_t)0x00000000U) /*!< unselect SDRAM device0 */
|
||||
#define EXMC_SDRAM_DEVICE0_SELECT EXMC_SDCMD_DS0 /*!< select SDRAM device0 */
|
||||
|
||||
/* SDRAM device1 selection */
|
||||
#define EXMC_SDRAM_DEVICE1_UNSELECT ((uint32_t)0x00000000U) /*!< unselect SDRAM device1 */
|
||||
#define EXMC_SDRAM_DEVICE1_SELECT EXMC_SDCMD_DS1 /*!< select SDRAM device1 */
|
||||
|
||||
/* SDRAM device status */
|
||||
#define EXMC_SDRAM_DEVICE_NORMAL ((uint32_t)0x00000000U) /*!< normal status */
|
||||
#define EXMC_SDRAM_DEVICE_SELF_REFRESH ((uint32_t)0x00000001U) /*!< self refresh status */
|
||||
#define EXMC_SDRAM_DEVICE_POWER_DOWN ((uint32_t)0x00000002U) /*!< power down status */
|
||||
|
||||
/* sample cycle of read data */
|
||||
#define EXMC_SDRAM_READSAMPLE_0_EXTRAHCLK ((uint32_t)0x00000000U) /*!< add 0 extra HCLK cycle to the read data sample clock besides the delay chain */
|
||||
#define EXMC_SDRAM_READSAMPLE_1_EXTRAHCLK EXMC_SDRSCTL_SSCR /*!< add 1 extra HCLK cycle to the read data sample clock besides the delay chain */
|
||||
|
||||
/* read data sample polarity */
|
||||
#define EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE ((uint32_t)0x00000000U) /*!< sample data at rising edge */
|
||||
#define EXMC_SQPIPSRAM_SAMPLE_FALLING_EDGE EXMC_SINIT_POL /*!< sample data at falling edge */
|
||||
|
||||
/* SQPI SRAM command flag */
|
||||
#define EXMC_SEND_COMMAND_FLAG_RDID EXMC_SRCMD_RDID /*!< EXMC_SRCMD_RDID flag bit */
|
||||
#define EXMC_SEND_COMMAND_FLAG_SC EXMC_SWCMD_SC /*!< EXMC_SWCMD_SC flag bit */
|
||||
|
||||
/* EXMC flag bits */
|
||||
#define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTEN_INTRS /*!< interrupt rising edge status */
|
||||
#define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTEN_INTHS /*!< interrupt high-level status */
|
||||
#define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTEN_INTFS /*!< interrupt falling edge status */
|
||||
#define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTEN_FFEPT /*!< FIFO empty flag */
|
||||
#define EXMC_SDRAM_FLAG_REFRESH EXMC_SDSDAT_REIF /*!< refresh error interrupt flag */
|
||||
#define EXMC_SDRAM_FLAG_NREADY EXMC_SDSDAT_NRDY /*!< not ready status */
|
||||
|
||||
/* EXMC interrupt flag bits */
|
||||
#define EXMC_NAND_PCCARD_INT_FLAG_RISE EXMC_NPINTEN_INTREN /*!< rising edge interrupt and flag */
|
||||
#define EXMC_NAND_PCCARD_INT_FLAG_LEVEL EXMC_NPINTEN_INTHEN /*!< high-level interrupt and flag */
|
||||
#define EXMC_NAND_PCCARD_INT_FLAG_FALL EXMC_NPINTEN_INTFEN /*!< falling edge interrupt and flag */
|
||||
#define EXMC_SDRAM_INT_FLAG_REFRESH EXMC_SDARI_REIE /*!< refresh error interrupt and flag */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* NOR/SRAM */
|
||||
/* deinitialize EXMC NOR/SRAM region */
|
||||
void exmc_norsram_deinit(uint32_t exmc_norsram_region);
|
||||
/* initialize exmc_norsram_parameter_struct with the default values */
|
||||
void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
|
||||
/* initialize EXMC NOR/SRAM region */
|
||||
void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
|
||||
/* enable EXMC NOR/SRAM region */
|
||||
void exmc_norsram_enable(uint32_t exmc_norsram_region);
|
||||
/* disable EXMC NOR/SRAM region */
|
||||
void exmc_norsram_disable(uint32_t exmc_norsram_region);
|
||||
/* NAND */
|
||||
/* deinitialize EXMC NAND bank */
|
||||
void exmc_nand_deinit(uint32_t exmc_nand_bank);
|
||||
/* initialize exmc_nand_parameter_struct with the default values */
|
||||
void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct);
|
||||
/* initialize EXMC NAND bank */
|
||||
void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct);
|
||||
/* enable EXMC NAND bank */
|
||||
void exmc_nand_enable(uint32_t exmc_nand_bank);
|
||||
/* disable EXMC NAND bank */
|
||||
void exmc_nand_disable(uint32_t exmc_nand_bank);
|
||||
/* PC card */
|
||||
/* deinitialize EXMC PC card bank */
|
||||
void exmc_pccard_deinit(void);
|
||||
/* initialize exmc_pccard_parameter_struct with the default values */
|
||||
void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct);
|
||||
/* initialize EXMC PC card bank */
|
||||
void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct);
|
||||
/* enable EXMC PC card bank */
|
||||
void exmc_pccard_enable(void);
|
||||
/* disable EXMC PC card bank */
|
||||
void exmc_pccard_disable(void);
|
||||
/* SDRAM */
|
||||
/* deinitialize EXMC SDRAM device */
|
||||
void exmc_sdram_deinit(uint32_t exmc_sdram_device);
|
||||
/* initialize exmc_sdram_parameter_struct with the default values */
|
||||
void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct);
|
||||
/* initialize EXMC SDRAM device */
|
||||
void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct);
|
||||
/* initialize exmc_sdram_command_parameter_struct with the default values */
|
||||
void exmc_sdram_struct_command_para_init(exmc_sdram_command_parameter_struct *exmc_sdram_command_init_struct);
|
||||
/* SQPIPSRAM */
|
||||
/* deinitialize EXMC SQPIPSRAM */
|
||||
void exmc_sqpipsram_deinit(void);
|
||||
/* initialize exmc_sqpipsram_parameter_struct with the default values */
|
||||
void exmc_sqpipsram_struct_para_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct);
|
||||
/* initialize EXMC SQPIPSRAM */
|
||||
void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct);
|
||||
|
||||
/* function configuration */
|
||||
/* NOR/SRAM */
|
||||
/* configure consecutive clock */
|
||||
void exmc_norsram_consecutive_clock_config(uint32_t clock_mode);
|
||||
/* configure CRAM page size */
|
||||
void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size);
|
||||
/* NAND */
|
||||
/* enable or disable the EXMC NAND ECC function */
|
||||
void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue);
|
||||
/* get the EXMC ECC value */
|
||||
uint32_t exmc_ecc_get(uint32_t exmc_nand_bank);
|
||||
/* SDRAM */
|
||||
/* enable or disable read sample */
|
||||
void exmc_sdram_readsample_enable(ControlStatus newvalue);
|
||||
/* configure the delayed sample clock of read data */
|
||||
void exmc_sdram_readsample_config(uint32_t delay_cell, uint32_t extra_hclk);
|
||||
/* configure the SDRAM memory command */
|
||||
void exmc_sdram_command_config(exmc_sdram_command_parameter_struct* exmc_sdram_command_init_struct);
|
||||
/* set auto-refresh interval */
|
||||
void exmc_sdram_refresh_count_set(uint32_t exmc_count);
|
||||
/* set the number of successive auto-refresh command */
|
||||
void exmc_sdram_autorefresh_number_set(uint32_t exmc_number);
|
||||
/* configure the write protection function */
|
||||
void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue);
|
||||
/* get the status of SDRAM device0 or device1 */
|
||||
uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device);
|
||||
/* SQPIPSRAM */
|
||||
/* set the read command */
|
||||
void exmc_sqpipsram_read_command_set(uint32_t read_command_mode,uint32_t read_wait_cycle,uint32_t read_command_code);
|
||||
/* set the write command */
|
||||
void exmc_sqpipsram_write_command_set(uint32_t write_command_mode,uint32_t write_wait_cycle,uint32_t write_command_code);
|
||||
/* send SPI read ID command */
|
||||
void exmc_sqpipsram_read_id_command_send(void);
|
||||
/* send SPI special command which does not have address and data phase */
|
||||
void exmc_sqpipsram_write_cmd_send(void);
|
||||
/* get the EXMC SPI ID low data */
|
||||
uint32_t exmc_sqpipsram_low_id_get(void);
|
||||
/* get the EXMC SPI ID high data */
|
||||
uint32_t exmc_sqpipsram_high_id_get(void);
|
||||
/* get the bit value of EXMC send write command bit or read ID command */
|
||||
FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* enable EXMC interrupt */
|
||||
void exmc_interrupt_enable(uint32_t exmc_bank,uint32_t interrupt);
|
||||
/* disable EXMC interrupt */
|
||||
void exmc_interrupt_disable(uint32_t exmc_bank,uint32_t interrupt);
|
||||
/* get EXMC flag status */
|
||||
FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag);
|
||||
/* clear EXMC flag status */
|
||||
void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag);
|
||||
/* get EXMC interrupt flag */
|
||||
FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt);
|
||||
/* clear EXMC interrupt flag */
|
||||
void exmc_interrupt_flag_clear(uint32_t exmc_bank,uint32_t interrupt);
|
||||
|
||||
#endif /* GD32F4XX_EXMC_H */
|
||||
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Reference in New Issue