From 29c2f1e3a8bb8b24a1609ec2fc62bd4376de9448 Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 6 Jun 2024 00:44:29 -0700 Subject: [PATCH 001/198] Modify Makefiles --- .../services/drivers/usb/components/port/xhci/usb_hc_xhci.h | 2 +- .../XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h index 077e316ff..f896e8207 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h @@ -1,7 +1,7 @@ #ifndef USB_HC_XHCI_H_ #define USB_HC_XHCI_H_ - +#include "xhci.h" diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h index 4b09aa70a..b52d35f8e 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h @@ -1,7 +1,7 @@ #ifndef XHCI_H_ #define XHCI_H_ - +#include "xhci_reg.h" From d1b462b83f5e19af0c6474fe7d4ae716ba195d5c Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 6 Jun 2024 00:44:56 -0700 Subject: [PATCH 002/198] Modify Makefiles --- .../XiZi_AIoT/services/drivers/usb/components/port/xhci/Makefile | 0 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/Makefile diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/Makefile new file mode 100644 index 000000000..e69de29bb From 09e7094ec3eac5ba38d6820aa0161972e80c6558 Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 6 Jun 2024 02:12:13 -0700 Subject: [PATCH 003/198] Modify Makefiles --- .../services/drivers/usb/components/Makefile | 2 +- .../services/drivers/usb/components/port/Makefile | 4 ++++ .../drivers/usb/components/port/xhci/Makefile | 11 +++++++++++ 3 files changed, 16 insertions(+), 1 deletion(-) create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/Makefile diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/Makefile index 847bf6b16..79a64c1ea 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/Makefile @@ -11,7 +11,7 @@ # libipc = $(KERNEL_ROOT)/services/app/libipc.o # libsem = $(KERNEL_ROOT)/services/app/libsemaphore.o -SRC_DIR := class core osal +SRC_DIR := class core osal port include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/Makefile new file mode 100644 index 000000000..f2783839d --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/Makefile @@ -0,0 +1,4 @@ +SRC_DIR := xhci + + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/Makefile index e69de29bb..d2b035543 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/Makefile @@ -0,0 +1,11 @@ +include $(KERNEL_ROOT)/services/drivers/usb/components/usb.mk + +objs += usb_hc_xhci.o + +all: ${objs} + @echo "generate $^" + @mv $^ $(KERNEL_ROOT)/services/drivers/usb/components + +%.o: %.c + @echo "cc $^" + @${cc} ${cflags} ${c_useropts} ${INC_DIR} -o $@ -c $^ \ No newline at end of file From cbdabf3adced7dfbdb4b36f47a10ddd7b57dcee8 Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 6 Jun 2024 19:06:37 -0700 Subject: [PATCH 004/198] Ajust code tree --- .../XiZi_AIoT/services/drivers/usb/usb_config.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_config.h diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_config.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_config.h new file mode 100644 index 000000000..e691e6bd1 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_config.h @@ -0,0 +1,17 @@ +#ifndef USB_CONFIG_H_ +#define USB_CONFIG_H_ + + + + + + + + + + + + + + +#endif From 64477bafda70f4d645f207bd977a421b8dbfe9d5 Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 6 Jun 2024 19:09:16 -0700 Subject: [PATCH 005/198] Modify code tree --- .../services/drivers/usb/libusb/usb_config.h | 17 ----------------- 1 file changed, 17 deletions(-) delete mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/libusb/usb_config.h diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/libusb/usb_config.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/libusb/usb_config.h deleted file mode 100644 index e691e6bd1..000000000 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/libusb/usb_config.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef USB_CONFIG_H_ -#define USB_CONFIG_H_ - - - - - - - - - - - - - - -#endif From e61dee89224d700e88b8c9a1c359fb00bbe61086 Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 6 Jun 2024 20:15:48 -0700 Subject: [PATCH 006/198] Modify Makefile --- Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk index a77bc089c..e060536cf 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk @@ -16,7 +16,9 @@ objdump = ${toolchain}objdump c_useropts = -O0 -INC_DIR = -I$(KERNEL_ROOT)/services/drivers/usb/components \ +INC_DIR = -I$(KERNEL_ROOT)/services/drivers/usb/ \ + -I$(KERNEL_ROOT)/services/drivers/usb/components/ \ + -I$(KERNEL_ROOT)/services/drivers/usb/components/class \ -I$(KERNEL_ROOT)/services/drivers/usb/components/class \ -I$(KERNEL_ROOT)/services/drivers/usb/components/class/cdc \ -I$(KERNEL_ROOT)/services/drivers/usb/components/class/hub \ From 236f8bdb311536316d1a36d86d0ea04e2300a521 Mon Sep 17 00:00:00 2001 From: xj Date: Fri, 7 Jun 2024 00:54:42 -0700 Subject: [PATCH 007/198] Modify files --- .../services/drivers/usb/usb_config.h | 153 ++++++++++++++++++ .../services/drivers/usb/usb_service/Makefile | 0 .../drivers/usb/usb_service/usb_host.c | 6 + .../drivers/usb/usb_service/usb_host.h | 9 ++ 4 files changed, 168 insertions(+) create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.h diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_config.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_config.h index e691e6bd1..b2496eada 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_config.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_config.h @@ -1,15 +1,168 @@ #ifndef USB_CONFIG_H_ #define USB_CONFIG_H_ +/* + * Copyright : (C) 2022 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: usb_config.h + * Date: 2022-09-19 17:28:44 + * LastEditTime: 2022-09-19 17:28:45 + * Description:  This file is for usb hc xhci configuration. + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhugengyu 2022/9/19 init commit + * 1.1 liqiaozhong 2023/2/10 update to v0.7.0 + */ +#ifdef __cplusplus +extern "C" +{ +#endif + +#include + +/* ================ USB common Configuration ================ */ +void *usb_hc_malloc(size_t size); +void usb_hc_free(); +void *usb_hc_malloc_align(size_t align, size_t size); + +#define usb_malloc(size) usb_hc_malloc(size) +#define usb_free(ptr) usb_hc_free(ptr) +#define usb_align(align, size) usb_hc_malloc_align(align, size) + +#ifndef CONFIG_USB_DBG_LEVEL + #define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR +#endif + +#ifndef CONFIG_USB_PRINTF + #define CONFIG_USB_PRINTF printf +#endif +/* Enable print with color */ +#define CONFIG_USB_PRINTF_COLOR_ENABLE + +/* data align size when use dma */ +#ifndef CONFIG_USB_ALIGN_SIZE + #define CONFIG_USB_ALIGN_SIZE 4 +#endif +/* attribute data into no cache ram */ +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable"))) +/* ================= USB Device Stack Configuration ================ */ + +/* Ep0 max transfer buffer, specially for receiving data from ep0 out */ +#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 256 + + +#ifndef CONFIG_USBDEV_MSC_BLOCK_SIZE + #define CONFIG_USBDEV_MSC_BLOCK_SIZE 512 +#endif + +#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING + #define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING + #define CONFIG_USBDEV_MSC_PRODUCT_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_VERSION_STRING + #define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" +#endif + +// #define CONFIG_USBHOST_GET_STRING_DESC +#define CONFIG_USBHOST_GET_DEVICE_DESC + +// #define CONFIG_USBDEV_MSC_THREAD +#define CONFIG_INPUT_MOUSE_WHEEL + +#ifdef CONFIG_USBDEV_MSC_THREAD + #ifndef CONFIG_USBDEV_MSC_STACKSIZE + #define CONFIG_USBDEV_MSC_STACKSIZE 2048 + #endif + + #ifndef CONFIG_USBDEV_MSC_PRIO + #define CONFIG_USBDEV_MSC_PRIO 4 + #endif +#endif + +#ifndef CONFIG_USBDEV_AUDIO_VERSION + #define CONFIG_USBDEV_AUDIO_VERSION 0x0100 +#endif + +#ifndef CONFIG_USBDEV_AUDIO_MAX_CHANNEL + #define CONFIG_USBDEV_AUDIO_MAX_CHANNEL 8 +#endif + + +/* ================ USB HOST Stack Configuration ================== */ + +#define CONFIG_USBHOST_MAX_RHPORTS 2 +#define CONFIG_USBHOST_MAX_EXTHUBS 2 +#define CONFIG_USBHOST_MAX_EHPORTS 4 +#define CONFIG_USBHOST_MAX_INTERFACES 6 +#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 1 +#define CONFIG_USBHOST_MAX_ENDPOINTS 4 + +#define CONFIG_USBHOST_DEV_NAMELEN 16 + +#ifndef CONFIG_USBHOST_PSC_PRIO + #define CONFIG_USBHOST_PSC_PRIO 4 +#endif +#ifndef CONFIG_USBHOST_PSC_STACKSIZE + #define CONFIG_USBHOST_PSC_STACKSIZE 4096 +#endif + +/* Ep0 max transfer buffer */ +#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 + +#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT + #define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#endif + +#ifndef CONFIG_USBHOST_MSC_TIMEOUT + #define CONFIG_USBHOST_MSC_TIMEOUT 5000 +#endif + +/* do not try to enumrate one interface */ +#ifndef CONFIG_USBHOST_ENUM_FIRST_INTERFACE_ONLY + #define CONFIG_USBHOST_ENUM_FIRST_INTERFACE_ONLY +#endif + +/* ================ USB Device Port Configuration ================*/ + +#define CONFIG_XHCI_PAGE_SIZE 4096U +#define CONFIG_XHCI_PAGE_SHIFT 12U + +/* ================ USB Host Port Configuration ==================*/ + +#define CONFIG_USBHOST_PIPE_NUM 10 + +/* ================ XHCI Configuration ================ */ +#define CONFIG_USBHOST_XHCI +#define CONFIG_USBHOST_XHCI_NUM 2 + +#ifdef __cplusplus +} +#endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/Makefile new file mode 100644 index 000000000..e69de29bb diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c new file mode 100644 index 000000000..b46384fc7 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c @@ -0,0 +1,6 @@ +#include "usb_host.h" + + +int main(){ + return 0; +} diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.h new file mode 100644 index 000000000..e6e9f9efb --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.h @@ -0,0 +1,9 @@ +#ifndef USB_HOST_H_ +#define USB_HOST_H_ + + + + + + +#endif From 02e06231751d3e6fcaceb1ec62d103dfcdf4d61f Mon Sep 17 00:00:00 2001 From: xj Date: Fri, 7 Jun 2024 00:54:57 -0700 Subject: [PATCH 008/198] Modify files --- .../XiZi_AIoT/services/drivers/usb/libusb/Makefile | 0 .../XiZi_AIoT/services/drivers/usb/libusb/usb_host.c | 6 ------ .../XiZi_AIoT/services/drivers/usb/libusb/usb_host.h | 9 --------- 3 files changed, 15 deletions(-) delete mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/libusb/Makefile delete mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/libusb/usb_host.c delete mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/libusb/usb_host.h diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/libusb/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/usb/libusb/Makefile deleted file mode 100644 index e69de29bb..000000000 diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/libusb/usb_host.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/libusb/usb_host.c deleted file mode 100644 index b46384fc7..000000000 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/libusb/usb_host.c +++ /dev/null @@ -1,6 +0,0 @@ -#include "usb_host.h" - - -int main(){ - return 0; -} diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/libusb/usb_host.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/libusb/usb_host.h deleted file mode 100644 index e6e9f9efb..000000000 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/libusb/usb_host.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef USB_HOST_H_ -#define USB_HOST_H_ - - - - - - -#endif From 8e1bd559d5eaa87e6083e0867f894522cf4722da Mon Sep 17 00:00:00 2001 From: xj Date: Fri, 7 Jun 2024 00:56:57 -0700 Subject: [PATCH 009/198] Modify Makefile --- .../XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.h | 1 + 1 file changed, 1 insertion(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.h index 5ccb9a2cb..c0216cf49 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.h @@ -1,6 +1,7 @@ #ifndef USB_OSAL_H_ #define USB_OSAL_H_ +#include "usb_config.h" int usb_wait_until(int msec); From cb397c2c9e813f53cc39816318446fcff8f10df8 Mon Sep 17 00:00:00 2001 From: xj Date: Fri, 7 Jun 2024 03:06:11 -0700 Subject: [PATCH 010/198] transplant header files --- .../usb/components/class/hub/usbh_hub.c | 1 + .../drivers/usb/components/common/usb_def.h | 700 ++++++++++++++++++ 2 files changed, 701 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c index 41cd7cc79..b45dfb84a 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c @@ -1 +1,2 @@ #include "usbh_hub.h" +#include "usb_def.h" diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_def.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_def.h index 31dded28c..489ce4a3b 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_def.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_def.h @@ -1,8 +1,708 @@ #ifndef USB_DEF_H_ #define USB_DEF_H_ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +/* Useful define */ +#define USB_1_1 0x0110 +#define USB_2_0 0x0200 +/* Set USB version to 2.1 so that the host will request the BOS descriptor */ +#define USB_2_1 0x0210 +#define USB_3_0 0x0300 +#define USB_3_1 0x0310 + +/* Device speeds */ +#define USB_SPEED_UNKNOWN 0 /* Transfer rate not yet set */ +#define USB_SPEED_LOW 1 /* USB 1.1 */ +#define USB_SPEED_FULL 2 /* USB 1.1 */ +#define USB_SPEED_HIGH 3 /* USB 2.0 */ +#define USB_SPEED_WIRELESS 4 /* Wireless USB 2.5 */ +#define USB_SPEED_SUPER 5 /* USB 3.0 */ +#define USB_SPEED_SUPER_PLUS 6 /* USB 3.1 */ + +/* Maximum number of devices per controller */ +#define USB_MAX_DEVICES (127) + +/* Default USB control EP, always 0 and 0x80 */ +#define USB_CONTROL_OUT_EP0 0 +#define USB_CONTROL_IN_EP0 0x80 + +/**< maximum packet size (MPS) for EP 0 */ +#define USB_CTRL_EP_MPS 64 + +/* USB PID Types */ +#define USB_PID_OUT (0x01) /* Tokens */ +#define USB_PID_IN (0x09) +#define USB_PID_SOF (0x05) +#define USB_PID_SETUP (0x0d) + +#define USB_PID_DATA0 (0x03) /* Data */ +#define USB_PID_DATA1 (0x0b) +#define USB_PID_DATA2 (0x07) +#define USB_PID_MDATA (0x0f) + +#define USB_PID_ACK (0x02) /* Handshake */ +#define USB_PID_NAK (0x0a) +#define USB_PID_STALL (0x0e) +#define USB_PID_NYET (0x06) + +#define USB_PID_PRE (0x0c) /* Special */ +#define USB_PID_ERR (0x0c) +#define USB_PID_SPLIT (0x08) +#define USB_PID_PING (0x04) +#define USB_PID_RESERVED (0x00) + +#define USB_REQUEST_DIR_SHIFT 7U /* Bits 7: Request dir */ +#define USB_REQUEST_DIR_OUT (0U << USB_REQUEST_DIR_SHIFT) /* Bit 7=0: Host-to-device */ +#define USB_REQUEST_DIR_IN (1U << USB_REQUEST_DIR_SHIFT) /* Bit 7=1: Device-to-host */ +#define USB_REQUEST_DIR_MASK (1U << USB_REQUEST_DIR_SHIFT) /* Bit 7=1: Direction bit */ + +#define USB_REQUEST_TYPE_SHIFT 5U /* Bits 5:6: Request type */ +#define USB_REQUEST_STANDARD (0U << USB_REQUEST_TYPE_SHIFT) +#define USB_REQUEST_CLASS (1U << USB_REQUEST_TYPE_SHIFT) +#define USB_REQUEST_VENDOR (2U << USB_REQUEST_TYPE_SHIFT) +#define USB_REQUEST_RESERVED (3U << USB_REQUEST_TYPE_SHIFT) +#define USB_REQUEST_TYPE_MASK (3U << USB_REQUEST_TYPE_SHIFT) + +#define USB_REQUEST_RECIPIENT_SHIFT 0U /* Bits 0:4: Recipient */ +#define USB_REQUEST_RECIPIENT_DEVICE (0U << USB_REQUEST_RECIPIENT_SHIFT) +#define USB_REQUEST_RECIPIENT_INTERFACE (1U << USB_REQUEST_RECIPIENT_SHIFT) +#define USB_REQUEST_RECIPIENT_ENDPOINT (2U << USB_REQUEST_RECIPIENT_SHIFT) +#define USB_REQUEST_RECIPIENT_OTHER (3U << USB_REQUEST_RECIPIENT_SHIFT) +#define USB_REQUEST_RECIPIENT_MASK (3U << USB_REQUEST_RECIPIENT_SHIFT) + +/* USB Standard Request Codes */ +#define USB_REQUEST_GET_STATUS 0x00 +#define USB_REQUEST_CLEAR_FEATURE 0x01 +#define USB_REQUEST_SET_FEATURE 0x03 +#define USB_REQUEST_SET_ADDRESS 0x05 +#define USB_REQUEST_GET_DESCRIPTOR 0x06 +#define USB_REQUEST_SET_DESCRIPTOR 0x07 +#define USB_REQUEST_GET_CONFIGURATION 0x08 +#define USB_REQUEST_SET_CONFIGURATION 0x09 +#define USB_REQUEST_GET_INTERFACE 0x0A +#define USB_REQUEST_SET_INTERFACE 0x0B +#define USB_REQUEST_SYNCH_FRAME 0x0C +#define USB_REQUEST_SET_ENCRYPTION 0x0D +#define USB_REQUEST_GET_ENCRYPTION 0x0E +#define USB_REQUEST_RPIPE_ABORT 0x0E +#define USB_REQUEST_SET_HANDSHAKE 0x0F +#define USB_REQUEST_RPIPE_RESET 0x0F +#define USB_REQUEST_GET_HANDSHAKE 0x10 +#define USB_REQUEST_SET_CONNECTION 0x11 +#define USB_REQUEST_SET_SECURITY_DATA 0x12 +#define USB_REQUEST_GET_SECURITY_DATA 0x13 +#define USB_REQUEST_SET_WUSB_DATA 0x14 +#define USB_REQUEST_LOOPBACK_DATA_WRITE 0x15 +#define USB_REQUEST_LOOPBACK_DATA_READ 0x16 +#define USB_REQUEST_SET_INTERFACE_DS 0x17 + +/* USB Standard Feature selectors */ +#define USB_FEATURE_ENDPOINT_HALT 0 +#define USB_FEATURE_SELF_POWERED 0 +#define USB_FEATURE_REMOTE_WAKEUP 1 +#define USB_FEATURE_TEST_MODE 2 +#define USB_FEATURE_BATTERY 2 +#define USB_FEATURE_BHNPENABLE 3 +#define USB_FEATURE_WUSBDEVICE 3 +#define USB_FEATURE_AHNPSUPPORT 4 +#define USB_FEATURE_AALTHNPSUPPORT 5 +#define USB_FEATURE_DEBUGMODE 6 + +/* USB GET_STATUS Bit Values */ +#define USB_GETSTATUS_ENDPOINT_HALT 0x01 +#define USB_GETSTATUS_SELF_POWERED 0x01 +#define USB_GETSTATUS_REMOTE_WAKEUP 0x02 + +/* USB Descriptor Types */ +#define USB_DESCRIPTOR_TYPE_DEVICE 0x01U +#define USB_DESCRIPTOR_TYPE_CONFIGURATION 0x02U +#define USB_DESCRIPTOR_TYPE_STRING 0x03U +#define USB_DESCRIPTOR_TYPE_INTERFACE 0x04U +#define USB_DESCRIPTOR_TYPE_ENDPOINT 0x05U +#define USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER 0x06U +#define USB_DESCRIPTOR_TYPE_OTHER_SPEED 0x07U +#define USB_DESCRIPTOR_TYPE_INTERFACE_POWER 0x08U +#define USB_DESCRIPTOR_TYPE_OTG 0x09U +#define USB_DESCRIPTOR_TYPE_DEBUG 0x0AU +#define USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION 0x0BU +#define USB_DESCRIPTOR_TYPE_BINARY_OBJECT_STORE 0x0FU +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY 0x10U +#define USB_DESCRIPTOR_TYPE_WIRELESS_ENDPOINTCOMP 0x11U + +/* Class Specific Descriptor */ +#define USB_CS_DESCRIPTOR_TYPE_DEVICE 0x21U +#define USB_CS_DESCRIPTOR_TYPE_CONFIGURATION 0x22U +#define USB_CS_DESCRIPTOR_TYPE_STRING 0x23U +#define USB_CS_DESCRIPTOR_TYPE_INTERFACE 0x24U +#define USB_CS_DESCRIPTOR_TYPE_ENDPOINT 0x25U + +#define USB_DESCRIPTOR_TYPE_SUPERSPEED_ENDPOINT_COMPANION 0x30U +#define USB_DESCRIPTOR_TYPE_SUPERSPEED_ISO_ENDPOINT_COMPANION 0x31U + +/* USB Device Classes */ +#define USB_DEVICE_CLASS_RESERVED 0x00 +#define USB_DEVICE_CLASS_AUDIO 0x01 +#define USB_DEVICE_CLASS_CDC 0x02 +#define USB_DEVICE_CLASS_HID 0x03 +#define USB_DEVICE_CLASS_MONITOR 0x04 +#define USB_DEVICE_CLASS_PHYSICAL 0x05 +#define USB_DEVICE_CLASS_IMAGE 0x06 +#define USB_DEVICE_CLASS_PRINTER 0x07 +#define USB_DEVICE_CLASS_MASS_STORAGE 0x08 +#define USB_DEVICE_CLASS_HUB 0x09 +#define USB_DEVICE_CLASS_CDC_DATA 0x0a +#define USB_DEVICE_CLASS_SMART_CARD 0x0b +#define USB_DEVICE_CLASS_SECURITY 0x0d +#define USB_DEVICE_CLASS_VIDEO 0x0e +#define USB_DEVICE_CLASS_HEALTHCARE 0x0f +#define USB_DEVICE_CLASS_DIAG_DEVICE 0xdc +#define USB_DEVICE_CLASS_WIRELESS 0xe0 +#define USB_DEVICE_CLASS_MISC 0xef +#define USB_DEVICE_CLASS_APP_SPECIFIC 0xfe +#define USB_DEVICE_CLASS_VEND_SPECIFIC 0xff + +/* usb string index define */ +#define USB_STRING_LANGID_INDEX 0x00 +#define USB_STRING_MFC_INDEX 0x01 +#define USB_STRING_PRODUCT_INDEX 0x02 +#define USB_STRING_SERIAL_INDEX 0x03 +#define USB_STRING_CONFIG_INDEX 0x04 +#define USB_STRING_INTERFACE_INDEX 0x05 +#define USB_STRING_OS_INDEX 0x06 +#define USB_STRING_MAX USB_STRING_OS_INDEX +/* + * Devices supporting Microsoft OS Descriptors store special string + * descriptor at fixed index (0xEE). It is read when a new device is + * attached to a computer for the first time. + */ +#define USB_OSDESC_STRING_DESC_INDEX 0xEE + +/* bmAttributes in Configuration Descriptor */ +#define USB_CONFIG_REMOTE_WAKEUP 0x20 +#define USB_CONFIG_POWERED_MASK 0x40 +#define USB_CONFIG_BUS_POWERED 0x80 +#define USB_CONFIG_SELF_POWERED 0xC0 + +/* bMaxPower in Configuration Descriptor */ +#define USB_CONFIG_POWER_MA(mA) ((mA) / 2) + +/* bEndpointAddress in Endpoint Descriptor */ +#define USB_ENDPOINT_DIRECTION_MASK 0x80 +#define USB_ENDPOINT_OUT(addr) ((addr) | 0x00) +#define USB_ENDPOINT_IN(addr) ((addr) | 0x80) + +/** + * USB endpoint direction and number. + */ +#define USB_EP_DIR_MASK 0x80U +#define USB_EP_DIR_IN 0x80U +#define USB_EP_DIR_OUT 0x00U + +/** Get endpoint index (number) from endpoint address */ +#define USB_EP_GET_IDX(ep) ((ep) & ~USB_EP_DIR_MASK) +/** Get direction from endpoint address */ +#define USB_EP_GET_DIR(ep) ((ep)&USB_EP_DIR_MASK) +/** Get endpoint address from endpoint index and direction */ +#define USB_EP_GET_ADDR(idx, dir) ((idx) | ((dir)&USB_EP_DIR_MASK)) +/** True if the endpoint is an IN endpoint */ +#define USB_EP_DIR_IS_IN(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_IN) +/** True if the endpoint is an OUT endpoint */ +#define USB_EP_DIR_IS_OUT(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_OUT) + +/* bmAttributes in Endpoint Descriptor */ +#define USB_ENDPOINT_TYPE_SHIFT 0 +#define USB_ENDPOINT_TYPE_CONTROL (0 << USB_ENDPOINT_TYPE_SHIFT) +#define USB_ENDPOINT_TYPE_ISOCHRONOUS (1 << USB_ENDPOINT_TYPE_SHIFT) +#define USB_ENDPOINT_TYPE_BULK (2 << USB_ENDPOINT_TYPE_SHIFT) +#define USB_ENDPOINT_TYPE_INTERRUPT (3 << USB_ENDPOINT_TYPE_SHIFT) +#define USB_ENDPOINT_TYPE_MASK (3 << USB_ENDPOINT_TYPE_SHIFT) + +#define USB_ENDPOINT_SYNC_SHIFT 2 +#define USB_ENDPOINT_SYNC_NO_SYNCHRONIZATION (0 << USB_ENDPOINT_SYNC_SHIFT) +#define USB_ENDPOINT_SYNC_ASYNCHRONOUS (1 << USB_ENDPOINT_SYNC_SHIFT) +#define USB_ENDPOINT_SYNC_ADAPTIVE (2 << USB_ENDPOINT_SYNC_SHIFT) +#define USB_ENDPOINT_SYNC_SYNCHRONOUS (3 << USB_ENDPOINT_SYNC_SHIFT) +#define USB_ENDPOINT_SYNC_MASK (3 << USB_ENDPOINT_SYNC_SHIFT) + +#define USB_ENDPOINT_USAGE_SHIFT 4 +#define USB_ENDPOINT_USAGE_DATA (0 << USB_ENDPOINT_USAGE_SHIFT) +#define USB_ENDPOINT_USAGE_FEEDBACK (1 << USB_ENDPOINT_USAGE_SHIFT) +#define USB_ENDPOINT_USAGE_IMPLICIT_FEEDBACK (2 << USB_ENDPOINT_USAGE_SHIFT) +#define USB_ENDPOINT_USAGE_MASK (3 << USB_ENDPOINT_USAGE_SHIFT) + +#define USB_ENDPOINT_MAX_ADJUSTABLE (1 << 7) + +/* wMaxPacketSize in Endpoint Descriptor */ +#define USB_MAXPACKETSIZE_SHIFT 0 +#define USB_MAXPACKETSIZE_MASK (0x7ff << USB_MAXPACKETSIZE_SHIFT) +#define USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT 11 +#define USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_NONE (0 << USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT) +#define USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_ONE (1 << USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT) +#define USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_TWO (2 << USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT) +#define USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_MASK (3 << USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT) + +/* bDevCapabilityType in Device Capability Descriptor */ +#define USB_DEVICE_CAPABILITY_WIRELESS_USB 1 +#define USB_DEVICE_CAPABILITY_USB_2_0_EXTENSION 2 +#define USB_DEVICE_CAPABILITY_SUPERSPEED_USB 3 +#define USB_DEVICE_CAPABILITY_CONTAINER_ID 4 +#define USB_DEVICE_CAPABILITY_PLATFORM 5 +#define USB_DEVICE_CAPABILITY_POWER_DELIVERY_CAPABILITY 6 +#define USB_DEVICE_CAPABILITY_BATTERY_INFO_CAPABILITY 7 +#define USB_DEVICE_CAPABILITY_PD_CONSUMER_PORT_CAPABILITY 8 +#define USB_DEVICE_CAPABILITY_PD_PROVIDER_PORT_CAPABILITY 9 +#define USB_DEVICE_CAPABILITY_SUPERSPEED_PLUS 10 +#define USB_DEVICE_CAPABILITY_PRECISION_TIME_MEASUREMENT 11 +#define USB_DEVICE_CAPABILITY_WIRELESS_USB_EXT 12 + +#define USB_BOS_CAPABILITY_EXTENSION 0x02 +#define USB_BOS_CAPABILITY_PLATFORM 0x05 + +/* OTG SET FEATURE Constants */ +#define USB_OTG_FEATURE_B_HNP_ENABLE 3 /* Enable B device to perform HNP */ +#define USB_OTG_FEATURE_A_HNP_SUPPORT 4 /* A device supports HNP */ +#define USB_OTG_FEATURE_A_ALT_HNP_SUPPORT 5 /* Another port on the A device supports HNP */ + +/* WinUSB Microsoft OS 2.0 descriptor request codes */ +#define WINUSB_REQUEST_GET_DESCRIPTOR_SET 0x07 +#define WINUSB_REQUEST_SET_ALT_ENUM 0x08 + +/* WinUSB Microsoft OS 2.0 descriptor sizes */ +#define WINUSB_DESCRIPTOR_SET_HEADER_SIZE 10 +#define WINUSB_FUNCTION_SUBSET_HEADER_SIZE 8 +#define WINUSB_FEATURE_COMPATIBLE_ID_SIZE 20 + +/* WinUSB Microsoft OS 2.0 Descriptor Types */ +#define WINUSB_SET_HEADER_DESCRIPTOR_TYPE 0x00 +#define WINUSB_SUBSET_HEADER_CONFIGURATION_TYPE 0x01 +#define WINUSB_SUBSET_HEADER_FUNCTION_TYPE 0x02 +#define WINUSB_FEATURE_COMPATIBLE_ID_TYPE 0x03 +#define WINUSB_FEATURE_REG_PROPERTY_TYPE 0x04 +#define WINUSB_FEATURE_MIN_RESUME_TIME_TYPE 0x05 +#define WINUSB_FEATURE_MODEL_ID_TYPE 0x06 +#define WINUSB_FEATURE_CCGP_DEVICE_TYPE 0x07 + +#define WINUSB_PROP_DATA_TYPE_REG_SZ 0x01 +#define WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ 0x07 + +/* WebUSB Descriptor Types */ +#define WEBUSB_DESCRIPTOR_SET_HEADER_TYPE 0x00 +#define WEBUSB_CONFIGURATION_SUBSET_HEADER_TYPE 0x01 +#define WEBUSB_FUNCTION_SUBSET_HEADER_TYPE 0x02 +#define WEBUSB_URL_TYPE 0x03 + +/* WebUSB Request Codes */ +#define WEBUSB_REQUEST_GET_URL 0x02 + +/* bScheme in URL descriptor */ +#define WEBUSB_URL_SCHEME_HTTP 0x00 +#define WEBUSB_URL_SCHEME_HTTPS 0x01 + +/* WebUSB Descriptor sizes */ +#define WEBUSB_DESCRIPTOR_SET_HEADER_SIZE 5 +#define WEBUSB_CONFIGURATION_SUBSET_HEADER_SIZE 4 +#define WEBUSB_FUNCTION_SUBSET_HEADER_SIZE 3 + +/* Setup packet definition used to read raw data from USB line */ +struct usb_setup_packet { + /** Request type. Bits 0:4 determine recipient, see + * \ref usb_request_recipient. Bits 5:6 determine type, see + * \ref usb_request_type. Bit 7 determines data transfer direction, see + * \ref usb_endpoint_direction. + */ + uint8_t bmRequestType; + + /** Request. If the type bits of bmRequestType are equal to + * \ref usb_request_type::LIBUSB_REQUEST_TYPE_STANDARD + * "USB_REQUEST_TYPE_STANDARD" then this field refers to + * \ref usb_standard_request. For other cases, use of this field is + * application-specific. */ + uint8_t bRequest; + + /** Value. Varies according to request */ + uint16_t wValue; + + /** Index. Varies according to request, typically used to pass an index + * or offset */ + uint16_t wIndex; + + /** Number of bytes to transfer */ + uint16_t wLength; +} __attribute__((packed)); + +#define USB_SIZEOF_SETUP_PACKET 8 + +struct usb_device_descriptor { + uint8_t bLength; /* Descriptor size in bytes = 18 */ + uint8_t bDescriptorType; /* DEVICE descriptor type = 1 */ + uint16_t bcdUSB; /* USB spec in BCD, e.g. 0x0200 */ + uint8_t bDeviceClass; /* Class code, if 0 see interface */ + uint8_t bDeviceSubClass; /* Sub-Class code, 0 if class = 0 */ + uint8_t bDeviceProtocol; /* Protocol, if 0 see interface */ + uint8_t bMaxPacketSize0; /* Endpoint 0 max. size */ + uint16_t idVendor; /* Vendor ID per USB-IF */ + uint16_t idProduct; /* Product ID per manufacturer */ + uint16_t bcdDevice; /* Device release # in BCD */ + uint8_t iManufacturer; /* Index to manufacturer string */ + uint8_t iProduct; /* Index to product string */ + uint8_t iSerialNumber; /* Index to serial number string */ + uint8_t bNumConfigurations; /* Number of possible configurations */ +} __attribute__((packed)); + +#define USB_SIZEOF_DEVICE_DESC 18 + +/** Standard Configuration Descriptor */ +struct usb_configuration_descriptor { + uint8_t bLength; /* Descriptor size in bytes = 9 */ + uint8_t bDescriptorType; /* CONFIGURATION type = 2 or 7 */ + uint16_t wTotalLength; /* Length of concatenated descriptors */ + uint8_t bNumInterfaces; /* Number of interfaces, this config. */ + uint8_t bConfigurationValue; /* Value to set this config. */ + uint8_t iConfiguration; /* Index to configuration string */ + uint8_t bmAttributes; /* Config. characteristics */ + uint8_t bMaxPower; /* Max.power from bus, 2mA units */ +} __attribute__((packed)); + +#define USB_SIZEOF_CONFIG_DESC 9 + + + +/** Standard Interface Descriptor */ +struct usb_interface_descriptor { + uint8_t bLength; /* Descriptor size in bytes = 9 */ + uint8_t bDescriptorType; /* INTERFACE descriptor type = 4 */ + uint8_t bInterfaceNumber; /* Interface no.*/ + uint8_t bAlternateSetting; /* Value to select this IF */ + uint8_t bNumEndpoints; /* Number of endpoints excluding 0 */ + uint8_t bInterfaceClass; /* Class code, 0xFF = vendor */ + uint8_t bInterfaceSubClass; /* Sub-Class code, 0 if class = 0 */ + uint8_t bInterfaceProtocol; /* Protocol, 0xFF = vendor */ + uint8_t iInterface; /* Index to interface string */ +} __attribute__((packed)); + +#define USB_SIZEOF_INTERFACE_DESC 9 + +/** Standard Endpoint Descriptor */ +struct usb_endpoint_descriptor { + uint8_t bLength; /* Descriptor size in bytes = 7 */ + uint8_t bDescriptorType; /* ENDPOINT descriptor type = 5 */ + uint8_t bEndpointAddress; /* Endpoint # 0 - 15 | IN/OUT */ + uint8_t bmAttributes; /* Transfer type */ + uint16_t wMaxPacketSize; /* Bits 10:0 = max. packet size */ + uint8_t bInterval; /* Polling interval in (micro) frames */ +} __attribute__((packed)); + +#define USB_SIZEOF_ENDPOINT_DESC 7 + +/** Unicode (UTF16LE) String Descriptor */ +struct usb_string_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bString; +} __attribute__((packed)); + +#define USB_SIZEOF_STRING_LANGID_DESC 4 + +/* USB Interface Association Descriptor */ +struct usb_interface_association_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bFirstInterface; + uint8_t bInterfaceCount; + uint8_t bFunctionClass; + uint8_t bFunctionSubClass; + uint8_t bFunctionProtocol; + uint8_t iFunction; +} __attribute__((packed)); + +#define USB_SIZEOF_IAD_DESC 8 + +/** USB device_qualifier descriptor */ +struct usb_device_qualifier_descriptor { + uint8_t bLength; /* Descriptor size in bytes = 10 */ + uint8_t bDescriptorType; /* DEVICE QUALIFIER type = 6 */ + uint16_t bcdUSB; /* USB spec in BCD, e.g. 0x0200 */ + uint8_t bDeviceClass; /* Class code, if 0 see interface */ + uint8_t bDeviceSubClass; /* Sub-Class code, 0 if class = 0 */ + uint8_t bDeviceProtocol; /* Protocol, if 0 see interface */ + uint8_t bMaxPacketSize; /* Endpoint 0 max. size */ + uint8_t bNumConfigurations; /* Number of possible configurations */ + uint8_t bReserved; /* Reserved = 0 */ +} __attribute__((packed)); + +#define USB_SIZEOF_DEVICE_QUALIFIER_DESC 10 + +/* Microsoft OS function descriptor. + * This can be used to request a specific driver (such as WINUSB) to be + * loaded on Windows. Unlike other descriptors, it is requested by a special + * request USB_REQ_GETMSFTOSDESCRIPTOR. + * More details: + * https://msdn.microsoft.com/en-us/windows/hardware/gg463179 + * And excellent explanation: + * https://github.com/pbatard/libwdi/wiki/WCID-Devices + * + * The device will have exactly one "Extended Compat ID Feature Descriptor", + * which may contain multiple "Function Descriptors" associated with + * different interfaces. + */ + +/* MS OS 1.0 string descriptor */ +struct usb_msosv1_string_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bString[14]; + uint8_t bMS_VendorCode; /* Vendor Code, used for a control request */ + uint8_t bPad; /* Padding byte for VendorCode look as UTF16 */ +} __attribute__((packed)); + +/* MS OS 1.0 Header descriptor */ +struct usb_msosv1_compat_id_header_descriptor { + uint32_t dwLength; + uint16_t bcdVersion; + uint16_t wIndex; + uint8_t bCount; + uint8_t reserved[7]; +} __attribute__((packed)); + +/* MS OS 1.0 Function descriptor */ +struct usb_msosv1_comp_id_function_descriptor { + uint8_t bFirstInterfaceNumber; + uint8_t reserved1; + uint8_t compatibleID[8]; + uint8_t subCompatibleID[8]; + uint8_t reserved2[6]; +} __attribute__((packed)); + +#define usb_msosv1_comp_id_create(x) \ + struct usb_msosv1_comp_id { \ + struct usb_msosv1_compat_id_header_descriptor compat_id_header; \ + struct usb_msosv1_comp_id_function_descriptor compat_id_function[x]; \ + }; + +struct usb_msosv1_descriptor { + uint8_t *string; + uint8_t string_len; + uint8_t vendor_code; + uint8_t *compat_id; + uint16_t compat_id_len; + uint8_t *comp_id_property; + uint16_t comp_id_property_len; +}; + + +/* MS OS 2.0 Header descriptor */ +struct usb_msosv2_header_descriptor { + uint32_t dwLength; + uint16_t bcdVersion; + uint16_t wIndex; + uint8_t bCount; +} __attribute__((packed)); + +/*Microsoft OS 2.0 set header descriptor*/ +struct usb_msosv2_set_header_descriptor { + uint16_t wLength; + uint16_t wDescriptorType; + uint32_t dwWindowsVersion; + uint16_t wDescriptorSetTotalLength; +} __attribute__((packed)); + +/* Microsoft OS 2.0 compatibleID descriptor*/ +struct usb_msosv2_comp_id_descriptor { + uint16_t wLength; + uint16_t wDescriptorType; + uint8_t compatibleID[8]; + uint8_t subCompatibleID[8]; +} __attribute__((packed)); + + +/* MS OS 2.0 property descriptor */ +struct usb_msosv2_property_descriptor { + uint16_t wLength; + uint16_t wDescriptorType; + uint32_t dwPropertyDataType; + uint16_t wPropertyNameLength; + const char *bPropertyName; + uint32_t dwPropertyDataLength; + const char *bPropertyData; +}; + +/* Microsoft OS 2.0 subset function descriptor */ +struct usb_msosv2_subset_function_descriptor { + uint16_t wLength; + uint16_t wDescriptorType; + uint8_t bFirstInterface; + uint8_t bReserved; + uint16_t wSubsetLength; +} __attribute__((packed)); + +struct usb_msosv2_descriptor { + uint8_t *compat_id; + uint16_t compat_id_len; + uint8_t vendor_code; +}; + +/* BOS header Descriptor */ +struct usb_bos_header_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumDeviceCaps; +} __attribute__((packed)); + +/* BOS Capability platform Descriptor */ +struct usb_bos_capability_platform_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + uint8_t bReserved; + uint8_t PlatformCapabilityUUID[16]; +} __attribute__((packed)); + +/* BOS Capability MS OS Descriptors version 2 */ +struct usb_bos_capability_msosv2_descriptor { + uint32_t dwWindowsVersion; + uint16_t wMSOSDescriptorSetTotalLength; + uint8_t bVendorCode; + uint8_t bAltEnumCode; +} __attribute__((packed)); + +/* BOS Capability webusb */ +struct usb_bos_capability_webusb_descriptor { + uint16_t bcdVersion; + uint8_t bVendorCode; + uint8_t iLandingPage; +} __attribute__((packed)); + +/* BOS Capability extension Descriptor*/ +struct usb_bos_capability_extension_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + uint32_t bmAttributes; +} __attribute__((packed)); + +/* Microsoft OS 2.0 Platform Capability Descriptor +* See https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/ +* microsoft-defined-usb-descriptors +* Adapted from the source: +* https://github.com/sowbug/weblight/blob/master/firmware/webusb.c +* (BSD-2) Thanks http://janaxelson.com/files/ms_os_20_descriptors.c +*/ +struct usb_bos_capability_platform_msosv2_descriptor { + struct usb_bos_capability_platform_descriptor platform_msos; + struct usb_bos_capability_msosv2_descriptor data_msosv2; +} __attribute__((packed)); + +/* WebUSB Platform Capability Descriptor: +* https://wicg.github.io/webusb/#webusb-platform-capability-descriptor +*/ +struct usb_bos_capability_platform_webusb_descriptor { + struct usb_bos_capability_platform_descriptor platform_webusb; + struct usb_bos_capability_webusb_descriptor data_webusb; +} __attribute__((packed)); + +struct usb_webusb_url_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bScheme; + char URL[]; +} __attribute__((packed)); + +struct usb_webusb_url_ex_descriptor { + uint8_t vendor_code; + uint8_t *string; + uint32_t string_len; +} __attribute__((packed)); + +struct usb_bos_descriptor { + uint8_t *string; + uint32_t string_len; +}; + +/* USB Device Capability Descriptor */ +struct usb_device_capability_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; +} __attribute__((packed)); + +/** USB descriptor header */ +struct usb_desc_header { + uint8_t bLength; /**< descriptor length */ + uint8_t bDescriptorType; /**< descriptor type */ +}; + +// clang-format off +#define USB_DEVICE_DESCRIPTOR_INIT(bcdUSB, bDeviceClass, bDeviceSubClass, bDeviceProtocol, idVendor, idProduct, bcdDevice, bNumConfigurations) \ + 0x12, /* bLength */ \ + USB_DESCRIPTOR_TYPE_DEVICE, /* bDescriptorType */ \ + WBVAL(bcdUSB), /* bcdUSB */ \ + bDeviceClass, /* bDeviceClass */ \ + bDeviceSubClass, /* bDeviceSubClass */ \ + bDeviceProtocol, /* bDeviceProtocol */ \ + 0x40, /* bMaxPacketSize */ \ + WBVAL(idVendor), /* idVendor */ \ + WBVAL(idProduct), /* idProduct */ \ + WBVAL(bcdDevice), /* bcdDevice */ \ + USB_STRING_MFC_INDEX, /* iManufacturer */ \ + USB_STRING_PRODUCT_INDEX, /* iProduct */ \ + USB_STRING_SERIAL_INDEX, /* iSerial */ \ + bNumConfigurations /* bNumConfigurations */ + +#define USB_CONFIG_DESCRIPTOR_INIT(wTotalLength, bNumInterfaces, bConfigurationValue, bmAttributes, bMaxPower) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_CONFIGURATION, /* bDescriptorType */ \ + WBVAL(wTotalLength), /* wTotalLength */ \ + bNumInterfaces, /* bNumInterfaces */ \ + bConfigurationValue, /* bConfigurationValue */ \ + 0x00, /* iConfiguration */ \ + bmAttributes, /* bmAttributes */ \ + USB_CONFIG_POWER_MA(bMaxPower) /* bMaxPower */ + +#define USB_INTERFACE_DESCRIPTOR_INIT(bInterfaceNumber, bAlternateSetting, bNumEndpoints, \ + bInterfaceClass, bInterfaceSubClass, bInterfaceProtocol, iInterface) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + bAlternateSetting, /* bAlternateSetting */ \ + bNumEndpoints, /* bNumEndpoints */ \ + bInterfaceClass, /* bInterfaceClass */ \ + bInterfaceSubClass, /* bInterfaceSubClass */ \ + bInterfaceProtocol, /* bInterfaceProtocol */ \ + iInterface /* iInterface */ + +#define USB_ENDPOINT_DESCRIPTOR_INIT(bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval) \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + bEndpointAddress, /* bEndpointAddress */ \ + bmAttributes, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + bInterval /* bInterval */ + +#define USB_IAD_INIT(bFirstInterface, bInterfaceCount, bFunctionClass, bFunctionSubClass, bFunctionProtocol) \ + 0x08, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ + bFirstInterface, /* bFirstInterface */ \ + bInterfaceCount, /* bInterfaceCount */ \ + bFunctionClass, /* bFunctionClass */ \ + bFunctionSubClass, /* bFunctionSubClass */ \ + bFunctionProtocol, /* bFunctionProtocol */ \ + 0x00 /* iFunction */ + +#define USB_LANGID_INIT(id) \ + 0x04, /* bLength */ \ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ \ + WBVAL(id) /* wLangID0 */ +// clang-format on #endif From 7968c89e5da997090af9795445556f00f1fe16c2 Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 10 Jun 2024 23:06:41 -0700 Subject: [PATCH 011/198] Modify header files --- .../drivers/usb/components/common/usb_errno.h | 298 ++++++++++++ .../drivers/usb/components/common/usb_hc.h | 139 ++++++ .../drivers/usb/components/common/usb_list.h | 453 ++++++++++++++++++ .../drivers/usb/components/common/usb_log.h | 77 +++ .../drivers/usb/components/common/usb_util.h | 200 ++++++++ .../drivers/usb/components/core/usbh_core.c | 7 +- 6 files changed, 1173 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_errno.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_errno.h index 5f7a59859..a56bb9162 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_errno.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_errno.h @@ -1,6 +1,304 @@ +/* + * Apache NuttX + * Copyright 2020 The Apache Software Foundation + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef USB_ERROR_H_ #define USB_ERROR_H_ +#ifndef CONFIG_USB_ERROR_USE_SYSTEM + +#define EPERM 1 +#define EPERM_STR "Operation not permitted" +#define ENOENT 2 +#define ENOENT_STR "No such file or directory" +#define ESRCH 3 +#define ESRCH_STR "No such process" +#define EINTR 4 +#define EINTR_STR "Interrupted system call" +#define EIO 5 +#define EIO_STR "I/O error" +#define ENXIO 6 +#define ENXIO_STR "No such device or address" +#define E2BIG 7 +#define E2BIG_STR "Arg list too long" +#define ENOEXEC 8 +#define ENOEXEC_STR "Exec format error" +#define EBADF 9 +#define EBADF_STR "Bad file number" +#define ECHILD 10 +#define ECHILD_STR "No child processes" +#define EAGAIN 11 +#define EWOULDBLOCK EAGAIN +#define EAGAIN_STR "Try again" +#define ENOMEM 12 +#define ENOMEM_STR "Out of memory" +#define EACCES 13 +#define EACCES_STR "Permission denied" +#define EFAULT 14 /* Linux errno extension */ +#define EFAULT_STR "Bad address" +#define ENOTBLK 15 +#define ENOTBLK_STR "Block device required" +#define EBUSY 16 +#define EBUSY_STR "Device or resource busy" +#define EEXIST 17 +#define EEXIST_STR "File exists" +#define EXDEV 18 +#define EXDEV_STR "Cross-device link" +#define ENODEV 19 +#define ENODEV_STR "No such device" +#define ENOTDIR 20 +#define ENOTDIR_STR "Not a directory" +#define EISDIR 21 +#define EISDIR_STR "Is a directory" +#define EINVAL 22 +#define EINVAL_STR "Invalid argument" +#define ENFILE 23 +#define ENFILE_STR "File table overflow" +#define EMFILE 24 +#define EMFILE_STR "Too many open files" +#define ENOTTY 25 +#define ENOTTY_STR "Not a typewriter" +#define ETXTBSY 26 +#define ETXTBSY_STR "Text file busy" +#define EFBIG 27 +#define EFBIG_STR "File too large" +#define ENOSPC 28 +#define ENOSPC_STR "No space left on device" +#define ESPIPE 29 +#define ESPIPE_STR "Illegal seek" +#define EROFS 30 +#define EROFS_STR "Read-only file system" +#define EMLINK 31 +#define EMLINK_STR "Too many links" +#define EPIPE 32 +#define EPIPE_STR "Broken pipe" +#define EDOM 33 +#define EDOM_STR "Math argument out of domain of func" +#define ERANGE 34 +#define ERANGE_STR "Math result not representable" +#define ENOMSG 35 +#define ENOMSG_STR "No message of desired type" +#define EIDRM 36 +#define EIDRM_STR "Identifier removed" +#define ECHRNG 37 /* Linux errno extension */ +#define ECHRNG_STR "Channel number out of range" +#define EL2NSYNC 38 /* Linux errno extension */ +#define EL2NSYNC_STR "Level 2 not synchronized" +#define EL3HLT 39 /* Linux errno extension */ +#define EL3HLT_STR "Level 3 halted" +#define EL3RST 40 /* Linux errno extension */ +#define EL3RST_STR "Level 3 reset" +#define ELNRNG 41 /* Linux errno extension */ +#define ELNRNG_STR "Link number out of range" +#define EUNATCH 42 /* Linux errno extension */ +#define EUNATCH_STR "Protocol driver not attached" +#define ENOCSI 43 /* Linux errno extension */ +#define ENOCSI_STR "No CSI structure available" +#define EL2HLT 44 /* Linux errno extension */ +#define EL2HLT_STR "Level 2 halted" +#define EDEADLK 45 +#define EDEADLK_STR "Resource deadlock would occur" +#define ENOLCK 46 +#define ENOLCK_STR "No record locks available" + +#define EBADE 50 /* Linux errno extension */ +#define EBADE_STR "Invalid exchange" +#define EBADR 51 /* Linux errno extension */ +#define EBADR_STR "Invalid request descriptor" +#define EXFULL 52 /* Linux errno extension */ +#define EXFULL_STR "Exchange full" +#define ENOANO 53 /* Linux errno extension */ +#define ENOANO_STR "No anode" +#define EBADRQC 54 /* Linux errno extension */ +#define EBADRQC_STR "Invalid request code" +#define EBADSLT 55 /* Linux errno extension */ +#define EBADSLT_STR "Invalid slot" +#define EDEADLOCK 56 /* Linux errno extension */ +#define EDEADLOCK_STR "File locking deadlock error" +#define EBFONT 57 /* Linux errno extension */ +#define EBFONT_STR "Bad font file format" + +#define ENOSTR 60 +#define ENOSTR_STR "Device not a stream" +#define ENODATA 61 +#define ENODATA_STR "No data available" +#define ETIME 62 +#define ETIME_STR "Timer expired" +#define ENOSR 63 +#define ENOSR_STR "Out of streams resources" +#define ENONET 64 /* Linux errno extension */ +#define ENONET_STR "Machine is not on the network" +#define ENOPKG 65 /* Linux errno extension */ +#define ENOPKG_STR "Package not installed" +#define EREMOTE 66 /* Linux errno extension */ +#define EREMOTE_STR "Object is remote" +#define ENOLINK 67 +#define ENOLINK_STR "Link has been severed" +#define EADV 68 /* Linux errno extension */ +#define EADV_STR "Advertise error" +#define ESRMNT 69 /* Linux errno extension */ +#define ESRMNT_STR "Srmount error" +#define ECOMM 70 /* Linux errno extension */ +#define ECOMM_STR "Communication error on send" +#define EPROTO 71 +#define EPROTO_STR "Protocol error" + +#define EMULTIHOP 74 +#define EMULTIHOP_STR "Multihop attempted" +#define ELBIN 75 /* Linux errno extension */ +#define ELBIN_STR "Inode is remote" +#define EDOTDOT 76 /* Linux errno extension */ +#define EDOTDOT_STR "RFS specific error" +#define EBADMSG 77 +#define EBADMSG_STR "Not a data message" + +#define EFTYPE 79 +#define EFTYPE_STR "Inappropriate file type or format" +#define ENOTUNIQ 80 /* Linux errno extension */ +#define ENOTUNIQ_STR "Name not unique on network" +#define EBADFD 81 /* Linux errno extension */ +#define EBADFD_STR "File descriptor in bad state" +#define EREMCHG 82 /* Linux errno extension */ +#define EREMCHG_STR "Remote address changed" +#define ELIBACC 83 /* Linux errno extension */ +#define ELIBACC_STR "Can not access a needed shared library" +#define ELIBBAD 84 /* Linux errno extension */ +#define ELIBBAD_STR "Accessing a corrupted shared library" +#define ELIBSCN 85 /* Linux errno extension */ +#define ELIBSCN_STR ".lib section in a.out corrupted" +#define ELIBMAX 86 /* Linux errno extension */ +#define ELIBMAX_STR "Attempting to link in too many shared libraries" +#define ELIBEXEC 87 /* Linux errno extension */ +#define ELIBEXEC_STR "Cannot exec a shared library directly" +#define ENOSYS 88 +#define ENOSYS_STR "Function not implemented" +#define ENMFILE 89 /* Cygwin */ +#define ENMFILE_STR "No more files" +#define ENOTEMPTY 90 +#define ENOTEMPTY_STR "Directory not empty" +#define ENAMETOOLONG 91 +#define ENAMETOOLONG_STR "File name too long" +#define ELOOP 92 +#define ELOOP_STR "Too many symbolic links encountered" + +#define EOPNOTSUPP 95 +#define EOPNOTSUPP_STR "Operation not supported on transport endpoint" +#define EPFNOSUPPORT 96 +#define EPFNOSUPPORT_STR "Protocol family not supported" + +#define ECONNRESET 104 +#define ECONNRESET_STR "Connection reset by peer" +#define ENOBUFS 105 +#define ENOBUFS_STR "No buffer space available" +#define EAFNOSUPPORT 106 +#define EAFNOSUPPORT_STR "Address family not supported by protocol" +#define EPROTOTYPE 107 +#define EPROTOTYPE_STR "Protocol wrong type for socket" +#define ENOTSOCK 108 +#define ENOTSOCK_STR "Socket operation on non-socket" +#define ENOPROTOOPT 109 +#define ENOPROTOOPT_STR "Protocol not available" +#define ESHUTDOWN 110 /* Linux errno extension */ +#define ESHUTDOWN_STR "Cannot send after transport endpoint shutdown" +#define ECONNREFUSED 111 +#define ECONNREFUSED_STR "Connection refused" +#define EADDRINUSE 112 +#define EADDRINUSE_STR "Address already in use" +#define ECONNABORTED 113 +#define ECONNABORTED_STR "Software caused connection abort" +#define ENETUNREACH 114 +#define ENETUNREACH_STR "Network is unreachable" +#define ENETDOWN 115 +#define ENETDOWN_STR "Network is down" +#define ETIMEDOUT 116 +#define ETIMEDOUT_STR "Connection timed out" +#define EHOSTDOWN 117 +#define EHOSTDOWN_STR "Host is down" +#define EHOSTUNREACH 118 +#define EHOSTUNREACH_STR "No route to host" +#define EINPROGRESS 119 +#define EINPROGRESS_STR "Operation now in progress" +#define EALREADY 120 +#define EALREADY_STR "Socket already connected" +#define EDESTADDRREQ 121 +#define EDESTADDRREQ_STR "Destination address required" +#define EMSGSIZE 122 +#define EMSGSIZE_STR "Message too long" +#define EPROTONOSUPPORT 123 +#define EPROTONOSUPPORT_STR "Protocol not supported" +#define ESOCKTNOSUPPORT 124 /* Linux errno extension */ +#define ESOCKTNOSUPPORT_STR "Socket type not supported" +#define EADDRNOTAVAIL 125 +#define EADDRNOTAVAIL_STR "Cannot assign requested address" +#define ENETRESET 126 +#define ENETRESET_STR "Network dropped connection because of reset" +#define EISCONN 127 +#define EISCONN_STR "Transport endpoint is already connected" +#define ENOTCONN 128 +#define ENOTCONN_STR "Transport endpoint is not connected" +#define ETOOMANYREFS 129 +#define ETOOMANYREFS_STR "Too many references: cannot splice" +#define EPROCLIM 130 +#define EPROCLIM_STR "Limit would be exceeded by attempted fork" +#define EUSERS 131 +#define EUSERS_STR "Too many users" +#define EDQUOT 132 +#define EDQUOT_STR "Quota exceeded" +#define ESTALE 133 +#define ESTALE_STR "Stale NFS file handle" +#define ENOTSUP 134 +#define ENOTSUP_STR "Not supported" +#define ENOMEDIUM 135 /* Linux errno extension */ +#define ENOMEDIUM_STR "No medium found" +#define ENOSHARE 136 /* Cygwin */ +#define ENOSHARE_STR "No such host or network path" +#define ECASECLASH 137 /* Cygwin */ +#define ECASECLASH_STR "Filename exists with different case" +#define EILSEQ 138 +#define EILSEQ_STR "Illegal byte sequence" +#define EOVERFLOW 139 +#define EOVERFLOW_STR "Value too large for defined data type" +#define ECANCELED 140 +#define ECANCELED_STR "Operation cancelled" +#define ENOTRECOVERABLE 141 +#define ENOTRECOVERABLE_STR "State not recoverable" +#define EOWNERDEAD 142 +#define EOWNERDEAD_STR "Previous owner died" +#define ESTRPIPE 143 /* Linux errno extension */ +#define ESTRPIPE_STR "Streams pipe error" + +#define __ELASTERROR 2000 /* Users can add values starting here */ +#else +#include +#endif +/**************************************************************************** + * Public Type Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* Return a pointer to the thread specific errno. */ + +int *__errno(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_hc.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_hc.h index fc910b9b8..26070dd49 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_hc.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_hc.h @@ -1,7 +1,146 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ + #ifndef USB_HC_H_ #define USB_HC_H_ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void (*usbh_complete_callback_t)(void *arg, int nbytes); +typedef void *usbh_pipe_t; + +struct usbh_bus; + +/** + * @brief USB Endpoint Configuration. + * + * Structure containing the USB endpoint configuration. + */ +struct usbh_endpoint_cfg { + struct usbh_hubport *hport; + uint8_t ep_addr; /* Endpoint addr with direction */ + uint8_t ep_type; /* Endpoint type */ + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_interval; /* Endpoint interval */ + uint8_t mult; /* Endpoint additional transcation */ +}; + +/** + * @brief USB Iso Configuration. + * + * Structure containing the USB Iso configuration. + */ +struct usbh_iso_frame_packet { + uint8_t *transfer_buffer; + uint32_t transfer_buffer_length; + uint32_t actual_length; + int errorcode; +}; + +/** + * @brief USB Urb Configuration. + * + * Structure containing the USB Urb configuration. + */ +struct usbh_urb { + usbh_pipe_t pipe; + struct usb_setup_packet *setup; + uint8_t *transfer_buffer; + uint32_t transfer_buffer_length; + int transfer_flags; + uint32_t actual_length; + uint32_t timeout; + int errorcode; + uint32_t num_of_iso_packets; + uint32_t start_frame; + usbh_complete_callback_t complete; + void *arg; + struct usbh_iso_frame_packet iso_packet[0]; +}; + +/** + * @brief usb host controller hardware init. + * + * @return On success will return 0, and others indicate fail. + */ +int usb_hc_init(uint32_t id); + +/** + * @brief Get frame number. + * + * @return frame number. + */ +uint16_t usbh_get_frame_number(void); +/** + * @brief control roothub. + * + * @param usb usb bus instance + * @param setup setup request buffer. + * @param buf buf for reading response or write data. + * @return On success will return 0, and others indicate fail. + */ +int usbh_roothub_control(struct usbh_bus *usb, struct usb_setup_packet *setup, uint8_t *buf); + +/** + * @brief reconfig endpoint pipe. + * + * @param pipe A memory allocated for pipe. + * @param dev_addr device address. + * @param ep_mps endpoint max packet size. + * @param mult endpoint additional transcation + * @return On success will return 0, and others indicate fail. + */ +int usbh_ep_pipe_reconfigure(struct usbh_bus *usb, usbh_pipe_t pipe, uint8_t dev_addr, uint8_t ep_mps, uint8_t mult); + +/** + * @brief Allocate pipe for endpoint + * + * @param pipe A memory location provided by the caller in which to save the allocated pipe. + * @param ep_cfg Describes the endpoint info to be allocated. + * @return On success will return 0, and others indicate fail. + */ +int usbh_pipe_alloc(usbh_pipe_t *pipe, const struct usbh_endpoint_cfg *ep_cfg); + +/** + * @brief Free a pipe in which saves endpoint info. + * + * @param pipe A memory location provided by the caller in which to free the allocated endpoint info. + * @return On success will return 0, and others indicate fail. + */ +int usbh_pipe_free(usbh_pipe_t pipe); + +/** + * @brief Submit a usb transfer request to an endpoint. + * + * If timeout is not zero, this function will be in poll transfer mode, + * otherwise will be in async transfer mode. + * + * @param urb Usb request block. + * @return On success will return 0, and others indicate fail. + */ +int usbh_submit_urb(struct usbh_urb *urb); + +/** + * @brief Cancel a transfer request. + * + * This function will call When calls usbh_submit_urb and return -ETIMEOUT or -ESHUTDOWN. + * + * @param urb Usb request block. + * @return On success will return 0, and others indicate fail. + */ +int usbh_kill_urb(struct usbh_urb *urb); + +#ifdef __cplusplus +} +#endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_list.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_list.h index 44f28777b..7566d879e 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_list.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_list.h @@ -1,7 +1,460 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef USB_LIST_H_ #define USB_LIST_H_ +#include +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** + * usb_container_of - return the member address of ptr, if the type of ptr is the + * struct type. + */ +#define usb_container_of(ptr, type, member) \ + ((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member))) + +/** + * Single List structure + */ +struct usb_slist_node { + struct usb_slist_node *next; /**< point to next node. */ +}; +typedef struct usb_slist_node usb_slist_t; /**< Type for single list. */ + +/** + * @brief initialize a single list + * + * @param l the single list to be initialized + */ +static inline void usb_slist_init(usb_slist_t *l) +{ + l->next = NULL; +} + +static inline void usb_slist_add_head(usb_slist_t *l, usb_slist_t *n) +{ + n->next = l->next; + l->next = n; +} + +static inline void usb_slist_add_tail(usb_slist_t *l, usb_slist_t *n) +{ + usb_slist_t *tmp = l; + + while (tmp->next) { + tmp = tmp->next; + } + + /* append the node to the tail */ + tmp->next = n; + n->next = NULL; +} + +static inline void usb_slist_insert(usb_slist_t *l, usb_slist_t *next, usb_slist_t *n) +{ + if (!next) { + usb_slist_add_tail(next, l); + return; + } + + while (l->next) { + if (l->next == next) { + l->next = n; + n->next = next; + } + + l = l->next; + } +} + +static inline usb_slist_t *usb_slist_remove(usb_slist_t *l, usb_slist_t *n) +{ + usb_slist_t *tmp = l; + /* remove slist head */ + while (tmp->next && tmp->next != n) { + tmp = tmp->next; + } + + /* remove node */ + if (tmp->next != (usb_slist_t *)0) { + tmp->next = tmp->next->next; + } + + return l; +} + +static inline unsigned int usb_slist_len(const usb_slist_t *l) +{ + unsigned int len = 0; + const usb_slist_t *list = l->next; + + while (list != NULL) { + list = list->next; + len++; + } + + return len; +} + +static inline unsigned int usb_slist_contains(usb_slist_t *l, usb_slist_t *n) +{ + while (l->next) { + if (l->next == n) { + return 0; + } + + l = l->next; + } + + return 1; +} + +static inline usb_slist_t *usb_slist_head(usb_slist_t *l) +{ + return l->next; +} + +static inline usb_slist_t *usb_slist_tail(usb_slist_t *l) +{ + while (l->next) { + l = l->next; + } + + return l; +} + +static inline usb_slist_t *usb_slist_next(usb_slist_t *n) +{ + return n->next; +} + +static inline int usb_slist_isempty(usb_slist_t *l) +{ + return l->next == NULL; +} + +/** + * @brief initialize a slist object + */ +#define USB_SLIST_OBJECT_INIT(object) \ + { \ + NULL \ + } + +/** + * @brief initialize a slist object + */ +#define USB_SLIST_DEFINE(slist) \ + usb_slist_t slist = { NULL } + +/** + * @brief get the struct for this single list node + * @param node the entry point + * @param type the type of structure + * @param member the name of list in structure + */ +#define usb_slist_entry(node, type, member) \ + usb_container_of(node, type, member) + +/** + * usb_slist_first_entry - get the first element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define usb_slist_first_entry(ptr, type, member) \ + usb_slist_entry((ptr)->next, type, member) + +/** + * usb_slist_tail_entry - get the tail element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define usb_slist_tail_entry(ptr, type, member) \ + usb_slist_entry(usb_slist_tail(ptr), type, member) + +/** + * usb_slist_first_entry_or_null - get the first element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define usb_slist_first_entry_or_null(ptr, type, member) \ + (usb_slist_isempty(ptr) ? NULL : usb_slist_first_entry(ptr, type, member)) + +/** + * usb_slist_for_each - iterate over a single list + * @pos: the usb_slist_t * to use as a loop cursor. + * @head: the head for your single list. + */ +#define usb_slist_for_each(pos, head) \ + for (pos = (head)->next; pos != NULL; pos = pos->next) + +#define usb_slist_for_each_safe(pos, next, head) \ + for (pos = (head)->next, next = pos->next; pos; \ + pos = next, next = pos->next) + +/** + * usb_slist_for_each_entry - iterate over single list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your single list. + * @member: the name of the list_struct within the struct. + */ +#define usb_slist_for_each_entry(pos, head, member) \ + for (pos = usb_slist_entry((head)->next, typeof(*pos), member); \ + &pos->member != (NULL); \ + pos = usb_slist_entry(pos->member.next, typeof(*pos), member)) + +#define usb_slist_for_each_entry_safe(pos, n, head, member) \ + for (pos = usb_slist_entry((head)->next, typeof(*pos), member), \ + n = usb_slist_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (NULL); \ + pos = n, n = usb_slist_entry(pos->member.next, typeof(*pos), member)) + +/** + * Double List structure + */ +struct usb_dlist_node { + struct usb_dlist_node *next; /**< point to next node. */ + struct usb_dlist_node *prev; /**< point to prev node. */ +}; +typedef struct usb_dlist_node usb_dlist_t; /**< Type for lists. */ + +/** + * @brief initialize a list + * + * @param l list to be initialized + */ +static inline void usb_dlist_init(usb_dlist_t *l) +{ + l->next = l->prev = l; +} + +/** + * @brief insert a node after a list + * + * @param l list to insert it + * @param n new node to be inserted + */ +static inline void usb_dlist_insert_after(usb_dlist_t *l, usb_dlist_t *n) +{ + l->next->prev = n; + n->next = l->next; + + l->next = n; + n->prev = l; +} + +/** + * @brief insert a node before a list + * + * @param n new node to be inserted + * @param l list to insert it + */ +static inline void usb_dlist_insert_before(usb_dlist_t *l, usb_dlist_t *n) +{ + l->prev->next = n; + n->prev = l->prev; + + l->prev = n; + n->next = l; +} + +/** + * @brief remove node from list. + * @param n the node to remove from the list. + */ +static inline void usb_dlist_remove(usb_dlist_t *n) +{ + n->next->prev = n->prev; + n->prev->next = n->next; + + n->next = n->prev = n; +} + +/** + * @brief move node from list. + * @param n the node to remove from the list. + */ +static inline void usb_dlist_move_head(usb_dlist_t *l, usb_dlist_t *n) +{ + usb_dlist_remove(n); + usb_dlist_insert_after(l, n); +} + +/** + * @brief move node from list. + * @param n the node to remove from the list. + */ +static inline void usb_dlist_move_tail(usb_dlist_t *l, usb_dlist_t *n) +{ + usb_dlist_remove(n); + usb_dlist_insert_before(l, n); +} + +/** + * @brief tests whether a list is empty + * @param l the list to test. + */ +static inline int usb_dlist_isempty(const usb_dlist_t *l) +{ + return l->next == l; +} + +/** + * @brief get the list length + * @param l the list to get. + */ +static inline unsigned int usb_dlist_len(const usb_dlist_t *l) +{ + unsigned int len = 0; + const usb_dlist_t *p = l; + + while (p->next != l) { + p = p->next; + len++; + } + + return len; +} + +/** + * @brief initialize a dlist object + */ +#define USB_DLIST_OBJECT_INIT(object) \ + { \ + &(object), &(object) \ + } +/** + * @brief initialize a dlist object + */ +#define USB_DLIST_DEFINE(list) \ + usb_dlist_t list = { &(list), &(list) } + +/** + * @brief get the struct for this entry + * @param node the entry point + * @param type the type of structure + * @param member the name of list in structure + */ +#define usb_dlist_entry(node, type, member) \ + usb_container_of(node, type, member) + +/** + * dlist_first_entry - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define usb_dlist_first_entry(ptr, type, member) \ + usb_dlist_entry((ptr)->next, type, member) +/** + * dlist_first_entry_or_null - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define usb_dlist_first_entry_or_null(ptr, type, member) \ + (usb_dlist_isempty(ptr) ? NULL : usb_dlist_first_entry(ptr, type, member)) + +/** + * usb_dlist_for_each - iterate over a list + * @pos: the usb_dlist_t * to use as a loop cursor. + * @head: the head for your list. + */ +#define usb_dlist_for_each(pos, head) \ + for (pos = (head)->next; pos != (head); pos = pos->next) + +/** + * usb_dlist_for_each_prev - iterate over a list + * @pos: the dlist_t * to use as a loop cursor. + * @head: the head for your list. + */ +#define usb_dlist_for_each_prev(pos, head) \ + for (pos = (head)->prev; pos != (head); pos = pos->prev) + +/** + * usb_dlist_for_each_safe - iterate over a list safe against removal of list entry + * @pos: the dlist_t * to use as a loop cursor. + * @n: another dlist_t * to use as temporary storage + * @head: the head for your list. + */ +#define usb_dlist_for_each_safe(pos, n, head) \ + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) + +#define usb_dlist_for_each_prev_safe(pos, n, head) \ + for (pos = (head)->prev, n = pos->prev; pos != (head); \ + pos = n, n = pos->prev) +/** + * usb_dlist_for_each_entry - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define usb_dlist_for_each_entry(pos, head, member) \ + for (pos = usb_dlist_entry((head)->next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = usb_dlist_entry(pos->member.next, typeof(*pos), member)) + +/** + * usb_usb_dlist_for_each_entry_reverse - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define usb_dlist_for_each_entry_reverse(pos, head, member) \ + for (pos = usb_dlist_entry((head)->prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = usb_dlist_entry(pos->member.prev, typeof(*pos), member)) + +/** + * usb_usb_dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define usb_dlist_for_each_entry_safe(pos, n, head, member) \ + for (pos = usb_dlist_entry((head)->next, typeof(*pos), member), \ + n = usb_dlist_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = usb_dlist_entry(n->member.next, typeof(*n), member)) + +/** + * usb_usb_dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define usb_dlist_for_each_entry_safe_reverse(pos, n, head, member) \ + for (pos = usb_dlist_entry((head)->prev, typeof(*pos), field), \ + n = usb_dlist_entry(pos->member.prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = usb_dlist_entry(pos->member.prev, typeof(*pos), member)) + +#ifdef __cplusplus +} +#endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_log.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_log.h index 09b3c911a..9ee105823 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_log.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_log.h @@ -1,9 +1,86 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef USB_LOG_H_ #define USB_LOG_H_ +#include +/* DEBUG level */ +#define USB_DBG_ERROR 0 +#define USB_DBG_WARNING 1 +#define USB_DBG_INFO 2 +#define USB_DBG_LOG 3 +#ifndef USB_DBG_TAG +#define USB_DBG_TAG "USB" +#endif +/* + * The color for terminal (foreground) + * BLACK 30 + * RED 31 + * GREEN 32 + * YELLOW 33 + * BLUE 34 + * PURPLE 35 + * CYAN 36 + * WHITE 37 + */ +#ifdef CONFIG_USB_PRINTF_COLOR_ENABLE +#define _USB_DBG_COLOR(n) CONFIG_USB_PRINTF("\033[" #n "m") +#define _USB_DBG_LOG_HDR(lvl_name, color_n) \ + CONFIG_USB_PRINTF("\033[" #color_n "m[" lvl_name "/" USB_DBG_TAG "] ") +#define _USB_DBG_LOG_X_END \ + CONFIG_USB_PRINTF("\033[0m") +#else +#define _USB_DBG_COLOR(n) +#define _USB_DBG_LOG_HDR(lvl_name, color_n) \ + CONFIG_USB_PRINTF("[" lvl_name "/" USB_DBG_TAG "] ") +#define _USB_DBG_LOG_X_END +#endif + +#define usb_dbg_log_line(lvl, color_n, fmt, ...) \ + do { \ + _USB_DBG_LOG_HDR(lvl, color_n); \ + CONFIG_USB_PRINTF(fmt, ##__VA_ARGS__); \ + _USB_DBG_LOG_X_END; \ + } while (0) + +#if (CONFIG_USB_DBG_LEVEL >= USB_DBG_LOG) +#define USB_LOG_DBG(fmt, ...) usb_dbg_log_line("D", 0, fmt, ##__VA_ARGS__) +#else +#define USB_LOG_DBG(...) {} +#endif + +#if (CONFIG_USB_DBG_LEVEL >= USB_DBG_INFO) +#define USB_LOG_INFO(fmt, ...) usb_dbg_log_line("I", 32, fmt, ##__VA_ARGS__) +#else +#define USB_LOG_INFO(...) {} +#endif + +#if (CONFIG_USB_DBG_LEVEL >= USB_DBG_WARNING) +#define USB_LOG_WRN(fmt, ...) usb_dbg_log_line("W", 33, fmt, ##__VA_ARGS__) +#else +#define USB_LOG_WRN(...) {} +#endif + +#if (CONFIG_USB_DBG_LEVEL >= USB_DBG_ERROR) +#define USB_LOG_ERR(fmt, ...) usb_dbg_log_line("E", 31, fmt, ##__VA_ARGS__) +#else +#define USB_LOG_ERR(...) {} +#endif + +#define USB_LOG_RAW(...) CONFIG_USB_PRINTF(__VA_ARGS__) + +void usb_assert(const char *filename, int linenum); +#define USB_ASSERT(f) \ + do { \ + if (!(f)) \ + usb_assert(__FILE__, __LINE__); \ + } while (0) #endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_util.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_util.h index 5f6aa22d1..aac7e2f6e 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_util.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_util.h @@ -1,7 +1,207 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef USB_UTIL_H_ #define USB_TIIL_H_ +#if defined(__CC_ARM) +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION +#define __PACKED_UNION __packed union +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#elif defined(__GNUC__) +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION +#define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#elif defined(__ICCARM__) || defined(__ICCRX__) +#ifndef __USED +#if __ICCARM_V8 +#define __USED __attribute__((used)) +#else +#define __USED __root +#endif +#endif +#ifndef __WEAK +#if __ICCARM_V8 +#define __WEAK __attribute__((weak)) +#else +#define __WEAK _Pragma("__weak") +#endif +#endif + +#ifndef __PACKED +#if __ICCARM_V8 +#define __PACKED __attribute__((packed, aligned(1))) +#else +/* Needs IAR language extensions */ +#define __PACKED __packed +#endif +#endif + +#ifndef __PACKED_STRUCT +#if __ICCARM_V8 +#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#else +/* Needs IAR language extensions */ +#define __PACKED_STRUCT __packed struct +#endif +#endif + +#ifndef __PACKED_UNION +#if __ICCARM_V8 +#define __PACKED_UNION union __attribute__((packed, aligned(1))) +#else +/* Needs IAR language extensions */ +#define __PACKED_UNION __packed union +#endif +#endif + +#ifndef __ALIGNED +#if __ICCARM_V8 +#define __ALIGNED(x) __attribute__((aligned(x))) +#elif (__VER__ >= 7080000) +/* Needs IAR language extensions */ +#define __ALIGNED(x) __attribute__((aligned(x))) +#else +#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. +#define __ALIGNED(x) +#endif +#endif + +#endif + +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__((aligned(4))) +#endif + +#ifndef ARG_UNUSED +#define ARG_UNUSED(x) (void)(x) +#endif + +#ifndef LO_BYTE +#define LO_BYTE(x) ((uint8_t)(x & 0x00FF)) +#endif + +#ifndef HI_BYTE +#define HI_BYTE(x) ((uint8_t)((x & 0xFF00) >> 8)) +#endif + +#ifndef MAX +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +#ifndef MIN +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef BCD +#define BCD(x) ((((x) / 10) << 4) | ((x) % 10)) +#endif + +#ifdef BIT +#undef BIT +#define BIT(n) (1UL << (n)) +#else +#define BIT(n) (1UL << (n)) +#endif + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(array) \ + ((int)((sizeof(array) / sizeof((array)[0])))) +#endif + +#ifndef BSWAP16 +#define BSWAP16(u16) (__builtin_bswap16(u16)) +#endif +#ifndef BSWAP32 +#define BSWAP32(u32) (__builtin_bswap32(u32)) +#endif + +#define GET_BE16(field) \ + (((uint16_t)(field)[0] << 8) | ((uint16_t)(field)[1])) + +#define GET_BE32(field) \ + (((uint32_t)(field)[0] << 24) | ((uint32_t)(field)[1] << 16) | ((uint32_t)(field)[2] << 8) | ((uint32_t)(field)[3] << 0)) + +#define SET_BE16(field, value) \ + do { \ + (field)[0] = (uint8_t)((value) >> 8); \ + (field)[1] = (uint8_t)((value) >> 0); \ + } while (0) + +#define SET_BE24(field, value) \ + do { \ + (field)[0] = (uint8_t)((value) >> 16); \ + (field)[1] = (uint8_t)((value) >> 8); \ + (field)[2] = (uint8_t)((value) >> 0); \ + } while (0) + +#define SET_BE32(field, value) \ + do { \ + (field)[0] = (uint8_t)((value) >> 24); \ + (field)[1] = (uint8_t)((value) >> 16); \ + (field)[2] = (uint8_t)((value) >> 8); \ + (field)[3] = (uint8_t)((value) >> 0); \ + } while (0) + +#define WBVAL(x) (x & 0xFF), ((x >> 8) & 0xFF) +#define DBVAL(x) (x & 0xFF), ((x >> 8) & 0xFF), ((x >> 16) & 0xFF), ((x >> 24) & 0xFF) + +#define PP_NARG(...) \ + PP_NARG_(__VA_ARGS__, PP_RSEQ_N()) +#define PP_NARG_(...) \ + PP_ARG_N(__VA_ARGS__) +#define PP_ARG_N( \ + _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \ + _11, _12, _13, _14, _15, _16, _17, _18, _19, _20, \ + _21, _22, _23, _24, _25, _26, _27, _28, _29, _30, \ + _31, _32, _33, _34, _35, _36, _37, _38, _39, _40, \ + _41, _42, _43, _44, _45, _46, _47, _48, _49, _50, \ + _51, _52, _53, _54, _55, _56, _57, _58, _59, _60, \ + _61, _62, _63, N, ...) N +#define PP_RSEQ_N() \ + 63, 62, 61, 60, \ + 59, 58, 57, 56, 55, 54, 53, 52, 51, 50, \ + 49, 48, 47, 46, 45, 44, 43, 42, 41, 40, \ + 39, 38, 37, 36, 35, 34, 33, 32, 31, 30, \ + 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, \ + 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, \ + 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 #endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c index bb47d65f8..fecddeddb 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c @@ -1,7 +1,12 @@ #include "usbh_core.h" +#include "usb_hc.h" +#include "usb_errno.h" +#include "usb_log.h" +#include "usb_list.h" +#include "usb_util.h" // #include "libserial.h" int main(){ return 0; -} \ No newline at end of file +} From 28d0cc056cad1bfd91cf515e79e6cf7aed3b2aeb Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 10 Jun 2024 23:08:28 -0700 Subject: [PATCH 012/198] Adjust code tree --- .../services/drivers/usb/components/{common => mem}/usb_mem.h | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename Ubiquitous/XiZi_AIoT/services/drivers/usb/components/{common => mem}/usb_mem.h (100%) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_mem.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_mem.h rename to Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h From b17ce138fa329486e0bd261e143c004ae7c404fc Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 10 Jun 2024 23:24:32 -0700 Subject: [PATCH 013/198] Modify code tree --- .../services/drivers/usb/components/Makefile | 2 +- .../services/drivers/usb/components/mem/Makefile | 11 +++++++++++ .../services/drivers/usb/components/mem/usb_mem.c | 2 ++ 3 files changed, 14 insertions(+), 1 deletion(-) create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/Makefile index 79a64c1ea..62e1a8580 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/Makefile @@ -11,7 +11,7 @@ # libipc = $(KERNEL_ROOT)/services/app/libipc.o # libsem = $(KERNEL_ROOT)/services/app/libsemaphore.o -SRC_DIR := class core osal port +SRC_DIR := class core mem osal port include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/Makefile new file mode 100644 index 000000000..2e22ab13e --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/Makefile @@ -0,0 +1,11 @@ +include $(KERNEL_ROOT)/services/drivers/usb/components/usb.mk + +objs = usb_mem.o + +all: ${objs} + @echo "generate $^" + @mv $^ $(KERNEL_ROOT)/services/drivers/usb/components + +%.o: %.c + @echo "cc $^" + @${cc} ${cflags} ${c_useropts} ${INC_DIR} -o $@ -c $^ \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c new file mode 100644 index 000000000..e6704f871 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c @@ -0,0 +1,2 @@ +#include "usb_mem.h" + From 02990bfd1e56f11e35eb07965ea31cea88d4da8f Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 11 Jun 2024 00:26:36 -0700 Subject: [PATCH 014/198] Modify source files --- .../services/drivers/usb/components/mem/usb_mem.c | 2 ++ .../services/drivers/usb/components/mem/usb_mem.h | 10 ++++++++++ .../XiZi_AIoT/services/drivers/usb/components/usb.mk | 1 + .../XiZi_AIoT/services/drivers/usb/usb_config.h | 12 ++++++------ 4 files changed, 19 insertions(+), 6 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c index e6704f871..2128a704d 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c @@ -1,2 +1,4 @@ +#include #include "usb_mem.h" + diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h index b5118468c..7697ac59b 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h @@ -1,8 +1,18 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef USB_MEM_H_ #define USB_MEM_H_ +#include +#define USB_MEM_ALIGNX __attribute__((aligned(CONFIG_USB_ALIGN_SIZE))) +void *usb_hc_malloc(size_t size); +void usb_hc_free(); +void *usb_hc_malloc_align(size_t align, size_t size); #endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk index e060536cf..488c3bd49 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk @@ -25,6 +25,7 @@ INC_DIR = -I$(KERNEL_ROOT)/services/drivers/usb/ \ -I$(KERNEL_ROOT)/services/drivers/usb/components/class/wireless \ -I$(KERNEL_ROOT)/services/drivers/usb/components/common \ -I$(KERNEL_ROOT)/services/drivers/usb/components/core \ + -I$(KERNEL_ROOT)/services/drivers/usb/components/mem \ -I$(KERNEL_ROOT)/services/drivers/usb/components/osal \ -I$(KERNEL_ROOT)/services/drivers/usb/components/port \ -I$(KERNEL_ROOT)/services/drivers/usb/components/port/xhci \ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_config.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_config.h index b2496eada..355a5813e 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_config.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_config.h @@ -36,13 +36,13 @@ extern "C" #include /* ================ USB common Configuration ================ */ -void *usb_hc_malloc(size_t size); -void usb_hc_free(); -void *usb_hc_malloc_align(size_t align, size_t size); +// void *usb_hc_malloc(size_t size); +// void usb_hc_free(); +// void *usb_hc_malloc_align(size_t align, size_t size); -#define usb_malloc(size) usb_hc_malloc(size) -#define usb_free(ptr) usb_hc_free(ptr) -#define usb_align(align, size) usb_hc_malloc_align(align, size) +// #define usb_malloc(size) usb_hc_malloc(size) +// #define usb_free(ptr) usb_hc_free(ptr) +// #define usb_align(align, size) usb_hc_malloc_align(align, size) #ifndef CONFIG_USB_DBG_LEVEL #define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR From 7d78fc6c2a5c28753fc1200a58cba19c2884e6d8 Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 11 Jun 2024 00:27:04 -0700 Subject: [PATCH 015/198] Modify source files --- .../XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c index fecddeddb..6379b01a6 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c @@ -4,6 +4,7 @@ #include "usb_log.h" #include "usb_list.h" #include "usb_util.h" +#include "usb_mem.h" // #include "libserial.h" int main(){ From 403d1daab1085926367e23b785deaadbc305ecce Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 11 Jun 2024 01:48:10 -0700 Subject: [PATCH 016/198] Implant USB memory functions --- .../drivers/usb/components/mem/usb_mem.c | 41 +++++++++++++++++++ .../drivers/usb/components/mem/usb_mem.h | 5 +++ 2 files changed, 46 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c index 2128a704d..555fe685f 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c @@ -2,3 +2,44 @@ #include "usb_mem.h" + +void *usb_hc_malloc(size_t size){ + void *result = malloc(size); + + if (result) + { + memset(result, 0U, size); + } + + return result; +} + + +void *usb_hc_malloc_align(size_t align, size_t size) +{ + size_t flag, adj_size; + + flag = align & (align - 1); + +/* + * align should be a power of 2. + */ + if(flag != 0) + return NULL; + + adj_size = (size + (align - 1)) &~ (align); + + void *result = malloc(size); + + if (result) + { + memset(result, 0U, size); + } + + return result; +} + +void usb_hc_free(void* ptr){ + if(ptr != NULL) + free(ptr); +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h index 7697ac59b..95e7c12ec 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h @@ -7,6 +7,7 @@ #define USB_MEM_H_ #include +#include "usb_config.h" #define USB_MEM_ALIGNX __attribute__((aligned(CONFIG_USB_ALIGN_SIZE))) @@ -14,5 +15,9 @@ void *usb_hc_malloc(size_t size); void usb_hc_free(); void *usb_hc_malloc_align(size_t align, size_t size); +#define usb_malloc(size) usb_hc_malloc(size) +#define usb_free(ptr) usb_hc_free(ptr) +#define usb_align(align, size) usb_hc_malloc_align(align, size) + #endif From 06b969a1190c9476bc4a3a5372c0b4f519549671 Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 11 Jun 2024 01:53:19 -0700 Subject: [PATCH 017/198] Modify header files --- .../services/drivers/usb/components/common/usb_errno.h | 4 ++-- .../services/drivers/usb/components/common/usb_util.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_errno.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_errno.h index a56bb9162..14b7402d1 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_errno.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_errno.h @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef USB_ERROR_H_ -#define USB_ERROR_H_ +#ifndef USB_ERRNO_H_ +#define USB_ERRNO_H_ #ifndef CONFIG_USB_ERROR_USE_SYSTEM diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_util.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_util.h index aac7e2f6e..0c46dbcb8 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_util.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_util.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #ifndef USB_UTIL_H_ -#define USB_TIIL_H_ +#define USB_UTIL_H_ #if defined(__CC_ARM) #ifndef __USED From 24262508c4b43f3a7d78fbf67a3ee654ee720d14 Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 11 Jun 2024 02:20:00 -0700 Subject: [PATCH 018/198] Modify header files --- .../drivers/usb/components/osal/usb_osal.h | 29 ++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.h index c0216cf49..303df88c5 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.h @@ -1,10 +1,37 @@ #ifndef USB_OSAL_H_ #define USB_OSAL_H_ +#include +#include #include "usb_config.h" -int usb_wait_until(int msec); +typedef void *usb_osal_thread_t; +typedef void *usb_osal_sem_t; +typedef void *usb_osal_mutex_t; +typedef void *usb_osal_mq_t; +typedef void (*usb_thread_entry_t)(void *argument); + +usb_osal_thread_t usb_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, usb_thread_entry_t entry, void *args); + +usb_osal_sem_t usb_osal_sem_create(uint32_t initial_count); +void usb_osal_sem_delete(usb_osal_sem_t sem); +int usb_osal_sem_take(usb_osal_sem_t sem, uint32_t timeout); +int usb_osal_sem_give(usb_osal_sem_t sem); + +usb_osal_mutex_t usb_osal_mutex_create(void); +void usb_osal_mutex_delete(usb_osal_mutex_t mutex); +int usb_osal_mutex_take(usb_osal_mutex_t mutex); +int usb_osal_mutex_give(usb_osal_mutex_t mutex); + +usb_osal_mq_t usb_osal_mq_create(uint32_t max_msgs); +int usb_osal_mq_send(usb_osal_mq_t mq, uintptr_t addr); +int usb_osal_mq_recv(usb_osal_mq_t mq, uintptr_t *addr, uint32_t timeout); + +size_t usb_osal_enter_critical_section(void); +void usb_osal_leave_critical_section(size_t flag); + +void usb_osal_msleep(uint32_t delay); #endif From 9469217fe6e98b9bfda471dd2f38c51055fbab8b Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 11 Jun 2024 03:09:06 -0700 Subject: [PATCH 019/198] Modify header files --- .../usb/components/port/xhci/xhci_reg.h | 495 ++++++++++++++++++ 1 file changed, 495 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci_reg.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci_reg.h index 0d9aede23..e3148ed8f 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci_reg.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci_reg.h @@ -1,9 +1,504 @@ +/* + * Copyright?: (C)?2022?Phytium?Information?Technology,?Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: xhci_reg.h + * Date: 2022-07-19 09:26:25 + * LastEditTime: 2022-07-19 09:26:25 + * Description: ?This file is for xhci register definition. + * + * Modify?History: + * Ver???Who????????Date?????????Changes + * -----?------?????--------????-------------------------------------- + * 1.0 zhugengyu 2022/9/19 init commit + * 2.0 zhugengyu 2023/3/29 support usb3.0 device attached at roothub + */ + #ifndef XHCI_REG_H_ #define XHCI_REG_H_ +#include + +#if defined(__aarch64__) +#define BITS_PER_LONG 64U +#define XHCI_AARCH64 +#else +#define BITS_PER_LONG 32U +#define XHCI_AARCH32 +#endif + + +#define XHCI_GENMASK(h, l) \ + (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) + +#define XHCI_GENMASK_ULL(h, l) \ + (((~0ULL) - (1ULL << (l)) + 1) & \ + (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) + +#define XHCI32_GET_BITS(x, a, b) (uint32_t)((((uint32_t)(x)) & XHCI_GENMASK(a, b)) >> b) +#define XHCI32_SET_BITS(x, a, b) (uint32_t)((((uint32_t)(x)) << b) & XHCI_GENMASK(a, b)) +#define XHCI64_GET_BITS(x, a, b) (uint64_t)((((uint64_t)(x)) & XHCI_GENMASK_ULL(a, b)) >> b) +#define XHCI64_SET_BITS(x, a, b) (uint64_t)((((uint64_t)(x)) << b) & XHCI_GENMASK_ULL(a, b)) + +/** Capability register length */ +#define XHCI_CAP_CAPLENGTH 0x00 + +/** Host controller interface version number */ +#define XHCI_CAP_HCIVERSION 0x02 + +/** Structural parameters 1 */ +#define XHCI_CAP_HCSPARAMS1 0x04 + +/** Number of device slots */ +#define XHCI_HCSPARAMS1_SLOTS(params) ( ( (params) >> 0 ) & 0xff ) + +/** Number of interrupters */ +#define XHCI_HCSPARAMS1_INTRS(params) ( ( (params) >> 8 ) & 0x3ff ) + +/** Number of ports */ +#define XHCI_HCSPARAMS1_PORTS(params) ( ( (params) >> 24 ) & 0xff ) + +/** Structural parameters 2 */ +#define XHCI_CAP_HCSPARAMS2 0x08 + +/** Number of page-sized scratchpad buffers */ +#define XHCI_HCSPARAMS2_SCRATCHPADS(params) \ + ( ( ( (params) >> 16 ) & 0x3e0 ) | ( ( (params) >> 27 ) & 0x1f ) ) + +/** Capability parameters */ +#define XHCI_CAP_HCCPARAMS1 0x10 + +/** 64-bit addressing capability */ +#define XHCI_HCCPARAMS1_ADDR64(params) ( ( (params) >> 0 ) & 0x1 ) + +/** Context size shift */ +#define XHCI_HCCPARAMS1_CSZ_SHIFT(params) ( 5 + ( ( (params) >> 2 ) & 0x1 ) ) + +/** xHCI extended capabilities pointer */ +#define XHCI_HCCPARAMS1_XECP(params) ( ( ( (params) >> 16 ) & 0xffff ) << 2 ) + +/** Doorbell offset */ +#define XHCI_CAP_DBOFF 0x14 + +/** Runtime register space offset */ +#define XHCI_CAP_RTSOFF 0x18 + +/** xHCI extended capability ID */ +#define XHCI_XECP_ID(xecp) ( ( (xecp) >> 0 ) & 0xff ) + +/** Next xHCI extended capability pointer */ +#define XHCI_XECP_NEXT(xecp) ( ( ( (xecp) >> 8 ) & 0xff ) << 2 ) + +/** USB legacy support extended capability */ +#define XHCI_XECP_ID_LEGACY 1 + +/** USB legacy support BIOS owned semaphore */ +#define XHCI_USBLEGSUP_BIOS 0x02 + +/** USB legacy support BIOS ownership flag */ +#define XHCI_USBLEGSUP_BIOS_OWNED 0x01 + +/** USB legacy support OS owned semaphore */ +#define XHCI_USBLEGSUP_OS 0x03 + +/** USB legacy support OS ownership flag */ +#define XHCI_USBLEGSUP_OS_OWNED 0x01 + +/** USB legacy support control/status */ +#define XHCI_USBLEGSUP_CTLSTS 0x04 + +/** Supported protocol extended capability */ +#define XHCI_XECP_ID_SUPPORTED 2 + +/** Supported protocol revision */ +#define XHCI_SUPPORTED_REVISION 0x00 + +/** Supported protocol minor revision */ +#define XHCI_SUPPORTED_REVISION_VER(revision) ( ( (revision) >> 16 ) & 0xffff ) + +/** Supported protocol name */ +#define XHCI_SUPPORTED_NAME 0x04 + +/** Supported protocol ports */ +#define XHCI_SUPPORTED_PORTS 0x08 + +/** Supported protocol port offset */ +#define XHCI_SUPPORTED_PORTS_OFFSET(ports) ( ( (ports) >> 0 ) & 0xff ) + +/** Supported protocol port count */ +#define XHCI_SUPPORTED_PORTS_COUNT(ports) ( ( (ports) >> 8 ) & 0xff ) + +/** Supported protocol PSI count */ +#define XHCI_SUPPORTED_PORTS_PSIC(ports) ( ( (ports) >> 28 ) & 0x0f ) + +/** Supported protocol slot */ +#define XHCI_SUPPORTED_SLOT 0x0c + +/** Supported protocol slot type */ +#define XHCI_SUPPORTED_SLOT_TYPE(slot) ( ( (slot) >> 0 ) & 0x1f ) + +/** Supported protocol PSI */ +#define XHCI_SUPPORTED_PSI(index) ( 0x10 + ( (index) * 4 ) ) + +/** Supported protocol PSI value */ +#define XHCI_SUPPORTED_PSI_VALUE(psi) ( ( (psi) >> 0 ) & 0x0f ) + +/** Supported protocol PSI mantissa */ +#define XHCI_SUPPORTED_PSI_MANTISSA(psi) ( ( (psi) >> 16 ) & 0xffff ) + +/** Supported protocol PSI exponent */ +#define XHCI_SUPPORTED_PSI_EXPONENT(psi) ( ( (psi) >> 4 ) & 0x03 ) + +/** Default PSI values */ +enum { + /** Full speed (12Mbps) */ + XHCI_SPEED_FULL = 1, + /** Low speed (1.5Mbps) */ + XHCI_SPEED_LOW = 2, + /** High speed (480Mbps) */ + XHCI_SPEED_HIGH = 3, + /** Super speed */ + XHCI_SPEED_SUPER = 4, +}; + +/** USB command register */ +#define XHCI_OP_USBCMD 0x00 + +/** Run/stop */ +#define XHCI_USBCMD_RUN 0x00000001UL + +/* Interrupter Enable (INTE) 1: enabled - RW */ +#define XHCI_USBCMD_INTE (1UL << 2) + +/** Host controller reset */ +#define XHCI_USBCMD_HCRST 0x00000002UL + +/** USB status register */ +#define XHCI_OP_USBSTS 0x04 + +/** Host controller halted */ +#define XHCI_USBSTS_HCH 0x00000001UL + +/** Interrupt Pending (IP) */ +#define XHCI_USBSTS_EINT (1UL << 3) + +/** Page size register */ +#define XHCI_OP_PAGESIZE 0x08 + +/** Page size */ +#define XHCI_PAGESIZE(pagesize) ( (pagesize) << 12 ) + +/** Device notifcation control register */ +#define XHCI_OP_DNCTRL 0x14 + +/** Command ring control register */ +#define XHCI_OP_CRCR 0x18 + +/** Command ring cycle state */ +#define XHCI_CRCR_RCS 0x00000001UL + +/** Command abort */ +#define XHCI_CRCR_CA 0x00000004UL + +/** Command ring running */ +#define XHCI_CRCR_CRR 0x00000008UL + +/** Device context base address array pointer */ +#define XHCI_OP_DCBAAP 0x30 + +/** Configure register */ +#define XHCI_OP_CONFIG 0x38 + +/** Maximum device slots enabled */ +#define XHCI_CONFIG_MAX_SLOTS_EN(slots) ( (slots) << 0 ) + +/** Maximum device slots enabled mask */ +#define XHCI_CONFIG_MAX_SLOTS_EN_MASK \ + XHCI_CONFIG_MAX_SLOTS_EN ( 0xff ) + +/** Port status and control register */ +#define XHCI_OP_PORTSC(port) ( 0x400 - 0x10 + ( (port) << 4 ) ) + +/** Current connect status */ +#define XHCI_PORTSC_CCS 0x00000001UL + +/** Port enabled */ +#define XHCI_PORTSC_PED 0x00000002UL + +#define XHCI_PORTSC_OCA (1 << 3) + +/** Port reset */ +#define XHCI_PORTSC_PR 0x00000010UL + +/** Port link state */ +#define XHCI_PORTSC_PLS(pls) ( (pls) << 5 ) + +/** U0 state */ +#define XHCI_PORTSC_PLS_U0 XHCI_PORTSC_PLS ( 0 ) + +/** Disabled port link state */ +#define XHCI_PORTSC_PLS_DISABLED XHCI_PORTSC_PLS ( 4 ) + +/** RxDetect port link state */ +#define XHCI_PORTSC_PLS_RXDETECT XHCI_PORTSC_PLS ( 5 ) + +/** Polling state */ +#define XHCI_PORTSC_PLS_POLLING XHCI_PORTSC_PLS ( 7 ) + +/** Port link state mask */ +#define XHCI_PORTSC_PLS_MASK XHCI_PORTSC_PLS ( 0xf ) + +/** Port power */ +#define XHCI_PORTSC_PP 0x00000200UL + +/** Time to delay after enabling power to a port */ +#define XHCI_PORT_POWER_DELAY_MS 20 + +/** Port speed ID value */ +#define XHCI_PORTSC_PSIV(portsc) ( ( (portsc) >> 10 ) & 0xf ) + +/** Port indicator control */ +#define XHCI_PORTSC_PIC(indicators) ( (indicators) << 14 ) + +/** Port indicator control mask */ +#define XHCI_PORTSC_PIC_MASK XHCI_PORTSC_PIC ( 3 ) + +/** Port link state write strobe */ +#define XHCI_PORTSC_LWS 0x00010000UL + +/** Time to delay after writing the port link state */ +#define XHCI_LINK_STATE_DELAY_MS 100 + +/** Connect status change */ +#define XHCI_PORTSC_CSC (1 << 17) + +/** Port enabled/disabled change */ +#define XHCI_PORTSC_PEC (1 << 18) + +/** Warm port reset change */ +#define XHCI_PORTSC_WRC (1 << 19) + +/** Over-current change */ +#define XHCI_PORTSC_OCC (1 << 20) + +/** Port reset change */ +#define XHCI_PORTSC_PRC (1 << 21) + +/** Port link state change */ +#define XHCI_PORTSC_PLC (1 << 22) + +/** Port config error change */ +#define XHCI_PORTSC_CEC (1 << 23) + +/* Cold Attach Status 1: Far-end Receiver Terminations were detected */ +#define XHCI_PORTSC_CAS (1 << 24) + +/* Wake on Connect Enable 1: enable port to be sensitive to device connects */ +#define XHCI_PORTSC_WCE (1 << 25) + +/* Wake on Disconnect Enable 1: enable port to be sensitive to device disconnects */ +#define XHCI_PORTSC_WDE (1 << 26) + +/* Wake on Over-current Enable 1: enable port to be sensitive to over-current conditions */ +#define XHCI_PORTSC_WOE (1 << 27) + +/* Device Removable, 0: Device is removable. 1: Device is non-removable */ +#define XHCI_PORTSC_DR (1 << 30) + +/* Warm Port Reset 1: follow Warm Reset sequence */ +#define XHCI_PORTSC_WPR (1 << 31) + +/** Port status change mask */ +#define XHCI_PORTSC_CHANGE \ + ( XHCI_PORTSC_CSC | XHCI_PORTSC_PEC | XHCI_PORTSC_WRC | \ + XHCI_PORTSC_OCC | XHCI_PORTSC_PRC | XHCI_PORTSC_PLC | \ + XHCI_PORTSC_CEC ) + +#define XHCI_PORTSC_RW_MASK (XHCI_PORTSC_PR | XHCI_PORTSC_PLS_MASK | XHCI_PORTSC_PP \ + | XHCI_PORTSC_PIC_MASK | XHCI_PORTSC_LWS | XHCI_PORTSC_WCE \ + | XHCI_PORTSC_WDE | XHCI_PORTSC_WOE) + +/** Port status and control bits which should be preserved + * + * The port status and control register is a horrendous mix of + * differing semantics. Some bits are written to only when a separate + * write strobe bit is set. Some bits should be preserved when + * modifying other bits. Some bits will be cleared if written back as + * a one. Most excitingly, the "port enabled" bit has the semantics + * that 1=enabled, 0=disabled, yet writing a 1 will disable the port. + */ +#define XHCI_PORTSC_PRESERVE ( XHCI_PORTSC_PP | XHCI_PORTSC_PIC_MASK ) + +/** Port power management status and control register */ +#define XHCI_OP_PORTPMSC(port) ( 0x404 - 0x10 + ( (port) << 4 ) ) + +/** Port link info register */ +#define XHCI_OP_PORTLI(port) ( 0x408 - 0x10 + ( (port) << 4 ) ) + +/** Port hardware link power management control register */ +#define XHCI_OP_PORTHLPMC(port) ( 0x40c - 0x10 + ( (port) << 4 ) ) + +/* Doorbell registers are 32 bits in length */ +#define XHCI_REG_DB_SIZE 4 + +/** Interrupter Management Register */ +#define XHCI_RUN_IR_IMAN(intr) ( 0x20 + ( (intr) << 5 ) ) + +/* Interrupt Pending, 1: an interrupt is pending for this Interrupter */ +#define XHCI_RUN_IR_IMAN_IP (1 << 0) + +/* Interrupt Enable, 1: capable of generating an interrupt. */ +#define XHCI_RUN_IR_IMAN_IE (1 << 1) + +/** Interrupter Moderation Register */ +#define XHCI_RUN_IR_IMOD(intr) ( 0x24 + ( (intr) << 5 ) ) + +/** Event ring segment table size register */ +#define XHCI_RUN_ERSTSZ(intr) ( 0x28 + ( (intr) << 5 ) ) + +/** Event ring segment table base address register */ +#define XHCI_RUN_ERSTBA(intr) ( 0x30 + ( (intr) << 5 ) ) + +/** Event ring dequeue pointer register */ +#define XHCI_RUN_ERDP(intr) ( 0x38 + ( (intr) << 5 ) ) + +/** Event Handler Busy */ +#define XHCI_RUN_ERDP_EHB (1 << 3) + +/** Minimum alignment required for data structures + * + * With the exception of the scratchpad buffer pages (which are + * page-aligned), data structures used by xHCI generally require from + * 16 to 64 byte alignment and must not cross an (xHCI) page boundary. + * We simplify this requirement by aligning each structure on its own + * size, with a minimum of a 64 byte alignment. + */ +#define XHCI_MIN_ALIGN 64 + +/** Maximum transfer size */ +#define XHCI_MTU 65536 + +/** Read/Write Data Barrier for ARM */ +#define BARRIER() __asm__ __volatile__("": : :"memory") + +#ifdef XHCI_AARCH64 +#define DSB() __asm__ __volatile__("dsb sy": : : "memory") +#else +#define DSB() __asm__ __volatile__("dsb": : : "memory") +#endif +/** + * Read byte from memory-mapped device + * + * @v io_addr I/O address + * @ret data Value read + */ +static inline uint8_t readb(void *io_addr ) { + uint8_t val = *(volatile const uint8_t *)io_addr; + BARRIER(); + return val; +} + +/** + * Read 16-bit word from memory-mapped device + * + * @v io_addr I/O address + * @ret data Value read + */ +static inline uint16_t readw(void * io_addr ) { + uint16_t val = *(volatile const uint16_t *)io_addr; + BARRIER(); + return val; +} + +/** + * Read 32-bit dword from memory-mapped device + * + * @v io_addr I/O address + * @ret data Value read + */ +static inline uint32_t readl(void * io_addr ) { + uint32_t val = *(volatile const uint32_t *)io_addr; + BARRIER(); + return val; +} + +/** + * Read 64-bit qword from memory-mapped device + * + * @v io_addr I/O address + * @ret data Value read + */ +static inline uint64_t readq(void * io_addr ) { + uint64_t val = *(volatile const uint64_t *)io_addr; + BARRIER(); + return val; +} + +/** + * Write byte to memory-mapped device + * + * @v data Value to write + * @v io_addr I/O address + */ +static inline void writeb(uint8_t data, void * io_addr ) { + BARRIER(); + *(volatile uint8_t *)io_addr = data; +} + +/** + * Write 16-bit word to memory-mapped device + * + * @v data Value to write + * @v io_addr I/O address + */ +static inline void writew(uint16_t data, void * io_addr ) { + BARRIER(); + *(volatile uint16_t *)io_addr = data; +} + +/** + * Write 32-bit dword to memory-mapped device + * + * @v data Value to writed + * @v io_addr I/O address + */ +static inline void writel(uint32_t data, void * io_addr ) { + BARRIER(); + *(volatile uint32_t *)io_addr = data; +} + +/** + * Write 64-bit qword to memory-mapped device + * + * @v data Value to write + * @v io_addr I/O address + */ +static inline void writeq(uint64_t data, void * io_addr ) { + BARRIER(); + *(volatile uint64_t *)io_addr = data; +} + +/** + * Byte-order converter for ARM-Little-End + */ +#define CPU_TO_LE64(x) ((uint64_t)(x)) +#define LE64_to_CPU(x) ((uint64_t)(x)) +#define CPU_TO_LE32(x) ((uint32_t)(x)) +#define LE32_TO_CPU(x) ((uint32_t)(x)) +#define CPU_TO_LE16(x) ((uint16_t)(x)) +#define LE16_TO_CPU(x) ((uint16_t)(x)) #endif From 6039856cd29c6278e3f65ef64ea8686e5dd11465 Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 11 Jun 2024 22:58:17 -0700 Subject: [PATCH 020/198] Modify source files --- .../usb/components/class/hub/usb_hub.h | 118 ++++++++ .../usb/components/class/hub/usbh_hub.h | 16 + .../drivers/usb/components/core/usbh_core.h | 284 ++++++++++++++++++ .../drivers/usb/components/osal/usb_osal.c | 6 +- 4 files changed, 421 insertions(+), 3 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usb_hub.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usb_hub.h index de5074663..d66b40a25 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usb_hub.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usb_hub.h @@ -1,6 +1,124 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef USB_HUB_H_ #define USB_HUB_H_ +#include + +/* HUB Class Descriptor Types */ +#define HUB_DESCRIPTOR_TYPE_HUB 0x29 +#define HUB_DESCRIPTOR_TYPE_HUB3 0x2a + +/* Hub class requests */ +#define HUB_REQUEST_GET_STATUS USB_REQUEST_GET_STATUS +#define HUB_REQUEST_CLEAR_FEATURE USB_REQUEST_CLEAR_FEATURE +#define HUB_REQUEST_SET_FEATURE USB_REQUEST_SET_FEATURE +#define HUB_REQUEST_GET_DESCRIPTOR USB_REQUEST_GET_DESCRIPTOR +#define HUB_REQUEST_SET_DESCRIPTOR USB_REQUEST_SET_DESCRIPTOR +#define HUB_REQUEST_CLEAR_TT_BUFFER (0x08) +#define HUB_REQUEST_RESET_TT (0x09) +#define HUB_REQUEST_GET_TT_STATE (0x0a) +#define HUB_REQUEST_STOP_TT (0x0b) +#define HUB_REQUEST_SET_HUB_DEPTH (0x0C) + +/* Hub class features */ +#define HUB_FEATURE_HUB_C_LOCALPOWER (0x0) +#define HUB_FEATURE_HUB_C_OVERCURRENT (0x1) + +/* Port features */ +#define HUB_PORT_FEATURE_CONNECTION (0x00) +#define HUB_PORT_FEATURE_ENABLE (0x01) +#define HUB_PORT_FEATURE_SUSPEND (0x02) +#define HUB_PORT_FEATURE_OVERCURRENT (0x03) +#define HUB_PORT_FEATURE_RESET (0x04) +#define HUB_PORT_FEATURE_L1 (0x05) +#define HUB_PORT_FEATURE_POWER (0x08) +#define HUB_PORT_FEATURE_LOWSPEED (0x09) +#define HUB_PORT_FEATURE_HIGHSPEED (0x0a) +#define HUB_PORT_FEATURE_C_CONNECTION (0x10) +#define HUB_PORT_FEATURE_C_ENABLE (0x11) +#define HUB_PORT_FEATURE_C_SUSPEND (0x12) +#define HUB_PORT_FEATURE_C_OVER_CURREN (0x13) +#define HUB_PORT_FEATURE_C_RESET (0x14) +#define HUB_PORT_FEATURE_TEST (0x15) +#define HUB_PORT_FEATURE_INDICATOR (0x16) +#define HUB_PORT_FEATURE_C_PORTL1 (0x17) + +/* Hub status */ +#define HUB_STATUS_LOCALPOWER (1 << 0) +#define HUB_STATUS_OVERCURRENT (1 << 1) + +/* Hub status change */ +#define HUB_STATUS_C_LOCALPOWER (1 << 0) +#define HUB_STATUS_C_OVERCURRENT (1 << 1) + +/* Hub port status */ +#define HUB_PORT_STATUS_CONNECTION (1 << 0) +#define HUB_PORT_STATUS_ENABLE (1 << 1) +#define HUB_PORT_STATUS_SUSPEND (1 << 2) +#define HUB_PORT_STATUS_OVERCURRENT (1 << 3) +#define HUB_PORT_STATUS_RESET (1 << 4) +#define HUB_PORT_STATUS_L1 (1 << 5) +#define HUB_PORT_STATUS_POWER (1 << 8) +#define HUB_PORT_STATUS_LOW_SPEED (1 << 9) +#define HUB_PORT_STATUS_HIGH_SPEED (1 << 10) +#define HUB_PORT_STATUS_TEST (1 << 11) +#define HUB_PORT_STATUS_INDICATOR (1 << 12) + +/* Hub port status change */ +#define HUB_PORT_STATUS_C_CONNECTION (1 << 0) +#define HUB_PORT_STATUS_C_ENABLE (1 << 1) +#define HUB_PORT_STATUS_C_SUSPEND (1 << 2) +#define HUB_PORT_STATUS_C_OVERCURRENT (1 << 3) +#define HUB_PORT_STATUS_C_RESET (1 << 4) +#define HUB_PORT_STATUS_C_L1 (1 << 5) + +/* Hub characteristics */ +#define HUB_CHAR_LPSM_SHIFT (0) /* Bits 0-1: Logical Power Switching Mode */ +#define HUB_CHAR_LPSM_MASK (3 << HUB_CHAR_LPSM_SHIFT) +#define HUB_CHAR_LPSM_GANGED (0 << HUB_CHAR_LPSM_SHIFT) +#define HUB_CHAR_LPSM_INDIVIDUAL (1 << HUB_CHAR_LPSM_SHIFT) +#define HUB_CHAR_COMPOUND (1 << 2) /* Bit 2: Compound device */ +#define HUB_CHAR_OCPM_SHIFT (3) /* Bits 3-4: Over-current Protection Mode */ +#define HUB_CHAR_OCPM_MASK (3 << HUB_CHAR_OCPM_SHIFT) +#define HUB_CHAR_OCPM_GLOBAL (0 << HUB_CHAR_OCPM_SHIFT) +#define HUB_CHAR_OCPM_INDIVIDUAL (1 << HUB_CHAR_OCPM_SHIFT) +#define HUB_CHAR_TTTT_SHIFT (5) /* Bits 5-6: TT Think Time */ +#define HUB_CHAR_TTTT_MASK (3 << HUB_CHAR_TTTT_SHIFT) +#define HUB_CHAR_TTTT_8_BITS (0 << HUB_CHAR_TTTT_SHIFT) +#define HUB_CHAR_TTTT_16_BITS (1 << HUB_CHAR_TTTT_SHIFT) +#define HUB_CHAR_TTTT_24_BITS (2 << HUB_CHAR_TTTT_SHIFT) +#define HUB_CHAR_TTTT_32_BITS (3 << HUB_CHAR_TTTT_SHIFT) +#define HUB_CHAR_PORTIND (1 << 7) /* Bit 7: Port Indicators Supported */ + +/* Hub descriptor */ +struct usb_hub_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint16_t wHubCharacteristics; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint8_t DeviceRemovable; + uint8_t PortPwrCtrlMask; +} __PACKED; + +#define USB_SIZEOF_HUB_DESC 9 + +/* Hub status */ +struct hub_status { + uint16_t wPortStatus; + uint16_t wPortChange; +}; + +/* Hub port status */ +struct hub_port_status { + uint16_t wPortStatus; + uint16_t wPortChange; +}; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.h index 1ea7bf19f..08dcfa7b7 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.h @@ -1,9 +1,25 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef USBH_HUB_H_ #define USBH_HUB_H_ +#include "usbh_core.h" #include "usb_hub.h" +#ifdef __cplusplus +extern "C" { +#endif +void usbh_roothub_thread_wakeup(uint32_t usb_id, uint8_t port); +int usbh_hub_initialize(struct usbh_bus *usb); +struct usbh_hubport *usbh_get_roothub_port (struct usbh_bus *bus, unsigned int port); + +#ifdef __cplusplus +} +#endif #endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h index 1a2de80c4..ddc40012b 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h @@ -1,7 +1,291 @@ #ifndef USBH_CORE_H_ #define USBH_CORE_H_ +#include +#include +#include +#include +#include "usb_config.h" +#include "usb_util.h" +#include "usb_errno.h" +#include "usb_def.h" +#include "usb_list.h" +#include "usb_mem.h" +#include "usb_log.h" +#include "usb_hc.h" +#include "usb_osal.h" +#include "usb_hub.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#define USB_CLASS_MATCH_VENDOR 0x0001 +#define USB_CLASS_MATCH_PRODUCT 0x0002 +#define USB_CLASS_MATCH_INTF_CLASS 0x0004 +#define USB_CLASS_MATCH_INTF_SUBCLASS 0x0008 +#define USB_CLASS_MATCH_INTF_PROTOCOL 0x0010 + +#define CLASS_CONNECT(hport, i) ((hport)->config.intf[i].class_driver->connect(hport, i)) +#define CLASS_DISCONNECT(hport, i) ((hport)->config.intf[i].class_driver->disconnect(hport, i)) + +#ifdef __ARMCC_VERSION /* ARM C Compiler */ +#define CLASS_INFO_DEFINE __attribute__((section("usbh_class_info"))) __USED __ALIGNED(1) +#elif defined(__GNUC__) +#define CLASS_INFO_DEFINE __attribute__((section(".usbh_class_info"))) __USED __ALIGNED(1) +#elif defined(__ICCARM__) || defined(__ICCRX__) +#pragma section = "usbh_class_info" +#define CLASS_INFO_DEFINE __attribute__((section("usbh_class_info"))) __USED __ALIGNED(1) +#endif + + +static inline void usbh_control_urb_fill(struct usbh_urb *urb, + usbh_pipe_t pipe, + struct usb_setup_packet *setup, + uint8_t *transfer_buffer, + uint32_t transfer_buffer_length, + uint32_t timeout, + usbh_complete_callback_t complete, + void *arg) +{ + urb->pipe = pipe; + urb->setup = setup; + urb->transfer_buffer = transfer_buffer; + urb->transfer_buffer_length = transfer_buffer_length; + urb->timeout = timeout; + urb->complete = complete; + urb->arg = arg; +} + + + +static inline void usbh_bulk_urb_fill(struct usbh_urb *urb, + usbh_pipe_t pipe, + uint8_t *transfer_buffer, + uint32_t transfer_buffer_length, + uint32_t timeout, + usbh_complete_callback_t complete, + void *arg) +{ + urb->pipe = pipe; + urb->setup = NULL; + urb->transfer_buffer = transfer_buffer; + urb->transfer_buffer_length = transfer_buffer_length; + urb->timeout = timeout; + urb->complete = complete; + urb->arg = arg; +} + + + +static inline void usbh_int_urb_fill(struct usbh_urb *urb, + usbh_pipe_t pipe, + uint8_t *transfer_buffer, + uint32_t transfer_buffer_length, + uint32_t timeout, + usbh_complete_callback_t complete, + void *arg) +{ + urb->pipe = pipe; + urb->setup = NULL; + urb->transfer_buffer = transfer_buffer; + urb->transfer_buffer_length = transfer_buffer_length; + urb->timeout = timeout; + urb->complete = complete; + urb->arg = arg; +} + + + +struct usbh_class_info { + uint8_t match_flags; /* Used for product specific matches; range is inclusive */ + uint8_t class; /* Base device class code */ + uint8_t subclass; /* Sub-class, depends on base class. Eg. */ + uint8_t protocol; /* Protocol, depends on base class. Eg. */ + uint16_t vid; /* Vendor ID (for vendor/product specific devices) */ + uint16_t pid; /* Product ID (for vendor/product specific devices) */ + const struct usbh_class_driver *class_driver; +}; + + +struct usbh_hubport; + +struct usbh_class_driver { + const char *driver_name; + int (*connect)(struct usbh_hubport *hport, uint8_t intf); + int (*disconnect)(struct usbh_hubport *hport, uint8_t intf); +}; + + + +struct usbh_endpoint { + struct usb_endpoint_descriptor ep_desc; +}; + +struct usbh_interface_altsetting { + struct usb_interface_descriptor intf_desc; + struct usbh_endpoint ep[CONFIG_USBHOST_MAX_ENDPOINTS]; +}; + +struct usbh_interface { + char devname[CONFIG_USBHOST_DEV_NAMELEN]; + struct usbh_class_driver *class_driver; + void *priv; + struct usbh_interface_altsetting altsetting[CONFIG_USBHOST_MAX_INTF_ALTSETTINGS]; + uint8_t altsetting_num; +}; + +struct usbh_configuration { + struct usb_configuration_descriptor config_desc; + struct usbh_interface intf[CONFIG_USBHOST_MAX_INTERFACES]; +}; + +struct usbh_hub; + + +struct usbh_hubport { + /** Name */ + char name[32]; + bool connected; /* True: device connected; false: disconnected */ + uint8_t port; /* Hub port index */ + uint8_t dev_addr; /* device address */ + uint8_t speed; /* device speed */ + usbh_pipe_t ep0; /* control ep pipe info */ + struct usb_device_descriptor device_desc; + struct usbh_configuration config; + const char *iManufacturer; + const char *iProduct; + const char *iSerialNumber; + uint8_t *raw_config_desc; + struct usb_setup_packet *setup; + struct usbh_hub *parent; +#ifdef CONFIG_USBHOST_XHCI + uint32_t protocol; /* port protocol, for xhci, some ports are USB2.0, others are USB3.0 */ +#endif +}; + + + +struct usbh_bus; + +struct usbh_hub { + usb_slist_t list; + bool connected; + bool is_roothub; + uint8_t index; + uint8_t hub_addr; + usbh_pipe_t intin; + uint8_t *int_buffer; + struct usbh_urb intin_urb; + struct usb_hub_descriptor hub_desc; + struct usbh_hubport child[CONFIG_USBHOST_MAX_EHPORTS]; + struct usbh_hubport *parent; + usb_slist_t hub_event_list; + struct usbh_bus *usb; + uint32_t ports; /* num of ports */ + USB_MEM_ALIGNX uint8_t g_hub_buf[32]; + USB_MEM_ALIGNX uint8_t g_hub_intbuf[CONFIG_USBHOST_MAX_EXTHUBS + 1][1]; +}; + + +int usbh_hport_activate_epx(usbh_pipe_t *pipe, struct usbh_hubport *hport, struct usb_endpoint_descriptor *ep_desc); + +/** + * @brief Submit an control transfer to an endpoint. + * This is a blocking method; this method will not return until the transfer has completed. + * Default timeout is 500ms. + * + * @param pipe The control endpoint to send/receive the control request. + * @param setup Setup packet to be sent. + * @param buffer buffer used for sending the request and for returning any responses. + * @return On success will return 0, and others indicate fail. + */ +int usbh_control_transfer(usbh_pipe_t pipe, struct usb_setup_packet *setup, uint8_t *buffer); + +struct usbh_devaddr_map { + /** + * alloctab[0]:addr from 0~31 + * alloctab[1]:addr from 32~63 + * alloctab[2]:addr from 64~95 + * alloctab[3]:addr from 96~127 + * + */ + uint8_t next; /* Next device address */ + uint32_t alloctab[4]; /* Bit allocation table */ +}; + +struct usbh_bus { + usb_slist_t list; + uint8_t id; + /** Largest transfer allowed on the bus */ + size_t mtu; + struct usbh_devaddr_map devgen; + struct usbh_hub roothub; +#if CONFIG_USBHOST_MAX_EXTHUBS > 0 + struct usbh_hub exthub[CONFIG_USBHOST_MAX_EXTHUBS]; +#endif + struct usbh_hubport roothub_parent_port; + usb_slist_t hub_event_head; + usb_slist_t hub_class_head; + usb_osal_sem_t hub_event_wait; + usb_osal_thread_t hub_thread; + usb_osal_mq_t hub_mq; + void *priv; /* private data, usb host */ + int (*hub_open)(struct usbh_hub *hub); + void (*hub_close)(struct usbh_hub *hub); + int (*root_open)(struct usbh_hub *hub); + USB_MEM_ALIGNX uint8_t ep0_request_buffer[CONFIG_USBHOST_REQUEST_BUFFER_LEN]; + USB_MEM_ALIGNX struct usb_setup_packet g_setup[CONFIG_USBHOST_MAX_EXTHUBS + 1][CONFIG_USBHOST_MAX_EHPORTS]; +}; + +/** + * Get USB transaction translator + * + * @v hport Hub port of USB device + * @ret port Transaction translator port, or NULL + */ +struct usbh_hubport *usbh_transaction_translator ( struct usbh_hubport *hport ); + +/** + * Get USB route string + * + * @v hport Hub Port of USB device + * @ret route USB route string + */ +unsigned int usbh_route_string ( struct usbh_hubport *hport ); + +static inline struct usbh_bus* usbh_get_bus_of_port(struct usbh_hubport *hport) +{ + USB_ASSERT(hport && hport->parent); + return hport->parent->usb; +} + +static inline struct usbh_hub *usbh_get_roothub_of_port(struct usbh_hubport *hport) +{ + return &(usbh_get_bus_of_port(hport)->roothub); +} + +struct usbh_bus* usbh_get_bus_of_index(uint8_t usb); + +/** + * Get USB root hub port + * + * @v hport Hub port of USB device + * @ret port Root hub port + */ +struct usbh_hubport * usbh_root_hub_port ( struct usbh_hubport *hport ); + +int usbh_initialize(uint32_t id, struct usbh_bus *usb); +struct usbh_hubport *usbh_find_hubport(uint32_t id, uint8_t dev_addr); +void *usbh_find_class_instance(const char *devname); +int lsusb(int argc, char **argv); + + +#ifdef __cplusplus +} +#endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c index 46e58b361..2731ef6bb 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c @@ -1,6 +1,6 @@ #include "usb_osal.h" -int usb_wait_until(int msec){ - return 0; -} +usb_osal_thread_t usb_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, usb_thread_entry_t entry, void *args){ + return NULL; +} \ No newline at end of file From 7635db0f84b0534d4abe7c596924dcad10200eea Mon Sep 17 00:00:00 2001 From: xj Date: Wed, 12 Jun 2024 01:50:27 -0700 Subject: [PATCH 021/198] Editing OS abstract layer codes for USB --- .../drivers/usb/components/osal/usb_osal.c | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c index 2731ef6bb..e19c77368 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c @@ -1,6 +1,41 @@ +/* + * Edited by Kameblue on June 12, 2024. + * + * For adapting CherryUSB to XiZi AIoT. + */ + #include "usb_osal.h" +#include "libserial.h" +#include "usyscall.h" usb_osal_thread_t usb_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, usb_thread_entry_t entry, void *args){ + int ret; + char *task_param[] = { args, NULL }; + ret = thread(entry, name, task_param); + + return (usb_osal_thread_t)ret; +} + + +usb_osal_sem_t usb_osal_sem_create(uint32_t initial_count){ + + return NULL; +} + + + +void usb_osal_sem_delete(usb_osal_sem_t sem){ + +} + + +int usb_osal_sem_take(usb_osal_sem_t sem, uint32_t timeout){ + return 0; +} + + +int usb_osal_sem_give(usb_osal_sem_t sem){ + return 0; } \ No newline at end of file From a3795dd0f72ab68784479a2caa4417a468519be2 Mon Sep 17 00:00:00 2001 From: xj Date: Wed, 12 Jun 2024 18:39:47 -0700 Subject: [PATCH 022/198] Delete a source file --- .../services/drivers/usb/components/osal/usb_osal_xiuos.c | 1 - 1 file changed, 1 deletion(-) delete mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal_xiuos.c diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal_xiuos.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal_xiuos.c deleted file mode 100644 index 391a315c8..000000000 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal_xiuos.c +++ /dev/null @@ -1 +0,0 @@ -#include "usb_osal.h" From 3acfca1e34f2bda98ff04089537ff4ec94e63612 Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 13 Jun 2024 00:08:58 -0700 Subject: [PATCH 023/198] Add comments --- .../drivers/usb/components/mem/usb_mem.c | 10 ++++++++++ .../drivers/usb/components/mem/usb_mem.h | 16 ++++++++++++++++ .../drivers/usb/components/osal/usb_osal.c | 8 ++++++++ 3 files changed, 34 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c index 555fe685f..54e47f614 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c @@ -1,6 +1,16 @@ #include #include "usb_mem.h" +/************************************************* +File name: usb_mem.c +Description: support usb memory management +Others: take CherryUSB v0.1.2/CherryUSB/port/xhci/usb_hc_xhci.c for references + https://github.com/cherry-embedded/CherryUSB/blob/v0.10.2/port/xhci/usb_hc_xhci.c +History: +1. Date: 2024-06-12 +Author: AIIT XUOS Lab +Modification: re-develop usb_hc_malloc, usb_hc_malloc_align and usb_hc_free functions +*************************************************/ void *usb_hc_malloc(size_t size){ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h index 95e7c12ec..b47417473 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h @@ -2,7 +2,23 @@ * Copyright (c) 2022, sakumisu * * SPDX-License-Identifier: Apache-2.0 + * + * */ + + +/************************************************* +File name: usb_mem.h +Description: support usb memory management +Others: take CherryUSB v0.10.2/CherryUSB/cherryusb_config_template.h for references + https://github.com/cherry-embedded/CherryUSB/blob/v0.10.2/cherryusb_config_template.h +History: +1. Date: 2024-06-12 +Author: AIIT XUOS Lab +Modification: Use usb_malloc, usb_free and usb_align functions +*************************************************/ + + #ifndef USB_MEM_H_ #define USB_MEM_H_ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c index e19c77368..caa94e5ef 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c @@ -6,6 +6,7 @@ #include "usb_osal.h" #include "libserial.h" +#include "syscall.h" #include "usyscall.h" @@ -17,6 +18,13 @@ usb_osal_thread_t usb_osal_thread_create(const char *name, uint32_t stack_size, return (usb_osal_thread_t)ret; } +void usb_osal_thread_delete(usb_osal_thread_t thread){ + int thread_id; + thread_id = (int)thread; + + kill(thread_id); +} + usb_osal_sem_t usb_osal_sem_create(uint32_t initial_count){ From b3fdaef64087eaa63063fe52894c071b49aec0e4 Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 13 Jun 2024 03:00:24 -0700 Subject: [PATCH 024/198] Replanting OSAL codes --- .../drivers/usb/components/osal/usb_osal.c | 84 +++++++++++++++++-- .../drivers/usb/components/osal/usb_osal.h | 32 +++++++ 2 files changed, 110 insertions(+), 6 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c index caa94e5ef..521e041e6 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c @@ -1,9 +1,20 @@ -/* - * Edited by Kameblue on June 12, 2024. +/* + * Copyright (c) 2022, sakumisu * - * For adapting CherryUSB to XiZi AIoT. + * SPDX-License-Identifier: Apache-2.0 */ +/************************************************* +File name: usb_osal.c +Description: adopt cherry USB to XiZi AIOT. +Others: CherryUSB v0.1.2/CherryUSB/osal/usb_osal_freertos.c for references + https://github.com/cherry-embedded/CherryUSB/blob/v0.10.2/osal/usb_osal_freertos.c +History: +1. Date: 2024-06-13 +Author: AIIT XUOS Lab +Modification: rename the file name, and re-develop all OS abstract layer function. +*************************************************/ + #include "usb_osal.h" #include "libserial.h" #include "syscall.h" @@ -27,23 +38,84 @@ void usb_osal_thread_delete(usb_osal_thread_t thread){ usb_osal_sem_t usb_osal_sem_create(uint32_t initial_count){ + int sem_id; + sem_id = semaphore_new(initial_count); - return NULL; + return (usb_osal_sem_t)sem_id; } void usb_osal_sem_delete(usb_osal_sem_t sem){ - + int sem_id; + sem_id = (int)sem; + semaphore_free(sem_id); } int usb_osal_sem_take(usb_osal_sem_t sem, uint32_t timeout){ + int sem_id; + sem_id = (int)sem; + + if(sem_id < 0) + return -1; + + semaphore_wait(sem_id); + return 0; } int usb_osal_sem_give(usb_osal_sem_t sem){ + int sem_id; + sem_id = (int)sem; + + if(sem_id < 0) + return -1; + + semaphore_signal(sem_id); + return 0; -} \ No newline at end of file +} + +usb_osal_mutex_t usb_osal_mutex_create(void){ + int mutex_id; + + mutex_id = semaphore_new(1); + + return (usb_osal_mutex_t)mutex_id; +} + +void usb_osal_mutex_delete(usb_osal_mutex_t mutex){ + int mutex_id; + mutex_id = (int)mutex; + semaphore_free(mutex_id); +} + +int usb_osal_mutex_take(usb_osal_mutex_t mutex){ + int mutex_id; + mutex_id = (int)mutex; + + if(mutex_id < 0) + return -1; + + semaphore_wait(mutex_id); + + return 0; +} + + +int usb_osal_mutex_give(usb_osal_mutex_t mutex){ + int mutex_id; + mutex_id = (int)mutex; + + if(mutex_id < 0) + return -1; + + semaphore_signal(mutex_id); + + return 0; +} + + diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.h index 303df88c5..5317bd35a 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.h @@ -1,3 +1,20 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ + + + /************************************************* +File name: usb_osal.h +Description: support OS abstract layer +Others: take CherryUSB v0.1.2/CherryUSB/osal/usb_osal.h for references + https://github.com/cherry-embedded/CherryUSB/blob/v0.10.2/osal/usb_osal.h +History: +1. Date: 2024-06-13 +Author: AIIT XUOS Lab +Modification: introduce message queue mechanism. +*************************************************/ #ifndef USB_OSAL_H_ #define USB_OSAL_H_ @@ -13,6 +30,7 @@ typedef void *usb_osal_mq_t; typedef void (*usb_thread_entry_t)(void *argument); usb_osal_thread_t usb_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, usb_thread_entry_t entry, void *args); +void usb_osal_thread_delete(usb_osal_thread_t thread); usb_osal_sem_t usb_osal_sem_create(uint32_t initial_count); void usb_osal_sem_delete(usb_osal_sem_t sem); @@ -34,4 +52,18 @@ void usb_osal_leave_critical_section(size_t flag); void usb_osal_msleep(uint32_t delay); +/* + * Defination of the Message queue. + */ + + #if 1 +struct osal_msg_queue{ + uint16_t msg_size; + uint16_t max_msgs; + uint16_t cur; + uint16_t header; + uint16_t tail; +}; +#endif + #endif From 7472a6de3d6ab5e4ae977f83f21b86cb9cebe2f8 Mon Sep 17 00:00:00 2001 From: xj Date: Sat, 15 Jun 2024 20:52:26 -0700 Subject: [PATCH 025/198] Modify OS Abstract layer --- .../drivers/usb/components/osal/usb_osal.c | 144 ++++++++++++++++++ .../drivers/usb/components/osal/usb_osal.h | 44 +++++- 2 files changed, 181 insertions(+), 7 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c index 521e041e6..3e5ef1157 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c @@ -16,6 +16,7 @@ Modification: rename the file name, and re-develop all OS abstract layer functio *************************************************/ #include "usb_osal.h" +#include "usb_mem.h" #include "libserial.h" #include "syscall.h" #include "usyscall.h" @@ -119,3 +120,146 @@ int usb_osal_mutex_give(usb_osal_mutex_t mutex){ } +osal_msg_queue_t osal_mq_create(const char *name, + size_t msg_size, + size_t max_msgs, + uint8_t flag){ + osal_msg_queue_t mq; + size_t buf_size; + +/* Unused now */ + (void *)name; + (void *)flag; + + + if(msg_size <= 0 || max_msgs <=0) + return NULL; + + mq = usb_malloc(sizeof(struct osal_msg_queue)); + + if(mq == NULL) + return NULL; + + buf_size = (sizeof(struct osal_mq_msg_header) + msg_size) * max_msgs; + + if(buf_size > MAX_MSG_QUEUE_BUF_SIZE){ + usb_free(mq); + return NULL; + } + + memset(mq, 0, sizeof(struct osal_msg_queue)); + + mq->data = usb_malloc(buf_size); + + if(mq->data == NULL){ + usb_free(mq); + return NULL; + } + + mq->mutex = usb_osal_mutex_create(); + + if(mq->mutex == NULL){ + usb_free(mq->data); + usb_free(mq); + return NULL; + } + + mq->msg_size = msg_size; + mq->max_msgs = max_msgs; + + return mq; +} + + + +void osal_mq_delete(osal_msg_queue_t mq){ + int mutex_id; + if(mq == NULL) + return; + + if(mq->data) + usb_free(mq->data); + + mutex_id = (int)(mq->mutex); + if(mutex_id > 0) + usb_osal_mutex_delete(mq->mutex); + + usb_free(mq); +} + + + +int osal_mq_send(osal_msg_queue_t mq, + void *msg, + size_t msg_len, + uint32_t timeout){ + return -1; +} + + + +int osal_mq_recv(osal_msg_queue_t mq, + void *msg, + size_t msg_len, + uint32_t timeout){ + uint16_t header, tail; + int mutex_id; + osal_mq_msg_header_t msg_header; + uint8_t *msg_buf; + size_t copy_len; + + if(mq == NULL || msg == NULL || msg_len == 0) + return -1; + + if(msg_len > mq->msg_size) + return -1; + + mutex_id = (int)(mq->mutex); + if(mutex_id <= 0) + return -1; + + usb_osal_sem_take(mq->mutex, timeout); + + header = mq->header; + tail = mq->tail; + +/* message queue is empty. */ + if(header == tail){ + usb_osal_sem_give(mq->mutex); + return 0; + } + + msg_header = (osal_mq_msg_header_t)(mq->data + (sizeof(struct osal_mq_msg_header) + mq->msg_size) * header); + msg_buf = (uint8_t *)(msg_header + 1); + copy_len = (msg_header->len > msg_len?msg_len:msg_header->len); + + + return -1; +} + + +usb_osal_mq_t usb_osal_mq_create(uint32_t max_msgs){ + osal_msg_queue_t mq; + mq = osal_mq_create("usb_mq", sizeof(uintptr_t *), max_msgs, 0); + return (usb_osal_mq_t)mq; +} + + +void usb_osal_mq_delete(usb_osal_mq_t mq){ + osal_msg_queue_t osal_mq; + osal_mq = (osal_msg_queue_t)mq; + + if(osal_mq != NULL) + osal_mq_delete(osal_mq); +} + + +int usb_osal_mq_recv(usb_osal_mq_t mq, uintptr_t *addr, uint32_t timeout){ + return osal_mq_recv((osal_msg_queue_t)mq, addr, sizeof(uintptr_t *), timeout); +} + + + +int usb_osal_mq_send(usb_osal_mq_t mq, uintptr_t addr){ + return osal_mq_send((osal_msg_queue_t)mq, &addr, sizeof(uintptr_t *), 0); +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.h index 5317bd35a..0d32449ed 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.h @@ -43,6 +43,7 @@ int usb_osal_mutex_take(usb_osal_mutex_t mutex); int usb_osal_mutex_give(usb_osal_mutex_t mutex); usb_osal_mq_t usb_osal_mq_create(uint32_t max_msgs); +void usb_osal_mq_delete(usb_osal_mq_t mq); int usb_osal_mq_send(usb_osal_mq_t mq, uintptr_t addr); int usb_osal_mq_recv(usb_osal_mq_t mq, uintptr_t *addr, uint32_t timeout); @@ -56,14 +57,43 @@ void usb_osal_msleep(uint32_t delay); * Defination of the Message queue. */ - #if 1 +#define MAX_MSG_QUEUE_BUF_SIZE 65535 * 65535 + struct osal_msg_queue{ - uint16_t msg_size; - uint16_t max_msgs; - uint16_t cur; - uint16_t header; - uint16_t tail; + uint16_t msg_size; + uint16_t max_msgs; + uint16_t cur; + uint16_t header; + uint16_t tail; + void *msg_queue_head; + void *msg_queue_tail; + usb_osal_mutex_t *mutex; + uint8_t *data; }; -#endif + +typedef struct osal_msg_queue *osal_msg_queue_t; + +struct osal_mq_msg_header{ + uint16_t len; +}; + +typedef struct osal_mq_msg_header *osal_mq_msg_header_t; + +osal_msg_queue_t osal_mq_create(const char *name, + size_t msg_size, + size_t max_msgs, + uint8_t flag); + +void osal_mq_delete(osal_msg_queue_t mq); + +int osal_mq_send(osal_msg_queue_t mq, + void *msg, + size_t msg_len, + uint32_t timeout); + +int osal_mq_recv(osal_msg_queue_t mq, + void *msg, + size_t msg_len, + uint32_t timeout); #endif From 97e0d1aa67149f75fb13bcca31ae0f32cc7c0849 Mon Sep 17 00:00:00 2001 From: xj Date: Sun, 16 Jun 2024 20:12:18 -0700 Subject: [PATCH 026/198] Develop OS abstract layer functions --- .../drivers/usb/components/osal/usb_osal.c | 66 +++++++++++++++++-- 1 file changed, 61 insertions(+), 5 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c index 3e5ef1157..c1bc3b220 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c @@ -9,10 +9,11 @@ File name: usb_osal.c Description: adopt cherry USB to XiZi AIOT. Others: CherryUSB v0.1.2/CherryUSB/osal/usb_osal_freertos.c for references https://github.com/cherry-embedded/CherryUSB/blob/v0.10.2/osal/usb_osal_freertos.c + History: -1. Date: 2024-06-13 +1. Date: 2024-06-17 Author: AIIT XUOS Lab -Modification: rename the file name, and re-develop all OS abstract layer function. +Modification: rename the file name, and re-develop all OS abstract layer functions. *************************************************/ #include "usb_osal.h" @@ -30,6 +31,8 @@ usb_osal_thread_t usb_osal_thread_create(const char *name, uint32_t stack_size, return (usb_osal_thread_t)ret; } + + void usb_osal_thread_delete(usb_osal_thread_t thread){ int thread_id; thread_id = (int)thread; @@ -38,6 +41,7 @@ void usb_osal_thread_delete(usb_osal_thread_t thread){ } + usb_osal_sem_t usb_osal_sem_create(uint32_t initial_count){ int sem_id; @@ -55,6 +59,7 @@ void usb_osal_sem_delete(usb_osal_sem_t sem){ } + int usb_osal_sem_take(usb_osal_sem_t sem, uint32_t timeout){ int sem_id; sem_id = (int)sem; @@ -68,6 +73,7 @@ int usb_osal_sem_take(usb_osal_sem_t sem, uint32_t timeout){ } + int usb_osal_sem_give(usb_osal_sem_t sem){ int sem_id; sem_id = (int)sem; @@ -80,6 +86,8 @@ int usb_osal_sem_give(usb_osal_sem_t sem){ return 0; } + + usb_osal_mutex_t usb_osal_mutex_create(void){ int mutex_id; @@ -88,12 +96,16 @@ usb_osal_mutex_t usb_osal_mutex_create(void){ return (usb_osal_mutex_t)mutex_id; } + + void usb_osal_mutex_delete(usb_osal_mutex_t mutex){ int mutex_id; mutex_id = (int)mutex; semaphore_free(mutex_id); } + + int usb_osal_mutex_take(usb_osal_mutex_t mutex){ int mutex_id; mutex_id = (int)mutex; @@ -107,6 +119,7 @@ int usb_osal_mutex_take(usb_osal_mutex_t mutex){ } + int usb_osal_mutex_give(usb_osal_mutex_t mutex){ int mutex_id; mutex_id = (int)mutex; @@ -120,6 +133,7 @@ int usb_osal_mutex_give(usb_osal_mutex_t mutex){ } + osal_msg_queue_t osal_mq_create(const char *name, size_t msg_size, size_t max_msgs, @@ -193,7 +207,41 @@ int osal_mq_send(osal_msg_queue_t mq, void *msg, size_t msg_len, uint32_t timeout){ - return -1; + uint16_t header, tail, tail_nxt; + int mutex_id; + osal_mq_msg_header_t msg_tail; + uint8_t *msg_buf; + + if(mq == NULL || msg == NULL || msg_len == 0) + return -1; + + if(msg_len > mq->msg_size) + return -1; + + mutex_id = (int)(mq->mutex); + if(mutex_id <= 0) + return -1; + + usb_osal_sem_take(mq->mutex, timeout); + + + tail = mq->tail; + header = mq->header; + /* message queue is full. */ + tail_nxt = (tail + 1) > mq->max_msgs ? (tail + 1 -mq->max_msgs):(tail + 1); + if(tail_nxt == header){ + usb_osal_sem_give(mq->mutex); + return 0; + } + + msg_tail = (osal_mq_msg_header_t)(mq->data + (sizeof(struct osal_mq_msg_header) + mq->msg_size) * header); + msg_buf = (uint8_t *)(msg_tail + 1); + + msg_tail->len = msg_len; + memcpy(msg_buf, msg, msg_len); + usb_osal_sem_give(mq->mutex); + + return msg_len; } @@ -231,13 +279,19 @@ int osal_mq_recv(osal_msg_queue_t mq, msg_header = (osal_mq_msg_header_t)(mq->data + (sizeof(struct osal_mq_msg_header) + mq->msg_size) * header); msg_buf = (uint8_t *)(msg_header + 1); - copy_len = (msg_header->len > msg_len?msg_len:msg_header->len); + copy_len = (msg_header->len > msg_len ? msg_len : msg_header->len); + memcpy(msg, msg_buf, copy_len); - return -1; + header++; + mq->header = (header > mq->max_msgs) ? (header - mq->max_msgs) : (header); + usb_osal_sem_give(mq->mutex); + + return copy_len; } + usb_osal_mq_t usb_osal_mq_create(uint32_t max_msgs){ osal_msg_queue_t mq; mq = osal_mq_create("usb_mq", sizeof(uintptr_t *), max_msgs, 0); @@ -245,6 +299,7 @@ usb_osal_mq_t usb_osal_mq_create(uint32_t max_msgs){ } + void usb_osal_mq_delete(usb_osal_mq_t mq){ osal_msg_queue_t osal_mq; osal_mq = (osal_msg_queue_t)mq; @@ -254,6 +309,7 @@ void usb_osal_mq_delete(usb_osal_mq_t mq){ } + int usb_osal_mq_recv(usb_osal_mq_t mq, uintptr_t *addr, uint32_t timeout){ return osal_mq_recv((osal_msg_queue_t)mq, addr, sizeof(uintptr_t *), timeout); } From 04a0e2a0f6b82c4408d38b365b89c7b3a481e72d Mon Sep 17 00:00:00 2001 From: xj Date: Sun, 16 Jun 2024 23:39:02 -0700 Subject: [PATCH 027/198] Re-design xhci functions to dock with USB core --- .../usb/components/port/xhci/usb_hc_xhci.c | 38 +++++++++ .../usb/components/port/xhci/usb_hc_xhci.h | 82 +++++++++++++++++++ 2 files changed, 120 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index c9c52dbe9..4ee4cdec2 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -1 +1,39 @@ +/* + * Copyright : (C) 2022 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: usb_hc_xhci.c + * Date: 2022-09-19 17:24:36 + * LastEditTime: 2022-09-19 17:24:36 + * Description:  This file is for xhci function implementation. + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhugengyu 2022/9/19 init commit + * 1.1 zhugengyu 2022/10/9 add dumpers and fix command abort + * 2.0 zhugengyu 2023/3/29 support usb3.0 device attached at roothub + */ + + +/************************************************* +File name: usb_hc_xhci.h +Description: the xhci functions to dock with the USB core layer. +Others: take CherryUSB v0.1.2/CherryUSB/osal/usb_osal.h for references + https://github.com/cherry-embedded/CherryUSB/blob/v0.10.2/osal/usb_osal.h +History: +1. Date: 2024-06-17 +Author: AIIT XUOS Lab +Modification: rewrite xhci functions to dock with USB core layer, so that the USB core can easily expand to other USB IP. +*************************************************/ #include "usb_hc_xhci.h" + diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h index f896e8207..c1821f1fe 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h @@ -2,8 +2,90 @@ #define USB_HC_XHCI_H_ #include "xhci.h" +#include "usbh_core.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief xHCI host controller hardware init. + * + * @return On success will return 0, and others indicate fail. + */ +int xhci_usb_hc_init(uint32_t id); + +/** + * @brief Get frame number. + * + * @return frame number. + */ +uint16_t xhci_usbh_get_frame_number(void); +/** + * @brief control roothub. + * + * @param usb usb bus instance + * @param setup setup request buffer. + * @param buf buf for reading response or write data. + * @return On success will return 0, and others indicate fail. + */ +int xhci_usbh_roothub_control(struct usbh_bus *usb, struct usb_setup_packet *setup, uint8_t *buf); + +/** + * @brief reconfig endpoint pipe. + * + * @param pipe A memory allocated for pipe. + * @param dev_addr device address. + * @param ep_mps endpoint max packet size. + * @param mult endpoint additional transcation + * @return On success will return 0, and others indicate fail. + */ +int xhci_usbh_ep_pipe_reconfigure(struct usbh_bus *usb, usbh_pipe_t pipe, uint8_t dev_addr, uint8_t ep_mps, uint8_t mult); + +/** + * @brief Allocate pipe for endpoint + * + * @param pipe A memory location provided by the caller in which to save the allocated pipe. + * @param ep_cfg Describes the endpoint info to be allocated. + * @return On success will return 0, and others indicate fail. + */ +int xhci_usbh_pipe_alloc(usbh_pipe_t *pipe, const struct usbh_endpoint_cfg *ep_cfg); + +/** + * @brief Free a pipe in which saves endpoint info. + * + * @param pipe A memory location provided by the caller in which to free the allocated endpoint info. + * @return On success will return 0, and others indicate fail. + */ +int xhci_usbh_pipe_free(usbh_pipe_t pipe); + +/** + * @brief Submit a usb transfer request to an xHCI endpoint. + * + * If timeout is not zero, this function will be in poll transfer mode, + * otherwise will be in async transfer mode. + * + * @param urb Usb request block. + * @return On success will return 0, and others indicate fail. + */ +int xhci_usbh_submit_urb(struct usbh_urb *urb); + +/** + * @brief Cancel a transfer request. + * + * This function will call When calls usbh_submit_urb and return -ETIMEOUT or -ESHUTDOWN. + * + * @param urb Usb request block. + * @return On success will return 0, and others indicate fail. + */ +int xhci_usbh_kill_urb(struct usbh_urb *urb); + +void XHCI_USBH_IRQHandler(void *param); +#ifdef __cplusplus +} +#endif #endif From 0a1df937adc5e918bba593621394d7b5cbd3e88f Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Mon, 17 Jun 2024 15:35:15 +0800 Subject: [PATCH 028/198] Modify usbh_core.c for references file --- .../drivers/usb/components/core/usbh_core.c | 953 +++++++++++++++++- 1 file changed, 944 insertions(+), 9 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c index 6379b01a6..134378d2b 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c @@ -1,13 +1,948 @@ -#include "usbh_core.h" -#include "usb_hc.h" -#include "usb_errno.h" -#include "usb_log.h" -#include "usb_list.h" -#include "usb_util.h" -#include "usb_mem.h" -// #include "libserial.h" +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/************************************************* +File name: usbh_core.c +Description: adopt cherry USB to XiZi AIOT. +Others: CherryUSB third-party/cherryusb/core/usbh_core.c for references + https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/blob/master/third-party/cherryusb/core/usbh_core.c +*************************************************/ -int main(){ +#include "usbh_core.h" +#include "usbh_hub.h" + +struct usbh_class_info *usbh_class_info_table_begin = NULL; +struct usbh_class_info *usbh_class_info_table_end = NULL; + +static usb_slist_t usb_buses = USB_SLIST_OBJECT_INIT(usb_buses); + +/* general descriptor field offsets */ +#define DESC_bLength 0 /** Length offset */ +#define DESC_bDescriptorType 1 /** Descriptor type offset */ + +#define USB_DEV_ADDR_MAX 0x7f +#define USB_DEV_ADDR_MARK_OFFSET 5 +#define USB_DEV_ADDR_MARK_MASK 0x1f + +struct usbh_bus* usbh_get_bus_of_index(uint8_t usb) +{ + usb_slist_t *i; + struct usbh_bus* target_bus = NULL; + struct usbh_bus* bus = NULL; + size_t flags = usb_osal_enter_critical_section(); + + usb_slist_for_each(i, &usb_buses) + { + bus = usb_slist_entry(i, struct usbh_bus, list); + if (bus->id == usb) { + target_bus = bus; + break; + } + } + usb_osal_leave_critical_section(flags); + + return target_bus; +} + +struct usbh_bus* usbh_get_bus_of_devname(const char *devname) +{ + uint8_t usb_id = 0, dev_id = 0; + int matched = 0; + uint32_t name_len = strlen(devname); + + /* e.g. /usb0/hub1, return the usb-id 0 */ + for (uint32_t i = 0; i < name_len; i++) { + if (('0' <= devname[i]) && ('9' >= devname[i])) { + usb_id = usb_id * 10 + (devname[i] - '0'); + if (!matched) { + matched = 1; + } + } else { + if (matched) { + break; + } + } + } + + /* success only if all items mathched */ + if (matched) { + USB_LOG_INFO("id = %d \r\n", usb_id); + return usbh_get_bus_of_index(usb_id); + } else { + return NULL; /* not matched */ + } +} + +/** + * Get USB transaction translator + * + * @v hport Hub port of USB device + * @ret port Transaction translator port, or NULL + */ +struct usbh_hubport *usbh_transaction_translator ( struct usbh_hubport *hport ) { + struct usbh_hubport *parent; + + if (hport->parent->is_roothub) { + return NULL; + } + + /* Navigate up to root hub. If we find a low-speed or + * full-speed device with a higher-speed parent hub, then that + * device's port is the transaction translator. + */ + for (; (parent = hport->parent->parent); hport = parent) { + if ((hport->speed <= USB_SPEED_FULL) && + (parent->speed > USB_SPEED_FULL)) { + return hport; + } + } + + return NULL; +} + +/** + * Get USB route string + * + * @v hport Hub Port of USB device + * @ret route USB route string + */ +unsigned int usbh_route_string ( struct usbh_hubport *hport ) { + struct usbh_hubport *parent; + unsigned int route; + + /* Navigate up to root hub, constructing route string as we go */ + for (route = 0; (parent = hport->parent->parent); hport = parent) { + route <<= 4; + route |= ( ( hport->dev_addr > 0xf ) ? + 0xf : hport->dev_addr ); + } + + return route; +} + +/** + * Get USB root hub port + * + * @v usb USB device + * @ret port Root hub port + */ +struct usbh_hubport * usbh_root_hub_port ( struct usbh_hubport *hport ) { + struct usbh_hubport *parent; + + /* Navigate up to root hub */ + while (parent = hport->parent->parent) { + hport = parent; + } + return hport; +} + +static int usbh_allocate_devaddr(struct usbh_devaddr_map *devgen) +{ + uint8_t startaddr = devgen->next; + uint8_t devaddr; + int index; + int bitno; + + for (;;) { + devaddr = devgen->next; + if (devgen->next >= 0x7f) { + devgen->next = 2; + } else { + devgen->next++; + } + + index = devaddr >> 5; + bitno = devaddr & 0x1f; + if ((devgen->alloctab[index] & (1 << bitno)) == 0) { + devgen->alloctab[index] |= (1 << bitno); + return (int)devaddr; + } + + if (startaddr == devaddr) { + return -ENOMEM; + } + } +} + +static int usbh_free_devaddr(struct usbh_devaddr_map *devgen, uint8_t devaddr) +{ + int index; + int bitno; + + if ((devaddr > 0) && (devaddr < USB_DEV_ADDR_MAX)) { + index = devaddr >> USB_DEV_ADDR_MARK_OFFSET; + bitno = devaddr & USB_DEV_ADDR_MARK_MASK; + + /* Free the address */ + if ((devgen->alloctab[index] |= (1 << bitno)) != 0) { + devgen->alloctab[index] &= ~(1 << bitno); + } else { + return -1; + } + + if (devaddr < devgen->next) { + devgen->next = devaddr; + } + } + return 0; } + +static const struct usbh_class_driver *usbh_find_class_driver(uint8_t class, uint8_t subclass, uint8_t protocol, + uint16_t vid, uint16_t pid) +{ + struct usbh_class_info *index = NULL; + + for (index = usbh_class_info_table_begin; index < usbh_class_info_table_end; index++) { + if ((index->match_flags & (USB_CLASS_MATCH_VENDOR | USB_CLASS_MATCH_PRODUCT | USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL)) == + (USB_CLASS_MATCH_VENDOR | USB_CLASS_MATCH_PRODUCT | USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL)) { + if (index->vid == vid && index->pid == pid && + index->class == class && index->subclass == subclass && index->protocol == protocol) { + return index->class_driver; + } + } else if ((index->match_flags & (USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL)) == + (USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL)) { + if (index->class == class && index->subclass == subclass && index->protocol == protocol) { + return index->class_driver; + } + } else if ((index->match_flags & (USB_CLASS_MATCH_VENDOR | USB_CLASS_MATCH_PRODUCT | USB_CLASS_MATCH_INTF_CLASS)) == + (USB_CLASS_MATCH_VENDOR | USB_CLASS_MATCH_PRODUCT | USB_CLASS_MATCH_INTF_CLASS)) { + if (index->vid == vid && index->pid == pid && index->class == class) { + return index->class_driver; + } + } else if ((index->match_flags & (USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS)) == (USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS)) { + if (index->class == class && index->subclass == subclass) { + return index->class_driver; + } + } else if ((index->match_flags & (USB_CLASS_MATCH_INTF_CLASS)) == USB_CLASS_MATCH_INTF_CLASS) { + if (index->class == class) { + return index->class_driver; + } + } + } + return NULL; +} + +static int parse_device_descriptor(struct usbh_hubport *hport, struct usb_device_descriptor *desc, uint16_t length) +{ + if (desc->bLength != USB_SIZEOF_DEVICE_DESC) { + USB_LOG_ERR("invalid device bLength 0x%02x\r\n", desc->bLength); + return -EINVAL; + } else if (desc->bDescriptorType != USB_DESCRIPTOR_TYPE_DEVICE) { + USB_LOG_ERR("unexpected device descriptor 0x%02x\r\n", desc->bDescriptorType); + return -EINVAL; + } else { + if (length <= 8) { + return 0; + } +#if 0 + USB_LOG_DBG("Device Descriptor:\r\n"); + USB_LOG_DBG("bLength: 0x%02x \r\n", desc->bLength); + USB_LOG_DBG("bDescriptorType: 0x%02x \r\n", desc->bDescriptorType); + USB_LOG_DBG("bcdUSB: 0x%04x \r\n", desc->bcdUSB); + USB_LOG_DBG("bDeviceClass: 0x%02x \r\n", desc->bDeviceClass); + USB_LOG_DBG("bDeviceSubClass: 0x%02x \r\n", desc->bDeviceSubClass); + USB_LOG_DBG("bDeviceProtocol: 0x%02x \r\n", desc->bDeviceProtocol); + USB_LOG_DBG("bMaxPacketSize0: 0x%02x \r\n", desc->bMaxPacketSize0); + USB_LOG_DBG("idVendor: 0x%04x \r\n", desc->idVendor); + USB_LOG_DBG("idProduct: 0x%04x \r\n", desc->idProduct); + USB_LOG_DBG("bcdDevice: 0x%04x \r\n", desc->bcdDevice); + USB_LOG_DBG("iManufacturer: 0x%02x \r\n", desc->iManufacturer); + USB_LOG_DBG("iProduct: 0x%02x \r\n", desc->iProduct); + USB_LOG_DBG("iSerialNumber: 0x%02x \r\n", desc->iSerialNumber); + USB_LOG_DBG("bNumConfigurations: 0x%02x\r\n", desc->bNumConfigurations); +#endif + hport->device_desc.bLength = desc->bLength; + hport->device_desc.bDescriptorType = desc->bDescriptorType; + hport->device_desc.bcdUSB = desc->bcdUSB; + hport->device_desc.bDeviceClass = desc->bDeviceClass; + hport->device_desc.bDeviceSubClass = desc->bDeviceSubClass; + hport->device_desc.bDeviceProtocol = desc->bDeviceProtocol; + hport->device_desc.bMaxPacketSize0 = desc->bMaxPacketSize0; + hport->device_desc.idVendor = desc->idVendor; + hport->device_desc.idProduct = desc->idProduct; + hport->device_desc.bcdDevice = desc->bcdDevice; + hport->device_desc.iManufacturer = desc->iManufacturer; + hport->device_desc.iProduct = desc->iProduct; + hport->device_desc.iSerialNumber = desc->iSerialNumber; + hport->device_desc.bNumConfigurations = desc->bNumConfigurations; + } + return 0; +} + +static int parse_config_descriptor(struct usbh_hubport *hport, struct usb_configuration_descriptor *desc, uint16_t length) +{ + struct usb_interface_descriptor *intf_desc; + struct usb_endpoint_descriptor *ep_desc; + uint8_t cur_alt_setting = 0xff; + uint8_t cur_iface = 0xff; + uint8_t cur_ep = 0xff; + uint8_t cur_ep_num = 0xff; + uint32_t desc_len = 0; + uint8_t *p; + + if (desc->bLength != USB_SIZEOF_CONFIG_DESC) { + USB_LOG_ERR("invalid config bLength 0x%02x\r\n", desc->bLength); + return -EINVAL; + } else if (desc->bDescriptorType != USB_DESCRIPTOR_TYPE_CONFIGURATION) { + USB_LOG_ERR("unexpected config descriptor 0x%02x\r\n", desc->bDescriptorType); + return -EINVAL; + } else { + if (length <= USB_SIZEOF_CONFIG_DESC) { + return 0; + } +#if 0 + USB_LOG_DBG("Config Descriptor:\r\n"); + USB_LOG_DBG("bLength: 0x%02x \r\n", desc->bLength); + USB_LOG_DBG("bDescriptorType: 0x%02x \r\n", desc->bDescriptorType); + USB_LOG_DBG("wTotalLength: 0x%04x \r\n", desc->wTotalLength); + USB_LOG_DBG("bNumInterfaces: 0x%02x \r\n", desc->bNumInterfaces); + USB_LOG_DBG("bConfigurationValue: 0x%02x \r\n", desc->bConfigurationValue); + USB_LOG_DBG("iConfiguration: 0x%02x \r\n", desc->iConfiguration); + USB_LOG_DBG("bmAttributes: 0x%02x \r\n", desc->bmAttributes); + USB_LOG_DBG("bMaxPower: 0x%02x \r\n", desc->bMaxPower); +#endif + hport->config.config_desc.bLength = desc->bLength; + hport->config.config_desc.bDescriptorType = desc->bDescriptorType; + hport->config.config_desc.wTotalLength = desc->wTotalLength; + hport->config.config_desc.bNumInterfaces = desc->bNumInterfaces; + hport->config.config_desc.bConfigurationValue = desc->bConfigurationValue; + hport->config.config_desc.iConfiguration = desc->iConfiguration; + hport->config.config_desc.iConfiguration = desc->iConfiguration; + hport->config.config_desc.bmAttributes = desc->bmAttributes; + hport->config.config_desc.bMaxPower = desc->bMaxPower; + + p = (uint8_t *)desc; + p += USB_SIZEOF_CONFIG_DESC; + desc_len = USB_SIZEOF_CONFIG_DESC; + + memset(hport->config.intf, 0, sizeof(struct usbh_interface) * CONFIG_USBHOST_MAX_INTERFACES); + + while (p[DESC_bLength] && (desc_len <= length)) { + switch (p[DESC_bDescriptorType]) { + case USB_DESCRIPTOR_TYPE_INTERFACE: + intf_desc = (struct usb_interface_descriptor *)p; + cur_iface = intf_desc->bInterfaceNumber; + cur_alt_setting = intf_desc->bAlternateSetting; + cur_ep_num = intf_desc->bNumEndpoints; + cur_ep = 0; + if (cur_iface > (CONFIG_USBHOST_MAX_INTERFACES - 1)) { + USB_LOG_ERR("Interface num overflow\r\n"); + return -ENOMEM; + } + if (cur_alt_setting > (CONFIG_USBHOST_MAX_INTF_ALTSETTINGS - 1)) { + USB_LOG_ERR("Interface altsetting num overflow\r\n"); + return -ENOMEM; + } + if (cur_ep_num > CONFIG_USBHOST_MAX_ENDPOINTS) { + USB_LOG_ERR("Endpoint num overflow\r\n"); + return -ENOMEM; + } +#if 0 + USB_LOG_DBG("Interface Descriptor:\r\n"); + USB_LOG_DBG("bLength: 0x%02x \r\n", intf_desc->bLength); + USB_LOG_DBG("bDescriptorType: 0x%02x \r\n", intf_desc->bDescriptorType); + USB_LOG_DBG("bInterfaceNumber: 0x%02x \r\n", intf_desc->bInterfaceNumber); + USB_LOG_DBG("bAlternateSetting: 0x%02x \r\n", intf_desc->bAlternateSetting); + USB_LOG_DBG("bNumEndpoints: 0x%02x \r\n", intf_desc->bNumEndpoints); + USB_LOG_DBG("bInterfaceClass: 0x%02x \r\n", intf_desc->bInterfaceClass); + USB_LOG_DBG("bInterfaceSubClass: 0x%02x \r\n", intf_desc->bInterfaceSubClass); + USB_LOG_DBG("bInterfaceProtocol: 0x%02x \r\n", intf_desc->bInterfaceProtocol); + USB_LOG_DBG("iInterface: 0x%02x \r\n", intf_desc->iInterface); +#endif + memcpy(&hport->config.intf[cur_iface].altsetting[cur_alt_setting].intf_desc, intf_desc, 9); + hport->config.intf[cur_iface].altsetting_num = cur_alt_setting + 1; + break; + case USB_DESCRIPTOR_TYPE_ENDPOINT: + ep_desc = (struct usb_endpoint_descriptor *)p; + memcpy(&hport->config.intf[cur_iface].altsetting[cur_alt_setting].ep[cur_ep].ep_desc, ep_desc, 7); + cur_ep++; + break; + + default: + break; + } + /* skip to next descriptor */ + p += p[DESC_bLength]; + desc_len += p[DESC_bLength]; + } + } + return 0; +} + +#ifdef CONFIG_USBHOST_GET_STRING_DESC +void usbh_print_string(char *lead, uint8_t *str) +{ + uint8_t string[64 + 1] = { 0 }; + + int len, i = 2, j = 0; + + len = str[0]; + while (i < len) { + string[j] = str[i]; + i += 2; + j++; + } + USB_LOG_RAW("%s%s\r\n", lead, string); +} +#endif + +static void usbh_print_hubport_info(struct usbh_hubport *hport) +{ + USB_LOG_RAW("Device Descriptor:\r\n"); + USB_LOG_RAW("bLength: 0x%02x \r\n", hport->device_desc.bLength); + USB_LOG_RAW("bDescriptorType: 0x%02x \r\n", hport->device_desc.bDescriptorType); + USB_LOG_RAW("bcdUSB: 0x%04x \r\n", hport->device_desc.bcdUSB); + USB_LOG_RAW("bDeviceClass: 0x%02x \r\n", hport->device_desc.bDeviceClass); + USB_LOG_RAW("bDeviceSubClass: 0x%02x \r\n", hport->device_desc.bDeviceSubClass); + USB_LOG_RAW("bDeviceProtocol: 0x%02x \r\n", hport->device_desc.bDeviceProtocol); + USB_LOG_RAW("bMaxPacketSize0: 0x%02x \r\n", hport->device_desc.bMaxPacketSize0); + USB_LOG_RAW("idVendor: 0x%04x \r\n", hport->device_desc.idVendor); + USB_LOG_RAW("idProduct: 0x%04x \r\n", hport->device_desc.idProduct); + USB_LOG_RAW("bcdDevice: 0x%04x \r\n", hport->device_desc.bcdDevice); + USB_LOG_RAW("iManufacturer: 0x%02x \r\n", hport->device_desc.iManufacturer); + USB_LOG_RAW("iProduct: 0x%02x \r\n", hport->device_desc.iProduct); + USB_LOG_RAW("iSerialNumber: 0x%02x \r\n", hport->device_desc.iSerialNumber); + USB_LOG_RAW("bNumConfigurations: 0x%02x\r\n", hport->device_desc.bNumConfigurations); + + USB_LOG_RAW("Config Descriptor:\r\n"); + USB_LOG_RAW("bLength: 0x%02x \r\n", hport->config.config_desc.bLength); + USB_LOG_RAW("bDescriptorType: 0x%02x \r\n", hport->config.config_desc.bDescriptorType); + USB_LOG_RAW("wTotalLength: 0x%04x \r\n", hport->config.config_desc.wTotalLength); + USB_LOG_RAW("bNumInterfaces: 0x%02x \r\n", hport->config.config_desc.bNumInterfaces); + USB_LOG_RAW("bConfigurationValue: 0x%02x \r\n", hport->config.config_desc.bConfigurationValue); + USB_LOG_RAW("iConfiguration: 0x%02x \r\n", hport->config.config_desc.iConfiguration); + USB_LOG_RAW("bmAttributes: 0x%02x \r\n", hport->config.config_desc.bmAttributes); + USB_LOG_RAW("bMaxPower: 0x%02x \r\n", hport->config.config_desc.bMaxPower); + + for (uint8_t i = 0; i < hport->config.config_desc.bNumInterfaces; i++) { + for (uint8_t j = 0; j < hport->config.intf[i].altsetting_num; j++) { + USB_LOG_RAW("Interface Descriptor:\r\n"); + USB_LOG_RAW("bLength: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bLength); + USB_LOG_RAW("bDescriptorType: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bDescriptorType); + USB_LOG_RAW("bInterfaceNumber: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bInterfaceNumber); + USB_LOG_RAW("bAlternateSetting: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bAlternateSetting); + USB_LOG_RAW("bNumEndpoints: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bNumEndpoints); + USB_LOG_RAW("bInterfaceClass: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bInterfaceClass); + USB_LOG_RAW("bInterfaceSubClass: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bInterfaceSubClass); + USB_LOG_RAW("bInterfaceProtocol: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bInterfaceProtocol); + USB_LOG_RAW("iInterface: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.iInterface); + + for (uint8_t k = 0; k < hport->config.intf[i].altsetting[j].intf_desc.bNumEndpoints; k++) { + USB_LOG_RAW("Endpoint Descriptor:\r\n"); + USB_LOG_RAW("bLength: 0x%02x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.bLength); + USB_LOG_RAW("bDescriptorType: 0x%02x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.bDescriptorType); + USB_LOG_RAW("bEndpointAddress: 0x%02x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.bEndpointAddress); + USB_LOG_RAW("bmAttributes: 0x%02x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.bmAttributes); + USB_LOG_RAW("wMaxPacketSize: 0x%04x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.wMaxPacketSize); + USB_LOG_RAW("bInterval: 0x%02x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.bInterval); + } + } + } +} + +static int usbh_get_default_mps(int speed) +{ + switch (speed) { + case USB_SPEED_LOW: /* For low speed, we use 8 bytes */ + return 8; + case USB_SPEED_FULL: /* For full or high speed, we use 64 bytes */ + case USB_SPEED_HIGH: + return 64; + case USB_SPEED_SUPER: /* For super speed , we must use 512 bytes */ + case USB_SPEED_SUPER_PLUS: + return 512; + default: + return 64; + } +} + +int usbh_hport_activate_ep0(struct usbh_hubport *hport) +{ + struct usbh_endpoint_cfg ep0_cfg = { 0 }; + + ep0_cfg.ep_addr = 0x00; + ep0_cfg.ep_interval = 0x00; + ep0_cfg.ep_mps = usbh_get_default_mps(hport->speed); + ep0_cfg.ep_type = USB_ENDPOINT_TYPE_CONTROL; + ep0_cfg.hport = hport; + + usbh_pipe_alloc(&hport->ep0, &ep0_cfg); + return 0; +} + +int usbh_hport_deactivate_ep0(struct usbh_hubport *hport) +{ + struct usbh_bus *usb = usbh_get_bus_of_port(hport); + +#ifndef CONFIG_USBHOST_XHCI + if (hport->dev_addr > 0) { + usbh_free_devaddr(&(usb->g_usbh_bus.devgen), hport->dev_addr); + } +#endif + if (hport->ep0) { + usbh_pipe_free(hport->ep0); + } + + hport->ep0 = NULL; + hport->dev_addr = 0; + return 0; +} + +int usbh_hport_activate_epx(usbh_pipe_t *pipe, struct usbh_hubport *hport, struct usb_endpoint_descriptor *ep_desc) +{ + struct usbh_endpoint_cfg ep_cfg = { 0 }; + + ep_cfg.ep_addr = ep_desc->bEndpointAddress; + ep_cfg.ep_type = ep_desc->bmAttributes & USB_ENDPOINT_TYPE_MASK; + ep_cfg.ep_mps = ep_desc->wMaxPacketSize & USB_MAXPACKETSIZE_MASK; + ep_cfg.ep_interval = ep_desc->bInterval; + ep_cfg.mult = (ep_desc->wMaxPacketSize & USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_MASK) >> USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT; + ep_cfg.hport = hport; + + USB_LOG_INFO("Ep=%02x Attr=%02u Mps=%d Interval=%02u Mult=%02u\r\n", + ep_cfg.ep_addr, + ep_desc->bmAttributes, + ep_cfg.ep_mps, + ep_cfg.ep_interval, + ep_cfg.mult); + + return usbh_pipe_alloc(pipe, &ep_cfg); +} + +int usbh_enumerate(struct usbh_hubport *hport) +{ + struct usb_interface_descriptor *intf_desc; + struct usb_device_descriptor *dev_desc; + struct usb_setup_packet *setup; + struct usbh_bus *usb = usbh_get_bus_of_port(hport); + int dev_addr; + uint16_t ep_mps; + int ret; + + hport->setup = &usb->g_setup[hport->parent->index - 1][hport->port - 1]; + setup = hport->setup; + + /* Read the first 8 bytes of the device descriptor */ + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup->wValue = (uint16_t)((USB_DESCRIPTOR_TYPE_DEVICE << 8) | 0); + setup->wIndex = 0; + setup->wLength = 8; + + dev_desc = (struct usb_device_descriptor *)usb->ep0_request_buffer; + ret = usbh_control_transfer(hport->ep0, setup, (uint8_t *)dev_desc); + if (ret < 0) { + USB_LOG_ERR("Failed to get device descriptor,errorcode:%d\r\n", ret); + goto errout; + } + + parse_device_descriptor(hport, dev_desc, 8); + + /* Extract the correct max packetsize from the device descriptor */ + if (dev_desc->bcdUSB >= USB_3_0) { + ep_mps = 1 << dev_desc->bMaxPacketSize0; + } else { + ep_mps = dev_desc->bMaxPacketSize0; + } + + USB_LOG_DBG("Device rev=%04x cls=%02x sub=%02x proto=%02x size=%d\r\n", + dev_desc->bcdUSB, dev_desc->bDeviceClass, dev_desc->bDeviceSubClass, + dev_desc->bDeviceProtocol, ep_mps); + + /* Reconfigure EP0 with the correct maximum packet size */ + usbh_ep_pipe_reconfigure(usb, hport->ep0, 0, ep_mps, 0); + +#ifdef CONFIG_USBHOST_XHCI + extern int usbh_get_xhci_devaddr(usbh_pipe_t * pipe); + + /* Assign a function address to the device connected to this port */ + dev_addr = usbh_get_xhci_devaddr(hport->ep0); + if (dev_addr < 0) { + USB_LOG_ERR("Failed to allocate devaddr,errorcode:%d\r\n", ret); + goto errout; + } +#else + /* Assign a function address to the device connected to this port */ + dev_addr = usbh_allocate_devaddr(&usb->devgen); + if (dev_addr < 0) { + USB_LOG_ERR("Failed to allocate devaddr,errorcode:%d\r\n", ret); + goto errout; + } +#endif + + /* Set the USB device address */ + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_SET_ADDRESS; + setup->wValue = dev_addr; + setup->wIndex = 0; + setup->wLength = 0; + + ret = usbh_control_transfer(hport->ep0, setup, NULL); + if (ret < 0) { + USB_LOG_ERR("Failed to set devaddr,errorcode:%d\r\n", ret); + goto errout; + } + + /* Wait device set address completely */ + usb_osal_msleep(2); + + /* Assign the function address to the port */ + hport->dev_addr = dev_addr; + + /* And reconfigure EP0 with the correct address */ + usbh_ep_pipe_reconfigure(usb, hport->ep0, dev_addr, ep_mps, 0); + + /* Read the full device descriptor */ + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup->wValue = (uint16_t)((USB_DESCRIPTOR_TYPE_DEVICE << 8) | 0); + setup->wIndex = 0; + setup->wLength = USB_SIZEOF_DEVICE_DESC; + + ret = usbh_control_transfer(hport->ep0, setup, usb->ep0_request_buffer); + if (ret < 0) { + USB_LOG_ERR("Failed to get full device descriptor,errorcode:%d\r\n", ret); + goto errout; + } + + parse_device_descriptor(hport, (struct usb_device_descriptor *)usb->ep0_request_buffer, USB_SIZEOF_DEVICE_DESC); + USB_LOG_INFO("New device found,idVendor:%04x,idProduct:%04x,bcdDevice:%04x\r\n", + ((struct usb_device_descriptor *)usb->ep0_request_buffer)->idVendor, + ((struct usb_device_descriptor *)usb->ep0_request_buffer)->idProduct, + ((struct usb_device_descriptor *)usb->ep0_request_buffer)->bcdDevice); + + /* Read the first 9 bytes of the config descriptor */ + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup->wValue = (uint16_t)((USB_DESCRIPTOR_TYPE_CONFIGURATION << 8) | 0); + setup->wIndex = 0; + setup->wLength = USB_SIZEOF_CONFIG_DESC; + + ret = usbh_control_transfer(hport->ep0, setup, usb->ep0_request_buffer); + if (ret < 0) { + USB_LOG_ERR("Failed to get config descriptor,errorcode:%d\r\n", ret); + goto errout; + } + + parse_config_descriptor(hport, (struct usb_configuration_descriptor *)usb->ep0_request_buffer, USB_SIZEOF_CONFIG_DESC); + + /* Read the full size of the configuration data */ + uint16_t wTotalLength = ((struct usb_configuration_descriptor *)usb->ep0_request_buffer)->wTotalLength; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup->wValue = (uint16_t)((USB_DESCRIPTOR_TYPE_CONFIGURATION << 8) | 0); + setup->wIndex = 0; + setup->wLength = wTotalLength; + + ret = usbh_control_transfer(hport->ep0, setup, usb->ep0_request_buffer); + if (ret < 0) { + USB_LOG_ERR("Failed to get full config descriptor,errorcode:%d\r\n", ret); + goto errout; + } + + ret = parse_config_descriptor(hport, (struct usb_configuration_descriptor *)usb->ep0_request_buffer, wTotalLength); + if (ret < 0) { + USB_LOG_ERR("Parse config fail\r\n"); + goto errout; + } + USB_LOG_INFO("The device has %d interfaces\r\n", ((struct usb_configuration_descriptor *)usb->ep0_request_buffer)->bNumInterfaces); + hport->raw_config_desc = usb_malloc(wTotalLength); + if (hport->raw_config_desc == NULL) { + ret = -ENOMEM; + USB_LOG_ERR("No memory to alloc for raw_config_desc\r\n"); + goto errout; + } + memcpy(hport->raw_config_desc, usb->ep0_request_buffer, wTotalLength); +#ifdef CONFIG_USBHOST_GET_STRING_DESC + /* Get Manufacturer string */ + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup->wValue = (uint16_t)((USB_DESCRIPTOR_TYPE_STRING << 8) | USB_STRING_MFC_INDEX); + setup->wIndex = 0x0409; + setup->wLength = 255; + + ret = usbh_control_transfer(hport->ep0, setup, usb->ep0_request_buffer); + if (ret < 0) { + USB_LOG_ERR("Failed to get Manufacturer string,errorcode:%d\r\n", ret); + goto errout; + } + + usbh_print_string("Manufacturer: ", usb->ep0_request_buffer); + + /* Get Product string */ + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup->wValue = (uint16_t)((USB_DESCRIPTOR_TYPE_STRING << 8) | USB_STRING_PRODUCT_INDEX); + setup->wIndex = 0x0409; + setup->wLength = 255; + + ret = usbh_control_transfer(hport->ep0, setup, usb->ep0_request_buffer); + if (ret < 0) { + USB_LOG_ERR("Failed to get get Product string,errorcode:%d\r\n", ret); + goto errout; + } + + usbh_print_string("Product: ", usb->ep0_request_buffer); + + /* Get SerialNumber string */ + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup->wValue = (uint16_t)((USB_DESCRIPTOR_TYPE_STRING << 8) | USB_STRING_SERIAL_INDEX); + setup->wIndex = 0x0409; + setup->wLength = 255; + + ret = usbh_control_transfer(hport->ep0, setup, usb->ep0_request_buffer); + if (ret < 0) { + USB_LOG_ERR("Failed to get get SerialNumber string,errorcode:%d\r\n", ret); + goto errout; + } + + usbh_print_string("SerialNumber: ", usb->ep0_request_buffer); +#endif + /* Select device configuration 1 */ + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_SET_CONFIGURATION; + setup->wValue = 1; + setup->wIndex = 0; + setup->wLength = 0; + + ret = usbh_control_transfer(hport->ep0, setup, NULL); + if (ret < 0) { + USB_LOG_ERR("Failed to set configuration,errorcode:%d\r\n", ret); + goto errout; + } + + USB_LOG_INFO("Enumeration success, start loading class driver\r\n"); + +#ifdef CONFIG_USBHOST_ENUM_FIRST_INTERFACE_ONLY + USB_LOG_INFO("Support %d Interfaces, select the first one \r\n", hport->config.config_desc.bNumInterfaces); + hport->config.config_desc.bNumInterfaces = 1U; +#endif + + /*search supported class driver*/ + for (uint8_t i = 0; i < hport->config.config_desc.bNumInterfaces; i++) { + intf_desc = &hport->config.intf[i].altsetting[0].intf_desc; + + struct usbh_class_driver *class_driver = (struct usbh_class_driver *)usbh_find_class_driver(intf_desc->bInterfaceClass, intf_desc->bInterfaceSubClass, intf_desc->bInterfaceProtocol, hport->device_desc.idVendor, hport->device_desc.idProduct); + + if (class_driver == NULL) { + USB_LOG_ERR("do not support Class:0x%02x,Subclass:0x%02x,Protocl:0x%02x\r\n", + intf_desc->bInterfaceClass, + intf_desc->bInterfaceSubClass, + intf_desc->bInterfaceProtocol); + + continue; + } + hport->config.intf[i].class_driver = class_driver; + USB_LOG_INFO("Class:0x%02x,Subclass:0x%02x,Protocl:0x%02x\r\n", + intf_desc->bInterfaceClass, + intf_desc->bInterfaceSubClass, + intf_desc->bInterfaceProtocol); + USB_LOG_RAW("Loading %s class driver\r\n", class_driver->driver_name); + ret = CLASS_CONNECT(hport, i); + } + +errout: + if (hport->raw_config_desc) { + usb_free(hport->raw_config_desc); + hport->raw_config_desc = NULL; + } + return ret; +} + +struct usbh_hubport *usbh_find_hubport(uint32_t usb_id, uint8_t dev_addr) +{ + struct usbh_hubport *hport; + struct usbh_bus *usb = usbh_get_bus_of_index(usb_id); + usb_slist_t *hub_list; + usb_slist_for_each(hub_list, &usb->hub_class_head) + { + struct usbh_hub *hub = usb_slist_entry(hub_list, struct usbh_hub, list); + for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + hport = &hub->child[port]; + if (hport->connected) { + if (hport->dev_addr == dev_addr) { + return &hub->child[port]; + } + } + } + } + return NULL; +} + +void *usbh_find_class_instance(const char *devname) +{ + struct usbh_hubport *hport; + usb_slist_t *hub_list; + struct usbh_bus* usb = usbh_get_bus_of_devname(devname); + if (!usb) { + return NULL; + } + + usb_slist_for_each(hub_list, &usb->hub_class_head) + { + struct usbh_hub *hub = usb_slist_entry(hub_list, struct usbh_hub, list); + for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + hport = &hub->child[port]; + if (hport->connected) { + for (uint8_t itf = 0; itf < hport->config.config_desc.bNumInterfaces; itf++) { + if ((strncmp(hport->config.intf[itf].devname, devname, CONFIG_USBHOST_DEV_NAMELEN) == 0) && hport->config.intf[itf].priv) + return hport->config.intf[itf].priv; + } + } + } + } + return NULL; +} + +int usbh_initialize(uint32_t id, struct usbh_bus *usb) +{ + memset(usb, 0, sizeof(struct usbh_bus)); + +#ifdef __ARMCC_VERSION /* ARM C Compiler */ + extern const int usbh_class_info$$Base; + extern const int usbh_class_info$$Limit; + usbh_class_info_table_begin = (struct usbh_class_info *)&usbh_class_info$$Base; + usbh_class_info_table_end = (struct usbh_class_info *)&usbh_class_info$$Limit; +#elif defined(__GNUC__) + extern uint32_t __usbh_class_info_start__; + extern uint32_t __usbh_class_info_end__; + usbh_class_info_table_begin = (struct usbh_class_info *)&__usbh_class_info_start__; + usbh_class_info_table_end = (struct usbh_class_info *)&__usbh_class_info_end__; +#elif defined(__ICCARM__) || defined(__ICCRX__) + usbh_class_info_table_begin = (struct usbh_class_info *)__section_begin("usbh_class_info"); + usbh_class_info_table_end = (struct usbh_class_info *)__section_end("usbh_class_info"); +#endif + + /* allocate usb bus */ + usb->mtu = 65536; + + /* devaddr 1 is for roothub */ + usb->devgen.next = 2; + + usb->hub_event_head.next = NULL; + usb->hub_class_head.next = NULL; + usb->id = id; + + usb_slist_add_tail(&usb_buses, &(usb->list)); + usbh_hub_initialize(usb); + return 0; +} + +int usbh_control_transfer(usbh_pipe_t pipe, struct usb_setup_packet *setup, uint8_t *buffer) +{ + struct usbh_urb *urb; + int ret; + + urb = usb_malloc(sizeof(struct usbh_urb)); + memset(urb, 0, sizeof(struct usbh_urb)); + + usbh_control_urb_fill(urb, pipe, setup, buffer, setup->wLength, CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT, NULL, NULL); + + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + usb_free(urb); + return ret; +} + +int lsusb(int argc, char **argv) +{ + usb_slist_t *i; + struct usbh_hubport *hport; + const char *opt = NULL; + int min_argc = 3; + int max_argc = 4; + uint8_t usb_id = 0; + + if (argc < min_argc) { + USB_LOG_RAW("Usage: lsusb [options]...\r\n"); + + USB_LOG_RAW("List USB devices\r\n"); + USB_LOG_RAW(" -v, --verbose\r\n"); + USB_LOG_RAW(" Increase verbosity (show descriptors)\r\n"); + // USB_LOG_RAW(" -s [[bus]:[devnum]]\r\n"); + // USB_LOG_RAW(" Show only devices with specified device and/or bus numbers (in decimal)\r\n"); + // USB_LOG_RAW(" -d vendor:[product]\r\n"); + // USB_LOG_RAW(" Show only devices with the specified vendor and product ID numbers (in hexadecimal)\r\n"); + USB_LOG_RAW(" -t, --tree\r\n"); + USB_LOG_RAW(" Dump the physical USB device hierachy as a tree\r\n"); + USB_LOG_RAW(" -V, --version\r\n"); + USB_LOG_RAW(" Show version of program\r\n"); + USB_LOG_RAW(" -h, --help\r\n"); + USB_LOG_RAW(" Show usage and help\r\n"); + return 0; + } + + if (argc > max_argc) { + return 0; + } + + usb_id = (uint8_t)strtoul(argv[1], NULL, 10); + struct usbh_bus* usb = usbh_get_bus_of_index(usb_id); + if (NULL == usb) { + return 0; + } + + opt = argv[2]; + + if (strcmp(opt, "-t") == 0) { + usb_slist_for_each(i, &usb->hub_class_head) + { + struct usbh_hub *hub = usb_slist_entry(i, struct usbh_hub, list); + + if (hub->is_roothub) { + USB_LOG_RAW("/: Hub %02u, ports=%u, is roothub\r\n", hub->index, hub->hub_desc.bNbrPorts); + } else { + USB_LOG_RAW("/: Hub %02u, ports=%u, mounted on Hub %02u:Port %u\r\n", + hub->index, + hub->hub_desc.bNbrPorts, + hub->parent->parent->index, + hub->parent->port); + } + + for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + hport = &hub->child[port]; + if (hport && hport->connected) { + for (uint8_t i = 0; i < hport->config.config_desc.bNumInterfaces; i++) { + if (hport->config.intf[i].class_driver && hport->config.intf[i].class_driver->driver_name) { + USB_LOG_RAW(" |__Port %u,Port addr:0x%02x,If %u,ClassDriver=%s\r\n", + hport->port, + hport->dev_addr, + i, + hport->config.intf[i].class_driver->driver_name); + } + } + } + } + } + } + + if (strcmp(opt, "-v") == 0) { + usb_slist_for_each(i, &usb->hub_class_head) + { + struct usbh_hub *hub = usb_slist_entry(i, struct usbh_hub, list); + for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + hport = &hub->child[port]; + if (hport->connected) { + USB_LOG_RAW("Hub %02u,Port %u,Port addr:0x%02x,VID:PID 0x%04x:0x%04x\r\n", + hub->index, + hport->port, + hport->dev_addr, + hport->device_desc.idVendor, + hport->device_desc.idProduct); + usbh_print_hubport_info(hport); + } + } + } + } + + return 0; +} \ No newline at end of file From 01a92a269c0f44b3dad0e493888391f455f675f5 Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 17 Jun 2024 02:50:14 -0700 Subject: [PATCH 029/198] Implant xhci codes --- .../usb/components/class/hub/usbh_hub.c | 6 + .../drivers/usb/components/osal/usb_osal.c | 12 + .../usb/components/port/xhci/usb_hc_xhci.c | 61 +- .../usb/components/port/xhci/usb_hc_xhci.h | 37 + .../drivers/usb/components/port/xhci/xhci.h | 970 ++++++++++++++++++ 5 files changed, 1083 insertions(+), 3 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c index b45dfb84a..cbf69aee1 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c @@ -1,2 +1,8 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ #include "usbh_hub.h" #include "usb_def.h" + diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c index c1bc3b220..7439f3f74 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c @@ -318,4 +318,16 @@ int usb_osal_mq_recv(usb_osal_mq_t mq, uintptr_t *addr, uint32_t timeout){ int usb_osal_mq_send(usb_osal_mq_t mq, uintptr_t addr){ return osal_mq_send((osal_msg_queue_t)mq, &addr, sizeof(uintptr_t *), 0); +} + + + +size_t usb_osal_enter_critical_section(void){ + return 0; +} + + + +void usb_osal_leave_critical_section(size_t flag){ + } \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index 4ee4cdec2..c680dabd9 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -26,14 +26,69 @@ /************************************************* -File name: usb_hc_xhci.h +File name: usb_hc_xhci.c Description: the xhci functions to dock with the USB core layer. -Others: take CherryUSB v0.1.2/CherryUSB/osal/usb_osal.h for references - https://github.com/cherry-embedded/CherryUSB/blob/v0.10.2/osal/usb_osal.h +Others: take CherryUSB v0.1.2/port/xhci/usb_hc_xhci.c for references + https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/blob/master/third-party/cherryusb/port/xhci/usb_hc_xhci.c History: 1. Date: 2024-06-17 Author: AIIT XUOS Lab Modification: rewrite xhci functions to dock with USB core layer, so that the USB core can easily expand to other USB IP. *************************************************/ #include "usb_hc_xhci.h" +#include "usbh_hub.h" +#include "xhci.h" + +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +// static struct xhci_host xhci_host[CONFIG_USBHOST_XHCI_NUM]; + +__WEAK void usb_hc_low_level_init(uint32_t id) +{ + +} + + + +__WEAK void *usb_hc_malloc(size_t size) +{ + return NULL; +} + + + +__WEAK void *usb_hc_malloc_align(size_t align, size_t size) +{ + return NULL; +} + + + +__WEAK void usb_hc_free() +{ +} + + + +/* one may get xhci register base address by PCIe bus emuration */ +__WEAK unsigned long usb_hc_get_register_base(uint32_t id) +{ + return 0U; +} + + + +static inline struct xhci_host* xhci_get_inst_of_port(struct usbh_hubport *hport) { + USB_ASSERT(hport && hport->parent); + struct usbh_bus *usb = hport->parent->usb; + return (struct xhci_host*)usb->priv; +} + diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h index c1821f1fe..a71e7fc4f 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h @@ -1,3 +1,40 @@ +/* + * Copyright : (C) 2022 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: usb_hc_xhci.h + * Date: 2022-07-19 09:26:25 + * LastEditTime: 2022-07-19 09:26:25 + * Description: This file is for xhci data structure definition. + * + * Modify History: + * Ver Who Date Changes + * ----- ------ -------- -------------------------------------- + * 1.0 zhugengyu 2022/9/19 init commit + * 2.0 zhugengyu 2023/3/29 support usb3.0 device attached at roothub + */ + + /************************************************* +File name: usb_hc_xhci.h +Description: the xhci functions to dock with the USB core layer. +Others: take CherryUSB v0.1.2/port/xhci/usb_hc_xhci.h for references + https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/blob/master/third-party/cherryusb/port/xhci/usb_hc_xhci.h +History: +1. Date: 2024-06-17 +Author: AIIT XUOS Lab +Modification: rewrite xhci functions to dock with USB core layer, so that the xhci can unbind the USB core. + It means the USB core can be esily dock with to other USB IP in future. +*************************************************/ + #ifndef USB_HC_XHCI_H_ #define USB_HC_XHCI_H_ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h index b52d35f8e..0d8bff14f 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h @@ -1,9 +1,979 @@ +/* + * Copyright : (C) 2022 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: xhci.h + * Date: 2022-07-19 09:26:25 + * LastEditTime: 2022-07-19 09:26:25 + * Description: This file is for xhci register definition. + * + * Modify History: + * Ver Who Date Changes + * ----- ------ -------- -------------------------------------- + * 1.0 zhugengyu 2022/9/19 init commit + * 2.0 zhugengyu 2023/3/29 support usb3.0 device attached at roothub + */ + + /************************************************* +File name: xhci.h +Description: the xhci data structure. +Others: take CherryUSB v0.1.2/port/xhci/xhci.h for references + https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/blob/master/third-party/cherryusb/port/xhci/xhci.h +History: +1. Date: 2024-06-17 +Author: AIIT XUOS Lab +Modification: replant and redefine some xhci data structure, so that the cherryUSB can adapt to XiZi AIOT. +*************************************************/ #ifndef XHCI_H_ #define XHCI_H_ #include "xhci_reg.h" +#include "usbh_core.h" + +/** @file + * + * USB eXtensible Host Controller Interface (xHCI) driver + * + */ +#define XHCI_RING_ITEMS 16U +#define XHCI_ALIGMENT 64U +#define XHCI_RING_SIZE (XHCI_RING_ITEMS * sizeof(union xhci_trb)) +/* + * xhci_ring structs are allocated with XHCI_RING_SIZE alignment, + * then we can get it from a trb pointer (provided by evt ring). + */ +#define XHCI_RING(_trb) \ + ((struct xhci_ring*)((unsigned long)(_trb) & ~(XHCI_RING_SIZE-1))) + +/** Device context base address array */ +struct xhci_dcbaa { + /** Context base addresses */ + uint64_t *context; +}; + + + + +/** Scratchpad buffer */ +struct xhci_scratchpad { + /** Number of page-sized scratchpad buffers */ + unsigned int count; + /** Scratchpad buffer area */ + uintptr_t buffer; + /** Scratchpad array */ + uint64_t *array; +}; + +/** An input control context */ +struct xhci_control_context { + /** Drop context flags */ + uint32_t drop; + /** Add context flags */ + uint32_t add; + /** Reserved */ + uint32_t reserved_a[5]; + /** Configuration value */ + uint8_t config; + /** Interface number */ + uint8_t intf; + /** Alternate setting */ + uint8_t alt; + /** Reserved */ + uint8_t reserved_b; +} __attribute__ (( packed )); + +/** A slot context */ +struct xhci_slot_context { + /** Device info 03-00h */ + uint32_t info; + /** Maximum exit latency */ + uint16_t latency; + /** Root hub port number */ + uint8_t port; + /** Number of downstream ports 07-04h */ + uint8_t ports; + /** TT hub slot ID */ + uint8_t tt_id; + /** TT port number */ + uint8_t tt_port; + /** Interrupter target 0b-08h */ + uint16_t intr; + /** USB address */ + uint8_t address; + /** Reserved */ + uint16_t reserved_a; + /** Slot state 0f-0ch */ + uint8_t state; + /** Reserved */ + uint32_t reserved_b[4]; +} __attribute__ (( packed )); + +/** Construct slot context device info */ +#define XHCI_SLOT_INFO( entries, hub, speed, route ) \ + ( ( (entries) << 27 ) | ( (hub) << 26 ) | ( (speed) << 20 ) | (route) ) + +/** An endpoint context */ +struct xhci_endpoint_context { + /** Endpoint state 03-00h*/ + uint8_t state; + /** Stream configuration */ + uint8_t stream; +#define XHCI_EPCTX_MULT_GET(stream) XHCI32_GET_BITS(stream, 1, 0) +#define XHCI_EPCTX_STREAM_GET(stream) XHCI32_GET_BITS(stream, 6, 2) +#define XHCI_EPCTX_LSA BIT(7) + /** Polling interval */ + uint8_t interval; + /** Max ESIT payload high */ + uint8_t esit_high; + /** Endpoint type 04-04h */ + uint8_t type; +#define XHCI_EPCTX_CERR_GET(type) XHCI32_GET_BITS(type, 2, 1) +#define XHCI_EPCTX_TYPE_GET(type) XHCI32_GET_BITS(type, 5, 3) +#define XHCI_EPCTX_HID BIT(7) + /** Maximum burst size */ + uint8_t burst; + /** Maximum packet size */ + uint16_t mtu; + /** Transfer ring dequeue pointer 0f-08h */ + uint64_t dequeue; +#define XHCI_EPCTX_DCS BIT(0) + /** Average TRB length 13-10h */ + uint16_t trb_len; + /** Max ESIT payload low */ + uint16_t esit_low; + /** Reserved */ + uint32_t reserved[3]; +} __attribute__ (( packed )); + +/** Endpoint states */ +enum { + /** Endpoint is disabled */ + XHCI_ENDPOINT_DISABLED = 0, + /** Endpoint is running */ + XHCI_ENDPOINT_RUNNING = 1, + /** Endpoint is halted due to a USB Halt condition */ + XHCI_ENDPOINT_HALTED = 2, + /** Endpoint is stopped */ + XHCI_ENDPOINT_STOPPED = 3, + /** Endpoint is halted due to a TRB error */ + XHCI_ENDPOINT_ERROR = 4, +}; + +/** Endpoint state mask */ +#define XHCI_ENDPOINT_STATE_MASK 0x07 + +/** Endpoint type */ +#define XHCI_EP_TYPE(type) ( (type) << 3 ) + +/** Control endpoint type */ +#define XHCI_EP_TYPE_CONTROL XHCI_EP_TYPE ( 4 ) + +/** Input endpoint type */ +#define XHCI_EP_TYPE_IN XHCI_EP_TYPE ( 4 ) + +/** Periodic endpoint type */ +#define XHCI_EP_TYPE_PERIODIC XHCI_EP_TYPE ( 1 ) + +/** Endpoint dequeue cycle state */ +#define XHCI_EP_DCS 0x00000001UL + +/** Control endpoint average TRB length */ +#define XHCI_EP0_TRB_LEN 8 + +/** + * Calculate doorbell register value + * + * @v target Doorbell target + * @v stream Doorbell stream ID + * @ret dbval Doorbell register value + */ +#define XHCI_DBVAL( target, stream ) ( (target) | ( (stream) << 16 ) ) + + +/** Slot context index */ +#define XHCI_CTX_SLOT 0 + +/** Calculate context index from USB endpoint address */ +/* refer to spec. Figure 4-4: Endpoint Context Addressing + ep0 = 1, ep1-out = 2, ep1-in = 3, ... ep15-out = 30, ep15-in = 31 */ +#define XHCI_CTX(address) \ + ( (address) ? ( ( ( (address) & 0x0f ) << 1 ) | \ + ( ( (address) & 0x80 ) >> 7 ) ) : 1 ) + +/** Endpoint zero context index */ +#define XHCI_CTX_EP0 XHCI_CTX ( 0x00 ) + +/** End of contexts */ +#define XHCI_CTX_END 32 + +/** Device context index */ +#define XHCI_DCI(ctx) ( (ctx) + 0 ) + +/** Input context index */ +#define XHCI_ICI(ctx) ( (ctx) + 1 ) + +/** Number of TRBs (excluding Link TRB) in the command ring + * + * This is a policy decision. + */ +#define XHCI_CMD_TRBS_LOG2 2 + +/** Number of TRBs in the event ring + * + * This is a policy decision. + */ +#define XHCI_EVENT_TRBS_LOG2 6 + +/** Number of TRBs in a transfer ring + * + * This is a policy decision. + */ +#define XHCI_TRANSFER_TRBS_LOG2 6 + +/** Maximum time to wait for BIOS to release ownership + * + * This is a policy decision. + */ +#define XHCI_USBLEGSUP_MAX_WAIT_MS 100 + +/** Maximum time to wait for host controller to stop + * + * This is a policy decision. + */ +#define XHCI_STOP_MAX_WAIT_MS 100 + +/** Maximum time to wait for reset to complete + * + * This is a policy decision. + */ +#define XHCI_RESET_MAX_WAIT_MS 500 + +/** Maximum time to wait for a command to complete + * + * The "address device" command involves waiting for a response to a + * USB control transaction, and so we must wait for up to the 5000ms + * that USB allows for devices to respond to control transactions. + */ +#define XHCI_COMMAND_MAX_WAIT_MS 5000 + +/** Time to delay after aborting a command + * + * This is a policy decision + */ +#define XHCI_COMMAND_ABORT_DELAY_MS 500 + +/** Maximum time to wait for a port reset to complete + * + * This is a policy decision. + */ +#define XHCI_PORT_RESET_MAX_WAIT_MS 500 + + + /** A transfer request block template */ +struct xhci_trb_template { + /** Parameter */ + uint64_t parameter; + /** Status */ + uint32_t status; + /** Control */ + uint32_t control; +}; + + +/** A transfer request block */ +struct xhci_trb_common { + /** Reserved */ + uint64_t reserved_a; + /** Reserved */ + uint32_t reserved_b; + /** Flags */ + uint8_t flags; + /** Type */ + uint8_t type; + /** Reserved */ + uint16_t reserved_c; +} __attribute__ (( packed )); + + +/** Transfer request block cycle bit flag */ +#define XHCI_TRB_C 0x01 + +/** Transfer request block toggle cycle bit flag */ +#define XHCI_TRB_TC 0x02 + +/** Transfer request block chain flag */ +#define XHCI_TRB_CH 0x10 + +/** Transfer request block interrupt on completion flag */ +#define XHCI_TRB_IOC 0x20 + +/** Transfer request block immediate data flag */ +#define XHCI_TRB_IDT 0x40 + +/** Transfer request block type */ +#define XHCI_TRB_TYPE(type) ( (type) << 2 ) + +/** Transfer request block type mask */ +#define XHCI_TRB_TYPE_MASK XHCI_TRB_TYPE ( 0x3f ) + + +/** A normal transfer request block */ +struct xhci_trb_normal { + /** Data buffer */ + uint64_t data; + /** Length */ + uint32_t len; + /** Flags */ + uint8_t flags; + /** Type */ + uint8_t type; + /** Reserved */ + uint16_t reserved; +} __attribute__ (( packed )); + +/** A normal transfer request block */ +#define XHCI_TRB_NORMAL XHCI_TRB_TYPE ( 1 ) + +/** Construct TD size field */ +#define XHCI_TD_SIZE(remaining) \ + ( ( ( (remaining) <= 0xf ) ? remaining : 0xf ) << 17 ) + + + + +/** A setup stage transfer request block */ +struct xhci_trb_setup { + /** Setup packet, 04-00h sw will copy request content to this field */ + struct usb_setup_packet packet; + /** Length 08h */ + uint32_t len; + /** Flags 0ch */ + uint8_t flags; + /** Type */ + uint8_t type; + /** Transfer direction */ + uint8_t direction; + /** Reserved */ + uint8_t reserved; +} __attribute__ (( packed )); + +/** A setup stage transfer request block */ +#define XHCI_TRB_SETUP XHCI_TRB_TYPE ( 2 ) + +/** Setup stage input data direction */ +#define XHCI_SETUP_IN 3 + +/** Setup stage output data direction */ +#define XHCI_SETUP_OUT 2 + + + +/** A data stage transfer request block */ +struct xhci_trb_data { + /** Data buffer */ + uint64_t data; + /** Length */ + uint32_t len; + /** Flags */ + uint8_t flags; + /** Type */ + uint8_t type; + /** Transfer direction */ + uint8_t direction; + /** Reserved */ + uint8_t reserved; +} __attribute__ (( packed )); + +/** A data stage transfer request block */ +#define XHCI_TRB_DATA XHCI_TRB_TYPE ( 3 ) + +/** Input data direction */ +#define XHCI_DATA_IN 0x01 + +/** Output data direction */ +#define XHCI_DATA_OUT 0x00 + +/** A status stage transfer request block */ +struct xhci_trb_status { + /** Reserved */ + uint64_t reserved_a; + /** Reserved */ + uint32_t reserved_b; + /** Flags */ + uint8_t flags; + /** Type */ + uint8_t type; + /** Direction */ + uint8_t direction; + /** Reserved */ + uint8_t reserved_c; +} __attribute__ (( packed )); + +/** A status stage transfer request block */ +#define XHCI_TRB_STATUS XHCI_TRB_TYPE ( 4 ) + +/** Input status direction */ +#define XHCI_STATUS_IN 0x01 + +/** Output status direction */ +#define XHCI_STATUS_OUT 0x00 + +/** A link transfer request block */ +struct xhci_trb_link { + /** Next ring segment */ + uint64_t next; + /** Reserved */ + uint32_t reserved_a; + /** Flags */ + uint8_t flags; + /** Type */ + uint8_t type; + /** Reserved */ + uint16_t reserved_c; +} __attribute__ (( packed )); + +/** A link transfer request block */ +#define XHCI_TRB_LINK XHCI_TRB_TYPE ( 6 ) + +/** A no-op transfer request block */ +#define XHCI_TRB_NOP XHCI_TRB_TYPE ( 8 ) + + + + +/** An enable slot transfer request block */ +struct xhci_trb_enable_slot { + /** Reserved */ + uint64_t reserved_a; + /** Reserved */ + uint32_t reserved_b; + /** Flags */ + uint8_t flags; + /** Type */ + uint8_t type; + /** Slot type */ + uint8_t slot; + /** Reserved */ + uint8_t reserved_c; +} __attribute__ (( packed )); + +/** An enable slot transfer request block */ +#define XHCI_TRB_ENABLE_SLOT XHCI_TRB_TYPE ( 9 ) + +/** A disable slot transfer request block */ +struct xhci_trb_disable_slot { + /** Reserved */ + uint64_t reserved_a; + /** Reserved */ + uint32_t reserved_b; + /** Flags */ + uint8_t flags; + /** Type */ + uint8_t type; + /** Reserved */ + uint8_t reserved_c; + /** Slot ID */ + uint8_t slot; +} __attribute__ (( packed )); + +/** A disable slot transfer request block */ +#define XHCI_TRB_DISABLE_SLOT XHCI_TRB_TYPE ( 10 ) + +/** A context transfer request block */ +struct xhci_trb_context { + /** Input context */ + uint64_t input; + /** Reserved */ + uint32_t reserved_a; + /** Flags */ + uint8_t flags; + /** Type */ + uint8_t type; + /** Reserved */ + uint8_t reserved_b; + /** Slot ID */ + uint8_t slot; +} __attribute__ (( packed )); + +/** An address device transfer request block */ +#define XHCI_TRB_ADDRESS_DEVICE XHCI_TRB_TYPE ( 11 ) + +/** A configure endpoint transfer request block */ +#define XHCI_TRB_CONFIGURE_ENDPOINT XHCI_TRB_TYPE ( 12 ) + +/** An evaluate context transfer request block */ +#define XHCI_TRB_EVALUATE_CONTEXT XHCI_TRB_TYPE ( 13 ) + +/** A reset endpoint transfer request block */ +struct xhci_trb_reset_endpoint { + /** Reserved */ + uint64_t reserved_a; + /** Reserved */ + uint32_t reserved_b; + /** Flags */ + uint8_t flags; + /** Type */ + uint8_t type; + /** Endpoint ID */ + uint8_t endpoint; + /** Slot ID */ + uint8_t slot; +} __attribute__ (( packed )); + +/** A reset endpoint transfer request block */ +#define XHCI_TRB_RESET_ENDPOINT XHCI_TRB_TYPE ( 14 ) + +/** A stop endpoint transfer request block */ +struct xhci_trb_stop_endpoint { + /** Reserved */ + uint64_t reserved_a; + /** Reserved */ + uint32_t reserved_b; + /** Flags */ + uint8_t flags; + /** Type */ + uint8_t type; + /** Endpoint ID */ + uint8_t endpoint; + /** Slot ID */ + uint8_t slot; +} __attribute__ (( packed )); + +/** A stop endpoint transfer request block */ +#define XHCI_TRB_STOP_ENDPOINT XHCI_TRB_TYPE ( 15 ) + +/** A set transfer ring dequeue pointer transfer request block */ +struct xhci_trb_set_tr_dequeue_pointer { + /** Dequeue pointer */ + uint64_t dequeue; + /** Reserved */ + uint32_t reserved; + /** Flags */ + uint8_t flags; + /** Type */ + uint8_t type; + /** Endpoint ID */ + uint8_t endpoint; + /** Slot ID */ + uint8_t slot; +} __attribute__ (( packed )); + +/** A set transfer ring dequeue pointer transfer request block */ +#define XHCI_TRB_SET_TR_DEQUEUE_POINTER XHCI_TRB_TYPE ( 16 ) + +/** A no-op command transfer request block */ +#define XHCI_TRB_NOP_CMD XHCI_TRB_TYPE ( 23 ) + +/** A transfer event transfer request block */ +struct xhci_trb_transfer { + /** Transfer TRB pointer */ + uint64_t transfer; + /** Residual transfer length */ + uint16_t residual; + /** Reserved */ + uint8_t reserved; + /** Completion code */ + uint8_t code; + /** Flags */ + uint8_t flags; + /** Type */ + uint8_t type; + /** Endpoint ID */ + uint8_t endpoint; + /** Slot ID */ + uint8_t slot; +} __attribute__ (( packed )); + +/** A transfer event transfer request block */ +#define XHCI_TRB_TRANSFER XHCI_TRB_TYPE ( 32 ) + +/** A command completion event transfer request block */ +struct xhci_trb_complete { + /** Command TRB pointer */ + uint64_t command; + /** Parameter */ + uint8_t parameter[3]; + /** Completion code */ + uint8_t code; + /** Flags */ + uint8_t flags; + /** Type */ + uint8_t type; + /** Virtual function ID */ + uint8_t vf; + /** Slot ID */ + uint8_t slot; +} __attribute__ (( packed )); + +/** A command completion event transfer request block */ +#define XHCI_TRB_COMPLETE XHCI_TRB_TYPE ( 33 ) + +/** xHCI completion codes */ +enum xhci_completion_code { + /** Timeout */ + XHCI_CMPLT_TIMEOUT = -1, + /** Success */ + XHCI_CMPLT_SUCCESS = 1, + /** Stall Error */ + XHCI_CMPLT_STALL = 6, + /** Bandwidth Error */ + XHCI_CMPLT_BANDWIDTH = 8, + /** Endpoint Not Enabled Error */ + XHCI_CMPLT_ENDPOINT_NOT_ENABLED = 12, + /** Short packet */ + XHCI_CMPLT_SHORT = 13, + /** Parameter Error */ + XHCI_CMPLT_PARAMETER = 17, + /** Command ring stopped */ + XHCI_CMPLT_CMD_STOPPED = 24, +}; + +/** A port status change transfer request block */ +struct xhci_trb_port_status { + /** Reserved */ + uint8_t reserved_a[3]; + /** Port ID */ + uint8_t port; + /** Reserved */ + uint8_t reserved_b[7]; + /** Completion code */ + uint8_t code; + /** Flags */ + uint8_t flags; + /** Type */ + uint8_t type; + /** Reserved */ + uint16_t reserved_c; +} __attribute__ (( packed )); + +/** A port status change transfer request block */ +#define XHCI_TRB_PORT_STATUS XHCI_TRB_TYPE ( 34 ) + +/** A port status change transfer request block */ +struct xhci_trb_host_controller { + /** Reserved */ + uint64_t reserved_a; + /** Reserved */ + uint8_t reserved_b[3]; + /** Completion code */ + uint8_t code; + /** Flags */ + uint8_t flags; + /** Type */ + uint8_t type; + /** Reserved */ + uint16_t reserved_c; +} __attribute__ (( packed )); + +/** A port status change transfer request block */ +#define XHCI_TRB_HOST_CONTROLLER XHCI_TRB_TYPE ( 37 ) + +/** A transfer request block */ +union xhci_trb { + /** Template */ + struct xhci_trb_template template; + /** Common fields */ + struct xhci_trb_common common; + /** Normal TRB */ + struct xhci_trb_normal normal; + /** Setup stage TRB */ + struct xhci_trb_setup setup; + /** Data stage TRB */ + struct xhci_trb_data data; + /** Status stage TRB */ + struct xhci_trb_status status; + /** Link TRB */ + struct xhci_trb_link link; + /** Enable slot TRB */ + struct xhci_trb_enable_slot enable; + /** Disable slot TRB */ + struct xhci_trb_disable_slot disable; + /** Input context TRB */ + struct xhci_trb_context context; + /** Reset endpoint TRB */ + struct xhci_trb_reset_endpoint reset; + /** Stop endpoint TRB */ + struct xhci_trb_stop_endpoint stop; + /** Set transfer ring dequeue pointer TRB */ + struct xhci_trb_set_tr_dequeue_pointer dequeue; + /** Transfer event */ + struct xhci_trb_transfer transfer; + /** Command completion event */ + struct xhci_trb_complete complete; + /** Port status changed event */ + struct xhci_trb_port_status port; + /** Host controller event */ + struct xhci_trb_host_controller host; +} __attribute__ (( packed )); + + + + +struct xhci_ring { + union xhci_trb ring[XHCI_RING_ITEMS]; + union xhci_trb evt; + uint32_t eidx; + uint32_t nidx; + uint32_t cs; + usb_osal_mutex_t lock; +}; + + + + +/** An event ring segment */ +struct xhci_er_seg { + /** Base address */ + uint64_t base; + /** Number of TRBs */ + uint32_t count; + /** Reserved */ + uint32_t reserved; +} __attribute__ (( packed )); + +/** An xHCI endpoint */ +struct xhci_endpoint { + struct xhci_ring reqs; /* DO NOT MOVE reqs from structure beg */ + /** xHCI device */ + struct xhci_host *xhci; + /** xHCI slot */ + struct xhci_slot *slot; + /** Endpoint address */ + unsigned int address; + /** Context index */ + unsigned int ctx; + /** Endpoint type in USB definition */ + unsigned int ep_type; + /** Endpoint type in XHCI Endpoint context definition */ + unsigned int ctx_type; + + /** Maximum transfer size (Maximum packet size) */ + unsigned int mtu; + /** Maximum burst size */ + unsigned int burst; + /** Endpoint interval */ + unsigned int interval; + + /** Endpoint context */ + struct xhci_endpoint_context *context; + + /* command or transfer waiter */ + int timeout; /* = 0 no need to wait */ + bool waiter; + usb_osal_sem_t waitsem; + + /* handle urb */ + struct usbh_hubport *hport; + struct usbh_urb *urb; /* NULL if no active URB */ +}; + +/** An xHCI device slot */ +struct xhci_slot { + /** xHCI device */ + struct xhci_host *xhci; + /** Slot ID */ + unsigned int id; + /** Slot context */ + struct xhci_slot_context *context; + + /** Route string */ + unsigned int route; + /** Root hub port number */ + unsigned int port; + /** Protocol speed ID */ + unsigned int psiv; + /** Number of ports (if this device is a hub) */ + unsigned int ports; + /** Transaction translator slot ID */ + unsigned int tt_id; + /** Transaction translator port */ + unsigned int tt_port; + + /** Endpoints, indexed by context ID */ + struct xhci_endpoint *endpoint[XHCI_CTX_END]; +}; + +/** An xHCI device */ +struct xhci_host { + /** USB bus */ + struct usbh_bus *bus; + /** Name */ + char name[4]; + + /* xhci registers base addr */ + /** Registers base */ + void *base; + /** Capability registers */ + void *cap; + /** Operational registers */ + void *op; + /** Runtime registers */ + void *run; + /** Doorbell registers */ + void *db; + /** extended capability */ + unsigned int xecp; + /** capability cache */ + uint32_t hcs[3]; + uint32_t hcc; + /** xhci version */ + uint16_t version; + + /** Number of device slots */ + unsigned int slots; + /** Number of interrupters */ + unsigned int intrs; + /** Number of ports */ + unsigned int ports; + + /** 64-bit addressing capability */ + int addr64; + /** Context size shift */ + unsigned int csz_shift; + /** Page size */ + size_t pagesize; + + /** USB legacy support capability (if present and enabled) */ + unsigned int legacy; + + /** Device context base address array */ + void *phy_acbaa; + struct xhci_dcbaa dcbaa; + + /** Scratchpad buffer */ + void *phy_scratch; + + struct xhci_scratchpad scratch; + + /** Device slots, indexed by slot ID */ + void **phy_slot; + struct xhci_slot **slot; + + /** Command ring */ + struct xhci_ring *cmds; + /** Event ring */ + struct xhci_ring *evts; + struct xhci_er_seg *eseg; + + struct xhci_endpoint *cur_cmd_pipe; +}; + + + + +/** + * Calculate input context offset + * + * @v xhci xHCI device + * @v ctx Context index + */ +static inline size_t xhci_input_context_offset ( struct xhci_host *xhci, + unsigned int ctx ) { + + return ( XHCI_ICI ( ctx ) << xhci->csz_shift ); +} + +/** + * Calculate device context offset + * + * @v xhci xHCI device + * @v ctx Context index + */ +static inline size_t xhci_device_context_offset ( struct xhci_host *xhci, + unsigned int ctx ) { + + return ( XHCI_DCI ( ctx ) << xhci->csz_shift ); +} + +/* Probe XCHI device */ +int xhci_probe ( struct xhci_host *xhci, unsigned long baseaddr ); + +/* Open XHCI device and start running */ +int xhci_open ( struct xhci_host *xhci ); + +/* Close XHCI device and stop running */ +void xhci_close ( struct xhci_host *xhci ); + +/* Remove XHCI device and free allocated memory */ +void xhci_remove ( struct xhci_host *xhci ); + +/* Enable port */ +int xhci_port_enable (struct xhci_host *xhci, uint32_t port); + +/* Get port speed */ +uint32_t xhci_root_speed ( struct xhci_host *xhci, uint8_t port ); + +/* Open and enable device */ +int xhci_device_open ( struct xhci_host *xhci, struct xhci_endpoint *pipe, int *slot_id ); + +/* Assign device address */ +int xhci_device_address ( struct xhci_host *xhci, struct xhci_slot *slot, struct xhci_endpoint *pipe ); + +/* Close device and free allocated memory */ +void xhci_device_close ( struct xhci_slot *slot ); + +/* Open control endpoint for slot */ +int xhci_ctrl_endpoint_open ( struct xhci_host *xhci, struct xhci_slot *slot, struct xhci_endpoint *pipe ); + +/* Open work endpoint for slot */ +int xhci_work_endpoint_open ( struct xhci_host *xhci, struct xhci_slot *slot, struct xhci_endpoint *pipe ); + +/* Close endpoint and free allocated memory */ +void xhci_endpoint_close ( struct xhci_endpoint *ep ); + +/* Update MTU (Max packet size) of endpoint */ +int xhci_endpoint_mtu ( struct xhci_endpoint *ep ); + +/* Enqueue message transfer, usually for control transfer */ +void xhci_endpoint_message ( struct xhci_endpoint *ep, struct usb_setup_packet *packet, + void *data_buff, int datalen ); + +/* Enqueue stream transfer, usually for bulk/interrupt transfer */ +void xhci_endpoint_stream ( struct xhci_endpoint *ep, void *data_buff, int datalen ); + +/* Process event ring in interrupt */ +void xhci_event_process(struct xhci_host *xhci); + +/* Wait for a ring to empty (all TRBs processed by hardware) */ +int xhci_event_wait(struct xhci_host *xhci, + struct xhci_endpoint *pipe, + struct xhci_ring *ring); + +/* Dump host controller registers */ +void xhci_dump(struct xhci_host *xhci); + +/* Dump port registers */ +void xhci_dump_port ( struct xhci_host *xhci, + unsigned int port ); + +/* Dump Port status */ +void xhci_dump_port_status(uint32_t port, uint32_t portsc); + +/* Dump input context */ +void xhci_dump_input_ctx( struct xhci_host *xhci, const struct xhci_endpoint *endpoint, const void *input); + +/* Dump Endpoint */ +void xhci_dump_endpoint(const struct xhci_endpoint *ep); + +/* Dump endpoint context */ +void xhci_dump_ep_ctx(const struct xhci_endpoint_context *ep); + +/* Dump TRB */ +void xhci_dump_trbs(const union xhci_trb *trbs, unsigned int count); + +/* Dump slot context */ +void xhci_dump_slot_ctx(const struct xhci_slot_context *const sc); #endif From 303737e590912146212fcc4868cdb052f5a7a801 Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 17 Jun 2024 19:01:59 -0700 Subject: [PATCH 030/198] Copy xhci functions first. We should redevelop xhci functions step by step --- .../usb/components/port/xhci/usb_hc_xhci.c | 444 +++ .../drivers/usb/components/port/xhci/xhci.c | 2605 +++++++++++++++++ 2 files changed, 3049 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index c680dabd9..51057192c 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -91,4 +91,448 @@ static inline struct xhci_host* xhci_get_inst_of_port(struct usbh_hubport *hport return (struct xhci_host*)usb->priv; } +static struct xhci_host xhci_host[CONFIG_USBHOST_XHCI_NUM]; +/* xhci hardware init */ +int usb_hc_init(uint32_t id) +{ + USB_ASSERT(id < CONFIG_USBHOST_XHCI_NUM); + int rc = 0; + struct usbh_bus *bus = usbh_get_bus_of_index(id); + USB_ASSERT(bus); + struct xhci_host *xhci = &(xhci_host[id]); + + size_t flag = usb_osal_enter_critical_section(); /* no interrupt when init hc */ + + usb_hc_low_level_init(id); /* set gic and memp */ + + memset(xhci, 0, sizeof(*xhci)); + xhci->bus = bus; + bus->priv = xhci; + if (rc = xhci_probe(xhci, usb_hc_get_register_base(id)) != 0) { + goto err_open; + } + + if (rc = xhci_open(xhci) != 0 ) { + goto err_open; + } + + err_open: + usb_osal_leave_critical_section(flag); + return rc; +} + + + +int usbh_roothub_control(struct usbh_bus *usb, struct usb_setup_packet *setup, uint8_t *buf) +{ + uint8_t nports; + uint8_t port; + uint32_t portsc; + uint32_t status; + int ret = 0; + struct xhci_host *xhci = usb->priv; + nports = CONFIG_USBHOST_MAX_RHPORTS; + + port = setup->wIndex; + + /* + bmRequestType bit[4:0], define whether the request is directed to the device (0000b), + specific interface (00001b), endpoint (00010b), or other element (00011b) + bRequest, identifies the request + wValue, pass the request-specific info to the device + */ + if (setup->bmRequestType & USB_REQUEST_RECIPIENT_DEVICE) /* request is directed to device */ + { + switch (setup->bRequest) + { + case HUB_REQUEST_CLEAR_FEATURE: /* disable the feature */ + switch (setup->wValue) + { + case HUB_FEATURE_HUB_C_LOCALPOWER: + USB_LOG_ERR("HUB_FEATURE_HUB_C_LOCALPOWER not implmented.\n"); + break; + case HUB_FEATURE_HUB_C_OVERCURRENT: + USB_LOG_ERR("HUB_FEATURE_HUB_C_OVERCURRENT not implmented.\n"); + break; + default: + return -EPIPE; + } + break; + case HUB_REQUEST_SET_FEATURE: /* set a value reported in the hub status */ + switch (setup->wValue) + { + case HUB_FEATURE_HUB_C_LOCALPOWER: + USB_LOG_ERR("HUB_FEATURE_HUB_C_LOCALPOWER not implmented.\n"); + break; + case HUB_FEATURE_HUB_C_OVERCURRENT: + USB_LOG_ERR("HUB_FEATURE_HUB_C_OVERCURRENT not implmented.\n"); + break; + default: + return -EPIPE; + } + break; + case HUB_REQUEST_GET_DESCRIPTOR: + USB_LOG_ERR("HUB_REQUEST_GET_DESCRIPTOR not implmented.\n"); + break; + case HUB_REQUEST_GET_STATUS: + USB_ASSERT(buf); + memset(buf, 0, 4); + break; + default: + break; + } + } + else if (setup->bmRequestType & USB_REQUEST_RECIPIENT_OTHER) + { + switch (setup->bRequest) + { + case HUB_REQUEST_CLEAR_FEATURE: + if (!port || port > nports) + { + return -EPIPE; + } + + portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port ) ); + switch (setup->wValue) + { + case HUB_PORT_FEATURE_ENABLE: + break; + case HUB_PORT_FEATURE_SUSPEND: + case HUB_PORT_FEATURE_C_SUSPEND: + break; + case HUB_PORT_FEATURE_POWER: + break; + case HUB_PORT_FEATURE_C_CONNECTION: + portsc |= XHCI_PORTSC_CSC; + break; + case HUB_PORT_FEATURE_C_ENABLE: + portsc |= XHCI_PORTSC_PEC; + break; + case HUB_PORT_FEATURE_C_OVER_CURREN: + break; + case HUB_PORT_FEATURE_C_RESET: + break; + default: + return -EPIPE; + } + + uint32_t pclear = portsc & XHCI_PORTSC_RW_MASK; + /* clear port status */ + writel(pclear, xhci->op + XHCI_OP_PORTSC ( port )); + + break; + case HUB_REQUEST_SET_FEATURE: + if (!port || port > nports) + { + return -EPIPE; + } + + switch (setup->wValue) + { + case HUB_PORT_FEATURE_SUSPEND: + break; + case HUB_PORT_FEATURE_POWER: + break; + case HUB_PORT_FEATURE_RESET: + ret = xhci_port_enable(xhci, port); + break; + default: + return -EPIPE; + } + break; + case HUB_REQUEST_GET_STATUS: + if (!port || port > nports) + { + return -EPIPE; + } + + portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port ) ); + status = 0; + + if (portsc & XHCI_PORTSC_CSC) + { + /* Port connection status changed */ + status |= (1 << HUB_PORT_FEATURE_C_CONNECTION); + + /* always clear all the status change bits */ + uint32_t temp = portsc & ( XHCI_PORTSC_PRESERVE | XHCI_PORTSC_CHANGE ); + writel ( temp, xhci->op + XHCI_OP_PORTSC ( port ) ); + } + + if (portsc & XHCI_PORTSC_PEC) + { + /* Port enabled status changed */ + status |= (1 << HUB_PORT_FEATURE_C_ENABLE); + } + + if (portsc & XHCI_PORTSC_OCC) + { + /* Port status changed due to over-current */ + status |= (1 << HUB_PORT_FEATURE_C_OVER_CURREN); + } + + if (portsc & XHCI_PORTSC_CCS) + { + /* Port connected */ + status |= (1 << HUB_PORT_FEATURE_CONNECTION); + } + + if (portsc & XHCI_PORTSC_PED) + { + /* Port enabled */ + status |= (1 << HUB_PORT_FEATURE_ENABLE); + + const unsigned int speed = xhci_root_speed(xhci, port); + USB_LOG_DBG("Port-%d speed = %d \r\n", port, speed); + if (speed == USB_SPEED_LOW) + { + status |= (1 << HUB_PORT_FEATURE_LOWSPEED); + } + else if (speed == USB_SPEED_HIGH) + { + status |= (1 << HUB_PORT_FEATURE_HIGHSPEED); + } + /* else is full-speed */ + } + + if (portsc & XHCI_PORTSC_OCA) + { + /* Over-current condition */ + status |= (1 << HUB_PORT_FEATURE_OVERCURRENT); + } + + if (portsc & XHCI_PORTSC_PR) + { + /* Reset is in progress */ + status |= (1 << HUB_PORT_FEATURE_RESET); + } + + if (portsc & XHCI_PORTSC_PP) + { + /* Port is not power off */ + status |= (1 << HUB_PORT_FEATURE_POWER); + } + memcpy(buf, &status, 4); + break; + default: + break; + } + } + + return 0; +} + + + + +uint8_t usbh_get_port_speed(struct usbh_hub *hub, const uint8_t port) +{ + USB_ASSERT(hub); + struct usbh_bus *usb = hub->usb; + USB_ASSERT(usb && usb->priv); + struct xhci_host *xhci = usb->priv; + + if (hub->is_roothub) { + return xhci_root_speed(xhci, port); + } else { + struct usbh_hubport *roothub_port = usbh_root_hub_port(&(hub->child[port])); + /* TODO, hanlde TT for low-speed device on high-speed hub, but it doesn't matter, since + we haven't well handle hub yet */ + USB_ASSERT(roothub_port); + return xhci_root_speed(xhci, roothub_port->port); + } +} + +int usbh_ep_pipe_reconfigure(struct usbh_bus *usb, usbh_pipe_t pipe, uint8_t dev_addr, uint8_t mtu, uint8_t speed) +{ + struct xhci_endpoint *ppipe = (struct xhci_endpoint *)pipe; + size_t old_mtu = ppipe->mtu; + int rc = 0; + + if (mtu != old_mtu) { + ppipe->mtu = mtu; + rc = xhci_endpoint_mtu(ppipe); + } + + return rc; +} + +int usbh_pipe_alloc(usbh_pipe_t *pipe, const struct usbh_endpoint_cfg *ep_cfg) +{ + int rc = 0; + int slot_id = 0; + struct xhci_host *xhci = xhci_get_inst_of_port(ep_cfg->hport); + struct usbh_hubport *hport = ep_cfg->hport; + struct xhci_endpoint *ppipe = usb_align(XHCI_RING_SIZE, sizeof(struct xhci_endpoint)); + struct xhci_slot *slot; + + if (NULL == ppipe) { + return -ENOMEM; + } + + memset(ppipe, 0, sizeof(struct xhci_endpoint)); + + ppipe->waitsem = usb_osal_sem_create(0); + ppipe->waiter = false; + ppipe->urb = NULL; + ppipe->hport = hport; + + ppipe->address = ep_cfg->ep_addr; + ppipe->mtu = ep_cfg->ep_mps; + ppipe->interval = ep_cfg->ep_interval; + ppipe->ep_type = ep_cfg->ep_type; + ppipe->burst = 0U; + + if (ppipe->address == 0) { /* if try to allocate ctrl ep, open device first */ + USB_LOG_DBG("allocate device for port-%d \r\n", hport->port); + rc = xhci_device_open(xhci, ppipe, &slot_id); + if (rc) { + goto failed; + } + + slot = xhci->slot[slot_id]; + USB_ASSERT(slot); + rc = xhci_ctrl_endpoint_open(xhci, slot, ppipe); + if (rc) { + goto failed; + } + + rc = xhci_device_address(xhci, slot, ppipe); + if (rc) { + goto failed; + } + } else { + slot_id = hport->dev_addr; + slot = xhci->slot[slot_id]; + + rc = xhci_work_endpoint_open(xhci, slot, ppipe); + if (rc) { + goto failed; + } + } + + *pipe = (usbh_pipe_t)ppipe; + return rc; +failed: + usb_free(ppipe); + *pipe = NULL; + return rc; +} + +int usbh_get_xhci_devaddr(usbh_pipe_t *pipe) +{ + struct xhci_endpoint *ppipe = (struct xhci_endpoint *)pipe; + USB_ASSERT(ppipe && (ppipe->slot)); + return ppipe->slot->id; +} + +int usbh_pipe_free(usbh_pipe_t pipe) +{ + int ret = 0; + struct xhci_endpoint *ppipe = (struct xhci_endpoint *)pipe; + + if (!ppipe) { + return -EINVAL; + } + + struct usbh_urb *urb = ppipe->urb; + if (urb) { + usbh_kill_urb(urb); + } + + size_t flags = usb_osal_enter_critical_section(); + xhci_endpoint_close(ppipe); + usb_osal_leave_critical_section(flags); + return 0; +} + +int usbh_submit_urb(struct usbh_urb *urb) +{ + int ret = 0; + if (!urb || !urb->pipe) { + return -EINVAL; + } + + struct xhci_endpoint *ppipe = (struct xhci_endpoint *)urb->pipe; + struct xhci_host *xhci = ppipe->xhci; + struct usb_setup_packet *setup = urb->setup; + size_t flags = usb_osal_enter_critical_section(); + + urb->errorcode = -EBUSY; + urb->actual_length = 0U; + + ppipe->urb = urb; + ppipe->timeout = urb->timeout; + if (ppipe->timeout > 0) { + ppipe->waiter = true; + } else { + ppipe->waiter = false; + } + + usb_osal_leave_critical_section(flags); + switch (ppipe->ep_type) { + case USB_ENDPOINT_TYPE_CONTROL: + USB_ASSERT(setup); + if (setup->bRequest == USB_REQUEST_SET_ADDRESS) { + /* Set address command sent during xhci_alloc_pipe. */ + goto skip_req; + } + + USB_LOG_DBG("%s request-%d.\n", __func__, setup->bRequest); + xhci_endpoint_message(ppipe, setup, urb->transfer_buffer, urb->transfer_buffer_length); + break; + case USB_ENDPOINT_TYPE_INTERRUPT: + case USB_ENDPOINT_TYPE_BULK: + xhci_endpoint_stream(ppipe, urb->transfer_buffer, urb->transfer_buffer_length); + break; + default: + USB_ASSERT(0U); + break; + } + + /* wait all ring handled by xHc */ + int cc = xhci_event_wait(xhci, ppipe, &ppipe->reqs); + if ((cc != XHCI_CMPLT_SUCCESS) && + !((cc == XHCI_CMPLT_TIMEOUT) && (ppipe->ep_type == USB_ENDPOINT_TYPE_INTERRUPT))) + { + /* ignore transfer timeout for interrupt type */ + USB_LOG_ERR("%s: xfer failed (cc %d).\n", __func__, cc); + ret = -1; + urb->errorcode = cc; + goto errout_timeout; + } + +skip_req: +errout_timeout: + /* Timeout will run here */ + usbh_kill_urb(urb); + return ret; +} + +int usbh_kill_urb(struct usbh_urb *urb) +{ + return 0; +} + +void USBH_IRQHandler(void *param) +{ + USB_ASSERT(param); + struct usbh_bus *bus = (struct usbh_bus *)param; + struct xhci_host *xhci = bus->priv; + USB_ASSERT(xhci); + uint32_t usbsts; + uint32_t runtime; + + /* clear interrupt status */ + usbsts = readl ( xhci->op + XHCI_OP_USBSTS ); + usbsts |= XHCI_USBSTS_EINT; + writel(usbsts, xhci->op + XHCI_OP_USBSTS); + + /* ack interrupt */ + runtime = readl(xhci->run + XHCI_RUN_IR_IMAN ( 0 )); + runtime |= XHCI_RUN_IR_IMAN_IP; + writel (runtime, xhci->run + XHCI_RUN_IR_IMAN ( 0 )); + + (void)xhci_event_process(xhci); +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 8dc67c9cc..911782a2f 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -1 +1,2606 @@ +/* + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: xhci.c + * Date: 2022-07-19 09:26:25 + * LastEditTime: 2022-07-19 09:26:25 + * Description:  This file is for xhci functions implmentation. + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhugengyu 2022/9/19 init commit + * 2.0 zhugengyu 2023/3/29 support usb3.0 device attached at roothub + */ + + /************************************************* +File name: xhci.c +Description: the xhci driver functions. +Others: take CherryUSB v0.1.2/port/xhci/xhci.c for references + https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/blob/master/third-party/cherryusb/port/xhci/xhci.c +History: +1. Date: 2024-06-18 +Author: AIIT XUOS Lab +Modification: replant and redefine some xhci data structure, so that the cherryUSB can adapt to XiZi AIOT. +*************************************************/ + +#include "usbh_core.h" +#include "usbh_hub.h" +#include "xhci_reg.h" #include "xhci.h" + + +/* + * Copyright聽: (C)聽2022聽Phytium聽Information聽Technology,聽Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: xhci.c + * Date: 2022-07-19 09:26:25 + * LastEditTime: 2022-07-19 09:26:25 + * Description: 聽This file is for xhci functions implmentation. + * + * Modify聽History: + * Ver聽聽聽Who聽聽聽聽聽聽聽聽Date聽聽聽聽聽聽聽聽聽Changes + * -----聽------聽聽聽聽聽--------聽聽聽聽-------------------------------------- + * 1.0 zhugengyu 2022/9/19 init commit + * 2.0 zhugengyu 2023/3/29 support usb3.0 device attached at roothub + */ + +#include "usbh_core.h" +#include "usbh_hub.h" + +#include "xhci_reg.h" +#include "xhci.h" + + +/** @file + * + * USB eXtensible Host Controller Interface (xHCI) driver + * + */ + +#define XHCI_DUMP 1 + +/** Define a XHCI speed in PSI + * + * @v mantissa Mantissa + * @v exponent Exponent (in engineering terms: 1=k, 2=M, 3=G) + * @ret speed USB speed + */ +#define XCHI_PSI( mantissa, exponent ) ( (exponent << 16) | (mantissa) ) + +/** USB device speeds */ +enum { + /** Not connected */ + XCHI_PSI_NONE = 0, + /** Low speed (1.5Mbps) */ + XCHI_PSI_LOW = XCHI_PSI ( 1500, 1 ), + /** Full speed (12Mbps) */ + XCHI_PSI_FULL = XCHI_PSI ( 12, 2 ), + /** High speed (480Mbps) */ + XCHI_PSI_HIGH = XCHI_PSI ( 480, 2 ), + /** Super speed (5Gbps) */ + XCHI_PSI_SUPER = XCHI_PSI ( 5, 3 ), +}; + + +/** + * Calculate buffer alignment + * + * @v len Length + * @ret align Buffer alignment + * + * Determine alignment required for a buffer which must be aligned to + * at least XHCI_MIN_ALIGN and which must not cross a page boundary. + */ +static inline size_t xhci_align ( size_t len ) { + size_t align; + + /* Align to own length (rounded up to a power of two) */ + align = ( 1 << fls ( len - 1 ) ); + + /* Round up to XHCI_MIN_ALIGN if needed */ + if ( align < XHCI_MIN_ALIGN ) + align = XHCI_MIN_ALIGN; + + return align; +} + + +/** + * Write potentially 64-bit register + * + * @v xhci xHCI device + * @v value Value + * @v reg Register address + * @ret rc Return status code + */ +static inline int xhci_writeq ( struct xhci_host *xhci, uintptr_t value, void *reg ) { + + /* If this is a 32-bit build, then this can never fail + * (allowing the compiler to optimise out the error path). + */ + if ( sizeof ( value ) <= sizeof ( uint32_t ) ) { + writel ( value, reg ); + writel ( 0, ( reg + sizeof ( uint32_t ) ) ); + return 0; + } + + /* If the device does not support 64-bit addresses and this + * address is outside the 32-bit address space, then fail. + */ + if ( ( value & ~0xffffffffULL ) && ! xhci->addr64 ) { + USB_LOG_DBG("XHCI %s cannot access address %lx\n", + xhci->name, value ); + return -ENOTSUP; + } + + /* If this is a 64-bit build, then writeq() is available */ + writeq ( value, reg ); + return 0; +} + +/** + * Initialise device + * + * @v xhci xHCI device + * @v regs MMIO registers + */ +static void xhci_init ( struct xhci_host *xhci, void *regs ) { + uint32_t hcsparams1; + uint32_t hcsparams2; + uint32_t hccparams1; + uint32_t pagesize; + size_t caplength; + size_t rtsoff; + size_t dboff; + + /* Locate capability, operational, runtime, and doorbell registers */ + xhci->cap = regs; + caplength = readb ( xhci->cap + XHCI_CAP_CAPLENGTH ); + rtsoff = readl ( xhci->cap + XHCI_CAP_RTSOFF ); + dboff = readl ( xhci->cap + XHCI_CAP_DBOFF ); + xhci->op = ( xhci->cap + caplength ); + xhci->run = ( xhci->cap + rtsoff ); + xhci->db = ( xhci->cap + dboff ); + + /* avoid access XHCI_REG_CAP_HCIVERSION = 0x2, unaligned memory */ + xhci->version = ((readl ( xhci->cap + XHCI_CAP_CAPLENGTH ) >> 16) & 0xffff); + + USB_LOG_DBG("XHCI %s version %x cap %08lx op %08lx run %08lx db %08lx\n", + xhci->name, xhci->version, ( xhci->cap ), + ( xhci->op ), ( xhci->run ), + ( xhci->db ) ); + + if (xhci->version < 0x96 || xhci->version > 0x120) { + USB_LOG_WRN("XHCI %s not support.\n", xhci->name); + } + + /* Read structural parameters 1 */ + hcsparams1 = readl ( xhci->cap + XHCI_CAP_HCSPARAMS1 ); + xhci->slots = XHCI_HCSPARAMS1_SLOTS ( hcsparams1 ); + xhci->intrs = XHCI_HCSPARAMS1_INTRS ( hcsparams1 ); + xhci->ports = XHCI_HCSPARAMS1_PORTS ( hcsparams1 ); + USB_LOG_DBG("XHCI %s has %d slots %d intrs %d ports\n", + xhci->name, xhci->slots, xhci->intrs, xhci->ports ); + + /* Read structural parameters 2 */ + hcsparams2 = readl ( xhci->cap + XHCI_CAP_HCSPARAMS2 ); + xhci->scratch.count = XHCI_HCSPARAMS2_SCRATCHPADS ( hcsparams2 ); + USB_LOG_DBG("XHCI %s needs %d scratchpads\n", + xhci->name, xhci->scratch.count ); + + /* Read capability parameters 1 */ + hccparams1 = readl ( xhci->cap + XHCI_CAP_HCCPARAMS1 ); + xhci->addr64 = XHCI_HCCPARAMS1_ADDR64 ( hccparams1 ); + xhci->csz_shift = XHCI_HCCPARAMS1_CSZ_SHIFT ( hccparams1 ); + xhci->xecp = (XHCI_HCCPARAMS1_XECP ( hccparams1 )); + USB_LOG_DBG("XHCI %s context %d bit\n", + xhci->name, (xhci->addr64 ? 64 : 32) ); + + /* Read page size */ + pagesize = readl ( xhci->op + XHCI_OP_PAGESIZE ); + xhci->pagesize = XHCI_PAGESIZE ( pagesize ); + USB_ASSERT ( xhci->pagesize != 0 ); + USB_ASSERT ( ( ( xhci->pagesize ) & ( xhci->pagesize - 1 ) ) == 0 ); + USB_LOG_DBG("XHCI %s page size %zd bytes\n", + xhci->name, xhci->pagesize ); +} + +/** + * Find extended capability + * + * @v xhci xHCI device + * @v id Capability ID + * @v offset Offset to previous extended capability instance, or zero + * @ret offset Offset to extended capability, or zero if not found + */ +static unsigned int xhci_extended_capability ( struct xhci_host *xhci, + unsigned int id, + unsigned int offset ) { + uint32_t xecp; + unsigned int next; + + /* Locate the extended capability */ + while ( 1 ) { + + /* Locate first or next capability as applicable */ + if ( offset ) { + xecp = readl ( xhci->cap + offset ); + next = XHCI_XECP_NEXT ( xecp ); + } else { + next = xhci->xecp; + } + if ( ! next ) + return 0; + offset += next; + + /* Check if this is the requested capability */ + xecp = readl ( xhci->cap + offset ); + if ( XHCI_XECP_ID ( xecp ) == id ) + return offset; + } +} + +/** + * Initialise USB legacy support + * + * @v xhci xHCI device + */ +static void xhci_legacy_init ( struct xhci_host *xhci ) { + unsigned int legacy; + uint8_t bios; + + /* Locate USB legacy support capability (if present) */ + legacy = xhci_extended_capability ( xhci, XHCI_XECP_ID_LEGACY, 0 ); + if ( ! legacy ) { + /* Not an error; capability may not be present */ + USB_LOG_DBG("XHCI %s has no USB legacy support capability\n", + xhci->name ); + return; + } + + /* Check if legacy USB support is enabled */ + USB_LOG_DBG("XHCI %s bios offset 0x%x\n", xhci->name, (xhci->cap + legacy + XHCI_USBLEGSUP_BIOS)); + /* bios = readb ( xhci->cap + legacy + XHCI_USBLEGSUP_BIOS ); cannot access offset 0x2, work around */ + bios = readl ( xhci->cap + legacy ); + bios = (bios >> 16) & 0xffff; + if ( ! ( bios & XHCI_USBLEGSUP_BIOS_OWNED ) ) { + /* Not an error; already owned by OS */ + USB_LOG_DBG("XHCI %s USB legacy support already disabled\n", + xhci->name ); + return; + } + + /* Record presence of USB legacy support capability */ + xhci->legacy = legacy; +} + + + +/** + * Claim ownership from BIOS + * + * @v xhci xHCI device + */ +static void xhci_legacy_claim ( struct xhci_host *xhci ) { + uint32_t ctlsts; + uint8_t bios; + unsigned int i; + + /* Do nothing unless legacy support capability is present */ + if ( ! xhci->legacy ) + return; + + /* Claim ownership */ + writeb ( XHCI_USBLEGSUP_OS_OWNED, + xhci->cap + xhci->legacy + XHCI_USBLEGSUP_OS ); + + /* Wait for BIOS to release ownership */ + for ( i = 0 ; i < XHCI_USBLEGSUP_MAX_WAIT_MS ; i++ ) { + + /* Check if BIOS has released ownership */ + bios = readb ( xhci->cap + xhci->legacy + XHCI_USBLEGSUP_BIOS ); + if ( ! ( bios & XHCI_USBLEGSUP_BIOS_OWNED ) ) { + USB_LOG_DBG("XHCI %s claimed ownership from BIOS\n", + xhci->name ); + ctlsts = readl ( xhci->cap + xhci->legacy + + XHCI_USBLEGSUP_CTLSTS ); + if ( ctlsts ) { + USB_LOG_DBG("XHCI %s warning: BIOS retained " + "SMIs: %08x\n", xhci->name, ctlsts ); + } + return; + } + + /* Delay */ + usb_osal_msleep ( 1 ); + } + + /* BIOS did not release ownership. Claim it forcibly by + * disabling all SMIs. + */ + USB_LOG_DBG("XHCI %s could not claim ownership from BIOS: forcibly " + "disabling SMIs\n", xhci->name ); + writel ( 0, xhci->cap + xhci->legacy + XHCI_USBLEGSUP_CTLSTS ); +} + +/** Prevent the release of ownership back to BIOS */ +static int xhci_legacy_prevent_release; + +/** + * Release ownership back to BIOS + * + * @v xhci xHCI device + */ +static void xhci_legacy_release ( struct xhci_host *xhci ) { + + /* Do nothing unless legacy support capability is present */ + if ( ! xhci->legacy ) + return; + + /* Do nothing if releasing ownership is prevented */ + if ( xhci_legacy_prevent_release ) { + USB_LOG_DBG("XHCI %s not releasing ownership to BIOS\n", + xhci->name ); + return; + } + + /* Release ownership */ + writeb ( 0, xhci->cap + xhci->legacy + XHCI_USBLEGSUP_OS ); + USB_LOG_DBG("XHCI %s released ownership to BIOS\n", xhci->name ); +} + +/** + * Stop xHCI device + * + * @v xhci xHCI device + * @ret rc Return status code + */ +static int xhci_stop ( struct xhci_host *xhci ) { + uint32_t usbcmd; + uint32_t usbsts; + unsigned int i; + + /* Clear run/stop bit */ + usbcmd = readl ( xhci->op + XHCI_OP_USBCMD ); + usbcmd &= ~XHCI_USBCMD_RUN; + writel ( usbcmd, xhci->op + XHCI_OP_USBCMD ); + + /* Wait for device to stop */ + for ( i = 0 ; i < XHCI_STOP_MAX_WAIT_MS ; i++ ) { + + /* Check if device is stopped */ + usbsts = readl ( xhci->op + XHCI_OP_USBSTS ); + if ( usbsts & XHCI_USBSTS_HCH ) + return 0; + + /* Delay */ + usb_osal_msleep ( 1 ); + } + + USB_LOG_DBG("XHCI %s timed out waiting for stop\n", xhci->name ); + return -ETIMEDOUT; +} + +/** + * Reset xHCI device + * + * @v xhci xHCI device + * @ret rc Return status code + */ +static int xhci_reset ( struct xhci_host *xhci ) { + uint32_t usbcmd; + unsigned int i; + int rc; + + /* The xHCI specification states that resetting a running + * device may result in undefined behaviour, so try stopping + * it first. + */ + if ( ( rc = xhci_stop ( xhci ) ) != 0 ) { + /* Ignore errors and attempt to reset the device anyway */ + } + + /* Reset device */ + writel ( XHCI_USBCMD_HCRST, xhci->op + XHCI_OP_USBCMD ); + + /* Wait for reset to complete */ + for ( i = 0 ; i < XHCI_RESET_MAX_WAIT_MS ; i++ ) { + + /* Check if reset is complete */ + usbcmd = readl ( xhci->op + XHCI_OP_USBCMD ); + if ( ! ( usbcmd & XHCI_USBCMD_HCRST ) ) + return 0; + + /* Delay */ + usb_osal_msleep ( 1 ); + } + + USB_LOG_DBG("XHCI %s timed out waiting for reset\n", xhci->name ); + return -ETIMEDOUT; +} + + +/** + * Find supported protocol extended capability for a port + * + * @v xhci xHCI device + * @v port Port number + * @ret supported Offset to extended capability, or zero if not found + */ +static unsigned int xhci_supported_protocol ( struct xhci_host *xhci, + unsigned int port ) { + unsigned int supported = 0; + unsigned int offset; + unsigned int count; + uint32_t ports; + + /* Iterate over all supported protocol structures */ + while ( ( supported = xhci_extended_capability ( xhci, + XHCI_XECP_ID_SUPPORTED, + supported ) ) ) { + + /* Determine port range */ + ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS ); + offset = XHCI_SUPPORTED_PORTS_OFFSET ( ports ); + count = XHCI_SUPPORTED_PORTS_COUNT ( ports ); + + /* Check if port lies within this range */ + if ( ( port - offset ) < count ) + return supported; + } + + USB_LOG_DBG("XHCI %s Port-%d has no supported protocol\n", + xhci->name, port ); + return 0; +} + +/** + * Transcribe port speed (for debugging) + * + * @v psi Protocol speed ID + * @ret speed Transcribed speed + */ +static inline const char * xhci_speed_name ( uint32_t psi ) { + static const char *exponents[4] = { "", "k", "M", "G" }; + static char buf[ 10 /* "xxxxxXbps" + NUL */ ]; + unsigned int mantissa; + unsigned int exponent; + + /* Extract mantissa and exponent */ + mantissa = XHCI_SUPPORTED_PSI_MANTISSA ( psi ); + exponent = XHCI_SUPPORTED_PSI_EXPONENT ( psi ); + + /* Transcribe speed */ + snprintf ( buf, sizeof ( buf ), "%d%sbps", + mantissa, exponents[exponent] ); + return buf; +} + +/** + * Find port protocol + * + * @v xhci xHCI device + * @v port Port number + * @ret protocol USB protocol, or zero if not found + */ +static unsigned int xhci_port_protocol ( struct xhci_host *xhci, + unsigned int port ) { + unsigned int supported = xhci_supported_protocol ( xhci, port ); + union { + uint32_t raw; + char text[5]; + } name; + unsigned int protocol; + unsigned int type; + unsigned int psic; + unsigned int psiv; + unsigned int i; + uint32_t revision; + uint32_t ports; + uint32_t slot; + uint32_t psi; + + /* Fail if there is no supported protocol */ + if ( ! supported ) + return 0; + + /* Determine protocol version */ + revision = readl ( xhci->cap + supported + XHCI_SUPPORTED_REVISION ); + protocol = XHCI_SUPPORTED_REVISION_VER ( revision ); + + /* Describe port protocol */ +#if XHCI_DUMP + { + name.raw = CPU_TO_LE32 ( readl ( xhci->cap + supported + + XHCI_SUPPORTED_NAME ) ); + name.text[4] = '\0'; + slot = readl ( xhci->cap + supported + XHCI_SUPPORTED_SLOT ); + type = XHCI_SUPPORTED_SLOT_TYPE ( slot ); + USB_LOG_DBG("XHCI %s-%d %sv%04x type %d \r\n", + xhci->name, port, name.text, protocol, type ); + ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS ); + psic = XHCI_SUPPORTED_PORTS_PSIC ( ports ); + if ( psic ) { + USB_LOG_DBG(" speeds \r\n" ); + for ( i = 0 ; i < psic ; i++ ) { + psi = readl ( xhci->cap + supported + + XHCI_SUPPORTED_PSI ( i ) ); + psiv = XHCI_SUPPORTED_PSI_VALUE ( psi ); + USB_LOG_DBG(" %d:%s \r\n", psiv, xhci_speed_name ( psi ) ); + } + } + } +#endif + + return protocol; +} + +/** + * Probe XCHI device + * + * @v xhci XCHI device + * @v baseaddr XHCI device register base address + * @ret rc Return status code + */ +int xhci_probe ( struct xhci_host *xhci, unsigned long baseaddr ) { + USB_ASSERT(xhci && (xhci->bus)); + int error = 0; + struct usbh_hubport *port; + unsigned int i; + + xhci->base = (void *)baseaddr; + xhci->name[0] = '0' + xhci->bus->id; + xhci->name[1] = '\0'; + + /* Initialise xHCI device */ + xhci_init ( xhci, xhci->base ); + + /* Initialise USB legacy support and claim ownership */ + xhci_legacy_init ( xhci ); + xhci_legacy_claim ( xhci ); + + /* Reset device */ + if ( ( error = xhci_reset ( xhci ) ) != 0 ) + goto err_reset; + + /* Set port protocols */ + for ( i = 1 ; i <= xhci->ports ; i++ ) { + port = usbh_get_roothub_port ( xhci->bus, i ); + port->protocol = xhci_port_protocol ( xhci, i ); + } + + return error; + +err_reset: + xhci_legacy_release ( xhci ); + return -1; +} + +/*********************************************************************/ + +/** + * Allocate device context base address array + * + * @v xhci xHCI device + * @ret rc Return status code + */ +static int xhci_dcbaa_alloc ( struct xhci_host *xhci ) { + size_t len; + uintptr_t dcbaap; + int rc; + + /* Allocate and initialise structure. Must be at least + * 64-byte aligned and must not cross a page boundary, so + * align on its own size (rounded up to a power of two and + * with a minimum of 64 bytes). + */ + len = ( ( xhci->slots + 1 ) * sizeof ( xhci->dcbaa.context[0] ) ); + xhci->dcbaa.context = usb_align(xhci_align ( len ), len); + if ( ! xhci->dcbaa.context ) { + USB_LOG_ERR("XHCI %s could not allocate DCBAA\n", xhci->name ); + rc = -ENOMEM; + goto err_alloc; + } + memset ( xhci->dcbaa.context, 0, len ); + + /* Program DCBAA pointer */ + dcbaap = (uintptr_t)( xhci->dcbaa.context ); + if ( ( rc = xhci_writeq ( xhci, dcbaap, + xhci->op + XHCI_OP_DCBAAP ) ) != 0 ) + goto err_writeq; + + USB_LOG_DBG("XHCI %s DCBAA at [%08lx,%08lx)\n", xhci->name, + ( xhci->dcbaa.context ), + ( ( xhci->dcbaa.context ) + len ) ); + return 0; + + err_writeq: + usb_free ( xhci->dcbaa.context ); + err_alloc: + return rc; +} + + +/** + * Allocate scratchpad buffers + * + * @v xhci xHCI device + * @ret rc Return status code + */ +static int xhci_scratchpad_alloc ( struct xhci_host *xhci ) { + struct xhci_scratchpad *scratch = &xhci->scratch; + size_t buffer_len; + size_t array_len; + uintptr_t addr; + unsigned int i; + int rc; + + /* Do nothing if no scratchpad buffers are used */ + if ( ! scratch->count ) { + USB_LOG_INFO("XHCI %s no need to allocate scratchpad buffers\n", + xhci->name ); + return 0; + } + + /* Allocate scratchpad buffers */ + buffer_len = ( scratch->count * xhci->pagesize ); + scratch->buffer = (uintptr_t)usb_align ( xhci->pagesize, buffer_len ); + if ( ! scratch->buffer ) { + USB_LOG_ERR("XHCI %s could not allocate scratchpad buffers\n", + xhci->name ); + rc = -ENOMEM; + goto err_alloc; + } + memset ( (void *)scratch->buffer, 0, buffer_len ); + + /* Allocate scratchpad array */ + array_len = ( scratch->count * sizeof ( scratch->array[0] ) ); + scratch->array = usb_align(xhci_align ( array_len ), array_len); + if ( ! scratch->array ) { + USB_LOG_ERR("XHCI %s could not allocate scratchpad buffer " + "array\n", xhci->name ); + rc = -ENOMEM; + goto err_alloc_array; + } + + /* Populate scratchpad array */ + addr = ( scratch->buffer + 0 ); + for ( i = 0 ; i < scratch->count ; i++ ) { + scratch->array[i] = CPU_TO_LE64 ( (uintptr_t)addr ); + addr += xhci->pagesize; + } + + /* Set scratchpad array pointer */ + USB_ASSERT ( xhci->dcbaa.context != NULL ); + xhci->dcbaa.context[0] = CPU_TO_LE64 ( ( (uintptr_t)scratch->array ) ); + + USB_LOG_DBG("XHCI %s scratchpad [%08lx,%08lx) array [%08lx,%08lx)\n", + xhci->name, ( scratch->buffer, 0 ), + ( scratch->buffer, buffer_len ), + ( scratch->array ), + ( ( scratch->array ) + array_len ) ); + return 0; + + usb_free ( scratch->array ); + err_alloc_array: + usb_free ( scratch->buffer ); + err_alloc: + return rc; +} + +/** + * Allocate command ring + * + * @v xhci xHCI device + * @ret rc Return status code + */ +static int xhci_command_alloc ( struct xhci_host *xhci ) { + uintptr_t crp; + int rc; + + /* Allocate TRB ring */ + xhci->cmds = usb_align(XHCI_RING_SIZE, sizeof(*xhci->cmds)); /* command ring */ + if (! xhci->cmds) + goto err_ring_alloc; + + memset(xhci->cmds, 0U, sizeof(*xhci->cmds)); + + xhci->cmds->lock = usb_osal_mutex_create(); + USB_ASSERT(xhci->cmds->lock); + + xhci->cmds->cs = 1; /* cycle state = 1 */ + + /* Program command ring control register */ + crp = (uintptr_t)( xhci->cmds ); + if ( ( rc = xhci_writeq ( xhci, ( crp | XHCI_CRCR_RCS ), + xhci->op + XHCI_OP_CRCR ) ) != 0 ) + goto err_writeq; + + USB_LOG_DBG("XHCI %s CRCR at [%08lx,%08lx)\n", xhci->name, + ( xhci->cmds->ring ), + ( ( xhci->cmds->ring ) + sizeof(xhci->cmds->ring) ) ); + return 0; + + err_writeq: + usb_free(xhci->cmds);; + err_ring_alloc: + return rc; +} + +/** + * Allocate event ring + * + * @v xhci xHCI device + * @ret rc Return status code + */ +static int xhci_event_alloc ( struct xhci_host *xhci ) { + unsigned int count; + size_t len; + int rc; + + /* Allocate event ring */ + xhci->evts = usb_align(XHCI_RING_SIZE, sizeof(*xhci->evts)); /* event ring */ + if ( ! xhci->evts ) { + rc = -ENOMEM; + goto err_alloc_trb; + } + + memset(xhci->evts, 0U, sizeof(*xhci->evts)); + + /* Allocate event ring segment table */ + xhci->eseg = usb_align(XHCI_ALIGMENT, sizeof(*xhci->eseg)); /* event segment */ + if ( ! xhci->eseg ) { + rc = -ENOMEM; + goto err_alloc_segment; + } + memset(xhci->eseg, 0U, sizeof(*xhci->eseg)); + xhci->eseg->base = CPU_TO_LE64 ( ( (uintptr_t)xhci->evts ) ); + xhci->eseg->count = XHCI_RING_ITEMS; /* items of event ring TRB */ + + /* Program event ring registers */ + writel ( 1, xhci->run + XHCI_RUN_ERSTSZ ( 0 ) ); /* bit[15:0] event ring segment table size */ + if ( ( rc = xhci_writeq ( xhci, (uintptr_t)( xhci->evts ), + xhci->run + XHCI_RUN_ERDP ( 0 ) ) ) != 0 ) /* bit[63:4] event ring dequeue pointer */ + goto err_writeq_erdp; + if ( ( rc = xhci_writeq ( xhci, (uintptr_t)( xhci->eseg ), + xhci->run + XHCI_RUN_ERSTBA ( 0 ) ) ) != 0 ) /* bit[63:6] event ring segment table base addr */ + goto err_writeq_erstba; + + xhci->evts->cs = 1; /* cycle state = 1 */ + USB_LOG_DBG("XHCI %s event ring [%08lx,%08lx) table [%08lx,%08lx)\n", + xhci->name, ( xhci->evts->ring ), + ( ( xhci->evts->ring ) + sizeof(xhci->evts->ring) ), + ( xhci->eseg ), + ( ( xhci->eseg ) + + sizeof ( xhci->eseg[0] ) ) ); + return 0; + + xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERSTBA ( 0 ) ); + err_writeq_erstba: + xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERDP ( 0 ) ); + err_writeq_erdp: + usb_free ( xhci->eseg ); + err_alloc_segment: + usb_free ( xhci->evts ); + err_alloc_trb: + return rc; +} + +/** + * Start xHCI device + * + * @v xhci xHCI device + */ +static void xhci_run ( struct xhci_host *xhci ) { + uint32_t config; + uint32_t usbcmd; + uint32_t runtime; + + /* Configure number of device slots */ + config = readl ( xhci->op + XHCI_OP_CONFIG ); + config &= ~XHCI_CONFIG_MAX_SLOTS_EN_MASK; + config |= XHCI_CONFIG_MAX_SLOTS_EN ( xhci->slots ); + writel ( config, xhci->op + XHCI_OP_CONFIG ); + + /* Enable port interrupt */ + writel ( 500U, xhci->run + XHCI_RUN_IR_IMOD ( 0 ) ); + runtime = readl(xhci->run + XHCI_RUN_IR_IMAN ( 0 )); + runtime |= XHCI_RUN_IR_IMAN_IE; + writel (runtime, xhci->run + XHCI_RUN_IR_IMAN ( 0 )); + + /* Set run/stop bit and enable interrupt */ + usbcmd = readl ( xhci->op + XHCI_OP_USBCMD ); + usbcmd |= XHCI_USBCMD_RUN | XHCI_USBCMD_INTE; + writel ( usbcmd, xhci->op + XHCI_OP_USBCMD ); + + USB_LOG_DBG("XHCI %s start running\n", xhci->name ); +} + +/** + * Free event ring + * + * @v xhci xHCI device + */ +static void xhci_event_free ( struct xhci_host *xhci ) { + + /* Clear event ring registers */ + writel ( 0, xhci->run + XHCI_RUN_ERSTSZ ( 0 ) ); + xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERSTBA ( 0 ) ); + xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERDP ( 0 ) ); + + /* Free event ring segment table */ + usb_free ( xhci->eseg ); + + /* Free event ring */ + usb_free ( xhci->evts ); +} + +/** + * Free command ring + * + * @v xhci xHCI device + */ +static void xhci_command_free ( struct xhci_host *xhci ) { + + /* Sanity check */ + USB_ASSERT ( ( readl ( xhci->op + XHCI_OP_CRCR ) & XHCI_CRCR_CRR ) == 0 ); + + /* Clear command ring control register */ + xhci_writeq ( xhci, 0, xhci->op + XHCI_OP_CRCR ); + + /* Free TRB ring */ + usb_free ( xhci->cmds ); +} + +/** + * Free scratchpad buffers + * + * @v xhci xHCI device + */ +static void xhci_scratchpad_free ( struct xhci_host *xhci ) { + struct xhci_scratchpad *scratch = &xhci->scratch; + size_t array_len; + size_t buffer_len; + + /* Do nothing if no scratchpad buffers are used */ + if ( ! scratch->count ) + return; + + /* Clear scratchpad array pointer */ + USB_ASSERT ( xhci->dcbaa.context != NULL ); + xhci->dcbaa.context[0] = 0; + + /* Free scratchpad array */ + array_len = ( scratch->count * sizeof ( scratch->array[0] ) ); + usb_free ( scratch->array ); + + /* Free scratchpad buffers */ + buffer_len = ( scratch->count * xhci->pagesize ); + usb_free ( scratch->buffer ); +} + +/** + * Free device context base address array + * + * @v xhci xHCI device + */ +static void xhci_dcbaa_free ( struct xhci_host *xhci ) { + size_t len; + unsigned int i; + + /* Sanity check */ + for ( i = 0 ; i <= xhci->slots ; i++ ) + USB_ASSERT ( xhci->dcbaa.context[i] == 0 ); + + /* Clear DCBAA pointer */ + xhci_writeq ( xhci, 0, xhci->op + XHCI_OP_DCBAAP ); + + /* Free DCBAA */ + len = ( ( xhci->slots + 1 ) * sizeof ( xhci->dcbaa.context[0] ) ); + usb_free ( xhci->dcbaa.context ); +} + +/** + * Open XHCI device + * + * @v xhci XHCI device + * @ret rc Return status code + */ +int xhci_open ( struct xhci_host *xhci ) { + int rc; + + /* Allocate device slot array */ + xhci->slot = usb_malloc ( ( xhci->slots + 1 ) * sizeof ( xhci->slot[0] ) ); + if ( ! xhci->slot ) { + rc = -ENOMEM; + goto err_slot_alloc; + } + + /* Allocate device context base address array */ + if ( ( rc = xhci_dcbaa_alloc ( xhci ) ) != 0 ) + goto err_dcbaa_alloc; + + /* Allocate scratchpad buffers */ + if ( ( rc = xhci_scratchpad_alloc ( xhci ) ) != 0 ) + goto err_scratchpad_alloc; + + /* Allocate command ring */ + if ( ( rc = xhci_command_alloc ( xhci ) ) != 0 ) + goto err_command_alloc; + + /* Allocate event ring */ + if ( ( rc = xhci_event_alloc ( xhci ) ) != 0 ) + goto err_event_alloc; + + /* Start controller */ + xhci_run ( xhci ); + + return 0; + + xhci_stop ( xhci ); + xhci_event_free ( xhci ); + err_event_alloc: + xhci_command_free ( xhci ); + err_command_alloc: + xhci_scratchpad_free ( xhci ); + err_scratchpad_alloc: + xhci_dcbaa_free ( xhci ); + err_dcbaa_alloc: + usb_free ( xhci->slot ); + err_slot_alloc: + return rc; + +} + +/** + * Close XHCI device + * + * @v xhci XHCI Device + */ +void xhci_close ( struct xhci_host *xhci ) { + unsigned int i; + + /* Sanity checks */ + USB_ASSERT ( xhci->slot != NULL ); + for ( i = 0 ; i <= xhci->slots ; i++ ) + USB_ASSERT ( xhci->slot[i] == NULL ); + + xhci_stop ( xhci ); + usb_free (xhci->evts); + usb_free (xhci->eseg); + usb_free (xhci->cmds); + xhci_scratchpad_free ( xhci ); + xhci_dcbaa_free ( xhci ); + usb_free ( xhci->slot ); +} + +/** + * Remove XHCI device + * + * @v xhci XHCI device + */ +void xhci_remove ( struct xhci_host *xhci ) { + xhci_reset ( xhci ); + xhci_legacy_release ( xhci ); + usb_free ( xhci ); + + /* If we are shutting down to boot an OS, then prevent the + * release of ownership back to BIOS. + */ + xhci_legacy_prevent_release = 0; +} + +/*********************************************************************/ + +/** + * Enable port + * + * @v xhci XHCI device + * @v port Port number + * @ret rc Return status code + */ +int xhci_port_enable(struct xhci_host *xhci, uint32_t port) { + uint32_t portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port ) ); + + /* double check if connected */ + if (!(portsc & XHCI_PORTSC_CCS)) { + USB_LOG_ERR("device connectiong lost !!! \r\n"); + return -ENOENT; + } + + switch ( portsc & XHCI_PORTSC_PLS_MASK ) + { + case XHCI_PORTSC_PLS_U0: + /* A USB3 port - controller automatically performs reset */ + break; + case XHCI_PORTSC_PLS_POLLING: + /* A USB2 port - perform device reset */ + xhci_dump_port_status(port, portsc); + writel ((portsc | XHCI_PORTSC_PR), (xhci->op + XHCI_OP_PORTSC ( port ))); /* reset port */ + break; + default: + USB_LOG_ERR("PLS: %d \r\n", (portsc & XHCI_PORTSC_PLS_MASK)); + return -ENOENT; + } + + /* Wait for device to complete reset and be enabled */ + uint32_t end = 1000U, start = 0U; + for (;;) { + portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port ) ); + if (!(portsc & XHCI_PORTSC_CCS)) { + /* USB 2.0 port would be disconnected after reset */ + USB_LOG_INFO("USB 2.0 port disconnected during reset, need rescan \r\n"); + return 0; + } + + if (portsc & XHCI_PORTSC_PED) { /* check if port enabled */ + /* Reset complete */ + break; + } + + if (++start > end) { + USB_LOG_ERR("Wait timeout, portsc=0x%x !!!\n", portsc); + return -ENXIO; + } + + usb_osal_msleep(1); + } + + xhci_dump_port_status(port, portsc); + return 0; +} + +/** + * Convert USB Speed to PSI + * + * @v speed USB speed + * @ret psi USB speed in PSI + */ +static unsigned int xhci_speed_to_psi(int speed) { + unsigned int psi = USB_SPEED_UNKNOWN; + + switch (speed) { + case USB_SPEED_LOW: + psi = XCHI_PSI_LOW; + break; + case USB_SPEED_FULL: + psi = XCHI_PSI_FULL; + break; + case USB_SPEED_HIGH: + psi = XCHI_PSI_HIGH; + break; + case USB_SPEED_SUPER: + psi = XCHI_PSI_SUPER; + break; + } + + return psi; +} + +/** + * Convert USB PSI to Speed + * + * @v psi USB speed in PSI + * @ret speed USB speed + */ +static int xhci_psi_to_speed(int psi) { + int speed = USB_SPEED_UNKNOWN; + + switch (psi) { + case XCHI_PSI_LOW: + speed = USB_SPEED_LOW; + break; + case XCHI_PSI_FULL: + speed = USB_SPEED_FULL; + break; + case XCHI_PSI_HIGH: + speed = USB_SPEED_HIGH; + break; + case XCHI_PSI_SUPER: + speed = USB_SPEED_SUPER; + break; + } + + return speed; +} + +/** + * Find port speed + * + * @v xhci xHCI device + * @v port Port number + * @v psiv Protocol speed ID value + * @ret speed Port speed, or negative error + */ +static int xhci_port_speed ( struct xhci_host *xhci, unsigned int port, + unsigned int psiv ) { + unsigned int supported = xhci_supported_protocol ( xhci, port ); + unsigned int psic; + unsigned int mantissa; + unsigned int exponent; + unsigned int speed; + unsigned int i; + uint32_t ports; + uint32_t psi; + + /* Fail if there is no supported protocol */ + if ( ! supported ) + return -ENOTSUP; + + /* Get protocol speed ID count */ + ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS ); + psic = XHCI_SUPPORTED_PORTS_PSIC ( ports ); + + /* Use protocol speed ID table unless device is known to be faulty */ + /* Iterate over PSI dwords looking for a match */ + for ( i = 0 ; i < psic ; i++ ) { + psi = readl ( xhci->cap + supported + + XHCI_SUPPORTED_PSI ( i ) ); + if ( psiv == XHCI_SUPPORTED_PSI_VALUE ( psi ) ) { + mantissa = XHCI_SUPPORTED_PSI_MANTISSA ( psi ); + exponent = XHCI_SUPPORTED_PSI_EXPONENT ( psi ); + return xhci_psi_to_speed(XCHI_PSI ( mantissa, exponent )); + } + } + + /* Record device as faulty if no match is found */ + if ( psic != 0 ) { + USB_LOG_ERR("XHCI %s-%d spurious PSI value %d: " + "assuming PSI table is invalid\n", + xhci->name, port, psiv ); + } + + /* Use the default mappings */ + switch ( psiv ) { + case XHCI_SPEED_LOW : return USB_SPEED_LOW; + case XHCI_SPEED_FULL : return USB_SPEED_FULL; + case XHCI_SPEED_HIGH : return USB_SPEED_HIGH; + case XHCI_SPEED_SUPER : return USB_SPEED_SUPER; + default: + USB_LOG_ERR("XHCI %s-%d unrecognised PSI value %d\n", + xhci->name, port, psiv ); + return -ENOTSUP; + } +} + +/** + * Find protocol speed ID value + * + * @v xhci xHCI device + * @v port Port number + * @v speed USB speed + * @ret psiv Protocol speed ID value, or negative error + */ +static int xhci_port_psiv ( struct xhci_host *xhci, unsigned int port, + unsigned int speed ) { + unsigned int supported = xhci_supported_protocol ( xhci, port ); + unsigned int psic; + unsigned int mantissa; + unsigned int exponent; + unsigned int psiv; + unsigned int i; + uint32_t ports; + uint32_t psi; + + /* Fail if there is no supported protocol */ + if ( ! supported ) + return -ENOTSUP; + + /* Get protocol speed ID count */ + ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS ); + psic = XHCI_SUPPORTED_PORTS_PSIC ( ports ); + + /* Use the default mappings if applicable */ + if ( psic == 0 ) { + switch ( speed ) { + case USB_SPEED_LOW : return XHCI_SPEED_LOW; + case USB_SPEED_FULL : return XHCI_SPEED_FULL; + case USB_SPEED_HIGH : return XHCI_SPEED_HIGH; + case USB_SPEED_SUPER : return XHCI_SPEED_SUPER; + default: + USB_LOG_DBG("XHCI %s-%d non-standard speed %d\n", + xhci->name, port, speed ); + return -ENOTSUP; + } + } + + /* Iterate over PSI dwords looking for a match */ + for ( i = 0 ; i < psic ; i++ ) { + psi = readl ( xhci->cap + supported + XHCI_SUPPORTED_PSI ( i )); + mantissa = XHCI_SUPPORTED_PSI_MANTISSA ( psi ); + exponent = XHCI_SUPPORTED_PSI_EXPONENT ( psi ); + if ( xhci_speed_to_psi(speed) == XCHI_PSI ( mantissa, exponent ) ) { + psiv = XHCI_SUPPORTED_PSI_VALUE ( psi ); + return psiv; + } + } + + USB_LOG_DBG("XHCI %s-%d unrepresentable speed %#x\n", + xhci->name, port, speed ); + return -ENOENT; +} + +/** + * Update root hub port speed + * + * @v xhci XHCI device + * @v port Port number + * @ret rc Return status code (speed) + */ +uint32_t xhci_root_speed ( struct xhci_host *xhci, uint8_t port ) { + uint32_t portsc; + unsigned int psiv; + int ccs; + int ped; + int csc; + int speed; + unsigned int protocol = xhci_port_protocol(xhci, port); + + /* Read port status */ + portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port ) ); + USB_LOG_DBG("XHCI %s-%d status is 0x%08x, protocol 0x%x\n", + xhci->name, port, portsc, protocol ); + ccs = ( portsc & XHCI_PORTSC_CCS ); + ped = ( portsc & XHCI_PORTSC_PED ); + csc = ( portsc & XHCI_PORTSC_CSC ); + psiv = XHCI_PORTSC_PSIV ( portsc ); + + USB_LOG_DBG("XHCI %s port-%d ccs: %d, ped: %d, csc: %d, psiv: 0x%x\n", + xhci->name, port, !!ccs, !!ped, !!csc, psiv); + + /* Port speed is not valid unless port is connected */ + if ( ! ccs ) { + speed = USB_SPEED_UNKNOWN; + USB_LOG_ERR("XHCI %s port-%d speed unkown\n", xhci->name, port); + return speed; + } + + /* For USB2 ports, the PSIV field is not valid until the port + * completes reset and becomes enabled. + */ + if ( ( protocol < USB_3_0 ) && ! ped ) { + speed = USB_SPEED_FULL; + return speed; + } + + /* Get port speed and map to generic USB speed */ + speed = xhci_port_speed ( xhci, port, psiv ); + if ( speed < 0 ) { + return speed; + } + + return speed; +} + +/*********************************************************************/ +/** + * Add a TRB to the given ring + * + * @v ring XHCI TRB ring + * @v trb TRB content to be added + */ +static inline void xhci_trb_fill(struct xhci_ring *ring, union xhci_trb *trb) { + union xhci_trb *dst = &ring->ring[ring->nidx]; + memcpy((void *)dst, (void *)trb, sizeof(*trb)); + dst->template.control |= (ring->cs ? XHCI_TRB_C : 0); + xhci_dump_trbs(dst, 1); +} + +/** + * Queue a TRB onto a ring, wrapping ring as needed + * + * @v ring XHCI TRB ring + * @v trb TRB content to be added + */ +static void xhci_trb_queue(struct xhci_ring *ring, union xhci_trb *trb) { + + if (ring->nidx >= XHCI_RING_ITEMS - 1) { + /* if it is the last trb in the list, put a link trb in the end */ + union xhci_trb link_trb; + link_trb.link.type = XHCI_TRB_LINK; + link_trb.link.flags = XHCI_TRB_TC; + link_trb.link.next = CPU_TO_LE64(((uintptr_t)ring->ring)); + + xhci_trb_fill(ring, &link_trb); + + ring->nidx = 0; /* adjust dequeue index to 0 */ + ring->cs ^= 1; /* toggle cycle interpretation of sw */ + } + + xhci_trb_fill(ring, trb); + ring->nidx++; /* ahead dequeue index */ +} + +/** + * Wait for a ring to empty (all TRBs processed by hardware) + * + * @v xhci XHCI Device + * @v ep Owner Endpoint of current TRB ring + * @ ring XHCI TRB ring + */ +int xhci_event_wait(struct xhci_host *xhci, + struct xhci_endpoint *ep, + struct xhci_ring *ring) { + int cc = XHCI_CMPLT_SUCCESS; + + if (ep->timeout > 0) + { + if (usb_osal_sem_take(ep->waitsem, ep->timeout) < 0) + { + cc = XHCI_CMPLT_TIMEOUT; + } + else + { + cc = ring->evt.complete.code; /* bit[31:24] completion code */ + } + } + + return cc; +} + +/** + * Ring doorbell register + * + * @v xhci XHCI device + * @v slotid Slot id to ring + * @v value Value send to doorbell + */ +static inline void xhci_doorbell ( struct xhci_host *xhci, uint32_t slotid, uint32_t value ) { + + DSB(); + writel ( value, xhci->db + slotid * XHCI_REG_DB_SIZE ); /* bit[7:0] db target, is ep_id */ +} + +/** + * Abort command + * + * @v xhci xHCI device + */ +static void xhci_abort ( struct xhci_host *xhci ) { + uintptr_t crp; + + /* Abort the command */ + USB_LOG_WRN("XHCI %s aborting command\n", xhci->name ); + xhci_writeq ( xhci, XHCI_CRCR_CA, xhci->op + XHCI_OP_CRCR ); + + /* Allow time for command to abort */ + usb_osal_msleep ( XHCI_COMMAND_ABORT_DELAY_MS ); + + /* Sanity check */ + USB_ASSERT ( ( readl ( xhci->op + XHCI_OP_CRCR ) & XHCI_CRCR_CRR ) == 0 ); + + /* Consume (and ignore) any final command status */ + int cc = xhci_event_wait(xhci, xhci->cur_cmd_pipe, xhci->cmds); + if (XHCI_CMPLT_SUCCESS != cc) { + USB_LOG_ERR("XHCI %s abort command failed, cc %d\n", xhci->name, cc); + } + + /* Reset the command ring control register */ + memset(xhci->cmds->ring, 0U, XHCI_RING_ITEMS * sizeof(union xhci_trb)); + xhci_writeq ( xhci, ( (uint64_t)(uintptr_t)xhci->cmds | xhci->cmds->cs ), xhci->op + XHCI_OP_CRCR ); +} + +/** + * Submit a command to the xhci controller ring + * + * @v xhci XHCI Device + * @v ep Owner Endpoint of current TRB ring + * @ trb Command TRB to be sent + */ +static int xhci_cmd_submit(struct xhci_host *xhci, struct xhci_endpoint *ep, union xhci_trb *trb) { + + int rc = 0; + usb_osal_mutex_take(xhci->cmds->lock); /* handle command one by one */ + + ep->timeout = 5000; + ep->waiter = true; + xhci->cur_cmd_pipe = ep; + + xhci_trb_queue(xhci->cmds, trb); + + /* pass command trb to hardware */ + DSB(); + + xhci_doorbell(xhci, 0, 0); /* 0 = db host controller, 0 = db targe hc command */ + int cc = xhci_event_wait(xhci, ep, xhci->cmds); + if (XHCI_CMPLT_SUCCESS != cc) { + USB_LOG_ERR("XHCI %s cmd failed, cc %d\n", xhci->name, cc); + xhci_abort(xhci); /* Abort command */ + rc = -ENOTSUP; + } + + usb_osal_mutex_give(xhci->cmds->lock); + xhci->cur_cmd_pipe = NULL; + return rc; +} + +/** + * Issue NOP and wait for completion + * + * @v xhci xHCI device + * @v ep Command Endpoint + * @ret rc Return status code + */ +static int xhci_nop ( struct xhci_host *xhci, struct xhci_endpoint *ep ) { + union xhci_trb trb; + struct xhci_trb_common *nop = &trb.common; + int rc; + + /* Construct command */ + memset ( nop, 0, sizeof ( *nop ) ); + nop->flags = XHCI_TRB_IOC; + nop->type = XHCI_TRB_NOP_CMD; + + /* Issue command and wait for completion */ + if ( ( rc = xhci_cmd_submit(xhci, ep, &trb ) ) != 0 ) + return rc; + + return 0; +} + +/** + * Issue Enable slot and wait for completion + * + * @v xhci xHCI device + * @v ep Command Endpoint + * @v type Type of Slot to be enabled + * @ret rc Return status code + */ +static int xhci_enable_slot(struct xhci_host *xhci, struct xhci_endpoint *ep, unsigned int type) { + union xhci_trb trb; + struct xhci_trb_enable_slot *enable = &trb.enable; + struct xhci_trb_complete *enabled; + unsigned int slot; + int rc; + + /* Construct command */ + memset ( enable, 0, sizeof ( *enable ) ); + enable->slot = type; + enable->type = XHCI_TRB_ENABLE_SLOT; + + /* Issue command and Wait for completion */ + if ( ( rc = xhci_cmd_submit(xhci, ep, &trb) ) != 0 ) { + USB_LOG_ERR("XHCI %s could not enable new slot, type %d\n", + xhci->name, type ); + return rc; + } + + /* Extract slot number */ + enabled = &(xhci->cmds->evt.complete); + slot = enabled->slot; + + USB_LOG_DBG("XHCI %s slot %d enabled\n", xhci->name, slot ); + return slot; +} + +/** + * Disable slot + * + * @v xhci xHCI device + * @v ep Command Endpoint + * @v slot Device slot + * @ret rc Return status code + */ +static int xhci_disable_slot ( struct xhci_host *xhci, struct xhci_endpoint *ep, + unsigned int slot ) { + union xhci_trb trb; + struct xhci_trb_disable_slot *disable = &trb.disable; + int rc; + + /* Construct command */ + memset ( disable, 0, sizeof ( *disable ) ); + disable->type = XHCI_TRB_DISABLE_SLOT; + disable->slot = slot; + + /* Issue command and wait for completion */ + if ( ( rc = xhci_cmd_submit ( xhci, ep, &trb ) ) != 0 ) { + USB_LOG_DBG("XHCI %s could not disable slot %d: %s\n", + xhci->name, slot, strerror ( rc ) ); + return rc; + } + + USB_LOG_DBG("XHCI %s slot %d disabled\n", xhci->name, slot ); + return 0; +} + +/** + * Issue context-based command and wait for completion + * + * @v xhci xHCI device + * @v slot Device slot + * @v endpoint Endpoint + * @v type TRB type + * @v populate Input context populater + * @ret rc Return status code + */ +static int xhci_context ( struct xhci_host *xhci, struct xhci_slot *slot, + struct xhci_endpoint *ep, unsigned int type, + void ( * populate ) ( struct xhci_host *xhci, + struct xhci_slot *slot, + struct xhci_endpoint *ep, + void *input ) ) { + union xhci_trb trb; + struct xhci_trb_context *context = &trb.context; + size_t len; + void *input; + int rc; + + /* Allocate an input context */ + len = xhci_input_context_offset ( xhci, XHCI_CTX_END ); + input = usb_align(xhci_align ( len ), len); + if ( ! input ) { + rc = -ENOMEM; + goto err_alloc; + } + memset ( input, 0, len ); + + /* Populate input context */ + populate ( xhci, slot, ep, input ); + + /* Construct command */ + memset ( context, 0, sizeof ( *context ) ); + context->type = type; + context->input = CPU_TO_LE64 ( ( (uintptr_t)input ) ); + context->slot = slot->id; + + /* Issue command and wait for completion */ + if ( ( rc = xhci_cmd_submit ( xhci, ep, &trb ) ) != 0 ) { + xhci_dump_input_ctx(xhci, ep, input); + goto err_command; + } + + err_command: + usb_free ( input ); + err_alloc: + return rc; +} + +/** + * Populate address device input context + * + * @v xhci xHCI device + * @v slot Device slot + * @v endpoint Endpoint + * @v input Input context + */ +static void xhci_address_device_input ( struct xhci_host *xhci, + struct xhci_slot *slot, + struct xhci_endpoint *endpoint, + void *input ) { + struct xhci_control_context *control_ctx; + struct xhci_slot_context *slot_ctx; + struct xhci_endpoint_context *ep_ctx; + + /* Sanity checks */ + USB_ASSERT ( endpoint->ctx == XHCI_CTX_EP0 ); + + /* Populate control context, add slot context and ep context */ + control_ctx = input; + control_ctx->add = CPU_TO_LE32 ( ( 1 << XHCI_CTX_SLOT ) | + ( 1 << XHCI_CTX_EP0 ) ); + + /* Populate slot context */ + slot_ctx = ( input + xhci_input_context_offset ( xhci, XHCI_CTX_SLOT )); + slot_ctx->info = CPU_TO_LE32 ( XHCI_SLOT_INFO ( 1, 0, slot->psiv, + slot->route ) ); + slot_ctx->port = slot->port; + slot_ctx->tt_id = slot->tt_id; + slot_ctx->tt_port = slot->tt_port; + + /* Populate control endpoint context */ + ep_ctx = ( input + xhci_input_context_offset ( xhci, XHCI_CTX_EP0 ) ); + ep_ctx->type = XHCI_EP_TYPE_CONTROL; /* bit[5:3] endpoint type */ + ep_ctx->burst = endpoint->burst; /* bit[16:8] max burst size */ + ep_ctx->mtu = CPU_TO_LE16 ( endpoint->mtu ); /* bit[31:16] max packet size */ + + /* + bit[63:4] tr dequeue pointer + bit[0] dequeue cycle state + */ + ep_ctx->dequeue = CPU_TO_LE64 ( (uint64_t)( (uintptr_t)&endpoint->reqs.ring[0] ) | XHCI_EP_DCS ); + ep_ctx->trb_len = CPU_TO_LE16 ( XHCI_EP0_TRB_LEN ); /* bit[15:0] average trb length */ +} + +/** + * Address device + * + * @v xhci xHCI device + * @v endpoint Endpoint + * @v slot Device slot + * @ret rc Return status code + */ +static inline int xhci_address_device ( struct xhci_host *xhci, + struct xhci_endpoint *ep, + struct xhci_slot *slot ) { + struct xhci_slot_context *slot_ctx; + int rc; + + /* Assign device address */ + if ( ( rc = xhci_context ( xhci, slot, slot->endpoint[XHCI_CTX_EP0], + XHCI_TRB_ADDRESS_DEVICE, + xhci_address_device_input ) ) != 0 ) + + USB_LOG_DBG("XHCI %s slot ctx 0x%x\n", xhci->name, slot->context); + + /* Get assigned address for check */ + slot_ctx = ( slot->context + + xhci_device_context_offset ( xhci, XHCI_CTX_SLOT ) ); + USB_LOG_DBG("XHCI %s slot ctx 0x%x assigned address 0x%x\n", + xhci->name, slot_ctx, slot_ctx->address ); + + return rc; +} + +/** + * Reset endpoint + * + * @v xhci xHCI device + * @v slot Device slot + * @v endpoint Endpoint + * @ret rc Return status code + */ +int xhci_reset_endpoint ( struct xhci_host *xhci, + struct xhci_slot *slot, + struct xhci_endpoint *endpoint ) { + union xhci_trb trb; + struct xhci_trb_reset_endpoint *reset = &trb.reset; + int rc; + + /* Construct command */ + memset ( reset, 0, sizeof ( *reset ) ); + reset->slot = slot->id; + reset->endpoint = endpoint->ctx; + reset->type = XHCI_TRB_RESET_ENDPOINT; + + /* Issue command and wait for completion */ + if ( ( rc = xhci_cmd_submit ( xhci, endpoint, &trb ) ) != 0 ) { + USB_LOG_DBG("XHCI %s slot %d ctx %d could not reset endpoint " + "in state %d: %s\n", xhci->name, slot->id, endpoint->ctx, + endpoint->context->state, strerror ( rc ) ); + return rc; + } + + return 0; +} + +/** + * Stop endpoint + * + * @v xhci xHCI device + * @v slot Device slot + * @v endpoint Endpoint + * @ret rc Return status code + */ +static inline int xhci_stop_endpoint ( struct xhci_host *xhci, + struct xhci_slot *slot, + struct xhci_endpoint *endpoint ) { + union xhci_trb trb; + struct xhci_trb_stop_endpoint *stop = &trb.stop; + int rc; + + /* Construct command */ + memset ( stop, 0, sizeof ( *stop ) ); + stop->slot = slot->id; + stop->endpoint = endpoint->ctx; + stop->type = XHCI_TRB_STOP_ENDPOINT; + + /* Issue command and wait for completion */ + if ( ( rc = xhci_cmd_submit ( xhci, endpoint, &trb ) ) != 0 ) { + USB_LOG_DBG("XHCI %s slot %d ctx %d could not stop endpoint " + "in state %d: %s\n", xhci->name, slot->id, endpoint->ctx, + endpoint->context->state, strerror ( rc ) ); + return rc; + } + + return 0; +} + +/*********************************************************************/ + +/** + * Find port slot type + * + * @v xhci xHCI device + * @v port Port number + * @ret type Slot type, or negative error + */ +static int xhci_port_slot_type ( struct xhci_host *xhci, unsigned int port ) { + unsigned int supported = xhci_supported_protocol ( xhci, port ); + unsigned int type; + uint32_t slot; + + /* Fail if there is no supported protocol */ + if ( ! supported ) + return -ENOTSUP; + + /* Get slot type */ + slot = readl ( xhci->cap + supported + XHCI_SUPPORTED_SLOT ); + type = XHCI_SUPPORTED_SLOT_TYPE ( slot ); + + return type; +} + +/** + * Open device + * + * @v xhci XHCI device + * @v ep Endpoint + * @ret slot_id Return device slot id + * @ret rc Return status code + */ +int xhci_device_open ( struct xhci_host *xhci, struct xhci_endpoint *ep, int *slot_id ) { + struct usbh_hubport *hport = ep->hport; + struct usbh_hubport *tt = usbh_transaction_translator(hport); + struct xhci_slot *slot; + struct xhci_slot *tt_slot; + int type; + int rc; + int id; + size_t len; + + /* Determine applicable slot type */ + type = xhci_port_slot_type ( xhci, hport->port ); + if ( type < 0 ) { + rc = type; + USB_LOG_ERR("XHCI %s-%d has no slot type\n", + xhci->name, hport->port ); + goto err_type; + } + + /* Allocate a device slot number */ + id = xhci_enable_slot ( xhci, ep, type ); + if ( id < 0 ) { + rc = id; + goto err_enable_slot; + } + + USB_ASSERT ( ( id > 0 ) && ( ( unsigned int ) id <= xhci->slots ) ); + USB_ASSERT ( xhci->slot[id] == NULL ); + + /* Allocate and initialise structure */ + slot = usb_malloc ( sizeof ( *slot ) ); + if ( ! slot ) { + rc = -ENOMEM; + goto err_alloc; + } + slot->id = id; + xhci->slot[id] = slot; + slot->xhci = xhci; + if ( tt ) { + tt_slot = xhci->slot[tt->dev_addr]; + slot->tt_id = tt_slot->id; + slot->tt_port = tt->port; + } + + /* Allocate a device context */ + len = xhci_device_context_offset ( xhci, XHCI_CTX_END ); + slot->context = usb_align(xhci_align ( len ), len); + if ( ! slot->context ) { + rc = -ENOMEM; + goto err_alloc_context; + } + memset ( slot->context, 0, len ); + + /* Set device context base address */ + USB_ASSERT ( xhci->dcbaa.context[id] == 0 ); + xhci->dcbaa.context[id] = CPU_TO_LE64 ( ( (uintptr_t)slot->context ) ); + + USB_LOG_DBG("XHCI %s slot %d device context [%08lx,%08lx)\n", + xhci->name, slot->id, ( slot->context ), + ( ( slot->context ) + len ) ); + *slot_id = id; + return 0; + + xhci->dcbaa.context[id] = 0; + usb_free ( slot->context ); + +err_alloc_context: + xhci->slot[id] = NULL; + usb_free ( slot ); +err_alloc: + xhci_disable_slot ( xhci, ep, id ); +err_enable_slot: +err_type: + return rc; +} + +/*********************************************************************/ + +/** + * Assign device address + * + * @v xhci XHCI device + * @v slot Slot + * @v ep Endpoint + * @ret rc Return status code + */ +int xhci_device_address ( struct xhci_host *xhci, struct xhci_slot *slot, struct xhci_endpoint *ep ) { + USB_ASSERT((slot->xhci) && (ep->hport)); + struct usbh_hubport *hport = ep->hport; + int psiv; + int rc; + + /* Calculate route string */ + slot->route = usbh_route_string (hport); + + /* Calculate root hub port number */ + struct usbh_hubport *root_port = usbh_root_hub_port (hport); + slot->port = root_port->port; + + /* Calculate protocol speed ID */ + psiv = xhci_port_psiv ( xhci, slot->port, hport->speed ); + if ( psiv < 0 ) { + rc = psiv; + return rc; + } + slot->psiv = psiv; + + /* Address device */ + if ( ( rc = xhci_address_device ( xhci, ep, slot ) ) != 0 ) + return rc; + + return 0; +} + + +/** + * Close device + * + * @v slot Slot + */ +void xhci_device_close ( struct xhci_slot *slot ) { + struct xhci_host *xhci = slot->xhci; + size_t len = xhci_device_context_offset ( xhci, XHCI_CTX_END ); + unsigned int id = slot->id; + int rc; + + /* Disable slot */ + if ( ( rc = xhci_disable_slot ( xhci, slot->endpoint[0], id ) ) != 0 ) { + /* Slot is still enabled. Leak the slot context, + * since the controller may still write to this + * memory, and leave the DCBAA entry intact. + * + * If the controller later reports that this same slot + * has been re-enabled, then some assertions will be + * triggered. + */ + USB_LOG_DBG("XHCI %s slot %d leaking context memory\n", + xhci->name, slot->id ); + slot->context = NULL; + } + + /* Free slot */ + if ( slot->context ) { + usb_free ( slot->context ); + xhci->dcbaa.context[id] = 0; + } + xhci->slot[id] = NULL; + usb_free ( slot ); +} + + +/** + * Populate configure endpoint input context + * + * @v xhci xHCI device + * @v slot Device slot + * @v endpoint Endpoint + * @v input Input context + */ +static void xhci_configure_endpoint_input ( struct xhci_host *xhci, + struct xhci_slot *slot, + struct xhci_endpoint *endpoint, + void *input ) { + struct xhci_control_context *control_ctx; + struct xhci_slot_context *slot_ctx; + struct xhci_endpoint_context *ep_ctx; + + xhci_dump_endpoint(endpoint); + + /* Populate control context */ + control_ctx = input; + control_ctx->add = CPU_TO_LE32 (( 1 << XHCI_CTX_SLOT ) | ( 1 << endpoint->ctx ) ); + control_ctx->drop = CPU_TO_LE32 (( 1 << XHCI_CTX_SLOT ) | ( 1 << endpoint->ctx ) ); + + /* Populate slot context */ + slot_ctx = ( input + xhci_input_context_offset ( xhci, XHCI_CTX_SLOT )); + slot_ctx->info = CPU_TO_LE32 ( XHCI_SLOT_INFO ( ( XHCI_CTX_END - 1 ), + ( slot->ports ? 1 : 0 ), + slot->psiv, 0 ) ); + slot_ctx->ports = slot->ports; + + /* Populate endpoint context */ + ep_ctx = ( input + xhci_input_context_offset ( xhci, endpoint->ctx ) ); + ep_ctx->interval = endpoint->interval; /* bit[23:16] for interrupt ep, set interval to control interrupt period */ + /* + Value Endpoint Type Direction + 0 Not Valid N/A + 1 Isoch Out + 2 Bulk Out + 3 Interrupt Out + 4 Control Bidirectional + 5 Isoch In + 6 Bulk In + 7 Interrupt In + */ + ep_ctx->type = endpoint->ctx_type; + ep_ctx->burst = endpoint->burst; + ep_ctx->mtu = CPU_TO_LE16 ( endpoint->mtu ); /* bit[31:16] max packet size */ + ep_ctx->dequeue = CPU_TO_LE64 ( (uint64_t)( (uintptr_t)&(endpoint->reqs.ring[0]) ) | XHCI_EP_DCS ); + + /* TODO: endpoint attached on hub may need different setting here */ + if (endpoint->ep_type == USB_ENDPOINT_TYPE_BULK) { + ep_ctx->trb_len = CPU_TO_LE16 ( 256U ); /* bit[15:0] average trb length */ + } else if (endpoint->ep_type == USB_ENDPOINT_TYPE_INTERRUPT) { + ep_ctx->trb_len = CPU_TO_LE16 (16U); + ep_ctx->esit_low = CPU_TO_LE16 ( endpoint->mtu ); /* bit[31:16] max ESIT payload */ + } + + xhci_dump_input_ctx(xhci, endpoint, input); +} + +/** + * Configure endpoint + * + * @v xhci xHCI device + * @v slot Device slot + * @v endpoint Endpoint + * @ret rc Return status code + */ +static inline int xhci_configure_endpoint ( struct xhci_host *xhci, + struct xhci_slot *slot, + struct xhci_endpoint *endpoint ){ + int rc; + + /* Configure endpoint */ + if ( ( rc = xhci_context ( xhci, slot, endpoint, + XHCI_TRB_CONFIGURE_ENDPOINT, + xhci_configure_endpoint_input ) ) != 0 ){ + USB_LOG_ERR("XHCI %s slot %d ctx %d configure failed, error %d !!!\n", + xhci->name, slot->id, endpoint->ctx, rc ); + return rc; + } + + /* Sanity check */ + if ( ( endpoint->context->state & XHCI_ENDPOINT_STATE_MASK ) + != XHCI_ENDPOINT_RUNNING ){ + xhci_dump_slot_ctx(endpoint->slot->context); + xhci_dump_ep_ctx(endpoint->context); + USB_LOG_ERR("XHCI %s slot %d ctx %d configure failed !!!\n", + xhci->name, slot->id, endpoint->ctx ); + return -1; + } + + USB_LOG_DBG("XHCI %s slot %d ctx %d configured\n", + xhci->name, slot->id, endpoint->ctx ); + return 0; +} + +/** + * Populate deconfigure endpoint input context + * + * @v xhci xHCI device + * @v slot Device slot + * @v endpoint Endpoint + * @v input Input context + */ +static void +xhci_deconfigure_endpoint_input ( struct xhci_host *xhci __unused, + struct xhci_slot *slot __unused, + struct xhci_endpoint *endpoint, + void *input ) { + struct xhci_control_context *control_ctx; + struct xhci_slot_context *slot_ctx; + + /* Populate control context */ + control_ctx = input; + control_ctx->add = CPU_TO_LE32 ( 1 << XHCI_CTX_SLOT ); + control_ctx->drop = CPU_TO_LE32 ( 1 << endpoint->ctx ); + + /* Populate slot context */ + slot_ctx = ( input + xhci_input_context_offset ( xhci, XHCI_CTX_SLOT )); + slot_ctx->info = CPU_TO_LE32 ( XHCI_SLOT_INFO ( ( XHCI_CTX_END - 1 ), + 0, 0, 0 ) ); +} + +/** + * Deconfigure endpoint + * + * @v xhci xHCI device + * @v slot Device slot + * @v endpoint Endpoint + * @ret rc Return status code + */ +static inline int xhci_deconfigure_endpoint ( struct xhci_host *xhci, + struct xhci_slot *slot, + struct xhci_endpoint *endpoint ) { + int rc; + + /* Deconfigure endpoint */ + if ( ( rc = xhci_context ( xhci, slot, endpoint, + XHCI_TRB_CONFIGURE_ENDPOINT, + xhci_deconfigure_endpoint_input ) ) != 0 ) + return rc; + + USB_LOG_DBG("XHCI %s slot %d ctx %d deconfigured\n", + xhci->name, slot->id, endpoint->ctx ); + return 0; +} + +/*********************************************************************/ + +/** + * Open control endpoint + * + * @v xhci XHCI device + * @v slot Slot + * @v ep Endpoint + * @ret rc Return status code + */ +int xhci_ctrl_endpoint_open ( struct xhci_host *xhci, struct xhci_slot *slot, struct xhci_endpoint *ep ) { + unsigned int ctx; + + /* Calculate context index */ + ctx = XHCI_CTX ( ep->address ); + USB_ASSERT ( slot->endpoint[ctx] == NULL ); + + if (USB_ENDPOINT_TYPE_CONTROL != ep->ep_type) { + return -EINVAL; + } + + /* initialise structure */ + slot->endpoint[ctx] = ep; + ep->xhci = xhci; + ep->slot = slot; + ep->ctx = ctx; + ep->ctx_type = XHCI_EP_TYPE_CONTROL; + ep->context = ( ( ( void * ) slot->context ) + + xhci_device_context_offset ( xhci, ctx ) ); + ep->reqs.cs = 1; /* cycle state = 1 */ + + USB_LOG_DBG("XHCI %s slot %d endpoint 0x%x ep type %d xhci ep type 0x%x\n", + xhci->name, slot->id, ep->address, ep->ep_type, + (ep->ctx_type >> 3) ); + + USB_LOG_DBG("XHCI %s slot %d ctx %d ring [%08lx,%08lx)\n", + xhci->name, slot->id, ctx, ( ep->reqs.ring ), + ( ( ep->reqs.ring ) + sizeof(ep->reqs.ring) ) ); + + return 0; +} + +/*********************************************************************/ + +/** + * Open work endpoint + * + * @v xhci XHCI device + * @v slot Slot + * @v ep USB endpoint + * @ret rc Return status code + */ +int xhci_work_endpoint_open ( struct xhci_host *xhci, struct xhci_slot *slot, struct xhci_endpoint *ep ) { + unsigned int ctx; + unsigned int interval; + unsigned int ctx_type; + int rc; + + /* Calculate context index */ + ctx = XHCI_CTX ( ep->address ); + USB_ASSERT ( slot->endpoint[ctx] == NULL ); + + if (USB_ENDPOINT_TYPE_CONTROL == ep->ep_type) { + return -EINVAL; + } + + /* Calculate endpoint type */ + /* + Value Endpoint Type Direction, bit[5:3] + 0 Not Valid N/A + 1 Isoch Out + 2 Bulk Out + 3 Interrupt Out + 4 Control Bidirectional + 5 Isoch In + 6 Bulk In + 7 Interrupt In + */ + ctx_type = XHCI_EP_TYPE ( ep->ep_type ); + if ( ep->address & USB_EP_DIR_IN ) + ctx_type |= XHCI_EP_TYPE_IN; + + /* initialise structure */ + slot->endpoint[ctx] = ep; + ep->xhci = xhci; + ep->slot = slot; + ep->ctx = ctx; + + /* Calculate interval */ + if ( ctx_type & XHCI_EP_TYPE_PERIODIC ) { + ep->interval = ( fls ( ep->interval ) - 1 ); + } + + ep->ctx_type = ctx_type; + ep->context = ( ( ( void * ) slot->context ) + + xhci_device_context_offset ( xhci, ctx ) ); + ep->reqs.cs = 1; /* cycle state = 1 */ + + USB_LOG_DBG("XHCI %s slot %d endpoint 0x%x ep type %d xhci ep type 0x%x\n", + xhci->name, slot->id, ep->address, ep->ep_type, + (ep->ctx_type >> 3) ); + + /* Configure endpoint */ + if (( rc = xhci_configure_endpoint ( xhci, slot, ep ) ) != 0) { + goto err_configure_endpoint; + } + + USB_LOG_DBG("XHCI %s slot %d ctx %d ring [%08lx,%08lx)\n", + xhci->name, slot->id, ctx, ( ep->reqs.ring ), + ( ( ep->reqs.ring ) + sizeof(ep->reqs.ring) ) ); + + return 0; + err_configure_endpoint: + (void)xhci_deconfigure_endpoint ( xhci, slot, ep ); + slot->endpoint[ctx] = NULL; + return rc; +} + +/** + * Close endpoint + * + * @v ep USB endpoint + */ +void xhci_endpoint_close ( struct xhci_endpoint *ep ) { + struct xhci_slot *slot = ep->slot; + struct xhci_host *xhci = slot->xhci; + unsigned int ctx = ep->ctx; + + /* Deconfigure endpoint, if applicable */ + if ( ctx != XHCI_CTX_EP0 ) + (void)xhci_deconfigure_endpoint ( xhci, slot, ep ); + + slot->endpoint[ctx] = NULL; + usb_free(ep); +} + +/*********************************************************************/ + +/** + * Enqueue message transfer + * + * @v ep USB endpoint + * @v packet Setup packet buffer + * @v data_buff Data buffer + * @v datalen Data length + * @ret rc Return status code + */ +void xhci_endpoint_message ( struct xhci_endpoint *ep, + struct usb_setup_packet *packet, + void *data_buff, + int datalen ) { + struct xhci_host *xhci = ep->xhci; + struct xhci_slot *slot = ep->slot; + union xhci_trb trb; + struct xhci_trb_setup *setup; + struct xhci_trb_data *data; + struct xhci_trb_status *status; + unsigned int input; + + /* Construct setup stage TRB */ + setup = &(trb.setup); + memset ( setup, 0, sizeof ( *setup ) ); + + memcpy ( &setup->packet, packet, sizeof ( setup->packet ) ); + setup->len = CPU_TO_LE32 ( sizeof ( *packet ) ); /* bit[16:0] trb transfer length, always 8 */ + setup->flags = XHCI_TRB_IDT; /* bit[6] Immediate Data (IDT), parameters take effect */ + setup->type = XHCI_TRB_SETUP; /* bit[15:10] trb type */ + input = ( packet->bmRequestType & CPU_TO_LE16 ( USB_REQUEST_DIR_IN ) ); + if (datalen > 0) { + /* bit[17:16] Transfer type, 2 = OUT Data, 3 = IN Data */ + setup->direction = ( input ? XHCI_SETUP_IN : XHCI_SETUP_OUT ); + } + + xhci_trb_queue(&(ep->reqs), &trb); + + /* Construct data stage TRB, if applicable */ + if (datalen > 0) { + data = &(trb.data); + memset ( data, 0, sizeof ( *data ) ); + + data->data = CPU_TO_LE64 ( (uintptr_t)data_buff ); + data->len = CPU_TO_LE32 ( datalen ); + data->type = XHCI_TRB_DATA; /* bit[15:10] trb type */ + data->direction = ( input ? XHCI_DATA_IN : XHCI_DATA_OUT ); /* bit[16] Direction, 0 = OUT, 1 = IN */ + + xhci_trb_queue(&(ep->reqs), &trb); + } + + status = &(trb.status); + memset ( status, 0, sizeof ( *status ) ); + status->flags = XHCI_TRB_IOC; + status->type = XHCI_TRB_STATUS; + status->direction = + ( ( datalen && input ) ? XHCI_STATUS_OUT : XHCI_STATUS_IN ); + + xhci_trb_queue(&(ep->reqs), &trb); + + /* pass command trb to hardware */ + DSB(); + + USB_LOG_DBG("ring doorbell slot-%d ep-%d \r\n", slot->id, ep->ctx); + xhci_doorbell(xhci, slot->id, ep->ctx); /* 0 = db host controller, 0 = db targe hc command */ + + return; +} + +/*********************************************************************/ + +/** + * Enqueue stream transfer + * + * @v ep USB endpoint + * @v data_buff Data buffer + * @v datalen Data length + * @ret rc Return status code + */ +void xhci_endpoint_stream ( struct xhci_endpoint *ep, + void *data_buff, + int datalen ) { + struct xhci_host *xhci = ep->xhci; + struct xhci_slot *slot = ep->slot; + union xhci_trb trbs; + union xhci_trb *trb = &trbs; + struct xhci_trb_normal *normal; + int trb_len; + + /* Calculate TRB length */ + trb_len = XHCI_MTU; + if ( trb_len > datalen ) { + trb_len = datalen; + } else { + USB_LOG_ERR("transfer length %d exceed MTU %d \r\n", datalen, trb_len); + goto err_enqueue; + } + + /* Construct normal TRBs */ + normal = &trb->normal; + memset ( normal, 0, sizeof ( *normal ) ); + normal->data = CPU_TO_LE64 ( (uintptr_t)data_buff ); + normal->len = CPU_TO_LE32 ( trb_len ); + normal->type = XHCI_TRB_NORMAL; + normal->flags = XHCI_TRB_IOC; + + xhci_trb_queue(&(ep->reqs), trb); + + /* pass command trb to hardware */ + DSB(); + + xhci_doorbell(xhci, slot->id, ep->ctx); + +err_enqueue: + return; +} + +/*********************************************************************/ + +/** + * Populate evaluate context input context + * + * @v xhci xHCI device + * @v slot Device slot + * @v endpoint Endpoint + * @v input Input context + */ +static void xhci_evaluate_context_input ( struct xhci_host *xhci, + struct xhci_slot *slot __unused, + struct xhci_endpoint *endpoint, + void *input ) { + struct xhci_control_context *control_ctx; + struct xhci_slot_context *slot_ctx; + struct xhci_endpoint_context *ep_ctx; + + /* Populate control context */ + control_ctx = input; + control_ctx->add = CPU_TO_LE32 ( ( 1 << XHCI_CTX_SLOT ) /*| + ( 1 << endpoint->ctx )*/ ); + control_ctx->drop = CPU_TO_LE32 ( ( 1 << XHCI_CTX_SLOT ) /* | + ( 1 << endpoint->ctx )*/ ); + + /* Populate slot context */ + slot_ctx = ( input + xhci_input_context_offset ( xhci, XHCI_CTX_SLOT )); + slot_ctx->info = CPU_TO_LE32 ( XHCI_SLOT_INFO ( ( XHCI_CTX_END - 1 ), + 0, 0, 0 ) ); + + /* Populate endpoint context */ + ep_ctx = ( input + xhci_input_context_offset ( xhci, endpoint->ctx ) ); + ep_ctx->mtu = CPU_TO_LE16 ( endpoint->mtu ); +} + +/** + * Evaluate context + * + * @v xhci xHCI device + * @v slot Device slot + * @v endpoint Endpoint + * @ret rc Return status code + */ +static inline int xhci_evaluate_context ( struct xhci_host *xhci, + struct xhci_slot *slot, + struct xhci_endpoint *endpoint ) { + int rc; + + /* Configure endpoint */ + if ( ( rc = xhci_context ( xhci, slot, endpoint, + XHCI_TRB_EVALUATE_CONTEXT, + xhci_evaluate_context_input ) ) != 0 ) + return rc; + + USB_LOG_DBG("XHCI %s slot %d ctx %d (re-)evaluated\n", + xhci->name, slot->id, endpoint->ctx ); + return 0; +} + +/** + * Update MTU + * + * @v ep USB endpoint + * @ret rc Return status code + */ +int xhci_endpoint_mtu ( struct xhci_endpoint *ep ) { + struct xhci_endpoint *endpoint = ( ep ); + struct xhci_slot *slot = endpoint->slot; + struct xhci_host *xhci = slot->xhci; + int rc; + + /* Evalulate context */ + if ( ( rc = xhci_evaluate_context ( xhci, slot, endpoint ) ) != 0 ) + return rc; + + return 0; +} + +/*********************************************************************/ + +/** + * Handle port status event + * + * @v xhci xHCI device + * @v trb Port status event + */ +static void xhci_port_status ( struct xhci_host *xhci, + struct xhci_trb_port_status *trb ) { + struct usbh_bus *bus = xhci->bus; + USB_ASSERT(bus); + + uint32_t portsc; + + /* Sanity check */ + USB_ASSERT ( ( trb->port > 0 ) && ( trb->port <= xhci->ports ) ); + + /* Record disconnections, changes flag will be cleared later */ + portsc = readl ( xhci->op + XHCI_OP_PORTSC ( trb->port ) ); + xhci_dump_port_status(trb->port, portsc); + + if (portsc & XHCI_PORTSC_CSC) { + /* Report port status change */ + usbh_roothub_thread_wakeup ( bus->id, trb->port ); + } +} + +/** + * Handle transfer event + * + * @v xhci xHCI device + * @v trb Transfer event TRB + */ +static void xhci_transfer ( struct xhci_host *xhci, + struct xhci_trb_transfer *trb ) { + struct xhci_slot *slot; + struct xhci_endpoint *endpoint; + union xhci_trb *trans_trb = (void *)(uintptr_t)(trb->transfer); + struct xhci_ring *trans_ring = XHCI_RING(trans_trb); /* to align addr is ring base */ + union xhci_trb *pending = &trans_ring->evt; /* preserve event trb pending to handle */ + uint32_t eidx = trans_trb - trans_ring->ring + 1; /* calculate current evt trb index */ + int rc; + + /* Identify slot */ + if ( ( trb->slot > xhci->slots ) || + ( ( slot = xhci->slot[trb->slot] ) == NULL ) ) { + USB_LOG_DBG("XHCI %s transfer event invalid slot %d:\n", + xhci->name, trb->slot ); + return; + } + + /* Identify endpoint */ + if ( ( trb->endpoint >= XHCI_CTX_END ) || + ( ( endpoint = slot->endpoint[trb->endpoint] ) == NULL ) ) { + USB_LOG_DBG("XHCI %s slot %d transfer event invalid epid " + "%d:\n", xhci->name, slot->id, trb->endpoint ); + return; + } + + /* Record completion */ + memcpy(pending, trb, sizeof(*trb)); /* copy current trb to cmd/transfer ring */ + trans_ring->eidx = eidx; + + /* Check for errors */ + if ( ! ( ( trb->code == XHCI_CMPLT_SUCCESS ) || + ( trb->code == XHCI_CMPLT_SHORT ) ) ) { + USB_LOG_ERR("XHCI %s slot %d ctx %d failed (code %d)\n", + xhci->name, slot->id, endpoint->ctx, trb->code); + + /* Sanity check */ + USB_ASSERT ( ( endpoint->context->state & XHCI_ENDPOINT_STATE_MASK ) + != XHCI_ENDPOINT_RUNNING ); + + xhci_dump_ep_ctx(endpoint->context); + return; + } + + if (endpoint->waiter) { + endpoint->waiter = false; + usb_osal_sem_give(endpoint->waitsem); + } + + if (endpoint->urb) { + struct usbh_urb *cur_urb = endpoint->urb; + cur_urb->errorcode = trb->code; + /* bit [23:0] TRB Transfer length, residual number of bytes not transferred + for OUT, is the value of (len of trb) - (data bytes transmitted), '0' means successful + for IN, is the value of (len of trb) - (data bytes received), + if cc is Short Packet, value is the diff between expected trans size and actual recv bytes + if cc is other error, value is the diff between expected trans size and actual recv bytes */ + cur_urb->actual_length += cur_urb->transfer_buffer_length - trb->residual; /* bit [23:0] */ + + if (cur_urb->complete) { + if (cur_urb->errorcode < 0) { + cur_urb->complete(cur_urb->arg, cur_urb->errorcode); + } else { + cur_urb->complete(cur_urb->arg, cur_urb->actual_length); + } + } + } + + return; +} + +/** + * Handle command completion event + * + * @v xhci xHCI device + * @v trb Command completion event + */ +static void xhci_complete ( struct xhci_host *xhci, + struct xhci_trb_complete *trb ) { + int rc; + union xhci_trb *cmd_trb = (void *)(uintptr_t)(trb->command); + struct xhci_ring *cmd_ring = XHCI_RING(cmd_trb); /* to align addr is ring base */ + union xhci_trb *pending = &cmd_ring->evt; /* preserve event trb pending to handle */ + uint32_t eidx = cmd_trb - cmd_ring->ring + 1; /* calculate current evt trb index */ + struct xhci_endpoint *work_pipe = xhci->cur_cmd_pipe; + + /* Ignore "command ring stopped" notifications */ + if ( trb->code == XHCI_CMPLT_CMD_STOPPED ) { + USB_LOG_DBG("XHCI %s command ring stopped\n", xhci->name ); + return; + } + + /* Record completion */ + USB_LOG_DBG("command-0x%x completed !!! \r\n", pending); + memcpy(pending, trb, sizeof(*trb)); /* copy current trb to cmd/transfer ring */ + cmd_ring->eidx = eidx; + + USB_ASSERT(work_pipe); + if (work_pipe->waiter) + { + work_pipe->waiter = false; + usb_osal_sem_give(work_pipe->waitsem); + } +} + +/** + * Handle host controller event + * + * @v xhci xHCI device + * @v trb Host controller event + */ +static void xhci_host_controller ( struct xhci_host *xhci, + struct xhci_trb_host_controller *trb ) { + int rc; + + /* Construct error */ + rc = -( trb->code ); + USB_LOG_ERR("XHCI %s host controller event (code %d)\n", + xhci->name, trb->code ); +} + +/** + * Process event ring in interrupt + * + * @v xhci xHCI device + */ +void xhci_event_process(struct xhci_host *xhci) { + struct xhci_ring *evts = xhci->evts; + unsigned int evt_type; + uint32_t nidx; + uint32_t cs; + union xhci_trb *trb; + uint32_t control; + uint64_t erdp; + + /* check and ack event */ + for (;;) { + /* Stop if we reach an empty TRB */ + DSB(); + + nidx = evts->nidx; /* index of dequeue trb */ + cs = evts->cs; /* cycle state toggle by xHc */ + trb = evts->ring + nidx; /* current trb */ + control = trb->common.flags; /* trb control field */ + + if ((control & XHCI_TRB_C) != (cs ? 1 : 0)) { /* if cycle state not toggle, no events need to handle */ + break; + } + + /* Handle TRB */ + evt_type = ( trb->common.type & XHCI_TRB_TYPE_MASK ); + switch ( evt_type ) { + + case XHCI_TRB_TRANSFER : + xhci_transfer ( xhci, &trb->transfer ); + break; + + case XHCI_TRB_COMPLETE : + xhci_complete ( xhci, &trb->complete ); + break; + + case XHCI_TRB_PORT_STATUS: + xhci_port_status ( xhci, &trb->port ); + break; + + case XHCI_TRB_HOST_CONTROLLER: + xhci_host_controller ( xhci, &trb->host ); + break; + + default: + USB_LOG_DBG("XHCI %s unrecognised event type %d\n:", + xhci->name, ( evt_type ) ); + break; + } + + /* move ring index, notify xhci */ + nidx++; /* head to next trb */ + if (nidx == XHCI_RING_ITEMS) + { + nidx = 0; /* roll-back if reach end of list */ + cs = cs ? 0 : 1; + evts->cs = cs; /* sw toggle cycle state */ + } + evts->nidx = nidx; + + /* Update dequeue pointer if applicable */ + erdp = (uint64_t)(unsigned long)(evts->ring + nidx); + xhci_writeq ( xhci, (uintptr_t)( erdp ) | XHCI_RUN_ERDP_EHB, + xhci->run + XHCI_RUN_ERDP ( 0 ) ); + } + + return; +} \ No newline at end of file From d4f72f2ad9ce24bcfdfe2b72c60a2a5354cd8589 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 18 Jun 2024 16:09:32 +0800 Subject: [PATCH 031/198] Decoupling core and xhci. --- .../drivers/usb/components/core/usbh_core.c | 100 ++++++++++++++---- .../drivers/usb/components/core/usbh_core.h | 51 +++++---- 2 files changed, 112 insertions(+), 39 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c index 134378d2b..1822356cd 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c @@ -3,16 +3,24 @@ * * SPDX-License-Identifier: Apache-2.0 */ - + /************************************************* File name: usbh_core.c Description: adopt cherry USB to XiZi AIOT. Others: CherryUSB third-party/cherryusb/core/usbh_core.c for references https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/blob/master/third-party/cherryusb/core/usbh_core.c + +History: +1. Date: 2024-06-18 +Author: AIIT XUOS Lab +Modification: + Modify function usbh_enumerate usbh_hport_activate_ep0 usbh_hport_deactivate_ep0 and usbh_hport_activate_epx, for select host controller function. + new function usbh_control_transfer_msg, for references usbh_control_transfer, to select host controller function by type. *************************************************/ #include "usbh_core.h" #include "usbh_hub.h" +#include "usb_hc_xhci.h" struct usbh_class_info *usbh_class_info_table_begin = NULL; struct usbh_class_info *usbh_class_info_table_end = NULL; @@ -463,6 +471,7 @@ static int usbh_get_default_mps(int speed) int usbh_hport_activate_ep0(struct usbh_hubport *hport) { + struct usbh_bus *usb = usbh_get_bus_of_port(hport); struct usbh_endpoint_cfg ep0_cfg = { 0 }; ep0_cfg.ep_addr = 0x00; @@ -471,7 +480,14 @@ int usbh_hport_activate_ep0(struct usbh_hubport *hport) ep0_cfg.ep_type = USB_ENDPOINT_TYPE_CONTROL; ep0_cfg.hport = hport; - usbh_pipe_alloc(&hport->ep0, &ep0_cfg); + if (USB_HC_XHCI == usb->usb_hc_type) { + xhci_usbh_pipe_alloc(&hport->ep0, &ep0_cfg); + } + else { + USB_LOG_WRN("invalid usb controller type %d \r\n", usb->usb_hc_type); + return -EINVAL; + } + return 0; } @@ -485,7 +501,13 @@ int usbh_hport_deactivate_ep0(struct usbh_hubport *hport) } #endif if (hport->ep0) { - usbh_pipe_free(hport->ep0); + if (USB_HC_XHCI == usb->usb_hc_type) { + xhci_usbh_pipe_free(hport->ep0); + } + else { + USB_LOG_WRN("invalid usb controller type %d \r\n", usb->usb_hc_type); + return -EINVAL; + } } hport->ep0 = NULL; @@ -495,6 +517,7 @@ int usbh_hport_deactivate_ep0(struct usbh_hubport *hport) int usbh_hport_activate_epx(usbh_pipe_t *pipe, struct usbh_hubport *hport, struct usb_endpoint_descriptor *ep_desc) { + struct usbh_bus *usb = usbh_get_bus_of_port(hport); struct usbh_endpoint_cfg ep_cfg = { 0 }; ep_cfg.ep_addr = ep_desc->bEndpointAddress; @@ -511,7 +534,13 @@ int usbh_hport_activate_epx(usbh_pipe_t *pipe, struct usbh_hubport *hport, struc ep_cfg.ep_interval, ep_cfg.mult); - return usbh_pipe_alloc(pipe, &ep_cfg); + if (USB_HC_XHCI == usb->usb_hc_type) { + return xhci_usbh_pipe_alloc(pipe, &ep_cfg); + } + else { + USB_LOG_WRN("invalid usb controller type %d \r\n", usb->usb_hc_type); + return -EINVAL; + } } int usbh_enumerate(struct usbh_hubport *hport) @@ -535,7 +564,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wLength = 8; dev_desc = (struct usb_device_descriptor *)usb->ep0_request_buffer; - ret = usbh_control_transfer(hport->ep0, setup, (uint8_t *)dev_desc); + ret = usbh_control_transfer_msg(usb->usb_hc_type, hport->ep0, setup, (uint8_t *)dev_desc); if (ret < 0) { USB_LOG_ERR("Failed to get device descriptor,errorcode:%d\r\n", ret); goto errout; @@ -558,14 +587,22 @@ int usbh_enumerate(struct usbh_hubport *hport) usbh_ep_pipe_reconfigure(usb, hport->ep0, 0, ep_mps, 0); #ifdef CONFIG_USBHOST_XHCI - extern int usbh_get_xhci_devaddr(usbh_pipe_t * pipe); + if (USB_HC_XHCI == usb->usb_hc_type) { + extern int usbh_get_xhci_devaddr(usbh_pipe_t * pipe); + + /* Assign a function address to the device connected to this port */ + dev_addr = usbh_get_xhci_devaddr(hport->ep0); + if (dev_addr < 0) { + USB_LOG_ERR("Failed to allocate devaddr,errorcode:%d\r\n", ret); + goto errout; + } - /* Assign a function address to the device connected to this port */ - dev_addr = usbh_get_xhci_devaddr(hport->ep0); - if (dev_addr < 0) { - USB_LOG_ERR("Failed to allocate devaddr,errorcode:%d\r\n", ret); + } + else { + USB_LOG_WRN("invalid usb controller type %d \r\n", usb->usb_hc_type); goto errout; } + #else /* Assign a function address to the device connected to this port */ dev_addr = usbh_allocate_devaddr(&usb->devgen); @@ -582,7 +619,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wIndex = 0; setup->wLength = 0; - ret = usbh_control_transfer(hport->ep0, setup, NULL); + ret = usbh_control_transfer_msg(usb->usb_hc_type, hport->ep0, setup, NULL); if (ret < 0) { USB_LOG_ERR("Failed to set devaddr,errorcode:%d\r\n", ret); goto errout; @@ -604,7 +641,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wIndex = 0; setup->wLength = USB_SIZEOF_DEVICE_DESC; - ret = usbh_control_transfer(hport->ep0, setup, usb->ep0_request_buffer); + ret = usbh_control_transfer_msg(usb->usb_hc_type, hport->ep0, setup, usb->ep0_request_buffer); if (ret < 0) { USB_LOG_ERR("Failed to get full device descriptor,errorcode:%d\r\n", ret); goto errout; @@ -623,7 +660,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wIndex = 0; setup->wLength = USB_SIZEOF_CONFIG_DESC; - ret = usbh_control_transfer(hport->ep0, setup, usb->ep0_request_buffer); + ret = usbh_control_transfer_msg(usb->usb_hc_type, hport->ep0, setup, usb->ep0_request_buffer); if (ret < 0) { USB_LOG_ERR("Failed to get config descriptor,errorcode:%d\r\n", ret); goto errout; @@ -640,7 +677,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wIndex = 0; setup->wLength = wTotalLength; - ret = usbh_control_transfer(hport->ep0, setup, usb->ep0_request_buffer); + ret = usbh_control_transfer_msg(usb->usb_hc_type, hport->ep0, setup, usb->ep0_request_buffer); if (ret < 0) { USB_LOG_ERR("Failed to get full config descriptor,errorcode:%d\r\n", ret); goto errout; @@ -667,7 +704,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wIndex = 0x0409; setup->wLength = 255; - ret = usbh_control_transfer(hport->ep0, setup, usb->ep0_request_buffer); + ret = usbh_control_transfer_msg(usb->usb_hc_type, hport->ep0, setup, usb->ep0_request_buffer); if (ret < 0) { USB_LOG_ERR("Failed to get Manufacturer string,errorcode:%d\r\n", ret); goto errout; @@ -682,7 +719,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wIndex = 0x0409; setup->wLength = 255; - ret = usbh_control_transfer(hport->ep0, setup, usb->ep0_request_buffer); + ret = usbh_control_transfer_msg(usb->usb_hc_type, hport->ep0, setup, usb->ep0_request_buffer); if (ret < 0) { USB_LOG_ERR("Failed to get get Product string,errorcode:%d\r\n", ret); goto errout; @@ -697,7 +734,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wIndex = 0x0409; setup->wLength = 255; - ret = usbh_control_transfer(hport->ep0, setup, usb->ep0_request_buffer); + ret = usbh_control_transfer_msg(usb->usb_hc_type, hport->ep0, setup, usb->ep0_request_buffer); if (ret < 0) { USB_LOG_ERR("Failed to get get SerialNumber string,errorcode:%d\r\n", ret); goto errout; @@ -712,7 +749,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wIndex = 0; setup->wLength = 0; - ret = usbh_control_transfer(hport->ep0, setup, NULL); + ret = usbh_control_transfer_msg(usb->usb_hc_type, hport->ep0, setup, NULL); if (ret < 0) { USB_LOG_ERR("Failed to set configuration,errorcode:%d\r\n", ret); goto errout; @@ -853,6 +890,31 @@ int usbh_control_transfer(usbh_pipe_t pipe, struct usb_setup_packet *setup, uint return ret; } +int usbh_control_transfer_msg(uint8_t hc_type, usbh_pipe_t pipe, struct usb_setup_packet *setup, uint8_t *buffer) +{ + struct usbh_urb *urb; + int ret; + + urb = usb_malloc(sizeof(struct usbh_urb)); + memset(urb, 0, sizeof(struct usbh_urb)); + + usbh_control_urb_fill(urb, pipe, setup, buffer, setup->wLength, CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT, NULL, NULL); + + if (USB_HC_XHCI == hc_type) { + ret = xhci_usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + } + else { + USB_LOG_WRN("invalid usb controller type %d \r\n", hc_type); + ret = -EINVAL; + } + + usb_free(urb); + return ret; +} + int lsusb(int argc, char **argv) { usb_slist_t *i; @@ -945,4 +1007,4 @@ int lsusb(int argc, char **argv) } return 0; -} \ No newline at end of file +} diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h index ddc40012b..6022c7ef2 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h @@ -1,3 +1,22 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/************************************************* +File name: usbh_core.c +Description: adopt cherry USB to XiZi AIOT. +Others: CherryUSB third-party/cherryusb/core/usbh_core.h for references + https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/blob/master/third-party/cherryusb/core/usbh_core.h + +History: +1. Date: 2024-06-18 +Author: AIIT XUOS Lab +Modification: new parameter usb_hc_type for host controller type. +*************************************************/ + + #ifndef USBH_CORE_H_ #define USBH_CORE_H_ @@ -21,6 +40,14 @@ extern "C" { #endif +/** + * @brief USB host controller type. + * USB 1.1 OHCI UHCI + * USB 2.0 EHCI DWC2 + * USB 3.0 XHCI DWC3 + */ +#define USB_HC_XHCI 5 +#define USB_HC_DWC3 6 #define USB_CLASS_MATCH_VENDOR 0x0001 #define USB_CLASS_MATCH_PRODUCT 0x0002 @@ -40,7 +67,6 @@ extern "C" { #define CLASS_INFO_DEFINE __attribute__((section("usbh_class_info"))) __USED __ALIGNED(1) #endif - static inline void usbh_control_urb_fill(struct usbh_urb *urb, usbh_pipe_t pipe, struct usb_setup_packet *setup, @@ -59,8 +85,6 @@ static inline void usbh_control_urb_fill(struct usbh_urb *urb, urb->arg = arg; } - - static inline void usbh_bulk_urb_fill(struct usbh_urb *urb, usbh_pipe_t pipe, uint8_t *transfer_buffer, @@ -78,8 +102,6 @@ static inline void usbh_bulk_urb_fill(struct usbh_urb *urb, urb->arg = arg; } - - static inline void usbh_int_urb_fill(struct usbh_urb *urb, usbh_pipe_t pipe, uint8_t *transfer_buffer, @@ -97,8 +119,6 @@ static inline void usbh_int_urb_fill(struct usbh_urb *urb, urb->arg = arg; } - - struct usbh_class_info { uint8_t match_flags; /* Used for product specific matches; range is inclusive */ uint8_t class; /* Base device class code */ @@ -109,17 +129,13 @@ struct usbh_class_info { const struct usbh_class_driver *class_driver; }; - struct usbh_hubport; - struct usbh_class_driver { const char *driver_name; int (*connect)(struct usbh_hubport *hport, uint8_t intf); int (*disconnect)(struct usbh_hubport *hport, uint8_t intf); }; - - struct usbh_endpoint { struct usb_endpoint_descriptor ep_desc; }; @@ -143,8 +159,6 @@ struct usbh_configuration { }; struct usbh_hub; - - struct usbh_hubport { /** Name */ char name[32]; @@ -167,9 +181,7 @@ struct usbh_hubport { }; - struct usbh_bus; - struct usbh_hub { usb_slist_t list; bool connected; @@ -189,7 +201,6 @@ struct usbh_hub { USB_MEM_ALIGNX uint8_t g_hub_intbuf[CONFIG_USBHOST_MAX_EXTHUBS + 1][1]; }; - int usbh_hport_activate_epx(usbh_pipe_t *pipe, struct usbh_hubport *hport, struct usb_endpoint_descriptor *ep_desc); /** @@ -204,6 +215,8 @@ int usbh_hport_activate_epx(usbh_pipe_t *pipe, struct usbh_hubport *hport, struc */ int usbh_control_transfer(usbh_pipe_t pipe, struct usb_setup_packet *setup, uint8_t *buffer); +int usbh_control_transfer_msg(uint8_t hc_type, usbh_pipe_t pipe, struct usb_setup_packet *setup, uint8_t *buffer); + struct usbh_devaddr_map { /** * alloctab[0]:addr from 0~31 @@ -219,6 +232,7 @@ struct usbh_devaddr_map { struct usbh_bus { usb_slist_t list; uint8_t id; + uint8_t usb_hc_type; /** Largest transfer allowed on the bus */ size_t mtu; struct usbh_devaddr_map devgen; @@ -282,11 +296,8 @@ struct usbh_hubport *usbh_find_hubport(uint32_t id, uint8_t dev_addr); void *usbh_find_class_instance(const char *devname); int lsusb(int argc, char **argv); - #ifdef __cplusplus } #endif - - -#endif +#endif /* USBH_CORE_H */ From 75e1299ac75f40ab93537c0f43d67e355c267b93 Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 18 Jun 2024 05:04:38 -0700 Subject: [PATCH 032/198] Establish Folders for future USB IP --- .../XiZi_AIoT/services/drivers/usb/components/port/README.md | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/README.md diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/README.md b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/README.md new file mode 100644 index 000000000..b0109ef6a --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/README.md @@ -0,0 +1,3 @@ +USB3.0: xhci dwc3 +USB2.0: ehci dwc2 +USB1.1: ohci uhci From 01a0f62f7897e102fe7b251863cb72685e480f5c Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 18 Jun 2024 05:20:32 -0700 Subject: [PATCH 033/198] Adding folders for future USB IP --- .../usb/components/port/xhci/usb_hc_xhci.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index 51057192c..e23726388 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -535,4 +535,21 @@ void USBH_IRQHandler(void *param) writel (runtime, xhci->run + XHCI_RUN_IR_IMAN ( 0 )); (void)xhci_event_process(xhci); -} \ No newline at end of file +} + + +/* + * Functions for xHCI drivers. These functions are called by USB core. + */ +int xhci_usb_hc_init(uint32_t id){ + return 0; +} + + + +uint16_t xhci_usbh_get_frame_number(void){ + return 0; +} + + + From eee6a74ff0af13a4d6aeb4d8061745d0d49b8ba5 Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 18 Jun 2024 05:27:09 -0700 Subject: [PATCH 034/198] Adding folders for future USB IP --- .../services/drivers/usb/components/port/dwc2/.gitignore | 0 .../services/drivers/usb/components/port/dwc3/.gitignore | 0 .../services/drivers/usb/components/port/ehci/.gitignore | 0 .../services/drivers/usb/components/port/ohci/.gitignore | 0 .../services/drivers/usb/components/port/uhci/.gitignore | 0 5 files changed, 0 insertions(+), 0 deletions(-) create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc2/.gitignore create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/.gitignore create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/ehci/.gitignore create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/ohci/.gitignore create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/uhci/.gitignore diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc2/.gitignore b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc2/.gitignore new file mode 100644 index 000000000..e69de29bb diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/.gitignore b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/.gitignore new file mode 100644 index 000000000..e69de29bb diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/ehci/.gitignore b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/ehci/.gitignore new file mode 100644 index 000000000..e69de29bb diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/ohci/.gitignore b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/ohci/.gitignore new file mode 100644 index 000000000..e69de29bb diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/uhci/.gitignore b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/uhci/.gitignore new file mode 100644 index 000000000..e69de29bb From 3d5e8ed6fcb56f43d388c32d9d9a1cea42b50d71 Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 18 Jun 2024 18:32:11 -0700 Subject: [PATCH 035/198] uncouple the USB core and xhci --- .../usb/components/port/xhci/usb_hc_xhci.c | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index e23726388..563fc6692 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -552,4 +552,36 @@ uint16_t xhci_usbh_get_frame_number(void){ } +int xhci_usbh_roothub_control(struct usbh_bus *usb, struct usb_setup_packet *setup, uint8_t *buf){ + return 0; +} + +int xhci_usbh_ep_pipe_reconfigure(struct usbh_bus *usb, usbh_pipe_t pipe, uint8_t dev_addr, uint8_t ep_mps, uint8_t mult){ + return 0; +} + + +int xhci_usbh_pipe_alloc(usbh_pipe_t *pipe, const struct usbh_endpoint_cfg *ep_cfg){ + return 0; +} + + +int xhci_usbh_pipe_free(usbh_pipe_t pipe){ + return 0; +} + + +int xhci_usbh_submit_urb(struct usbh_urb *urb){ + return 0; +} + + +int xhci_usbh_kill_urb(struct usbh_urb *urb){ + return 0; +} + + +void XHCI_USBH_IRQHandler(void *param){ + +} \ No newline at end of file From cc22f1b8f89c22436a63e3746be08a1d85c77c9c Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Wed, 19 Jun 2024 10:33:20 +0800 Subject: [PATCH 036/198] New field usb_hc_type in data structure usbh_urb --- .../drivers/usb/components/common/usb_hc.h | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_hc.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_hc.h index 26070dd49..4ab24939f 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_hc.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_hc.h @@ -3,6 +3,16 @@ * * SPDX-License-Identifier: Apache-2.0 */ +/************************************************* +File name: usb_hc.h +Description: adopt cherry USB to XiZi AIOT. +Others: take CherryUSB v0.1.2/common/usb_hc.h for references + https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/blob/master/third-party/cherryusb/common/usb_hc.h +History: +1. Date: 2024-06-19 +Author: AIIT XUOS Lab +Modification: New field usb_hc_type in data structure usbh_urb. +*************************************************/ #ifndef USB_HC_H_ #define USB_HC_H_ @@ -59,6 +69,7 @@ struct usbh_urb { uint32_t actual_length; uint32_t timeout; int errorcode; + uint8_t usb_hc_type; uint32_t num_of_iso_packets; uint32_t start_frame; usbh_complete_callback_t complete; @@ -142,7 +153,4 @@ int usbh_kill_urb(struct usbh_urb *urb); } #endif - - - -#endif +#endif /* USB_HC_H_ */ From 9f3edeb6b43711b352d14cfc0df663aecbd9afb4 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Wed, 19 Jun 2024 10:35:39 +0800 Subject: [PATCH 037/198] Extract the functions of the host controller to USB core. --- .../drivers/usb/components/core/usbh_core.c | 56 +++++++++++++++++-- .../usb/components/port/xhci/usb_hc_xhci.c | 4 +- 2 files changed, 55 insertions(+), 5 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c index 1822356cd..52ea8b7fa 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c @@ -13,9 +13,12 @@ Others: CherryUSB third-party/cherryusb/core/usbh_core.c for references History: 1. Date: 2024-06-18 Author: AIIT XUOS Lab -Modification: - Modify function usbh_enumerate usbh_hport_activate_ep0 usbh_hport_deactivate_ep0 and usbh_hport_activate_epx, for select host controller function. - new function usbh_control_transfer_msg, for references usbh_control_transfer, to select host controller function by type. +Modification: Modify function usbh_enumerate usbh_hport_activate_ep0 usbh_hport_deactivate_ep0 and usbh_hport_activate_epx, for select host controller function. + New function usbh_control_transfer_msg, for references usbh_control_transfer, to select host controller function by type. + +2. Date: 2024-06-19 +Author: AIIT XUOS Lab +Modification: Extract the functions of the host controller to core. *************************************************/ #include "usbh_core.h" @@ -589,7 +592,6 @@ int usbh_enumerate(struct usbh_hubport *hport) #ifdef CONFIG_USBHOST_XHCI if (USB_HC_XHCI == usb->usb_hc_type) { extern int usbh_get_xhci_devaddr(usbh_pipe_t * pipe); - /* Assign a function address to the device connected to this port */ dev_addr = usbh_get_xhci_devaddr(hport->ep0); if (dev_addr < 0) { @@ -1008,3 +1010,49 @@ int lsusb(int argc, char **argv) return 0; } + +/* xhci hardware init */ +int usb_hc_init(uint32_t id) +{ + return 0; +} + +int usbh_roothub_control(struct usbh_bus *usb, struct usb_setup_packet *setup, uint8_t *buf) +{ + return 0; +} + +int usbh_ep_pipe_reconfigure(struct usbh_bus *usb, usbh_pipe_t pipe, uint8_t dev_addr, uint8_t mtu, uint8_t speed) +{ + return 0; +} + +int usbh_pipe_alloc(usbh_pipe_t *pipe, const struct usbh_endpoint_cfg *ep_cfg) +{ + return 0; +} + +int usbh_get_xhci_devaddr(usbh_pipe_t *pipe) +{ + return 0; +} + +int usbh_pipe_free(usbh_pipe_t pipe) +{ + return 0; +} + +int usbh_submit_urb(struct usbh_urb *urb) +{ + return 0; +} + +int usbh_kill_urb(struct usbh_urb *urb) +{ + return 0; +} + +void USBH_IRQHandler(void *param) +{ +} + diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index 563fc6692..4e5d109c7 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -93,6 +93,8 @@ static inline struct xhci_host* xhci_get_inst_of_port(struct usbh_hubport *hport static struct xhci_host xhci_host[CONFIG_USBHOST_XHCI_NUM]; +/* Functions that need to be refactored */ +#if 0 /* xhci hardware init */ int usb_hc_init(uint32_t id) { @@ -536,7 +538,7 @@ void USBH_IRQHandler(void *param) (void)xhci_event_process(xhci); } - +#endif /* * Functions for xHCI drivers. These functions are called by USB core. From 83a4b774b5b524a92d3a177bde9ab996faf19aed Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 18 Jun 2024 23:10:46 -0700 Subject: [PATCH 038/198] Modify xhci functions for USB core --- .../usb/components/port/xhci/usb_hc_xhci.c | 219 +++++++++++++++++- 1 file changed, 218 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index 4e5d109c7..85813ae0f 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -544,7 +544,30 @@ void USBH_IRQHandler(void *param) * Functions for xHCI drivers. These functions are called by USB core. */ int xhci_usb_hc_init(uint32_t id){ - return 0; + USB_ASSERT(id < CONFIG_USBHOST_XHCI_NUM); + int rc = 0; + struct usbh_bus *bus = usbh_get_bus_of_index(id); + USB_ASSERT(bus); + struct xhci_host *xhci = &(xhci_host[id]); + + size_t flag = usb_osal_enter_critical_section(); /* no interrupt when init hc */ + + usb_hc_low_level_init(id); /* set gic and memp */ + + memset(xhci, 0, sizeof(*xhci)); + xhci->bus = bus; + bus->priv = xhci; + if (rc = xhci_probe(xhci, usb_hc_get_register_base(id)) != 0) { + goto err_open; + } + + if (rc = xhci_open(xhci) != 0 ) { + goto err_open; + } + + err_open: + usb_osal_leave_critical_section(flag); + return rc; } @@ -555,6 +578,200 @@ uint16_t xhci_usbh_get_frame_number(void){ int xhci_usbh_roothub_control(struct usbh_bus *usb, struct usb_setup_packet *setup, uint8_t *buf){ + uint8_t nports; + uint8_t port; + uint32_t portsc; + uint32_t status; + int ret = 0; + struct xhci_host *xhci = usb->priv; + nports = CONFIG_USBHOST_MAX_RHPORTS; + + port = setup->wIndex; + + /* + bmRequestType bit[4:0], define whether the request is directed to the device (0000b), + specific interface (00001b), endpoint (00010b), or other element (00011b) + bRequest, identifies the request + wValue, pass the request-specific info to the device + */ + if (setup->bmRequestType & USB_REQUEST_RECIPIENT_DEVICE) /* request is directed to device */ + { + switch (setup->bRequest) + { + case HUB_REQUEST_CLEAR_FEATURE: /* disable the feature */ + switch (setup->wValue) + { + case HUB_FEATURE_HUB_C_LOCALPOWER: + USB_LOG_ERR("HUB_FEATURE_HUB_C_LOCALPOWER not implmented.\n"); + break; + case HUB_FEATURE_HUB_C_OVERCURRENT: + USB_LOG_ERR("HUB_FEATURE_HUB_C_OVERCURRENT not implmented.\n"); + break; + default: + return -EPIPE; + } + break; + case HUB_REQUEST_SET_FEATURE: /* set a value reported in the hub status */ + switch (setup->wValue) + { + case HUB_FEATURE_HUB_C_LOCALPOWER: + USB_LOG_ERR("HUB_FEATURE_HUB_C_LOCALPOWER not implmented.\n"); + break; + case HUB_FEATURE_HUB_C_OVERCURRENT: + USB_LOG_ERR("HUB_FEATURE_HUB_C_OVERCURRENT not implmented.\n"); + break; + default: + return -EPIPE; + } + break; + case HUB_REQUEST_GET_DESCRIPTOR: + USB_LOG_ERR("HUB_REQUEST_GET_DESCRIPTOR not implmented.\n"); + break; + case HUB_REQUEST_GET_STATUS: + USB_ASSERT(buf); + memset(buf, 0, 4); + break; + default: + break; + } + } + else if (setup->bmRequestType & USB_REQUEST_RECIPIENT_OTHER) + { + switch (setup->bRequest) + { + case HUB_REQUEST_CLEAR_FEATURE: + if (!port || port > nports) + { + return -EPIPE; + } + + portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port ) ); + switch (setup->wValue) + { + case HUB_PORT_FEATURE_ENABLE: + break; + case HUB_PORT_FEATURE_SUSPEND: + case HUB_PORT_FEATURE_C_SUSPEND: + break; + case HUB_PORT_FEATURE_POWER: + break; + case HUB_PORT_FEATURE_C_CONNECTION: + portsc |= XHCI_PORTSC_CSC; + break; + case HUB_PORT_FEATURE_C_ENABLE: + portsc |= XHCI_PORTSC_PEC; + break; + case HUB_PORT_FEATURE_C_OVER_CURREN: + break; + case HUB_PORT_FEATURE_C_RESET: + break; + default: + return -EPIPE; + } + + uint32_t pclear = portsc & XHCI_PORTSC_RW_MASK; + /* clear port status */ + writel(pclear, xhci->op + XHCI_OP_PORTSC ( port )); + + break; + case HUB_REQUEST_SET_FEATURE: + if (!port || port > nports) + { + return -EPIPE; + } + + switch (setup->wValue) + { + case HUB_PORT_FEATURE_SUSPEND: + break; + case HUB_PORT_FEATURE_POWER: + break; + case HUB_PORT_FEATURE_RESET: + ret = xhci_port_enable(xhci, port); + break; + default: + return -EPIPE; + } + break; + case HUB_REQUEST_GET_STATUS: + if (!port || port > nports) + { + return -EPIPE; + } + + portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port ) ); + status = 0; + + if (portsc & XHCI_PORTSC_CSC) + { + /* Port connection status changed */ + status |= (1 << HUB_PORT_FEATURE_C_CONNECTION); + + /* always clear all the status change bits */ + uint32_t temp = portsc & ( XHCI_PORTSC_PRESERVE | XHCI_PORTSC_CHANGE ); + writel ( temp, xhci->op + XHCI_OP_PORTSC ( port ) ); + } + + if (portsc & XHCI_PORTSC_PEC) + { + /* Port enabled status changed */ + status |= (1 << HUB_PORT_FEATURE_C_ENABLE); + } + + if (portsc & XHCI_PORTSC_OCC) + { + /* Port status changed due to over-current */ + status |= (1 << HUB_PORT_FEATURE_C_OVER_CURREN); + } + + if (portsc & XHCI_PORTSC_CCS) + { + /* Port connected */ + status |= (1 << HUB_PORT_FEATURE_CONNECTION); + } + + if (portsc & XHCI_PORTSC_PED) + { + /* Port enabled */ + status |= (1 << HUB_PORT_FEATURE_ENABLE); + + const unsigned int speed = xhci_root_speed(xhci, port); + USB_LOG_DBG("Port-%d speed = %d \r\n", port, speed); + if (speed == USB_SPEED_LOW) + { + status |= (1 << HUB_PORT_FEATURE_LOWSPEED); + } + else if (speed == USB_SPEED_HIGH) + { + status |= (1 << HUB_PORT_FEATURE_HIGHSPEED); + } + /* else is full-speed */ + } + + if (portsc & XHCI_PORTSC_OCA) + { + /* Over-current condition */ + status |= (1 << HUB_PORT_FEATURE_OVERCURRENT); + } + + if (portsc & XHCI_PORTSC_PR) + { + /* Reset is in progress */ + status |= (1 << HUB_PORT_FEATURE_RESET); + } + + if (portsc & XHCI_PORTSC_PP) + { + /* Port is not power off */ + status |= (1 << HUB_PORT_FEATURE_POWER); + } + memcpy(buf, &status, 4); + break; + default: + break; + } + } + return 0; } From eef25d3004c011e970322c4b3214f67282192b0e Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 18 Jun 2024 23:21:44 -0700 Subject: [PATCH 039/198] Modify xhci functions for USB core --- .../drivers/usb/components/port/xhci/usb_hc_xhci.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index 85813ae0f..4573a80e6 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -776,8 +776,17 @@ int xhci_usbh_roothub_control(struct usbh_bus *usb, struct usb_setup_packet *set } -int xhci_usbh_ep_pipe_reconfigure(struct usbh_bus *usb, usbh_pipe_t pipe, uint8_t dev_addr, uint8_t ep_mps, uint8_t mult){ - return 0; +int xhci_usbh_ep_pipe_reconfigure(struct usbh_bus *usb, usbh_pipe_t pipe, uint8_t dev_addr, uint8_t mtu, uint8_t speed){ + struct xhci_endpoint *ppipe = (struct xhci_endpoint *)pipe; + size_t old_mtu = ppipe->mtu; + int rc = 0; + + if (mtu != old_mtu) { + ppipe->mtu = mtu; + rc = xhci_endpoint_mtu(ppipe); + } + + return rc; } From a66824c9ad09ceb9ed61c890894c40794feab841 Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 18 Jun 2024 23:23:47 -0700 Subject: [PATCH 040/198] Modify xhci functions for USB core --- .../usb/components/port/xhci/usb_hc_xhci.c | 59 ++++++++++++++++++- 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index 4573a80e6..36b5f368c 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -791,7 +791,64 @@ int xhci_usbh_ep_pipe_reconfigure(struct usbh_bus *usb, usbh_pipe_t pipe, uint8_ int xhci_usbh_pipe_alloc(usbh_pipe_t *pipe, const struct usbh_endpoint_cfg *ep_cfg){ - return 0; + int rc = 0; + int slot_id = 0; + struct xhci_host *xhci = xhci_get_inst_of_port(ep_cfg->hport); + struct usbh_hubport *hport = ep_cfg->hport; + struct xhci_endpoint *ppipe = usb_align(XHCI_RING_SIZE, sizeof(struct xhci_endpoint)); + struct xhci_slot *slot; + + if (NULL == ppipe) { + return -ENOMEM; + } + + memset(ppipe, 0, sizeof(struct xhci_endpoint)); + + ppipe->waitsem = usb_osal_sem_create(0); + ppipe->waiter = false; + ppipe->urb = NULL; + ppipe->hport = hport; + + ppipe->address = ep_cfg->ep_addr; + ppipe->mtu = ep_cfg->ep_mps; + ppipe->interval = ep_cfg->ep_interval; + ppipe->ep_type = ep_cfg->ep_type; + ppipe->burst = 0U; + + if (ppipe->address == 0) { /* if try to allocate ctrl ep, open device first */ + USB_LOG_DBG("allocate device for port-%d \r\n", hport->port); + rc = xhci_device_open(xhci, ppipe, &slot_id); + if (rc) { + goto failed; + } + + slot = xhci->slot[slot_id]; + USB_ASSERT(slot); + rc = xhci_ctrl_endpoint_open(xhci, slot, ppipe); + if (rc) { + goto failed; + } + + rc = xhci_device_address(xhci, slot, ppipe); + if (rc) { + goto failed; + } + } else { + slot_id = hport->dev_addr; + slot = xhci->slot[slot_id]; + + rc = xhci_work_endpoint_open(xhci, slot, ppipe); + if (rc) { + goto failed; + } + } + + *pipe = (usbh_pipe_t)ppipe; + return rc; +failed: + usb_free(ppipe); + *pipe = NULL; + return rc; } From 5d240f93aeee10fc29988d92e654ac749232a85d Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 18 Jun 2024 23:30:51 -0700 Subject: [PATCH 041/198] Modify xhci functions for USB core --- .../drivers/usb/components/port/xhci/usb_hc_xhci.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index 36b5f368c..a85cac217 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -852,6 +852,14 @@ failed: } +int usbh_get_xhci_devaddr(usbh_pipe_t *pipe) +{ + struct xhci_endpoint *ppipe = (struct xhci_endpoint *)pipe; + USB_ASSERT(ppipe && (ppipe->slot)); + return ppipe->slot->id; +} + + int xhci_usbh_pipe_free(usbh_pipe_t pipe){ return 0; } From 545c240c8d19705b7b591acf6a52049b9fe7c766 Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 18 Jun 2024 23:34:39 -0700 Subject: [PATCH 042/198] Modify xhci functions for USB core --- .../usb/components/port/xhci/usb_hc_xhci.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index a85cac217..099c2bb0e 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -861,6 +861,21 @@ int usbh_get_xhci_devaddr(usbh_pipe_t *pipe) int xhci_usbh_pipe_free(usbh_pipe_t pipe){ + int ret = 0; + struct xhci_endpoint *ppipe = (struct xhci_endpoint *)pipe; + + if (!ppipe) { + return -EINVAL; + } + + struct usbh_urb *urb = ppipe->urb; + if (urb) { + usbh_kill_urb(urb); + } + + size_t flags = usb_osal_enter_critical_section(); + xhci_endpoint_close(ppipe); + usb_osal_leave_critical_section(flags); return 0; } From 7f188bff034f50126cfd44e20afbe1700e218dde Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Thu, 20 Jun 2024 17:44:51 +0800 Subject: [PATCH 043/198] Modify USB core code to decouple from xhci. --- .../drivers/usb/components/common/usb_hc.h | 9 + .../drivers/usb/components/core/usbh_core.c | 169 ++++++++++-------- .../drivers/usb/components/core/usbh_core.h | 2 +- 3 files changed, 103 insertions(+), 77 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_hc.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_hc.h index 4ab24939f..a7f09f8a3 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_hc.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_hc.h @@ -100,6 +100,14 @@ uint16_t usbh_get_frame_number(void); */ int usbh_roothub_control(struct usbh_bus *usb, struct usb_setup_packet *setup, uint8_t *buf); +/** + * @brief get device address. + * + * @param hport Hub port of USB device + * @return On success will return device address, and others indicate fail. + */ +int usbh_get_devaddr(struct usbh_hubport *hport); + /** * @brief reconfig endpoint pipe. * @@ -127,6 +135,7 @@ int usbh_pipe_alloc(usbh_pipe_t *pipe, const struct usbh_endpoint_cfg *ep_cfg); * @return On success will return 0, and others indicate fail. */ int usbh_pipe_free(usbh_pipe_t pipe); +int usbh_pipe_free_xiuos(struct usbh_hubport *hport, usbh_pipe_t pipe); /** * @brief Submit a usb transfer request to an endpoint. diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c index 52ea8b7fa..0596bd0ac 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c @@ -90,20 +90,20 @@ struct usbh_bus* usbh_get_bus_of_devname(const char *devname) /** * Get USB transaction translator * - * @v hport Hub port of USB device + * @v hport Hub port of USB device * @ret port Transaction translator port, or NULL */ struct usbh_hubport *usbh_transaction_translator ( struct usbh_hubport *hport ) { - struct usbh_hubport *parent; + struct usbh_hubport *parent; if (hport->parent->is_roothub) { return NULL; } - /* Navigate up to root hub. If we find a low-speed or - * full-speed device with a higher-speed parent hub, then that - * device's port is the transaction translator. - */ + /* Navigate up to root hub. If we find a low-speed or + * full-speed device with a higher-speed parent hub, then that + * device's port is the transaction translator. + */ for (; (parent = hport->parent->parent); hport = parent) { if ((hport->speed <= USB_SPEED_FULL) && (parent->speed > USB_SPEED_FULL)) { @@ -117,18 +117,18 @@ struct usbh_hubport *usbh_transaction_translator ( struct usbh_hubport *hport ) /** * Get USB route string * - * @v hport Hub Port of USB device - * @ret route USB route string + * @v hport Hub Port of USB device + * @ret route USB route string */ unsigned int usbh_route_string ( struct usbh_hubport *hport ) { struct usbh_hubport *parent; - unsigned int route; + unsigned int route; /* Navigate up to root hub, constructing route string as we go */ for (route = 0; (parent = hport->parent->parent); hport = parent) { route <<= 4; - route |= ( ( hport->dev_addr > 0xf ) ? - 0xf : hport->dev_addr ); + route |= ( ( hport->dev_addr > 0xf ) ? + 0xf : hport->dev_addr ); } return route; @@ -137,8 +137,8 @@ unsigned int usbh_route_string ( struct usbh_hubport *hport ) { /** * Get USB root hub port * - * @v usb USB device - * @ret port Root hub port + * @v usb USB device + * @ret port Root hub port */ struct usbh_hubport * usbh_root_hub_port ( struct usbh_hubport *hport ) { struct usbh_hubport *parent; @@ -483,13 +483,7 @@ int usbh_hport_activate_ep0(struct usbh_hubport *hport) ep0_cfg.ep_type = USB_ENDPOINT_TYPE_CONTROL; ep0_cfg.hport = hport; - if (USB_HC_XHCI == usb->usb_hc_type) { - xhci_usbh_pipe_alloc(&hport->ep0, &ep0_cfg); - } - else { - USB_LOG_WRN("invalid usb controller type %d \r\n", usb->usb_hc_type); - return -EINVAL; - } + usbh_pipe_alloc(&hport->ep0, &ep0_cfg); return 0; } @@ -504,13 +498,7 @@ int usbh_hport_deactivate_ep0(struct usbh_hubport *hport) } #endif if (hport->ep0) { - if (USB_HC_XHCI == usb->usb_hc_type) { - xhci_usbh_pipe_free(hport->ep0); - } - else { - USB_LOG_WRN("invalid usb controller type %d \r\n", usb->usb_hc_type); - return -EINVAL; - } + usbh_pipe_free_xiuos(hport, hport->ep0); } hport->ep0 = NULL; @@ -520,7 +508,6 @@ int usbh_hport_deactivate_ep0(struct usbh_hubport *hport) int usbh_hport_activate_epx(usbh_pipe_t *pipe, struct usbh_hubport *hport, struct usb_endpoint_descriptor *ep_desc) { - struct usbh_bus *usb = usbh_get_bus_of_port(hport); struct usbh_endpoint_cfg ep_cfg = { 0 }; ep_cfg.ep_addr = ep_desc->bEndpointAddress; @@ -537,13 +524,7 @@ int usbh_hport_activate_epx(usbh_pipe_t *pipe, struct usbh_hubport *hport, struc ep_cfg.ep_interval, ep_cfg.mult); - if (USB_HC_XHCI == usb->usb_hc_type) { - return xhci_usbh_pipe_alloc(pipe, &ep_cfg); - } - else { - USB_LOG_WRN("invalid usb controller type %d \r\n", usb->usb_hc_type); - return -EINVAL; - } + return usbh_pipe_alloc(pipe, &ep_cfg); } int usbh_enumerate(struct usbh_hubport *hport) @@ -567,7 +548,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wLength = 8; dev_desc = (struct usb_device_descriptor *)usb->ep0_request_buffer; - ret = usbh_control_transfer_msg(usb->usb_hc_type, hport->ep0, setup, (uint8_t *)dev_desc); + ret = usbh_control_transfer_xiuos(hport, hport->ep0, setup, (uint8_t *)dev_desc); if (ret < 0) { USB_LOG_ERR("Failed to get device descriptor,errorcode:%d\r\n", ret); goto errout; @@ -589,30 +570,12 @@ int usbh_enumerate(struct usbh_hubport *hport) /* Reconfigure EP0 with the correct maximum packet size */ usbh_ep_pipe_reconfigure(usb, hport->ep0, 0, ep_mps, 0); -#ifdef CONFIG_USBHOST_XHCI - if (USB_HC_XHCI == usb->usb_hc_type) { - extern int usbh_get_xhci_devaddr(usbh_pipe_t * pipe); - /* Assign a function address to the device connected to this port */ - dev_addr = usbh_get_xhci_devaddr(hport->ep0); - if (dev_addr < 0) { - USB_LOG_ERR("Failed to allocate devaddr,errorcode:%d\r\n", ret); - goto errout; - } - - } - else { - USB_LOG_WRN("invalid usb controller type %d \r\n", usb->usb_hc_type); - goto errout; - } - -#else /* Assign a function address to the device connected to this port */ - dev_addr = usbh_allocate_devaddr(&usb->devgen); + dev_addr = usbh_get_devaddr(hport); if (dev_addr < 0) { USB_LOG_ERR("Failed to allocate devaddr,errorcode:%d\r\n", ret); goto errout; } -#endif /* Set the USB device address */ setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_DEVICE; @@ -621,7 +584,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wIndex = 0; setup->wLength = 0; - ret = usbh_control_transfer_msg(usb->usb_hc_type, hport->ep0, setup, NULL); + ret = usbh_control_transfer_xiuos(hport, hport->ep0, setup, NULL); if (ret < 0) { USB_LOG_ERR("Failed to set devaddr,errorcode:%d\r\n", ret); goto errout; @@ -643,7 +606,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wIndex = 0; setup->wLength = USB_SIZEOF_DEVICE_DESC; - ret = usbh_control_transfer_msg(usb->usb_hc_type, hport->ep0, setup, usb->ep0_request_buffer); + ret = usbh_control_transfer_xiuos(hport, hport->ep0, setup, usb->ep0_request_buffer); if (ret < 0) { USB_LOG_ERR("Failed to get full device descriptor,errorcode:%d\r\n", ret); goto errout; @@ -662,7 +625,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wIndex = 0; setup->wLength = USB_SIZEOF_CONFIG_DESC; - ret = usbh_control_transfer_msg(usb->usb_hc_type, hport->ep0, setup, usb->ep0_request_buffer); + ret = usbh_control_transfer_xiuos(hport, hport->ep0, setup, usb->ep0_request_buffer); if (ret < 0) { USB_LOG_ERR("Failed to get config descriptor,errorcode:%d\r\n", ret); goto errout; @@ -679,7 +642,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wIndex = 0; setup->wLength = wTotalLength; - ret = usbh_control_transfer_msg(usb->usb_hc_type, hport->ep0, setup, usb->ep0_request_buffer); + ret = usbh_control_transfer_xiuos(hport, hport->ep0, setup, usb->ep0_request_buffer); if (ret < 0) { USB_LOG_ERR("Failed to get full config descriptor,errorcode:%d\r\n", ret); goto errout; @@ -706,7 +669,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wIndex = 0x0409; setup->wLength = 255; - ret = usbh_control_transfer_msg(usb->usb_hc_type, hport->ep0, setup, usb->ep0_request_buffer); + ret = usbh_control_transfer_xiuos(hport, hport->ep0, setup, usb->ep0_request_buffer); if (ret < 0) { USB_LOG_ERR("Failed to get Manufacturer string,errorcode:%d\r\n", ret); goto errout; @@ -721,7 +684,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wIndex = 0x0409; setup->wLength = 255; - ret = usbh_control_transfer_msg(usb->usb_hc_type, hport->ep0, setup, usb->ep0_request_buffer); + ret = usbh_control_transfer_xiuos(hport, hport->ep0, setup, usb->ep0_request_buffer); if (ret < 0) { USB_LOG_ERR("Failed to get get Product string,errorcode:%d\r\n", ret); goto errout; @@ -736,7 +699,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wIndex = 0x0409; setup->wLength = 255; - ret = usbh_control_transfer_msg(usb->usb_hc_type, hport->ep0, setup, usb->ep0_request_buffer); + ret = usbh_control_transfer_xiuos(hport, hport->ep0, setup, usb->ep0_request_buffer); if (ret < 0) { USB_LOG_ERR("Failed to get get SerialNumber string,errorcode:%d\r\n", ret); goto errout; @@ -751,7 +714,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wIndex = 0; setup->wLength = 0; - ret = usbh_control_transfer_msg(usb->usb_hc_type, hport->ep0, setup, NULL); + ret = usbh_control_transfer_xiuos(hport, hport->ep0, setup, NULL); if (ret < 0) { USB_LOG_ERR("Failed to set configuration,errorcode:%d\r\n", ret); goto errout; @@ -892,27 +855,22 @@ int usbh_control_transfer(usbh_pipe_t pipe, struct usb_setup_packet *setup, uint return ret; } -int usbh_control_transfer_msg(uint8_t hc_type, usbh_pipe_t pipe, struct usb_setup_packet *setup, uint8_t *buffer) +int usbh_control_transfer_xiuos(struct usbh_hubport *hport, usbh_pipe_t pipe, struct usb_setup_packet *setup, uint8_t *buffer) { + struct usbh_bus *usb = usbh_get_bus_of_port(hport); struct usbh_urb *urb; int ret; urb = usb_malloc(sizeof(struct usbh_urb)); memset(urb, 0, sizeof(struct usbh_urb)); + urb->usb_hc_type = usb->usb_hc_type; usbh_control_urb_fill(urb, pipe, setup, buffer, setup->wLength, CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT, NULL, NULL); - if (USB_HC_XHCI == hc_type) { - ret = xhci_usbh_submit_urb(urb); - if (ret == 0) { - ret = urb->actual_length; - } + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; } - else { - USB_LOG_WRN("invalid usb controller type %d \r\n", hc_type); - ret = -EINVAL; - } - usb_free(urb); return ret; } @@ -1029,7 +987,18 @@ int usbh_ep_pipe_reconfigure(struct usbh_bus *usb, usbh_pipe_t pipe, uint8_t dev int usbh_pipe_alloc(usbh_pipe_t *pipe, const struct usbh_endpoint_cfg *ep_cfg) { - return 0; + struct usbh_bus *usb = usbh_get_bus_of_port(ep_cfg->hport); + int rc = 0; + + if (USB_HC_XHCI == usb->usb_hc_type) { + rc = xhci_usbh_pipe_alloc(pipe, ep_cfg); + } + else { + USB_LOG_WRN("invalid usb controller type %d \r\n", usb->usb_hc_type); + return -EINVAL; + } + + return rc; } int usbh_get_xhci_devaddr(usbh_pipe_t *pipe) @@ -1037,14 +1006,62 @@ int usbh_get_xhci_devaddr(usbh_pipe_t *pipe) return 0; } +int usbh_get_devaddr(struct usbh_hubport *hport) +{ + int dev_addr; + struct usbh_bus *usb = usbh_get_bus_of_port(hport); + +#ifdef CONFIG_USBHOST_XHCI + if (USB_HC_XHCI == usb->usb_hc_type) { + /* Assign a function address to the device connected to this port */ + dev_addr = usbh_get_xhci_devaddr(hport->ep0); + } + else { + USB_LOG_WRN("invalid usb controller type %d \r\n", usb->usb_hc_type); + return -EINVAL; + } +#else + /* Assign a function address to the device connected to this port */ + dev_addr = usbh_allocate_devaddr(&usb->devgen); +#endif + + return dev_addr; +} + int usbh_pipe_free(usbh_pipe_t pipe) { return 0; } +int usbh_pipe_free_xiuos(struct usbh_hubport *hport, usbh_pipe_t pipe) +{ + int ret = 0; + struct usbh_bus *usb = usbh_get_bus_of_port(hport); + + if (USB_HC_XHCI == usb->usb_hc_type) { + ret = xhci_usbh_pipe_free(hport->ep0); + } + else { + USB_LOG_WRN("invalid usb controller type %d \r\n", usb->usb_hc_type); + return -EINVAL; + } + + return ret; +} + int usbh_submit_urb(struct usbh_urb *urb) { - return 0; + int ret; + + if (USB_HC_XHCI == urb->usb_hc_type) { + ret = xhci_usbh_submit_urb(urb); + } + else { + USB_LOG_WRN("invalid usb controller type %d \r\n", urb->usb_hc_type); + ret = -EINVAL; + } + + return ret; } int usbh_kill_urb(struct usbh_urb *urb) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h index 6022c7ef2..f7019f322 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h @@ -215,7 +215,7 @@ int usbh_hport_activate_epx(usbh_pipe_t *pipe, struct usbh_hubport *hport, struc */ int usbh_control_transfer(usbh_pipe_t pipe, struct usb_setup_packet *setup, uint8_t *buffer); -int usbh_control_transfer_msg(uint8_t hc_type, usbh_pipe_t pipe, struct usb_setup_packet *setup, uint8_t *buffer); +int usbh_control_transfer_xiuos(struct usbh_hubport *hport, usbh_pipe_t pipe, struct usb_setup_packet *setup, uint8_t *buffer); struct usbh_devaddr_map { /** From 39620c574ee23bcfc175362f72acb78152443bbf Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Mon, 24 Jun 2024 14:10:54 +0800 Subject: [PATCH 044/198] Modifying functions in usb core is related to xhci. --- .../drivers/usb/components/core/usbh_core.c | 83 +++++++++++++++++-- .../drivers/usb/components/core/usbh_core.h | 66 ++++++++++++++- 2 files changed, 141 insertions(+), 8 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c index 0596bd0ac..369ab2890 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c @@ -19,6 +19,11 @@ Modification: Modify function usbh_enumerate usbh_hport_activate_ep0 usbh_hport_ 2. Date: 2024-06-19 Author: AIIT XUOS Lab Modification: Extract the functions of the host controller to core. + +3. Date: 2024-06-24 +Author: AIIT XUOS Lab +Modification: Modifying functions in usb core is related to xhci. + *************************************************/ #include "usbh_core.h" @@ -857,15 +862,13 @@ int usbh_control_transfer(usbh_pipe_t pipe, struct usb_setup_packet *setup, uint int usbh_control_transfer_xiuos(struct usbh_hubport *hport, usbh_pipe_t pipe, struct usb_setup_packet *setup, uint8_t *buffer) { - struct usbh_bus *usb = usbh_get_bus_of_port(hport); struct usbh_urb *urb; int ret; urb = usb_malloc(sizeof(struct usbh_urb)); memset(urb, 0, sizeof(struct usbh_urb)); - urb->usb_hc_type = usb->usb_hc_type; - usbh_control_urb_fill(urb, pipe, setup, buffer, setup->wLength, CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT, NULL, NULL); + usbh_control_urb_fill_xiuos(urb, hport, pipe, setup, buffer, setup->wLength, CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT, NULL, NULL); ret = usbh_submit_urb(urb); if (ret == 0) { @@ -972,17 +975,64 @@ int lsusb(int argc, char **argv) /* xhci hardware init */ int usb_hc_init(uint32_t id) { - return 0; + int ret = 0; + struct usbh_bus* usb = usbh_get_bus_of_index(id); + + if (USB_HC_XHCI == usb->usb_hc_type) { + ret = xhci_usb_hc_init(usb->id); + } + else { + USB_LOG_WRN("invalid usb controller type %d \r\n", usb->usb_hc_type); + return -EINVAL; + } + + return ret; } int usbh_roothub_control(struct usbh_bus *usb, struct usb_setup_packet *setup, uint8_t *buf) { - return 0; + int ret = 0; + + if (USB_HC_XHCI == usb->usb_hc_type) { + ret = xhci_usbh_roothub_control(usb, setup, buf); + } + else { + USB_LOG_WRN("invalid usb controller type %d \r\n", usb->usb_hc_type); + return -EINVAL; + } + + return ret; +} + +uint8_t usbh_get_port_speed(struct usbh_hub *hub, const uint8_t port) +{ + uint8_t speed; + struct usbh_bus *usb = hub->usb; + + if (USB_HC_XHCI == usb->usb_hc_type) { + speed = xhci_usbh_get_port_speed(hub, port + 1); + } + else { + USB_LOG_WRN("invalid usb controller type %d \r\n", usb->usb_hc_type); + return -EINVAL; + } + + return speed; } int usbh_ep_pipe_reconfigure(struct usbh_bus *usb, usbh_pipe_t pipe, uint8_t dev_addr, uint8_t mtu, uint8_t speed) { - return 0; + int rc = 0; + + if (USB_HC_XHCI == usb->usb_hc_type) { + rc = xhci_usbh_ep_pipe_reconfigure(usb, pipe, dev_addr, mtu, speed); + } + else { + USB_LOG_WRN("invalid usb controller type %d \r\n", usb->usb_hc_type); + return -EINVAL; + } + + return rc; } int usbh_pipe_alloc(usbh_pipe_t *pipe, const struct usbh_endpoint_cfg *ep_cfg) @@ -1066,10 +1116,29 @@ int usbh_submit_urb(struct usbh_urb *urb) int usbh_kill_urb(struct usbh_urb *urb) { - return 0; + int ret; + + if (USB_HC_XHCI == urb->usb_hc_type) { + ret = xhci_usbh_kill_urb(urb); + } + else { + USB_LOG_WRN("invalid usb controller type %d \r\n", urb->usb_hc_type); + ret = -EINVAL; + } + + return ret; } void USBH_IRQHandler(void *param) { + USB_ASSERT(param); + struct usbh_bus *bus = (struct usbh_bus *)param; + + if (USB_HC_XHCI == bus->usb_hc_type) { + XHCI_USBH_IRQHandler(param); + } + else { + USB_LOG_WRN("invalid usb controller type %d \r\n", bus->usb_hc_type); + } } diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h index f7019f322..1637d1d2c 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h @@ -13,7 +13,11 @@ Others: CherryUSB third-party/cherryusb/core/usbh_core.h for references History: 1. Date: 2024-06-18 Author: AIIT XUOS Lab -Modification: new parameter usb_hc_type for host controller type. +Modification: New parameter usb_hc_type for host controller type. + +2. Date: 2024-06-24 +Author: AIIT XUOS Lab +Modification: Refactor the function that fills urb with usb_hc_type. *************************************************/ @@ -85,6 +89,27 @@ static inline void usbh_control_urb_fill(struct usbh_urb *urb, urb->arg = arg; } +static inline void usbh_control_urb_fill_xiuos(struct usbh_urb *urb, + struct usbh_hubport *hport, + usbh_pipe_t pipe, + struct usb_setup_packet *setup, + uint8_t *transfer_buffer, + uint32_t transfer_buffer_length, + uint32_t timeout, + usbh_complete_callback_t complete, + void *arg) +{ + struct usbh_bus *usb = usbh_get_bus_of_port(hport); + urb->usb_hc_type = usb->usb_hc_type; + urb->pipe = pipe; + urb->setup = setup; + urb->transfer_buffer = transfer_buffer; + urb->transfer_buffer_length = transfer_buffer_length; + urb->timeout = timeout; + urb->complete = complete; + urb->arg = arg; +} + static inline void usbh_bulk_urb_fill(struct usbh_urb *urb, usbh_pipe_t pipe, uint8_t *transfer_buffer, @@ -102,6 +127,26 @@ static inline void usbh_bulk_urb_fill(struct usbh_urb *urb, urb->arg = arg; } +static inline void usbh_bulk_urb_fill_xiuos(struct usbh_urb *urb, + struct usbh_hubport *hport, + usbh_pipe_t pipe, + uint8_t *transfer_buffer, + uint32_t transfer_buffer_length, + uint32_t timeout, + usbh_complete_callback_t complete, + void *arg) +{ + struct usbh_bus *usb = usbh_get_bus_of_port(hport); + urb->usb_hc_type = usb->usb_hc_type; + urb->pipe = pipe; + urb->setup = NULL; + urb->transfer_buffer = transfer_buffer; + urb->transfer_buffer_length = transfer_buffer_length; + urb->timeout = timeout; + urb->complete = complete; + urb->arg = arg; +} + static inline void usbh_int_urb_fill(struct usbh_urb *urb, usbh_pipe_t pipe, uint8_t *transfer_buffer, @@ -119,6 +164,25 @@ static inline void usbh_int_urb_fill(struct usbh_urb *urb, urb->arg = arg; } +static inline void usbh_int_urb_fill_xiuos(struct usbh_urb *urb, + struct usbh_hubport *hport, + usbh_pipe_t pipe, + uint8_t *transfer_buffer, + uint32_t transfer_buffer_length, + uint32_t timeout, + usbh_complete_callback_t complete, + void *arg) +{ + struct usbh_bus *usb = usbh_get_bus_of_port(hport); + urb->usb_hc_type = usb->usb_hc_type; + urb->pipe = pipe; + urb->setup = NULL; + urb->transfer_buffer = transfer_buffer; + urb->transfer_buffer_length = transfer_buffer_length; + urb->timeout = timeout; + urb->complete = complete; + urb->arg = arg; +} struct usbh_class_info { uint8_t match_flags; /* Used for product specific matches; range is inclusive */ uint8_t class; /* Base device class code */ From 56b8a29888638ea6d4dd0b5981eed7d9de59b86d Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Mon, 24 Jun 2024 14:15:33 +0800 Subject: [PATCH 045/198] Modifying functions in usb core is related to xhci. --- .../services/drivers/usb/components/common/usb_hc.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_hc.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_hc.h index a7f09f8a3..6791945a7 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_hc.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_hc.h @@ -108,6 +108,15 @@ int usbh_roothub_control(struct usbh_bus *usb, struct usb_setup_packet *setup, u */ int usbh_get_devaddr(struct usbh_hubport *hport); +/** + * @brief get port speed. + * + * @param hport Hub of USB device + * @param port Port index + * @return On success will return speed, and others indicate fail. + */ +uint8_t usbh_get_port_speed(struct usbh_hub *hub, const uint8_t port); + /** * @brief reconfig endpoint pipe. * From dd55f8d73131170af0141a9be32bb93ccc1dd64b Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Mon, 24 Jun 2024 14:52:48 +0800 Subject: [PATCH 046/198] Modifying functions in usb core is related to xhci. --- .../drivers/usb/components/common/usb_hc.h | 1 + .../drivers/usb/components/core/usbh_core.h | 121 +++++++++--------- 2 files changed, 62 insertions(+), 60 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_hc.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_hc.h index 6791945a7..c7c830b55 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_hc.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_hc.h @@ -28,6 +28,7 @@ typedef void (*usbh_complete_callback_t)(void *arg, int nbytes); typedef void *usbh_pipe_t; struct usbh_bus; +struct usbh_hub; /** * @brief USB Endpoint Configuration. diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h index 1637d1d2c..e31185baa 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h @@ -89,27 +89,6 @@ static inline void usbh_control_urb_fill(struct usbh_urb *urb, urb->arg = arg; } -static inline void usbh_control_urb_fill_xiuos(struct usbh_urb *urb, - struct usbh_hubport *hport, - usbh_pipe_t pipe, - struct usb_setup_packet *setup, - uint8_t *transfer_buffer, - uint32_t transfer_buffer_length, - uint32_t timeout, - usbh_complete_callback_t complete, - void *arg) -{ - struct usbh_bus *usb = usbh_get_bus_of_port(hport); - urb->usb_hc_type = usb->usb_hc_type; - urb->pipe = pipe; - urb->setup = setup; - urb->transfer_buffer = transfer_buffer; - urb->transfer_buffer_length = transfer_buffer_length; - urb->timeout = timeout; - urb->complete = complete; - urb->arg = arg; -} - static inline void usbh_bulk_urb_fill(struct usbh_urb *urb, usbh_pipe_t pipe, uint8_t *transfer_buffer, @@ -127,26 +106,6 @@ static inline void usbh_bulk_urb_fill(struct usbh_urb *urb, urb->arg = arg; } -static inline void usbh_bulk_urb_fill_xiuos(struct usbh_urb *urb, - struct usbh_hubport *hport, - usbh_pipe_t pipe, - uint8_t *transfer_buffer, - uint32_t transfer_buffer_length, - uint32_t timeout, - usbh_complete_callback_t complete, - void *arg) -{ - struct usbh_bus *usb = usbh_get_bus_of_port(hport); - urb->usb_hc_type = usb->usb_hc_type; - urb->pipe = pipe; - urb->setup = NULL; - urb->transfer_buffer = transfer_buffer; - urb->transfer_buffer_length = transfer_buffer_length; - urb->timeout = timeout; - urb->complete = complete; - urb->arg = arg; -} - static inline void usbh_int_urb_fill(struct usbh_urb *urb, usbh_pipe_t pipe, uint8_t *transfer_buffer, @@ -164,25 +123,6 @@ static inline void usbh_int_urb_fill(struct usbh_urb *urb, urb->arg = arg; } -static inline void usbh_int_urb_fill_xiuos(struct usbh_urb *urb, - struct usbh_hubport *hport, - usbh_pipe_t pipe, - uint8_t *transfer_buffer, - uint32_t transfer_buffer_length, - uint32_t timeout, - usbh_complete_callback_t complete, - void *arg) -{ - struct usbh_bus *usb = usbh_get_bus_of_port(hport); - urb->usb_hc_type = usb->usb_hc_type; - urb->pipe = pipe; - urb->setup = NULL; - urb->transfer_buffer = transfer_buffer; - urb->transfer_buffer_length = transfer_buffer_length; - urb->timeout = timeout; - urb->complete = complete; - urb->arg = arg; -} struct usbh_class_info { uint8_t match_flags; /* Used for product specific matches; range is inclusive */ uint8_t class; /* Base device class code */ @@ -355,6 +295,67 @@ struct usbh_bus* usbh_get_bus_of_index(uint8_t usb); */ struct usbh_hubport * usbh_root_hub_port ( struct usbh_hubport *hport ); +static inline void usbh_control_urb_fill_xiuos(struct usbh_urb *urb, + struct usbh_hubport *hport, + usbh_pipe_t pipe, + struct usb_setup_packet *setup, + uint8_t *transfer_buffer, + uint32_t transfer_buffer_length, + uint32_t timeout, + usbh_complete_callback_t complete, + void *arg) +{ + struct usbh_bus *usb = usbh_get_bus_of_port(hport); + urb->usb_hc_type = usb->usb_hc_type; + urb->pipe = pipe; + urb->setup = setup; + urb->transfer_buffer = transfer_buffer; + urb->transfer_buffer_length = transfer_buffer_length; + urb->timeout = timeout; + urb->complete = complete; + urb->arg = arg; +} + +static inline void usbh_bulk_urb_fill_xiuos(struct usbh_urb *urb, + struct usbh_hubport *hport, + usbh_pipe_t pipe, + uint8_t *transfer_buffer, + uint32_t transfer_buffer_length, + uint32_t timeout, + usbh_complete_callback_t complete, + void *arg) +{ + struct usbh_bus *usb = usbh_get_bus_of_port(hport); + urb->usb_hc_type = usb->usb_hc_type; + urb->pipe = pipe; + urb->setup = NULL; + urb->transfer_buffer = transfer_buffer; + urb->transfer_buffer_length = transfer_buffer_length; + urb->timeout = timeout; + urb->complete = complete; + urb->arg = arg; +} + +static inline void usbh_int_urb_fill_xiuos(struct usbh_urb *urb, + struct usbh_hubport *hport, + usbh_pipe_t pipe, + uint8_t *transfer_buffer, + uint32_t transfer_buffer_length, + uint32_t timeout, + usbh_complete_callback_t complete, + void *arg) +{ + struct usbh_bus *usb = usbh_get_bus_of_port(hport); + urb->usb_hc_type = usb->usb_hc_type; + urb->pipe = pipe; + urb->setup = NULL; + urb->transfer_buffer = transfer_buffer; + urb->transfer_buffer_length = transfer_buffer_length; + urb->timeout = timeout; + urb->complete = complete; + urb->arg = arg; +} + int usbh_initialize(uint32_t id, struct usbh_bus *usb); struct usbh_hubport *usbh_find_hubport(uint32_t id, uint8_t dev_addr); void *usbh_find_class_instance(const char *devname); From aa68affc4674e2870fd5623ae41f8637e7ec35f3 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Mon, 24 Jun 2024 15:08:02 +0800 Subject: [PATCH 047/198] rewrite xhci function usbh_get_port_speed --- .../drivers/usb/components/port/xhci/usb_hc_xhci.c | 10 ++++++++++ .../drivers/usb/components/port/xhci/usb_hc_xhci.h | 9 +++++++++ 2 files changed, 19 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index 099c2bb0e..cf81dd396 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -34,6 +34,10 @@ History: 1. Date: 2024-06-17 Author: AIIT XUOS Lab Modification: rewrite xhci functions to dock with USB core layer, so that the USB core can easily expand to other USB IP. + +2. Date: 2024-06-24 +Author: AIIT XUOS Lab +Modification: rewrite xhci function usbh_get_port_speed to dock with USB core layer. *************************************************/ #include "usb_hc_xhci.h" #include "usbh_hub.h" @@ -775,6 +779,12 @@ int xhci_usbh_roothub_control(struct usbh_bus *usb, struct usb_setup_packet *set return 0; } +// TODO: +uint8_t xhci_usbh_get_port_speed(struct usbh_hub *hub, const uint8_t port) +{ + return 0; +} + int xhci_usbh_ep_pipe_reconfigure(struct usbh_bus *usb, usbh_pipe_t pipe, uint8_t dev_addr, uint8_t mtu, uint8_t speed){ struct xhci_endpoint *ppipe = (struct xhci_endpoint *)pipe; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h index a71e7fc4f..1af816dfe 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h @@ -68,6 +68,15 @@ uint16_t xhci_usbh_get_frame_number(void); */ int xhci_usbh_roothub_control(struct usbh_bus *usb, struct usb_setup_packet *setup, uint8_t *buf); +/** + * @brief get port speed. + * + * @param hport Hub of USB device. + * @param port Port index. + * @return On success will return speed, and others indicate fail. + */ +uint8_t xhci_usbh_get_port_speed(struct usbh_hub *hub, const uint8_t port); + /** * @brief reconfig endpoint pipe. * From 513b74b8456d0fe9d78c180bc921fc63e1b82530 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Mon, 24 Jun 2024 15:31:57 +0800 Subject: [PATCH 048/198] Modify usbh_hub.c according to freertos source code. --- .../usb/components/class/hub/usbh_hub.c | 743 +++++++++++++++++- 1 file changed, 741 insertions(+), 2 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c index cbf69aee1..98e59adc6 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c @@ -3,6 +3,745 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#include "usbh_hub.h" -#include "usb_def.h" +/************************************************* +File name: usbh_hub.c +Description: adopt cherry USB to XiZi AIOT. +Others: CherryUSB third-party/cherryusb/class/hub/usbh_hub.c for references + https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/blob/master/third-party/cherryusb/class/hub/usbh_hub.c +*************************************************/ +#include "usbh_hub.h" + +#define DEV_FORMAT "/usb%d/hub%d" + +#define HUB_DEBOUNCE_TIMEOUT 1500 +#define HUB_DEBOUNCE_STEP 25 +#define HUB_DEBOUNCE_STABLE 100 +#define DELAY_TIME_AFTER_RESET 200 + +#define EXTHUB_FIRST_INDEX 2 + +#if CONFIG_USBHOST_MAX_EXTHUBS > 0 +static uint32_t g_devinuse = 0; +#endif + +extern int usbh_hport_activate_ep0(struct usbh_hubport *hport); +extern int usbh_hport_deactivate_ep0(struct usbh_hubport *hport); +extern int usbh_enumerate(struct usbh_hubport *hport); +static void usbh_hub_thread_wakeup(struct usbh_hub *hub); + +static const char *speed_table[] = { "error-speed", "low-speed", "full-speed", "high-speed", "wireless-speed", "super-speed", "superplus-speed" }; + +struct usbh_hubport *usbh_get_roothub_port (struct usbh_bus *bus, unsigned int address) +{ + return &(bus->roothub.child[ address - 1 ]); +} + +#if CONFIG_USBHOST_MAX_EXTHUBS > 0 +static int usbh_hub_devno_alloc(void) +{ + int devno; + + for (devno = EXTHUB_FIRST_INDEX; devno < 32; devno++) { + uint32_t bitno = 1 << devno; + if ((g_devinuse & bitno) == 0) { + g_devinuse |= bitno; + return devno; + } + } + + return -EMFILE; +} + +static void usbh_hub_devno_free(uint8_t devno) +{ + if (devno >= EXTHUB_FIRST_INDEX && devno < 32) { + g_devinuse &= ~(1 << devno); + } +} +#endif + +static void usbh_hub_register(struct usbh_hub *hub) +{ + struct usbh_bus *usb = hub->usb; + usb_slist_add_tail(&usb->hub_class_head, &hub->list); +} + +#if CONFIG_USBHOST_MAX_EXTHUBS > 0 +static void usbh_hub_unregister(struct usbh_hub *hub) +{ + struct usbh_bus *usb = hub->usb; + usb_slist_remove(&usb->hub_class_head, &hub->list); +} + +static int _usbh_hub_get_hub_descriptor(struct usbh_hub *hub, uint8_t *buffer) +{ + struct usb_setup_packet *setup; + int ret; + + setup = hub->parent->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; + + /* TODO: hub descriptor has some difference between USB 2.0 and USB 3.x, + and we havn't handle the difference here */ + if ((hub->parent->speed == USB_SPEED_SUPER) || + (hub->parent->speed == USB_SPEED_SUPER_PLUS)) { + setup->wValue = HUB_DESCRIPTOR_TYPE_HUB3 << 8; + } else { + setup->wValue = HUB_DESCRIPTOR_TYPE_HUB << 8; + } + + setup->wIndex = 0; + setup->wLength = USB_SIZEOF_HUB_DESC; + + ret = usbh_control_transfer(hub->parent->ep0, setup, hub->g_hub_buf); + if (ret < 0) { + return ret; + } + memcpy(buffer, hub->g_hub_buf, USB_SIZEOF_HUB_DESC); + return ret; +} + +static int _usbh_hub_get_status(struct usbh_hub *hub, uint8_t *buffer) +{ + struct usb_setup_packet *setup; + int ret; + + setup = hub->parent->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = HUB_REQUEST_GET_STATUS; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = 2; + + ret = usbh_control_transfer(hub->parent->ep0, setup, hub->g_hub_buf); + if (ret < 0) { + return ret; + } + memcpy(buffer, hub->g_hub_buf, 2); + return ret; +} +#endif + +static int _usbh_hub_get_portstatus(struct usbh_hub *hub, uint8_t port, struct hub_port_status *port_status) +{ + struct usb_setup_packet *setup; + int ret; + + setup = hub->parent->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_OTHER; + setup->bRequest = HUB_REQUEST_GET_STATUS; + setup->wValue = 0; + setup->wIndex = port; + setup->wLength = 4; + + ret = usbh_control_transfer(hub->parent->ep0, setup, hub->g_hub_buf); + if (ret < 0) { + return ret; + } + memcpy(port_status, hub->g_hub_buf, 4); + return ret; +} + +static int _usbh_hub_set_feature(struct usbh_hub *hub, uint8_t port, uint8_t feature) +{ + struct usb_setup_packet *setup; + + setup = hub->parent->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_OTHER; + setup->bRequest = HUB_REQUEST_SET_FEATURE; + setup->wValue = feature; + setup->wIndex = port; + setup->wLength = 0; + + return usbh_control_transfer(hub->parent->ep0, setup, NULL); +} + +static int _usbh_hub_clear_feature(struct usbh_hub *hub, uint8_t port, uint8_t feature) +{ + struct usb_setup_packet *setup; + + setup = hub->parent->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_OTHER; + setup->bRequest = HUB_REQUEST_CLEAR_FEATURE; + setup->wValue = feature; + setup->wIndex = port; + setup->wLength = 0; + + return usbh_control_transfer(hub->parent->ep0, setup, NULL); +} + +static int _usbh_hub_set_depth(struct usbh_hub *hub, uint16_t depth) +{ + struct usb_setup_packet *setup; + + setup = hub->parent->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = HUB_REQUEST_SET_HUB_DEPTH; + setup->wValue = depth; + setup->wIndex = 0; + setup->wLength = 0; + + return usbh_control_transfer(hub->parent->ep0, setup, NULL); +} + +#if CONFIG_USBHOST_MAX_EXTHUBS > 0 +static int parse_hub_descriptor(struct usb_hub_descriptor *desc, uint16_t length) +{ + if (desc->bLength != USB_SIZEOF_HUB_DESC) { + USB_LOG_ERR("invalid device bLength 0x%02x\r\n", desc->bLength); + return -1; + } else if (desc->bDescriptorType != HUB_DESCRIPTOR_TYPE_HUB) { + USB_LOG_ERR("unexpected descriptor 0x%02x\r\n", desc->bDescriptorType); + return -2; + } else { + USB_LOG_RAW("Hub Descriptor:\r\n"); + USB_LOG_RAW("bLength: 0x%02x \r\n", desc->bLength); + USB_LOG_RAW("bDescriptorType: 0x%02x \r\n", desc->bDescriptorType); + USB_LOG_RAW("bNbrPorts: 0x%02x \r\n", desc->bNbrPorts); + USB_LOG_RAW("wHubCharacteristics: 0x%04x \r\n", desc->wHubCharacteristics); + USB_LOG_RAW("bPwrOn2PwrGood: 0x%02x \r\n", desc->bPwrOn2PwrGood); + USB_LOG_RAW("bHubContrCurrent: 0x%02x \r\n", desc->bHubContrCurrent); + USB_LOG_RAW("DeviceRemovable: 0x%02x \r\n", desc->DeviceRemovable); + USB_LOG_RAW("PortPwrCtrlMask: 0x%02x \r\n", desc->PortPwrCtrlMask); + } + return 0; +} +#endif + +static int usbh_hub_get_portstatus(struct usbh_hub *hub, uint8_t port, struct hub_port_status *port_status) +{ + struct usb_setup_packet roothub_setup; + struct usb_setup_packet *setup; + + if (hub->is_roothub) { + setup = &roothub_setup; + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_OTHER; + setup->bRequest = HUB_REQUEST_GET_STATUS; + setup->wValue = 0; + setup->wIndex = port; + setup->wLength = 4; + return usbh_roothub_control(hub->usb, &roothub_setup, (uint8_t *)port_status); + } else { + return _usbh_hub_get_portstatus(hub, port, port_status); + } +} + +static int usbh_hub_set_feature(struct usbh_hub *hub, uint8_t port, uint8_t feature) +{ + struct usb_setup_packet roothub_setup; + struct usb_setup_packet *setup; + + if (hub->is_roothub) { + setup = &roothub_setup; + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_OTHER; + setup->bRequest = HUB_REQUEST_SET_FEATURE; + setup->wValue = feature; + setup->wIndex = port; + setup->wLength = 0; + return usbh_roothub_control(hub->usb, setup, NULL); + } else { + return _usbh_hub_set_feature(hub, port, feature); + } +} + +static int usbh_hub_clear_feature(struct usbh_hub *hub, uint8_t port, uint8_t feature) +{ + struct usb_setup_packet roothub_setup; + struct usb_setup_packet *setup; + + if (hub->is_roothub) { + setup = &roothub_setup; + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_OTHER; + setup->bRequest = HUB_REQUEST_CLEAR_FEATURE; + setup->wValue = feature; + setup->wIndex = port; + setup->wLength = 0; + return usbh_roothub_control(hub->usb, setup, NULL); + } else { + return _usbh_hub_clear_feature(hub, port, feature); + } +} + +static int usbh_hub_set_depth(struct usbh_hub *hub, uint16_t depth) +{ + struct usb_setup_packet roothub_setup; + struct usb_setup_packet *setup; + + if (hub->is_roothub) { + setup = &roothub_setup; + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = HUB_REQUEST_SET_HUB_DEPTH; + setup->wValue = depth; + setup->wIndex = 0; + setup->wLength = 0; + return usbh_roothub_control(hub->usb, setup, NULL); + } else { + return _usbh_hub_set_depth(hub, depth); + } +} + +#if CONFIG_USBHOST_MAX_EXTHUBS > 0 +static void hub_int_complete_callback(void *arg, int nbytes) +{ + struct usbh_hub *hub = (struct usbh_hub *)arg; + + if (nbytes > 0) { + usbh_hub_thread_wakeup(hub); + } +} + +static int usbh_hub_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + struct hub_port_status port_status; + struct usbh_bus *usb = usbh_get_bus_of_port(hport); + int ret; + int index; + + index = usbh_hub_devno_alloc(); + if (index > (CONFIG_USBHOST_MAX_EXTHUBS + EXTHUB_FIRST_INDEX - 1)) { + USB_LOG_ERR("No memory to alloc hub class\r\n"); + usbh_hub_devno_free(index); + return -ENOMEM; + } + + struct usbh_hub *hub = &(usb->exthub[index - EXTHUB_FIRST_INDEX]); + + memset(hub, 0, sizeof(struct usbh_hub)); + hub->hub_addr = hport->dev_addr; + hub->parent = hport; + hub->index = index; + + hport->config.intf[intf].priv = hub; + + ret = _usbh_hub_get_hub_descriptor(hub, (uint8_t *)&hub->hub_desc); + if (ret < 0) { + return ret; + } + + parse_hub_descriptor(&hub->hub_desc, USB_SIZEOF_HUB_DESC); + + for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + hub->child[port].port = port + 1; + hub->child[port].parent = hub; + } + + ep_desc = &hport->config.intf[intf].altsetting[0].ep[0].ep_desc; + if (ep_desc->bEndpointAddress & 0x80) { + usbh_hport_activate_epx(&hub->intin, hport, ep_desc); + } else { + return -1; + } + + if (hport->speed == USB_SPEED_SUPER) { + uint16_t depth = 0; + struct usbh_hubport *parent = hport->parent->parent; + while (parent) { + depth++; + parent = parent->parent->parent; + } + + ret = usbh_hub_set_depth(hub, depth); + if (ret < 0) { + return ret; + } + } + + for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + ret = usbh_hub_set_feature(hub, port + 1, HUB_PORT_FEATURE_POWER); + if (ret < 0) { + return ret; + } + } + + for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + ret = usbh_hub_get_portstatus(hub, port + 1, &port_status); + USB_LOG_INFO("port %u, status:0x%02x, change:0x%02x\r\n", port + 1, port_status.wPortStatus, port_status.wPortChange); + if (ret < 0) { + return ret; + } + } + + hub->ports = hub->hub_desc.bNbrPorts; + hub->connected = true; + hub->usb = usb; + snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, usb->id, hub->index); + usbh_hub_register(hub); + USB_LOG_RAW("Register HUB Class:%s for USB-%d\r\n", hport->config.intf[intf].devname, usb->id); + + hub->int_buffer = hub->g_hub_intbuf[hub->index - 1]; + usbh_int_urb_fill(&hub->intin_urb, hub->intin, hub->int_buffer, 1, 0, hub_int_complete_callback, hub); + usbh_submit_urb(&hub->intin_urb); + return 0; +} + +static int usbh_hub_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usbh_hubport *child; + int ret = 0; + + struct usbh_hub *hub = (struct usbh_hub *)hport->config.intf[intf].priv; + + if (hub) { + usbh_hub_devno_free(hub->index); + + if (hub->intin) { + usbh_pipe_free(hub->intin); + } + + for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + child = &hub->child[port]; + usbh_hport_deactivate_ep0(child); + for (uint8_t i = 0; i < child->config.config_desc.bNumInterfaces; i++) { + if (child->config.intf[i].class_driver && child->config.intf[i].class_driver->disconnect) { + CLASS_DISCONNECT(child, i); + } + } + + child->config.config_desc.bNumInterfaces = 0; + child->parent = NULL; + } + + usbh_hub_unregister(hub); + memset(hub, 0, sizeof(struct usbh_hub)); + + if (hport->config.intf[intf].devname[0] != '\0') + USB_LOG_RAW("Unregister HUB Class:%s\r\n", hport->config.intf[intf].devname); + } + return ret; +} +#endif + +static void usbh_hubport_release(struct usbh_hubport *child) +{ + if (child->connected) { + child->connected = false; + usbh_hport_deactivate_ep0(child); + for (uint8_t i = 0; i < child->config.config_desc.bNumInterfaces; i++) { + if (child->config.intf[i].class_driver && child->config.intf[i].class_driver->disconnect) { + CLASS_DISCONNECT(child, i); + } + } + child->config.config_desc.bNumInterfaces = 0; + } +} + +static void usbh_hub_dump_status(struct usbh_hub *hub, uint8_t port, uint16_t portstatus, uint16_t portchange) +{ + USB_LOG_DBG("===================== \r\n"); + USB_LOG_DBG("hub-%d port-%d status 0x%x\r\n", hub->hub_addr, port, portstatus); + USB_LOG_DBG(" connection: %d\r\n", !!(portstatus & HUB_PORT_STATUS_CONNECTION)); + USB_LOG_DBG(" enable: %d\r\n", !!(portstatus & HUB_PORT_STATUS_ENABLE)); + USB_LOG_DBG(" suspend: %d\r\n", !!(portstatus & HUB_PORT_STATUS_SUSPEND)); + USB_LOG_DBG(" overcurrent: %d\r\n", !!(portstatus & HUB_PORT_STATUS_OVERCURRENT)); + USB_LOG_DBG(" reseting: %d\r\n", !!(portstatus & HUB_PORT_STATUS_RESET)); + USB_LOG_DBG(" power: %d\r\n", !!(portstatus & HUB_PORT_STATUS_POWER)); + if (portstatus & HUB_PORT_STATUS_LOW_SPEED) { + USB_LOG_DBG(" low-speed\r\n"); + } else if (portstatus & HUB_PORT_STATUS_HIGH_SPEED) { + USB_LOG_DBG(" high-speed\r\n"); + } else { + USB_LOG_DBG(" full-speed\r\n"); + } + USB_LOG_DBG(" test: %d\r\n", !!(portstatus & HUB_PORT_STATUS_TEST)); + USB_LOG_DBG(" indicator: %d\r\n", !!(portstatus & HUB_PORT_STATUS_INDICATOR)); + USB_LOG_DBG("hub-%d port-%d change 0x%x\r\n", hub->hub_addr, port, portchange); + USB_LOG_DBG(" connection change: %d\r\n", !!(portchange & HUB_PORT_STATUS_C_CONNECTION)); + USB_LOG_DBG(" enable change: %d\r\n", !!(portchange & HUB_PORT_STATUS_C_ENABLE)); + USB_LOG_DBG(" suspend change: %d\r\n", !!(portchange & HUB_PORT_STATUS_C_SUSPEND)); + USB_LOG_DBG(" overcurrent change: %d\r\n", !!(portchange & HUB_PORT_STATUS_C_OVERCURRENT)); + USB_LOG_DBG(" reset change: %d\r\n", !!(portchange & HUB_PORT_STATUS_C_RESET)); + USB_LOG_DBG("=====================\r\n"); +} + +static void usbh_hub_events(struct usbh_hub *hub) +{ + struct usbh_hubport *child; + struct hub_port_status port_status; + uint8_t portchange_index; + uint16_t portstatus; + uint16_t portchange; + uint16_t mask; + uint16_t feat; + uint8_t speed; + int ret; + + if (!hub->connected) { + return; + } + + for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + portchange_index = hub->int_buffer[0]; + + USB_LOG_DBG("Port change:0x%02x, Port:%u\r\n", portchange_index, port + 1); + + if (!(portchange_index & (1 << (port + 1)))) { + continue; + } + portchange_index &= ~(1 << (port + 1)); + USB_LOG_DBG("Port %d change\r\n", port + 1); + + /* Read hub port status */ + ret = usbh_hub_get_portstatus(hub, port + 1, &port_status); + if (ret < 0) { + USB_LOG_ERR("Failed to read port %u status, errorcode: %d\r\n", port + 1, ret); + continue; + } + + portstatus = port_status.wPortStatus; + portchange = port_status.wPortChange; + + usbh_hub_dump_status(hub, port + 1, portstatus, portchange); + + /* First, clear all change bits */ + mask = 1; + feat = HUB_PORT_FEATURE_C_CONNECTION; + while (portchange) { + if (portchange & mask) { + ret = usbh_hub_clear_feature(hub, port + 1, feat); + if (ret < 0) { + USB_LOG_ERR("Failed to clear port %u, change mask:%04x, errorcode:%d\r\n", port + 1, mask, ret); + continue; + } + portchange &= (~mask); + } + mask <<= 1; + feat++; + } + + portchange = port_status.wPortChange; + + /* Second, if port changes, debounces first */ + if (portchange & HUB_PORT_STATUS_C_CONNECTION) { + uint16_t connection = 0; + uint16_t debouncestable = 0; + for (uint32_t debouncetime = 0; debouncetime < HUB_DEBOUNCE_TIMEOUT; debouncetime += HUB_DEBOUNCE_STEP) { + /* Read hub port status */ + ret = usbh_hub_get_portstatus(hub, port + 1, &port_status); + if (ret < 0) { + USB_LOG_ERR("Failed to read port %u status, errorcode: %d\r\n", port + 1, ret); + continue; + } + + portstatus = port_status.wPortStatus; + portchange = port_status.wPortChange; + + USB_LOG_DBG("Port %u, status:0x%02x, change:0x%02x\r\n", port + 1, portstatus, portchange); + + if (!(portchange & HUB_PORT_STATUS_C_CONNECTION) && + ((portstatus & HUB_PORT_STATUS_CONNECTION) == connection)) { + debouncestable += HUB_DEBOUNCE_STEP; + if (debouncestable >= HUB_DEBOUNCE_STABLE) { + break; + } + } else { + debouncestable = 0; + connection = portstatus & HUB_PORT_STATUS_CONNECTION; + } + + if (portchange & HUB_PORT_STATUS_C_CONNECTION) { + usbh_hub_clear_feature(hub, port + 1, HUB_PORT_FEATURE_C_CONNECTION); + } + + usb_osal_msleep(HUB_DEBOUNCE_STEP); + } + + /** check if debounce ok */ + if (debouncestable < HUB_DEBOUNCE_STABLE) { + USB_LOG_ERR("Failed to debounce port %u\r\n", port + 1); + break; + } + + /* Last, check connect status */ + if (portstatus & HUB_PORT_STATUS_CONNECTION) { + ret = usbh_hub_set_feature(hub, port + 1, HUB_PORT_FEATURE_RESET); + if (ret < 0) { + USB_LOG_ERR("Failed to reset port %u,errorcode:%d\r\n", port + 1, ret); + continue; + } + + usb_osal_msleep(DELAY_TIME_AFTER_RESET); + /* Read hub port status */ + ret = usbh_hub_get_portstatus(hub, port + 1, &port_status); + if (ret < 0) { + USB_LOG_ERR("Failed to read port %u status, errorcode: %d\r\n", port + 1, ret); + continue; + } + + portstatus = port_status.wPortStatus; + portchange = port_status.wPortChange; + USB_LOG_DBG("Reset: %d, Enable: %d \r\n", + !!(portstatus & HUB_PORT_STATUS_RESET), + !!(portstatus & HUB_PORT_STATUS_ENABLE)); + if (!(portstatus & HUB_PORT_STATUS_RESET) && (portstatus & HUB_PORT_STATUS_ENABLE)) { + if (portchange & HUB_PORT_STATUS_C_RESET) { + ret = usbh_hub_clear_feature(hub, port + 1, HUB_PORT_FEATURE_C_RESET); + if (ret < 0) { + USB_LOG_ERR("Failed to clear port %u reset change, errorcode: %d\r\n", port + 1, ret); + } + } + + if (portstatus & HUB_PORT_STATUS_HIGH_SPEED) { + speed = USB_SPEED_HIGH; + } else if (portstatus & HUB_PORT_STATUS_LOW_SPEED) { + speed = USB_SPEED_LOW; + } +#ifdef CONFIG_USBHOST_XHCI + /* USB3.0 speed cannot get from portstatus, checkout port speed instead */ + else { + extern uint8_t usbh_get_port_speed(struct usbh_hub *hub, const uint8_t port); + + uint8_t port_speed = usbh_get_port_speed(hub, port + 1); + if (port_speed >= USB_SPEED_SUPER) { + /* assert that when using USB 3.0 ports, attached device must also be USB 3.0 speed */ + speed = port_speed; + } else { + speed = USB_SPEED_FULL; + } + } +#else + else { + speed = USB_SPEED_FULL; + } +#endif + + child = &hub->child[port]; + /** release child sources first */ + usbh_hubport_release(child); + + memset(child, 0, sizeof(struct usbh_hubport)); + child->parent = hub; + child->connected = true; + child->port = port + 1; + child->speed = speed; + + USB_LOG_RAW("New %s device on Hub %u, Port %u connected\r\n", speed_table[speed], hub->index, port + 1); + + /* Configure EP0 with the default maximum packet size */ + usbh_hport_activate_ep0(child); + + if (usbh_enumerate(child) < 0) { + /** release child sources */ + usbh_hubport_release(child); + USB_LOG_ERR("Port %u enumerate fail\r\n", port + 1); + } + } else { + child = &hub->child[port]; + /** release child sources */ + usbh_hubport_release(child); + + /** some USB 3.0 ip may failed to enable USB 2.0 port for USB 3.0 device */ + USB_LOG_WRN("Failed to enable port %u\r\n", port + 1); + + continue; + } + } else { + child = &hub->child[port]; + /** release child sources */ + usbh_hubport_release(child); + USB_LOG_INFO("Device on Hub %u, Port %u disconnected\r\n", hub->index, port + 1); + } + } + } + + hub->int_buffer[0] = 0; + /* Start next hub int transfer */ + if (!hub->is_roothub && hub->connected) { + usbh_submit_urb(&hub->intin_urb); + } +} + +static void usbh_hub_thread(void *argument) +{ + struct usbh_hub *hub; + int ret = 0; + struct usbh_bus *usb = (struct usbh_bus *)argument; + + usb_hc_init(usb->id); + while (1) { + USB_LOG_DBG("wait event of mq@%p \r\n", usb->hub_mq); + ret = usb_osal_mq_recv(usb->hub_mq, (void *)&hub, 0xffffffff); + if (ret < 0) { + continue; + } + USB_LOG_DBG("handle event of hub@%p \r\n", hub); + usbh_hub_events(hub); + } +} + +static void usbh_roothub_register(struct usbh_bus *usb) +{ + struct usbh_hub* roothub = &(usb->roothub); + memset(roothub, 0, sizeof(struct usbh_hub)); + + roothub->connected = true; + roothub->index = 1; + roothub->is_roothub = true; + roothub->parent = NULL; + roothub->hub_addr = 1; + roothub->hub_desc.bNbrPorts = CONFIG_USBHOST_MAX_RHPORTS; + roothub->usb = usb; + usbh_hub_register(roothub); +} + +static void usbh_hub_thread_wakeup(struct usbh_hub *hub) +{ + USB_LOG_DBG("try to wakeup hub0x%x \r\n", hub); + struct usbh_bus *usb = hub->usb; + usb_osal_mq_send(usb->hub_mq, (uintptr_t)hub); +} + +void usbh_roothub_thread_wakeup(uint32_t usb_id, uint8_t port) +{ + struct usbh_bus* usb = usbh_get_bus_of_index(usb_id); + struct usbh_hub* roothub = &(usb->roothub); + + roothub->int_buffer = roothub->g_hub_intbuf[roothub->index - 1]; + roothub->int_buffer[0] |= (1 << port); + USB_LOG_DBG("port-%u wakeup roothub@%p \r\n", port, roothub); + usbh_hub_thread_wakeup(roothub); +} + +int usbh_hub_initialize(struct usbh_bus *usb) +{ + usbh_roothub_register(usb); + + usb->hub_mq = usb_osal_mq_create(7); + if (usb->hub_mq == NULL) { + return -1; + } + + char thread_name[12]; + snprintf(thread_name, 12, "usb%d_hub", usb->id); + usb->hub_thread = usb_osal_thread_create(thread_name, CONFIG_USBHOST_PSC_STACKSIZE, CONFIG_USBHOST_PSC_PRIO, usbh_hub_thread, usb); + if (usb->hub_thread == NULL) { + return -1; + } + + return 0; +} +#if CONFIG_USBHOST_MAX_EXTHUBS > 0 +const struct usbh_class_driver hub_class_driver = { + .driver_name = "hub", + .connect = usbh_hub_connect, + .disconnect = usbh_hub_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info hub_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS, + .class = USB_DEVICE_CLASS_HUB, + .subclass = 0, + .protocol = 0, + .vid = 0x00, + .pid = 0x00, + .class_driver = &hub_class_driver +}; +#endif From 47a330b08fe47d2c936fd57cdc2bd87bb603a4f5 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Mon, 24 Jun 2024 15:42:00 +0800 Subject: [PATCH 049/198] Modify the hub to decouple from xhci. --- .../usb/components/class/hub/usbh_hub.c | 25 +++++++++++-------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c index 98e59adc6..e3674d327 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c @@ -8,9 +8,16 @@ File name: usbh_hub.c Description: adopt cherry USB to XiZi AIOT. Others: CherryUSB third-party/cherryusb/class/hub/usbh_hub.c for references https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/blob/master/third-party/cherryusb/class/hub/usbh_hub.c + +History: +1. Date: 2024-06-24 +Author: AIIT XUOS Lab +Modification: Modify the hub to decouple from xhci. *************************************************/ #include "usbh_hub.h" +#include "usb_def.h" + #define DEV_FORMAT "/usb%d/hub%d" @@ -96,7 +103,7 @@ static int _usbh_hub_get_hub_descriptor(struct usbh_hub *hub, uint8_t *buffer) setup->wIndex = 0; setup->wLength = USB_SIZEOF_HUB_DESC; - ret = usbh_control_transfer(hub->parent->ep0, setup, hub->g_hub_buf); + ret = usbh_control_transfer_xiuos(hub->parent, hub->parent->ep0, setup, hub->g_hub_buf); if (ret < 0) { return ret; } @@ -117,7 +124,7 @@ static int _usbh_hub_get_status(struct usbh_hub *hub, uint8_t *buffer) setup->wIndex = 0; setup->wLength = 2; - ret = usbh_control_transfer(hub->parent->ep0, setup, hub->g_hub_buf); + ret = usbh_control_transfer_xiuos(hub->parent, hub->parent->ep0, setup, hub->g_hub_buf); if (ret < 0) { return ret; } @@ -139,7 +146,7 @@ static int _usbh_hub_get_portstatus(struct usbh_hub *hub, uint8_t port, struct h setup->wIndex = port; setup->wLength = 4; - ret = usbh_control_transfer(hub->parent->ep0, setup, hub->g_hub_buf); + ret = usbh_control_transfer_xiuos(hub->parent, hub->parent->ep0, setup, hub->g_hub_buf); if (ret < 0) { return ret; } @@ -159,7 +166,7 @@ static int _usbh_hub_set_feature(struct usbh_hub *hub, uint8_t port, uint8_t fea setup->wIndex = port; setup->wLength = 0; - return usbh_control_transfer(hub->parent->ep0, setup, NULL); + return usbh_control_transfer_xiuos(hub->parent, hub->parent->ep0, setup, NULL); } static int _usbh_hub_clear_feature(struct usbh_hub *hub, uint8_t port, uint8_t feature) @@ -174,7 +181,7 @@ static int _usbh_hub_clear_feature(struct usbh_hub *hub, uint8_t port, uint8_t f setup->wIndex = port; setup->wLength = 0; - return usbh_control_transfer(hub->parent->ep0, setup, NULL); + return usbh_control_transfer_xiuos(hub->parent, hub->parent->ep0, setup, NULL); } static int _usbh_hub_set_depth(struct usbh_hub *hub, uint16_t depth) @@ -189,7 +196,7 @@ static int _usbh_hub_set_depth(struct usbh_hub *hub, uint16_t depth) setup->wIndex = 0; setup->wLength = 0; - return usbh_control_transfer(hub->parent->ep0, setup, NULL); + return usbh_control_transfer_xiuos(hub->parent, hub->parent->ep0, setup, NULL); } #if CONFIG_USBHOST_MAX_EXTHUBS > 0 @@ -378,7 +385,7 @@ static int usbh_hub_connect(struct usbh_hubport *hport, uint8_t intf) USB_LOG_RAW("Register HUB Class:%s for USB-%d\r\n", hport->config.intf[intf].devname, usb->id); hub->int_buffer = hub->g_hub_intbuf[hub->index - 1]; - usbh_int_urb_fill(&hub->intin_urb, hub->intin, hub->int_buffer, 1, 0, hub_int_complete_callback, hub); + usbh_int_urb_fill_xiuos(&hub->intin_urb, hub->parent, hub->intin, hub->int_buffer, 1, 0, hub_int_complete_callback, hub); usbh_submit_urb(&hub->intin_urb); return 0; } @@ -394,7 +401,7 @@ static int usbh_hub_disconnect(struct usbh_hubport *hport, uint8_t intf) usbh_hub_devno_free(hub->index); if (hub->intin) { - usbh_pipe_free(hub->intin); + usbh_pipe_free_xiuos(hport, hub->intin); } for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { @@ -597,8 +604,6 @@ static void usbh_hub_events(struct usbh_hub *hub) #ifdef CONFIG_USBHOST_XHCI /* USB3.0 speed cannot get from portstatus, checkout port speed instead */ else { - extern uint8_t usbh_get_port_speed(struct usbh_hub *hub, const uint8_t port); - uint8_t port_speed = usbh_get_port_speed(hub, port + 1); if (port_speed >= USB_SPEED_SUPER) { /* assert that when using USB 3.0 ports, attached device must also be USB 3.0 speed */ From e9b9e907c62ecad5ab5b612db3b1c16a40f15ca8 Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 25 Jun 2024 19:38:58 -0700 Subject: [PATCH 050/198] Add physical page interface --- .../drivers/usb/components/mem/usb_mem.c | 11 +++++++++++ .../drivers/usb/components/mem/usb_mem.h | 16 ++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c index 54e47f614..f4a220235 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c @@ -52,4 +52,15 @@ void *usb_hc_malloc_align(size_t align, size_t size) void usb_hc_free(void* ptr){ if(ptr != NULL) free(ptr); +} + + +usb_dir_page_t usb_alloc_dir_page(int len, int flag, int headroom_len){ + return NULL; +} + + + +void usb_free_dir_page(usb_dir_page_t page){ + } \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h index b47417473..03fea763c 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h @@ -23,6 +23,7 @@ Modification: Use usb_malloc, usb_free and usb_align functions #define USB_MEM_H_ #include +#include #include "usb_config.h" #define USB_MEM_ALIGNX __attribute__((aligned(CONFIG_USB_ALIGN_SIZE))) @@ -35,5 +36,20 @@ void *usb_hc_malloc_align(size_t align, size_t size); #define usb_free(ptr) usb_hc_free(ptr) #define usb_align(align, size) usb_hc_malloc_align(align, size) +struct usb_dir_page{ + uint64_t vir_addr; + uint64_t phy_addr; + uint32_t size; + uint32_t len; + uint32_t flag; + uint32_t headroom_len; +}__PACKED; + +typedef struct usb_dir_page *usb_dir_page_t; + +usb_dir_page_t usb_alloc_dir_page(int len, int flag, int headroom_len); +void usb_free_dir_page(usb_dir_page_t page); + + #endif From 9bf663c4767a390e461d722a541136c1f45878de Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 25 Jun 2024 22:58:36 -0700 Subject: [PATCH 051/198] Add address of USB3.0 host controller registers in RK3568 --- .../drivers/usb/components/port/xhci/usb_hc_xhci.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h index 1af816dfe..fb1c1bed0 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h @@ -45,6 +45,13 @@ Modification: rewrite xhci functions to dock with USB core layer, so that the xh extern "C" { #endif +/* + * Address of USB3 host control base Register in RK3568. + */ +#define USB3_0_BASE_ADDR 0xFCC00000 +#define USB3_1_BASE_ADDR 0xFD000000 + + /** * @brief xHCI host controller hardware init. * From e44ae64451caa54fd2469ecc60bd4ef39581cd6d Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 25 Jun 2024 23:39:18 -0700 Subject: [PATCH 052/198] Add address of USB3.0 host controller registers in RK3568 --- .../drivers/usb/components/port/xhci/usb_hc_xhci.c | 11 ++++++++++- .../drivers/usb/components/port/xhci/usb_hc_xhci.h | 2 ++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index cf81dd396..aaca03d1c 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -84,7 +84,16 @@ __WEAK void usb_hc_free() /* one may get xhci register base address by PCIe bus emuration */ __WEAK unsigned long usb_hc_get_register_base(uint32_t id) { - return 0U; + unsigned long base_addr; + + if(USB3_0_ID == id) + base_addr = USB3_0_BASE_ADDR; + else if(USB3_1_ID == id) + base_addr = USB3_1_BASE_ADDR; + else + base_addr = 0; + + return base_addr; } diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h index fb1c1bed0..1bc444f4e 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h @@ -48,6 +48,8 @@ extern "C" { /* * Address of USB3 host control base Register in RK3568. */ +#define USB3_0_ID 0 +#define USB3_1_ID 1 #define USB3_0_BASE_ADDR 0xFCC00000 #define USB3_1_BASE_ADDR 0xFD000000 From 2c82079be71138c9606bb2d8883f67dc0fe3021b Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 27 Jun 2024 20:10:44 -0700 Subject: [PATCH 053/198] Adding more USB hardware information for RK3568 --- .../drivers/usb/components/port/xhci/usb_hc_xhci.h | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h index 1bc444f4e..79e256341 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h @@ -47,12 +47,14 @@ extern "C" { /* * Address of USB3 host control base Register in RK3568. + * USB3_ADDR_OFFSET_UPPER_BOUND can be found in Part 2, + * Table 16-1 USB3 Address Mapping. */ -#define USB3_0_ID 0 -#define USB3_1_ID 1 -#define USB3_0_BASE_ADDR 0xFCC00000 -#define USB3_1_BASE_ADDR 0xFD000000 - +#define USB3_0_ID 0 +#define USB3_1_ID 1 +#define USB3_0_BASE_ADDR 0xFCC00000 +#define USB3_1_BASE_ADDR 0xFD000000 +#define USB3_ADDR_OFFSET_UPPER_BOUND 0x07FFF /** * @brief xHCI host controller hardware init. From b0471990a3bcbe6b3257cf2b1aa3f50664ded9c5 Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 27 Jun 2024 20:28:57 -0700 Subject: [PATCH 054/198] Adding more USB hardware information for RK3568 --- .../services/drivers/usb/components/port/xhci/usb_hc_xhci.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h index 79e256341..22ca571bb 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h @@ -56,6 +56,9 @@ extern "C" { #define USB3_1_BASE_ADDR 0xFD000000 #define USB3_ADDR_OFFSET_UPPER_BOUND 0x07FFF +#define USB3_VIRADDR_BASE 0x0000002000000000ULL +#define USB3_1_VIRADDR_BASE USB3_VIRADDR_BASE +#define USB3_2_VIRADDR_BASE USB3_VIRADDR_BASE + USB3_ADDR_OFFSET_UPPER_BOUND /** * @brief xHCI host controller hardware init. * From bf1947052b0fd7bffecc7856faf3b421b7af147e Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 27 Jun 2024 23:06:22 -0700 Subject: [PATCH 055/198] Adding more USB hardware information for RK3568 --- .../services/drivers/usb/components/port/xhci/xhci.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h index 0d8bff14f..d701eb935 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h @@ -813,16 +813,27 @@ struct xhci_host { char name[4]; /* xhci registers base addr */ + /* + * base, cap, op, run and db are pointed to their according physical address. However, the user-space driver can not access physical + * address directly. So we add these data members: base_addr, cap_addr, op_addr, run_addr and ad_addr, and bind them to the according + * physical address. + */ /** Registers base */ void *base; + void *base_addr; /** Capability registers */ void *cap; + void *cap_addr; + /** Operational registers */ void *op; + void *op_addr; /** Runtime registers */ void *run; + void *run_addr; /** Doorbell registers */ void *db; + void *db_addr; /** extended capability */ unsigned int xecp; /** capability cache */ From 805cd766ea069be133003b970a662248ebd39117 Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 27 Jun 2024 23:45:07 -0700 Subject: [PATCH 056/198] Adding more USB hardware information for RK3568 --- .../usb/components/port/xhci/usb_hc_xhci.c | 28 +++++++++++++++++++ .../usb/components/port/xhci/usb_hc_xhci.h | 4 +-- 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index aaca03d1c..a79daa672 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -97,6 +97,34 @@ __WEAK unsigned long usb_hc_get_register_base(uint32_t id) } +__WEAK int usb_hc_get_register_id(unsigned long base_addr){ + int id; + + if(USB3_0_BASE_ADDR == base_addr) + id = USB3_0_ID; + else if(USB3_1_BASE_ADDR == base_addr) + id = USB3_1_ID; + else + id = -1; + + return id; +} + + +__WEAK unsigned long usb_hc_get_register_vir_base(uint32_t id) +{ + unsigned long base_addr; + + if(USB3_0_ID == id) + base_addr = USB3_0_VIRADDR_BASE; + else if(USB3_1_ID == id) + base_addr = USB3_1_VIRADDR_BASE; + else + base_addr = 0; + + return base_addr; +} + static inline struct xhci_host* xhci_get_inst_of_port(struct usbh_hubport *hport) { USB_ASSERT(hport && hport->parent); diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h index 22ca571bb..12827defe 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h @@ -57,8 +57,8 @@ extern "C" { #define USB3_ADDR_OFFSET_UPPER_BOUND 0x07FFF #define USB3_VIRADDR_BASE 0x0000002000000000ULL -#define USB3_1_VIRADDR_BASE USB3_VIRADDR_BASE -#define USB3_2_VIRADDR_BASE USB3_VIRADDR_BASE + USB3_ADDR_OFFSET_UPPER_BOUND +#define USB3_0_VIRADDR_BASE USB3_VIRADDR_BASE +#define USB3_1_VIRADDR_BASE USB3_VIRADDR_BASE + USB3_ADDR_OFFSET_UPPER_BOUND /** * @brief xHCI host controller hardware init. * From d2c1180cce93d324811f6b1cb0722b2bbe660038 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 28 Jun 2024 15:00:21 +0800 Subject: [PATCH 057/198] Modify usb core to call functions defined by xhci. --- .../services/drivers/usb/components/core/usbh_core.c | 5 ----- .../drivers/usb/components/port/xhci/usb_hc_xhci.h | 8 ++++++++ 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c index 369ab2890..9356a2e64 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c @@ -1051,11 +1051,6 @@ int usbh_pipe_alloc(usbh_pipe_t *pipe, const struct usbh_endpoint_cfg *ep_cfg) return rc; } -int usbh_get_xhci_devaddr(usbh_pipe_t *pipe) -{ - return 0; -} - int usbh_get_devaddr(struct usbh_hubport *hport) { int dev_addr; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h index 12827defe..e501e466f 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h @@ -111,6 +111,14 @@ int xhci_usbh_ep_pipe_reconfigure(struct usbh_bus *usb, usbh_pipe_t pipe, uint8_ */ int xhci_usbh_pipe_alloc(usbh_pipe_t *pipe, const struct usbh_endpoint_cfg *ep_cfg); +/** + * @brief get device address. + * + * @param pipe A memory allocated for pipe. + * @return On success will return device address, and others indicate fail. + */ +int usbh_get_xhci_devaddr(usbh_pipe_t *pipe); + /** * @brief Free a pipe in which saves endpoint info. * From 3beb9fb2b9f7e87748b48abcabeb7cb78755e16f Mon Sep 17 00:00:00 2001 From: xj Date: Fri, 28 Jun 2024 00:15:10 -0700 Subject: [PATCH 058/198] Adding more USB hardware information for RK3568 --- .../services/drivers/usb/components/port/xhci/usb_hc_xhci.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h index 12827defe..90d4a9df2 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h @@ -142,6 +142,12 @@ int xhci_usbh_kill_urb(struct usbh_urb *urb); void XHCI_USBH_IRQHandler(void *param); +__WEAK unsigned long usb_hc_get_register_base(uint32_t id); + +__WEAK int usb_hc_get_register_id(unsigned long base_addr); + +__WEAK unsigned long usb_hc_get_register_vir_base(uint32_t id); + #ifdef __cplusplus } From 7ed436a8c8c65a512dcbeb355b3b8ad1dff50445 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 28 Jun 2024 18:00:28 +0800 Subject: [PATCH 059/198] Add TODO comments to the function to be modified. --- .../XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c | 2 ++ .../XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h | 3 +++ 2 files changed, 5 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c index 9356a2e64..674fe4639 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c @@ -842,6 +842,7 @@ int usbh_initialize(uint32_t id, struct usbh_bus *usb) return 0; } +/* TODO: This function will be replaced by usbh_control_transfer_xiuos.*/ int usbh_control_transfer(usbh_pipe_t pipe, struct usb_setup_packet *setup, uint8_t *buffer) { struct usbh_urb *urb; @@ -1073,6 +1074,7 @@ int usbh_get_devaddr(struct usbh_hubport *hport) return dev_addr; } +/* TODO: This function will be replaced by usbh_pipe_free_xiuos.*/ int usbh_pipe_free(usbh_pipe_t pipe) { return 0; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h index e31185baa..3cba17813 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h @@ -71,6 +71,7 @@ extern "C" { #define CLASS_INFO_DEFINE __attribute__((section("usbh_class_info"))) __USED __ALIGNED(1) #endif +/* TODO: This function will be replaced by usbh_control_urb_fill_xiuos.*/ static inline void usbh_control_urb_fill(struct usbh_urb *urb, usbh_pipe_t pipe, struct usb_setup_packet *setup, @@ -89,6 +90,7 @@ static inline void usbh_control_urb_fill(struct usbh_urb *urb, urb->arg = arg; } +/* TODO: This function will be replaced by usbh_bulk_urb_fill_xiuos.*/ static inline void usbh_bulk_urb_fill(struct usbh_urb *urb, usbh_pipe_t pipe, uint8_t *transfer_buffer, @@ -106,6 +108,7 @@ static inline void usbh_bulk_urb_fill(struct usbh_urb *urb, urb->arg = arg; } +/* TODO: This function will be replaced by usbh_int_urb_fill_xiuos.*/ static inline void usbh_int_urb_fill(struct usbh_urb *urb, usbh_pipe_t pipe, uint8_t *transfer_buffer, From 41a4e81d7d3e56763dd342c34ed2f8f8d60dd083 Mon Sep 17 00:00:00 2001 From: xj Date: Fri, 28 Jun 2024 04:12:02 -0700 Subject: [PATCH 060/198] Adding more USB hardware information for RK3568 --- .../drivers/usb/components/port/xhci/xhci.c | 36 ++++++++++++++++--- 1 file changed, 31 insertions(+), 5 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 911782a2f..41aa8200d 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -38,7 +38,7 @@ Modification: replant and redefine some xhci data structure, so that the cherryU /* - * Copyright聽: (C)聽2022聽Phytium聽Information聽Technology,聽Inc. + * Copyright : (C) 2022 Phytium Information Technology, Inc. * All Rights Reserved. * * This program is OPEN SOURCE software: you can redistribute it and/or modify it @@ -53,20 +53,34 @@ Modification: replant and redefine some xhci data structure, so that the cherryU * FilePath: xhci.c * Date: 2022-07-19 09:26:25 * LastEditTime: 2022-07-19 09:26:25 - * Description: 聽This file is for xhci functions implmentation. + * Description:  This file is for xhci functions implmentation. * - * Modify聽History: - * Ver聽聽聽Who聽聽聽聽聽聽聽聽Date聽聽聽聽聽聽聽聽聽Changes - * -----聽------聽聽聽聽聽--------聽聽聽聽-------------------------------------- + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- * 1.0 zhugengyu 2022/9/19 init commit * 2.0 zhugengyu 2023/3/29 support usb3.0 device attached at roothub */ + /************************************************* +File name: xhci.c +Description: adopt cherry USB to XiZi AIOT. +Others: CherryUSB third-party/cherryusb/port/xhci/xhci.c for references + https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/blob/master/third-party/cherryusb/port/xhci/xhci.c + +History: +1. Date: 2024-06-28 +Author: AIIT XUOS Lab +Modification: Modify xhci_probe functions in order to adopt to XiZi AIOT. + +*************************************************/ + #include "usbh_core.h" #include "usbh_hub.h" #include "xhci_reg.h" #include "xhci.h" +#include "usb_hc_xhci.h" /** @file @@ -171,8 +185,20 @@ static void xhci_init ( struct xhci_host *xhci, void *regs ) { size_t rtsoff; size_t dboff; + int id; + uint64_t cap_vir_addr; + /* Locate capability, operational, runtime, and doorbell registers */ xhci->cap = regs; + + id = usb_hc_get_register_id(regs); + + cap_vir_addr = usb_hc_get_register_vir_base(id); + + if(!mmap(cap_vir_addr, regs, USB3_ADDR_OFFSET_UPPER_BOUND, true)){ + + } + caplength = readb ( xhci->cap + XHCI_CAP_CAPLENGTH ); rtsoff = readl ( xhci->cap + XHCI_CAP_RTSOFF ); dboff = readl ( xhci->cap + XHCI_CAP_DBOFF ); From 9ce725944779d3cdefe2867f113f569d86531963 Mon Sep 17 00:00:00 2001 From: xj Date: Fri, 28 Jun 2024 04:32:00 -0700 Subject: [PATCH 061/198] Adding more USB hardware information for RK3568 --- .../drivers/usb/components/port/xhci/xhci.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 41aa8200d..b91cc0f36 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -196,15 +196,26 @@ static void xhci_init ( struct xhci_host *xhci, void *regs ) { cap_vir_addr = usb_hc_get_register_vir_base(id); if(!mmap(cap_vir_addr, regs, USB3_ADDR_OFFSET_UPPER_BOUND, true)){ - + return; } - caplength = readb ( xhci->cap + XHCI_CAP_CAPLENGTH ); - rtsoff = readl ( xhci->cap + XHCI_CAP_RTSOFF ); - dboff = readl ( xhci->cap + XHCI_CAP_DBOFF ); + xhci->cap_addr = xhci->base_addr = cap_vir_addr; + +// caplength = readb ( xhci->cap + XHCI_CAP_CAPLENGTH ); + caplength = readb ( xhci->cap_addr + XHCI_CAP_CAPLENGTH ); +// rtsoff = readl ( xhci->cap + XHCI_CAP_RTSOFF ); + rtsoff = readl ( xhci->cap_addr + XHCI_CAP_RTSOFF ); + +// dboff = readl ( xhci->cap + XHCI_CAP_DBOFF ); + dboff = readl ( xhci->cap_addr + XHCI_CAP_DBOFF ); xhci->op = ( xhci->cap + caplength ); + xhci->op_addr = ( xhci->cap_addr + caplength ); + xhci->run = ( xhci->cap + rtsoff ); + xhci->run_addr = ( xhci->cap_addr + rtsoff ); + xhci->db = ( xhci->cap + dboff ); + xhci->db_addr = ( xhci->cap_addr + dboff ); /* avoid access XHCI_REG_CAP_HCIVERSION = 0x2, unaligned memory */ xhci->version = ((readl ( xhci->cap + XHCI_CAP_CAPLENGTH ) >> 16) & 0xffff); From 7c48797ecf846d56f0aa1dbe4322234e9b992a5d Mon Sep 17 00:00:00 2001 From: xj Date: Fri, 28 Jun 2024 04:37:15 -0700 Subject: [PATCH 062/198] Adding more USB hardware information for RK3568 --- .../drivers/usb/components/port/xhci/xhci.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index b91cc0f36..41c1a9c1b 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -218,7 +218,8 @@ static void xhci_init ( struct xhci_host *xhci, void *regs ) { xhci->db_addr = ( xhci->cap_addr + dboff ); /* avoid access XHCI_REG_CAP_HCIVERSION = 0x2, unaligned memory */ - xhci->version = ((readl ( xhci->cap + XHCI_CAP_CAPLENGTH ) >> 16) & 0xffff); + // xhci->version = ((readl ( xhci->cap + XHCI_CAP_CAPLENGTH ) >> 16) & 0xffff); + xhci->version = ((readl ( xhci->cap_addr + XHCI_CAP_CAPLENGTH ) >> 16) & 0xffff); USB_LOG_DBG("XHCI %s version %x cap %08lx op %08lx run %08lx db %08lx\n", xhci->name, xhci->version, ( xhci->cap ), @@ -230,7 +231,9 @@ static void xhci_init ( struct xhci_host *xhci, void *regs ) { } /* Read structural parameters 1 */ - hcsparams1 = readl ( xhci->cap + XHCI_CAP_HCSPARAMS1 ); +// hcsparams1 = readl ( xhci->cap + XHCI_CAP_HCSPARAMS1 ); + hcsparams1 = readl ( xhci->cap_addr + XHCI_CAP_HCSPARAMS1 ); + xhci->slots = XHCI_HCSPARAMS1_SLOTS ( hcsparams1 ); xhci->intrs = XHCI_HCSPARAMS1_INTRS ( hcsparams1 ); xhci->ports = XHCI_HCSPARAMS1_PORTS ( hcsparams1 ); @@ -238,13 +241,16 @@ static void xhci_init ( struct xhci_host *xhci, void *regs ) { xhci->name, xhci->slots, xhci->intrs, xhci->ports ); /* Read structural parameters 2 */ - hcsparams2 = readl ( xhci->cap + XHCI_CAP_HCSPARAMS2 ); +// hcsparams2 = readl ( xhci->cap + XHCI_CAP_HCSPARAMS2 ); + hcsparams2 = readl ( xhci->cap_addr + XHCI_CAP_HCSPARAMS2 ); xhci->scratch.count = XHCI_HCSPARAMS2_SCRATCHPADS ( hcsparams2 ); USB_LOG_DBG("XHCI %s needs %d scratchpads\n", xhci->name, xhci->scratch.count ); /* Read capability parameters 1 */ - hccparams1 = readl ( xhci->cap + XHCI_CAP_HCCPARAMS1 ); +// hccparams1 = readl ( xhci->cap + XHCI_CAP_HCCPARAMS1 ); + hccparams1 = readl ( xhci->cap_addr + XHCI_CAP_HCCPARAMS1 ); + xhci->addr64 = XHCI_HCCPARAMS1_ADDR64 ( hccparams1 ); xhci->csz_shift = XHCI_HCCPARAMS1_CSZ_SHIFT ( hccparams1 ); xhci->xecp = (XHCI_HCCPARAMS1_XECP ( hccparams1 )); @@ -252,7 +258,9 @@ static void xhci_init ( struct xhci_host *xhci, void *regs ) { xhci->name, (xhci->addr64 ? 64 : 32) ); /* Read page size */ - pagesize = readl ( xhci->op + XHCI_OP_PAGESIZE ); +// pagesize = readl ( xhci->op + XHCI_OP_PAGESIZE ); + pagesize = readl ( xhci->op_addr + XHCI_OP_PAGESIZE ); + xhci->pagesize = XHCI_PAGESIZE ( pagesize ); USB_ASSERT ( xhci->pagesize != 0 ); USB_ASSERT ( ( ( xhci->pagesize ) & ( xhci->pagesize - 1 ) ) == 0 ); From eac58cedec899e382c56088995d6ac90995caf0f Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 1 Jul 2024 00:12:14 -0700 Subject: [PATCH 063/198] Modify xhci_extended_capability so that the xHCI can adapt to XiZi AIOT --- .../services/drivers/usb/components/port/xhci/xhci.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 41c1a9c1b..accd06a45 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -287,7 +287,8 @@ static unsigned int xhci_extended_capability ( struct xhci_host *xhci, /* Locate first or next capability as applicable */ if ( offset ) { - xecp = readl ( xhci->cap + offset ); + // xecp = readl ( xhci->cap + offset ); + xecp = readl ( xhci->cap_addr + offset ); next = XHCI_XECP_NEXT ( xecp ); } else { next = xhci->xecp; @@ -297,7 +298,9 @@ static unsigned int xhci_extended_capability ( struct xhci_host *xhci, offset += next; /* Check if this is the requested capability */ - xecp = readl ( xhci->cap + offset ); +// xecp = readl ( xhci->cap + offset ); + xecp = readl ( xhci->cap_addr + offset ); + if ( XHCI_XECP_ID ( xecp ) == id ) return offset; } From e34d688cc35931dc7923903c5d94494a956c3028 Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 1 Jul 2024 01:37:23 -0700 Subject: [PATCH 064/198] Modify xhci_legacy_init so that the xHCI can adapt to XiZi AIOT --- .../XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index accd06a45..a86acaf22 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -327,7 +327,8 @@ static void xhci_legacy_init ( struct xhci_host *xhci ) { /* Check if legacy USB support is enabled */ USB_LOG_DBG("XHCI %s bios offset 0x%x\n", xhci->name, (xhci->cap + legacy + XHCI_USBLEGSUP_BIOS)); /* bios = readb ( xhci->cap + legacy + XHCI_USBLEGSUP_BIOS ); cannot access offset 0x2, work around */ - bios = readl ( xhci->cap + legacy ); +// bios = readl ( xhci->cap + legacy ); + bios = readl ( xhci->cap_addr + legacy ); bios = (bios >> 16) & 0xffff; if ( ! ( bios & XHCI_USBLEGSUP_BIOS_OWNED ) ) { /* Not an error; already owned by OS */ From 3efb2335c5daf62d4f4d831fb165d7fbbb713764 Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 1 Jul 2024 03:02:01 -0700 Subject: [PATCH 065/198] Modify xhci_stop so that the xHCI can adapt to XiZi AIOT --- .../drivers/usb/components/port/xhci/xhci.c | 23 ++++++++++++++----- 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index a86acaf22..193907743 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -358,18 +358,26 @@ static void xhci_legacy_claim ( struct xhci_host *xhci ) { return; /* Claim ownership */ +// writeb ( XHCI_USBLEGSUP_OS_OWNED, +// xhci->cap + xhci->legacy + XHCI_USBLEGSUP_OS ); + writeb ( XHCI_USBLEGSUP_OS_OWNED, - xhci->cap + xhci->legacy + XHCI_USBLEGSUP_OS ); + xhci->cap_addr + xhci->legacy + XHCI_USBLEGSUP_OS ); /* Wait for BIOS to release ownership */ for ( i = 0 ; i < XHCI_USBLEGSUP_MAX_WAIT_MS ; i++ ) { /* Check if BIOS has released ownership */ - bios = readb ( xhci->cap + xhci->legacy + XHCI_USBLEGSUP_BIOS ); +// bios = readb ( xhci->cap + xhci->legacy + XHCI_USBLEGSUP_BIOS ); + bios = readb ( xhci->cap_addr + xhci->legacy + XHCI_USBLEGSUP_BIOS ); + if ( ! ( bios & XHCI_USBLEGSUP_BIOS_OWNED ) ) { USB_LOG_DBG("XHCI %s claimed ownership from BIOS\n", xhci->name ); - ctlsts = readl ( xhci->cap + xhci->legacy + +// ctlsts = readl ( xhci->cap + xhci->legacy + +// XHCI_USBLEGSUP_CTLSTS ); + + ctlsts = readl ( xhci->cap_addr + xhci->legacy + XHCI_USBLEGSUP_CTLSTS ); if ( ctlsts ) { USB_LOG_DBG("XHCI %s warning: BIOS retained " @@ -428,15 +436,18 @@ static int xhci_stop ( struct xhci_host *xhci ) { unsigned int i; /* Clear run/stop bit */ - usbcmd = readl ( xhci->op + XHCI_OP_USBCMD ); +// usbcmd = readl ( xhci->op + XHCI_OP_USBCMD ); + usbcmd = readl ( xhci->op_addr + XHCI_OP_USBCMD ); usbcmd &= ~XHCI_USBCMD_RUN; - writel ( usbcmd, xhci->op + XHCI_OP_USBCMD ); +// writel ( usbcmd, xhci->op + XHCI_OP_USBCMD ); + writel ( usbcmd, xhci->op_addr + XHCI_OP_USBCMD ); /* Wait for device to stop */ for ( i = 0 ; i < XHCI_STOP_MAX_WAIT_MS ; i++ ) { /* Check if device is stopped */ - usbsts = readl ( xhci->op + XHCI_OP_USBSTS ); +// usbsts = readl ( xhci->op + XHCI_OP_USBSTS ); + usbsts = readl ( xhci->op_addr + XHCI_OP_USBSTS ); if ( usbsts & XHCI_USBSTS_HCH ) return 0; From 21a0f8ed30401fff2d815e61a599cb3b37b68cee Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 1 Jul 2024 04:13:01 -0700 Subject: [PATCH 066/198] Modify xhci_reset so that the xHCI can adapt to XiZi AIOT --- .../services/drivers/usb/components/port/xhci/xhci.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 193907743..c87ec3293 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -479,13 +479,16 @@ static int xhci_reset ( struct xhci_host *xhci ) { } /* Reset device */ - writel ( XHCI_USBCMD_HCRST, xhci->op + XHCI_OP_USBCMD ); +// writel ( XHCI_USBCMD_HCRST, xhci->op + XHCI_OP_USBCMD ); + writel ( XHCI_USBCMD_HCRST, xhci->op_addr + XHCI_OP_USBCMD ); + /* Wait for reset to complete */ for ( i = 0 ; i < XHCI_RESET_MAX_WAIT_MS ; i++ ) { /* Check if reset is complete */ - usbcmd = readl ( xhci->op + XHCI_OP_USBCMD ); +// usbcmd = readl ( xhci->op + XHCI_OP_USBCMD ); + usbcmd = readl ( xhci->op_addr + XHCI_OP_USBCMD ); if ( ! ( usbcmd & XHCI_USBCMD_HCRST ) ) return 0; From e30c4e662fbd0d9bbc339c198237c2219e63ab8c Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 1 Jul 2024 05:01:14 -0700 Subject: [PATCH 067/198] Modify xhci_port_protocol, xhci_supported_protocol and xhci_legacy_release so that the xHCI can adapt to XiZi AIOT --- .../drivers/usb/components/port/xhci/xhci.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index c87ec3293..292af3f2c 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -420,7 +420,8 @@ static void xhci_legacy_release ( struct xhci_host *xhci ) { } /* Release ownership */ - writeb ( 0, xhci->cap + xhci->legacy + XHCI_USBLEGSUP_OS ); +// writeb ( 0, xhci->cap + xhci->legacy + XHCI_USBLEGSUP_OS ); + writeb ( 0, xhci->cap_addr + xhci->legacy + XHCI_USBLEGSUP_OS ); USB_LOG_DBG("XHCI %s released ownership to BIOS\n", xhci->name ); } @@ -586,7 +587,8 @@ static unsigned int xhci_port_protocol ( struct xhci_host *xhci, return 0; /* Determine protocol version */ - revision = readl ( xhci->cap + supported + XHCI_SUPPORTED_REVISION ); +// revision = readl ( xhci->cap + supported + XHCI_SUPPORTED_REVISION ); + revision = readl ( xhci->cap_addr + supported + XHCI_SUPPORTED_REVISION ); protocol = XHCI_SUPPORTED_REVISION_VER ( revision ); /* Describe port protocol */ @@ -599,11 +601,14 @@ static unsigned int xhci_port_protocol ( struct xhci_host *xhci, type = XHCI_SUPPORTED_SLOT_TYPE ( slot ); USB_LOG_DBG("XHCI %s-%d %sv%04x type %d \r\n", xhci->name, port, name.text, protocol, type ); - ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS ); +// ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS ); + ports = readl ( xhci->cap_addr + supported + XHCI_SUPPORTED_PORTS ); psic = XHCI_SUPPORTED_PORTS_PSIC ( ports ); if ( psic ) { USB_LOG_DBG(" speeds \r\n" ); for ( i = 0 ; i < psic ; i++ ) { +// psi = readl ( xhci->cap + supported + +// XHCI_SUPPORTED_PSI ( i ) ); psi = readl ( xhci->cap + supported + XHCI_SUPPORTED_PSI ( i ) ); psiv = XHCI_SUPPORTED_PSI_VALUE ( psi ); @@ -1209,13 +1214,16 @@ static int xhci_port_speed ( struct xhci_host *xhci, unsigned int port, return -ENOTSUP; /* Get protocol speed ID count */ - ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS ); +// ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS ); + ports = readl ( xhci->cap_addr + supported + XHCI_SUPPORTED_PORTS ); psic = XHCI_SUPPORTED_PORTS_PSIC ( ports ); /* Use protocol speed ID table unless device is known to be faulty */ /* Iterate over PSI dwords looking for a match */ for ( i = 0 ; i < psic ; i++ ) { - psi = readl ( xhci->cap + supported + +// psi = readl ( xhci->cap + supported + +// XHCI_SUPPORTED_PSI ( i ) ); + psi = readl ( xhci->cap_addr + supported + XHCI_SUPPORTED_PSI ( i ) ); if ( psiv == XHCI_SUPPORTED_PSI_VALUE ( psi ) ) { mantissa = XHCI_SUPPORTED_PSI_MANTISSA ( psi ); From ac3527bbc2e026a48a915f597b59d8ab93558733 Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 1 Jul 2024 05:03:28 -0700 Subject: [PATCH 068/198] Modify xhci_port_protocol, xhci_supported_protocol and xhci_legacy_release so that the xHCI can adapt to XiZi AIOT --- .../XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 292af3f2c..11167cbb9 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -522,7 +522,8 @@ static unsigned int xhci_supported_protocol ( struct xhci_host *xhci, supported ) ) ) { /* Determine port range */ - ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS ); +// ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS ); + ports = readl ( xhci->cap_addr + supported + XHCI_SUPPORTED_PORTS ); offset = XHCI_SUPPORTED_PORTS_OFFSET ( ports ); count = XHCI_SUPPORTED_PORTS_COUNT ( ports ); From b2c3a24f3512f1d26d8bd716a170020e46c4c34d Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 1 Jul 2024 05:18:53 -0700 Subject: [PATCH 069/198] Modify xhci_port_protocol, xhci_supported_protocol and xhci_legacy_release so that the xHCI can adapt to XiZi AIOT --- .../XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 11167cbb9..e0020f1e2 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -610,7 +610,7 @@ static unsigned int xhci_port_protocol ( struct xhci_host *xhci, for ( i = 0 ; i < psic ; i++ ) { // psi = readl ( xhci->cap + supported + // XHCI_SUPPORTED_PSI ( i ) ); - psi = readl ( xhci->cap + supported + + psi = readl ( xhci->cap_addr + supported + XHCI_SUPPORTED_PSI ( i ) ); psiv = XHCI_SUPPORTED_PSI_VALUE ( psi ); USB_LOG_DBG(" %d:%s \r\n", psiv, xhci_speed_name ( psi ) ); From 12e5b67108855288fd701d671afaff262e26b276 Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 2 Jul 2024 19:48:07 -0700 Subject: [PATCH 070/198] update kernel codes --- .../services/lib/usyscall/usyscall.c | 271 ++++++------- .../services/lib/usyscall/usyscall.h | 203 +++++----- .../XiZi_AIoT/softkernel/include/syscall.h | 228 +++++------ .../XiZi_AIoT/softkernel/syscall/sys_mmap.c | 138 +++---- .../XiZi_AIoT/softkernel/syscall/sys_state.c | 358 +++++++++--------- .../XiZi_AIoT/softkernel/syscall/syscall.c | 178 ++++----- .../softkernel/trap/clock_irq_handler.c | 146 +++---- 7 files changed, 789 insertions(+), 733 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.c b/Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.c index f975d5aaf..48cfdd30b 100644 --- a/Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.c +++ b/Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.c @@ -1,132 +1,141 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ -#include "usyscall.h" -#include "libmem.h" - -int spawn(struct Session* session, int fd, ipc_read_fn ipc_read, ipc_fsize_fn ipc_fsize, char* name, char** argv) -{ - /* read elf image */ - int file_size = ipc_fsize(session, fd); - void* img = malloc(file_size); - int read_len = 0; - while (read_len < file_size) { - int cur_read_len = file_size - read_len < 4096 ? file_size - read_len : 4096; - if (cur_read_len < 0) { - return -1; - } - read_len += ipc_read(session, fd, (char*)((uintptr_t)img + read_len), read_len, cur_read_len); - } - /* sys call */ - int ret = syscall(SYSCALL_SPAWN, (uintptr_t)img, (uintptr_t)name, (uintptr_t)argv, 0); - free(img); - return ret; -} - -int thread(void* entry, const char* name, char** argv) -{ - return syscall(SYSCALL_THREAD, (uintptr_t)entry, (uintptr_t)name, (uintptr_t)argv, 0); -} - -void exit(int status) -{ - syscall(SYSCALL_EXIT, (uintptr_t)status, 0, 0, 0); -} - -int yield(task_yield_reason reason) -{ - return syscall(SYSCALL_YIELD, (uintptr_t)reason, 0, 0, 0); -} - -int kill(int pid) -{ - return syscall(SYSCALL_KILL, (intptr_t)pid, 0, 0, 0); -} - -int register_server(char* name) -{ - return syscall(SYSCALL_SERVER, (intptr_t)name, 0, 0, 0); -} - -int session(char* path, int capacity, struct Session* user_session) -{ - return syscall(SYSCALL_SESSION, (intptr_t)path, (intptr_t)capacity, (intptr_t)user_session, 0); -} - -int poll_session(struct Session* userland_session_arr, int arr_capacity) -{ - return syscall(SYSCALL_POLL_SESSION, (intptr_t)userland_session_arr, (intptr_t)arr_capacity, 0, 0); -} - -int close_session(struct Session* session) -{ - return syscall(SYSCALL_CLOSE_SESSION, (intptr_t)session, 0, 0, 0); -} - -int get_memblock_info(sys_state_info* info) -{ - return syscall(SYSCALL_SYS_STATE, SYS_STATE_MEMBLOCK_INFO, (intptr_t)info, 0, 0); -} - -int set_priority(sys_state_info* info) -{ - return syscall(SYSCALL_SYS_STATE, SYS_STATE_SET_TASK_PRIORITY, (intptr_t)info, 0, 0); -} - -int task_heap_base() -{ - return syscall(SYSCALL_SYS_STATE, SYS_STATE_GET_HEAP_BASE, 0, 0, 0); -} - -int show_task() -{ - return syscall(SYSCALL_SYS_STATE, SYS_STATE_SHOW_TASKS, 0, 0, 0); -} - -int show_mem() -{ - return syscall(SYSCALL_SYS_STATE, SYS_STATE_SHOW_MEM_INFO, 0, 0, 0); -} - -int show_cpu() -{ - return syscall(SYSCALL_SYS_STATE, SYS_STATE_SHOW_CPU_INFO, 0, 0, 0); -} - -int mmap(uintptr_t vaddr, uintptr_t paddr, int len, bool is_dev) -{ - return syscall(SYSCALL_MMAP, vaddr, paddr, (intptr_t)len, (intptr_t)is_dev); -} - -int register_irq(int irq, int opcode) -{ - return syscall(SYSCALL_REGISTER_IRQ, (intptr_t)irq, (intptr_t)opcode, 0, 0); -} - -int semaphore_new(int val) -{ - return syscall(SYSCALL_SEMAPHORE, (intptr_t)SYS_SEM_NEW, (intptr_t)val, 0, 0); -} - -bool semaphore_free(int sem_id) -{ - return syscall(SYSCALL_SEMAPHORE, (intptr_t)SYS_SEM_FREE, (intptr_t)sem_id, 0, 0); -} - -bool semaphore_wait(int sem_id) -{ - return syscall(SYSCALL_SEMAPHORE, (intptr_t)SYS_SEM_WAIT, (intptr_t)sem_id, 0, 0); -} - -bool semaphore_signal(int sem_id) -{ - return syscall(SYSCALL_SEMAPHORE, (intptr_t)SYS_SEM_SIGNAL, (intptr_t)sem_id, 0, 0); +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +#include "usyscall.h" +#include "libmem.h" + +int spawn(struct Session* session, int fd, ipc_read_fn ipc_read, ipc_fsize_fn ipc_fsize, char* name, char** argv) +{ + /* read elf image */ + int file_size = ipc_fsize(session, fd); + void* img = malloc(file_size); + int read_len = 0; + while (read_len < file_size) { + int cur_read_len = file_size - read_len < 4096 ? file_size - read_len : 4096; + if (cur_read_len < 0) { + return -1; + } + read_len += ipc_read(session, fd, (char*)((uintptr_t)img + read_len), read_len, cur_read_len); + } + /* sys call */ + int ret = syscall(SYSCALL_SPAWN, (uintptr_t)img, (uintptr_t)name, (uintptr_t)argv, 0); + free(img); + return ret; +} + +int thread(void* entry, const char* name, char** argv) +{ + return syscall(SYSCALL_THREAD, (uintptr_t)entry, (uintptr_t)name, (uintptr_t)argv, 0); +} + +void exit(int status) +{ + syscall(SYSCALL_EXIT, (uintptr_t)status, 0, 0, 0); +} + +int yield(task_yield_reason reason) +{ + return syscall(SYSCALL_YIELD, (uintptr_t)reason, 0, 0, 0); +} + +int kill(int pid) +{ + return syscall(SYSCALL_KILL, (intptr_t)pid, 0, 0, 0); +} + +int register_server(char* name) +{ + return syscall(SYSCALL_SERVER, (intptr_t)name, 0, 0, 0); +} + +int session(char* path, int capacity, struct Session* user_session) +{ + return syscall(SYSCALL_SESSION, (intptr_t)path, (intptr_t)capacity, (intptr_t)user_session, 0); +} + +int poll_session(struct Session* userland_session_arr, int arr_capacity) +{ + return syscall(SYSCALL_POLL_SESSION, (intptr_t)userland_session_arr, (intptr_t)arr_capacity, 0, 0); +} + +int close_session(struct Session* session) +{ + return syscall(SYSCALL_CLOSE_SESSION, (intptr_t)session, 0, 0, 0); +} + +int get_memblock_info(sys_state_info* info) +{ + return syscall(SYSCALL_SYS_STATE, SYS_STATE_MEMBLOCK_INFO, (intptr_t)info, 0, 0); +} + +int set_priority(sys_state_info* info) +{ + return syscall(SYSCALL_SYS_STATE, SYS_STATE_SET_TASK_PRIORITY, (intptr_t)info, 0, 0); +} + +int task_heap_base() +{ + return syscall(SYSCALL_SYS_STATE, SYS_STATE_GET_HEAP_BASE, 0, 0, 0); +} + +int show_task() +{ + return syscall(SYSCALL_SYS_STATE, SYS_STATE_SHOW_TASKS, 0, 0, 0); +} + +int show_mem() +{ + return syscall(SYSCALL_SYS_STATE, SYS_STATE_SHOW_MEM_INFO, 0, 0, 0); +} + +int show_cpu() +{ + return syscall(SYSCALL_SYS_STATE, SYS_STATE_SHOW_CPU_INFO, 0, 0, 0); +} + +uintptr_t mmap(uintptr_t vaddr, uintptr_t paddr, int len, bool is_dev) +{ + uintptr_t vaddr_inner = vaddr, paddr_inner = paddr; + if (syscall(SYSCALL_MMAP, (intptr_t)&vaddr_inner, (intptr_t)&paddr_inner, (intptr_t)len, (intptr_t)is_dev) < 0) { + return (uintptr_t)NULL; + } + return vaddr_inner; +} + +int naive_mmap(uintptr_t* vaddr, uintptr_t* paddr, int len, bool is_dev) +{ + return syscall(SYSCALL_MMAP, (uintptr_t)vaddr, (intptr_t)paddr, (intptr_t)len, (intptr_t)is_dev); +} + +int register_irq(int irq, int opcode) +{ + return syscall(SYSCALL_REGISTER_IRQ, (intptr_t)irq, (intptr_t)opcode, 0, 0); +} + +int semaphore_new(int val) +{ + return syscall(SYSCALL_SEMAPHORE, (intptr_t)SYS_SEM_NEW, (intptr_t)val, 0, 0); +} + +bool semaphore_free(int sem_id) +{ + return syscall(SYSCALL_SEMAPHORE, (intptr_t)SYS_SEM_FREE, (intptr_t)sem_id, 0, 0); +} + +bool semaphore_wait(int sem_id) +{ + return syscall(SYSCALL_SEMAPHORE, (intptr_t)SYS_SEM_WAIT, (intptr_t)sem_id, 0, 0); +} + +bool semaphore_signal(int sem_id) +{ + return syscall(SYSCALL_SEMAPHORE, (intptr_t)SYS_SEM_SIGNAL, (intptr_t)sem_id, 0, 0); } \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.h b/Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.h index ddb0cf0af..8adca0de8 100644 --- a/Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.h +++ b/Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.h @@ -1,100 +1,105 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ -#pragma once -#include - -#include "libserial.h" -#include "session.h" - -// clang-format off -#define SYSCALL_TEST 0 -#define SYSCALL_SPAWN 1 // generate a brand new task to run elf -#define SYSCALL_EXIT 2 // exit task, delete the task cb -#define SYSCALL_YIELD 3 // yield task, go to scheduler - -#define SYSCALL_MMAP 4 // map a virt page to phy page -#define SYSCALL_SERVER 5 // register current task as a server -#define SYSCALL_SESSION 6 // create a session to a server -#define SYSCALL_POLL_SESSION 7 // server poll for it's server sessions -#define SYSCALL_CLOSE_SESSION 8 // client close it's client sessions - -#define SYSCALL_THREAD 9 // generate a thread using old memspace -#define SYSCALL_SYS_STATE 10 // run system state -#define SYSCALL_REGISTER_IRQ 11 // - -#define SYSCALL_KILL 12 // kill the task by id - -#define SYSCALL_SEMAPHORE 13 // semaphore related operations -// clang-format on - -typedef enum { - SYS_STATE_TEST = 0, - SYS_STATE_SET_TASK_PRIORITY, - SYS_STATE_GET_HEAP_BASE, - SYS_STATE_MEMBLOCK_INFO, - SYS_STATE_SHOW_TASKS, - SYS_STATE_SHOW_MEM_INFO, - SYS_STATE_SHOW_CPU_INFO, -} sys_state_option; - -typedef enum { - SYS_TASK_YIELD_NO_REASON = 0x0, - SYS_TASK_YIELD_FOREVER = 0x1, - SYS_TASK_YIELD_BLOCK_IPC = 0x2, -} task_yield_reason; - -typedef union { - struct { - uintptr_t memblock_start; - uintptr_t memblock_end; - } memblock_info; - int priority; -} sys_state_info; - -typedef enum { - SYS_SEM_NEW = 0, - SYS_SEM_FREE, - SYS_SEM_SIGNAL, - SYS_SEM_WAIT, -} sys_sem_option; - -typedef int (*ipc_read_fn)(struct Session* session, int fd, char* dst, int offset, int len); -typedef int (*ipc_fsize_fn)(struct Session* session, int fd); -typedef int (*ipc_write_fn)(struct Session* session, int fd, char* src, int offset, int len); - -int syscall(int sys_num, intptr_t a1, intptr_t a2, intptr_t a3, intptr_t a4); - -int spawn(struct Session* session, int fd, ipc_read_fn ipc_read, ipc_fsize_fn ipc_fsize, char* name, char** argv); -int thread(void* entry, const char* name, char** argv); -void exit(int status); -int yield(task_yield_reason reason); -int kill(int pid); - -int register_server(char* name); -int session(char* path, int capacity, struct Session* user_session); -int poll_session(struct Session* userland_session_arr, int arr_capacity); -int close_session(struct Session* session); -int register_irq(int irq, int opcode); - -int mmap(uintptr_t vaddr, uintptr_t paddr, int len, bool is_dev); - -int task_heap_base(); -int get_memblock_info(sys_state_info* info); -int set_priority(sys_state_info* info); -int show_task(); -int show_mem(); -int show_cpu(); - -int semaphore_new(int val); -bool semaphore_free(int sem_id); -bool semaphore_wait(int sem_id); +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +#pragma once +#include + +#include "libserial.h" +#include "session.h" + +// clang-format off +#define SYSCALL_TEST 0 +#define SYSCALL_SPAWN 1 // generate a brand new task to run elf +#define SYSCALL_EXIT 2 // exit task, delete the task cb +#define SYSCALL_YIELD 3 // yield task, go to scheduler + +#define SYSCALL_MMAP 4 // map a virt page to phy page +#define SYSCALL_SERVER 5 // register current task as a server +#define SYSCALL_SESSION 6 // create a session to a server +#define SYSCALL_POLL_SESSION 7 // server poll for it's server sessions +#define SYSCALL_CLOSE_SESSION 8 // client close it's client sessions + +#define SYSCALL_THREAD 9 // generate a thread using old memspace +#define SYSCALL_SYS_STATE 10 // run system state +#define SYSCALL_REGISTER_IRQ 11 // + +#define SYSCALL_KILL 12 // kill the task by id + +#define SYSCALL_SEMAPHORE 13 // semaphore related operations +// clang-format on + +typedef enum { + SYS_STATE_TEST = 0, + SYS_STATE_SET_TASK_PRIORITY, + SYS_STATE_GET_HEAP_BASE, + SYS_STATE_MEMBLOCK_INFO, + SYS_STATE_SHOW_TASKS, + SYS_STATE_SHOW_MEM_INFO, + SYS_STATE_SHOW_CPU_INFO, + SYS_STATE_GET_CURRENT_TICK, + SYS_STATE_GET_CURRENT_SECOND, +} sys_state_option; + +typedef enum { + SYS_TASK_YIELD_NO_REASON = 0x0, + SYS_TASK_YIELD_FOREVER = 0x1, + SYS_TASK_YIELD_BLOCK_IPC = 0x2, +} task_yield_reason; + +typedef union { + struct { + uintptr_t memblock_start; + uintptr_t memblock_end; + } memblock_info; + int priority; + uintptr_t current_tick; + uintptr_t current_second; +} sys_state_info; + +typedef enum { + SYS_SEM_NEW = 0, + SYS_SEM_FREE, + SYS_SEM_SIGNAL, + SYS_SEM_WAIT, +} sys_sem_option; + +typedef int (*ipc_read_fn)(struct Session* session, int fd, char* dst, int offset, int len); +typedef int (*ipc_fsize_fn)(struct Session* session, int fd); +typedef int (*ipc_write_fn)(struct Session* session, int fd, char* src, int offset, int len); + +int syscall(int sys_num, intptr_t a1, intptr_t a2, intptr_t a3, intptr_t a4); + +int spawn(struct Session* session, int fd, ipc_read_fn ipc_read, ipc_fsize_fn ipc_fsize, char* name, char** argv); +int thread(void* entry, const char* name, char** argv); +void exit(int status); +int yield(task_yield_reason reason); +int kill(int pid); + +int register_server(char* name); +int session(char* path, int capacity, struct Session* user_session); +int poll_session(struct Session* userland_session_arr, int arr_capacity); +int close_session(struct Session* session); +int register_irq(int irq, int opcode); + +uintptr_t mmap(uintptr_t vaddr, uintptr_t paddr, int len, bool is_dev); +int naive_mmap(uintptr_t* vaddr, uintptr_t* paddr, int len, bool is_dev); + +int task_heap_base(); +int get_memblock_info(sys_state_info* info); +int set_priority(sys_state_info* info); +int show_task(); +int show_mem(); +int show_cpu(); + +int semaphore_new(int val); +bool semaphore_free(int sem_id); +bool semaphore_wait(int sem_id); bool semaphore_signal(int sem_id); \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/softkernel/include/syscall.h b/Ubiquitous/XiZi_AIoT/softkernel/include/syscall.h index 4e1ba2a7a..13e5e845d 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/include/syscall.h +++ b/Ubiquitous/XiZi_AIoT/softkernel/include/syscall.h @@ -1,112 +1,116 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ -/** - * @file syscall.h - * @brief syscall header - * @version 3.0 - * @author AIIT XUOS Lab - * @date 2023.08.25 - */ - -/************************************************* -File name: syscall.h -Description: syscall header -Others: -History: -1. Date: 2023-08-28 -Author: AIIT XUOS Lab -Modification: -1. first version -*************************************************/ -#pragma once - -// clang-format off -#define SYSCALL_TEST 0 -#define SYSCALL_SPAWN 1 // generate a brand new task to run elf -#define SYSCALL_EXIT 2 // exit task, delete the task cb -#define SYSCALL_YIELD 3 // yield task, go to scheduler - -#define SYSCALL_MMAP 4 // map a virt page to phy page -#define SYSCALL_SERVER 5 // register current task as a server -#define SYSCALL_SESSION 6 // create a session to a server -#define SYSCALL_POLL_SESSION 7 // server poll for it's server sessions -#define SYSCALL_CLOSE_SESSION 8 // client close it's client sessions - -#define SYSCALL_THREAD 9 // generate a thread using old memspace -#define SYSCALL_SYS_STATE 10 // run system state -#define SYSCALL_REGISTER_IRQ 11 // - -#define SYSCALL_KILL 12 // kill the task by id - -#define SYSCALL_SEMAPHORE 13 // semaphore related operations -// clang-format on - -#ifndef __ASSEMBLER__ -#include - -#include "share_page.h" -#include "task.h" - -typedef enum { - SYS_STATE_TEST = 0, - SYS_STATE_SET_TASK_PRIORITY, - SYS_STATE_GET_HEAP_BASE, - SYS_STATE_MEMBLOCK_INFO, - SYS_STATE_SHOW_TASKS, - SYS_STATE_SHOW_MEM_INFO, - SYS_STATE_SHOW_CPU_INFO, -} sys_state_option; - -typedef enum { - SYS_TASK_YIELD_NO_REASON = 0x0, - SYS_TASK_YIELD_FOREVER = 0x1, - SYS_TASK_YIELD_BLOCK_IPC = 0x2, -} task_yield_reason; - -typedef union { - struct { - uintptr_t memblock_start; - uintptr_t memblock_end; - } memblock_info; - int priority; -} sys_state_info; - -typedef enum { - SYS_SEM_NEW = 0, - SYS_SEM_FREE, - SYS_SEM_SIGNAL, - SYS_SEM_WAIT, -} sys_sem_option; - -int syscall(int sys_num, uintptr_t param1, uintptr_t param2, uintptr_t param3, uintptr_t param4); - -int sys_spawn(char* img_start, char* name, char** argv); -int sys_thread(uintptr_t entry, char* name, char** argv); -int sys_exit(struct Thread* ptask); -int sys_yield(task_yield_reason reason); -int sys_kill(int id); - -int sys_register_as_server(char* name); -int sys_connect_session(char* path, int capacity, struct Session* user_session); -int sys_poll_session(struct Session* userland_session_arr, int arr_capacity); -int sys_close_session(struct Thread* task, struct Session* session); - -int sys_exec(char* img_start, char* name, char** argv); -int sys_state(sys_state_option option, sys_state_info* info); -int sys_mmap(uintptr_t vaddr, uintptr_t paddr, int len, int is_dev); - -int sys_register_irq(int irq_num, int irq_opcode); -int sys_unbind_irq_all(struct Thread* task); -int sys_unbind_irq(struct Thread* task, int irq_num); - -int sys_semaphore(sys_sem_option op, int sem_id); -#endif +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file syscall.h + * @brief syscall header + * @version 3.0 + * @author AIIT XUOS Lab + * @date 2023.08.25 + */ + +/************************************************* +File name: syscall.h +Description: syscall header +Others: +History: +1. Date: 2023-08-28 +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#pragma once + +// clang-format off +#define SYSCALL_TEST 0 +#define SYSCALL_SPAWN 1 // generate a brand new task to run elf +#define SYSCALL_EXIT 2 // exit task, delete the task cb +#define SYSCALL_YIELD 3 // yield task, go to scheduler + +#define SYSCALL_MMAP 4 // map a virt page to phy page +#define SYSCALL_SERVER 5 // register current task as a server +#define SYSCALL_SESSION 6 // create a session to a server +#define SYSCALL_POLL_SESSION 7 // server poll for it's server sessions +#define SYSCALL_CLOSE_SESSION 8 // client close it's client sessions + +#define SYSCALL_THREAD 9 // generate a thread using old memspace +#define SYSCALL_SYS_STATE 10 // run system state +#define SYSCALL_REGISTER_IRQ 11 // + +#define SYSCALL_KILL 12 // kill the task by id + +#define SYSCALL_SEMAPHORE 13 // semaphore related operations +// clang-format on + +#ifndef __ASSEMBLER__ +#include + +#include "share_page.h" +#include "task.h" + +typedef enum { + SYS_STATE_TEST = 0, + SYS_STATE_SET_TASK_PRIORITY, + SYS_STATE_GET_HEAP_BASE, + SYS_STATE_MEMBLOCK_INFO, + SYS_STATE_SHOW_TASKS, + SYS_STATE_SHOW_MEM_INFO, + SYS_STATE_SHOW_CPU_INFO, + SYS_STATE_GET_CURRENT_TICK, + SYS_STATE_GET_CURRENT_SECOND, +} sys_state_option; + +typedef enum { + SYS_TASK_YIELD_NO_REASON = 0x0, + SYS_TASK_YIELD_FOREVER = 0x1, + SYS_TASK_YIELD_BLOCK_IPC = 0x2, +} task_yield_reason; + +typedef union { + struct { + uintptr_t memblock_start; + uintptr_t memblock_end; + } memblock_info; + int priority; + uintptr_t current_tick; + uintptr_t current_second; +} sys_state_info; + +typedef enum { + SYS_SEM_NEW = 0, + SYS_SEM_FREE, + SYS_SEM_SIGNAL, + SYS_SEM_WAIT, +} sys_sem_option; + +int syscall(int sys_num, uintptr_t param1, uintptr_t param2, uintptr_t param3, uintptr_t param4); + +int sys_spawn(char* img_start, char* name, char** argv); +int sys_thread(uintptr_t entry, char* name, char** argv); +int sys_exit(struct Thread* ptask); +int sys_yield(task_yield_reason reason); +int sys_kill(int id); + +int sys_register_as_server(char* name); +int sys_connect_session(char* path, int capacity, struct Session* user_session); +int sys_poll_session(struct Session* userland_session_arr, int arr_capacity); +int sys_close_session(struct Thread* task, struct Session* session); + +int sys_exec(char* img_start, char* name, char** argv); +int sys_state(sys_state_option option, sys_state_info* info); +int sys_mmap(uintptr_t* vaddr, uintptr_t* paddr, int len, int is_dev); + +int sys_register_irq(int irq_num, int irq_opcode); +int sys_unbind_irq_all(struct Thread* task); +int sys_unbind_irq(struct Thread* task, int irq_num); + +int sys_semaphore(sys_sem_option op, int sem_id); +#endif diff --git a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_mmap.c b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_mmap.c index 1c94c1d5f..432d910e6 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_mmap.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_mmap.c @@ -1,69 +1,71 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ -/** - * @file sys_mmap.c - * @brief map task phy address to virt address - * @version 3.0 - * @author AIIT XUOS Lab - * @date 2023.08.25 - */ - -/************************************************* -File name: sys_mmap.c -Description: map task phy address to virt address -Others: -History: -1. Date: 2023-08-28 -Author: AIIT XUOS Lab -Modification: -1. first version -*************************************************/ -#include - -#include "assert.h" -#include "kalloc.h" -#include "multicores.h" -#include "share_page.h" -#include "syscall.h" -#include "task.h" - -int sys_mmap(uintptr_t vaddr, uintptr_t paddr, int len, int is_dev) -{ - struct Thread* cur_task = cur_cpu()->task; - assert(cur_task != NULL); - - int true_len = ALIGNUP(len, PAGE_SIZE); - - if (paddr != (uintptr_t)NULL) { - if (xizi_share_page_manager.task_map_pages(cur_task, vaddr, paddr, true_len / PAGE_SIZE, is_dev) == (uintptr_t)NULL) { - return -1; - } - } else { - int load_len = 0; - uintptr_t load_vaddr = vaddr; - while (load_len < true_len) { - char* paddr = raw_alloc(PAGE_SIZE); - if (paddr == NULL) { - return -1; - } - if (xizi_share_page_manager.task_map_pages(cur_task, load_vaddr, (uintptr_t)paddr, 1, false) == (uintptr_t)NULL) { - raw_free(paddr); - return -1; - } - load_vaddr += PAGE_SIZE; - load_len += PAGE_SIZE; - } - } - - cur_task->memspace->mem_size += true_len; - return vaddr + true_len; +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file sys_mmap.c + * @brief map task phy address to virt address + * @version 3.0 + * @author AIIT XUOS Lab + * @date 2023.08.25 + */ + +/************************************************* +File name: sys_mmap.c +Description: map task phy address to virt address +Others: +History: +1. Date: 2023-08-28 +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#include + +#include "assert.h" +#include "kalloc.h" +#include "multicores.h" +#include "share_page.h" +#include "syscall.h" +#include "task.h" + +int sys_mmap(uintptr_t* vaddr, uintptr_t* paddr, int len, int is_dev) +{ + struct Thread* cur_task = cur_cpu()->task; + assert(cur_task != NULL); + + int true_len = ALIGNUP(len, PAGE_SIZE); + + if (*paddr != (uintptr_t)NULL) { + if (xizi_share_page_manager.task_map_pages(cur_task, *vaddr, *paddr, true_len / PAGE_SIZE, is_dev) == (uintptr_t)NULL) { + return -1; + } + } else { + int load_len = 0; + uintptr_t load_vaddr = *vaddr; + while (load_len < true_len) { + char* new_paddr = raw_alloc(PAGE_SIZE); + if (new_paddr == NULL) { + return -1; + } + if (xizi_share_page_manager.task_map_pages(cur_task, load_vaddr, (uintptr_t)new_paddr, 1, false) == (uintptr_t)NULL) { + raw_free(new_paddr); + return -1; + } + load_vaddr += PAGE_SIZE; + load_len += PAGE_SIZE; + *paddr = (uintptr_t)new_paddr; + } + } + + cur_task->memspace->mem_size += true_len; + *vaddr = *vaddr + true_len; + return 0; } \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_state.c b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_state.c index ddc3f5f69..47817ea14 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_state.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_state.c @@ -1,170 +1,190 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ -/** - * @file sys_state.c - * @brief task ask for kernel status(for debug perpose) - * @version 3.0 - * @author AIIT XUOS Lab - * @date 2023.08.25 - */ - -/************************************************* -File name: sys_state.c -Description: task ask for kernel status(for debug perpose) -Others: -History: -1. Date: 2023-08-28 -Author: AIIT XUOS Lab -Modification: -1. first version -*************************************************/ -#include -#include - -#include "assert.h" -#include "buddy.h" -#include "log.h" -#include "multicores.h" -#include "pagetable.h" -#include "syscall.h" -#include "task.h" - -extern uint8_t _binary_fs_img_start[], _binary_fs_img_end[]; - -#define SHOWINFO_BORDER_LINE() LOG_PRINTF("******************************************************\n"); -#define SHOWTASK_TASK_BASE_INFO(task) LOG_PRINTF(" %-6d %-16s %-4d 0x%x(%-d)\n", task->tid, task->name, task->priority, task->memspace->mem_size >> 10, task->memspace->mem_size >> 10) - -void show_tasks(void) -{ - struct Thread* task = NULL; - SHOWINFO_BORDER_LINE(); - for (int i = 0; i < NR_CPU; i++) { - LOG_PRINTF("CPU %-2d: %s\n", i, (global_cpus[i].task == NULL ? "NULL" : global_cpus[i].task->name)); - } - SHOWINFO_BORDER_LINE(); - LOG_PRINTF("%-8s %-6s %-16s %-4s %-8s\n", "STAT", "ID", "TASK", "PRI", "MEM(KB)"); - DOUBLE_LIST_FOR_EACH_ENTRY(task, &xizi_task_manager.task_running_list_head, node) - { - LOG_PRINTF("%-8s", "RUNNING"); - SHOWTASK_TASK_BASE_INFO(task); - } - - for (int i = 0; i < TASK_MAX_PRIORITY; i++) { - if (IS_DOUBLE_LIST_EMPTY(&xizi_task_manager.task_list_head[i])) { - continue; - } - DOUBLE_LIST_FOR_EACH_ENTRY(task, &xizi_task_manager.task_list_head[i], node) - { - switch (task->state) { - case INIT: - LOG_PRINTF("%-8s", "INIT"); - break; - case READY: - LOG_PRINTF("%-8s", "READY"); - break; - case RUNNING: - LOG_PRINTF("%-8s", "RUNNING"); - break; - case DEAD: - LOG_PRINTF("%-8s", "DEAD"); - break; - default: - break; - } - - SHOWTASK_TASK_BASE_INFO(task); - } - } - - DOUBLE_LIST_FOR_EACH_ENTRY(task, &xizi_task_manager.task_blocked_list_head, node) - { - LOG_PRINTF("%-8s", "BLOCK"); - SHOWTASK_TASK_BASE_INFO(task); - } - - struct ksemaphore* sem = NULL; - DOUBLE_LIST_FOR_EACH_ENTRY(sem, &xizi_task_manager.semaphore_pool.sem_list_guard, sem_list_node) - { - task = NULL; - DOUBLE_LIST_FOR_EACH_ENTRY(task, &sem->wait_list_guard, node) - { - LOG_PRINTF("%-8s", "BLOCK"); - SHOWTASK_TASK_BASE_INFO(task); - } - } - - SHOWINFO_BORDER_LINE(); - return; -} - -extern struct KBuddy user_phy_freemem_buddy; -extern struct KBuddy kern_virtmem_buddy; -extern uintptr_t kernel_data_end[]; -void show_mem(void) -{ - SHOWINFO_BORDER_LINE(); - - uint64_t total = (PHY_MEM_STOP - V2P(kernel_data_end)); - uint64_t user_dynamic_free = 0; - uint64_t kernel_free = 0; - for (int j = 0; j < MAX_BUDDY_ORDER; j++) { - user_dynamic_free += user_phy_freemem_buddy.free_list[j].n_free_pages * (1 << j) * PAGE_SIZE; - kernel_free += kern_virtmem_buddy.free_list[j].n_free_pages * (1 << j) * PAGE_SIZE; - } - LOG_PRINTF("%-16s 0x%016lx\n", "TOTAL(B)", total); - LOG_PRINTF("%-16s 0x%016lx\n", "KERNEL USED(B)", (kern_virtmem_buddy.mem_end - kern_virtmem_buddy.mem_start - kernel_free)); - LOG_PRINTF("%-16s 0x%016lx\n", "LIBMEM USED(B)", (user_phy_freemem_buddy.mem_end - user_phy_freemem_buddy.mem_start - user_dynamic_free)); - LOG_PRINTF("%-16s 0x%016lx\n", "FREE(B)", user_dynamic_free + kernel_free); - - SHOWINFO_BORDER_LINE(); - return; -} - -void show_cpu(void) -{ - LOG_PRINTF("**********************************************************\n"); -#ifdef ARCH_SMP - /// @todo support smp - KPrintf(" cpu VALUE \n"); -#endif - - int cpu_id = 0; - - struct Thread* current_task = cur_cpu()->task; - assert(current_task != NULL); - - LOG_PRINTF(" ID COMMAND USED_TICKS FREE_TICKS \n"); - LOG_PRINTF(" %d %s %d %d\n", cpu_id, current_task->name, TASK_CLOCK_TICK - current_task->remain_tick, current_task->remain_tick); - - LOG_PRINTF("***********************************************************\n"); - return; -} - -int sys_state(sys_state_option option, sys_state_info* info) -{ - if (option == SYS_STATE_MEMBLOCK_INFO) { - info->memblock_info.memblock_start = (uintptr_t)V2P(_binary_fs_img_start); - info->memblock_info.memblock_end = (uintptr_t)V2P(_binary_fs_img_end); - } else if (option == SYS_STATE_GET_HEAP_BASE) { - return cur_cpu()->task->memspace->heap_base; - } else if (option == SYS_STATE_SET_TASK_PRIORITY) { - xizi_task_manager.set_cur_task_priority(info->priority); - } else if (option == SYS_STATE_SHOW_TASKS) { - show_tasks(); - } else if (option == SYS_STATE_SHOW_MEM_INFO) { - show_mem(); - } else if (option == SYS_STATE_SHOW_CPU_INFO) { - show_cpu(); - } - - return 0; +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file sys_state.c + * @brief task ask for kernel status(for debug perpose) + * @version 3.0 + * @author AIIT XUOS Lab + * @date 2023.08.25 + */ + +/************************************************* +File name: sys_state.c +Description: task ask for kernel status(for debug perpose) +Others: +History: +1. Date: 2023-08-28 +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#include +#include + +#include "assert.h" +#include "buddy.h" +#include "log.h" +#include "multicores.h" +#include "pagetable.h" +#include "syscall.h" +#include "task.h" + +extern uint8_t _binary_fs_img_start[], _binary_fs_img_end[]; + +#define SHOWINFO_BORDER_LINE() LOG_PRINTF("******************************************************\n"); +#define SHOWTASK_TASK_BASE_INFO(task) LOG_PRINTF(" %-6d %-16s %-4d 0x%x(%-d)\n", task->tid, task->name, task->priority, task->memspace->mem_size >> 10, task->memspace->mem_size >> 10) + +void show_tasks(void) +{ + struct Thread* task = NULL; + SHOWINFO_BORDER_LINE(); + for (int i = 0; i < NR_CPU; i++) { + LOG_PRINTF("CPU %-2d: %s\n", i, (global_cpus[i].task == NULL ? "NULL" : global_cpus[i].task->name)); + } + SHOWINFO_BORDER_LINE(); + LOG_PRINTF("%-8s %-6s %-16s %-4s %-8s\n", "STAT", "ID", "TASK", "PRI", "MEM(KB)"); + DOUBLE_LIST_FOR_EACH_ENTRY(task, &xizi_task_manager.task_running_list_head, node) + { + LOG_PRINTF("%-8s", "RUNNING"); + SHOWTASK_TASK_BASE_INFO(task); + } + + for (int i = 0; i < TASK_MAX_PRIORITY; i++) { + if (IS_DOUBLE_LIST_EMPTY(&xizi_task_manager.task_list_head[i])) { + continue; + } + DOUBLE_LIST_FOR_EACH_ENTRY(task, &xizi_task_manager.task_list_head[i], node) + { + switch (task->state) { + case INIT: + LOG_PRINTF("%-8s", "INIT"); + break; + case READY: + LOG_PRINTF("%-8s", "READY"); + break; + case RUNNING: + LOG_PRINTF("%-8s", "RUNNING"); + break; + case DEAD: + LOG_PRINTF("%-8s", "DEAD"); + break; + default: + break; + } + + SHOWTASK_TASK_BASE_INFO(task); + } + } + + DOUBLE_LIST_FOR_EACH_ENTRY(task, &xizi_task_manager.task_blocked_list_head, node) + { + LOG_PRINTF("%-8s", "BLOCK"); + SHOWTASK_TASK_BASE_INFO(task); + } + + struct ksemaphore* sem = NULL; + DOUBLE_LIST_FOR_EACH_ENTRY(sem, &xizi_task_manager.semaphore_pool.sem_list_guard, sem_list_node) + { + task = NULL; + DOUBLE_LIST_FOR_EACH_ENTRY(task, &sem->wait_list_guard, node) + { + LOG_PRINTF("%-8s", "BLOCK"); + SHOWTASK_TASK_BASE_INFO(task); + } + } + + SHOWINFO_BORDER_LINE(); + return; +} + +extern struct KBuddy user_phy_freemem_buddy; +extern struct KBuddy kern_virtmem_buddy; +extern uintptr_t kernel_data_end[]; +void show_mem(void) +{ + SHOWINFO_BORDER_LINE(); + + uint64_t total = (PHY_MEM_STOP - V2P(kernel_data_end)); + uint64_t user_dynamic_free = 0; + uint64_t kernel_free = 0; + for (int j = 0; j < MAX_BUDDY_ORDER; j++) { + user_dynamic_free += user_phy_freemem_buddy.free_list[j].n_free_pages * (1 << j) * PAGE_SIZE; + kernel_free += kern_virtmem_buddy.free_list[j].n_free_pages * (1 << j) * PAGE_SIZE; + } + LOG_PRINTF("%-16s 0x%016lx\n", "TOTAL(B)", total); + LOG_PRINTF("%-16s 0x%016lx\n", "KERNEL USED(B)", (kern_virtmem_buddy.mem_end - kern_virtmem_buddy.mem_start - kernel_free)); + LOG_PRINTF("%-16s 0x%016lx\n", "LIBMEM USED(B)", (user_phy_freemem_buddy.mem_end - user_phy_freemem_buddy.mem_start - user_dynamic_free)); + LOG_PRINTF("%-16s 0x%016lx\n", "FREE(B)", user_dynamic_free + kernel_free); + + SHOWINFO_BORDER_LINE(); + return; +} + +void show_cpu(void) +{ + LOG_PRINTF("**********************************************************\n"); +#ifdef ARCH_SMP + /// @todo support smp + KPrintf(" cpu VALUE \n"); +#endif + + int cpu_id = 0; + + struct Thread* current_task = cur_cpu()->task; + assert(current_task != NULL); + + LOG_PRINTF(" ID COMMAND USED_TICKS FREE_TICKS \n"); + LOG_PRINTF(" %d %s %d %d\n", cpu_id, current_task->name, TASK_CLOCK_TICK - current_task->remain_tick, current_task->remain_tick); + + LOG_PRINTF("***********************************************************\n"); + return; +} + +int sys_state(sys_state_option option, sys_state_info* info) +{ + switch (option) { + case SYS_STATE_MEMBLOCK_INFO: { + info->memblock_info.memblock_start = (uintptr_t)V2P(_binary_fs_img_start); + info->memblock_info.memblock_end = (uintptr_t)V2P(_binary_fs_img_end); + break; + } + case SYS_STATE_GET_HEAP_BASE: + return cur_cpu()->task->memspace->heap_base; + case SYS_STATE_SET_TASK_PRIORITY: + xizi_task_manager.set_cur_task_priority(info->priority); + break; + case SYS_STATE_SHOW_TASKS: + show_tasks(); + break; + case SYS_STATE_SHOW_MEM_INFO: + show_mem(); + break; + case SYS_STATE_SHOW_CPU_INFO: + show_cpu(); + break; + case SYS_STATE_GET_CURRENT_TICK: { + extern void hw_current_tick(uintptr_t * tick); + hw_current_tick(&info->current_tick); + break; + } + case SYS_STATE_GET_CURRENT_SECOND: { + extern void hw_current_second(uintptr_t * tick); + hw_current_second(&info->current_second); + break; + } + case SYS_STATE_TEST: + default: + break; + } + + return 0; } \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/softkernel/syscall/syscall.c b/Ubiquitous/XiZi_AIoT/softkernel/syscall/syscall.c index 4a15e6389..f5cd4c528 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/syscall/syscall.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/syscall/syscall.c @@ -1,90 +1,90 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ -/** - * @file syscall.c - * @brief syscall distributor - * @version 3.0 - * @author AIIT XUOS Lab - * @date 2023.08.25 - */ - -/************************************************* -File name: syscall.c -Description: syscall distributor -Others: -History: -1. Date: 2023-08-28 -Author: AIIT XUOS Lab -Modification: -1. first version -*************************************************/ -#include "log.h" -#include "multicores.h" -#include "trap_common.h" - -#include "syscall.h" - -int syscall(int sys_num, uintptr_t param1, uintptr_t param2, uintptr_t param3, uintptr_t param4) -{ - int ret = -1; - - switch (sys_num) { - case SYSCALL_TEST: - ret = 0; - break; - case SYSCALL_SPAWN: - ret = sys_spawn((char*)param1, (char*)param2, (char**)param3); - break; - case SYSCALL_THREAD: - ret = sys_thread((uintptr_t)param1, (char*)param2, (char**)param3); - break; - case SYSCALL_EXIT: - ret = sys_exit(cur_cpu()->task); - break; - case SYSCALL_YIELD: - ret = sys_yield((task_yield_reason)param1); - break; - case SYSCALL_SERVER: - ret = sys_register_as_server((char*)param1); - break; - case SYSCALL_SESSION: - ret = sys_connect_session((char*)param1, (int)param2, (struct Session*)param3); - break; - case SYSCALL_POLL_SESSION: - ret = sys_poll_session((struct Session*)param1, (int)param2); - break; - case SYSCALL_CLOSE_SESSION: - ret = sys_close_session(cur_cpu()->task, (struct Session*)param1); - break; - case SYSCALL_SYS_STATE: - ret = sys_state(param1, (sys_state_info*)param2); - break; - case SYSCALL_MMAP: - ret = sys_mmap(param1, param2, (int)param3, (int)param4); - break; - case SYSCALL_REGISTER_IRQ: - ret = sys_register_irq((int)param1, (int)param2); - break; - case SYSCALL_KILL: - ret = sys_kill((int)param1); - break; - case SYSCALL_SEMAPHORE: - ret = sys_semaphore((sys_sem_option)param1, (int)param2); - break; - default: - ERROR("Unsurport syscall(%d) right now\n", sys_num); - ret = -1; - break; - } - - return ret; +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file syscall.c + * @brief syscall distributor + * @version 3.0 + * @author AIIT XUOS Lab + * @date 2023.08.25 + */ + +/************************************************* +File name: syscall.c +Description: syscall distributor +Others: +History: +1. Date: 2023-08-28 +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#include "log.h" +#include "multicores.h" +#include "trap_common.h" + +#include "syscall.h" + +int syscall(int sys_num, uintptr_t param1, uintptr_t param2, uintptr_t param3, uintptr_t param4) +{ + int ret = -1; + + switch (sys_num) { + case SYSCALL_TEST: + ret = 0; + break; + case SYSCALL_SPAWN: + ret = sys_spawn((char*)param1, (char*)param2, (char**)param3); + break; + case SYSCALL_THREAD: + ret = sys_thread((uintptr_t)param1, (char*)param2, (char**)param3); + break; + case SYSCALL_EXIT: + ret = sys_exit(cur_cpu()->task); + break; + case SYSCALL_YIELD: + ret = sys_yield((task_yield_reason)param1); + break; + case SYSCALL_SERVER: + ret = sys_register_as_server((char*)param1); + break; + case SYSCALL_SESSION: + ret = sys_connect_session((char*)param1, (int)param2, (struct Session*)param3); + break; + case SYSCALL_POLL_SESSION: + ret = sys_poll_session((struct Session*)param1, (int)param2); + break; + case SYSCALL_CLOSE_SESSION: + ret = sys_close_session(cur_cpu()->task, (struct Session*)param1); + break; + case SYSCALL_SYS_STATE: + ret = sys_state(param1, (sys_state_info*)param2); + break; + case SYSCALL_MMAP: + ret = sys_mmap((uintptr_t*)param1, (uintptr_t*)param2, (int)param3, (int)param4); + break; + case SYSCALL_REGISTER_IRQ: + ret = sys_register_irq((int)param1, (int)param2); + break; + case SYSCALL_KILL: + ret = sys_kill((int)param1); + break; + case SYSCALL_SEMAPHORE: + ret = sys_semaphore((sys_sem_option)param1, (int)param2); + break; + default: + ERROR("Unsurport syscall(%d) right now\n", sys_num); + ret = -1; + break; + } + + return ret; } \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/softkernel/trap/clock_irq_handler.c b/Ubiquitous/XiZi_AIoT/softkernel/trap/clock_irq_handler.c index d7a66169c..7ab8808b8 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/trap/clock_irq_handler.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/trap/clock_irq_handler.c @@ -1,66 +1,82 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ -/** - * @file clock_irq_handler.c - * @brief clock interrupt handler - * @version 3.0 - * @author AIIT XUOS Lab - * @date 2023.08.25 - */ - -/************************************************* -File name: clock_irq_handler.c -Description: clock interrupt handler -Others: -History: -1. Date: 2023-08-28 -Author: AIIT XUOS Lab -Modification: -1. first version -*************************************************/ -#include "clock_common_op.h" - -#include "actracer.h" -#include "assert.h" -#include "multicores.h" -#include "task.h" - -#include "log.h" - -static struct TraceTag clock_driver_tag; -static struct XiziClockDriver* p_clock_driver = NULL; - -bool clock_intr_handler_init(struct TraceTag* p_clock_driver_tag) -{ - clock_driver_tag = *p_clock_driver_tag; - p_clock_driver = AchieveResource(p_clock_driver_tag); - return p_clock_driver != NULL; -} - -uint64_t global_tick = 0; -int xizi_clock_handler(int irq, void* tf, void* arg) -{ - /* handle clock interrupt using driver */ - if (p_clock_driver->is_timer_expired()) { - p_clock_driver->clear_clock_intr(); - global_tick++; - struct Thread* current_task = cur_cpu()->task; - if (current_task) { - current_task->remain_tick--; - current_task->maxium_tick--; - if (current_task->remain_tick == 0) { - xizi_task_manager.task_yield_noschedule(current_task, false); - } - } - } - return 0; +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file clock_irq_handler.c + * @brief clock interrupt handler + * @version 3.0 + * @author AIIT XUOS Lab + * @date 2023.08.25 + */ + +/************************************************* +File name: clock_irq_handler.c +Description: clock interrupt handler +Others: +History: +1. Date: 2023-08-28 +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#include "clock_common_op.h" + +#include "actracer.h" +#include "assert.h" +#include "multicores.h" +#include "task.h" + +static struct TraceTag clock_driver_tag; +static struct XiziClockDriver* p_clock_driver = NULL; + +bool clock_intr_handler_init(struct TraceTag* p_clock_driver_tag) +{ + clock_driver_tag = *p_clock_driver_tag; + p_clock_driver = AchieveResource(p_clock_driver_tag); + return p_clock_driver != NULL; +} + +void hw_current_tick(uintptr_t* tick) +{ + if (p_clock_driver == NULL) { + *tick = 0; + return; + } + *tick = p_clock_driver->get_tick(); +} + +void hw_current_second(uintptr_t* second) +{ + if (p_clock_driver == NULL) { + *second = 0; + return; + } + *second = p_clock_driver->get_second(); +} + +uint64_t global_tick = 0; +int xizi_clock_handler(int irq, void* tf, void* arg) +{ + /* handle clock interrupt using driver */ + if (p_clock_driver->is_timer_expired()) { + p_clock_driver->clear_clock_intr(); + global_tick++; + struct Thread* current_task = cur_cpu()->task; + if (current_task) { + current_task->remain_tick--; + current_task->maxium_tick--; + if (current_task->remain_tick == 0) { + xizi_task_manager.task_yield_noschedule(current_task, false); + } + } + } + return 0; } \ No newline at end of file From aedc9d86fc758400b040ab3566598efa7e665c2e Mon Sep 17 00:00:00 2001 From: xj Date: Wed, 3 Jul 2024 01:19:52 -0700 Subject: [PATCH 071/198] update dcbaa functions --- .../services/drivers/usb/components/port/xhci/xhci.c | 4 ++++ .../services/drivers/usb/components/port/xhci/xhci.h | 8 ++++++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index e0020f1e2..80157a736 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -674,6 +674,7 @@ err_reset: static int xhci_dcbaa_alloc ( struct xhci_host *xhci ) { size_t len; uintptr_t dcbaap; + uint64_t dcbaap_phy; int rc; /* Allocate and initialise structure. Must be at least @@ -683,6 +684,9 @@ static int xhci_dcbaa_alloc ( struct xhci_host *xhci ) { */ len = ( ( xhci->slots + 1 ) * sizeof ( xhci->dcbaa.context[0] ) ); xhci->dcbaa.context = usb_align(xhci_align ( len ), len); + + // + if ( ! xhci->dcbaa.context ) { USB_LOG_ERR("XHCI %s could not allocate DCBAA\n", xhci->name ); rc = -ENOMEM; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h index d701eb935..aead37d00 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h @@ -859,8 +859,12 @@ struct xhci_host { /** USB legacy support capability (if present and enabled) */ unsigned int legacy; - /** Device context base address array */ - void *phy_acbaa; + /* + * Device context base address array. + * + * dcbaa_addr holds the virtual address of the dcbaa, meanwhile acbaa keeps the value that should be writen to XHCI_OP_DCBAAP. + */ + void *dcbaa_addr; struct xhci_dcbaa dcbaa; /** Scratchpad buffer */ From 57ae6140711f488398bad9121d52c538119ff11b Mon Sep 17 00:00:00 2001 From: xj Date: Wed, 3 Jul 2024 04:58:05 -0700 Subject: [PATCH 072/198] update dcbaa functions in xhci.c, and Makefile in xhci --- .../drivers/usb/components/port/xhci/Makefile | 4 +- .../drivers/usb/components/port/xhci/xhci.c | 50 +++++++++++++------ .../drivers/usb/components/port/xhci/xhci.h | 2 +- .../usb/components/port/xhci/xhci_reg.h | 6 ++- 4 files changed, 41 insertions(+), 21 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/Makefile index d2b035543..0d1219924 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/Makefile @@ -1,6 +1,6 @@ include $(KERNEL_ROOT)/services/drivers/usb/components/usb.mk -objs += usb_hc_xhci.o +objs += usb_hc_xhci.o xhci.o all: ${objs} @echo "generate $^" @@ -8,4 +8,4 @@ all: ${objs} %.o: %.c @echo "cc $^" - @${cc} ${cflags} ${c_useropts} ${INC_DIR} -o $@ -c $^ \ No newline at end of file + @${cc} ${cflags} ${c_useropts} ${INC_DIR} -o $@ -c $^ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 80157a736..844fc8e63 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -673,8 +673,7 @@ err_reset: */ static int xhci_dcbaa_alloc ( struct xhci_host *xhci ) { size_t len; - uintptr_t dcbaap; - uint64_t dcbaap_phy; + uintptr_t dcbaap_addr, dcbaap_phy; int rc; /* Allocate and initialise structure. Must be at least @@ -683,21 +682,35 @@ static int xhci_dcbaa_alloc ( struct xhci_host *xhci ) { * with a minimum of 64 bytes). */ len = ( ( xhci->slots + 1 ) * sizeof ( xhci->dcbaa.context[0] ) ); - xhci->dcbaa.context = usb_align(xhci_align ( len ), len); +// xhci->dcbaa.context = usb_align(xhci_align ( len ), len); - // + xhci->dcbaa.context = NULL; + + rc = sys_mmap(&dcbaap_addr, &dcbaap_phy, len); + + if(rc != 0){ + USB_LOG_ERR("XHCI %s could not allocate DCBAA\n", xhci->name ); + rc = -ENOMEM; + goto err_alloc; + } + + xhci->dcbaa_addr = dcbaap_addr; + +#if 0 if ( ! xhci->dcbaa.context ) { USB_LOG_ERR("XHCI %s could not allocate DCBAA\n", xhci->name ); rc = -ENOMEM; goto err_alloc; } +#endif + memset ( xhci->dcbaa.context, 0, len ); /* Program DCBAA pointer */ - dcbaap = (uintptr_t)( xhci->dcbaa.context ); - if ( ( rc = xhci_writeq ( xhci, dcbaap, - xhci->op + XHCI_OP_DCBAAP ) ) != 0 ) +// dcbaap = (uintptr_t)( xhci->dcbaa.context ); + if ( ( rc = xhci_writeq ( xhci, dcbaap_phy, + xhci->op_addr + XHCI_OP_DCBAAP ) ) != 0 ) goto err_writeq; USB_LOG_DBG("XHCI %s DCBAA at [%08lx,%08lx)\n", xhci->name, @@ -1440,8 +1453,8 @@ int xhci_event_wait(struct xhci_host *xhci, * @v value Value send to doorbell */ static inline void xhci_doorbell ( struct xhci_host *xhci, uint32_t slotid, uint32_t value ) { - - DSB(); +// DSB(); + BARRIER(); writel ( value, xhci->db + slotid * XHCI_REG_DB_SIZE ); /* bit[7:0] db target, is ep_id */ } @@ -1493,7 +1506,8 @@ static int xhci_cmd_submit(struct xhci_host *xhci, struct xhci_endpoint *ep, uni xhci_trb_queue(xhci->cmds, trb); /* pass command trb to hardware */ - DSB(); +// DSB(); + BARRIER(); xhci_doorbell(xhci, 0, 0); /* 0 = db host controller, 0 = db targe hc command */ int cc = xhci_event_wait(xhci, ep, xhci->cmds); @@ -2079,8 +2093,8 @@ static inline int xhci_configure_endpoint ( struct xhci_host *xhci, * @v input Input context */ static void -xhci_deconfigure_endpoint_input ( struct xhci_host *xhci __unused, - struct xhci_slot *slot __unused, +xhci_deconfigure_endpoint_input ( struct xhci_host *xhci, + struct xhci_slot *slot, struct xhci_endpoint *endpoint, void *input ) { struct xhci_control_context *control_ctx; @@ -2319,7 +2333,8 @@ void xhci_endpoint_message ( struct xhci_endpoint *ep, xhci_trb_queue(&(ep->reqs), &trb); /* pass command trb to hardware */ - DSB(); +// DSB(); + BARRIER(); USB_LOG_DBG("ring doorbell slot-%d ep-%d \r\n", slot->id, ep->ctx); xhci_doorbell(xhci, slot->id, ep->ctx); /* 0 = db host controller, 0 = db targe hc command */ @@ -2367,7 +2382,8 @@ void xhci_endpoint_stream ( struct xhci_endpoint *ep, xhci_trb_queue(&(ep->reqs), trb); /* pass command trb to hardware */ - DSB(); +// DSB(); + BARRIER(); xhci_doorbell(xhci, slot->id, ep->ctx); @@ -2386,7 +2402,7 @@ err_enqueue: * @v input Input context */ static void xhci_evaluate_context_input ( struct xhci_host *xhci, - struct xhci_slot *slot __unused, + struct xhci_slot *slot, struct xhci_endpoint *endpoint, void *input ) { struct xhci_control_context *control_ctx; @@ -2625,7 +2641,9 @@ void xhci_event_process(struct xhci_host *xhci) { /* check and ack event */ for (;;) { /* Stop if we reach an empty TRB */ - DSB(); +// DSB(); +// __asm__ __volatile__("dsb sy": : : "memory"); + BARRIER(); nidx = evts->nidx; /* index of dequeue trb */ cs = evts->cs; /* cycle state toggle by xHc */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h index aead37d00..98cfb9b9f 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h @@ -864,7 +864,7 @@ struct xhci_host { * * dcbaa_addr holds the virtual address of the dcbaa, meanwhile acbaa keeps the value that should be writen to XHCI_OP_DCBAAP. */ - void *dcbaa_addr; + uintptr_t dcbaa_addr; struct xhci_dcbaa dcbaa; /** Scratchpad buffer */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci_reg.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci_reg.h index e3148ed8f..3c4a7d4fa 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci_reg.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci_reg.h @@ -391,9 +391,11 @@ enum { #define BARRIER() __asm__ __volatile__("": : :"memory") #ifdef XHCI_AARCH64 -#define DSB() __asm__ __volatile__("dsb sy": : : "memory") +// #define DSB() __asm__ __volatile__("dsb sy": : : "memory") +#define DSB() __asm__ volatile("dsb ish\n\t") #else -#define DSB() __asm__ __volatile__("dsb": : : "memory") +// #define DSB() __asm__ __volatile__("dsb": : : "memory") +#define DSB() __asm__ volatile("dsb ish\n\t") #endif From ad5acb644bdc8220ed0a07b1ee5ac12fa7f0bef5 Mon Sep 17 00:00:00 2001 From: xj Date: Wed, 3 Jul 2024 06:15:24 -0700 Subject: [PATCH 073/198] fix bugs --- .../drivers/usb/components/core/usbh_core.c | 2 +- .../drivers/usb/components/mem/usb_mem.h | 1 + .../usb/components/port/xhci/usb_hc_xhci.c | 4 ++-- .../drivers/usb/components/port/xhci/xhci.c | 17 +++++++++++------ .../drivers/usb/components/port/xhci/xhci.h | 1 + .../services/drivers/usb/components/usb.mk | 7 +++++++ 6 files changed, 23 insertions(+), 9 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c index 674fe4639..1bff9fc37 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c @@ -149,7 +149,7 @@ struct usbh_hubport * usbh_root_hub_port ( struct usbh_hubport *hport ) { struct usbh_hubport *parent; /* Navigate up to root hub */ - while (parent = hport->parent->parent) { + while ((parent = hport->parent->parent)) { hport = parent; } diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h index 03fea763c..5be052e2d 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h @@ -24,6 +24,7 @@ Modification: Use usb_malloc, usb_free and usb_align functions #include #include +#include #include "usb_config.h" #define USB_MEM_ALIGNX __attribute__((aligned(CONFIG_USB_ALIGN_SIZE))) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index a79daa672..88d74882e 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -598,11 +598,11 @@ int xhci_usb_hc_init(uint32_t id){ memset(xhci, 0, sizeof(*xhci)); xhci->bus = bus; bus->priv = xhci; - if (rc = xhci_probe(xhci, usb_hc_get_register_base(id)) != 0) { + if ((rc = xhci_probe(xhci, usb_hc_get_register_base(id)) != 0)) { goto err_open; } - if (rc = xhci_open(xhci) != 0 ) { + if ((rc = xhci_open(xhci) != 0) ) { goto err_open; } diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 844fc8e63..527cdf2c1 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -81,6 +81,7 @@ Modification: Modify xhci_probe functions in order to adopt to XiZi AIOT. #include "xhci_reg.h" #include "xhci.h" #include "usb_hc_xhci.h" +#include "usyscall.h" /** @file @@ -127,7 +128,9 @@ static inline size_t xhci_align ( size_t len ) { size_t align; /* Align to own length (rounded up to a power of two) */ - align = ( 1 << fls ( len - 1 ) ); +// align = ( 1 << fls ( len - 1 ) ); +// align = ( 1 << fls ( len - 1 ) ); + align = XHCI_MIN_ALIGN; /* Round up to XHCI_MIN_ALIGN if needed */ if ( align < XHCI_MIN_ALIGN ) @@ -191,15 +194,15 @@ static void xhci_init ( struct xhci_host *xhci, void *regs ) { /* Locate capability, operational, runtime, and doorbell registers */ xhci->cap = regs; - id = usb_hc_get_register_id(regs); + id = usb_hc_get_register_id((unsigned long)regs); cap_vir_addr = usb_hc_get_register_vir_base(id); - if(!mmap(cap_vir_addr, regs, USB3_ADDR_OFFSET_UPPER_BOUND, true)){ + if(!mmap(cap_vir_addr, (uintptr_t)regs, USB3_ADDR_OFFSET_UPPER_BOUND, true)){ return; } - xhci->cap_addr = xhci->base_addr = cap_vir_addr; + xhci->cap_addr = xhci->base_addr = (void *)cap_vir_addr; // caplength = readb ( xhci->cap + XHCI_CAP_CAPLENGTH ); caplength = readb ( xhci->cap_addr + XHCI_CAP_CAPLENGTH ); @@ -687,7 +690,7 @@ static int xhci_dcbaa_alloc ( struct xhci_host *xhci ) { xhci->dcbaa.context = NULL; - rc = sys_mmap(&dcbaap_addr, &dcbaap_phy, len); + rc = naive_mmap(&dcbaap_addr, &dcbaap_phy, len, false); if(rc != 0){ USB_LOG_ERR("XHCI %s could not allocate DCBAA\n", xhci->name ); @@ -2225,7 +2228,8 @@ int xhci_work_endpoint_open ( struct xhci_host *xhci, struct xhci_slot *slot, st /* Calculate interval */ if ( ctx_type & XHCI_EP_TYPE_PERIODIC ) { - ep->interval = ( fls ( ep->interval ) - 1 ); +// ep->interval = ( fls ( ep->interval ) - 1 ); + ep->interval = 256; } ep->ctx_type = ctx_type; @@ -2643,6 +2647,7 @@ void xhci_event_process(struct xhci_host *xhci) { /* Stop if we reach an empty TRB */ // DSB(); // __asm__ __volatile__("dsb sy": : : "memory"); +// __asm__ volatile("dmb ish\n\t"); BARRIER(); nidx = evts->nidx; /* index of dequeue trb */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h index 98cfb9b9f..d653a404d 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h @@ -36,6 +36,7 @@ Modification: replant and redefine some xhci data structure, so that the cherryU #ifndef XHCI_H_ #define XHCI_H_ +#include #include "xhci_reg.h" #include "usbh_core.h" diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk index 488c3bd49..ba38d3725 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk @@ -9,6 +9,13 @@ user_ldflags = --start-group,-lgcc,-lc,--end-group cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie #cflags = -Wall -g -std=c11 endif +ifeq ($(BOARD), ok1028a-c) +toolchain ?= aarch64-none-elf- +user_ldflags = -N -Ttext 0 +cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +board_specs = $(KERNEL_ROOT)/services/app/stub.o +endif + cc = ${toolchain}gcc ld = ${toolchain}g++ objdump = ${toolchain}objdump From f1bbde521689369e88b92dc18578723f88a91c5d Mon Sep 17 00:00:00 2001 From: xj Date: Wed, 3 Jul 2024 06:30:28 -0700 Subject: [PATCH 074/198] fix bugs --- .../drivers/usb/components/osal/usb_osal.c | 52 +++++++++---------- .../drivers/usb/components/osal/usb_osal.h | 2 +- 2 files changed, 27 insertions(+), 27 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c index 7439f3f74..e65d50ed6 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c @@ -19,12 +19,12 @@ Modification: rename the file name, and re-develop all OS abstract layer functio #include "usb_osal.h" #include "usb_mem.h" #include "libserial.h" -#include "syscall.h" +// #include "syscall.h" #include "usyscall.h" usb_osal_thread_t usb_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, usb_thread_entry_t entry, void *args){ - int ret; + long ret; char *task_param[] = { args, NULL }; ret = thread(entry, name, task_param); @@ -34,8 +34,8 @@ usb_osal_thread_t usb_osal_thread_create(const char *name, uint32_t stack_size, void usb_osal_thread_delete(usb_osal_thread_t thread){ - int thread_id; - thread_id = (int)thread; + long thread_id; + thread_id = (long)thread; kill(thread_id); } @@ -43,7 +43,7 @@ void usb_osal_thread_delete(usb_osal_thread_t thread){ usb_osal_sem_t usb_osal_sem_create(uint32_t initial_count){ - int sem_id; + long sem_id; sem_id = semaphore_new(initial_count); @@ -53,16 +53,16 @@ usb_osal_sem_t usb_osal_sem_create(uint32_t initial_count){ void usb_osal_sem_delete(usb_osal_sem_t sem){ - int sem_id; - sem_id = (int)sem; + long sem_id; + sem_id = (long)sem; semaphore_free(sem_id); } int usb_osal_sem_take(usb_osal_sem_t sem, uint32_t timeout){ - int sem_id; - sem_id = (int)sem; + long sem_id; + sem_id = (long)sem; if(sem_id < 0) return -1; @@ -75,8 +75,8 @@ int usb_osal_sem_take(usb_osal_sem_t sem, uint32_t timeout){ int usb_osal_sem_give(usb_osal_sem_t sem){ - int sem_id; - sem_id = (int)sem; + long sem_id; + sem_id = (long)sem; if(sem_id < 0) return -1; @@ -89,7 +89,7 @@ int usb_osal_sem_give(usb_osal_sem_t sem){ usb_osal_mutex_t usb_osal_mutex_create(void){ - int mutex_id; + long mutex_id; mutex_id = semaphore_new(1); @@ -99,16 +99,16 @@ usb_osal_mutex_t usb_osal_mutex_create(void){ void usb_osal_mutex_delete(usb_osal_mutex_t mutex){ - int mutex_id; - mutex_id = (int)mutex; + long mutex_id; + mutex_id = (long)mutex; semaphore_free(mutex_id); } int usb_osal_mutex_take(usb_osal_mutex_t mutex){ - int mutex_id; - mutex_id = (int)mutex; + long mutex_id; + mutex_id = (long)mutex; if(mutex_id < 0) return -1; @@ -121,8 +121,8 @@ int usb_osal_mutex_take(usb_osal_mutex_t mutex){ int usb_osal_mutex_give(usb_osal_mutex_t mutex){ - int mutex_id; - mutex_id = (int)mutex; + long mutex_id; + mutex_id = (long)mutex; if(mutex_id < 0) return -1; @@ -142,8 +142,8 @@ osal_msg_queue_t osal_mq_create(const char *name, size_t buf_size; /* Unused now */ - (void *)name; - (void *)flag; +// (void *)name; +// (void *)flag; if(msg_size <= 0 || max_msgs <=0) @@ -187,14 +187,14 @@ osal_msg_queue_t osal_mq_create(const char *name, void osal_mq_delete(osal_msg_queue_t mq){ - int mutex_id; + long mutex_id; if(mq == NULL) return; if(mq->data) usb_free(mq->data); - mutex_id = (int)(mq->mutex); + mutex_id = (long)(mq->mutex); if(mutex_id > 0) usb_osal_mutex_delete(mq->mutex); @@ -208,7 +208,7 @@ int osal_mq_send(osal_msg_queue_t mq, size_t msg_len, uint32_t timeout){ uint16_t header, tail, tail_nxt; - int mutex_id; + long mutex_id; osal_mq_msg_header_t msg_tail; uint8_t *msg_buf; @@ -218,7 +218,7 @@ int osal_mq_send(osal_msg_queue_t mq, if(msg_len > mq->msg_size) return -1; - mutex_id = (int)(mq->mutex); + mutex_id = (long)(mq->mutex); if(mutex_id <= 0) return -1; @@ -251,7 +251,7 @@ int osal_mq_recv(osal_msg_queue_t mq, size_t msg_len, uint32_t timeout){ uint16_t header, tail; - int mutex_id; + long mutex_id; osal_mq_msg_header_t msg_header; uint8_t *msg_buf; size_t copy_len; @@ -262,7 +262,7 @@ int osal_mq_recv(osal_msg_queue_t mq, if(msg_len > mq->msg_size) return -1; - mutex_id = (int)(mq->mutex); + mutex_id = (long)(mq->mutex); if(mutex_id <= 0) return -1; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.h index 0d32449ed..f9510af95 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.h @@ -57,7 +57,7 @@ void usb_osal_msleep(uint32_t delay); * Defination of the Message queue. */ -#define MAX_MSG_QUEUE_BUF_SIZE 65535 * 65535 +#define MAX_MSG_QUEUE_BUF_SIZE 65535 struct osal_msg_queue{ uint16_t msg_size; From 0c5851f05bb7096ed2c52c50fd4b9c914f158f6c Mon Sep 17 00:00:00 2001 From: xj Date: Wed, 3 Jul 2024 06:31:55 -0700 Subject: [PATCH 075/198] modify lwip_service.c for test --- Ubiquitous/XiZi_AIoT/services/net/libnet/lwip_service.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/net/libnet/lwip_service.c b/Ubiquitous/XiZi_AIoT/services/net/libnet/lwip_service.c index a6b1cb50f..c7bf12b7a 100644 --- a/Ubiquitous/XiZi_AIoT/services/net/libnet/lwip_service.c +++ b/Ubiquitous/XiZi_AIoT/services/net/libnet/lwip_service.c @@ -75,4 +75,4 @@ int ipc_close(struct Session* session, int s){ IPC_INTERFACE(Ipc_setsockopt, 5, s, level, optname, optval, optlen, sizeof(int), sizeof(int), sizeof(int), *(socklen_t*)optlen, sizeof(socklen_t)); int ipc_setsockopt(struct Session* session, int s, int level, int optname, void *optval, socklen_t optlen){ return IPC_CALL(Ipc_setsockopt)(session, &s, &level, &optname, optval, &optlen); -} \ No newline at end of file +} From 114ff07759aaa9c3970cfdb99e3ed59c0349b9d9 Mon Sep 17 00:00:00 2001 From: xj Date: Wed, 3 Jul 2024 18:46:26 -0700 Subject: [PATCH 076/198] replace header file which is referred in usb_log.h --- .../XiZi_AIoT/services/drivers/usb/components/common/usb_log.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_log.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_log.h index 9ee105823..e779a23a1 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_log.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_log.h @@ -6,7 +6,7 @@ #ifndef USB_LOG_H_ #define USB_LOG_H_ -#include +#include "libserial.h" /* DEBUG level */ #define USB_DBG_ERROR 0 From c5db36f4b94d17cbbc29455f58466010e9d16d14 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Thu, 4 Jul 2024 11:28:28 +0800 Subject: [PATCH 077/198] enable DSB --- .../services/drivers/usb/components/port/xhci/xhci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 527cdf2c1..75354f2db 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -1456,7 +1456,7 @@ int xhci_event_wait(struct xhci_host *xhci, * @v value Value send to doorbell */ static inline void xhci_doorbell ( struct xhci_host *xhci, uint32_t slotid, uint32_t value ) { -// DSB(); + DSB(); BARRIER(); writel ( value, xhci->db + slotid * XHCI_REG_DB_SIZE ); /* bit[7:0] db target, is ep_id */ } @@ -2702,4 +2702,4 @@ void xhci_event_process(struct xhci_host *xhci) { } return; -} \ No newline at end of file +} From 4a657a3044a67deebf1d25b2d51c11a747e08577 Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 4 Jul 2024 02:53:40 -0700 Subject: [PATCH 078/198] replace DSB --- .../services/drivers/usb/components/port/xhci/xhci_reg.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci_reg.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci_reg.h index 3c4a7d4fa..5702efe46 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci_reg.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci_reg.h @@ -391,11 +391,11 @@ enum { #define BARRIER() __asm__ __volatile__("": : :"memory") #ifdef XHCI_AARCH64 -// #define DSB() __asm__ __volatile__("dsb sy": : : "memory") -#define DSB() __asm__ volatile("dsb ish\n\t") +#define DSB() __asm__ __volatile__("dsb sy": : : "memory") +// #define DSB() __asm__ volatile("dsb ish\n\t") #else -// #define DSB() __asm__ __volatile__("dsb": : : "memory") -#define DSB() __asm__ volatile("dsb ish\n\t") +#define DSB() __asm__ __volatile__("dsb": : : "memory") +// #define DSB() __asm__ volatile("dsb ish\n\t") #endif From d2164713b390a5e4a1ed9183372cc7556a27fccd Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 4 Jul 2024 05:25:53 -0700 Subject: [PATCH 079/198] Add fls function --- .../drivers/usb/components/port/xhci/xhci.c | 9 ++-- .../drivers/usb/components/port/xhci/xhci.h | 45 +++++++++++++++++++ 2 files changed, 49 insertions(+), 5 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 75354f2db..da275556a 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -128,9 +128,8 @@ static inline size_t xhci_align ( size_t len ) { size_t align; /* Align to own length (rounded up to a power of two) */ -// align = ( 1 << fls ( len - 1 ) ); -// align = ( 1 << fls ( len - 1 ) ); - align = XHCI_MIN_ALIGN; + align = ( 1 << fls ( len - 1 ) ); +// align = XHCI_MIN_ALIGN; /* Round up to XHCI_MIN_ALIGN if needed */ if ( align < XHCI_MIN_ALIGN ) @@ -2228,8 +2227,8 @@ int xhci_work_endpoint_open ( struct xhci_host *xhci, struct xhci_slot *slot, st /* Calculate interval */ if ( ctx_type & XHCI_EP_TYPE_PERIODIC ) { -// ep->interval = ( fls ( ep->interval ) - 1 ); - ep->interval = 256; + ep->interval = ( fls ( ep->interval ) - 1 ); +// ep->interval = 256; } ep->ctx_type = ctx_type; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h index d653a404d..1d8403a4e 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h @@ -992,4 +992,49 @@ void xhci_dump_trbs(const union xhci_trb *trbs, unsigned int count); /* Dump slot context */ void xhci_dump_slot_ctx(const struct xhci_slot_context *const sc); + +/* + * Find the last (most-significant) bit set + * @x: the 64 bit length variate to search. + */ +static __always_inline int fls(uint64_t x) +{ + int r = 64; + + if(!x) + return 0; + + if (!(x & 0xffffffff00000000u)) { + x <<= 32; + r -= 32; + } + + if (!(x & 0xffff000000000000u)) { + x <<= 16; + r -= 16; + } + + if (!(x & 0xff00000000000000u)) { + x <<= 8; + r -= 8; + } + + if (!(x & 0xf000000000000000u)) { + x <<= 4; + r -= 4; + } + + if (!(x & 0xc000000000000000u)) { + x <<= 2; + r -= 2; + } + + if (!(x & 0x8000000000000000u)) { + x <<= 1; + r -= 1; + } + + return r; +} + #endif From ab573e238e9472f692ba1756027339c240dad552 Mon Sep 17 00:00:00 2001 From: xj Date: Fri, 5 Jul 2024 01:11:33 -0700 Subject: [PATCH 080/198] Implant scratchpad buffer functions --- .../services/drivers/usb/components/port/xhci/xhci.c | 3 ++- .../services/drivers/usb/components/port/xhci/xhci.h | 6 ++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index da275556a..abc84d67a 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -698,6 +698,7 @@ static int xhci_dcbaa_alloc ( struct xhci_host *xhci ) { } xhci->dcbaa_addr = dcbaap_addr; + xhci->dcbaa.context = (void *)dcbaap_phy; #if 0 if ( ! xhci->dcbaa.context ) { @@ -707,7 +708,7 @@ static int xhci_dcbaa_alloc ( struct xhci_host *xhci ) { } #endif - memset ( xhci->dcbaa.context, 0, len ); + memset ( (void *)xhci->dcbaa_addr, 0, len ); /* Program DCBAA pointer */ // dcbaap = (uintptr_t)( xhci->dcbaa.context ); diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h index 1d8403a4e..9c5a4b156 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h @@ -75,6 +75,12 @@ struct xhci_scratchpad { uintptr_t buffer; /** Scratchpad array */ uint64_t *array; + /* + * vir_addr: Vitual address array. It holds all the virtual address of the pages allocated to xHCI scratchpad buffer. + * array_phy: Physical address of array. + */ + uint64_t *vir_addr; + uintptr_t array_phy; }; /** An input control context */ From 7cb39f992c17233f13a71f5c0c17631de8d90c99 Mon Sep 17 00:00:00 2001 From: xj Date: Fri, 5 Jul 2024 06:05:54 -0700 Subject: [PATCH 081/198] Implant scratchpad buffer functions --- .../drivers/usb/components/port/xhci/xhci.c | 72 +++++++++++++++++-- .../drivers/usb/components/port/xhci/xhci.h | 12 +++- 2 files changed, 77 insertions(+), 7 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index abc84d67a..8484d7430 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -698,7 +698,8 @@ static int xhci_dcbaa_alloc ( struct xhci_host *xhci ) { } xhci->dcbaa_addr = dcbaap_addr; - xhci->dcbaa.context = (void *)dcbaap_phy; + xhci->dcbaa_phy = dcbaap_phy; + xhci->dcbaa.context = (void *)dcbaap_addr; #if 0 if ( ! xhci->dcbaa.context ) { @@ -708,7 +709,9 @@ static int xhci_dcbaa_alloc ( struct xhci_host *xhci ) { } #endif - memset ( (void *)xhci->dcbaa_addr, 0, len ); +// memset ( (void *)xhci->dcbaa_addr, 0, len ); + memset ( xhci->dcbaa.context, 0, len ); + /* Program DCBAA pointer */ // dcbaap = (uintptr_t)( xhci->dcbaa.context ); @@ -739,6 +742,7 @@ static int xhci_scratchpad_alloc ( struct xhci_host *xhci ) { size_t buffer_len; size_t array_len; uintptr_t addr; + uintptr_t vir_addr, phy_addr, vir_page_addr, phy_page_addr; unsigned int i; int rc; @@ -749,6 +753,60 @@ static int xhci_scratchpad_alloc ( struct xhci_host *xhci ) { return 0; } + /* Allocate buffer to store */ + array_len = scratch->count * sizeof ( scratch->array[0] ); + + rc = naive_mmap(&vir_addr, &phy_addr, array_len, false); + + if(rc != 0){ + USB_LOG_ERR("XHCI %s could not allocate scratch buffer\n", xhci->name ); + rc = -ENOMEM; + goto err_alloc; + } + + scratch->array_addr = (void *)vir_addr; + memset(scratch->array_addr, 0, array_len); + scratch->array_phy = phy_addr; + + +/* + * Allocate memory for storing all virtual address of physical pages allocated to xHCI as scratchpad buffer. + */ + buffer_len = scratch->count * sizeof ( scratch->sp_buffers[0] ); + scratch->sp_buffers = usb_align(xhci_align (buffer_len), buffer_len); + + if(!scratch->sp_buffers){ + USB_LOG_ERR("XHCI %s could not allocate scratchpad buffers\n", + xhci->name ); + goto err_alloc_array; + } + +/* + * Allocate physical page one by one, and store its physical address in vir_addr. + */ + for(i = 0; i < scratch->count; i++){ + rc = naive_mmap(&vir_page_addr, &phy_page_addr, xhci->pagesize, false); + + if(rc != 0){ + USB_LOG_ERR("XHCI %s could not allocate scratchpad buffers\n", + xhci->name ); + goto err_alloc_array_vir; + } + scratch->sp_buffers[i] = (void *)vir_page_addr; + scratch->array_addr[i] = phy_page_addr; + } + +/* + * PLEASE NOTICE: + * The value that write to context[0] is the physical address of the memory region, which holds all physical address of memory pages + * that are allocated to xHCI as scratchpad buffers. The byte order of the physical address should be little end. + */ + USB_ASSERT ( xhci->dcbaa.context != NULL ); + xhci->dcbaa.context[0] = scratch->array_phy; + + return 0; + +#if 0 /* Allocate scratchpad buffers */ buffer_len = ( scratch->count * xhci->pagesize ); scratch->buffer = (uintptr_t)usb_align ( xhci->pagesize, buffer_len ); @@ -787,10 +845,16 @@ static int xhci_scratchpad_alloc ( struct xhci_host *xhci ) { ( scratch->array ), ( ( scratch->array ) + array_len ) ); return 0; +#endif + + + + +// usb_free ( scratch->array ); +err_alloc_array_vir: - usb_free ( scratch->array ); err_alloc_array: - usb_free ( scratch->buffer ); +// usb_free ( scratch->buffer ); err_alloc: return rc; } diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h index 9c5a4b156..975bb2fec 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h @@ -76,11 +76,16 @@ struct xhci_scratchpad { /** Scratchpad array */ uint64_t *array; /* - * vir_addr: Vitual address array. It holds all the virtual address of the pages allocated to xHCI scratchpad buffer. + * array_addr: address array. It holds all the virtual address of the memory allocated to xHCI for storing all + * physical address of scratchpad buffer. * array_phy: Physical address of array. */ - uint64_t *vir_addr; + uint64_t *array_addr; uintptr_t array_phy; + /* + * sp_buffers: scratchpad buffers. It holds all the virtual address of memory pages that are allocated to xHCI. + */ + void **sp_buffers; }; /** An input control context */ @@ -869,9 +874,10 @@ struct xhci_host { /* * Device context base address array. * - * dcbaa_addr holds the virtual address of the dcbaa, meanwhile acbaa keeps the value that should be writen to XHCI_OP_DCBAAP. + * dcbaa_addr holds the virtual address of the dcbaa, meanwhile dcbaa_phy keeps the value that should be writen to XHCI_OP_DCBAAP. */ uintptr_t dcbaa_addr; + uintptr_t dcbaa_phy; struct xhci_dcbaa dcbaa; /** Scratchpad buffer */ From b623803db484965e5d78c28a9ec6ecef5cda0205 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 9 Jul 2024 16:34:10 +0800 Subject: [PATCH 082/198] Add compiling rndis. --- .../services/drivers/usb/components/class/Makefile | 4 ++-- .../drivers/usb/components/class/wireless/Makefile | 11 +++++++++++ 2 files changed, 13 insertions(+), 2 deletions(-) create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/Makefile diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/Makefile index d0ecbc1b9..0b42922a2 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/Makefile @@ -1,4 +1,4 @@ -SRC_DIR := hub +SRC_DIR := hub wireless -include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/Makefile new file mode 100644 index 000000000..b156211d4 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/Makefile @@ -0,0 +1,11 @@ +include $(KERNEL_ROOT)/services/drivers/usb/components/usb.mk + +objs = usbh_rndis.o rndis_host.o + +all: ${objs} + @echo "generate $^" + @mv $^ $(KERNEL_ROOT)/services/drivers/usb/components + +%.o: %.c + @echo "cc $^" + @${cc} ${cflags} ${c_useropts} ${INC_DIR} -o $@ -c $^ From 459a7ad7cffb480dc89f356f26a4d94846c1d172 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 9 Jul 2024 16:40:13 +0800 Subject: [PATCH 083/198] Modify usbh_rndis related files according to CherryUSB v0.1.2 --- .../usb/components/class/cdc/usb_cdc.h | 573 +++++++++++++++++- .../usb/components/class/wireless/ndis.h | 277 +++++++++ .../class/wireless/rndis_protocol.h | 298 +++++++++ .../components/class/wireless/usbh_rndis.c | 428 +++++++++++++ .../components/class/wireless/usbh_rndis.h | 49 +- 5 files changed, 1623 insertions(+), 2 deletions(-) create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/ndis.h diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/cdc/usb_cdc.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/cdc/usb_cdc.h index 04e864af1..2fcbcefd8 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/cdc/usb_cdc.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/cdc/usb_cdc.h @@ -1,9 +1,580 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/************************************************* +File name: usb_cdc.h +Description: adopt cherry USB to XiZi AIOT. +Others: take CherryUSB v0.10.2/class/cdc/usb_cdc.h for references + https://github.com/cherry-embedded/CherryUSB/blob/v0.10.2/class/cdc/usb_cdc.h +*************************************************/ + #ifndef USB_CDC_H_ #define USB_CDC_H_ +/*------------------------------------------------------------------------------ + * Definitions based on usbcdc11.pdf (www.usb.org) + *----------------------------------------------------------------------------*/ +/* Communication device class specification version 1.10 */ +#define CDC_V1_10 0x0110U +// Communication device class specification version 1.2 +#define CDC_V1_2_0 0x0120U +/* Communication interface class code */ +/* (usbcdc11.pdf, 4.2, Table 15) */ +#define CDC_COMMUNICATION_INTERFACE_CLASS 0x02U +/* Communication interface class subclass codes */ +/* (usbcdc11.pdf, 4.3, Table 16) */ +#define CDC_SUBCLASS_NONE 0x00 /* Reserved */ +#define CDC_SUBCLASS_DLC 0x01 /* Direct Line Control Model */ +#define CDC_SUBCLASS_ACM 0x02 /* Abstract Control Model */ +#define CDC_SUBCLASS_TCM 0x03 /* Telephone Control Model */ +#define CDC_SUBCLASS_MCM 0x04 /* Multi-Channel Control Model */ +#define CDC_SUBCLASS_CAPI 0x05 /* CAPI Control Model */ +#define CDC_SUBCLASS_ECM 0x06 /* Ethernet Networking Control Model */ +#define CDC_SUBCLASS_ATM 0x07 /* ATM Networking Control Model */ + /* 0x08-0x0d Reserved (future use) */ +#define CDC_SUBCLASS_MBIM 0x0e /* MBIM Control Model */ + /* 0x0f-0x7f Reserved (future use) */ + /* 0x80-0xfe Reserved (vendor specific) */ +#define CDC_DIRECT_LINE_CONTROL_MODEL 0x01U +#define CDC_ABSTRACT_CONTROL_MODEL 0x02U +#define CDC_TELEPHONE_CONTROL_MODEL 0x03U +#define CDC_MULTI_CHANNEL_CONTROL_MODEL 0x04U +#define CDC_CAPI_CONTROL_MODEL 0x05U +#define CDC_ETHERNET_NETWORKING_CONTROL_MODEL 0x06U +#define CDC_ATM_NETWORKING_CONTROL_MODEL 0x07U +#define CDC_WIRELESS_HANDSET_CONTROL_MODEL 0x08U +#define CDC_DEVICE_MANAGEMENT 0x09U +#define CDC_MOBILE_DIRECT_LINE_MODEL 0x0AU +#define CDC_OBEX 0x0BU +#define CDC_ETHERNET_EMULATION_MODEL 0x0CU +#define CDC_NETWORK_CONTROL_MODEL 0x0DU +/* Communication interface class control protocol codes */ +/* (usbcdc11.pdf, 4.4, Table 17) */ +#define CDC_COMMON_PROTOCOL_NONE 0x00U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS 0x01U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS_PCCA_101 0x02U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS_PCCA_101_AND_ANNEXO 0x03U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS_GSM_707 0x04U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS_3GPP_27007 0x05U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS_CDMA 0x06U +#define CDC_COMMON_PROTOCOL_ETHERNET_EMULATION_MODEL 0x07U +// NCM Communication Interface Protocol Codes +// (usbncm10.pdf, 4.2, Table 4-2) +#define CDC_NCM_PROTOCOL_NONE 0x00U +#define CDC_NCM_PROTOCOL_OEM 0xFEU -#endif +/* Data interface class code */ +/* (usbcdc11.pdf, 4.5, Table 18) */ +#define CDC_DATA_INTERFACE_CLASS 0x0A + +/* Data Interface Sub-Class Codes ********************************************/ +#define CDC_DATA_SUBCLASS_NONE 0x00 + +/* Data interface class protocol codes */ +/* (usbcdc11.pdf, 4.7, Table 19) */ +#define CDC_DATA_PROTOCOL_ISDN_BRI 0x30 +#define CDC_DATA_PROTOCOL_HDLC 0x31 +#define CDC_DATA_PROTOCOL_TRANSPARENT 0x32 +#define CDC_DATA_PROTOCOL_Q921_MANAGEMENT 0x50 +#define CDC_DATA_PROTOCOL_Q921_DATA_LINK 0x51 +#define CDC_DATA_PROTOCOL_Q921_MULTIPLEXOR 0x52 +#define CDC_DATA_PROTOCOL_V42 0x90 +#define CDC_DATA_PROTOCOL_EURO_ISDN 0x91 +#define CDC_DATA_PROTOCOL_V24_RATE_ADAPTATION 0x92 +#define CDC_DATA_PROTOCOL_CAPI 0x93 +#define CDC_DATA_PROTOCOL_HOST_BASED_DRIVER 0xFD +#define CDC_DATA_PROTOCOL_DESCRIBED_IN_PUFD 0xFE + +/* Type values for bDescriptorType field of functional descriptors */ +/* (usbcdc11.pdf, 5.2.3, Table 24) */ +#define CDC_CS_INTERFACE 0x24 +#define CDC_CS_ENDPOINT 0x25 + +/* Type values for bDescriptorSubtype field of functional descriptors */ +/* (usbcdc11.pdf, 5.2.3, Table 25) */ +#define CDC_FUNC_DESC_HEADER 0x00 +#define CDC_FUNC_DESC_CALL_MANAGEMENT 0x01 +#define CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT 0x02 +#define CDC_FUNC_DESC_DIRECT_LINE_MANAGEMENT 0x03 +#define CDC_FUNC_DESC_TELEPHONE_RINGER 0x04 +#define CDC_FUNC_DESC_REPORTING_CAPABILITIES 0x05 +#define CDC_FUNC_DESC_UNION 0x06 +#define CDC_FUNC_DESC_COUNTRY_SELECTION 0x07 +#define CDC_FUNC_DESC_TELEPHONE_OPERATIONAL_MODES 0x08 +#define CDC_FUNC_DESC_USB_TERMINAL 0x09 +#define CDC_FUNC_DESC_NETWORK_CHANNEL 0x0A +#define CDC_FUNC_DESC_PROTOCOL_UNIT 0x0B +#define CDC_FUNC_DESC_EXTENSION_UNIT 0x0C +#define CDC_FUNC_DESC_MULTI_CHANNEL_MANAGEMENT 0x0D +#define CDC_FUNC_DESC_CAPI_CONTROL_MANAGEMENT 0x0E +#define CDC_FUNC_DESC_ETHERNET_NETWORKING 0x0F +#define CDC_FUNC_DESC_ATM_NETWORKING 0x10 +#define CDC_FUNC_DESC_WIRELESS_HANDSET_CONTROL_MODEL 0x11 +#define CDC_FUNC_DESC_MOBILE_DIRECT_LINE_MODEL 0x12 +#define CDC_FUNC_DESC_MOBILE_DIRECT_LINE_MODEL_DETAIL 0x13 +#define CDC_FUNC_DESC_DEVICE_MANAGEMENT_MODEL 0x14 +#define CDC_FUNC_DESC_OBEX 0x15 +#define CDC_FUNC_DESC_COMMAND_SET 0x16 +#define CDC_FUNC_DESC_COMMAND_SET_DETAIL 0x17 +#define CDC_FUNC_DESC_TELEPHONE_CONTROL_MODEL 0x18 +#define CDC_FUNC_DESC_OBEX_SERVICE_IDENTIFIER 0x19 + +/* CDC class-specific request codes */ +/* (usbcdc11.pdf, 6.2, Table 46) */ +/* see Table 45 for info about the specific requests. */ +#define CDC_REQUEST_SEND_ENCAPSULATED_COMMAND 0x00 +#define CDC_REQUEST_GET_ENCAPSULATED_RESPONSE 0x01 +#define CDC_REQUEST_SET_COMM_FEATURE 0x02 +#define CDC_REQUEST_GET_COMM_FEATURE 0x03 +#define CDC_REQUEST_CLEAR_COMM_FEATURE 0x04 +#define CDC_REQUEST_SET_AUX_LINE_STATE 0x10 +#define CDC_REQUEST_SET_HOOK_STATE 0x11 +#define CDC_REQUEST_PULSE_SETUP 0x12 +#define CDC_REQUEST_SEND_PULSE 0x13 +#define CDC_REQUEST_SET_PULSE_TIME 0x14 +#define CDC_REQUEST_RING_AUX_JACK 0x15 +#define CDC_REQUEST_SET_LINE_CODING 0x20 +#define CDC_REQUEST_GET_LINE_CODING 0x21 +#define CDC_REQUEST_SET_CONTROL_LINE_STATE 0x22 +#define CDC_REQUEST_SEND_BREAK 0x23 +#define CDC_REQUEST_SET_RINGER_PARMS 0x30 +#define CDC_REQUEST_GET_RINGER_PARMS 0x31 +#define CDC_REQUEST_SET_OPERATION_PARMS 0x32 +#define CDC_REQUEST_GET_OPERATION_PARMS 0x33 +#define CDC_REQUEST_SET_LINE_PARMS 0x34 +#define CDC_REQUEST_GET_LINE_PARMS 0x35 +#define CDC_REQUEST_DIAL_DIGITS 0x36 +#define CDC_REQUEST_SET_UNIT_PARAMETER 0x37 +#define CDC_REQUEST_GET_UNIT_PARAMETER 0x38 +#define CDC_REQUEST_CLEAR_UNIT_PARAMETER 0x39 +#define CDC_REQUEST_GET_PROFILE 0x3A +#define CDC_REQUEST_SET_ETHERNET_MULTICAST_FILTERS 0x40 +#define CDC_REQUEST_SET_ETHERNET_PMP_FILTER 0x41 +#define CDC_REQUEST_GET_ETHERNET_PMP_FILTER 0x42 +#define CDC_REQUEST_SET_ETHERNET_PACKET_FILTER 0x43 +#define CDC_REQUEST_GET_ETHERNET_STATISTIC 0x44 +#define CDC_REQUEST_SET_ATM_DATA_FORMAT 0x50 +#define CDC_REQUEST_GET_ATM_DEVICE_STATISTICS 0x51 +#define CDC_REQUEST_SET_ATM_DEFAULT_VC 0x52 +#define CDC_REQUEST_GET_ATM_VC_STATISTICS 0x53 + +/* Communication feature selector codes */ +/* (usbcdc11.pdf, 6.2.2..6.2.4, Table 47) */ +#define CDC_ABSTRACT_STATE 0x01 +#define CDC_COUNTRY_SETTING 0x02 + +/** Control Signal Bitmap Values for SetControlLineState */ +#define SET_CONTROL_LINE_STATE_RTS 0x02 +#define SET_CONTROL_LINE_STATE_DTR 0x01 + +/* Feature Status returned for ABSTRACT_STATE Selector */ +/* (usbcdc11.pdf, 6.2.3, Table 48) */ +#define CDC_IDLE_SETTING (1 << 0) +#define CDC_DATA_MULTPLEXED_STATE (1 << 1) + +/* Control signal bitmap values for the SetControlLineState request */ +/* (usbcdc11.pdf, 6.2.14, Table 51) */ +#define CDC_DTE_PRESENT (1 << 0) +#define CDC_ACTIVATE_CARRIER (1 << 1) + +/* CDC class-specific notification codes */ +/* (usbcdc11.pdf, 6.3, Table 68) */ +/* see Table 67 for Info about class-specific notifications */ +#define CDC_NOTIFICATION_NETWORK_CONNECTION 0x00 +#define CDC_RESPONSE_AVAILABLE 0x01 +#define CDC_AUX_JACK_HOOK_STATE 0x08 +#define CDC_RING_DETECT 0x09 +#define CDC_NOTIFICATION_SERIAL_STATE 0x20 +#define CDC_CALL_STATE_CHANGE 0x28 +#define CDC_LINE_STATE_CHANGE 0x29 +#define CDC_CONNECTION_SPEED_CHANGE 0x2A + +/* UART state bitmap values (Serial state notification). */ +/* (usbcdc11.pdf, 6.3.5, Table 69) */ +#define CDC_SERIAL_STATE_OVERRUN (1 << 6) /* receive data overrun error has occurred */ +#define CDC_SERIAL_STATE_OVERRUN_Pos (6) +#define CDC_SERIAL_STATE_OVERRUN_Msk (1 << CDC_SERIAL_STATE_OVERRUN_Pos) +#define CDC_SERIAL_STATE_PARITY (1 << 5) /* parity error has occurred */ +#define CDC_SERIAL_STATE_PARITY_Pos (5) +#define CDC_SERIAL_STATE_PARITY_Msk (1 << CDC_SERIAL_STATE_PARITY_Pos) +#define CDC_SERIAL_STATE_FRAMING (1 << 4) /* framing error has occurred */ +#define CDC_SERIAL_STATE_FRAMING_Pos (4) +#define CDC_SERIAL_STATE_FRAMING_Msk (1 << CDC_SERIAL_STATE_FRAMING_Pos) +#define CDC_SERIAL_STATE_RING (1 << 3) /* state of ring signal detection */ +#define CDC_SERIAL_STATE_RING_Pos (3) +#define CDC_SERIAL_STATE_RING_Msk (1 << CDC_SERIAL_STATE_RING_Pos) +#define CDC_SERIAL_STATE_BREAK (1 << 2) /* state of break detection */ +#define CDC_SERIAL_STATE_BREAK_Pos (2) +#define CDC_SERIAL_STATE_BREAK_Msk (1 << CDC_SERIAL_STATE_BREAK_Pos) +#define CDC_SERIAL_STATE_TX_CARRIER (1 << 1) /* state of transmission carrier */ +#define CDC_SERIAL_STATE_TX_CARRIER_Pos (1) +#define CDC_SERIAL_STATE_TX_CARRIER_Msk (1 << CDC_SERIAL_STATE_TX_CARRIER_Pos) +#define CDC_SERIAL_STATE_RX_CARRIER (1 << 0) /* state of receiver carrier */ +#define CDC_SERIAL_STATE_RX_CARRIER_Pos (0) +#define CDC_SERIAL_STATE_RX_CARRIER_Msk (1 << CDC_SERIAL_STATE_RX_CARRIER_Pos) + +#define CDC_ECM_XMIT_OK (1 << 0) +#define CDC_ECM_RVC_OK (1 << 1) +#define CDC_ECM_XMIT_ERROR (1 << 2) +#define CDC_ECM_RCV_ERROR (1 << 3) +#define CDC_ECM_RCV_NO_BUFFER (1 << 4) +#define CDC_ECM_DIRECTED_BYTES_XMIT (1 << 5) +#define CDC_ECM_DIRECTED_FRAMES_XMIT (1 << 6) +#define CDC_ECM_MULTICAST_BYTES_XMIT (1 << 7) +#define CDC_ECM_MULTICAST_FRAMES_XMIT (1 << 8) +#define CDC_ECM_BROADCAST_BYTES_XMIT (1 << 9) +#define CDC_ECM_BROADCAST_FRAMES_XMIT (1 << 10) +#define CDC_ECM_DIRECTED_BYTES_RCV (1 << 11) +#define CDC_ECM_DIRECTED_FRAMES_RCV (1 << 12) +#define CDC_ECM_MULTICAST_BYTES_RCV (1 << 13) +#define CDC_ECM_MULTICAST_FRAMES_RCV (1 << 14) +#define CDC_ECM_BROADCAST_BYTES_RCV (1 << 15) +#define CDC_ECM_BROADCAST_FRAMES_RCV (1 << 16) +#define CDC_ECM_RCV_CRC_ERROR (1 << 17) +#define CDC_ECM_TRANSMIT_QUEUE_LENGTH (1 << 18) +#define CDC_ECM_RCV_ERROR_ALIGNMENT (1 << 19) +#define CDC_ECM_XMIT_ONE_COLLISION (1 << 20) +#define CDC_ECM_XMIT_MORE_COLLISIONS (1 << 21) +#define CDC_ECM_XMIT_DEFERRED (1 << 22) +#define CDC_ECM_XMIT_MAX_COLLISIONS (1 << 23) +#define CDC_ECM_RCV_OVERRUN (1 << 24) +#define CDC_ECM_XMIT_UNDERRUN (1 << 25) +#define CDC_ECM_XMIT_HEARTBEAT_FAILURE (1 << 26) +#define CDC_ECM_XMIT_TIMES_CRS_LOST (1 << 27) +#define CDC_ECM_XMIT_LATE_COLLISIONS (1 << 28) + +#define CDC_ECM_MAC_STR_DESC (uint8_t *)"010202030000" +#define CDC_ECM_MAC_ADDR0 0x00U /* 01 */ +#define CDC_ECM_MAC_ADDR1 0x02U /* 02 */ +#define CDC_ECM_MAC_ADDR2 0x02U /* 03 */ +#define CDC_ECM_MAC_ADDR3 0x03U /* 00 */ +#define CDC_ECM_MAC_ADDR4 0x00U /* 00 */ +#define CDC_ECM_MAC_ADDR5 0x00U /* 00 */ + +#define CDC_ECM_NET_DISCONNECTED 0x00U +#define CDC_ECM_NET_CONNECTED 0x01U + +#define CDC_ECM_ETH_STATS_RESERVED 0xE0U +#define CDC_ECM_BMREQUEST_TYPE_ECM 0xA1U + +#define CDC_ECM_CONNECT_SPEED_UPSTREAM 0x004C4B40U /* 5Mbps */ +#define CDC_ECM_CONNECT_SPEED_DOWNSTREAM 0x004C4B40U /* 5Mbps */ + +#define CDC_ECM_NOTIFY_CODE_NETWORK_CONNECTION 0x00 +#define CDC_ECM_NOTIFY_CODE_RESPONSE_AVAILABLE 0x01 +#define CDC_ECM_NOTIFY_CODE_CONNECTION_SPEED_CHANGE 0x2A + +/*------------------------------------------------------------------------------ + * Structures based on usbcdc11.pdf (www.usb.org) + *----------------------------------------------------------------------------*/ + +/* Header functional descriptor */ +/* (usbcdc11.pdf, 5.2.3.1) */ +/* This header must precede any list of class-specific descriptors. */ +struct cdc_header_descriptor { + uint8_t bFunctionLength; /* size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */ + uint8_t bDescriptorSubtype; /* Header functional descriptor subtype */ + uint16_t bcdCDC; /* USB CDC specification release version */ +} __attribute__((packed)); + +/* Call management functional descriptor */ +/* (usbcdc11.pdf, 5.2.3.2) */ +/* Describes the processing of calls for the communication class interface. */ +struct cdc_call_management_descriptor { + uint8_t bFunctionLength; /* size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */ + uint8_t bDescriptorSubtype; /* call management functional descriptor subtype */ + uint8_t bmCapabilities; /* capabilities that this configuration supports */ + uint8_t bDataInterface; /* interface number of the data class interface used for call management (optional) */ +} __attribute__((packed)); + +/* Abstract control management functional descriptor */ +/* (usbcdc11.pdf, 5.2.3.3) */ +/* Describes the command supported by the communication interface class with the Abstract Control Model subclass code. */ +struct cdc_abstract_control_management_descriptor { + uint8_t bFunctionLength; /* size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */ + uint8_t bDescriptorSubtype; /* abstract control management functional descriptor subtype */ + uint8_t bmCapabilities; /* capabilities supported by this configuration */ +} __attribute__((packed)); + +/* Union functional descriptors */ +/* (usbcdc11.pdf, 5.2.3.8) */ +/* Describes the relationship between a group of interfaces that can be considered to form a functional unit. */ +struct cdc_union_descriptor { + uint8_t bFunctionLength; /* size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */ + uint8_t bDescriptorSubtype; /* union functional descriptor subtype */ + uint8_t bMasterInterface; /* interface number designated as master */ +} __attribute__((packed)); + +/* Union functional descriptors with one slave interface */ +/* (usbcdc11.pdf, 5.2.3.8) */ +struct cdc_union_1slave_descriptor { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bControlInterface; + uint8_t bSubordinateInterface0; +} __attribute__((packed)); + +/* Line coding structure for GET_LINE_CODING / SET_LINE_CODING class requests*/ +/* Format of the data returned when a GetLineCoding request is received */ +/* (usbcdc11.pdf, 6.2.13) */ +struct cdc_line_coding { + uint32_t dwDTERate; /* Data terminal rate in bits per second */ + uint8_t bCharFormat; /* Number of stop bits */ + uint8_t bParityType; /* Parity bit type */ + uint8_t bDataBits; /* Number of data bits */ +} __attribute__((packed)); + +/** Data structure for the notification about SerialState */ +struct cdc_acm_notification { + uint8_t bmRequestType; + uint8_t bNotificationType; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; + uint16_t data; +} __attribute__((packed)); + +/** Ethernet Networking Functional Descriptor */ +struct cdc_ecm_descriptor { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t iMACAddress; + uint32_t bmEthernetStatistics; + uint16_t wMaxSegmentSize; + uint16_t wNumberMCFilters; + uint8_t bNumberPowerFilters; +} __attribute__((packed)); + +struct cdc_ecm_notification { + uint8_t bmRequestType; + uint8_t bNotificationType; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; + uint8_t data[8]; +} __attribute__((packed)); + +/*Length of template descriptor: 66 bytes*/ +#define CDC_ACM_DESCRIPTOR_LEN (8 + 9 + 5 + 5 + 4 + 5 + 7 + 9 + 7 + 7) +// clang-format off +#define CDC_ACM_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, wMaxPacketSize, str_idx) \ + /* Interface Associate */ \ + 0x08, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ + bFirstInterface, /* bFirstInterface */ \ + 0x02, /* bInterfaceCount */ \ + USB_DEVICE_CLASS_CDC, /* bFunctionClass */ \ + CDC_ABSTRACT_CONTROL_MODEL, /* bFunctionSubClass */ \ + CDC_COMMON_PROTOCOL_AT_COMMANDS, /* bFunctionProtocol */ \ + 0x00, /* iFunction */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_CDC, /* bInterfaceClass */ \ + CDC_ABSTRACT_CONTROL_MODEL, /* bInterfaceSubClass */ \ + CDC_COMMON_PROTOCOL_AT_COMMANDS, /* bInterfaceProtocol */ \ + str_idx, /* iInterface */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_HEADER, /* bDescriptorSubtype */ \ + WBVAL(CDC_V1_10), /* bcdCDC */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_CALL_MANAGEMENT, /* bDescriptorSubtype */ \ + 0x00, /* bmCapabilities */ \ + (uint8_t)(bFirstInterface + 1), /* bDataInterface */ \ + 0x04, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype */ \ + 0x02, /* bmCapabilities */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_UNION, /* bDescriptorSubtype */ \ + bFirstInterface, /* bMasterInterface */ \ + (uint8_t)(bFirstInterface + 1), /* bSlaveInterface0 */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + int_ep, /* bEndpointAddress */ \ + 0x03, /* bmAttributes */ \ + 0x08, 0x00, /* wMaxPacketSize */ \ + 0x0a, /* bInterval */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + (uint8_t)(bFirstInterface + 1), /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x02, /* bNumEndpoints */ \ + CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass */ \ + 0x00, /* bInterfaceSubClass */ \ + 0x00, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + out_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00, /* bInterval */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + in_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00 /* bInterval */ +// clang-format on + +/*Length of template descriptor: 66 bytes*/ +#define CDC_RNDIS_DESCRIPTOR_LEN (8 + 9 + 5 + 5 + 4 + 5 + 7 + 9 + 7 + 7) +// clang-format off +#define CDC_RNDIS_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, wMaxPacketSize, str_idx) \ + /* Interface Associate */ \ + 0x08, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ + bFirstInterface, /* bFirstInterface */ \ + 0x02, /* bInterfaceCount */ \ + USB_DEVICE_CLASS_WIRELESS, /* bFunctionClass */ \ + CDC_DIRECT_LINE_CONTROL_MODEL, /* bFunctionSubClass */ \ + CDC_COMMON_PROTOCOL_AT_COMMANDS_PCCA_101_AND_ANNEXO, /* bFunctionProtocol */ \ + 0x00, /* iFunction */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_WIRELESS, /* bInterfaceClass */ \ + CDC_DIRECT_LINE_CONTROL_MODEL, /* bInterfaceSubClass */ \ + CDC_COMMON_PROTOCOL_AT_COMMANDS_PCCA_101_AND_ANNEXO, /* bInterfaceProtocol */ \ + str_idx, /* iInterface */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_HEADER, /* bDescriptorSubtype */ \ + WBVAL(CDC_V1_10), /* bcdCDC */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_CALL_MANAGEMENT, /* bDescriptorSubtype */ \ + 0x00, /* bmCapabilities */ \ + (uint8_t)(bFirstInterface + 1), /* bDataInterface */ \ + 0x04, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype */ \ + 0x00, /* bmCapabilities */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_UNION, /* bDescriptorSubtype */ \ + bFirstInterface, /* bMasterInterface */ \ + (uint8_t)(bFirstInterface + 1), /* bSlaveInterface0 */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + int_ep, /* bEndpointAddress */ \ + 0x03, /* bmAttributes */ \ + 0x08, 0x00, /* wMaxPacketSize */ \ + 0x10, /* bInterval */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + (uint8_t)(bFirstInterface + 1), /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x02, /* bNumEndpoints */ \ + CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass */ \ + 0x00, /* bInterfaceSubClass */ \ + 0x00, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + out_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00, /* bInterval */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + in_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00 /* bInterval */ +// clang-format on + +#define DBVAL_BE(x) ((x >> 24) & 0xFF), ((x >> 16) & 0xFF), ((x >> 8) & 0xFF), (x & 0xFF) + +/*Length of template descriptor: 66 bytes*/ +#define CDC_ECM_DESCRIPTOR_LEN (8 + 9 + 5 + 5 + 13 + 7 + 9 + 7 + 7) +// clang-format off +#define CDC_ECM_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, wMaxPacketSize, \ +eth_statistics, wMaxSegmentSize, wNumberMCFilters, bNumberPowerFilters, str_idx) \ + /* Interface Associate */ \ + 0x08, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ + bFirstInterface, /* bFirstInterface */ \ + 0x02, /* bInterfaceCount */ \ + USB_DEVICE_CLASS_CDC, /* bFunctionClass */ \ + CDC_ETHERNET_NETWORKING_CONTROL_MODEL, /* bFunctionSubClass */ \ + CDC_COMMON_PROTOCOL_NONE, /* bFunctionProtocol */ \ + 0x00, /* iFunction */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_CDC, /* bInterfaceClass */ \ + CDC_ETHERNET_NETWORKING_CONTROL_MODEL, /* bInterfaceSubClass */ \ + CDC_COMMON_PROTOCOL_NONE, /* bInterfaceProtocol */ \ + str_idx, /* iInterface */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_HEADER, /* bDescriptorSubtype */ \ + WBVAL(CDC_V1_10), /* bcdCDC */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_UNION, /* bDescriptorSubtype */ \ + bFirstInterface, /* bMasterInterface */ \ + (uint8_t)(bFirstInterface + 1), /* bSlaveInterface0 */ \ + /* CDC_ECM Functional Descriptor */ \ + 0x0D, /* bFunctionLength */\ + CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */\ + CDC_FUNC_DESC_ETHERNET_NETWORKING, /* Ethernet Networking functional descriptor subtype */\ + str_idx, /* Device's MAC string index */\ + DBVAL_BE(eth_statistics), /* Ethernet statistics (bitmap) */\ + WBVAL(wMaxPacketSize),/* wMaxSegmentSize: Ethernet Maximum Segment size, typically 1514 bytes */\ + WBVAL(wNumberMCFilters), /* wNumberMCFilters: the number of multicast filters */\ + bNumberPowerFilters, /* bNumberPowerFilters: the number of wakeup power filters */\ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + int_ep, /* bEndpointAddress */ \ + 0x03, /* bmAttributes */ \ + 0x10, 0x00, /* wMaxPacketSize */ \ + 0x10, /* bInterval */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + (uint8_t)(bFirstInterface + 1), /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x02, /* bNumEndpoints */ \ + CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass */ \ + 0x00, /* bInterfaceSubClass */ \ + 0x00, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + out_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00, /* bInterval */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + in_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00 /* bInterval */ +// clang-format on + +#endif /* USB_CDC_H_ */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/ndis.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/ndis.h new file mode 100644 index 000000000..a3fb045e6 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/ndis.h @@ -0,0 +1,277 @@ +/* This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ndis.h *************************************************************** + * + * \brief + * This file contains the possible external configuration of the USB. + * + * \addtogroup usbstick + * + * + ******************************************************************************/ + +/** + \ingroup usbstick + \defgroup RNDIS RNDIS Support + @{ + */ + +/* + * ndis.h + * + * Modified by Colin O'Flynn + * ntddndis.h modified by Benedikt Spranger + * + * Thanks to the cygwin development team, + * espacially to Casper S. Hornstrup + * + * THIS SOFTWARE IS NOT COPYRIGHTED + * + * This source code is offered for use in the public domain. You may + * use, modify or distribute it freely. + * + * This code is distributed in the hope that it will be useful but + * WITHOUT ANY WARRANTY. ALL WARRANTIES, EXPRESS OR IMPLIED ARE HEREBY + * DISCLAIMED. This includes but is not limited to warranties of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +/************************************************* +File name: ndis.h +Description: adopt cherry USB to XiZi AIOT. +Others: take CherryUSB v0.10.2/class/wireless/ndis.h for references + https://github.com/cherry-embedded/CherryUSB/blob/v0.10.2/class/wireless/ndis.h +*************************************************/ + +#ifndef _NDIS_H_ +#define _NDIS_H_ + +#define NDIS_STATUS_MULTICAST_FULL 0xC0010009 +#define NDIS_STATUS_MULTICAST_EXISTS 0xC001000A +#define NDIS_STATUS_MULTICAST_NOT_FOUND 0xC001000B + +/* from drivers/net/sk98lin/h/skgepnmi.h */ +#define OID_PNP_CAPABILITIES 0xFD010100 +#define OID_PNP_SET_POWER 0xFD010101 +#define OID_PNP_QUERY_POWER 0xFD010102 +#define OID_PNP_ADD_WAKE_UP_PATTERN 0xFD010103 +#define OID_PNP_REMOVE_WAKE_UP_PATTERN 0xFD010104 +#define OID_PNP_ENABLE_WAKE_UP 0xFD010106 + +enum NDIS_DEVICE_POWER_STATE { + NdisDeviceStateUnspecified = 0, + NdisDeviceStateD0, + NdisDeviceStateD1, + NdisDeviceStateD2, + NdisDeviceStateD3, + NdisDeviceStateMaximum +}; + +struct NDIS_PM_WAKE_UP_CAPABILITIES { + enum NDIS_DEVICE_POWER_STATE MinMagicPacketWakeUp; + enum NDIS_DEVICE_POWER_STATE MinPatternWakeUp; + enum NDIS_DEVICE_POWER_STATE MinLinkChangeWakeUp; +}; + +/* NDIS_PNP_CAPABILITIES.Flags constants */ +#define NDIS_DEVICE_WAKE_UP_ENABLE 0x00000001 +#define NDIS_DEVICE_WAKE_ON_PATTERN_MATCH_ENABLE 0x00000002 +#define NDIS_DEVICE_WAKE_ON_MAGIC_PACKET_ENABLE 0x00000004 + +/* +struct NDIS_PNP_CAPABILITIES { + __le32 Flags; + struct NDIS_PM_WAKE_UP_CAPABILITIES WakeUpCapabilities; +}; + +struct NDIS_PM_PACKET_PATTERN { + __le32 Priority; + __le32 Reserved; + __le32 MaskSize; + __le32 PatternOffset; + __le32 PatternSize; + __le32 PatternFlags; +}; +*/ + +/* Required Object IDs (OIDs) */ +#define OID_GEN_SUPPORTED_LIST 0x00010101 +#define OID_GEN_HARDWARE_STATUS 0x00010102 +#define OID_GEN_MEDIA_SUPPORTED 0x00010103 +#define OID_GEN_MEDIA_IN_USE 0x00010104 +#define OID_GEN_MAXIMUM_LOOKAHEAD 0x00010105 +#define OID_GEN_MAXIMUM_FRAME_SIZE 0x00010106 +#define OID_GEN_LINK_SPEED 0x00010107 +#define OID_GEN_TRANSMIT_BUFFER_SPACE 0x00010108 +#define OID_GEN_RECEIVE_BUFFER_SPACE 0x00010109 +#define OID_GEN_TRANSMIT_BLOCK_SIZE 0x0001010A +#define OID_GEN_RECEIVE_BLOCK_SIZE 0x0001010B +#define OID_GEN_VENDOR_ID 0x0001010C +#define OID_GEN_VENDOR_DESCRIPTION 0x0001010D +#define OID_GEN_CURRENT_PACKET_FILTER 0x0001010E +#define OID_GEN_CURRENT_LOOKAHEAD 0x0001010F +#define OID_GEN_DRIVER_VERSION 0x00010110 +#define OID_GEN_MAXIMUM_TOTAL_SIZE 0x00010111 +#define OID_GEN_PROTOCOL_OPTIONS 0x00010112 +#define OID_GEN_MAC_OPTIONS 0x00010113 +#define OID_GEN_MEDIA_CONNECT_STATUS 0x00010114 +#define OID_GEN_MAXIMUM_SEND_PACKETS 0x00010115 +#define OID_GEN_VENDOR_DRIVER_VERSION 0x00010116 +#define OID_GEN_SUPPORTED_GUIDS 0x00010117 +#define OID_GEN_NETWORK_LAYER_ADDRESSES 0x00010118 +#define OID_GEN_TRANSPORT_HEADER_OFFSET 0x00010119 +#define OID_GEN_MACHINE_NAME 0x0001021A +#define OID_GEN_RNDIS_CONFIG_PARAMETER 0x0001021B +#define OID_GEN_VLAN_ID 0x0001021C + +/* Optional OIDs */ +#define OID_GEN_MEDIA_CAPABILITIES 0x00010201 +#define OID_GEN_PHYSICAL_MEDIUM 0x00010202 + +/* Required statistics OIDs */ +#define OID_GEN_XMIT_OK 0x00020101 +#define OID_GEN_RCV_OK 0x00020102 +#define OID_GEN_XMIT_ERROR 0x00020103 +#define OID_GEN_RCV_ERROR 0x00020104 +#define OID_GEN_RCV_NO_BUFFER 0x00020105 + +/* Optional statistics OIDs */ +#define OID_GEN_DIRECTED_BYTES_XMIT 0x00020201 +#define OID_GEN_DIRECTED_FRAMES_XMIT 0x00020202 +#define OID_GEN_MULTICAST_BYTES_XMIT 0x00020203 +#define OID_GEN_MULTICAST_FRAMES_XMIT 0x00020204 +#define OID_GEN_BROADCAST_BYTES_XMIT 0x00020205 +#define OID_GEN_BROADCAST_FRAMES_XMIT 0x00020206 +#define OID_GEN_DIRECTED_BYTES_RCV 0x00020207 +#define OID_GEN_DIRECTED_FRAMES_RCV 0x00020208 +#define OID_GEN_MULTICAST_BYTES_RCV 0x00020209 +#define OID_GEN_MULTICAST_FRAMES_RCV 0x0002020A +#define OID_GEN_BROADCAST_BYTES_RCV 0x0002020B +#define OID_GEN_BROADCAST_FRAMES_RCV 0x0002020C +#define OID_GEN_RCV_CRC_ERROR 0x0002020D +#define OID_GEN_TRANSMIT_QUEUE_LENGTH 0x0002020E +#define OID_GEN_GET_TIME_CAPS 0x0002020F +#define OID_GEN_GET_NETCARD_TIME 0x00020210 +#define OID_GEN_NETCARD_LOAD 0x00020211 +#define OID_GEN_DEVICE_PROFILE 0x00020212 +#define OID_GEN_INIT_TIME_MS 0x00020213 +#define OID_GEN_RESET_COUNTS 0x00020214 +#define OID_GEN_MEDIA_SENSE_COUNTS 0x00020215 +#define OID_GEN_FRIENDLY_NAME 0x00020216 +#define OID_GEN_MINIPORT_INFO 0x00020217 +#define OID_GEN_RESET_VERIFY_PARAMETERS 0x00020218 + +/* IEEE 802.3 (Ethernet) OIDs */ +#define NDIS_802_3_MAC_OPTION_PRIORITY 0x00000001 + +#define OID_802_3_PERMANENT_ADDRESS 0x01010101 +#define OID_802_3_CURRENT_ADDRESS 0x01010102 +#define OID_802_3_MULTICAST_LIST 0x01010103 +#define OID_802_3_MAXIMUM_LIST_SIZE 0x01010104 +#define OID_802_3_MAC_OPTIONS 0x01010105 +#define OID_802_3_RCV_ERROR_ALIGNMENT 0x01020101 +#define OID_802_3_XMIT_ONE_COLLISION 0x01020102 +#define OID_802_3_XMIT_MORE_COLLISIONS 0x01020103 +#define OID_802_3_XMIT_DEFERRED 0x01020201 +#define OID_802_3_XMIT_MAX_COLLISIONS 0x01020202 +#define OID_802_3_RCV_OVERRUN 0x01020203 +#define OID_802_3_XMIT_UNDERRUN 0x01020204 +#define OID_802_3_XMIT_HEARTBEAT_FAILURE 0x01020205 +#define OID_802_3_XMIT_TIMES_CRS_LOST 0x01020206 +#define OID_802_3_XMIT_LATE_COLLISIONS 0x01020207 + +/* Wireless LAN OIDs */ +/* Mandatory */ +#define OID_802_11_BSSID 0x0D010101 /* Q S */ +#define OID_802_11_SSID 0x0D010102 /* Q S */ +#define OID_802_11_NETWORK_TYPE_IN_USE 0x0D010204 /* Q S */ +#define OID_802_11_RSSI 0x0D010206 /* Q I */ +#define OID_802_11_BSSID_LIST 0x0D010217 /* Q */ +#define OID_802_11_BSSID_LIST_SCAN 0x0D01011A /* S */ +#define OID_802_11_INFRASTRUCTURE_MODE 0x0D010108 /* Q S */ +#define OID_802_11_SUPPORTED_RATES 0x0D01020E /* Q */ +#define OID_802_11_CONFIGURATION 0x0D010211 /* Q S */ +#define OID_802_11_ADD_WEP 0x0D010113 /* S */ +#define OID_802_11_WEP_STATUS 0x0D01011B /* Q S */ +#define OID_802_11_REMOVE_WEP 0x0D010114 /* S */ +#define OID_802_11_DISASSOCIATE 0x0D010115 /* S */ +#define OID_802_11_AUTHENTICATION_MODE 0x0D010118 /* Q S */ +#define OID_802_11_RELOAD_DEFAULTS 0x0D01011C /* S */ + +/* OID_GEN_MINIPORT_INFO constants */ +#define NDIS_MINIPORT_BUS_MASTER 0x00000001 +#define NDIS_MINIPORT_WDM_DRIVER 0x00000002 +#define NDIS_MINIPORT_SG_LIST 0x00000004 +#define NDIS_MINIPORT_SUPPORTS_MEDIA_QUERY 0x00000008 +#define NDIS_MINIPORT_INDICATES_PACKETS 0x00000010 +#define NDIS_MINIPORT_IGNORE_PACKET_QUEUE 0x00000020 +#define NDIS_MINIPORT_IGNORE_REQUEST_QUEUE 0x00000040 +#define NDIS_MINIPORT_IGNORE_TOKEN_RING_ERRORS 0x00000080 +#define NDIS_MINIPORT_INTERMEDIATE_DRIVER 0x00000100 +#define NDIS_MINIPORT_IS_NDIS_5 0x00000200 +#define NDIS_MINIPORT_IS_CO 0x00000400 +#define NDIS_MINIPORT_DESERIALIZE 0x00000800 +#define NDIS_MINIPORT_REQUIRES_MEDIA_POLLING 0x00001000 +#define NDIS_MINIPORT_SUPPORTS_MEDIA_SENSE 0x00002000 +#define NDIS_MINIPORT_NETBOOT_CARD 0x00004000 +#define NDIS_MINIPORT_PM_SUPPORTED 0x00008000 +#define NDIS_MINIPORT_SUPPORTS_MAC_ADDRESS_OVERWRITE 0x00010000 +#define NDIS_MINIPORT_USES_SAFE_BUFFER_APIS 0x00020000 +#define NDIS_MINIPORT_HIDDEN 0x00040000 +#define NDIS_MINIPORT_SWENUM 0x00080000 +#define NDIS_MINIPORT_SURPRISE_REMOVE_OK 0x00100000 +#define NDIS_MINIPORT_NO_HALT_ON_SUSPEND 0x00200000 +#define NDIS_MINIPORT_HARDWARE_DEVICE 0x00400000 +#define NDIS_MINIPORT_SUPPORTS_CANCEL_SEND_PACKETS 0x00800000 +#define NDIS_MINIPORT_64BITS_DMA 0x01000000 + +#define NDIS_MEDIUM_802_3 0x00000000 +#define NDIS_MEDIUM_802_5 0x00000001 +#define NDIS_MEDIUM_FDDI 0x00000002 +#define NDIS_MEDIUM_WAN 0x00000003 +#define NDIS_MEDIUM_LOCAL_TALK 0x00000004 +#define NDIS_MEDIUM_DIX 0x00000005 +#define NDIS_MEDIUM_ARCENT_RAW 0x00000006 +#define NDIS_MEDIUM_ARCENT_878_2 0x00000007 +#define NDIS_MEDIUM_ATM 0x00000008 +#define NDIS_MEDIUM_WIRELESS_LAN 0x00000009 +#define NDIS_MEDIUM_IRDA 0x0000000A +#define NDIS_MEDIUM_BPC 0x0000000B +#define NDIS_MEDIUM_CO_WAN 0x0000000C +#define NDIS_MEDIUM_1394 0x0000000D + +#define NDIS_PACKET_TYPE_DIRECTED 0x00000001 +#define NDIS_PACKET_TYPE_MULTICAST 0x00000002 +#define NDIS_PACKET_TYPE_ALL_MULTICAST 0x00000004 +#define NDIS_PACKET_TYPE_BROADCAST 0x00000008 +#define NDIS_PACKET_TYPE_SOURCE_ROUTING 0x00000010 +#define NDIS_PACKET_TYPE_PROMISCUOUS 0x00000020 +#define NDIS_PACKET_TYPE_SMT 0x00000040 +#define NDIS_PACKET_TYPE_ALL_LOCAL 0x00000080 +#define NDIS_PACKET_TYPE_GROUP 0x00000100 +#define NDIS_PACKET_TYPE_ALL_FUNCTIONAL 0x00000200 +#define NDIS_PACKET_TYPE_FUNCTIONAL 0x00000400 +#define NDIS_PACKET_TYPE_MAC_FRAME 0x00000800 + +#define NDIS_MEDIA_STATE_CONNECTED 0x00000000 +#define NDIS_MEDIA_STATE_DISCONNECTED 0x00000001 + +#define NDIS_MAC_OPTION_COPY_LOOKAHEAD_DATA 0x00000001 +#define NDIS_MAC_OPTION_RECEIVE_SERIALIZED 0x00000002 +#define NDIS_MAC_OPTION_TRANSFERS_NOT_PEND 0x00000004 +#define NDIS_MAC_OPTION_NO_LOOPBACK 0x00000008 +#define NDIS_MAC_OPTION_FULL_DUPLEX 0x00000010 +#define NDIS_MAC_OPTION_EOTX_INDICATION 0x00000020 +#define NDIS_MAC_OPTION_8021P_PRIORITY 0x00000040 +#define NDIS_MAC_OPTION_RESERVED 0x80000000 + +/** Hardware status of the underlying NIC */ +#define NDIS_HW_STS_READY 0x00000000UL +#define NDIS_HW_STS_INITIALIZING 0x00000001UL +#define NDIS_HW_STS_RESET 0x00000002UL +#define NDIS_HW_STS_CLOSING 0x00000003UL +#define NDIS_HW_STS_NOT_READY 0x00000004UL + +#endif /* _NDIS_H_ */ + +/** @} */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_protocol.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_protocol.h index af0ed8c17..8acb6756f 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_protocol.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_protocol.h @@ -1,9 +1,307 @@ +/** + * \file rndis_protocol.h + * RNDIS Defines + * + * \author + * Colin O'Flynn + * + * \addtogroup usbstick + */ + +/* Copyright (c) 2008 Colin O'Flynn + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + +/************************************************* +File name: rndis_protocol.h +Description: adopt cherry USB to XiZi AIOT. +Others: take CherryUSB v0.10.2/class/wireless/rndis_protocol.h for references + https://github.com/cherry-embedded/CherryUSB/blob/v0.10.2/class/wireless/rndis_protocol.h +*************************************************/ + #ifndef RNDIS_PROTOCOL_H_ #define RNDIS_PROTOCOL_H_ +/** + \addtogroup RNDIS + @{ + */ +#include +#define RNDIS_MAJOR_VERSION 1 +#define RNDIS_MINOR_VERSION 0 +#define RNDIS_STATUS_SUCCESS 0X00000000 +#define RNDIS_STATUS_FAILURE 0XC0000001 +#define RNDIS_STATUS_INVALID_DATA 0XC0010015 +#define RNDIS_STATUS_NOT_SUPPORTED 0XC00000BB +#define RNDIS_STATUS_MEDIA_CONNECT 0X4001000B +#define RNDIS_STATUS_MEDIA_DISCONNECT 0X4001000C +/* Message set for Connectionless (802.3) Devices */ +#define REMOTE_NDIS_PACKET_MSG 0x00000001 +#define REMOTE_NDIS_INITIALIZE_MSG 0X00000002 +#define REMOTE_NDIS_HALT_MSG 0X00000003 +#define REMOTE_NDIS_QUERY_MSG 0X00000004 +#define REMOTE_NDIS_SET_MSG 0X00000005 +#define REMOTE_NDIS_RESET_MSG 0X00000006 +#define REMOTE_NDIS_INDICATE_STATUS_MSG 0X00000007 +#define REMOTE_NDIS_KEEPALIVE_MSG 0X00000008 +#define REMOTE_NDIS_INITIALIZE_CMPLT 0X80000002 +#define REMOTE_NDIS_QUERY_CMPLT 0X80000004 +#define REMOTE_NDIS_SET_CMPLT 0X80000005 +#define REMOTE_NDIS_RESET_CMPLT 0X80000006 +#define REMOTE_NDIS_KEEPALIVE_CMPLT 0X80000008 + +typedef uint32_t rndis_MessageType_t; +typedef uint32_t rndis_MessageLength_t; +typedef uint32_t rndis_RequestId_t; +typedef uint32_t rndis_MajorVersion_t; +typedef uint32_t rndis_MinorVersion_t; +typedef uint32_t rndis_MaxTransferSize_t; +typedef uint32_t rndis_Status_t; + +/* Device Flags */ +#define RNDIS_DF_CONNECTIONLESS 0x00000001 +#define RNDIS_DF_CONNECTION_ORIENTED 0x00000002 +typedef uint32_t rndis_DeviceFlags_t; + +/* Mediums */ +#define RNDIS_MEDIUM_802_3 0x00000000 +typedef uint32_t rndis_Medium_t; + +typedef uint32_t rndis_MaxPacketsPerTransfer_t; +typedef uint32_t rndis_PacketAlignmentFactor_t; +typedef uint32_t rndis_AfListOffset_t; +typedef uint32_t rndis_AfListSize_t; + +/*** Remote NDIS Generic Message type ***/ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; +} rndis_generic_msg_t; + +/*** Remote NDIS Initialize Message ***/ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; + rndis_MajorVersion_t MajorVersion; + rndis_MinorVersion_t MinorVersion; + rndis_MaxTransferSize_t MaxTransferSize; +} rndis_initialize_msg_t; + +/* Response: */ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; + rndis_Status_t Status; + rndis_MajorVersion_t MajorVersion; + rndis_MinorVersion_t MinorVersion; + rndis_DeviceFlags_t DeviceFlags; + rndis_Medium_t Medium; + rndis_MaxPacketsPerTransfer_t MaxPacketsPerTransfer; + rndis_MaxTransferSize_t MaxTransferSize; + rndis_PacketAlignmentFactor_t PacketAlignmentFactor; + rndis_AfListOffset_t AfListOffset; + rndis_AfListSize_t AfListSize; +} rndis_initialize_cmplt_t; + +/*** Remote NDIS Halt Message ***/ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; +} rndis_halt_msg_t; + +typedef uint32_t rndis_Oid_t; +typedef uint32_t rndis_InformationBufferLength_t; +typedef uint32_t rndis_InformationBufferOffset_t; +typedef uint32_t rndis_DeviceVcHandle_t; + +/*** Remote NDIS Query Message ***/ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; + rndis_Oid_t Oid; + rndis_InformationBufferLength_t InformationBufferLength; + rndis_InformationBufferOffset_t InformationBufferOffset; + rndis_DeviceVcHandle_t DeviceVcHandle; +} rndis_query_msg_t; + +/* Response: */ + +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; + rndis_Status_t Status; + rndis_InformationBufferLength_t InformationBufferLength; + rndis_InformationBufferOffset_t InformationBufferOffset; +} rndis_query_cmplt_t; + +/*** Remote NDIS Set Message ***/ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; + rndis_Oid_t Oid; + rndis_InformationBufferLength_t InformationBufferLength; + rndis_InformationBufferOffset_t InformationBufferOffset; + rndis_DeviceVcHandle_t DeviceVcHandle; +} rndis_set_msg_t; + +/* Response */ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; + rndis_Status_t Status; +} rndis_set_cmplt_t; + +/* Information buffer layout for OID_GEN_RNDIS_CONFIG_PARAMETER */ +typedef uint32_t rndis_ParameterNameOffset_t; +typedef uint32_t rndis_ParameterNameLength_t; +typedef uint32_t rndis_ParameterType_t; +typedef uint32_t rndis_ParameterValueOffset_t; +typedef uint32_t rndis_ParameterValueLength_t; + +#define PARAMETER_TYPE_STRING 2 +#define PARAMETER_TYPE_NUMERICAL 0 + +typedef struct { + rndis_ParameterNameOffset_t ParameterNameOffset; + rndis_ParameterNameLength_t ParameterNameLength; + rndis_ParameterType_t ParameterType; + rndis_ParameterValueOffset_t ParameterValueOffset; + rndis_ParameterValueLength_t ParameterValueLength; +} rndis_config_parameter_t; + +typedef uint32_t rndis_Reserved_t; + +/*** Remote NDIS Soft Reset Message ***/ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_Reserved_t Reserved; +} rndis_reset_msg_t; + +typedef uint32_t rndis_AddressingReset_t; + +/* Response: */ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_Status_t Status; + rndis_AddressingReset_t AddressingReset; +} rndis_reset_cmplt_t; + +/*** Remote NDIS Indicate Status Message ***/ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_Status_t Status; + rndis_Status_t StatusBufferLength; + rndis_Status_t StatusBufferOffset; +} rndis_indicate_status_t; + +typedef uint32_t rndis_DiagStatus_t; +typedef uint32_t rndis_ErrorOffset_t; + +typedef struct { + rndis_DiagStatus_t DiagStatus; + rndis_ErrorOffset_t ErrorOffset; +} rndis_diagnostic_info_t; + +/*** Remote NDIS Keepalive Message */ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; +} rndis_keepalive_msg_t; + +/* Response: */ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; + rndis_Status_t Status; +} rndis_keepalive_cmplt_t; + +/*** Remote NDIS Data Packet ***/ + +typedef uint32_t rndis_DataOffset_t; +typedef uint32_t rndis_DataLength_t; +typedef uint32_t rndis_OOBDataOffset_t; +typedef uint32_t rndis_OOBDataLength_t; +typedef uint32_t rndis_NumOOBDataElements_t; +typedef uint32_t rndis_PerPacketInfoOffset_t; +typedef uint32_t rndis_PerPacketInfoLength_t; + +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_DataOffset_t DataOffset; + rndis_DataLength_t DataLength; + rndis_OOBDataOffset_t OOBDataOffset; + rndis_OOBDataLength_t OOBDataLength; + rndis_NumOOBDataElements_t NumOOBDataElements; + rndis_PerPacketInfoOffset_t PerPacketInfoOffset; + rndis_PerPacketInfoLength_t PerPacketInfoLength; + rndis_DeviceVcHandle_t DeviceVcHandle; + rndis_Reserved_t Reserved; +} rndis_data_packet_t; + +typedef uint32_t rndis_ClassInformationOffset_t; +typedef uint32_t rndis_Size_t; +typedef uint32_t rndis_Type_t; + +typedef struct { + rndis_Size_t Size; + rndis_Type_t Type; + rndis_ClassInformationOffset_t ClassInformationType; +} rndis_OOB_packet_t; + +#include "ndis.h" + +typedef enum rnids_state_e { + rndis_uninitialized, + rndis_initialized, + rndis_data_initialized +} rndis_state_t; + +typedef struct { + uint32_t txok; + uint32_t rxok; + uint32_t txbad; + uint32_t rxbad; +} usb_eth_stat_t; #endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c index 500bb1415..5cbb9b07b 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c @@ -1 +1,429 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/************************************************* +File name: usbh_rndis.c +Description: adopt cherry USB to XiZi AIOT. +Others: take CherryUSB v0.10.2/class/wireless/usbh_rndis.c for references + https://github.com/cherry-embedded/CherryUSB/blob/v0.10.2/class/wireless/usbh_rndis.c +*************************************************/ + +#include "usbh_core.h" #include "usbh_rndis.h" +#include "rndis_protocol.h" + +#define DEV_FORMAT "/dev/rndis" + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rndis_buf[4096]; + +static struct usbh_rndis g_rndis_class; + +static int usbh_rndis_init_msg_transfer(struct usbh_rndis *rndis_class) +{ + struct usb_setup_packet *setup = rndis_class->hport->setup; + int ret = 0; + rndis_initialize_msg_t *cmd; + rndis_initialize_cmplt_t *resp; + + cmd = (rndis_initialize_msg_t *)g_rndis_buf; + + cmd->MessageType = REMOTE_NDIS_INITIALIZE_MSG; + cmd->MessageLength = sizeof(rndis_initialize_msg_t); + cmd->RequestId = rndis_class->request_id++; + cmd->MajorVersion = 1; + cmd->MinorVersion = 0; + cmd->MaxTransferSize = 0x4000; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SEND_ENCAPSULATED_COMMAND; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = sizeof(rndis_initialize_msg_t); + + ret = usbh_control_transfer(rndis_class->hport->ep0, setup, (uint8_t *)cmd); + if (ret < 0) { + USB_LOG_ERR("rndis_initialize_msg_t send error, ret: %d\r\n", ret); + return ret; + } + + //ret = usbh_ep_intr_transfer() + + resp = (rndis_initialize_cmplt_t *)g_rndis_buf; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_GET_ENCAPSULATED_RESPONSE; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = 4096; + + ret = usbh_control_transfer(rndis_class->hport->ep0, setup, (uint8_t *)resp); + if (ret < 0) { + USB_LOG_ERR("rndis_initialize_cmplt_t recv error, ret: %d\r\n", ret); + return ret; + } + + return ret; +} + +int usbh_rndis_query_msg_transfer(struct usbh_rndis *rndis_class, uint32_t oid, uint32_t query_len, uint8_t *info, uint32_t *info_len) +{ + struct usb_setup_packet *setup = rndis_class->hport->setup; + int ret = 0; + rndis_query_msg_t *cmd; + rndis_query_cmplt_t *resp; + + cmd = (rndis_query_msg_t *)g_rndis_buf; + + cmd->MessageType = REMOTE_NDIS_QUERY_MSG; + cmd->MessageLength = query_len + sizeof(rndis_query_msg_t); + cmd->RequestId = rndis_class->request_id++; + cmd->Oid = oid; + cmd->InformationBufferLength = query_len; + cmd->InformationBufferOffset = 20; + cmd->DeviceVcHandle = 0; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SEND_ENCAPSULATED_COMMAND; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = query_len + sizeof(rndis_query_msg_t); + + ret = usbh_control_transfer(rndis_class->hport->ep0, setup, (uint8_t *)cmd); + if (ret < 0) { + USB_LOG_ERR("oid:%08x send error, ret: %d\r\n", (unsigned int)oid, ret); + return ret; + } + + //ret = usbh_ep_intr_transfer() + + resp = (rndis_query_cmplt_t *)g_rndis_buf; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_GET_ENCAPSULATED_RESPONSE; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = 4096; + + ret = usbh_control_transfer(rndis_class->hport->ep0, setup, (uint8_t *)resp); + if (ret < 0) { + USB_LOG_ERR("oid:%08x recv error, ret: %d\r\n", (unsigned int)oid, ret); + return ret; + } + + memcpy(info, ((uint8_t *)resp + sizeof(rndis_query_cmplt_t)), resp->InformationBufferLength); + *info_len = resp->InformationBufferLength; + + return ret; +} + +static int usbh_rndis_set_msg_transfer(struct usbh_rndis *rndis_class, uint32_t oid, uint8_t *info, uint32_t info_len) +{ + struct usb_setup_packet *setup = rndis_class->hport->setup; + int ret = 0; + rndis_set_msg_t *cmd; + rndis_set_cmplt_t *resp; + + cmd = (rndis_set_msg_t *)g_rndis_buf; + + cmd->MessageType = REMOTE_NDIS_SET_MSG; + cmd->MessageLength = info_len + sizeof(rndis_set_msg_t); + cmd->RequestId = rndis_class->request_id++; + cmd->Oid = oid; + cmd->InformationBufferLength = info_len; + cmd->InformationBufferOffset = 20; + cmd->DeviceVcHandle = 0; + + memcpy(((uint8_t *)cmd + sizeof(rndis_set_msg_t)), info, info_len); + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SEND_ENCAPSULATED_COMMAND; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = info_len + sizeof(rndis_set_msg_t); + + ret = usbh_control_transfer(rndis_class->hport->ep0, setup, (uint8_t *)cmd); + if (ret < 0) { + USB_LOG_ERR("oid:%08x send error, ret: %d\r\n", (unsigned int)oid, ret); + return ret; + } + + //ret = usbh_ep_intr_transfer(rndis_class->hport->intin,buf,len,500); + + resp = (rndis_set_cmplt_t *)g_rndis_buf; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_GET_ENCAPSULATED_RESPONSE; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = 4096; + + ret = usbh_control_transfer(rndis_class->hport->ep0, setup, (uint8_t *)resp); + if (ret < 0) { + USB_LOG_ERR("oid:%08x recv error, ret: %d\r\n", (unsigned int)oid, ret); + return ret; + } + + return ret; +} + +int usbh_rndis_bulk_out_transfer(struct usbh_rndis *rndis_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) +{ + int ret; + struct usbh_urb *urb = &rndis_class->bulkout_urb; + memset(urb, 0, sizeof(struct usbh_urb)); + + usbh_bulk_urb_fill(urb, rndis_class->bulkout, buffer, buflen, timeout, NULL, NULL); + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + return ret; +} + +int usbh_rndis_bulk_in_transfer(struct usbh_rndis *rndis_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) +{ + int ret; + struct usbh_urb *urb = &rndis_class->bulkin_urb; + memset(urb, 0, sizeof(struct usbh_urb)); + + usbh_bulk_urb_fill(urb, rndis_class->bulkin, buffer, buflen, timeout, NULL, NULL); + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + return ret; +} + +int usbh_rndis_keepalive(struct usbh_rndis *rndis_class) +{ + struct usb_setup_packet *setup = rndis_class->hport->setup; + int ret = 0; + rndis_keepalive_msg_t *cmd; + rndis_keepalive_cmplt_t *resp; + + cmd = (rndis_keepalive_msg_t *)g_rndis_buf; + + cmd->MessageType = REMOTE_NDIS_KEEPALIVE_MSG; + cmd->MessageLength = sizeof(rndis_keepalive_msg_t); + cmd->RequestId = rndis_class->request_id++; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SEND_ENCAPSULATED_COMMAND; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = sizeof(rndis_keepalive_msg_t); + + ret = usbh_control_transfer(rndis_class->hport->ep0, setup, (uint8_t *)cmd); + if (ret < 0) { + USB_LOG_ERR("keepalive send error, ret: %d\r\n", ret); + return ret; + } + + //ret = usbh_ep_intr_transfer(rndis_class->hport->intin,buf,len,500); + + resp = (rndis_keepalive_cmplt_t *)g_rndis_buf; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_GET_ENCAPSULATED_RESPONSE; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = 4096; + + ret = usbh_control_transfer(rndis_class->hport->ep0, setup, (uint8_t *)resp); + if (ret < 0) { + USB_LOG_ERR("keepalive recv error, ret: %d\r\n", ret); + return ret; + } + + return ret; +} + +static int usbh_rndis_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret; + uint32_t *oid_support_list; + unsigned int oid = 0; + unsigned int oid_num = 0; + uint32_t data_len; + uint8_t tmp_buffer[512]; + uint8_t data[32]; + + struct usbh_rndis *rndis_class = &g_rndis_class; + + memset(rndis_class, 0, sizeof(struct usbh_rndis)); + + rndis_class->hport = hport; + rndis_class->ctrl_intf = intf; + rndis_class->data_intf = intf + 1; + + hport->config.intf[intf].priv = rndis_class; + hport->config.intf[intf + 1].priv = NULL; + +#ifdef CONFIG_USBHOST_RNDIS_NOTIFY + ep_desc = &hport->config.intf[intf].altsetting[0].ep[0].ep_desc; + usbh_hport_activate_epx(&rndis_class->intin, hport, ep_desc); +#endif + for (uint8_t i = 0; i < hport->config.intf[intf + 1].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf + 1].altsetting[0].ep[i].ep_desc; + + if (ep_desc->bEndpointAddress & 0x80) { + usbh_hport_activate_epx(&rndis_class->bulkin, hport, ep_desc); + } else { + usbh_hport_activate_epx(&rndis_class->bulkout, hport, ep_desc); + } + } + + ret = usbh_rndis_init_msg_transfer(rndis_class); + if (ret < 0) { + return ret; + } + USB_LOG_INFO("rndis init success\r\n"); + + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_GEN_SUPPORTED_LIST, 0, tmp_buffer, &data_len); + if (ret < 0) { + return ret; + } + oid_num = (data_len / 4); + USB_LOG_INFO("rndis query OID_GEN_SUPPORTED_LIST success,oid num :%d\r\n", oid_num); + + oid_support_list = (uint32_t *)tmp_buffer; + + for (uint8_t i = 0; i < oid_num; i++) { + oid = oid_support_list[i]; + switch (oid) { + case OID_GEN_PHYSICAL_MEDIUM: + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_GEN_PHYSICAL_MEDIUM, 4, data, &data_len); + if (ret < 0) { + goto query_errorout; + } + break; + case OID_GEN_MAXIMUM_FRAME_SIZE: + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_GEN_MAXIMUM_FRAME_SIZE, 4, data, &data_len); + if (ret < 0) { + goto query_errorout; + } + break; + case OID_GEN_LINK_SPEED: + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_GEN_LINK_SPEED, 4, data, &data_len); + if (ret < 0) { + goto query_errorout; + } + + memcpy(&rndis_class->link_speed, data, 4); + break; + case OID_GEN_MEDIA_CONNECT_STATUS: + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_GEN_MEDIA_CONNECT_STATUS, 4, data, &data_len); + if (ret < 0) { + goto query_errorout; + } + if (NDIS_MEDIA_STATE_CONNECTED == data[0]) { + rndis_class->link_status = true; + } else { + rndis_class->link_status = false; + } + break; + case OID_802_3_MAXIMUM_LIST_SIZE: + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_802_3_MAXIMUM_LIST_SIZE, 4, data, &data_len); + if (ret < 0) { + goto query_errorout; + } + break; + case OID_802_3_CURRENT_ADDRESS: + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_802_3_CURRENT_ADDRESS, 6, data, &data_len); + if (ret < 0) { + goto query_errorout; + } + + for (uint8_t j = 0; j < 6; j++) { + rndis_class->mac[j] = data[j]; + } + break; + case OID_802_3_PERMANENT_ADDRESS: + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_802_3_PERMANENT_ADDRESS, 6, data, &data_len); + if (ret < 0) { + goto query_errorout; + } + break; + default: + USB_LOG_WRN("Ignore rndis query iod:%08x\r\n", oid); + continue; + } + USB_LOG_INFO("rndis query iod:%08x success\r\n", oid); + } + + uint32_t packet_filter = 0x0f; + usbh_rndis_set_msg_transfer(rndis_class, OID_GEN_CURRENT_PACKET_FILTER, (uint8_t *)&packet_filter, 4); + if (ret < 0) { + return ret; + } + USB_LOG_INFO("rndis set OID_GEN_CURRENT_PACKET_FILTER success\r\n"); + + uint8_t multicast_list[6] = { 0x01, 0x00, 0x5E, 0x00, 0x00, 0x01 }; + usbh_rndis_set_msg_transfer(rndis_class, OID_802_3_MULTICAST_LIST, multicast_list, 6); + if (ret < 0) { + return ret; + } + USB_LOG_INFO("rndis set OID_802_3_MULTICAST_LIST success\r\n"); + + memcpy(hport->config.intf[intf].devname, DEV_FORMAT, CONFIG_USBHOST_DEV_NAMELEN); + + USB_LOG_INFO("Register RNDIS Class:%s\r\n", hport->config.intf[intf].devname); + usbh_rndis_run(rndis_class); + return ret; +query_errorout: + USB_LOG_ERR("rndis query iod:%08x error\r\n", oid); + return ret; +} + +static int usbh_rndis_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_rndis *rndis_class = (struct usbh_rndis *)hport->config.intf[intf].priv; + + if (rndis_class) { + if (rndis_class->bulkin) { + usbh_pipe_free(rndis_class->bulkin); + } + + if (rndis_class->bulkout) { + usbh_pipe_free(rndis_class->bulkout); + } + + if (hport->config.intf[intf].devname[0] != '\0') { + USB_LOG_INFO("Unregister RNDIS Class:%s\r\n", hport->config.intf[intf].devname); + usbh_rndis_stop(rndis_class); + } + + memset(rndis_class, 0, sizeof(struct usbh_rndis)); + } + + return ret; +} + +__WEAK void usbh_rndis_run(struct usbh_rndis *rndis_class) +{ +} + +__WEAK void usbh_rndis_stop(struct usbh_rndis *rndis_class) +{ +} + +static const struct usbh_class_driver rndis_class_driver = { + .driver_name = "rndis", + .connect = usbh_rndis_connect, + .disconnect = usbh_rndis_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info rndis_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .class = USB_DEVICE_CLASS_WIRELESS, + .subclass = 0x01, + .protocol = 0x03, + .vid = 0x00, + .pid = 0x00, + .class_driver = &rndis_class_driver +}; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.h index c29198b50..26fea1f64 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.h @@ -1,9 +1,56 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +/************************************************* +File name: usbh_rndis.h +Description: adopt cherry USB to XiZi AIOT. +Others: take CherryUSB v0.10.2/class/wireless/usbh_rndis.h for references + https://github.com/cherry-embedded/CherryUSB/blob/v0.10.2/class/wireless/usbh_rndis.h +*************************************************/ #ifndef USBH_RNDIS_H_ #define USBH_RNDIS_H_ +#include +#include "usb_def.h" +#include "usb_cdc.h" +#include "usb_hc.h" +struct usbh_rndis { + struct usbh_hubport *hport; + uint8_t ctrl_intf; /* Control interface number */ + uint8_t data_intf; /* Data interface number */ + uint8_t minor; + usbh_pipe_t bulkin; /* Bulk IN endpoint */ + usbh_pipe_t bulkout; /* Bulk OUT endpoint */ + usbh_pipe_t intin; /* Notify endpoint */ + struct usbh_urb bulkin_urb; /* Bulk IN urb */ + struct usbh_urb bulkout_urb; /* Bulk OUT urb */ + uint32_t request_id; + uint32_t link_speed; + bool link_status; + uint8_t mac[6]; +}; - +#ifdef __cplusplus +extern "C" { #endif + +int usbh_rndis_bulk_out_transfer(struct usbh_rndis *rndis_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout); +int usbh_rndis_bulk_in_transfer(struct usbh_rndis *rndis_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout); + +int usbh_rndis_keepalive(struct usbh_rndis *rndis_class); + +void usbh_rndis_run(struct usbh_rndis *rndis_class); +void usbh_rndis_stop(struct usbh_rndis *rndis_class); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_RNDIS_H_ */ From 2da33e48dcccc2f58755756e0118c419c110aa73 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Wed, 10 Jul 2024 09:42:59 +0800 Subject: [PATCH 084/198] Added file modification description. --- .../services/drivers/usb/components/class/cdc/usb_cdc.h | 5 +++++ .../drivers/usb/components/class/wireless/usbh_rndis.h | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/cdc/usb_cdc.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/cdc/usb_cdc.h index 2fcbcefd8..3e42f1920 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/cdc/usb_cdc.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/cdc/usb_cdc.h @@ -9,6 +9,11 @@ File name: usb_cdc.h Description: adopt cherry USB to XiZi AIOT. Others: take CherryUSB v0.10.2/class/cdc/usb_cdc.h for references https://github.com/cherry-embedded/CherryUSB/blob/v0.10.2/class/cdc/usb_cdc.h + +History: +1. Date: 2024-07-09 +Author: AIIT XUOS Lab +Modification: Replace __PACKED with __attribute__((packed)) because of a compilation error. *************************************************/ #ifndef USB_CDC_H_ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.h index 26fea1f64..1aeac2992 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.h @@ -10,6 +10,11 @@ File name: usbh_rndis.h Description: adopt cherry USB to XiZi AIOT. Others: take CherryUSB v0.10.2/class/wireless/usbh_rndis.h for references https://github.com/cherry-embedded/CherryUSB/blob/v0.10.2/class/wireless/usbh_rndis.h + +History: +1. Date: 2024-07-09 +Author: AIIT XUOS Lab +Modification: Add usb_def.h stdbool.h and usb_hc.h because of a compilation error. *************************************************/ #ifndef USBH_RNDIS_H_ #define USBH_RNDIS_H_ From 4cceb8cd3bc6097808b9d86eb0ad0071900212ad Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Wed, 10 Jul 2024 09:44:08 +0800 Subject: [PATCH 085/198] rndis ADAPTS to usb core to decouple xhci. --- .../components/class/wireless/usbh_rndis.c | 29 +++++++++++-------- 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c index 5cbb9b07b..1e7f50102 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c @@ -9,6 +9,11 @@ File name: usbh_rndis.c Description: adopt cherry USB to XiZi AIOT. Others: take CherryUSB v0.10.2/class/wireless/usbh_rndis.c for references https://github.com/cherry-embedded/CherryUSB/blob/v0.10.2/class/wireless/usbh_rndis.c + +History: +1. Date: 2024-07-10 +Author: AIIT XUOS Lab +Modification: rndis ADAPTS to usb core to decouple xhci. *************************************************/ #include "usbh_core.h" @@ -43,7 +48,7 @@ static int usbh_rndis_init_msg_transfer(struct usbh_rndis *rndis_class) setup->wIndex = 0; setup->wLength = sizeof(rndis_initialize_msg_t); - ret = usbh_control_transfer(rndis_class->hport->ep0, setup, (uint8_t *)cmd); + ret = usbh_control_transfer_xiuos(rndis_class->hport, rndis_class->hport->ep0, setup, (uint8_t *)cmd); if (ret < 0) { USB_LOG_ERR("rndis_initialize_msg_t send error, ret: %d\r\n", ret); return ret; @@ -59,7 +64,7 @@ static int usbh_rndis_init_msg_transfer(struct usbh_rndis *rndis_class) setup->wIndex = 0; setup->wLength = 4096; - ret = usbh_control_transfer(rndis_class->hport->ep0, setup, (uint8_t *)resp); + ret = usbh_control_transfer_xiuos(rndis_class->hport, rndis_class->hport->ep0, setup, (uint8_t *)resp); if (ret < 0) { USB_LOG_ERR("rndis_initialize_cmplt_t recv error, ret: %d\r\n", ret); return ret; @@ -91,7 +96,7 @@ int usbh_rndis_query_msg_transfer(struct usbh_rndis *rndis_class, uint32_t oid, setup->wIndex = 0; setup->wLength = query_len + sizeof(rndis_query_msg_t); - ret = usbh_control_transfer(rndis_class->hport->ep0, setup, (uint8_t *)cmd); + ret = usbh_control_transfer_xiuos(rndis_class->hport, rndis_class->hport->ep0, setup, (uint8_t *)cmd); if (ret < 0) { USB_LOG_ERR("oid:%08x send error, ret: %d\r\n", (unsigned int)oid, ret); return ret; @@ -107,7 +112,7 @@ int usbh_rndis_query_msg_transfer(struct usbh_rndis *rndis_class, uint32_t oid, setup->wIndex = 0; setup->wLength = 4096; - ret = usbh_control_transfer(rndis_class->hport->ep0, setup, (uint8_t *)resp); + ret = usbh_control_transfer_xiuos(rndis_class->hport, rndis_class->hport->ep0, setup, (uint8_t *)resp); if (ret < 0) { USB_LOG_ERR("oid:%08x recv error, ret: %d\r\n", (unsigned int)oid, ret); return ret; @@ -143,7 +148,7 @@ static int usbh_rndis_set_msg_transfer(struct usbh_rndis *rndis_class, uint32_t setup->wIndex = 0; setup->wLength = info_len + sizeof(rndis_set_msg_t); - ret = usbh_control_transfer(rndis_class->hport->ep0, setup, (uint8_t *)cmd); + ret = usbh_control_transfer_xiuos(rndis_class->hport, rndis_class->hport->ep0, setup, (uint8_t *)cmd); if (ret < 0) { USB_LOG_ERR("oid:%08x send error, ret: %d\r\n", (unsigned int)oid, ret); return ret; @@ -159,7 +164,7 @@ static int usbh_rndis_set_msg_transfer(struct usbh_rndis *rndis_class, uint32_t setup->wIndex = 0; setup->wLength = 4096; - ret = usbh_control_transfer(rndis_class->hport->ep0, setup, (uint8_t *)resp); + ret = usbh_control_transfer_xiuos(rndis_class->hport, rndis_class->hport->ep0, setup, (uint8_t *)resp); if (ret < 0) { USB_LOG_ERR("oid:%08x recv error, ret: %d\r\n", (unsigned int)oid, ret); return ret; @@ -174,7 +179,7 @@ int usbh_rndis_bulk_out_transfer(struct usbh_rndis *rndis_class, uint8_t *buffer struct usbh_urb *urb = &rndis_class->bulkout_urb; memset(urb, 0, sizeof(struct usbh_urb)); - usbh_bulk_urb_fill(urb, rndis_class->bulkout, buffer, buflen, timeout, NULL, NULL); + usbh_bulk_urb_fill_xiuos(urb, rndis_class->hport, rndis_class->bulkout, buffer, buflen, timeout, NULL, NULL); ret = usbh_submit_urb(urb); if (ret == 0) { ret = urb->actual_length; @@ -188,7 +193,7 @@ int usbh_rndis_bulk_in_transfer(struct usbh_rndis *rndis_class, uint8_t *buffer, struct usbh_urb *urb = &rndis_class->bulkin_urb; memset(urb, 0, sizeof(struct usbh_urb)); - usbh_bulk_urb_fill(urb, rndis_class->bulkin, buffer, buflen, timeout, NULL, NULL); + usbh_bulk_urb_fill_xiuos(urb, rndis_class->hport, rndis_class->bulkin, buffer, buflen, timeout, NULL, NULL); ret = usbh_submit_urb(urb); if (ret == 0) { ret = urb->actual_length; @@ -215,7 +220,7 @@ int usbh_rndis_keepalive(struct usbh_rndis *rndis_class) setup->wIndex = 0; setup->wLength = sizeof(rndis_keepalive_msg_t); - ret = usbh_control_transfer(rndis_class->hport->ep0, setup, (uint8_t *)cmd); + ret = usbh_control_transfer_xiuos(rndis_class->hport, rndis_class->hport->ep0, setup, (uint8_t *)cmd); if (ret < 0) { USB_LOG_ERR("keepalive send error, ret: %d\r\n", ret); return ret; @@ -231,7 +236,7 @@ int usbh_rndis_keepalive(struct usbh_rndis *rndis_class) setup->wIndex = 0; setup->wLength = 4096; - ret = usbh_control_transfer(rndis_class->hport->ep0, setup, (uint8_t *)resp); + ret = usbh_control_transfer_xiuos(rndis_class->hport, rndis_class->hport->ep0, setup, (uint8_t *)resp); if (ret < 0) { USB_LOG_ERR("keepalive recv error, ret: %d\r\n", ret); return ret; @@ -386,11 +391,11 @@ static int usbh_rndis_disconnect(struct usbh_hubport *hport, uint8_t intf) if (rndis_class) { if (rndis_class->bulkin) { - usbh_pipe_free(rndis_class->bulkin); + usbh_pipe_free_xiuos(rndis_class->hport, rndis_class->bulkin); } if (rndis_class->bulkout) { - usbh_pipe_free(rndis_class->bulkout); + usbh_pipe_free_xiuos(rndis_class->hport, rndis_class->bulkout); } if (hport->config.intf[intf].devname[0] != '\0') { From a91baab6396cb5e050ddbfcae23b86770687f1d7 Mon Sep 17 00:00:00 2001 From: xj Date: Fri, 12 Jul 2024 04:21:57 -0700 Subject: [PATCH 086/198] for xhci command ring --- .../services/drivers/usb/components/port/xhci/xhci.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h index 975bb2fec..93b36c792 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h @@ -874,7 +874,8 @@ struct xhci_host { /* * Device context base address array. * - * dcbaa_addr holds the virtual address of the dcbaa, meanwhile dcbaa_phy keeps the value that should be writen to XHCI_OP_DCBAAP. + * dcbaa_addr holds the virtual address of the dcbaa, meanwhile dcbaa_phy keeps the value that should be writen to Device Context + * Base Address Array Pointer Register (XHCI_OP_DCBAAP). */ uintptr_t dcbaa_addr; uintptr_t dcbaa_phy; @@ -891,6 +892,12 @@ struct xhci_host { /** Command ring */ struct xhci_ring *cmds; + /* + * cmds_addr holds the virtual address of the command ring, meanwhile cmds_phy keeps the value that should be writen to Command Ring + * Control Register (XHCI_OP_CRCR). + */ + uintptr_t cmds_addr; + uintptr_t cmds_phy; /** Event ring */ struct xhci_ring *evts; struct xhci_er_seg *eseg; From f1f533cdc18d42a46b00cd136873abfdb22fa77c Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 16 Jul 2024 09:42:16 +0800 Subject: [PATCH 087/198] usbh_core hub and rndis use naive_mmap to assign virtual and physical addresses, and match the relevant codes. --- .../usb/components/class/hub/usbh_hub.c | 28 ++++- .../components/class/wireless/usbh_rndis.c | 109 +++++++++++++++--- .../drivers/usb/components/core/usbh_core.c | 31 +++-- .../drivers/usb/components/core/usbh_core.h | 20 +++- 4 files changed, 153 insertions(+), 35 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c index e3674d327..fef242ee0 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c @@ -13,10 +13,15 @@ History: 1. Date: 2024-06-24 Author: AIIT XUOS Lab Modification: Modify the hub to decouple from xhci. + +2. Date: 2024-07-16 +Author: AIIT XUOS Lab +Modification: rndis uses naive_mmap to assign virtual and physical addresses and match the relevant codes. *************************************************/ #include "usbh_hub.h" #include "usb_def.h" +#include "usyscall.h" #define DEV_FORMAT "/usb%d/hub%d" @@ -103,7 +108,7 @@ static int _usbh_hub_get_hub_descriptor(struct usbh_hub *hub, uint8_t *buffer) setup->wIndex = 0; setup->wLength = USB_SIZEOF_HUB_DESC; - ret = usbh_control_transfer_xiuos(hub->parent, hub->parent->ep0, setup, hub->g_hub_buf); + ret = usbh_control_transfer_xiuos(hub->parent, hub->parent->ep0, setup, hub->g_hub_buf_phy); if (ret < 0) { return ret; } @@ -124,7 +129,7 @@ static int _usbh_hub_get_status(struct usbh_hub *hub, uint8_t *buffer) setup->wIndex = 0; setup->wLength = 2; - ret = usbh_control_transfer_xiuos(hub->parent, hub->parent->ep0, setup, hub->g_hub_buf); + ret = usbh_control_transfer_xiuos(hub->parent, hub->parent->ep0, setup, hub->g_hub_buf_phy); if (ret < 0) { return ret; } @@ -146,7 +151,7 @@ static int _usbh_hub_get_portstatus(struct usbh_hub *hub, uint8_t port, struct h setup->wIndex = port; setup->wLength = 4; - ret = usbh_control_transfer_xiuos(hub->parent, hub->parent->ep0, setup, hub->g_hub_buf); + ret = usbh_control_transfer_xiuos(hub->parent, hub->parent->ep0, setup, hub->g_hub_buf_phy); if (ret < 0) { return ret; } @@ -289,7 +294,7 @@ static int usbh_hub_set_depth(struct usbh_hub *hub, uint16_t depth) setup->wValue = depth; setup->wIndex = 0; setup->wLength = 0; - return usbh_roothub_control(hub->usb, setup, NULL); + return usbh_roothub_control(hub->usb, setup, NULL); } else { return _usbh_hub_set_depth(hub, depth); } @@ -312,6 +317,8 @@ static int usbh_hub_connect(struct usbh_hubport *hport, uint8_t intf) struct usbh_bus *usb = usbh_get_bus_of_port(hport); int ret; int index; + uintptr_t vaddr, paddr; + int rc; index = usbh_hub_devno_alloc(); if (index > (CONFIG_USBHOST_MAX_EXTHUBS + EXTHUB_FIRST_INDEX - 1)) { @@ -327,6 +334,15 @@ static int usbh_hub_connect(struct usbh_hubport *hport, uint8_t intf) hub->parent = hport; hub->index = index; + /* g_hub_buf allocate virtual address and physical address*/ + rc = naive_mmap(&vaddr, &paddr, 32, false); + if(rc != 0){ + USB_LOG_ERR("g_hub_buf allocate error, ret: %d\n", rc); + return -ENOMEM; + } + hub->g_hub_buf = (uint8_t *)vaddr; + hub->g_hub_buf_phy = (uint8_t *)paddr; + hport->config.intf[intf].priv = hub; ret = _usbh_hub_get_hub_descriptor(hub, (uint8_t *)&hub->hub_desc); @@ -642,8 +658,8 @@ static void usbh_hub_events(struct usbh_hub *hub) child = &hub->child[port]; /** release child sources */ usbh_hubport_release(child); - - /** some USB 3.0 ip may failed to enable USB 2.0 port for USB 3.0 device */ + + /** some USB 3.0 ip may failed to enable USB 2.0 port for USB 3.0 device */ USB_LOG_WRN("Failed to enable port %u\r\n", port + 1); continue; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c index 1e7f50102..46f4b73a0 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c @@ -14,11 +14,16 @@ History: 1. Date: 2024-07-10 Author: AIIT XUOS Lab Modification: rndis ADAPTS to usb core to decouple xhci. + +2. Date: 2024-07-16 +Author: AIIT XUOS Lab +Modification: rndis uses naive_mmap to assign virtual and physical addresses and match the relevant codes. *************************************************/ #include "usbh_core.h" #include "usbh_rndis.h" #include "rndis_protocol.h" +#include "usyscall.h" #define DEV_FORMAT "/dev/rndis" @@ -32,8 +37,19 @@ static int usbh_rndis_init_msg_transfer(struct usbh_rndis *rndis_class) int ret = 0; rndis_initialize_msg_t *cmd; rndis_initialize_cmplt_t *resp; + rndis_initialize_msg_t *cmd_phy; + rndis_initialize_cmplt_t *resp_phy; + uintptr_t vaddr; + uintptr_t paddr; - cmd = (rndis_initialize_msg_t *)g_rndis_buf; + //cmd = (rndis_initialize_msg_t *)g_rndis_buf; + ret = naive_mmap(&vaddr, &paddr, sizeof(rndis_initialize_msg_t), false); + if(ret != 0){ + USB_LOG_ERR("rndis_initialize_msg_t allocate error, ret: %d\r\n", ret); + return -ENOMEM; + } + cmd = (rndis_initialize_msg_t *)vaddr; + cmd_phy = (rndis_initialize_msg_t *)paddr; cmd->MessageType = REMOTE_NDIS_INITIALIZE_MSG; cmd->MessageLength = sizeof(rndis_initialize_msg_t); @@ -48,7 +64,7 @@ static int usbh_rndis_init_msg_transfer(struct usbh_rndis *rndis_class) setup->wIndex = 0; setup->wLength = sizeof(rndis_initialize_msg_t); - ret = usbh_control_transfer_xiuos(rndis_class->hport, rndis_class->hport->ep0, setup, (uint8_t *)cmd); + ret = usbh_control_transfer_xiuos(rndis_class->hport, rndis_class->hport->ep0, setup, (uint8_t *)cmd_phy); if (ret < 0) { USB_LOG_ERR("rndis_initialize_msg_t send error, ret: %d\r\n", ret); return ret; @@ -56,7 +72,14 @@ static int usbh_rndis_init_msg_transfer(struct usbh_rndis *rndis_class) //ret = usbh_ep_intr_transfer() - resp = (rndis_initialize_cmplt_t *)g_rndis_buf; + //resp = (rndis_initialize_cmplt_t *)g_rndis_buf; + ret = naive_mmap(&vaddr, &paddr, 4096, false); // Parameter len is consistent with setup->wLength. + if(ret != 0){ + USB_LOG_ERR("rndis_initialize_cmplt_t allocate error, ret: %d\r\n", ret); + return -ENOMEM; + } + resp = (rndis_initialize_cmplt_t *)vaddr; + resp_phy = (rndis_initialize_cmplt_t *)paddr; setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; setup->bRequest = CDC_REQUEST_GET_ENCAPSULATED_RESPONSE; @@ -64,7 +87,7 @@ static int usbh_rndis_init_msg_transfer(struct usbh_rndis *rndis_class) setup->wIndex = 0; setup->wLength = 4096; - ret = usbh_control_transfer_xiuos(rndis_class->hport, rndis_class->hport->ep0, setup, (uint8_t *)resp); + ret = usbh_control_transfer_xiuos(rndis_class->hport, rndis_class->hport->ep0, setup, (uint8_t *)resp_phy); if (ret < 0) { USB_LOG_ERR("rndis_initialize_cmplt_t recv error, ret: %d\r\n", ret); return ret; @@ -79,8 +102,19 @@ int usbh_rndis_query_msg_transfer(struct usbh_rndis *rndis_class, uint32_t oid, int ret = 0; rndis_query_msg_t *cmd; rndis_query_cmplt_t *resp; + rndis_query_msg_t *cmd_phy; + rndis_query_cmplt_t *resp_phy; + uintptr_t vaddr; + uintptr_t paddr; - cmd = (rndis_query_msg_t *)g_rndis_buf; + //cmd = (rndis_query_msg_t *)g_rndis_buf; + ret = naive_mmap(&vaddr, &paddr, query_len + sizeof(rndis_query_msg_t), false); + if(ret != 0){ + USB_LOG_ERR("rndis_query_msg_t allocate error, ret: %d\r\n", ret); + return -ENOMEM; + } + cmd = (rndis_query_msg_t *)vaddr; + cmd_phy = (rndis_query_msg_t *)paddr; cmd->MessageType = REMOTE_NDIS_QUERY_MSG; cmd->MessageLength = query_len + sizeof(rndis_query_msg_t); @@ -96,7 +130,7 @@ int usbh_rndis_query_msg_transfer(struct usbh_rndis *rndis_class, uint32_t oid, setup->wIndex = 0; setup->wLength = query_len + sizeof(rndis_query_msg_t); - ret = usbh_control_transfer_xiuos(rndis_class->hport, rndis_class->hport->ep0, setup, (uint8_t *)cmd); + ret = usbh_control_transfer_xiuos(rndis_class->hport, rndis_class->hport->ep0, setup, (uint8_t *)cmd_phy); if (ret < 0) { USB_LOG_ERR("oid:%08x send error, ret: %d\r\n", (unsigned int)oid, ret); return ret; @@ -104,7 +138,14 @@ int usbh_rndis_query_msg_transfer(struct usbh_rndis *rndis_class, uint32_t oid, //ret = usbh_ep_intr_transfer() - resp = (rndis_query_cmplt_t *)g_rndis_buf; + //resp = (rndis_query_cmplt_t *)g_rndis_buf; + ret = naive_mmap(&vaddr, &paddr, 4096, false); + if(ret != 0){ + USB_LOG_ERR("rndis_query_cmplt_t allocate error, ret: %d\r\n", ret); + return -ENOMEM; + } + resp = (rndis_query_cmplt_t *)vaddr; + resp_phy = (rndis_query_cmplt_t *)paddr; setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; setup->bRequest = CDC_REQUEST_GET_ENCAPSULATED_RESPONSE; @@ -112,7 +153,7 @@ int usbh_rndis_query_msg_transfer(struct usbh_rndis *rndis_class, uint32_t oid, setup->wIndex = 0; setup->wLength = 4096; - ret = usbh_control_transfer_xiuos(rndis_class->hport, rndis_class->hport->ep0, setup, (uint8_t *)resp); + ret = usbh_control_transfer_xiuos(rndis_class->hport, rndis_class->hport->ep0, setup, (uint8_t *)resp_phy); if (ret < 0) { USB_LOG_ERR("oid:%08x recv error, ret: %d\r\n", (unsigned int)oid, ret); return ret; @@ -130,8 +171,19 @@ static int usbh_rndis_set_msg_transfer(struct usbh_rndis *rndis_class, uint32_t int ret = 0; rndis_set_msg_t *cmd; rndis_set_cmplt_t *resp; + rndis_set_msg_t *cmd_phy; + rndis_set_cmplt_t *resp_phy; + uintptr_t vaddr; + uintptr_t paddr; - cmd = (rndis_set_msg_t *)g_rndis_buf; + //cmd = (rndis_set_msg_t *)g_rndis_buf; + ret = naive_mmap(&vaddr, &paddr, info_len + sizeof(rndis_set_msg_t), false); + if(ret != 0){ + USB_LOG_ERR("rndis_set_msg_t allocate error, ret: %d\r\n", ret); + return -ENOMEM; + } + cmd = (rndis_set_msg_t *)vaddr; + cmd_phy = (rndis_set_msg_t *)paddr; cmd->MessageType = REMOTE_NDIS_SET_MSG; cmd->MessageLength = info_len + sizeof(rndis_set_msg_t); @@ -148,7 +200,7 @@ static int usbh_rndis_set_msg_transfer(struct usbh_rndis *rndis_class, uint32_t setup->wIndex = 0; setup->wLength = info_len + sizeof(rndis_set_msg_t); - ret = usbh_control_transfer_xiuos(rndis_class->hport, rndis_class->hport->ep0, setup, (uint8_t *)cmd); + ret = usbh_control_transfer_xiuos(rndis_class->hport, rndis_class->hport->ep0, setup, (uint8_t *)cmd_phy); if (ret < 0) { USB_LOG_ERR("oid:%08x send error, ret: %d\r\n", (unsigned int)oid, ret); return ret; @@ -156,7 +208,14 @@ static int usbh_rndis_set_msg_transfer(struct usbh_rndis *rndis_class, uint32_t //ret = usbh_ep_intr_transfer(rndis_class->hport->intin,buf,len,500); - resp = (rndis_set_cmplt_t *)g_rndis_buf; + //resp = (rndis_set_cmplt_t *)g_rndis_buf; + ret = naive_mmap(&vaddr, &paddr, 4096, false); + if(ret != 0){ + USB_LOG_ERR("rndis_set_cmplt_t allocate error, ret: %d\r\n", ret); + return -ENOMEM; + } + resp = (rndis_set_cmplt_t *)vaddr; + resp_phy = (rndis_set_cmplt_t *)paddr; setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; setup->bRequest = CDC_REQUEST_GET_ENCAPSULATED_RESPONSE; @@ -164,7 +223,7 @@ static int usbh_rndis_set_msg_transfer(struct usbh_rndis *rndis_class, uint32_t setup->wIndex = 0; setup->wLength = 4096; - ret = usbh_control_transfer_xiuos(rndis_class->hport, rndis_class->hport->ep0, setup, (uint8_t *)resp); + ret = usbh_control_transfer_xiuos(rndis_class->hport, rndis_class->hport->ep0, setup, (uint8_t *)resp_phy); if (ret < 0) { USB_LOG_ERR("oid:%08x recv error, ret: %d\r\n", (unsigned int)oid, ret); return ret; @@ -207,8 +266,19 @@ int usbh_rndis_keepalive(struct usbh_rndis *rndis_class) int ret = 0; rndis_keepalive_msg_t *cmd; rndis_keepalive_cmplt_t *resp; + rndis_keepalive_msg_t *cmd_phy; + rndis_keepalive_cmplt_t *resp_phy; + uintptr_t vaddr; + uintptr_t paddr; - cmd = (rndis_keepalive_msg_t *)g_rndis_buf; + //cmd = (rndis_keepalive_msg_t *)g_rndis_buf; + ret = naive_mmap(&vaddr, &paddr, sizeof(rndis_keepalive_msg_t), false); + if(ret != 0){ + USB_LOG_ERR("rndis_keepalive_msg_t allocate error, ret: %d\r\n", ret); + return -ENOMEM; + } + cmd = (rndis_keepalive_msg_t *)vaddr; + cmd_phy = (rndis_keepalive_msg_t *)paddr; cmd->MessageType = REMOTE_NDIS_KEEPALIVE_MSG; cmd->MessageLength = sizeof(rndis_keepalive_msg_t); @@ -220,7 +290,7 @@ int usbh_rndis_keepalive(struct usbh_rndis *rndis_class) setup->wIndex = 0; setup->wLength = sizeof(rndis_keepalive_msg_t); - ret = usbh_control_transfer_xiuos(rndis_class->hport, rndis_class->hport->ep0, setup, (uint8_t *)cmd); + ret = usbh_control_transfer_xiuos(rndis_class->hport, rndis_class->hport->ep0, setup, (uint8_t *)cmd_phy); if (ret < 0) { USB_LOG_ERR("keepalive send error, ret: %d\r\n", ret); return ret; @@ -228,7 +298,14 @@ int usbh_rndis_keepalive(struct usbh_rndis *rndis_class) //ret = usbh_ep_intr_transfer(rndis_class->hport->intin,buf,len,500); - resp = (rndis_keepalive_cmplt_t *)g_rndis_buf; + //resp = (rndis_keepalive_cmplt_t *)g_rndis_buf; + ret = naive_mmap(&vaddr, &paddr, 4096, false); + if(ret != 0){ + USB_LOG_ERR("rndis_keepalive_cmplt_t allocate error, ret: %d\r\n", ret); + return -ENOMEM; + } + resp = (rndis_keepalive_cmplt_t *)vaddr; + resp_phy = (rndis_keepalive_cmplt_t *)paddr; setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; setup->bRequest = CDC_REQUEST_GET_ENCAPSULATED_RESPONSE; @@ -236,7 +313,7 @@ int usbh_rndis_keepalive(struct usbh_rndis *rndis_class) setup->wIndex = 0; setup->wLength = 4096; - ret = usbh_control_transfer_xiuos(rndis_class->hport, rndis_class->hport->ep0, setup, (uint8_t *)resp); + ret = usbh_control_transfer_xiuos(rndis_class->hport, rndis_class->hport->ep0, setup, (uint8_t *)resp_phy); if (ret < 0) { USB_LOG_ERR("keepalive recv error, ret: %d\r\n", ret); return ret; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c index 1bff9fc37..7e5535504 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c @@ -24,11 +24,16 @@ Modification: Extract the functions of the host controller to core. Author: AIIT XUOS Lab Modification: Modifying functions in usb core is related to xhci. +4. Date: 2024-07-16 +Author: AIIT XUOS Lab +Modification: usb core uses naive_mmap to assign virtual and physical addresses and match the relevant codes. + *************************************************/ #include "usbh_core.h" #include "usbh_hub.h" #include "usb_hc_xhci.h" +#include "usyscall.h" struct usbh_class_info *usbh_class_info_table_begin = NULL; struct usbh_class_info *usbh_class_info_table_end = NULL; @@ -553,7 +558,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wLength = 8; dev_desc = (struct usb_device_descriptor *)usb->ep0_request_buffer; - ret = usbh_control_transfer_xiuos(hport, hport->ep0, setup, (uint8_t *)dev_desc); + ret = usbh_control_transfer_xiuos(hport, hport->ep0, setup, (uint8_t *)usb->ep0_request_buffer_phy); if (ret < 0) { USB_LOG_ERR("Failed to get device descriptor,errorcode:%d\r\n", ret); goto errout; @@ -611,7 +616,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wIndex = 0; setup->wLength = USB_SIZEOF_DEVICE_DESC; - ret = usbh_control_transfer_xiuos(hport, hport->ep0, setup, usb->ep0_request_buffer); + ret = usbh_control_transfer_xiuos(hport, hport->ep0, setup, usb->ep0_request_buffer_phy); if (ret < 0) { USB_LOG_ERR("Failed to get full device descriptor,errorcode:%d\r\n", ret); goto errout; @@ -630,7 +635,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wIndex = 0; setup->wLength = USB_SIZEOF_CONFIG_DESC; - ret = usbh_control_transfer_xiuos(hport, hport->ep0, setup, usb->ep0_request_buffer); + ret = usbh_control_transfer_xiuos(hport, hport->ep0, setup, usb->ep0_request_buffer_phy); if (ret < 0) { USB_LOG_ERR("Failed to get config descriptor,errorcode:%d\r\n", ret); goto errout; @@ -647,7 +652,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wIndex = 0; setup->wLength = wTotalLength; - ret = usbh_control_transfer_xiuos(hport, hport->ep0, setup, usb->ep0_request_buffer); + ret = usbh_control_transfer_xiuos(hport, hport->ep0, setup, usb->ep0_request_buffer_phy); if (ret < 0) { USB_LOG_ERR("Failed to get full config descriptor,errorcode:%d\r\n", ret); goto errout; @@ -674,7 +679,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wIndex = 0x0409; setup->wLength = 255; - ret = usbh_control_transfer_xiuos(hport, hport->ep0, setup, usb->ep0_request_buffer); + ret = usbh_control_transfer_xiuos(hport, hport->ep0, setup, usb->ep0_request_buffer_phy); if (ret < 0) { USB_LOG_ERR("Failed to get Manufacturer string,errorcode:%d\r\n", ret); goto errout; @@ -689,7 +694,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wIndex = 0x0409; setup->wLength = 255; - ret = usbh_control_transfer_xiuos(hport, hport->ep0, setup, usb->ep0_request_buffer); + ret = usbh_control_transfer_xiuos(hport, hport->ep0, setup, usb->ep0_request_buffer_phy); if (ret < 0) { USB_LOG_ERR("Failed to get get Product string,errorcode:%d\r\n", ret); goto errout; @@ -704,7 +709,7 @@ int usbh_enumerate(struct usbh_hubport *hport) setup->wIndex = 0x0409; setup->wLength = 255; - ret = usbh_control_transfer_xiuos(hport, hport->ep0, setup, usb->ep0_request_buffer); + ret = usbh_control_transfer_xiuos(hport, hport->ep0, setup, usb->ep0_request_buffer_phy); if (ret < 0) { USB_LOG_ERR("Failed to get get SerialNumber string,errorcode:%d\r\n", ret); goto errout; @@ -810,6 +815,9 @@ void *usbh_find_class_instance(const char *devname) int usbh_initialize(uint32_t id, struct usbh_bus *usb) { + uintptr_t vaddr, paddr; + int rc; + memset(usb, 0, sizeof(struct usbh_bus)); #ifdef __ARMCC_VERSION /* ARM C Compiler */ @@ -837,6 +845,15 @@ int usbh_initialize(uint32_t id, struct usbh_bus *usb) usb->hub_class_head.next = NULL; usb->id = id; + /* ep0_request_buffer allocate virtual address and physical address*/ + rc = naive_mmap(&vaddr, &paddr, CONFIG_USBHOST_REQUEST_BUFFER_LEN, false); + if(rc != 0){ + USB_LOG_ERR("ep0_request_buffer allocate error, ret: %d\n", rc); + return -ENOMEM; + } + usb->ep0_request_buffer = (uint8_t *)vaddr; + usb->ep0_request_buffer_phy = (uint8_t *)paddr; + usb_slist_add_tail(&usb_buses, &(usb->list)); usbh_hub_initialize(usb); return 0; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h index 3cba17813..919c6f737 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h @@ -18,6 +18,10 @@ Modification: New parameter usb_hc_type for host controller type. 2. Date: 2024-06-24 Author: AIIT XUOS Lab Modification: Refactor the function that fills urb with usb_hc_type. + +2. Date: 2024-07-16 +Author: AIIT XUOS Lab +Modification: Add physical addresses to data structures usbh_bus and usbh_bus. *************************************************/ @@ -167,8 +171,8 @@ struct usbh_configuration { struct usbh_hub; struct usbh_hubport { - /** Name */ - char name[32]; + /** Name */ + char name[32]; bool connected; /* True: device connected; false: disconnected */ uint8_t port; /* Hub port index */ uint8_t dev_addr; /* device address */ @@ -204,7 +208,9 @@ struct usbh_hub { usb_slist_t hub_event_list; struct usbh_bus *usb; uint32_t ports; /* num of ports */ - USB_MEM_ALIGNX uint8_t g_hub_buf[32]; + //USB_MEM_ALIGNX uint8_t g_hub_buf[32]; + uint8_t* g_hub_buf; //virtual address + uint8_t* g_hub_buf_phy; //physical address USB_MEM_ALIGNX uint8_t g_hub_intbuf[CONFIG_USBHOST_MAX_EXTHUBS + 1][1]; }; @@ -240,8 +246,8 @@ struct usbh_bus { usb_slist_t list; uint8_t id; uint8_t usb_hc_type; - /** Largest transfer allowed on the bus */ - size_t mtu; + /** Largest transfer allowed on the bus */ + size_t mtu; struct usbh_devaddr_map devgen; struct usbh_hub roothub; #if CONFIG_USBHOST_MAX_EXTHUBS > 0 @@ -257,7 +263,9 @@ struct usbh_bus { int (*hub_open)(struct usbh_hub *hub); void (*hub_close)(struct usbh_hub *hub); int (*root_open)(struct usbh_hub *hub); - USB_MEM_ALIGNX uint8_t ep0_request_buffer[CONFIG_USBHOST_REQUEST_BUFFER_LEN]; + //USB_MEM_ALIGNX uint8_t ep0_request_buffer[CONFIG_USBHOST_REQUEST_BUFFER_LEN]; + uint8_t* ep0_request_buffer; //virtual address + uint8_t* ep0_request_buffer_phy; //physical address USB_MEM_ALIGNX struct usb_setup_packet g_setup[CONFIG_USBHOST_MAX_EXTHUBS + 1][CONFIG_USBHOST_MAX_EHPORTS]; }; From 6504f11f00e87baba4b1a4478ba7125646d82fbe Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 16 Jul 2024 18:25:50 +0800 Subject: [PATCH 088/198] rndis uses naive_mmap to allocate memory during connect. --- .../components/class/wireless/usbh_rndis.c | 112 ++++++------------ 1 file changed, 39 insertions(+), 73 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c index 46f4b73a0..61259a7be 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c @@ -27,7 +27,11 @@ Modification: rndis uses naive_mmap to assign virtual and physical addresses and #define DEV_FORMAT "/dev/rndis" -USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rndis_buf[4096]; +//USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rndis_buf[4096]; +uint8_t *g_rndis_buf; +uint8_t *g_rndis_buf_phy; +uint8_t *g_rndis_keepalive_buf; +uint8_t *g_rndis_keepalive_buf_phy; static struct usbh_rndis g_rndis_class; @@ -39,17 +43,9 @@ static int usbh_rndis_init_msg_transfer(struct usbh_rndis *rndis_class) rndis_initialize_cmplt_t *resp; rndis_initialize_msg_t *cmd_phy; rndis_initialize_cmplt_t *resp_phy; - uintptr_t vaddr; - uintptr_t paddr; - //cmd = (rndis_initialize_msg_t *)g_rndis_buf; - ret = naive_mmap(&vaddr, &paddr, sizeof(rndis_initialize_msg_t), false); - if(ret != 0){ - USB_LOG_ERR("rndis_initialize_msg_t allocate error, ret: %d\r\n", ret); - return -ENOMEM; - } - cmd = (rndis_initialize_msg_t *)vaddr; - cmd_phy = (rndis_initialize_msg_t *)paddr; + cmd = (rndis_initialize_msg_t *)g_rndis_buf; + cmd_phy = (rndis_initialize_msg_t *)g_rndis_buf_phy; cmd->MessageType = REMOTE_NDIS_INITIALIZE_MSG; cmd->MessageLength = sizeof(rndis_initialize_msg_t); @@ -72,14 +68,8 @@ static int usbh_rndis_init_msg_transfer(struct usbh_rndis *rndis_class) //ret = usbh_ep_intr_transfer() - //resp = (rndis_initialize_cmplt_t *)g_rndis_buf; - ret = naive_mmap(&vaddr, &paddr, 4096, false); // Parameter len is consistent with setup->wLength. - if(ret != 0){ - USB_LOG_ERR("rndis_initialize_cmplt_t allocate error, ret: %d\r\n", ret); - return -ENOMEM; - } - resp = (rndis_initialize_cmplt_t *)vaddr; - resp_phy = (rndis_initialize_cmplt_t *)paddr; + resp = (rndis_initialize_cmplt_t *)g_rndis_buf; + resp_phy = (rndis_initialize_cmplt_t *)g_rndis_buf_phy; setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; setup->bRequest = CDC_REQUEST_GET_ENCAPSULATED_RESPONSE; @@ -104,17 +94,9 @@ int usbh_rndis_query_msg_transfer(struct usbh_rndis *rndis_class, uint32_t oid, rndis_query_cmplt_t *resp; rndis_query_msg_t *cmd_phy; rndis_query_cmplt_t *resp_phy; - uintptr_t vaddr; - uintptr_t paddr; - //cmd = (rndis_query_msg_t *)g_rndis_buf; - ret = naive_mmap(&vaddr, &paddr, query_len + sizeof(rndis_query_msg_t), false); - if(ret != 0){ - USB_LOG_ERR("rndis_query_msg_t allocate error, ret: %d\r\n", ret); - return -ENOMEM; - } - cmd = (rndis_query_msg_t *)vaddr; - cmd_phy = (rndis_query_msg_t *)paddr; + cmd = (rndis_query_msg_t *)g_rndis_buf; + cmd_phy = (rndis_query_msg_t *)g_rndis_buf_phy; cmd->MessageType = REMOTE_NDIS_QUERY_MSG; cmd->MessageLength = query_len + sizeof(rndis_query_msg_t); @@ -138,14 +120,8 @@ int usbh_rndis_query_msg_transfer(struct usbh_rndis *rndis_class, uint32_t oid, //ret = usbh_ep_intr_transfer() - //resp = (rndis_query_cmplt_t *)g_rndis_buf; - ret = naive_mmap(&vaddr, &paddr, 4096, false); - if(ret != 0){ - USB_LOG_ERR("rndis_query_cmplt_t allocate error, ret: %d\r\n", ret); - return -ENOMEM; - } - resp = (rndis_query_cmplt_t *)vaddr; - resp_phy = (rndis_query_cmplt_t *)paddr; + resp = (rndis_query_cmplt_t *)g_rndis_buf; + resp_phy = (rndis_query_cmplt_t *)g_rndis_buf_phy; setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; setup->bRequest = CDC_REQUEST_GET_ENCAPSULATED_RESPONSE; @@ -173,17 +149,9 @@ static int usbh_rndis_set_msg_transfer(struct usbh_rndis *rndis_class, uint32_t rndis_set_cmplt_t *resp; rndis_set_msg_t *cmd_phy; rndis_set_cmplt_t *resp_phy; - uintptr_t vaddr; - uintptr_t paddr; - //cmd = (rndis_set_msg_t *)g_rndis_buf; - ret = naive_mmap(&vaddr, &paddr, info_len + sizeof(rndis_set_msg_t), false); - if(ret != 0){ - USB_LOG_ERR("rndis_set_msg_t allocate error, ret: %d\r\n", ret); - return -ENOMEM; - } - cmd = (rndis_set_msg_t *)vaddr; - cmd_phy = (rndis_set_msg_t *)paddr; + cmd = (rndis_set_msg_t *)g_rndis_buf; + cmd_phy = (rndis_set_msg_t *)g_rndis_buf_phy; cmd->MessageType = REMOTE_NDIS_SET_MSG; cmd->MessageLength = info_len + sizeof(rndis_set_msg_t); @@ -208,14 +176,8 @@ static int usbh_rndis_set_msg_transfer(struct usbh_rndis *rndis_class, uint32_t //ret = usbh_ep_intr_transfer(rndis_class->hport->intin,buf,len,500); - //resp = (rndis_set_cmplt_t *)g_rndis_buf; - ret = naive_mmap(&vaddr, &paddr, 4096, false); - if(ret != 0){ - USB_LOG_ERR("rndis_set_cmplt_t allocate error, ret: %d\r\n", ret); - return -ENOMEM; - } - resp = (rndis_set_cmplt_t *)vaddr; - resp_phy = (rndis_set_cmplt_t *)paddr; + resp = (rndis_set_cmplt_t *)g_rndis_buf; + resp_phy = (rndis_set_cmplt_t *)g_rndis_buf_phy; setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; setup->bRequest = CDC_REQUEST_GET_ENCAPSULATED_RESPONSE; @@ -268,17 +230,9 @@ int usbh_rndis_keepalive(struct usbh_rndis *rndis_class) rndis_keepalive_cmplt_t *resp; rndis_keepalive_msg_t *cmd_phy; rndis_keepalive_cmplt_t *resp_phy; - uintptr_t vaddr; - uintptr_t paddr; - //cmd = (rndis_keepalive_msg_t *)g_rndis_buf; - ret = naive_mmap(&vaddr, &paddr, sizeof(rndis_keepalive_msg_t), false); - if(ret != 0){ - USB_LOG_ERR("rndis_keepalive_msg_t allocate error, ret: %d\r\n", ret); - return -ENOMEM; - } - cmd = (rndis_keepalive_msg_t *)vaddr; - cmd_phy = (rndis_keepalive_msg_t *)paddr; + cmd = (rndis_keepalive_msg_t *)g_rndis_keepalive_buf; + cmd_phy = (rndis_keepalive_msg_t *)g_rndis_keepalive_buf_phy; cmd->MessageType = REMOTE_NDIS_KEEPALIVE_MSG; cmd->MessageLength = sizeof(rndis_keepalive_msg_t); @@ -298,14 +252,8 @@ int usbh_rndis_keepalive(struct usbh_rndis *rndis_class) //ret = usbh_ep_intr_transfer(rndis_class->hport->intin,buf,len,500); - //resp = (rndis_keepalive_cmplt_t *)g_rndis_buf; - ret = naive_mmap(&vaddr, &paddr, 4096, false); - if(ret != 0){ - USB_LOG_ERR("rndis_keepalive_cmplt_t allocate error, ret: %d\r\n", ret); - return -ENOMEM; - } - resp = (rndis_keepalive_cmplt_t *)vaddr; - resp_phy = (rndis_keepalive_cmplt_t *)paddr; + resp = (rndis_keepalive_cmplt_t *)g_rndis_keepalive_buf; + resp_phy = (rndis_keepalive_cmplt_t *)g_rndis_keepalive_buf_phy; setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; setup->bRequest = CDC_REQUEST_GET_ENCAPSULATED_RESPONSE; @@ -332,6 +280,7 @@ static int usbh_rndis_connect(struct usbh_hubport *hport, uint8_t intf) uint32_t data_len; uint8_t tmp_buffer[512]; uint8_t data[32]; + uintptr_t vaddr, paddr; struct usbh_rndis *rndis_class = &g_rndis_class; @@ -341,6 +290,23 @@ static int usbh_rndis_connect(struct usbh_hubport *hport, uint8_t intf) rndis_class->ctrl_intf = intf; rndis_class->data_intf = intf + 1; + /* allocate virtual address and physical address*/ + ret = naive_mmap(&vaddr, &paddr, 4096, false); + if(ret != 0){ + USB_LOG_ERR("g_rndis_buf allocate error, ret: %d\n", ret); + return -ENOMEM; + } + g_rndis_buf = (uint8_t *)vaddr; + g_rndis_buf_phy = (uint8_t *)paddr; + + ret = naive_mmap(&vaddr, &paddr, 4096, false); + if(ret != 0){ + USB_LOG_ERR("g_rndis_keepalive_buf allocate error, ret: %d\n", ret); + return -ENOMEM; + } + g_rndis_keepalive_buf = (uint8_t *)vaddr; + g_rndis_keepalive_buf_phy = (uint8_t *)paddr; + hport->config.intf[intf].priv = rndis_class; hport->config.intf[intf + 1].priv = NULL; From 098d39181d3819c7e503116c8efe1c6731652c95 Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 16 Jul 2024 06:10:40 -0700 Subject: [PATCH 089/198] Command RING Initialize --- .../drivers/usb/components/port/xhci/xhci.c | 38 ++++++++++++++++++- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 8484d7430..09552e602 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -867,13 +867,31 @@ err_alloc_array_vir: */ static int xhci_command_alloc ( struct xhci_host *xhci ) { uintptr_t crp; - int rc; + uintptr_t cmds_addr, cmds_phy; + size_t len; + int rc, i; + struct xhci_trb_link *trb_link; /* Allocate TRB ring */ +#if 0 xhci->cmds = usb_align(XHCI_RING_SIZE, sizeof(*xhci->cmds)); /* command ring */ if (! xhci->cmds) goto err_ring_alloc; +#endif + len = sizeof(*xhci->cmds); + rc = naive_mmap(&cmds_addr, &cmds_phy, len, false); + + if(rc != 0){ + USB_LOG_ERR("XHCI %s could not allocate CMD RING\n", xhci->name ); + rc = -ENOMEM; + goto err_ring_alloc; + } + + xhci->cmds_addr = cmds_addr; + xhci->cmds_phy = cmds_phy; + + xhci->cmds = (struct xhci_ring *)cmds_addr; memset(xhci->cmds, 0U, sizeof(*xhci->cmds)); xhci->cmds->lock = usb_osal_mutex_create(); @@ -882,10 +900,26 @@ static int xhci_command_alloc ( struct xhci_host *xhci ) { xhci->cmds->cs = 1; /* cycle state = 1 */ /* Program command ring control register */ - crp = (uintptr_t)( xhci->cmds ); +// crp = (uintptr_t)( xhci->cmds ); + +#if 0 if ( ( rc = xhci_writeq ( xhci, ( crp | XHCI_CRCR_RCS ), xhci->op + XHCI_OP_CRCR ) ) != 0 ) goto err_writeq; +#endif + + for(i = 0; i < XHCI_RING_ITEMS; i++){ + trb_link = (struct xhci_trb_link *)&xhci->cmds->ring[i]; + trb_link->reserved_c |= XHCI_TRB_C; + + } + + trb_link = (struct xhci_trb_link *)&xhci->cmds->ring[XHCI_RING_ITEMS - 1]; + trb_link->reserved_c |= XHCI_TRB_TC; + +if ( ( rc = xhci_writeq ( xhci, ( cmds_phy | XHCI_CRCR_RCS ), + xhci->op_addr + XHCI_OP_CRCR ) ) != 0 ) + goto err_writeq; USB_LOG_DBG("XHCI %s CRCR at [%08lx,%08lx)\n", xhci->name, ( xhci->cmds->ring ), From f81170c61dd24ea23e687aa2c260c9594055fcdf Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 23 Jul 2024 09:24:27 +0800 Subject: [PATCH 090/198] Modify rndis_host.c according to CherryUSB v0.10.2 --- .../components/class/wireless/rndis_host.c | 239 ++++++++++++++++++ .../components/class/wireless/usbh_rndis.h | 1 + .../drivers/usb/components/osal/usb_osal.h | 1 + 3 files changed, 241 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c index 500bb1415..a38e6ab23 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c @@ -1 +1,240 @@ +/* FreeRTOS kernel includes. */ + +/************************************************* +File name: rndis_host.c +Description: adopt cherry USB to XiZi AIOT. +Others: CherryUSB v0.10.2/CherryUSB/third_party/FreeRTOS-10.4/rndis_host/rndis_host.c for references + https://github.com/cherry-embedded/CherryUSB/blob/v0.10.2/third_party/FreeRTOS-10.4/rndis_host/rndis_host.c + +History: +1. Date: 2024-07-22 +Author: AIIT XUOS Lab +Modification: Modify rndis_host.c according to + https://github.com/cherry-embedded/CherryUSB/blob/v0.10.2/third_party/FreeRTOS-10.4/rndis_host/rndis_host.c + https://github.com/cherry-embedded/CherryUSB/blob/v0.10.2/third_party/rt-thread-4.1.1/rndis_host/rndis_host_lwip2.1.2.c + and https://github.com/longtengmcu/USB-HOST-driver-4G-rndis-device/components/drivers/usb/usbhost/class/rndis_dev.c (Zhaoshimin). +*************************************************/ +#include +#include "usbh_core.h" #include "usbh_rndis.h" +#include "rndis_protocol.h" + +/* define the rdnis device state*/ +#define RNDIS_BUS_UNINITIALIZED 0 +#define RNDIS_BUS_INITIALIZED 1 +#define RNDIS_INITIALIZED 2 +#define RNDIS_DATA_INITIALIZED 3 + +#define USB_ETH_MTU (1500 + 14) +#define RNDIS_THREAD_STACK_SIZE (4096) + +#define NIOCTL_GADDR 0x01 +#define MAX_ADDR_LEN 6 +/* rndis device keepalive time 5000ms*/ +#define RNDIS_DEV_KEEPALIVE_TIMEOUT 5000 +/*should be the usb Integer multiple of maximum packet length N*64*/ +#define RNDIS_ETH_BUFFER_LEN (sizeof(rndis_data_packet_t) + USB_ETH_MTU + 42) +#define RNDIS_RXETH_BUFFER_LEN (RNDIS_ETH_BUFFER_LEN * 5) + +#define RT_TRUE 1 /**< boolean true */ +#define RT_FALSE 0 /**< boolean fails */ + +/* Static Variable Definition*/ +static struct usbh_rndis *s_rndis_class_ptr; + +USB_NOCACHE_RAM_SECTION uint8_t tx_buffer[RNDIS_ETH_BUFFER_LEN]; +USB_NOCACHE_RAM_SECTION uint8_t rx_buffer[RNDIS_RXETH_BUFFER_LEN]; +static uint8_t *rx_buf_ptr; +usb_osal_sem_t mutex_sem_handle; +usb_osal_thread_t timer_handle; +usb_osal_thread_t data_recv_task_handle; + +extern void eth_device_linkchange(bool up); //todo IPC function +extern void eth_device_ready(void *dataptr, size_t len); //todo IPC function + +static void rndis_dev_keepalive_timeout(void *pdata) +{ + int ret; + + while (1) { + usb_osal_msleep(RNDIS_DEV_KEEPALIVE_TIMEOUT); + + usb_osal_sem_take(mutex_sem_handle, USB_OSAL_WAITING_FOREVER); + ret = usbh_rndis_keepalive(s_rndis_class_ptr); + usb_osal_sem_give(mutex_sem_handle); + if (ret < 0) { + printf("rndis dev keepalive timeout!\n"); + } + } +} + +static void usbh_rndis_data_recv_entry(void *pdata) +{ + int ret = 0; + rndis_data_packet_t *pmsg; + int pmg_offset; + int recount = 5; + uint8_t data[4]; + uint32_t info_len = 0; + + struct usbh_rndis *rndis_class = (struct usbh_rndis *)pdata; + rx_buf_ptr = rx_buffer; + + if (!rndis_class->link_status) { + printf("linkdown, drop pkg\r\n"); + while(recount--) { + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_GEN_MEDIA_CONNECT_STATUS, sizeof(data), data, &info_len); + if (ret < 0) { + continue;; + } + if (NDIS_MEDIA_STATE_CONNECTED == data[0]) { + s_rndis_class_ptr->link_status = true; + eth_device_linkchange(RT_TRUE); + printf("linkup, drop pkg\r\n"); + break; + } else { + s_rndis_class_ptr->link_status = false; + eth_device_linkchange(RT_FALSE); + } + usb_osal_msleep(100); + } + } + + while (1) { + pmg_offset = 0; + ret = usbh_rndis_bulk_in_transfer(rndis_class, rx_buf_ptr, RNDIS_RXETH_BUFFER_LEN, USB_OSAL_WAITING_FOREVER); + if (ret <= 0) { + usb_osal_msleep(1); + continue; + } + while (ret > 0) { + pmsg = (rndis_data_packet_t *)(rx_buf_ptr + pmg_offset); + if (pmsg->MessageType == REMOTE_NDIS_PACKET_MSG) { + eth_device_ready((uint8_t *)(&pmsg->DataOffset) + pmsg->DataOffset, pmsg->MessageLength); + pmg_offset += pmsg->MessageLength; + ret -= pmsg->MessageLength; + } + } + } +} + +void usbh_rndis_run(struct usbh_rndis *rndis_class) +{ + s_rndis_class_ptr = rndis_class; + rx_buf_ptr = rx_buffer; + + mutex_sem_handle = usb_osal_sem_create(0); + if (NULL == mutex_sem_handle) { + printf("mutex semaphore creat faile!\r\n"); + return; + } + + timer_handle = usb_osal_thread_create("keepalive", RNDIS_THREAD_STACK_SIZE, 5, rndis_dev_keepalive_timeout, rndis_class); + if (NULL == timer_handle) { + printf("timer creation failed!\n"); + return; + } + + data_recv_task_handle = usb_osal_thread_create("rndis_recv", RNDIS_THREAD_STACK_SIZE, 5, usbh_rndis_data_recv_entry, rndis_class); + if (NULL == data_recv_task_handle) { + printf("rndis_lwip_rx Task creation failed!\n"); + return; + } +} + +void usbh_rndis_stop(struct usbh_rndis *rndis_class) +{ + usb_osal_thread_delete(data_recv_task_handle); + usb_osal_thread_delete(timer_handle); + usb_osal_sem_delete(mutex_sem_handle); + printf("rndis dev stop!\n"); +} + +static int rndis_msg_data_send(struct usbh_rndis *rndis_class, uint8_t *buffer, + int nbytes) +{ + int ret = 0; + int len = 0; + usb_osal_sem_take(mutex_sem_handle, USB_OSAL_WAITING_FOREVER); + len = usbh_rndis_bulk_out_transfer(rndis_class, buffer, nbytes, 5000); + usb_osal_sem_give(mutex_sem_handle); + if (len != nbytes) { + printf("rndis msg send fail\r\n"); + ret = -EBUSY; + } + return ret; +} + +int usbh_rndis_eth_tx(void *dataptr, size_t tot_len) +{ + uint8_t *buffer; + rndis_data_packet_t *hdr; + int ret; + int recount = 5; + uint8_t data[4]; + uint32_t info_len = 0; + + if (!s_rndis_class_ptr->link_status) { + printf("linkdown, drop pkg\r\n"); + while (recount--) { + ret = usbh_rndis_query_msg_transfer(s_rndis_class_ptr, OID_GEN_MEDIA_CONNECT_STATUS, sizeof(data), data, &info_len); + if (ret < 0) { + return -EBUSY; + } + if (NDIS_MEDIA_STATE_CONNECTED == data[0]) { + s_rndis_class_ptr->link_status = true; + eth_device_linkchange(RT_TRUE); + printf("linkup, drop pkg\r\n"); + break; + } else { + s_rndis_class_ptr->link_status = false; + eth_device_linkchange(RT_FALSE); + } + usb_osal_msleep(100); + } + return 0; + } + + USB_ASSERT((tot_len + sizeof(rndis_data_packet_t)) < sizeof(tx_buffer)); + if (tot_len > sizeof(tx_buffer)) { + printf("RNDIS MTU is:%d, but the send packet size is %d\r\n", sizeof(tx_buffer), tot_len); + tot_len = sizeof(tx_buffer); + } + + hdr = (rndis_data_packet_t *)tx_buffer; + memset(hdr, 0, sizeof(rndis_data_packet_t)); + hdr->MessageType = REMOTE_NDIS_PACKET_MSG; + hdr->MessageLength = sizeof(rndis_data_packet_t) + tot_len; + hdr->DataOffset = sizeof(rndis_data_packet_t) - sizeof(rndis_generic_msg_t); + hdr->DataLength = tot_len; + + buffer = (uint8_t *)(tx_buffer + sizeof(rndis_data_packet_t)); + memcpy(buffer, dataptr, tot_len); + + /* send */ + if ((hdr->MessageLength & 0x1FF) == 0) { + /* pad a dummy. */ + hdr->MessageLength += 1; + } + return rndis_msg_data_send(s_rndis_class_ptr, (uint8_t *)tx_buffer, hdr->MessageLength); +} + +int usbh_rndis_eth_control(int cmd, void *args) +{ + switch (cmd) { + case NIOCTL_GADDR: + /* get mac address */ + if (args) { + memcpy(args, s_rndis_class_ptr->mac, MAX_ADDR_LEN); + } else { + return -EINVAL; + } + break; + + default: + break; + } + + return 0; +} + diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.h index 1aeac2992..4d0dfaf28 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.h @@ -50,6 +50,7 @@ int usbh_rndis_bulk_out_transfer(struct usbh_rndis *rndis_class, uint8_t *buffer int usbh_rndis_bulk_in_transfer(struct usbh_rndis *rndis_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout); int usbh_rndis_keepalive(struct usbh_rndis *rndis_class); +int usbh_rndis_query_msg_transfer(struct usbh_rndis *rndis_class, uint32_t oid, uint32_t query_len, uint8_t *info, uint32_t *info_len); void usbh_rndis_run(struct usbh_rndis *rndis_class); void usbh_rndis_stop(struct usbh_rndis *rndis_class); diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.h index f9510af95..9cc4a7587 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.h @@ -22,6 +22,7 @@ Modification: introduce message queue mechanism. #include #include "usb_config.h" +#define USB_OSAL_WAITING_FOREVER (0xFFFFFFFFU) typedef void *usb_osal_thread_t; typedef void *usb_osal_sem_t; From 46d67a211578f902e2e146c78dead741567c0538 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 23 Jul 2024 14:56:38 +0800 Subject: [PATCH 091/198] rndis bulk transfer buffer uses physical addresses --- .../components/class/wireless/rndis_host.c | 54 ++++++++++++++----- 1 file changed, 41 insertions(+), 13 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c index a38e6ab23..7b9889d66 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c @@ -13,11 +13,16 @@ Modification: Modify rndis_host.c according to https://github.com/cherry-embedded/CherryUSB/blob/v0.10.2/third_party/FreeRTOS-10.4/rndis_host/rndis_host.c https://github.com/cherry-embedded/CherryUSB/blob/v0.10.2/third_party/rt-thread-4.1.1/rndis_host/rndis_host_lwip2.1.2.c and https://github.com/longtengmcu/USB-HOST-driver-4G-rndis-device/components/drivers/usb/usbhost/class/rndis_dev.c (Zhaoshimin). + +2. Date: 2024-07-23 +Author: AIIT XUOS Lab +Modification: rndis bulk transfer buffer uses physical addresses. *************************************************/ #include #include "usbh_core.h" #include "usbh_rndis.h" #include "rndis_protocol.h" +#include "usyscall.h" /* define the rdnis device state*/ #define RNDIS_BUS_UNINITIALIZED 0 @@ -34,7 +39,8 @@ Modification: Modify rndis_host.c according to #define RNDIS_DEV_KEEPALIVE_TIMEOUT 5000 /*should be the usb Integer multiple of maximum packet length N*64*/ #define RNDIS_ETH_BUFFER_LEN (sizeof(rndis_data_packet_t) + USB_ETH_MTU + 42) -#define RNDIS_RXETH_BUFFER_LEN (RNDIS_ETH_BUFFER_LEN * 5) +/* The maximum number of concatenated REMOTE_NDIS_PACKET_MSG messages in a single bus transfer to it, see MaxPacketsPerTransfer in REMOTE_NDIS_INITIALIZE_CMPLT. */ +#define RNDIS_RXETH_BUFFER_LEN (RNDIS_ETH_BUFFER_LEN * 1) #define RT_TRUE 1 /**< boolean true */ #define RT_FALSE 0 /**< boolean fails */ @@ -42,9 +48,14 @@ Modification: Modify rndis_host.c according to /* Static Variable Definition*/ static struct usbh_rndis *s_rndis_class_ptr; -USB_NOCACHE_RAM_SECTION uint8_t tx_buffer[RNDIS_ETH_BUFFER_LEN]; -USB_NOCACHE_RAM_SECTION uint8_t rx_buffer[RNDIS_RXETH_BUFFER_LEN]; -static uint8_t *rx_buf_ptr; +//USB_NOCACHE_RAM_SECTION uint8_t tx_buffer[RNDIS_ETH_BUFFER_LEN]; +//USB_NOCACHE_RAM_SECTION uint8_t rx_buffer[RNDIS_RXETH_BUFFER_LEN]; +//static uint8_t *rx_buf_ptr; +static uint8_t *tx_buffer; +static uint8_t *tx_buffer_phy; +static uint8_t *rx_buffer; +static uint8_t *rx_buffer_phy; + usb_osal_sem_t mutex_sem_handle; usb_osal_thread_t timer_handle; usb_osal_thread_t data_recv_task_handle; @@ -78,7 +89,6 @@ static void usbh_rndis_data_recv_entry(void *pdata) uint32_t info_len = 0; struct usbh_rndis *rndis_class = (struct usbh_rndis *)pdata; - rx_buf_ptr = rx_buffer; if (!rndis_class->link_status) { printf("linkdown, drop pkg\r\n"); @@ -102,13 +112,13 @@ static void usbh_rndis_data_recv_entry(void *pdata) while (1) { pmg_offset = 0; - ret = usbh_rndis_bulk_in_transfer(rndis_class, rx_buf_ptr, RNDIS_RXETH_BUFFER_LEN, USB_OSAL_WAITING_FOREVER); + ret = usbh_rndis_bulk_in_transfer(rndis_class, rx_buffer_phy, RNDIS_RXETH_BUFFER_LEN, USB_OSAL_WAITING_FOREVER); if (ret <= 0) { usb_osal_msleep(1); continue; } while (ret > 0) { - pmsg = (rndis_data_packet_t *)(rx_buf_ptr + pmg_offset); + pmsg = (rndis_data_packet_t *)(rx_buffer + pmg_offset); if (pmsg->MessageType == REMOTE_NDIS_PACKET_MSG) { eth_device_ready((uint8_t *)(&pmsg->DataOffset) + pmsg->DataOffset, pmsg->MessageLength); pmg_offset += pmsg->MessageLength; @@ -120,8 +130,26 @@ static void usbh_rndis_data_recv_entry(void *pdata) void usbh_rndis_run(struct usbh_rndis *rndis_class) { + uintptr_t vaddr, paddr; + int ret; + s_rndis_class_ptr = rndis_class; - rx_buf_ptr = rx_buffer; + + ret = naive_mmap(&vaddr, &paddr, RNDIS_ETH_BUFFER_LEN, false); + if(ret != 0){ + USB_LOG_ERR("tx_buf_ptr allocate error, ret: %d\n", ret); + return; + } + tx_buffer = (uint8_t *)vaddr; + tx_buffer_phy = (uint8_t *)paddr; + + ret = naive_mmap(&vaddr, &paddr, RNDIS_RXETH_BUFFER_LEN, false); + if(ret != 0){ + USB_LOG_ERR("rx_buf_ptr allocate error, ret: %d\n", ret); + return; + } + rx_buffer = (uint8_t *)vaddr; + rx_buffer_phy = (uint8_t *)paddr; mutex_sem_handle = usb_osal_sem_create(0); if (NULL == mutex_sem_handle) { @@ -195,10 +223,10 @@ int usbh_rndis_eth_tx(void *dataptr, size_t tot_len) return 0; } - USB_ASSERT((tot_len + sizeof(rndis_data_packet_t)) < sizeof(tx_buffer)); - if (tot_len > sizeof(tx_buffer)) { - printf("RNDIS MTU is:%d, but the send packet size is %d\r\n", sizeof(tx_buffer), tot_len); - tot_len = sizeof(tx_buffer); + USB_ASSERT((tot_len + sizeof(rndis_data_packet_t)) < RNDIS_ETH_BUFFER_LEN); + if (tot_len > RNDIS_ETH_BUFFER_LEN) { + printf("RNDIS MTU is:%d, but the send packet size is %d\r\n", RNDIS_ETH_BUFFER_LEN, tot_len); + tot_len = RNDIS_ETH_BUFFER_LEN; } hdr = (rndis_data_packet_t *)tx_buffer; @@ -216,7 +244,7 @@ int usbh_rndis_eth_tx(void *dataptr, size_t tot_len) /* pad a dummy. */ hdr->MessageLength += 1; } - return rndis_msg_data_send(s_rndis_class_ptr, (uint8_t *)tx_buffer, hdr->MessageLength); + return rndis_msg_data_send(s_rndis_class_ptr, (uint8_t *)tx_buffer_phy, hdr->MessageLength); } int usbh_rndis_eth_control(int cmd, void *args) From 1d7bcb479d42cf92fc4c355027ef4ee649f2825b Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 23 Jul 2024 18:17:59 +0800 Subject: [PATCH 092/198] Modify MessageLength in usbh_rndis_eth_tx --- .../components/class/wireless/rndis_host.c | 21 ++++++++++--------- .../components/class/wireless/usbh_rndis.c | 1 + .../components/class/wireless/usbh_rndis.h | 1 + 3 files changed, 13 insertions(+), 10 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c index 7b9889d66..a09cd73c2 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c @@ -17,6 +17,10 @@ Modification: Modify rndis_host.c according to 2. Date: 2024-07-23 Author: AIIT XUOS Lab Modification: rndis bulk transfer buffer uses physical addresses. + +3. Date: 2024-07-23 +Author: AIIT XUOS Lab +Modification: Modify MessageLength in usbh_rndis_eth_tx, see https://github.com/cherry-embedded/CherryUSB. *************************************************/ #include #include "usbh_core.h" @@ -42,9 +46,6 @@ Modification: rndis bulk transfer buffer uses physical addresses. /* The maximum number of concatenated REMOTE_NDIS_PACKET_MSG messages in a single bus transfer to it, see MaxPacketsPerTransfer in REMOTE_NDIS_INITIALIZE_CMPLT. */ #define RNDIS_RXETH_BUFFER_LEN (RNDIS_ETH_BUFFER_LEN * 1) -#define RT_TRUE 1 /**< boolean true */ -#define RT_FALSE 0 /**< boolean fails */ - /* Static Variable Definition*/ static struct usbh_rndis *s_rndis_class_ptr; @@ -99,12 +100,12 @@ static void usbh_rndis_data_recv_entry(void *pdata) } if (NDIS_MEDIA_STATE_CONNECTED == data[0]) { s_rndis_class_ptr->link_status = true; - eth_device_linkchange(RT_TRUE); + eth_device_linkchange(true); printf("linkup, drop pkg\r\n"); break; } else { s_rndis_class_ptr->link_status = false; - eth_device_linkchange(RT_FALSE); + eth_device_linkchange(false); } usb_osal_msleep(100); } @@ -211,12 +212,12 @@ int usbh_rndis_eth_tx(void *dataptr, size_t tot_len) } if (NDIS_MEDIA_STATE_CONNECTED == data[0]) { s_rndis_class_ptr->link_status = true; - eth_device_linkchange(RT_TRUE); + eth_device_linkchange(true); printf("linkup, drop pkg\r\n"); break; } else { s_rndis_class_ptr->link_status = false; - eth_device_linkchange(RT_FALSE); + eth_device_linkchange(false); } usb_osal_msleep(100); } @@ -239,11 +240,11 @@ int usbh_rndis_eth_tx(void *dataptr, size_t tot_len) buffer = (uint8_t *)(tx_buffer + sizeof(rndis_data_packet_t)); memcpy(buffer, dataptr, tot_len); - /* send */ - if ((hdr->MessageLength & 0x1FF) == 0) { - /* pad a dummy. */ + /* if message length is the multiple of wMaxPacketSize, we should add a short packet to tell device transfer is over. */ + if (!(hdr->MessageLength % s_rndis_class_ptr->ep_mps)) { hdr->MessageLength += 1; } + return rndis_msg_data_send(s_rndis_class_ptr, (uint8_t *)tx_buffer_phy, hdr->MessageLength); } diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c index 61259a7be..96bcb47f5 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c @@ -321,6 +321,7 @@ static int usbh_rndis_connect(struct usbh_hubport *hport, uint8_t intf) usbh_hport_activate_epx(&rndis_class->bulkin, hport, ep_desc); } else { usbh_hport_activate_epx(&rndis_class->bulkout, hport, ep_desc); + rndis_class->ep_mps = ep_desc->wMaxPacketSize; } } diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.h index 4d0dfaf28..2f7e293c9 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.h @@ -37,6 +37,7 @@ struct usbh_rndis { struct usbh_urb bulkout_urb; /* Bulk OUT urb */ uint32_t request_id; + uint32_t ep_mps; uint32_t link_speed; bool link_status; uint8_t mac[6]; From 181362892a310824f3d334b0a1cd15c7efcf031a Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Wed, 24 Jul 2024 15:44:24 +0800 Subject: [PATCH 093/198] Modify IPC-related functions in rndis host --- .../components/class/wireless/rndis_host.c | 20 +++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c index a09cd73c2..e9a82a47a 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c @@ -21,6 +21,10 @@ Modification: rndis bulk transfer buffer uses physical addresses. 3. Date: 2024-07-23 Author: AIIT XUOS Lab Modification: Modify MessageLength in usbh_rndis_eth_tx, see https://github.com/cherry-embedded/CherryUSB. + +4. Date: 2024-07-24 +Author: AIIT XUOS Lab +Modification: Modify IPC-related functions in rndis. *************************************************/ #include #include "usbh_core.h" @@ -61,8 +65,16 @@ usb_osal_sem_t mutex_sem_handle; usb_osal_thread_t timer_handle; usb_osal_thread_t data_recv_task_handle; -extern void eth_device_linkchange(bool up); //todo IPC function -extern void eth_device_ready(void *dataptr, size_t len); //todo IPC function + +__WEAK int eth_device_linkchange(bool up) +{ + return 0; +} + +__WEAK int eth_device_ready(void *dataptr, size_t len) +{ + return 0; +} static void rndis_dev_keepalive_timeout(void *pdata) { @@ -121,7 +133,7 @@ static void usbh_rndis_data_recv_entry(void *pdata) while (ret > 0) { pmsg = (rndis_data_packet_t *)(rx_buffer + pmg_offset); if (pmsg->MessageType == REMOTE_NDIS_PACKET_MSG) { - eth_device_ready((uint8_t *)(&pmsg->DataOffset) + pmsg->DataOffset, pmsg->MessageLength); + eth_device_ready((uint8_t *)(&pmsg->DataOffset) + pmsg->DataOffset, pmsg->DataLength); pmg_offset += pmsg->MessageLength; ret -= pmsg->MessageLength; } @@ -248,7 +260,7 @@ int usbh_rndis_eth_tx(void *dataptr, size_t tot_len) return rndis_msg_data_send(s_rndis_class_ptr, (uint8_t *)tx_buffer_phy, hdr->MessageLength); } -int usbh_rndis_eth_control(int cmd, void *args) +int usbh_rndis_eth_control(int cmd, void *args, size_t len) { switch (cmd) { case NIOCTL_GADDR: From bed67b388f95b843b7eff3af214d90f01b7921de Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 29 Jul 2024 02:03:42 -0700 Subject: [PATCH 094/198] Implanting event ring initialization --- .../drivers/usb/components/port/xhci/xhci.c | 58 +++++++++++++++++-- .../drivers/usb/components/port/xhci/xhci.h | 12 ++++ 2 files changed, 65 insertions(+), 5 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 09552e602..f4aa69518 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -941,35 +941,83 @@ if ( ( rc = xhci_writeq ( xhci, ( cmds_phy | XHCI_CRCR_RCS ), static int xhci_event_alloc ( struct xhci_host *xhci ) { unsigned int count; size_t len; + uintptr_t evts_addr, evts_phy, eseg_addr, eseg_phy; int rc; /* Allocate event ring */ + len = sizeof(*xhci->evts); + rc = naive_mmap(&evts_addr, &evts_phy, len, false); + + if(rc != 0){ + USB_LOG_ERR("XHCI %s could not allocate Event RING\n", xhci->name ); + rc = -ENOMEM; + goto err_alloc_trb; + } + + +#if 0 xhci->evts = usb_align(XHCI_RING_SIZE, sizeof(*xhci->evts)); /* event ring */ if ( ! xhci->evts ) { rc = -ENOMEM; goto err_alloc_trb; } +#endif + xhci->evts_addr = evts_addr; + xhci->evts_phy = evts_phy; + xhci->evts = (struct xhci_ring *)evts_addr; memset(xhci->evts, 0U, sizeof(*xhci->evts)); /* Allocate event ring segment table */ + + len = sizeof(*xhci->eseg); + rc = naive_mmap(&eseg_addr, &eseg_phy, len, false); + if(rc != 0){ + USB_LOG_ERR("XHCI %s could not allocate Event Segment\n", xhci->name ); + rc = -ENOMEM; + goto err_alloc_segment; + } + +#if 0 xhci->eseg = usb_align(XHCI_ALIGMENT, sizeof(*xhci->eseg)); /* event segment */ if ( ! xhci->eseg ) { rc = -ENOMEM; goto err_alloc_segment; } +#endif + + xhci->eseg_addr = eseg_addr; + xhci->eseg_phy = eseg_phy; + + xhci->eseg = (struct xhci_er_seg *)eseg_addr; + memset(xhci->eseg, 0U, sizeof(*xhci->eseg)); xhci->eseg->base = CPU_TO_LE64 ( ( (uintptr_t)xhci->evts ) ); xhci->eseg->count = XHCI_RING_ITEMS; /* items of event ring TRB */ /* Program event ring registers */ - writel ( 1, xhci->run + XHCI_RUN_ERSTSZ ( 0 ) ); /* bit[15:0] event ring segment table size */ +// writel ( 1, xhci->run + XHCI_RUN_ERSTSZ ( 0 ) ); /* bit[15:0] event ring segment table size */ + + writel ( 1, xhci->run_addr + XHCI_RUN_ERSTSZ ( 0 ) ); /* bit[15:0] event ring segment table size */ + +#if 0 if ( ( rc = xhci_writeq ( xhci, (uintptr_t)( xhci->evts ), xhci->run + XHCI_RUN_ERDP ( 0 ) ) ) != 0 ) /* bit[63:4] event ring dequeue pointer */ goto err_writeq_erdp; +#endif + if ( ( rc = xhci_writeq ( xhci, (uintptr_t)( xhci->evts_phy ), + xhci->run_addr + XHCI_RUN_ERDP ( 0 ) ) ) != 0 ) /* bit[63:4] event ring dequeue pointer */ + goto err_writeq_erdp; + +#if 0 if ( ( rc = xhci_writeq ( xhci, (uintptr_t)( xhci->eseg ), xhci->run + XHCI_RUN_ERSTBA ( 0 ) ) ) != 0 ) /* bit[63:6] event ring segment table base addr */ goto err_writeq_erstba; +#endif + + if ( ( rc = xhci_writeq ( xhci, (uintptr_t)( xhci->eseg_phy ), + xhci->run_addr + XHCI_RUN_ERSTBA ( 0 ) ) ) != 0 ) /* bit[63:6] event ring segment table base addr */ + goto err_writeq_erstba; xhci->evts->cs = 1; /* cycle state = 1 */ USB_LOG_DBG("XHCI %s event ring [%08lx,%08lx) table [%08lx,%08lx)\n", @@ -980,13 +1028,13 @@ static int xhci_event_alloc ( struct xhci_host *xhci ) { sizeof ( xhci->eseg[0] ) ) ); return 0; - xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERSTBA ( 0 ) ); + xhci_writeq ( xhci, 0, xhci->run_addr + XHCI_RUN_ERSTBA ( 0 ) ); err_writeq_erstba: - xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERDP ( 0 ) ); + xhci_writeq ( xhci, 0, xhci->run_addr + XHCI_RUN_ERDP ( 0 ) ); err_writeq_erdp: - usb_free ( xhci->eseg ); +// usb_free ( xhci->eseg ); err_alloc_segment: - usb_free ( xhci->evts ); +// usb_free ( xhci->evts ); err_alloc_trb: return rc; } diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h index 93b36c792..4105f7b83 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h @@ -900,7 +900,19 @@ struct xhci_host { uintptr_t cmds_phy; /** Event ring */ struct xhci_ring *evts; + /* + * evts_addr holds the virtual address of the event ring, meanwhile cvts_phy keeps the value that should be writen to Event Ring + * Dequeue Pointer Register (XHCI_RUN_ERDP). + */ + uintptr_t evts_addr; + uintptr_t evts_phy; struct xhci_er_seg *eseg; + /* + * eseg_addr holds the virtual address of the event segment, meanwhile cseg_phy keeps the value that should be writen to Event Ring + * Segment Table Size Register (XHCI_RUN_ERSTBA). + */ + uintptr_t eseg_addr; + uintptr_t eseg_phy; struct xhci_endpoint *cur_cmd_pipe; }; From f322fce7787e09f7d13e8ea998d71d7bff8003bd Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 29 Jul 2024 04:49:30 -0700 Subject: [PATCH 095/198] Implanting xhci_run and some free functions --- .../drivers/usb/components/port/xhci/xhci.c | 43 ++++++++++++------- 1 file changed, 27 insertions(+), 16 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index f4aa69518..54420b966 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -1050,21 +1050,28 @@ static void xhci_run ( struct xhci_host *xhci ) { uint32_t runtime; /* Configure number of device slots */ - config = readl ( xhci->op + XHCI_OP_CONFIG ); +// config = readl ( xhci->op + XHCI_OP_CONFIG ); + config = readl ( xhci->op_addr + XHCI_OP_CONFIG ); config &= ~XHCI_CONFIG_MAX_SLOTS_EN_MASK; config |= XHCI_CONFIG_MAX_SLOTS_EN ( xhci->slots ); - writel ( config, xhci->op + XHCI_OP_CONFIG ); +// writel ( config, xhci->op + XHCI_OP_CONFIG ); + writel ( config, xhci->op_addr + XHCI_OP_CONFIG ); /* Enable port interrupt */ - writel ( 500U, xhci->run + XHCI_RUN_IR_IMOD ( 0 ) ); - runtime = readl(xhci->run + XHCI_RUN_IR_IMAN ( 0 )); +// writel ( 500U, xhci->run + XHCI_RUN_IR_IMOD ( 0 ) ); + writel ( 500U, xhci->run_addr + XHCI_RUN_IR_IMOD ( 0 ) ); +// runtime = readl(xhci->run + XHCI_RUN_IR_IMAN ( 0 )); + runtime = readl(xhci->run_addr + XHCI_RUN_IR_IMAN ( 0 )); runtime |= XHCI_RUN_IR_IMAN_IE; - writel (runtime, xhci->run + XHCI_RUN_IR_IMAN ( 0 )); +// writel (runtime, xhci->run + XHCI_RUN_IR_IMAN ( 0 )); + writel (runtime, xhci->run_addr + XHCI_RUN_IR_IMAN ( 0 )); /* Set run/stop bit and enable interrupt */ - usbcmd = readl ( xhci->op + XHCI_OP_USBCMD ); +// usbcmd = readl ( xhci->op + XHCI_OP_USBCMD ); + usbcmd = readl ( xhci->op_addr + XHCI_OP_USBCMD ); usbcmd |= XHCI_USBCMD_RUN | XHCI_USBCMD_INTE; - writel ( usbcmd, xhci->op + XHCI_OP_USBCMD ); +// writel ( usbcmd, xhci->op + XHCI_OP_USBCMD ); + writel ( usbcmd, xhci->op_addr + XHCI_OP_USBCMD ); USB_LOG_DBG("XHCI %s start running\n", xhci->name ); } @@ -1077,15 +1084,18 @@ static void xhci_run ( struct xhci_host *xhci ) { static void xhci_event_free ( struct xhci_host *xhci ) { /* Clear event ring registers */ - writel ( 0, xhci->run + XHCI_RUN_ERSTSZ ( 0 ) ); - xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERSTBA ( 0 ) ); - xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERDP ( 0 ) ); +// writel ( 0, xhci->run + XHCI_RUN_ERSTSZ ( 0 ) ); + writel ( 0, xhci->run_addr + XHCI_RUN_ERSTSZ ( 0 ) ); +// xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERSTBA ( 0 ) ); + xhci_writeq ( xhci, 0, xhci->run_addr + XHCI_RUN_ERSTBA ( 0 ) ); +// xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERDP ( 0 ) ); + xhci_writeq ( xhci, 0, xhci->run_addr + XHCI_RUN_ERDP ( 0 ) ); /* Free event ring segment table */ - usb_free ( xhci->eseg ); +// usb_free ( xhci->eseg ); /* Free event ring */ - usb_free ( xhci->evts ); +// usb_free ( xhci->evts ); } /** @@ -1099,10 +1109,11 @@ static void xhci_command_free ( struct xhci_host *xhci ) { USB_ASSERT ( ( readl ( xhci->op + XHCI_OP_CRCR ) & XHCI_CRCR_CRR ) == 0 ); /* Clear command ring control register */ - xhci_writeq ( xhci, 0, xhci->op + XHCI_OP_CRCR ); +// xhci_writeq ( xhci, 0, xhci->op + XHCI_OP_CRCR ); + xhci_writeq ( xhci, 0, xhci->op_addr + XHCI_OP_CRCR ); /* Free TRB ring */ - usb_free ( xhci->cmds ); +// usb_free ( xhci->cmds ); } /** @@ -1125,11 +1136,11 @@ static void xhci_scratchpad_free ( struct xhci_host *xhci ) { /* Free scratchpad array */ array_len = ( scratch->count * sizeof ( scratch->array[0] ) ); - usb_free ( scratch->array ); +// usb_free ( scratch->array ); /* Free scratchpad buffers */ buffer_len = ( scratch->count * xhci->pagesize ); - usb_free ( scratch->buffer ); +// usb_free ( scratch->buffer ); } /** From 1bc171a1312e4a4b8cf7254e28a1617ebc60390c Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 29 Jul 2024 04:51:48 -0700 Subject: [PATCH 096/198] Implanting xhci_run and some free functions --- .../services/drivers/usb/components/port/xhci/xhci.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 54420b966..5bca1de1a 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -1157,11 +1157,12 @@ static void xhci_dcbaa_free ( struct xhci_host *xhci ) { USB_ASSERT ( xhci->dcbaa.context[i] == 0 ); /* Clear DCBAA pointer */ - xhci_writeq ( xhci, 0, xhci->op + XHCI_OP_DCBAAP ); +// xhci_writeq ( xhci, 0, xhci->op + XHCI_OP_DCBAAP ); + xhci_writeq ( xhci, 0, xhci->op_addr + XHCI_OP_DCBAAP ); /* Free DCBAA */ len = ( ( xhci->slots + 1 ) * sizeof ( xhci->dcbaa.context[0] ) ); - usb_free ( xhci->dcbaa.context ); +// usb_free ( xhci->dcbaa.context ); } /** @@ -1230,9 +1231,9 @@ void xhci_close ( struct xhci_host *xhci ) { USB_ASSERT ( xhci->slot[i] == NULL ); xhci_stop ( xhci ); - usb_free (xhci->evts); - usb_free (xhci->eseg); - usb_free (xhci->cmds); +// usb_free (xhci->evts); +// usb_free (xhci->eseg); +// usb_free (xhci->cmds); xhci_scratchpad_free ( xhci ); xhci_dcbaa_free ( xhci ); usb_free ( xhci->slot ); From 19269781b40e28df1f79ea13991c0a125c46af38 Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 1 Aug 2024 00:27:38 -0700 Subject: [PATCH 097/198] Add USB memory pool function --- .../drivers/usb/components/mem/usb_mem.c | 75 ++++++++++++++++++- .../drivers/usb/components/mem/usb_mem.h | 32 +++++--- 2 files changed, 93 insertions(+), 14 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c index f4a220235..d6db75b04 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c @@ -11,6 +11,7 @@ History: Author: AIIT XUOS Lab Modification: re-develop usb_hc_malloc, usb_hc_malloc_align and usb_hc_free functions *************************************************/ +struct usb_mem_pool usb_mem_pool; void *usb_hc_malloc(size_t size){ @@ -54,13 +55,81 @@ void usb_hc_free(void* ptr){ free(ptr); } +int usb_mem_pool_init(){ + int rc, count; + uintptr_t phy_addr, vir_addr; -usb_dir_page_t usb_alloc_dir_page(int len, int flag, int headroom_len){ - return NULL; + memset(&usb_mem_pool, 0, sizeof(usb_mem_pool)); + + count = 0; + while(count < MEM_POOL_SIZE){ + rc = naive_mmap(&vir_addr, &phy_addr, 4096, true); + + if(rc != 0) + goto mmap_error; + + usb_mem_pool.pages[count].vir_addr = vir_addr; + usb_mem_pool.pages[count].phy_addr = phy_addr; + + count++; + } + + return 0; + +mmap_error: + return -1; + +} + +usb_mem_page_t usb_alloc_mem_page(){ + usb_mem_page_t selected_page; + int header, tail; + + header = usb_mem_pool.header; + tail = usb_mem_pool.tail; + + +/* + * Check whether the memory pool is full or not. + */ + + if((tail + 1) % MEM_POOL_SIZE == header) + return NULL; + + selected_page = &usb_mem_pool.pages[tail]; + tail++; + + if(tail == MEM_POOL_SIZE) + tail = 0; + + usb_mem_pool.tail = tail; + + return selected_page; } -void usb_free_dir_page(usb_dir_page_t page){ +void usb_free_mem_page(usb_mem_page_t page){ + usb_mem_page_t selected_page; + int header, tail; + header = usb_mem_pool.header; + tail = usb_mem_pool.tail; + +/* + * Check whether the memory pool is full or not. + */ + if((header + 1) % MEM_POOL_SIZE == tail) + return; + + selected_page = &usb_mem_pool.pages[header]; + selected_page->vir_addr = page->vir_addr; + selected_page->phy_addr = page->phy_addr; + + header++; + + if(header == MEM_POOL_SIZE) + header = 0; + + usb_mem_pool.header = header; } \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h index 5be052e2d..a6d593160 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h @@ -26,9 +26,13 @@ Modification: Use usb_malloc, usb_free and usb_align functions #include #include #include "usb_config.h" +#include "usyscall.h" + #define USB_MEM_ALIGNX __attribute__((aligned(CONFIG_USB_ALIGN_SIZE))) +#define MEM_POOL_SIZE 128 + void *usb_hc_malloc(size_t size); void usb_hc_free(); void *usb_hc_malloc_align(size_t align, size_t size); @@ -37,19 +41,25 @@ void *usb_hc_malloc_align(size_t align, size_t size); #define usb_free(ptr) usb_hc_free(ptr) #define usb_align(align, size) usb_hc_malloc_align(align, size) -struct usb_dir_page{ - uint64_t vir_addr; - uint64_t phy_addr; - uint32_t size; - uint32_t len; - uint32_t flag; - uint32_t headroom_len; -}__PACKED; +struct usb_mem_page{ + uintptr_t vir_addr; + uintptr_t phy_addr; -typedef struct usb_dir_page *usb_dir_page_t; +}; -usb_dir_page_t usb_alloc_dir_page(int len, int flag, int headroom_len); -void usb_free_dir_page(usb_dir_page_t page); +struct usb_mem_pool{ + int header; + int tail; + struct usb_mem_page pages[MEM_POOL_SIZE]; +}; + +typedef struct usb_mem_page *usb_mem_page_t; +typedef struct usb_mem_pool *usb_mem_pool_t; + +int usb_mem_pool_init(); +void usb_mem_pool_destory(); +usb_mem_page_t usb_alloc_mem_page(); +void usb_free_mem_page(usb_mem_page_t page); From 6ab2083403330f7e8439e40f50d052622c7218da Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 1 Aug 2024 01:40:18 -0700 Subject: [PATCH 098/198] Add USB memory pool functions --- .../services/drivers/usb/components/mem/usb_mem.c | 8 +++++--- .../services/drivers/usb/components/mem/usb_mem.h | 2 +- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c index d6db75b04..134e29c35 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c @@ -81,7 +81,7 @@ mmap_error: } -usb_mem_page_t usb_alloc_mem_page(){ +int usb_alloc_mem_page(usb_mem_page_t page){ usb_mem_page_t selected_page; int header, tail; @@ -94,17 +94,19 @@ usb_mem_page_t usb_alloc_mem_page(){ */ if((tail + 1) % MEM_POOL_SIZE == header) - return NULL; + return -1; selected_page = &usb_mem_pool.pages[tail]; tail++; + memcpy(page, selected_page, sizeof(struct usb_mem_page)); + if(tail == MEM_POOL_SIZE) tail = 0; usb_mem_pool.tail = tail; - return selected_page; + return 0; } diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h index a6d593160..821234025 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h @@ -58,7 +58,7 @@ typedef struct usb_mem_pool *usb_mem_pool_t; int usb_mem_pool_init(); void usb_mem_pool_destory(); -usb_mem_page_t usb_alloc_mem_page(); +int usb_alloc_mem_page(usb_mem_page_t page); void usb_free_mem_page(usb_mem_page_t page); From 3928cd46b7fd8b92629f4c502a7392c3adc5bbb3 Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 1 Aug 2024 20:09:00 -0700 Subject: [PATCH 099/198] Replanting xhci_event_process function --- .../drivers/usb/components/port/xhci/xhci.c | 23 ++++++++++++------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 5bca1de1a..8f169c1d4 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -2794,11 +2794,13 @@ static void xhci_host_controller ( struct xhci_host *xhci, void xhci_event_process(struct xhci_host *xhci) { struct xhci_ring *evts = xhci->evts; unsigned int evt_type; - uint32_t nidx; - uint32_t cs; - union xhci_trb *trb; - uint32_t control; - uint64_t erdp; + uint32_t nidx; + uint32_t cs; + union xhci_trb *trb; + uint32_t control; + uint64_t erdp; + uintptr_t evts_phy = xhci->evts_phy; + /* check and ack event */ for (;;) { @@ -2854,9 +2856,14 @@ void xhci_event_process(struct xhci_host *xhci) { evts->nidx = nidx; /* Update dequeue pointer if applicable */ - erdp = (uint64_t)(unsigned long)(evts->ring + nidx); - xhci_writeq ( xhci, (uintptr_t)( erdp ) | XHCI_RUN_ERDP_EHB, - xhci->run + XHCI_RUN_ERDP ( 0 ) ); +// erdp = (uint64_t)(unsigned long)(evts->ring + nidx); + erdp = (uint64_t)(unsigned long)(evts_phy + nidx * sizeof(union xhci_trb)); +#if 0 + xhci_writeq ( xhci, (uintptr_t)( erdp ) | XHCI_RUN_ERDP_EHB, + xhci->run + XHCI_RUN_ERDP ( 0 ) ); +#endif + xhci_writeq ( xhci, (uintptr_t)( erdp ) | XHCI_RUN_ERDP_EHB, + xhci->run_addr + XHCI_RUN_ERDP ( 0 ) ); } return; From bf9c5056ac1f4a0b7dd38d1576ba773c6b74979d Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 5 Aug 2024 00:51:52 -0700 Subject: [PATCH 100/198] Adding usb memory pool functions --- .../drivers/usb/components/mem/usb_mem.c | 42 +++++++++++++++++++ .../drivers/usb/components/mem/usb_mem.h | 3 +- 2 files changed, 44 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c index 134e29c35..14da9ec0e 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c @@ -134,4 +134,46 @@ void usb_free_mem_page(usb_mem_page_t page){ header = 0; usb_mem_pool.header = header; +} + + +int usb_used_page_num_mem_pool(){ + int header, tail, used_num; + header = usb_mem_pool.header; + tail = usb_mem_pool.tail; + + used_num = tail - header; + + if(used_num < 0) + used_num += MEM_POOL_SIZE; + + return used_num; +} + + +uintptr_t usb_mem_page_phy2vir(uintptr_t phy_addr){ + int header, used_num, cnt; + uintptr_t vir_addr = 0; + + header = usb_mem_pool.header; + used_num = usb_used_page_num_mem_pool(); + + cnt = 0; + while(cnt < used_num){ + if(usb_mem_pool.pages[header].phy_addr == phy_addr){ + vir_addr = usb_mem_pool.pages[header].vir_addr; + break; + } + + + header++; + + if(header == MEM_POOL_SIZE - 1) + header = 0; + + + cnt++; + } + + return vir_addr; } \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h index 821234025..65b1d6fdd 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h @@ -60,7 +60,8 @@ int usb_mem_pool_init(); void usb_mem_pool_destory(); int usb_alloc_mem_page(usb_mem_page_t page); void usb_free_mem_page(usb_mem_page_t page); - +int usb_used_page_num_mem_pool(); +uintptr_t usb_mem_page_phy2vir(uintptr_t phy_addr); #endif From acf338844af9000641d9872127de800c0c1239f3 Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 5 Aug 2024 01:16:19 -0700 Subject: [PATCH 101/198] Replanting xhci_transfer --- .../drivers/usb/components/port/xhci/xhci.c | 23 +++++++++++++++---- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 8f169c1d4..d07154f82 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -2669,11 +2669,24 @@ static void xhci_transfer ( struct xhci_host *xhci, struct xhci_trb_transfer *trb ) { struct xhci_slot *slot; struct xhci_endpoint *endpoint; - union xhci_trb *trans_trb = (void *)(uintptr_t)(trb->transfer); - struct xhci_ring *trans_ring = XHCI_RING(trans_trb); /* to align addr is ring base */ - union xhci_trb *pending = &trans_ring->evt; /* preserve event trb pending to handle */ - uint32_t eidx = trans_trb - trans_ring->ring + 1; /* calculate current evt trb index */ - int rc; + uintptr_t vir_addr; + union xhci_trb *trans_trb; + struct xhci_ring *trans_ring; + union xhci_trb *pending; + uint32_t eidx; + int rc; + + vir_addr = usb_mem_page_phy2vir(trb->transfer); + +#if 0 + if(!vir_addr) + return; +#endif + + trans_trb = (void *)(uintptr_t)(vir_addr); + trans_ring = XHCI_RING(trans_trb); /* to align addr is ring base */ + pending = &trans_ring->evt; /* preserve event trb pending to handle */ + eidx = trans_trb - trans_ring->ring + 1; /* calculate current evt trb index */ /* Identify slot */ if ( ( trb->slot > xhci->slots ) || From 48ff62be238d320e52ad0b84ed9ad2fea0dab0be Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 5 Aug 2024 01:38:11 -0700 Subject: [PATCH 102/198] Replanting xhci_complete --- .../drivers/usb/components/port/xhci/xhci.c | 21 +++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index d07154f82..889ddd83f 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -2757,12 +2757,21 @@ static void xhci_transfer ( struct xhci_host *xhci, */ static void xhci_complete ( struct xhci_host *xhci, struct xhci_trb_complete *trb ) { - int rc; - union xhci_trb *cmd_trb = (void *)(uintptr_t)(trb->command); - struct xhci_ring *cmd_ring = XHCI_RING(cmd_trb); /* to align addr is ring base */ - union xhci_trb *pending = &cmd_ring->evt; /* preserve event trb pending to handle */ - uint32_t eidx = cmd_trb - cmd_ring->ring + 1; /* calculate current evt trb index */ - struct xhci_endpoint *work_pipe = xhci->cur_cmd_pipe; + int rc; + union xhci_trb *cmd_trb; + struct xhci_ring *cmd_ring; + union xhci_trb *pending; + uint32_t eidx; + struct xhci_endpoint *work_pipe; + uintptr_t vir_addr; + + vir_addr = usb_mem_page_phy2vir(trb->command); + + cmd_trb = (void *)(uintptr_t)(vir_addr); + cmd_ring = XHCI_RING(cmd_trb); /* to align addr is ring base */ + pending = &cmd_ring->evt; /* preserve event trb pending to handle */ + eidx = cmd_trb - cmd_ring->ring + 1; /* calculate current evt trb index */ + work_pipe = xhci->cur_cmd_pipe; /* Ignore "command ring stopped" notifications */ if ( trb->code == XHCI_CMPLT_CMD_STOPPED ) { From ad027ba080b9bbf78a90c2beecf9f886cae2b30d Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 5 Aug 2024 01:47:35 -0700 Subject: [PATCH 103/198] Replanting xhci_complete --- .../drivers/usb/components/port/xhci/xhci.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 889ddd83f..6a92876be 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -2763,14 +2763,19 @@ static void xhci_complete ( struct xhci_host *xhci, union xhci_trb *pending; uint32_t eidx; struct xhci_endpoint *work_pipe; - uintptr_t vir_addr; + uintptr_t addr_offset; - vir_addr = usb_mem_page_phy2vir(trb->command); +// vir_addr = usb_mem_page_phy2vir(trb->command); + cmd_ring = xhci->cmds; + addr_offset = trb->command - xhci->cmds_phy; - cmd_trb = (void *)(uintptr_t)(vir_addr); - cmd_ring = XHCI_RING(cmd_trb); /* to align addr is ring base */ + + // cmd_trb = (void *)(uintptr_t)(vir_addr); + // cmd_ring = XHCI_RING(cmd_trb); /* to align addr is ring base */ pending = &cmd_ring->evt; /* preserve event trb pending to handle */ - eidx = cmd_trb - cmd_ring->ring + 1; /* calculate current evt trb index */ +// eidx = cmd_trb - cmd_ring->ring + 1; /* calculate current evt trb index */ + eidx = addr_offset / sizeof(union xhci_trb); /* calculate current evt trb index */ + work_pipe = xhci->cur_cmd_pipe; /* Ignore "command ring stopped" notifications */ From 2eba5a80717f65cea858e9259c8a827f13d7bb32 Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 5 Aug 2024 02:20:41 -0700 Subject: [PATCH 104/198] Replanting xhci_port_status --- .../XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 6a92876be..6f803b3a0 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -2650,7 +2650,8 @@ static void xhci_port_status ( struct xhci_host *xhci, USB_ASSERT ( ( trb->port > 0 ) && ( trb->port <= xhci->ports ) ); /* Record disconnections, changes flag will be cleared later */ - portsc = readl ( xhci->op + XHCI_OP_PORTSC ( trb->port ) ); +// portsc = readl ( xhci->op + XHCI_OP_PORTSC ( trb->port ) ); + portsc = readl ( xhci->op_addr + XHCI_OP_PORTSC ( trb->port ) ); xhci_dump_port_status(trb->port, portsc); if (portsc & XHCI_PORTSC_CSC) { From 77bed3c28f9ae4abd3e4e9dab4fa57e0bd26ba04 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Mon, 5 Aug 2024 20:47:51 +0800 Subject: [PATCH 105/198] Modify USB Device Initialization in xHCI code and Command TRB code to apply to XiZi AIOT. --- .../usb/components/port/xhci/usb_hc_xhci.c | 29 ++++++++--- .../drivers/usb/components/port/xhci/xhci.c | 50 ++++++++++++++++--- .../drivers/usb/components/port/xhci/xhci.h | 2 + 3 files changed, 66 insertions(+), 15 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index 88d74882e..57fea8451 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -38,6 +38,10 @@ Modification: rewrite xhci functions to dock with USB core layer, so that the US 2. Date: 2024-06-24 Author: AIIT XUOS Lab Modification: rewrite xhci function usbh_get_port_speed to dock with USB core layer. + +3. Date: 2024-08-05 +Author: AIIT XUOS Lab +Modification: Modify USB Device Initialization in xHCI code to apply to XiZi AIOT. *************************************************/ #include "usb_hc_xhci.h" #include "usbh_hub.h" @@ -686,7 +690,7 @@ int xhci_usbh_roothub_control(struct usbh_bus *usb, struct usb_setup_packet *set return -EPIPE; } - portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port ) ); + portsc = readl ( xhci->op_addr + XHCI_OP_PORTSC ( port ) ); switch (setup->wValue) { case HUB_PORT_FEATURE_ENABLE: @@ -712,7 +716,7 @@ int xhci_usbh_roothub_control(struct usbh_bus *usb, struct usb_setup_packet *set uint32_t pclear = portsc & XHCI_PORTSC_RW_MASK; /* clear port status */ - writel(pclear, xhci->op + XHCI_OP_PORTSC ( port )); + writel(pclear, xhci->op_addr + XHCI_OP_PORTSC ( port )); break; case HUB_REQUEST_SET_FEATURE: @@ -740,7 +744,7 @@ int xhci_usbh_roothub_control(struct usbh_bus *usb, struct usb_setup_packet *set return -EPIPE; } - portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port ) ); + portsc = readl ( xhci->op_addr + XHCI_OP_PORTSC ( port ) ); status = 0; if (portsc & XHCI_PORTSC_CSC) @@ -750,7 +754,7 @@ int xhci_usbh_roothub_control(struct usbh_bus *usb, struct usb_setup_packet *set /* always clear all the status change bits */ uint32_t temp = portsc & ( XHCI_PORTSC_PRESERVE | XHCI_PORTSC_CHANGE ); - writel ( temp, xhci->op + XHCI_OP_PORTSC ( port ) ); + writel ( temp, xhci->op_addr + XHCI_OP_PORTSC ( port ) ); } if (portsc & XHCI_PORTSC_PEC) @@ -816,12 +820,23 @@ int xhci_usbh_roothub_control(struct usbh_bus *usb, struct usb_setup_packet *set return 0; } -// TODO: uint8_t xhci_usbh_get_port_speed(struct usbh_hub *hub, const uint8_t port) { - return 0; -} + USB_ASSERT(hub); + struct usbh_bus *usb = hub->usb; + USB_ASSERT(usb && usb->priv); + struct xhci_host *xhci = usb->priv; + if (hub->is_roothub) { + return xhci_root_speed(xhci, port); + } else { + struct usbh_hubport *roothub_port = usbh_root_hub_port(&(hub->child[port])); + /* TODO, hanlde TT for low-speed device on high-speed hub, but it doesn't matter, since + we haven't well handle hub yet */ + USB_ASSERT(roothub_port); + return xhci_root_speed(xhci, roothub_port->port); + } +} int xhci_usbh_ep_pipe_reconfigure(struct usbh_bus *usb, usbh_pipe_t pipe, uint8_t dev_addr, uint8_t mtu, uint8_t speed){ struct xhci_endpoint *ppipe = (struct xhci_endpoint *)pipe; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 6f803b3a0..81d9c9cac 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -29,6 +29,10 @@ History: 1. Date: 2024-06-18 Author: AIIT XUOS Lab Modification: replant and redefine some xhci data structure, so that the cherryUSB can adapt to XiZi AIOT. + +2. Date: 2024-08-05 +Author: AIIT XUOS Lab +Modification: Modify Command TRB code to apply to XiZi AIOT. *************************************************/ #include "usbh_core.h" @@ -1265,7 +1269,7 @@ void xhci_remove ( struct xhci_host *xhci ) { * @ret rc Return status code */ int xhci_port_enable(struct xhci_host *xhci, uint32_t port) { - uint32_t portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port ) ); + uint32_t portsc = readl ( xhci->op_addr + XHCI_OP_PORTSC ( port ) ); /* double check if connected */ if (!(portsc & XHCI_PORTSC_CCS)) { @@ -1281,7 +1285,7 @@ int xhci_port_enable(struct xhci_host *xhci, uint32_t port) { case XHCI_PORTSC_PLS_POLLING: /* A USB2 port - perform device reset */ xhci_dump_port_status(port, portsc); - writel ((portsc | XHCI_PORTSC_PR), (xhci->op + XHCI_OP_PORTSC ( port ))); /* reset port */ + writel ((portsc | XHCI_PORTSC_PR), (xhci->op_addr + XHCI_OP_PORTSC ( port ))); /* reset port */ break; default: USB_LOG_ERR("PLS: %d \r\n", (portsc & XHCI_PORTSC_PLS_MASK)); @@ -1291,7 +1295,7 @@ int xhci_port_enable(struct xhci_host *xhci, uint32_t port) { /* Wait for device to complete reset and be enabled */ uint32_t end = 1000U, start = 0U; for (;;) { - portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port ) ); + portsc = readl ( xhci->op_addr + XHCI_OP_PORTSC ( port ) ); if (!(portsc & XHCI_PORTSC_CCS)) { /* USB 2.0 port would be disconnected after reset */ USB_LOG_INFO("USB 2.0 port disconnected during reset, need rescan \r\n"); @@ -1455,7 +1459,7 @@ static int xhci_port_psiv ( struct xhci_host *xhci, unsigned int port, return -ENOTSUP; /* Get protocol speed ID count */ - ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS ); + ports = readl ( xhci->cap_addr + supported + XHCI_SUPPORTED_PORTS ); psic = XHCI_SUPPORTED_PORTS_PSIC ( ports ); /* Use the default mappings if applicable */ @@ -1474,7 +1478,7 @@ static int xhci_port_psiv ( struct xhci_host *xhci, unsigned int port, /* Iterate over PSI dwords looking for a match */ for ( i = 0 ; i < psic ; i++ ) { - psi = readl ( xhci->cap + supported + XHCI_SUPPORTED_PSI ( i )); + psi = readl ( xhci->cap_addr + supported + XHCI_SUPPORTED_PSI ( i )); mantissa = XHCI_SUPPORTED_PSI_MANTISSA ( psi ); exponent = XHCI_SUPPORTED_PSI_EXPONENT ( psi ); if ( xhci_speed_to_psi(speed) == XCHI_PSI ( mantissa, exponent ) ) { @@ -1505,7 +1509,7 @@ uint32_t xhci_root_speed ( struct xhci_host *xhci, uint8_t port ) { unsigned int protocol = xhci_port_protocol(xhci, port); /* Read port status */ - portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port ) ); + portsc = readl ( xhci->op_addr + XHCI_OP_PORTSC ( port ) ); USB_LOG_DBG("XHCI %s-%d status is 0x%08x, protocol 0x%x\n", xhci->name, port, portsc, protocol ); ccs = ( portsc & XHCI_PORTSC_CCS ); @@ -1616,7 +1620,7 @@ int xhci_event_wait(struct xhci_host *xhci, static inline void xhci_doorbell ( struct xhci_host *xhci, uint32_t slotid, uint32_t value ) { DSB(); BARRIER(); - writel ( value, xhci->db + slotid * XHCI_REG_DB_SIZE ); /* bit[7:0] db target, is ep_id */ + writel ( value, xhci->db_addr + slotid * XHCI_REG_DB_SIZE ); /* bit[7:0] db target, is ep_id */ } /** @@ -1793,14 +1797,25 @@ static int xhci_context ( struct xhci_host *xhci, struct xhci_slot *slot, size_t len; void *input; int rc; + uintptr_t input_vir; + uintptr_t input_phy; /* Allocate an input context */ len = xhci_input_context_offset ( xhci, XHCI_CTX_END ); +#if 0 input = usb_align(xhci_align ( len ), len); if ( ! input ) { rc = -ENOMEM; goto err_alloc; } +#endif + rc = naive_mmap(&input_vir, &input_phy, len, false); + if(rc != 0){ + USB_LOG_ERR("XHCI %s could not allocate xhci context\n", xhci->name ); + rc = -ENOMEM; + goto err_alloc; + } + input = input_vir; memset ( input, 0, len ); /* Populate input context */ @@ -1809,7 +1824,10 @@ static int xhci_context ( struct xhci_host *xhci, struct xhci_slot *slot, /* Construct command */ memset ( context, 0, sizeof ( *context ) ); context->type = type; +#if 0 context->input = CPU_TO_LE64 ( ( (uintptr_t)input ) ); +#endif + context->input = CPU_TO_LE64 ( ( (uintptr_t)input_phy ) ); context->slot = slot->id; /* Issue command and wait for completion */ @@ -1983,7 +2001,7 @@ static int xhci_port_slot_type ( struct xhci_host *xhci, unsigned int port ) { return -ENOTSUP; /* Get slot type */ - slot = readl ( xhci->cap + supported + XHCI_SUPPORTED_SLOT ); + slot = readl ( xhci->cap_addr + supported + XHCI_SUPPORTED_SLOT ); type = XHCI_SUPPORTED_SLOT_TYPE ( slot ); return type; @@ -2006,6 +2024,8 @@ int xhci_device_open ( struct xhci_host *xhci, struct xhci_endpoint *ep, int *sl int rc; int id; size_t len; + uintptr_t context_vir; + uintptr_t context_phy; /* Determine applicable slot type */ type = xhci_port_slot_type ( xhci, hport->port ); @@ -2043,16 +2063,30 @@ int xhci_device_open ( struct xhci_host *xhci, struct xhci_endpoint *ep, int *sl /* Allocate a device context */ len = xhci_device_context_offset ( xhci, XHCI_CTX_END ); +#if 0 slot->context = usb_align(xhci_align ( len ), len); if ( ! slot->context ) { rc = -ENOMEM; goto err_alloc_context; } +#endif + rc = naive_mmap(&context_addr, &context_phy, len, false); + if(rc != 0){ + USB_LOG_ERR("XHCI %s could not allocate xhci device context\n", xhci->name ); + rc = -ENOMEM; + goto err_alloc; + } + slot->context_vir = context_vir; + slot->context_phy = context_phy; + slot->context = (struct xhci_slot_context *)context_vir; memset ( slot->context, 0, len ); /* Set device context base address */ USB_ASSERT ( xhci->dcbaa.context[id] == 0 ); +#if 0 xhci->dcbaa.context[id] = CPU_TO_LE64 ( ( (uintptr_t)slot->context ) ); +#endif + xhci->dcbaa.context[id] = CPU_TO_LE64 ( ( (uintptr_t)slot->context_phy ) ); USB_LOG_DBG("XHCI %s slot %d device context [%08lx,%08lx)\n", xhci->name, slot->id, ( slot->context ), diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h index 4105f7b83..400ceef0d 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h @@ -799,6 +799,8 @@ struct xhci_slot { unsigned int id; /** Slot context */ struct xhci_slot_context *context; + uintptr_t context_vir; + uintptr_t context_phy; /** Route string */ unsigned int route; From 3886ed4b1260af03b5725f99446ca469844a39d7 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Mon, 5 Aug 2024 20:54:24 +0800 Subject: [PATCH 106/198] fix a bug --- .../services/drivers/usb/components/port/xhci/xhci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 81d9c9cac..7001a3e4e 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -1815,7 +1815,7 @@ static int xhci_context ( struct xhci_host *xhci, struct xhci_slot *slot, rc = -ENOMEM; goto err_alloc; } - input = input_vir; + input = (void *)input_vir; memset ( input, 0, len ); /* Populate input context */ @@ -2070,7 +2070,7 @@ int xhci_device_open ( struct xhci_host *xhci, struct xhci_endpoint *ep, int *sl goto err_alloc_context; } #endif - rc = naive_mmap(&context_addr, &context_phy, len, false); + rc = naive_mmap(&context_vir, &context_phy, len, false); if(rc != 0){ USB_LOG_ERR("XHCI %s could not allocate xhci device context\n", xhci->name ); rc = -ENOMEM; From 7d6cc6d1d881ea821757dc3dbd43157b451c0cc6 Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 5 Aug 2024 19:24:52 -0700 Subject: [PATCH 107/198] modify variate name --- .../drivers/usb/components/mem/usb_mem.c | 34 +++++++++---------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c index 14da9ec0e..505bf6ba1 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c @@ -11,7 +11,7 @@ History: Author: AIIT XUOS Lab Modification: re-develop usb_hc_malloc, usb_hc_malloc_align and usb_hc_free functions *************************************************/ -struct usb_mem_pool usb_mem_pool; +struct usb_mem_pool usb_mem_data_pool; void *usb_hc_malloc(size_t size){ @@ -59,7 +59,7 @@ int usb_mem_pool_init(){ int rc, count; uintptr_t phy_addr, vir_addr; - memset(&usb_mem_pool, 0, sizeof(usb_mem_pool)); + memset(&usb_mem_data_pool, 0, sizeof(usb_mem_data_pool)); count = 0; while(count < MEM_POOL_SIZE){ @@ -68,8 +68,8 @@ int usb_mem_pool_init(){ if(rc != 0) goto mmap_error; - usb_mem_pool.pages[count].vir_addr = vir_addr; - usb_mem_pool.pages[count].phy_addr = phy_addr; + usb_mem_data_pool.pages[count].vir_addr = vir_addr; + usb_mem_data_pool.pages[count].phy_addr = phy_addr; count++; } @@ -85,8 +85,8 @@ int usb_alloc_mem_page(usb_mem_page_t page){ usb_mem_page_t selected_page; int header, tail; - header = usb_mem_pool.header; - tail = usb_mem_pool.tail; + header = usb_mem_data_pool.header; + tail = usb_mem_data_pool.tail; /* @@ -96,7 +96,7 @@ int usb_alloc_mem_page(usb_mem_page_t page){ if((tail + 1) % MEM_POOL_SIZE == header) return -1; - selected_page = &usb_mem_pool.pages[tail]; + selected_page = &usb_mem_data_pool.pages[tail]; tail++; memcpy(page, selected_page, sizeof(struct usb_mem_page)); @@ -104,7 +104,7 @@ int usb_alloc_mem_page(usb_mem_page_t page){ if(tail == MEM_POOL_SIZE) tail = 0; - usb_mem_pool.tail = tail; + usb_mem_data_pool.tail = tail; return 0; } @@ -115,8 +115,8 @@ void usb_free_mem_page(usb_mem_page_t page){ usb_mem_page_t selected_page; int header, tail; - header = usb_mem_pool.header; - tail = usb_mem_pool.tail; + header = usb_mem_data_pool.header; + tail = usb_mem_data_pool.tail; /* * Check whether the memory pool is full or not. @@ -124,7 +124,7 @@ void usb_free_mem_page(usb_mem_page_t page){ if((header + 1) % MEM_POOL_SIZE == tail) return; - selected_page = &usb_mem_pool.pages[header]; + selected_page = &usb_mem_data_pool.pages[header]; selected_page->vir_addr = page->vir_addr; selected_page->phy_addr = page->phy_addr; @@ -133,14 +133,14 @@ void usb_free_mem_page(usb_mem_page_t page){ if(header == MEM_POOL_SIZE) header = 0; - usb_mem_pool.header = header; + usb_mem_data_pool.header = header; } int usb_used_page_num_mem_pool(){ int header, tail, used_num; - header = usb_mem_pool.header; - tail = usb_mem_pool.tail; + header = usb_mem_data_pool.header; + tail = usb_mem_data_pool.tail; used_num = tail - header; @@ -155,13 +155,13 @@ uintptr_t usb_mem_page_phy2vir(uintptr_t phy_addr){ int header, used_num, cnt; uintptr_t vir_addr = 0; - header = usb_mem_pool.header; + header = usb_mem_data_pool.header; used_num = usb_used_page_num_mem_pool(); cnt = 0; while(cnt < used_num){ - if(usb_mem_pool.pages[header].phy_addr == phy_addr){ - vir_addr = usb_mem_pool.pages[header].vir_addr; + if(usb_mem_data_pool.pages[header].phy_addr == phy_addr){ + vir_addr = usb_mem_data_pool.pages[header].vir_addr; break; } From 951c3bf203d010385ed086fdfff62756ed19487b Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 5 Aug 2024 19:42:04 -0700 Subject: [PATCH 108/198] modify function name --- .../services/drivers/usb/components/mem/usb_mem.c | 8 +++++++- .../services/drivers/usb/components/mem/usb_mem.h | 4 ++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c index 505bf6ba1..57b0ba0ca 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c @@ -55,7 +55,7 @@ void usb_hc_free(void* ptr){ free(ptr); } -int usb_mem_pool_init(){ +int usb_mem_data_pool_init(){ int rc, count; uintptr_t phy_addr, vir_addr; @@ -81,6 +81,12 @@ mmap_error: } + +void usb_mem_data_pool_destory(){ + +} + + int usb_alloc_mem_page(usb_mem_page_t page){ usb_mem_page_t selected_page; int header, tail; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h index 65b1d6fdd..4eaee15fd 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h @@ -56,8 +56,8 @@ struct usb_mem_pool{ typedef struct usb_mem_page *usb_mem_page_t; typedef struct usb_mem_pool *usb_mem_pool_t; -int usb_mem_pool_init(); -void usb_mem_pool_destory(); +int usb_mem_data_pool_init(); +void usb_mem_data_pool_destory(); int usb_alloc_mem_page(usb_mem_page_t page); void usb_free_mem_page(usb_mem_page_t page); int usb_used_page_num_mem_pool(); From c689c550d7e6828dffcc86e83998a66654876a4a Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 5 Aug 2024 19:51:38 -0700 Subject: [PATCH 109/198] modify function name --- .../services/drivers/usb/components/mem/usb_mem.c | 8 ++++---- .../services/drivers/usb/components/mem/usb_mem.h | 6 +++--- .../services/drivers/usb/components/port/xhci/xhci.c | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c index 57b0ba0ca..41fb72485 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c @@ -83,11 +83,11 @@ mmap_error: void usb_mem_data_pool_destory(){ - + } -int usb_alloc_mem_page(usb_mem_page_t page){ +int usb_alloc_mem_data_page(usb_mem_page_t page){ usb_mem_page_t selected_page; int header, tail; @@ -117,7 +117,7 @@ int usb_alloc_mem_page(usb_mem_page_t page){ -void usb_free_mem_page(usb_mem_page_t page){ +void usb_free_mem_data_page(usb_mem_page_t page){ usb_mem_page_t selected_page; int header, tail; @@ -157,7 +157,7 @@ int usb_used_page_num_mem_pool(){ } -uintptr_t usb_mem_page_phy2vir(uintptr_t phy_addr){ +uintptr_t usb_mem_data_page_phy2vir(uintptr_t phy_addr){ int header, used_num, cnt; uintptr_t vir_addr = 0; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h index 4eaee15fd..312cf2dcc 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h @@ -58,10 +58,10 @@ typedef struct usb_mem_pool *usb_mem_pool_t; int usb_mem_data_pool_init(); void usb_mem_data_pool_destory(); -int usb_alloc_mem_page(usb_mem_page_t page); -void usb_free_mem_page(usb_mem_page_t page); +int usb_alloc_mem_data_page(usb_mem_page_t page); +void usb_free_mem_data_page(usb_mem_page_t page); int usb_used_page_num_mem_pool(); -uintptr_t usb_mem_page_phy2vir(uintptr_t phy_addr); +uintptr_t usb_mem_data_page_phy2vir(uintptr_t phy_addr); #endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 7001a3e4e..408275d9a 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -2711,7 +2711,7 @@ static void xhci_transfer ( struct xhci_host *xhci, uint32_t eidx; int rc; - vir_addr = usb_mem_page_phy2vir(trb->transfer); + vir_addr = usb_mem_data_page_phy2vir(trb->transfer); #if 0 if(!vir_addr) From b383f88d7ddd2f3c75b8aeb75d1f9db9f5c08836 Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 5 Aug 2024 20:20:39 -0700 Subject: [PATCH 110/198] modify function name --- .../services/drivers/usb/components/mem/usb_mem.c | 8 ++++---- .../services/drivers/usb/components/mem/usb_mem.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c index 41fb72485..8ff4ac44d 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c @@ -143,10 +143,10 @@ void usb_free_mem_data_page(usb_mem_page_t page){ } -int usb_used_page_num_mem_pool(){ +int usb_used_page_num_mem_pool(usb_mem_pool_t mem_pool){ int header, tail, used_num; - header = usb_mem_data_pool.header; - tail = usb_mem_data_pool.tail; + header = mem_pool->header; + tail = mem_pool->tail; used_num = tail - header; @@ -162,7 +162,7 @@ uintptr_t usb_mem_data_page_phy2vir(uintptr_t phy_addr){ uintptr_t vir_addr = 0; header = usb_mem_data_pool.header; - used_num = usb_used_page_num_mem_pool(); + used_num = usb_used_page_num_mem_pool(&usb_mem_data_pool); cnt = 0; while(cnt < used_num){ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h index 312cf2dcc..238b8f1ec 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h @@ -60,7 +60,7 @@ int usb_mem_data_pool_init(); void usb_mem_data_pool_destory(); int usb_alloc_mem_data_page(usb_mem_page_t page); void usb_free_mem_data_page(usb_mem_page_t page); -int usb_used_page_num_mem_pool(); +int usb_used_page_num_mem_pool(usb_mem_pool_t mem_pool); uintptr_t usb_mem_data_page_phy2vir(uintptr_t phy_addr); From 5e829d5da058462782b59d7ecbc7c760407b3dc4 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 6 Aug 2024 14:44:05 +0800 Subject: [PATCH 111/198] Modify Transfer TRB code in xHCI to apply to XiZi AIOT. --- .../usb/components/port/xhci/usb_hc_xhci.c | 77 ++++++++++++++++++- .../drivers/usb/components/port/xhci/xhci.c | 36 +++++---- .../drivers/usb/components/port/xhci/xhci.h | 4 + 3 files changed, 102 insertions(+), 15 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index 57fea8451..f3f081016 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -859,6 +859,9 @@ int xhci_usbh_pipe_alloc(usbh_pipe_t *pipe, const struct usbh_endpoint_cfg *ep_c struct usbh_hubport *hport = ep_cfg->hport; struct xhci_endpoint *ppipe = usb_align(XHCI_RING_SIZE, sizeof(struct xhci_endpoint)); struct xhci_slot *slot; + uintptr_t ring_vir; + uintptr_t ring_phy; + size_t len; if (NULL == ppipe) { return -ENOMEM; @@ -877,6 +880,19 @@ int xhci_usbh_pipe_alloc(usbh_pipe_t *pipe, const struct usbh_endpoint_cfg *ep_c ppipe->ep_type = ep_cfg->ep_type; ppipe->burst = 0U; + /* Allocate xHCI ring */ + len = sizeof(*ppipe->ep_reqs); + rc = naive_mmap(&ring_vir, &ring_phy, len, false); + if(rc != 0){ + USB_LOG_ERR("XHCI %s could not allocate xhci device context\n", xhci->name ); + rc = -ENOMEM; + goto failed; + } + ppipe->ep_reqs_vir = ring_vir; + ppipe->ep_reqs_phy = ring_phy; + ppipe->ep_reqs = (struct xhci_ring *)ring_vir; + memset ( ppipe->ep_reqs, 0, len ); + if (ppipe->address == 0) { /* if try to allocate ctrl ep, open device first */ USB_LOG_DBG("allocate device for port-%d \r\n", hport->port); rc = xhci_device_open(xhci, ppipe, &slot_id); @@ -943,7 +959,66 @@ int xhci_usbh_pipe_free(usbh_pipe_t pipe){ int xhci_usbh_submit_urb(struct usbh_urb *urb){ - return 0; + int ret = 0; + if (!urb || !urb->pipe) { + return -EINVAL; + } + + struct xhci_endpoint *ppipe = (struct xhci_endpoint *)urb->pipe; + struct xhci_host *xhci = ppipe->xhci; + struct usb_setup_packet *setup = urb->setup; + size_t flags = usb_osal_enter_critical_section(); + + urb->errorcode = -EBUSY; + urb->actual_length = 0U; + + ppipe->urb = urb; + ppipe->timeout = urb->timeout; + if (ppipe->timeout > 0) { + ppipe->waiter = true; + } else { + ppipe->waiter = false; + } + + usb_osal_leave_critical_section(flags); + switch (ppipe->ep_type) { + case USB_ENDPOINT_TYPE_CONTROL: + USB_ASSERT(setup); + if (setup->bRequest == USB_REQUEST_SET_ADDRESS) { + /* Set address command sent during xhci_alloc_pipe. */ + goto skip_req; + } + + USB_LOG_DBG("%s request-%d.\n", __func__, setup->bRequest); + xhci_endpoint_message(ppipe, setup, urb->transfer_buffer, urb->transfer_buffer_length); + break; + case USB_ENDPOINT_TYPE_INTERRUPT: + case USB_ENDPOINT_TYPE_BULK: + xhci_endpoint_stream(ppipe, urb->transfer_buffer, urb->transfer_buffer_length); + break; + default: + USB_ASSERT(0U); + break; + } + + /* wait all ring handled by xHc */ +// int cc = xhci_event_wait(xhci, ppipe, &ppipe->reqs); + int cc = xhci_event_wait(xhci, ppipe, ppipe->ep_reqs); + if ((cc != XHCI_CMPLT_SUCCESS) && + !((cc == XHCI_CMPLT_TIMEOUT) && (ppipe->ep_type == USB_ENDPOINT_TYPE_INTERRUPT))) + { + /* ignore transfer timeout for interrupt type */ + USB_LOG_ERR("%s: xfer failed (cc %d).\n", __func__, cc); + ret = -1; + urb->errorcode = cc; + goto errout_timeout; + } + +skip_req: +errout_timeout: + /* Timeout will run here */ + usbh_kill_urb(urb); + return ret; } diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 408275d9a..fae28bd33 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -32,7 +32,7 @@ Modification: replant and redefine some xhci data structure, so that the cherryU 2. Date: 2024-08-05 Author: AIIT XUOS Lab -Modification: Modify Command TRB code to apply to XiZi AIOT. +Modification: Modify Command TRB and Transfer TRB code to apply to XiZi AIOT. *************************************************/ #include "usbh_core.h" @@ -1884,7 +1884,8 @@ static void xhci_address_device_input ( struct xhci_host *xhci, bit[63:4] tr dequeue pointer bit[0] dequeue cycle state */ - ep_ctx->dequeue = CPU_TO_LE64 ( (uint64_t)( (uintptr_t)&endpoint->reqs.ring[0] ) | XHCI_EP_DCS ); +// ep_ctx->dequeue = CPU_TO_LE64 ( (uint64_t)( (uintptr_t)&endpoint->reqs.ring[0] ) | XHCI_EP_DCS ); + ep_ctx->dequeue = CPU_TO_LE64 ( (uint64_t)( (uintptr_t)endpoint->ep_reqs_phy ) | XHCI_EP_DCS ); ep_ctx->trb_len = CPU_TO_LE16 ( XHCI_EP0_TRB_LEN ); /* bit[15:0] average trb length */ } @@ -2229,8 +2230,9 @@ static void xhci_configure_endpoint_input ( struct xhci_host *xhci, ep_ctx->type = endpoint->ctx_type; ep_ctx->burst = endpoint->burst; ep_ctx->mtu = CPU_TO_LE16 ( endpoint->mtu ); /* bit[31:16] max packet size */ - ep_ctx->dequeue = CPU_TO_LE64 ( (uint64_t)( (uintptr_t)&(endpoint->reqs.ring[0]) ) | XHCI_EP_DCS ); - +// ep_ctx->dequeue = CPU_TO_LE64 ( (uint64_t)( (uintptr_t)&(endpoint->reqs.ring[0]) ) | XHCI_EP_DCS ); + ep_ctx->dequeue = CPU_TO_LE64 ( (uint64_t)( (uintptr_t)endpoint->ep_reqs_phy ) | XHCI_EP_DCS ); + /* TODO: endpoint attached on hub may need different setting here */ if (endpoint->ep_type == USB_ENDPOINT_TYPE_BULK) { ep_ctx->trb_len = CPU_TO_LE16 ( 256U ); /* bit[15:0] average trb length */ @@ -2359,15 +2361,16 @@ int xhci_ctrl_endpoint_open ( struct xhci_host *xhci, struct xhci_slot *slot, st ep->ctx_type = XHCI_EP_TYPE_CONTROL; ep->context = ( ( ( void * ) slot->context ) + xhci_device_context_offset ( xhci, ctx ) ); - ep->reqs.cs = 1; /* cycle state = 1 */ +// ep->reqs.cs = 1; /* cycle state = 1 */ + ep->ep_reqs->cs = 1; /* cycle state = 1 */ USB_LOG_DBG("XHCI %s slot %d endpoint 0x%x ep type %d xhci ep type 0x%x\n", xhci->name, slot->id, ep->address, ep->ep_type, (ep->ctx_type >> 3) ); USB_LOG_DBG("XHCI %s slot %d ctx %d ring [%08lx,%08lx)\n", - xhci->name, slot->id, ctx, ( ep->reqs.ring ), - ( ( ep->reqs.ring ) + sizeof(ep->reqs.ring) ) ); + xhci->name, slot->id, ctx, ( ep->ep_reqs->ring ), + ( ( ep->ep_reqs->ring ) + sizeof(ep->ep_reqs->ring) ) ); return 0; } @@ -2427,7 +2430,8 @@ int xhci_work_endpoint_open ( struct xhci_host *xhci, struct xhci_slot *slot, st ep->ctx_type = ctx_type; ep->context = ( ( ( void * ) slot->context ) + xhci_device_context_offset ( xhci, ctx ) ); - ep->reqs.cs = 1; /* cycle state = 1 */ +// ep->reqs.cs = 1; /* cycle state = 1 */ + ep->ep_reqs->cs = 1; /* cycle state = 1 */ USB_LOG_DBG("XHCI %s slot %d endpoint 0x%x ep type %d xhci ep type 0x%x\n", xhci->name, slot->id, ep->address, ep->ep_type, @@ -2439,8 +2443,8 @@ int xhci_work_endpoint_open ( struct xhci_host *xhci, struct xhci_slot *slot, st } USB_LOG_DBG("XHCI %s slot %d ctx %d ring [%08lx,%08lx)\n", - xhci->name, slot->id, ctx, ( ep->reqs.ring ), - ( ( ep->reqs.ring ) + sizeof(ep->reqs.ring) ) ); + xhci->name, slot->id, ctx, ( ep->ep_reqs->ring ), + ( ( ep->ep_reqs->ring ) + sizeof(ep->ep_reqs->ring) ) ); return 0; err_configure_endpoint: @@ -2504,7 +2508,8 @@ void xhci_endpoint_message ( struct xhci_endpoint *ep, setup->direction = ( input ? XHCI_SETUP_IN : XHCI_SETUP_OUT ); } - xhci_trb_queue(&(ep->reqs), &trb); +// xhci_trb_queue(&(ep->reqs), &trb); + xhci_trb_queue(ep->ep_reqs, &trb); /* Construct data stage TRB, if applicable */ if (datalen > 0) { @@ -2516,7 +2521,8 @@ void xhci_endpoint_message ( struct xhci_endpoint *ep, data->type = XHCI_TRB_DATA; /* bit[15:10] trb type */ data->direction = ( input ? XHCI_DATA_IN : XHCI_DATA_OUT ); /* bit[16] Direction, 0 = OUT, 1 = IN */ - xhci_trb_queue(&(ep->reqs), &trb); +// xhci_trb_queue(&(ep->reqs), &trb); + xhci_trb_queue(ep->ep_reqs, &trb); } status = &(trb.status); @@ -2526,7 +2532,8 @@ void xhci_endpoint_message ( struct xhci_endpoint *ep, status->direction = ( ( datalen && input ) ? XHCI_STATUS_OUT : XHCI_STATUS_IN ); - xhci_trb_queue(&(ep->reqs), &trb); +// xhci_trb_queue(&(ep->reqs), &trb); + xhci_trb_queue(ep->ep_reqs, &trb); /* pass command trb to hardware */ // DSB(); @@ -2575,7 +2582,8 @@ void xhci_endpoint_stream ( struct xhci_endpoint *ep, normal->type = XHCI_TRB_NORMAL; normal->flags = XHCI_TRB_IOC; - xhci_trb_queue(&(ep->reqs), trb); +// xhci_trb_queue(&(ep->reqs), trb); + xhci_trb_queue(ep->ep_reqs, trb); /* pass command trb to hardware */ // DSB(); diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h index 400ceef0d..2a43d8856 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h @@ -758,6 +758,10 @@ struct xhci_er_seg { /** An xHCI endpoint */ struct xhci_endpoint { struct xhci_ring reqs; /* DO NOT MOVE reqs from structure beg */ + /** xHCI ring */ + struct xhci_ring *ep_reqs; + uintptr_t ep_reqs_vir; + uintptr_t ep_reqs_phy; /** xHCI device */ struct xhci_host *xhci; /** xHCI slot */ From f8768d29a227e2ce6f8e2bb5cca82b03a0e1ac2e Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 5 Aug 2024 23:54:52 -0700 Subject: [PATCH 112/198] add usb3.0 interrupt NO --- .../services/drivers/usb/components/port/xhci/usb_hc_xhci.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h index 4a2c521bf..4b1f89226 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h @@ -59,6 +59,10 @@ extern "C" { #define USB3_VIRADDR_BASE 0x0000002000000000ULL #define USB3_0_VIRADDR_BASE USB3_VIRADDR_BASE #define USB3_1_VIRADDR_BASE USB3_VIRADDR_BASE + USB3_ADDR_OFFSET_UPPER_BOUND + +#define USB3_0_INTERRUPT_NO 201 +#define USB3_1_INTERRUPT_NO 202 + /** * @brief xHCI host controller hardware init. * From 98a64f616d4c9f48af60097e738f9aedf7d2ce89 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Wed, 7 Aug 2024 09:32:21 +0800 Subject: [PATCH 113/198] xhci ring memory is fetched from the memory resource pool. --- .../usb/components/port/xhci/usb_hc_xhci.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index f3f081016..689c8f0eb 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -859,9 +859,8 @@ int xhci_usbh_pipe_alloc(usbh_pipe_t *pipe, const struct usbh_endpoint_cfg *ep_c struct usbh_hubport *hport = ep_cfg->hport; struct xhci_endpoint *ppipe = usb_align(XHCI_RING_SIZE, sizeof(struct xhci_endpoint)); struct xhci_slot *slot; - uintptr_t ring_vir; - uintptr_t ring_phy; - size_t len; + size_t len; + struct usb_mem_page ring_page; if (NULL == ppipe) { return -ENOMEM; @@ -882,15 +881,15 @@ int xhci_usbh_pipe_alloc(usbh_pipe_t *pipe, const struct usbh_endpoint_cfg *ep_c /* Allocate xHCI ring */ len = sizeof(*ppipe->ep_reqs); - rc = naive_mmap(&ring_vir, &ring_phy, len, false); + rc = usb_alloc_mem_data_page(&ring_page); if(rc != 0){ - USB_LOG_ERR("XHCI %s could not allocate xhci device context\n", xhci->name ); + USB_LOG_ERR("XHCI %s could not allocate xhci ring\n", xhci->name ); rc = -ENOMEM; goto failed; } - ppipe->ep_reqs_vir = ring_vir; - ppipe->ep_reqs_phy = ring_phy; - ppipe->ep_reqs = (struct xhci_ring *)ring_vir; + ppipe->ep_reqs_vir = ring_page.vir_addr; + ppipe->ep_reqs_phy = ring_page.phy_addr; + ppipe->ep_reqs = (struct xhci_ring *)ppipe->ep_reqs_vir; memset ( ppipe->ep_reqs, 0, len ); if (ppipe->address == 0) { /* if try to allocate ctrl ep, open device first */ From 22b137f92f7911dd864a41a80f290252641c30c9 Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 6 Aug 2024 23:33:57 -0700 Subject: [PATCH 114/198] Modify address mapping in xhci_transfer --- .../services/drivers/usb/components/port/xhci/xhci.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index fae28bd33..5dec2e413 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -2712,24 +2712,25 @@ static void xhci_transfer ( struct xhci_host *xhci, struct xhci_trb_transfer *trb ) { struct xhci_slot *slot; struct xhci_endpoint *endpoint; - uintptr_t vir_addr; + uintptr_t vir_addr, phy_addr; union xhci_trb *trans_trb; struct xhci_ring *trans_ring; union xhci_trb *pending; uint32_t eidx; int rc; - vir_addr = usb_mem_data_page_phy2vir(trb->transfer); + phy_addr = (trb->transfer & ~(XHCI_RING_SIZE-1)); + vir_addr = usb_mem_data_page_phy2vir(phy_addr); #if 0 if(!vir_addr) return; #endif - trans_trb = (void *)(uintptr_t)(vir_addr); - trans_ring = XHCI_RING(trans_trb); /* to align addr is ring base */ +// trans_trb = trb->transfer; + trans_ring = (struct xhci_ring *)(vir_addr); /* to align addr is ring base */ pending = &trans_ring->evt; /* preserve event trb pending to handle */ - eidx = trans_trb - trans_ring->ring + 1; /* calculate current evt trb index */ + eidx = (trb->transfer - phy_addr)/sizeof(union xhci_trb) + 1; /* calculate current evt trb index */ /* Identify slot */ if ( ( trb->slot > xhci->slots ) || From c637a3d0bc6bd5af4c63ad8412cc76ae92468872 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Wed, 7 Aug 2024 18:57:40 +0800 Subject: [PATCH 115/198] Modify xhci code to adapt to XIZI. --- .../services/drivers/usb/components/port/xhci/xhci.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 5dec2e413..7d0746025 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -319,7 +319,7 @@ static unsigned int xhci_extended_capability ( struct xhci_host *xhci, */ static void xhci_legacy_init ( struct xhci_host *xhci ) { unsigned int legacy; - uint8_t bios; + uint32_t bios; /* Locate USB legacy support capability (if present) */ legacy = xhci_extended_capability ( xhci, XHCI_XECP_ID_LEGACY, 0 ); @@ -1633,7 +1633,7 @@ static void xhci_abort ( struct xhci_host *xhci ) { /* Abort the command */ USB_LOG_WRN("XHCI %s aborting command\n", xhci->name ); - xhci_writeq ( xhci, XHCI_CRCR_CA, xhci->op + XHCI_OP_CRCR ); + xhci_writeq ( xhci, XHCI_CRCR_CA, xhci->op_addr + XHCI_OP_CRCR ); /* Allow time for command to abort */ usb_osal_msleep ( XHCI_COMMAND_ABORT_DELAY_MS ); @@ -1649,7 +1649,7 @@ static void xhci_abort ( struct xhci_host *xhci ) { /* Reset the command ring control register */ memset(xhci->cmds->ring, 0U, XHCI_RING_ITEMS * sizeof(union xhci_trb)); - xhci_writeq ( xhci, ( (uint64_t)(uintptr_t)xhci->cmds | xhci->cmds->cs ), xhci->op + XHCI_OP_CRCR ); + xhci_writeq ( xhci, ( (uint64_t)(uintptr_t)xhci->cmds | xhci->cmds->cs ), xhci->op_addr + XHCI_OP_CRCR ); } /** @@ -1837,7 +1837,9 @@ static int xhci_context ( struct xhci_host *xhci, struct xhci_slot *slot, } err_command: + #if 0 usb_free ( input ); + #endif err_alloc: return rc; } @@ -2203,6 +2205,7 @@ static void xhci_configure_endpoint_input ( struct xhci_host *xhci, /* Populate control context */ control_ctx = input; + /* see XHCI.pdf page 119 */ control_ctx->add = CPU_TO_LE32 (( 1 << XHCI_CTX_SLOT ) | ( 1 << endpoint->ctx ) ); control_ctx->drop = CPU_TO_LE32 (( 1 << XHCI_CTX_SLOT ) | ( 1 << endpoint->ctx ) ); From 55eef9ff58806916f177dc05dd61d2b6a397817c Mon Sep 17 00:00:00 2001 From: xj Date: Wed, 7 Aug 2024 19:21:28 -0700 Subject: [PATCH 116/198] Add comments --- .../XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 7d0746025..bcb0815a3 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -2733,6 +2733,8 @@ static void xhci_transfer ( struct xhci_host *xhci, // trans_trb = trb->transfer; trans_ring = (struct xhci_ring *)(vir_addr); /* to align addr is ring base */ pending = &trans_ring->evt; /* preserve event trb pending to handle */ + +/* We must pay attention on whether the result of eidx should increase by 1 or not, when we begin to debug. */ eidx = (trb->transfer - phy_addr)/sizeof(union xhci_trb) + 1; /* calculate current evt trb index */ /* Identify slot */ From b9de9baf1c46a71e0fd82cfb8d5d727a80ee3ee1 Mon Sep 17 00:00:00 2001 From: xj Date: Wed, 7 Aug 2024 23:43:11 -0700 Subject: [PATCH 117/198] Adding interrupt codes --- .../usb/components/port/xhci/usb_hc_xhci.c | 34 ++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index 689c8f0eb..768b5c560 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -47,6 +47,10 @@ Modification: Modify USB Device Initialization in xHCI code to apply to XiZi AIO #include "usbh_hub.h" #include "xhci.h" +#include "libipc.h" +#include "libserial.h" +#include "usyscall.h" + /************************** Constant Definitions *****************************/ /************************** Variable Definitions *****************************/ @@ -1028,4 +1032,32 @@ int xhci_usbh_kill_urb(struct usbh_urb *urb){ void XHCI_USBH_IRQHandler(void *param){ -} \ No newline at end of file +} + +int IPC_DO_SERVE_FUNC(Ipc_xhci_intr)(void* ignore) +{ + printf("TEST_SW_HDLR: In %s()\n", __func__); + + return 0; +} + + +#if 0 + +int IPC_DO_SERVE_FUNC(Ipc_wait_xhci_intr)(void* ignore) +{ + // delay the this handle +#if 0 + while (!has_one_interrupt) { + yield(SYS_TASK_YIELD_NO_REASON); + } +#endif + // serve can be done by now + + return 0; +} +#endif + +IPC_SERVER_INTERFACE(Ipc_xhci_intr, 1); +// IPC_SERVER_THREAD_INTERFACE(Ipc_wait_xhci_intr, 1); +// IPC_SERVER_REGISTER_INTERFACES(IpcXhciIntrHandler, 2, Ipc_xhci_intr, Ipc_wait_xhci_intr); From 0e09b5590374b4a622b480093b31dbb4d6163ff7 Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 8 Aug 2024 00:08:23 -0700 Subject: [PATCH 118/198] Adding interrupt codes --- .../usb/components/port/xhci/usb_hc_xhci.c | 15 ++++++++++++--- .../usb/components/port/xhci/usb_hc_xhci.h | 7 +++++++ 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index 768b5c560..03cc796db 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -47,9 +47,7 @@ Modification: Modify USB Device Initialization in xHCI code to apply to XiZi AIO #include "usbh_hub.h" #include "xhci.h" -#include "libipc.h" -#include "libserial.h" -#include "usyscall.h" + /************************** Constant Definitions *****************************/ @@ -1061,3 +1059,14 @@ int IPC_DO_SERVE_FUNC(Ipc_wait_xhci_intr)(void* ignore) IPC_SERVER_INTERFACE(Ipc_xhci_intr, 1); // IPC_SERVER_THREAD_INTERFACE(Ipc_wait_xhci_intr, 1); // IPC_SERVER_REGISTER_INTERFACES(IpcXhciIntrHandler, 2, Ipc_xhci_intr, Ipc_wait_xhci_intr); +IPC_SERVER_REGISTER_INTERFACES(IpcXhciIntrHandler, 1, Ipc_xhci_intr); + +int bind_xhci_intr(void *para){ + + if (register_irq(USB3_0_INTERRUPT_NO, Ipc_xhci_intr) < 0) { + printf("bind failed!\n"); + exit(1); + } + + return 0; +} diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h index 4b1f89226..5cd9fa556 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h @@ -41,6 +41,10 @@ Modification: rewrite xhci functions to dock with USB core layer, so that the xh #include "xhci.h" #include "usbh_core.h" +#include "libipc.h" +#include "libserial.h" +#include "usyscall.h" + #ifdef __cplusplus extern "C" { #endif @@ -160,6 +164,9 @@ __WEAK int usb_hc_get_register_id(unsigned long base_addr); __WEAK unsigned long usb_hc_get_register_vir_base(uint32_t id); +int bind_xhci_intr(void *para); + +IPC_SERVICES(IpcXhciIntrHandler, Ipc_xhci_intr); #ifdef __cplusplus } From cd35c4e733ccd5e3e8e85da2feee2d6445df2c77 Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 8 Aug 2024 00:18:38 -0700 Subject: [PATCH 119/198] Adding interrupt codes --- .../usb/components/port/xhci/usb_hc_xhci.c | 26 ++++++------------- 1 file changed, 8 insertions(+), 18 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index 03cc796db..f52dcb11c 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -1040,25 +1040,7 @@ int IPC_DO_SERVE_FUNC(Ipc_xhci_intr)(void* ignore) } -#if 0 - -int IPC_DO_SERVE_FUNC(Ipc_wait_xhci_intr)(void* ignore) -{ - // delay the this handle -#if 0 - while (!has_one_interrupt) { - yield(SYS_TASK_YIELD_NO_REASON); - } -#endif - // serve can be done by now - - return 0; -} -#endif - IPC_SERVER_INTERFACE(Ipc_xhci_intr, 1); -// IPC_SERVER_THREAD_INTERFACE(Ipc_wait_xhci_intr, 1); -// IPC_SERVER_REGISTER_INTERFACES(IpcXhciIntrHandler, 2, Ipc_xhci_intr, Ipc_wait_xhci_intr); IPC_SERVER_REGISTER_INTERFACES(IpcXhciIntrHandler, 1, Ipc_xhci_intr); int bind_xhci_intr(void *para){ @@ -1068,5 +1050,13 @@ int bind_xhci_intr(void *para){ exit(1); } + static char prog_name[] = "xhci0-intr-server"; + if (register_server(prog_name) < 0) { + printf("register server name: %s failed.\n", prog_name); + exit(1); + } + + ipc_server_loop(&IpcXhciIntrHandler); + return 0; } From 4170e41ab7a82d13cc0a380212a011016a73c4ef Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 8 Aug 2024 20:03:37 -0700 Subject: [PATCH 120/198] Add interrupt processing functions --- .../usb/components/port/xhci/usb_hc_xhci.c | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index f52dcb11c..9d5d72de4 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -1029,6 +1029,31 @@ int xhci_usbh_kill_urb(struct usbh_urb *urb){ void XHCI_USBH_IRQHandler(void *param){ + intptr_t id; + struct xhci_host *xhci; + struct xhci_endpoint *work_pipe; + uint32_t usbsts; + uint32_t runtime; + + id = (intptr_t)param; + + if(id < 0 || id >= CONFIG_USBHOST_XHCI_NUM){ + return; + } + + xhci = &xhci_host[id]; + USB_ASSERT(xhci); + + /* clear interrupt status */ + usbsts = readl ( xhci->op_addr + XHCI_OP_USBSTS ); + usbsts |= XHCI_USBSTS_EINT; + writel(usbsts, xhci->op_addr + XHCI_OP_USBSTS); + + /* ack interrupt */ + runtime = readl(xhci->run_addr + XHCI_RUN_IR_IMAN ( 0 )); + runtime |= XHCI_RUN_IR_IMAN_IP; + writel (runtime, xhci->run_addr + XHCI_RUN_IR_IMAN ( 0 )); + (void)xhci_event_process(xhci); } From 45a36e57768882bed0b7ac654f8f249e5fd65a6f Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 8 Aug 2024 20:20:28 -0700 Subject: [PATCH 121/198] Add interrupt processing functions --- .../services/drivers/usb/components/port/xhci/usb_hc_xhci.c | 4 ++++ .../services/drivers/usb/components/port/xhci/usb_hc_xhci.h | 1 + 2 files changed, 5 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index 9d5d72de4..e3ffe3e0f 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -1085,3 +1085,7 @@ int bind_xhci_intr(void *para){ return 0; } + +int create_xhci_intr_service(void *para){ + return 0; +} diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h index 5cd9fa556..eaef45fea 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h @@ -165,6 +165,7 @@ __WEAK int usb_hc_get_register_id(unsigned long base_addr); __WEAK unsigned long usb_hc_get_register_vir_base(uint32_t id); int bind_xhci_intr(void *para); +int create_xhci_intr_service(void *para); IPC_SERVICES(IpcXhciIntrHandler, Ipc_xhci_intr); From 0816b5427a2f3dd79b526aeb76faa8162ca6e9b9 Mon Sep 17 00:00:00 2001 From: xj Date: Fri, 9 Aug 2024 00:51:02 -0700 Subject: [PATCH 122/198] Add interrupt processing functions --- .../XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h index 2a43d8856..1bceb42f5 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h @@ -818,6 +818,8 @@ struct xhci_slot { unsigned int tt_id; /** Transaction translator port */ unsigned int tt_port; + /** Thread ID of the thread that is created to process xhci interrupt */ + unsigned int tid_intr; /** Endpoints, indexed by context ID */ struct xhci_endpoint *endpoint[XHCI_CTX_END]; From 91d06a23b3e8cc9006b29cf35aebcbdcf7221d98 Mon Sep 17 00:00:00 2001 From: xj Date: Fri, 9 Aug 2024 01:07:10 -0700 Subject: [PATCH 123/198] Add interrupt processing functions --- .../drivers/usb/components/port/xhci/usb_hc_xhci.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index e3ffe3e0f..075d29207 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -1087,5 +1087,18 @@ int bind_xhci_intr(void *para){ } int create_xhci_intr_service(void *para){ + struct xhci_host *xhci; + int tid; + + + xhci = (struct xhci_host *)para; + + if(xhci == NULL){ + return -1; + } + + + // tid = thread(); + return 0; } From 7003f26807154902987e850232a64fa46e1d100f Mon Sep 17 00:00:00 2001 From: xj Date: Fri, 9 Aug 2024 04:54:40 -0700 Subject: [PATCH 124/198] Add interrupt processing functions --- .../drivers/usb/components/port/xhci/usb_hc_xhci.c | 12 +++++++++++- .../services/drivers/usb/components/port/xhci/xhci.h | 5 +++-- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index 075d29207..7633a3ec8 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -1098,7 +1098,17 @@ int create_xhci_intr_service(void *para){ } - // tid = thread(); + tid = thread(bind_xhci_intr, "xhci_intr_procedure", para); + +/* Create thread error! */ + if(tid < 0){ + return -1; + }else if(tid > 0){ + xhci->tid_intr = tid; + }else{ +/* Child thread. do nothing except for the interrupt processing function. */ + } + return 0; } diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h index 1bceb42f5..5487ddfd0 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.h @@ -818,8 +818,6 @@ struct xhci_slot { unsigned int tt_id; /** Transaction translator port */ unsigned int tt_port; - /** Thread ID of the thread that is created to process xhci interrupt */ - unsigned int tid_intr; /** Endpoints, indexed by context ID */ struct xhci_endpoint *endpoint[XHCI_CTX_END]; @@ -922,6 +920,9 @@ struct xhci_host { uintptr_t eseg_addr; uintptr_t eseg_phy; + /* Thread ID of the thread that is created to process xhci interrupt */ + unsigned int tid_intr; + struct xhci_endpoint *cur_cmd_pipe; }; From 84ab3dff35c218a58acd9b75c64c5d923e4b1df3 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 13 Aug 2024 09:59:31 +0800 Subject: [PATCH 125/198] Modify rndis and lwip interaction function name. --- .../usb/components/class/wireless/rndis_host.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c index e9a82a47a..addf77d12 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c @@ -66,12 +66,12 @@ usb_osal_thread_t timer_handle; usb_osal_thread_t data_recv_task_handle; -__WEAK int eth_device_linkchange(bool up) +__WEAK int lwip_rndis_device_linkchange(bool up) { return 0; } -__WEAK int eth_device_ready(void *dataptr, size_t len) +__WEAK int lwip_rndis_data_recv(void *dataptr, size_t len) { return 0; } @@ -112,12 +112,12 @@ static void usbh_rndis_data_recv_entry(void *pdata) } if (NDIS_MEDIA_STATE_CONNECTED == data[0]) { s_rndis_class_ptr->link_status = true; - eth_device_linkchange(true); + lwip_rndis_device_linkchange(true); printf("linkup, drop pkg\r\n"); break; } else { s_rndis_class_ptr->link_status = false; - eth_device_linkchange(false); + lwip_rndis_device_linkchange(false); } usb_osal_msleep(100); } @@ -133,7 +133,7 @@ static void usbh_rndis_data_recv_entry(void *pdata) while (ret > 0) { pmsg = (rndis_data_packet_t *)(rx_buffer + pmg_offset); if (pmsg->MessageType == REMOTE_NDIS_PACKET_MSG) { - eth_device_ready((uint8_t *)(&pmsg->DataOffset) + pmsg->DataOffset, pmsg->DataLength); + lwip_rndis_data_recv((uint8_t *)(&pmsg->DataOffset) + pmsg->DataOffset, pmsg->DataLength); pmg_offset += pmsg->MessageLength; ret -= pmsg->MessageLength; } @@ -224,12 +224,12 @@ int usbh_rndis_eth_tx(void *dataptr, size_t tot_len) } if (NDIS_MEDIA_STATE_CONNECTED == data[0]) { s_rndis_class_ptr->link_status = true; - eth_device_linkchange(true); + lwip_rndis_device_linkchange(true); printf("linkup, drop pkg\r\n"); break; } else { s_rndis_class_ptr->link_status = false; - eth_device_linkchange(false); + lwip_rndis_device_linkchange(false); } usb_osal_msleep(100); } From aaceb82386951e4be3491a8ba6b7b86e13ae1fbc Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 13 Aug 2024 14:43:22 +0800 Subject: [PATCH 126/198] New IPC interface, lwip sends data to rndis --- .../XiZi_AIoT/services/drivers/usb/Makefile | 2 +- .../services/drivers/usb/components/usb.mk | 1 + .../services/drivers/usb/usb_service/Makefile | 10 ++++ .../drivers/usb/usb_service/rndis_service.c | 13 ++++++ .../drivers/usb/usb_service/rndis_service.h | 12 +++++ .../drivers/usb/usb_service/usb_host.c | 43 ++++++++++++++--- .../drivers/usb/usb_service/usb_host.h | 7 ++- .../services/net/net_server/Makefile | 6 ++- .../services/net/net_server/arch/Makefile | 1 + .../services/net/net_server/arch/ethernetif.c | 46 ++++++++++++++++++- .../XiZi_AIoT/services/net/net_server/lwip.mk | 3 +- 11 files changed, 129 insertions(+), 15 deletions(-) create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/rndis_service.c create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/rndis_service.h diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/usb/Makefile index 888b55863..99287c6c1 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/Makefile @@ -1,3 +1,3 @@ -SRC_DIR := components +SRC_DIR := components usb_service include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk index ba38d3725..32fa1fc2c 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk @@ -36,6 +36,7 @@ INC_DIR = -I$(KERNEL_ROOT)/services/drivers/usb/ \ -I$(KERNEL_ROOT)/services/drivers/usb/components/osal \ -I$(KERNEL_ROOT)/services/drivers/usb/components/port \ -I$(KERNEL_ROOT)/services/drivers/usb/components/port/xhci \ + -I$(KERNEL_ROOT)/services/drivers/usb/usb_service \ -I$(KERNEL_ROOT)/services//semaphore \ -I$(KERNEL_ROOT)/services/lib/ipc \ -I$(KERNEL_ROOT)/services/lib/memory \ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/Makefile index e69de29bb..27b53be78 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/Makefile @@ -0,0 +1,10 @@ +include $(KERNEL_ROOT)/services/drivers/usb/components/usb.mk + +objs = usb_host.o + +all: ${objs} + @echo "generate $^" + +%.o: %.c + @echo "cc $^" + @${cc} ${cflags} ${c_useropts} ${INC_DIR} -o $@ -c $^ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/rndis_service.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/rndis_service.c new file mode 100644 index 000000000..24bd7e7fa --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/rndis_service.c @@ -0,0 +1,13 @@ +#include "libipc.h" +#include "rndis_service.h" + +IPC_INTERFACE(Ipc_usbh_rndis_eth_tx, 2, dataptr, tot_len, *(size_t *)tot_len, sizeof(size_t)); +int ipc_usbh_rndis_eth_tx(struct Session* session, void *dataptr, size_t tot_len){ + return IPC_CALL(Ipc_usbh_rndis_eth_tx)(session, dataptr, &tot_len); +} + +IPC_INTERFACE(Ipc_usbh_rndis_eth_control, 3, cmd, args, len, sizeof(int), *(size_t *)len, sizeof(size_t)); +int ipc_usbh_rndis_eth_control(struct Session* session, int cmd, void *args, size_t len){ + return IPC_CALL(Ipc_usbh_rndis_eth_control)(session, &cmd, args, &len); +} + diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/rndis_service.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/rndis_service.h new file mode 100644 index 000000000..c9c2dcf34 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/rndis_service.h @@ -0,0 +1,12 @@ +#ifndef RNDIS_SERVICE_H_ +#define RNDIS_SERVICE_H_ + +#include "libipc.h" + +IPC_SERVICES(IpcRndisServer, Ipc_usbh_rndis_eth_tx, Ipc_usbh_rndis_eth_control); + +int ipc_usbh_rndis_eth_tx(struct Session* session, void *dataptr, size_t tot_len); +int ipc_usbh_rndis_eth_control(struct Session* session, int cmd, void *args, size_t len); + +#endif + diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c index b46384fc7..902455a1a 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c @@ -1,6 +1,37 @@ -#include "usb_host.h" - - -int main(){ - return 0; -} +#include "usb_host.h" +#include "usyscall.h" +#include "libipc.h" +#include "rndis_service.h" + +/* IPC rndis server */ +int IPC_DO_SERVE_FUNC(Ipc_usbh_rndis_eth_tx)(void *dataptr, size_t *tot_len){ + return usbh_rndis_eth_tx(dataptr, *tot_len); +} + +int IPC_DO_SERVE_FUNC(Ipc_usbh_rndis_eth_control)(int *cmd, void *args, size_t *len){ + return usbh_rndis_eth_control(*cmd, args, *len); +} + +IPC_SERVER_INTERFACE(Ipc_usbh_rndis_eth_tx, 2); +IPC_SERVER_INTERFACE(Ipc_usbh_rndis_eth_control, 3); + +IPC_SERVER_REGISTER_INTERFACES(IpcRndisServer, 2, Ipc_usbh_rndis_eth_tx, Ipc_usbh_rndis_eth_control); + +int ipc_rndis_server_init(void) +{ + if (register_server("RndisServer") < 0) { + printf("register server name: %s failed.\n", "RndisServer"); + return -1; + } + ipc_server_loop(&IpcRndisServer); + + return 0; +} + + +/* usb main*/ +int main(){ + ipc_rndis_server_init(); + return 0; +} + diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.h index e6e9f9efb..904cb4abe 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.h @@ -1,9 +1,8 @@ #ifndef USB_HOST_H_ #define USB_HOST_H_ +#include - - - - +int usbh_rndis_eth_tx(void *dataptr, size_t tot_len); +int usbh_rndis_eth_control(int cmd, void *args, size_t len); #endif diff --git a/Ubiquitous/XiZi_AIoT/services/net/net_server/Makefile b/Ubiquitous/XiZi_AIoT/services/net/net_server/Makefile index aeade75e7..498b63d53 100644 --- a/Ubiquitous/XiZi_AIoT/services/net/net_server/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/net/net_server/Makefile @@ -53,10 +53,12 @@ arch_usyscall = $(KERNEL_ROOT)/services/app/arch_usyscall.o session = $(KERNEL_ROOT)/services/app/session.o libipc = $(KERNEL_ROOT)/services/app/libipc.o libsem = $(KERNEL_ROOT)/services/app/libsemaphore.o +librndis = $(KERNEL_ROOT)/services/net/net_server/rndis_service.o + lwip: COMPILER lwip_server.o | bin - @${ld} ${user_ldflags} -e main -o $@ ${sys} ${api} ${core} ${ipv4} ${netif} lwip_server.o ${libserial} ${printf} ${libmem} ${usyscall} ${arch_usyscall} ${session} ${libipc} ${libsem} ${board_specs} + @${ld} ${user_ldflags} -e main -o $@ ${librndis} ${sys} ${api} ${core} ${ipv4} ${netif} lwip_server.o ${libserial} ${printf} ${libmem} ${usyscall} ${arch_usyscall} ${session} ${libipc} ${libsem} ${board_specs} @${objdump} -S $@ > $@.asm - @$(ar) -r liblwip.a ${sys} ${api} ${core} ${ipv4} ${netif} + @$(ar) -r liblwip.a ${librndis} ${sys} ${api} ${core} ${ipv4} ${netif} @mv *.o bin @mv $@ $(KERNEL_ROOT)/services/app @mv $@.asm $(KERNEL_ROOT)/services/app diff --git a/Ubiquitous/XiZi_AIoT/services/net/net_server/arch/Makefile b/Ubiquitous/XiZi_AIoT/services/net/net_server/arch/Makefile index 1a5320eda..6b1c4e9b6 100644 --- a/Ubiquitous/XiZi_AIoT/services/net/net_server/arch/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/net/net_server/arch/Makefile @@ -1,5 +1,6 @@ include $(KERNEL_ROOT)/services/net/net_server/lwip.mk objs += sys_arch.o ethernetif.o +objs += $(KERNEL_ROOT)/services/drivers/usb/usb_service/rndis_service.o arch: ${objs} diff --git a/Ubiquitous/XiZi_AIoT/services/net/net_server/arch/ethernetif.c b/Ubiquitous/XiZi_AIoT/services/net/net_server/arch/ethernetif.c index 91d0c91fa..5973e0cd1 100644 --- a/Ubiquitous/XiZi_AIoT/services/net/net_server/arch/ethernetif.c +++ b/Ubiquitous/XiZi_AIoT/services/net/net_server/arch/ethernetif.c @@ -20,10 +20,15 @@ #include "lwip/ethip6.h" #include "lwip/etharp.h" #include "libserial.h" +#include "rndis_service.h" + /* Define those to better describe your network interface. */ #define IFNAME0 'e' #define IFNAME1 'n' +/* IPC rndis client */ +struct Session *g_session_rndis = NULL; + /** * In this function, the hardware should be initialized. * Called from ethernetif_init(). @@ -80,6 +85,21 @@ void print_packet_data(const char *packet_data, int length) { } } } + +/** + * This function should do the actual transmission of the packet. + * + * @param dataptr pointer to the actual data in the buffer + * @param tot_len the length of this buffer + * @return ERR_OK if the send is success + * any other err_t on error + */ +int usbh_rndis_eth_tx(void *dataptr, size_t tot_len) +{ + struct Session* session = g_session_rndis; + return ipc_usbh_rndis_eth_tx(session, dataptr, tot_len);; +} + /** * This function should do the actual transmission of the packet. The packet is * contained in the pbuf that is passed to the function. This pbuf @@ -104,8 +124,11 @@ static err_t low_level_output(struct netif *netif, struct pbuf *p) #endif pbuf_copy_partial(p, buf, p->tot_len, 0); - + print_packet_data(buf, p->tot_len); + + usbh_rndis_eth_tx(buf, p->tot_len); + return ERR_OK; } @@ -149,6 +172,26 @@ void ethernetif_input(struct netif *netif) } } +/** + * In this function, get session info. + * Called from ethernetif_init(). + * + * @return lwIP error code + */ +int ipc_rndis_client_init(void) +{ + struct Session *session; + + session = mem_malloc(sizeof(struct Session)); + if(connect_session(session, "RndisServer", 4096) < 0) { + printf("connect session failed\n"); + return ERR_IF; + } + g_session_rndis = session; + + return ERR_OK; +} + /** * Should be called at the beginning of the program to set up the * network interface. It calls the function low_level_init() to do the @@ -190,6 +233,7 @@ err_t ethernetif_init(struct netif *netif) /* initialize the hardware */ low_level_init(netif); + ipc_rndis_client_init(); return ERR_OK; } diff --git a/Ubiquitous/XiZi_AIoT/services/net/net_server/lwip.mk b/Ubiquitous/XiZi_AIoT/services/net/net_server/lwip.mk index df9b6bd6e..0dc3e5777 100644 --- a/Ubiquitous/XiZi_AIoT/services/net/net_server/lwip.mk +++ b/Ubiquitous/XiZi_AIoT/services/net/net_server/lwip.mk @@ -41,4 +41,5 @@ INC_DIR = -I$(KERNEL_ROOT)/services/net/libnet \ -I$(KERNEL_ROOT)/services/lib/serial \ -I$(KERNEL_ROOT)/services/lib/usyscall \ -I$(KERNEL_ROOT)/services/boards/$(BOARD) \ - -I$(KERNEL_ROOT)/services/app + -I$(KERNEL_ROOT)/services/app \ + -I$(KERNEL_ROOT)/services/drivers/usb/usb_service From b53ba2e4b47bc8edb95ad508400ced779b67c7f9 Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 13 Aug 2024 19:31:36 -0700 Subject: [PATCH 127/198] Interrupt function --- .../drivers/usb/components/port/xhci/usb_hc_xhci.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index 7633a3ec8..8ccf71ace 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -612,6 +612,10 @@ int xhci_usb_hc_init(uint32_t id){ goto err_open; } + if((rc = create_xhci_intr_service(xhci) < 0 )){ + goto err_open; + } + err_open: usb_osal_leave_critical_section(flag); return rc; @@ -1035,12 +1039,14 @@ void XHCI_USBH_IRQHandler(void *param){ uint32_t usbsts; uint32_t runtime; + id = (intptr_t)param; if(id < 0 || id >= CONFIG_USBHOST_XHCI_NUM){ return; } + xhci = &xhci_host[id]; USB_ASSERT(xhci); @@ -1060,6 +1066,10 @@ void XHCI_USBH_IRQHandler(void *param){ int IPC_DO_SERVE_FUNC(Ipc_xhci_intr)(void* ignore) { printf("TEST_SW_HDLR: In %s()\n", __func__); + intptr_t id; + + id = 0; + XHCI_USBH_IRQHandler((void *)id); return 0; } From 059da067dfc7ce589e65814243876232238ece3e Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Wed, 14 Aug 2024 17:22:54 +0800 Subject: [PATCH 128/198] New IPC interface, lwip receives data from rndis. --- .../services/drivers/usb/components/usb.mk | 1 + .../services/drivers/usb/usb_service/Makefile | 1 + .../drivers/usb/usb_service/usb_host.c | 25 ++++++++++ .../services/net/libnet/lwip_rndis_service.c | 25 ++++++++++ .../services/net/libnet/lwip_rndis_service.h | 31 ++++++++++++ .../services/net/libnet/lwip_service.c | 6 +++ .../services/net/libnet/lwip_service.h | 10 +++- .../services/net/net_server/arch/ethernetif.c | 48 +++++++++++++++++-- .../services/net/net_server/arch/ethernetif.h | 2 +- .../services/net/net_server/lwip_server.c | 10 +++- 10 files changed, 151 insertions(+), 8 deletions(-) create mode 100644 Ubiquitous/XiZi_AIoT/services/net/libnet/lwip_rndis_service.c create mode 100644 Ubiquitous/XiZi_AIoT/services/net/libnet/lwip_rndis_service.h diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk index 32fa1fc2c..20415ddbd 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk @@ -42,6 +42,7 @@ INC_DIR = -I$(KERNEL_ROOT)/services/drivers/usb/ \ -I$(KERNEL_ROOT)/services/lib/memory \ -I$(KERNEL_ROOT)/services/lib/serial \ -I$(KERNEL_ROOT)/services/lib/usyscall \ + -I$(KERNEL_ROOT)/services/net/libnet \ -I$(KERNEL_ROOT)/services/boards/$(BOARD) \ -I$(KERNEL_ROOT)/services/app diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/Makefile index 27b53be78..3e4ac9f01 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/Makefile @@ -1,6 +1,7 @@ include $(KERNEL_ROOT)/services/drivers/usb/components/usb.mk objs = usb_host.o +objs += $(KERNEL_ROOT)/services/net/libnet/lwip_rndis_service.o all: ${objs} @echo "generate $^" diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c index 902455a1a..336b0a142 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c @@ -1,7 +1,9 @@ #include "usb_host.h" +#include "usb_mem.h" #include "usyscall.h" #include "libipc.h" #include "rndis_service.h" +#include "lwip_rndis_service.h" /* IPC rndis server */ int IPC_DO_SERVE_FUNC(Ipc_usbh_rndis_eth_tx)(void *dataptr, size_t *tot_len){ @@ -28,9 +30,32 @@ int ipc_rndis_server_init(void) return 0; } +/* IPC lwip client */ +struct Session *g_session_lwip = NULL; + +int ipc_lwip_client_init(void) +{ + struct Session *session; + + session = usb_malloc(sizeof(struct Session)); + if(connect_session(session, "LWIPServer", 4096) < 0) { + printf("connect session failed\n"); + return -1; + } + g_session_lwip = session; + + return 0; +} + +int lwip_rndis_data_recv(void *dataptr, size_t len) +{ + struct Session* session = g_session_lwip; + return ipc_lwip_rndis_data_recv(session, dataptr, len); +} /* usb main*/ int main(){ + ipc_lwip_client_init(); ipc_rndis_server_init(); return 0; } diff --git a/Ubiquitous/XiZi_AIoT/services/net/libnet/lwip_rndis_service.c b/Ubiquitous/XiZi_AIoT/services/net/libnet/lwip_rndis_service.c new file mode 100644 index 000000000..8228a5edd --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/net/libnet/lwip_rndis_service.c @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/************************************************* +History: +1. Date: 2024-08-14 +Author: AIIT XUOS Lab +Modification: New file lwip_rndis_service.c, in order to avoid rndis compiling other module functions. + Refer to $(KERNEL_ROOT)/services/net/libnet/lwip_service.c. +*************************************************/ +#include "lwip_rndis_service.h" + +// The interface between lwip and rndis +IPC_INTERFACE(Ipc_lwip_rndis_data_recv, 2, dataptr, len, *(size_t *)len, sizeof(size_t)); +int ipc_lwip_rndis_data_recv(struct Session* session, void *dataptr, size_t len){ + return IPC_CALL(Ipc_lwip_rndis_data_recv)(session, dataptr, &len); +} diff --git a/Ubiquitous/XiZi_AIoT/services/net/libnet/lwip_rndis_service.h b/Ubiquitous/XiZi_AIoT/services/net/libnet/lwip_rndis_service.h new file mode 100644 index 000000000..1a45bffc2 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/net/libnet/lwip_rndis_service.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/************************************************* +History: +1. Date: 2024-08-14 +Author: AIIT XUOS Lab +Modification: New file lwip_rndis_service.h, in order to avoid rndis compiling other module functions. + Refer to $(KERNEL_ROOT)/services/net/libnet/lwip_service.h. +*************************************************/ +#ifndef LWIP_RNDIS_SERVICE_H +#define LWIP_RNDIS_SERVICE_H + +#include "libipc.h" + +IPC_SERVICES(IpcLWIPServer, Ipc_socket, Ipc_bind,Ipc_connect,Ipc_listen,Ipc_accept, + Ipc_read, Ipc_recv, Ipc_recfrom, Ipc_sendto, Ipc_send, Ipc_write, Ipc_close, Ipc_setsockopt, + Ipc_lwip_rndis_data_recv); + +// The interface between lwip and rndis +int ipc_lwip_rndis_data_recv(struct Session* session, void *dataptr, size_t len); + +#endif /* LWIP_RNDIS_SERVICE_H */ diff --git a/Ubiquitous/XiZi_AIoT/services/net/libnet/lwip_service.c b/Ubiquitous/XiZi_AIoT/services/net/libnet/lwip_service.c index c7bf12b7a..7c5df676a 100644 --- a/Ubiquitous/XiZi_AIoT/services/net/libnet/lwip_service.c +++ b/Ubiquitous/XiZi_AIoT/services/net/libnet/lwip_service.c @@ -76,3 +76,9 @@ IPC_INTERFACE(Ipc_setsockopt, 5, s, level, optname, optval, optlen, sizeof(int), int ipc_setsockopt(struct Session* session, int s, int level, int optname, void *optval, socklen_t optlen){ return IPC_CALL(Ipc_setsockopt)(session, &s, &level, &optname, optval, &optlen); } + +// The interface between lwip and rndis +IPC_INTERFACE(Ipc_lwip_rndis_data_recv, 2, dataptr, len, *(size_t *)len, sizeof(size_t)); +int ipc_lwip_rndis_data_recv(struct Session* session, void *dataptr, size_t len){ + return IPC_CALL(Ipc_lwip_rndis_data_recv)(session, dataptr, &len); +} diff --git a/Ubiquitous/XiZi_AIoT/services/net/libnet/lwip_service.h b/Ubiquitous/XiZi_AIoT/services/net/libnet/lwip_service.h index 11fa77db1..655f89ae1 100644 --- a/Ubiquitous/XiZi_AIoT/services/net/libnet/lwip_service.h +++ b/Ubiquitous/XiZi_AIoT/services/net/libnet/lwip_service.h @@ -9,12 +9,15 @@ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. * See the Mulan PSL v2 for more details. */ +#ifndef LWIP_SERVICE_H +#define LWIP_SERVICE_H #include "libipc.h" #include "lwip/sockets.h" IPC_SERVICES(IpcLWIPServer, Ipc_socket, Ipc_bind,Ipc_connect,Ipc_listen,Ipc_accept, - Ipc_read, Ipc_recv, Ipc_recfrom, Ipc_sendto, Ipc_send, Ipc_write, Ipc_close, Ipc_setsockopt) + Ipc_read, Ipc_recv, Ipc_recfrom, Ipc_sendto, Ipc_send, Ipc_write, Ipc_close, Ipc_setsockopt, + Ipc_lwip_rndis_data_recv) int ipc_socket(struct Session* session, int domain, int type, int protocol); @@ -42,3 +45,8 @@ ssize_t ipc_write(struct Session* session, int s, void *data, size_t size); int ipc_close(struct Session* session, int s); int ipc_setsockopt(struct Session* session, int s, int level, int optname, void *optval, socklen_t optlen); + +// The interface between lwip and rndis +int ipc_lwip_rndis_data_recv(struct Session* session, void *dataptr, size_t len); + +#endif /* LWIP_SERVICE_H */ diff --git a/Ubiquitous/XiZi_AIoT/services/net/net_server/arch/ethernetif.c b/Ubiquitous/XiZi_AIoT/services/net/net_server/arch/ethernetif.c index 5973e0cd1..067bfe90c 100644 --- a/Ubiquitous/XiZi_AIoT/services/net/net_server/arch/ethernetif.c +++ b/Ubiquitous/XiZi_AIoT/services/net/net_server/arch/ethernetif.c @@ -26,6 +26,9 @@ #define IFNAME0 'e' #define IFNAME1 'n' +/* the lwip network interface */ +struct netif *g_netif = NULL; + /* IPC rndis client */ struct Session *g_session_rndis = NULL; @@ -137,13 +140,27 @@ static err_t low_level_output(struct netif *netif, struct pbuf *p) * packet from the interface into the pbuf. * * @param netif the lwip network interface structure for this ethernetif + * @param dataptr the received data + * @param len the length of received data * @return a pbuf filled with the received packet (including MAC header) * NULL on memory error */ -static struct pbuf* low_level_input(struct netif *netif) +static struct pbuf* low_level_input(struct netif *netif, void *dataptr, size_t len) { - struct pbuf *p=NULL, *q=NULL; - return p; + struct pbuf *p=NULL, *q=NULL; + int payload_offset = 0; + + /* allocate buffer */ + p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); //cherryusb 0.10.2 + if (p != NULL) { + for (q = p; q != NULL; q = q->next) { + /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ + memcpy(q->payload, dataptr + payload_offset, q->len); + payload_offset += q->len; + } + } + + return p; } /** @@ -154,13 +171,15 @@ static struct pbuf* low_level_input(struct netif *netif) * the appropriate input function is called. * * @param netif the lwip network interface structure for this ethernetif + * @param dataptr the received data + * @param len the length of received data */ -void ethernetif_input(struct netif *netif) +void ethernetif_input(struct netif *netif, void *dataptr, size_t len) { struct pbuf *p; /* move received packet into a new pbuf */ - p = low_level_input(netif); + p = low_level_input(netif, dataptr, len); /* if no packet could be read, silently ignore this */ if (p != NULL) { /* pass all packets to ethernet_input, which decides what packets it supports */ @@ -172,6 +191,22 @@ void ethernetif_input(struct netif *netif) } } +/** + * This function should be called when a packet is ready to be read + * from the interface. It uses the function ethernetif_input() that + * should handle the received data. + * + * @param dataptr received data + * @param len length of received data + * @return lwIP error code + */ +int lwip_rndis_data_recv(void *dataptr, size_t len) +{ + struct netif *netif = g_netif; + ethernetif_input(netif, dataptr, len); + return ERR_OK; +} + /** * In this function, get session info. * Called from ethernetif_init(). @@ -233,7 +268,10 @@ err_t ethernetif_init(struct netif *netif) /* initialize the hardware */ low_level_init(netif); + g_netif = netif; + ipc_rndis_client_init(); + return ERR_OK; } diff --git a/Ubiquitous/XiZi_AIoT/services/net/net_server/arch/ethernetif.h b/Ubiquitous/XiZi_AIoT/services/net/net_server/arch/ethernetif.h index 98a576b0a..c5e649636 100644 --- a/Ubiquitous/XiZi_AIoT/services/net/net_server/arch/ethernetif.h +++ b/Ubiquitous/XiZi_AIoT/services/net/net_server/arch/ethernetif.h @@ -17,6 +17,6 @@ #define NETIF_ENET_INIT_FUNC ethernetif_init err_t ethernetif_init(struct netif *netif); -void ethernetif_input(struct netif *netif); +int lwip_rndis_data_recv(void *dataptr, size_t len); #endif diff --git a/Ubiquitous/XiZi_AIoT/services/net/net_server/lwip_server.c b/Ubiquitous/XiZi_AIoT/services/net/net_server/lwip_server.c index 12757e45d..d0e9b7077 100644 --- a/Ubiquitous/XiZi_AIoT/services/net/net_server/lwip_server.c +++ b/Ubiquitous/XiZi_AIoT/services/net/net_server/lwip_server.c @@ -21,6 +21,7 @@ #include "netif/ethernet.h" #include "sys_arch.h" #include "lwip/sockets.h" +#include "arch/ethernetif.h" extern struct netif gnetif; @@ -89,6 +90,10 @@ int IPC_DO_SERVE_FUNC(Ipc_setsockopt)(int *s, int *level, int *optname, const vo return setsockopt(*s, *level, *optname, optval, *optlen); } +// The interface between lwip and rndis +int IPC_DO_SERVE_FUNC(Ipc_lwip_rndis_data_recv)(void *dataptr, size_t *len){ + return lwip_rndis_data_recv(dataptr, *len); +} IPC_SERVER_INTERFACE(Ipc_socket, 3); IPC_SERVER_INTERFACE(Ipc_bind, 3); @@ -103,6 +108,8 @@ IPC_SERVER_INTERFACE(Ipc_send, 4); IPC_SERVER_INTERFACE(Ipc_write, 3); IPC_SERVER_INTERFACE(Ipc_close, 1); IPC_SERVER_INTERFACE(Ipc_setsockopt, 5); +// The interface between lwip and rndis +IPC_SERVER_INTERFACE(Ipc_lwip_rndis_data_recv, 2); IPC_SERVER_REGISTER_INTERFACES(IpcLWIPServer, 12, Ipc_socket, @@ -117,7 +124,8 @@ IPC_SERVER_REGISTER_INTERFACES(IpcLWIPServer, 12, Ipc_send, Ipc_write, Ipc_close, - Ipc_setsockopt); + Ipc_setsockopt, + Ipc_lwip_rndis_data_recv); int main(int argc, char* argv[]){ char lwip_ipaddr[4] = { 192, 168, 130, 77 }; From a9273b98799bda28d4bdf0b333e6ac80df1854e9 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Thu, 15 Aug 2024 19:26:02 +0800 Subject: [PATCH 129/198] Merge branch rk3568_dev of https://www.gitlink.org.cn/tuyuyang/xiuos with commit 6bc856b7a6 into local --- Ubiquitous/XiZi_AIoT/Makefile | 6 +- .../XiZi_AIoT/hardkernel/arch/arm/Makefile | 2 +- .../hardkernel/arch/arm/armv8-a/Makefile | 4 +- .../{cortex-a72 => cortex-a55}/Makefile | 0 .../context_switch.S | 0 .../armv8-a/{cortex-a72 => cortex-a55}/core.c | 4 +- .../armv8-a/{cortex-a72 => cortex-a55}/core.h | 15 +- .../preboot_for_3568/3568.lds} | 42 +- .../cortex-a55/preboot_for_3568/Makefile | 6 + .../cortex-a55/preboot_for_3568/boot.S | 120 ++++++ .../preboot_for_3568}/config.mk | 7 +- .../preboot_for_3568/cortexA55.S} | 13 +- .../preboot_for_3568/include/cortex_a55.h} | 14 +- .../preboot_for_3568}/include/registers.h | 0 .../preboot_for_3568}/smp.c | 26 +- .../cortex-a55/preboot_for_3568/xizi_smp.S | 27 ++ .../armv8-a/{cortex-a55 => cortex-a72}/boot.S | 0 .../cortex-a72/preboot_for_ok1028a-c/Makefile | 5 - .../cortex-a72/preboot_for_ok1028a-c/boot.S | 81 ---- .../hardkernel/cache/L1/arm/Makefile | 4 +- .../cache/L1/arm/cortex-a55/Makefile | 3 + .../cache/L1/arm/cortex-a55/cache.S | 336 ++++++++++++++++ .../arm/{cortex-a72 => cortex-a55}/l1_cache.c | 32 +- .../arm/{cortex-a72 => cortex-a55}/l1_cache.h | 0 .../cache/L1/arm/cortex-a72/Makefile | 3 - .../hardkernel/cache/cache_common_ope.c | 4 +- .../XiZi_AIoT/hardkernel/clock/arm/Makefile | 2 +- .../hardkernel/clock/arm/armv8-a/Makefile | 4 +- .../ok1028a-c => cortex-a55/3568}/Makefile | 0 .../ok1028a-c => cortex-a55/3568}/clock.c | 18 +- .../3568}/include/generic_timer.h | 16 +- .../{cortex-a72 => cortex-a55}/Makefile | 0 .../XiZi_AIoT/hardkernel/hardkernel_init.c | 1 + .../XiZi_AIoT/hardkernel/intr/arm/Makefile | 2 +- .../hardkernel/intr/arm/armv8-a/Makefile | 2 +- .../3568}/exception_registers.h | 0 .../3568}/irq_numbers.h | 0 .../ok1028a-c => cortex-a55/3568}/trap.c | 27 +- .../3568}/trap_common.c | 2 +- .../{cortex-a72 => cortex-a55}/Makefile | 2 +- .../{cortex-a72 => cortex-a55}/error_debug.c | 82 ++-- .../{cortex-a72 => cortex-a55}/gicv3/Makefile | 0 .../{cortex-a72 => cortex-a55}/gicv3/gicv3.c | 0 .../gicv3/gicv3_common_opa.h | 0 .../gicv3/gicv3_registers.h | 4 +- .../hard_spinlock.S | 76 ++-- .../{cortex-a72 => cortex-a55}/trampoline.S | 38 +- .../XiZi_AIoT/hardkernel/intr/spinlock.c | 6 +- .../XiZi_AIoT/hardkernel/mmu/arm/Makefile | 2 +- .../mmu/arm/armv7-a/cortex-a9/bootmmu.c | 2 +- .../cortex-a9/imx6q-sabrelite/memlayout.h | 2 +- .../cortex-a9/zynq7000-zc702/memlayout.h | 2 +- .../hardkernel/mmu/arm/armv8-a/Makefile | 2 +- .../ok1028a-c => cortex-a55/3568}/memlayout.h | 22 +- .../{cortex-a72 => cortex-a55}/Makefile | 0 .../{cortex-a72 => cortex-a55}/bootmmu.c | 77 ++-- .../{cortex-a72 => cortex-a55}/include/mmu.h | 23 +- .../armv8-a/{cortex-a72 => cortex-a55}/mmu.c | 2 + .../pagetable_attr.c | 12 +- .../XiZi_AIoT/hardkernel/uart/arm/Makefile | 2 +- .../hardkernel/uart/arm/armv8-a/Makefile | 2 +- .../{cortex-a72 => cortex-a55}/Makefile | 0 .../cortex-a55/uart_io_for_3568/Makefile | 3 + .../uart_io_for_3568/include/ns16550.h | 198 +++++++++ .../uart_io_for_3568}/include/uart.h | 0 .../cortex-a55/uart_io_for_3568/ns16550.c | 103 +++++ .../cortex-a55/uart_io_for_3568/uart.c | 45 +++ .../armv8-a/{cortex-a55 => cortex-a72}/boot.S | 0 .../cortex-a72/uart_io_for_ok1028a-c/Makefile | 3 - .../cortex-a72/uart_io_for_ok1028a-c/uart.c | 128 ------ .../XiZi_AIoT/kernel_actracer/actracer.c | 40 +- Ubiquitous/XiZi_AIoT/path_kernel.mk | 26 +- Ubiquitous/XiZi_AIoT/services/app/Makefile | 12 +- Ubiquitous/XiZi_AIoT/services/app/init.c | 42 -- .../XiZi_AIoT/services/app/shell_port.c | 2 +- .../XiZi_AIoT/services/app/simple_client.c | 2 +- .../XiZi_AIoT/services/app/simple_server.c | 3 +- .../boards/{ok1028a-c => 3568}/Makefile | 4 +- .../{ok1028a-c => 3568}/arch_usyscall.c | 0 .../services/boards/3568/libserial.c | 250 ++++++++++++ .../boards/{ok1028a-c => 3568}/stub.c | 0 .../services/boards/imx6q-sabrelite/Makefile | 4 +- .../services/boards/ok1028a-c/libserial.c | 113 ------ .../services/boards/zynq7000-zc702/Makefile | 4 +- .../drivers/{rk-3568 => 3568}/Makefile | 0 .../drivers/{rk-3568 => 3568}/hal/Makefile | 9 +- .../drivers/{rk-3568 => 3568}/hal/hal_base.c | 10 +- .../drivers/{rk-3568 => 3568}/hal/hal_bsp.c | 0 .../drivers/{rk-3568 => 3568}/hal/hal_cru.c | 264 +----------- .../{rk-3568 => 3568}/hal/hal_cru_rk3568.c | 0 .../drivers/{rk-3568 => 3568}/hal/hal_debug.c | 0 .../drivers/{rk-3568 => 3568}/hal/hal_gmac.c | 56 ++- .../{rk-3568 => 3568}/hal/hal_gmac_3568.c | 0 .../drivers/{rk-3568 => 3568}/hal/hal_gpio.c | 0 .../{rk-3568 => 3568}/hal/hal_pinctrl_v2.c | 0 .../drivers/{rk-3568 => 3568}/hal/hal_timer.c | 0 .../{rk-3568 => 3568}/hal/system_rk3568.c | 0 .../drivers/{rk-3568 => 3568}/hal/test_gmac.c | 366 +++++++++-------- .../{rk-3568 => 3568}/include/hal_base.h | 0 .../{rk-3568 => 3568}/include/hal_bsp.h | 0 .../{rk-3568 => 3568}/include/hal_conf.h | 0 .../{rk-3568 => 3568}/include/hal_cru.h | 0 .../{rk-3568 => 3568}/include/hal_debug.h | 0 .../{rk-3568 => 3568}/include/hal_def.h | 0 .../{rk-3568 => 3568}/include/hal_driver.h | 0 .../{rk-3568 => 3568}/include/hal_gmac.h | 12 +- .../{rk-3568 => 3568}/include/hal_gpio.h | 0 .../{rk-3568 => 3568}/include/hal_list.h | 0 .../{rk-3568 => 3568}/include/hal_pinctrl.h | 0 .../{rk-3568 => 3568}/include/hal_pm.h | 0 .../{rk-3568 => 3568}/include/hal_timer.h | 0 .../{rk-3568 => 3568}/include/rk3568.h | 14 +- .../drivers/{rk-3568 => 3568}/include/soc.h | 0 .../{rk-3568 => 3568}/include/system_rk3568.h | 0 .../XiZi_AIoT/services/drivers/Makefile | 2 +- .../drivers/imx6q-sabrelite/clock/Makefile | 4 +- .../drivers/imx6q-sabrelite/enet/Makefile | 10 +- .../drivers/imx6q-sabrelite/gpio/Makefile | 4 +- .../drivers/imx6q-sabrelite/lib/Makefile | 4 +- .../services/drivers/ok1028a-c/Makefile | 3 - .../XiZi_AIoT/services/fs/fs_server/Makefile | 4 +- .../XiZi_AIoT/services/fs/libfs/Makefile | 4 +- .../XiZi_AIoT/services/lib/ipc/Makefile | 4 +- .../XiZi_AIoT/services/lib/ipc/libipc.c | 1 - .../XiZi_AIoT/services/lib/memory/Makefile | 4 +- .../XiZi_AIoT/services/lib/serial/Makefile | 4 +- .../XiZi_AIoT/services/lib/usyscall/Makefile | 4 +- .../services/lib/usyscall/usyscall.c | 295 +++++++------- .../services/lib/usyscall/usyscall.h | 211 +++++----- .../XiZi_AIoT/services/net/libnet/Makefile | 7 + .../XiZi_AIoT/services/net/net_server/lwip.mk | 7 + .../XiZi_AIoT/services/semaphore/Makefile | 4 +- .../services/shell/letter-shell/Makefile | 4 +- .../XiZi_AIoT/softkernel/include/buddy.h | 3 +- .../XiZi_AIoT/softkernel/include/kalloc.h | 1 + .../XiZi_AIoT/softkernel/include/memspace.h | 28 +- .../XiZi_AIoT/softkernel/include/pagetable.h | 13 +- .../XiZi_AIoT/softkernel/include/syscall.h | 232 +++++------ .../XiZi_AIoT/softkernel/include/task.h | 21 +- .../softkernel/init/softkernel_init.c | 2 +- Ubiquitous/XiZi_AIoT/softkernel/load_apps.S | 2 +- Ubiquitous/XiZi_AIoT/softkernel/main.c | 20 +- .../XiZi_AIoT/softkernel/memory/Makefile | 2 +- .../XiZi_AIoT/softkernel/memory/kalloc.c | 8 +- .../XiZi_AIoT/softkernel/memory/pagetable.c | 40 +- .../softkernel/memory/pagetable_level2.c | 19 - .../softkernel/memory/pagetable_level3.c | 23 +- .../XiZi_AIoT/softkernel/memory/share_page.c | 10 +- .../XiZi_AIoT/softkernel/syscall/sys_kill.c | 11 + .../XiZi_AIoT/softkernel/syscall/sys_mmap.c | 141 +++---- .../softkernel/syscall/sys_poll_session.c | 14 +- .../XiZi_AIoT/softkernel/syscall/sys_state.c | 378 +++++++++--------- .../XiZi_AIoT/softkernel/syscall/sys_thread.c | 5 + .../XiZi_AIoT/softkernel/syscall/sys_yield.c | 23 +- .../XiZi_AIoT/softkernel/syscall/syscall.c | 178 ++++----- .../XiZi_AIoT/softkernel/task/memspace.c | 39 +- Ubiquitous/XiZi_AIoT/softkernel/task/task.c | 23 +- .../softkernel/trap/clock_irq_handler.c | 162 ++++---- 158 files changed, 2742 insertions(+), 2135 deletions(-) rename Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/{cortex-a72 => cortex-a55}/Makefile (100%) rename Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/{cortex-a72 => cortex-a55}/context_switch.S (100%) rename Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/{cortex-a72 => cortex-a55}/core.c (93%) rename Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/{cortex-a72 => cortex-a55}/core.h (95%) rename Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/{cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds => cortex-a55/preboot_for_3568/3568.lds} (77%) create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/boot.S rename Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/{cortex-a72/preboot_for_ok1028a-c => cortex-a55/preboot_for_3568}/config.mk (50%) rename Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/{cortex-a72/preboot_for_ok1028a-c/cortexA72.S => cortex-a55/preboot_for_3568/cortexA55.S} (76%) rename Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/{cortex-a72/preboot_for_ok1028a-c/include/cortex_a72.h => cortex-a55/preboot_for_3568/include/cortex_a55.h} (97%) rename Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/{cortex-a72/preboot_for_ok1028a-c => cortex-a55/preboot_for_3568}/include/registers.h (100%) rename Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/{cortex-a72/preboot_for_ok1028a-c => cortex-a55/preboot_for_3568}/smp.c (75%) create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/xizi_smp.S rename Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/{cortex-a55 => cortex-a72}/boot.S (100%) delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/Makefile delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/boot.S create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a55/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a55/cache.S rename Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/{cortex-a72 => cortex-a55}/l1_cache.c (88%) rename Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/{cortex-a72 => cortex-a55}/l1_cache.h (100%) delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a72/Makefile rename Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/{cortex-a72/ok1028a-c => cortex-a55/3568}/Makefile (100%) rename Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/{cortex-a72/ok1028a-c => cortex-a55/3568}/clock.c (87%) rename Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/{cortex-a72/ok1028a-c => cortex-a55/3568}/include/generic_timer.h (69%) rename Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/{cortex-a72 => cortex-a55}/Makefile (100%) rename Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/{cortex-a72/ok1028a-c => cortex-a55/3568}/exception_registers.h (100%) rename Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/{cortex-a72/ok1028a-c => cortex-a55/3568}/irq_numbers.h (100%) rename Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/{cortex-a72/ok1028a-c => cortex-a55/3568}/trap.c (78%) rename Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/{cortex-a72/ok1028a-c => cortex-a55/3568}/trap_common.c (99%) rename Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/{cortex-a72 => cortex-a55}/Makefile (70%) rename Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/{cortex-a72 => cortex-a55}/error_debug.c (74%) rename Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/{cortex-a72 => cortex-a55}/gicv3/Makefile (100%) rename Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/{cortex-a72 => cortex-a55}/gicv3/gicv3.c (100%) rename Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/{cortex-a72 => cortex-a55}/gicv3/gicv3_common_opa.h (100%) rename Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/{cortex-a72 => cortex-a55}/gicv3/gicv3_registers.h (93%) rename Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/{cortex-a72 => cortex-a55}/hard_spinlock.S (63%) rename Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/{cortex-a72 => cortex-a55}/trampoline.S (95%) rename Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/{cortex-a72/ok1028a-c => cortex-a55/3568}/memlayout.h (78%) rename Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/{cortex-a72 => cortex-a55}/Makefile (100%) rename Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/{cortex-a72 => cortex-a55}/bootmmu.c (53%) rename Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/{cortex-a72 => cortex-a55}/include/mmu.h (91%) rename Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/{cortex-a72 => cortex-a55}/mmu.c (99%) rename Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/{cortex-a72 => cortex-a55}/pagetable_attr.c (78%) rename Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/{cortex-a72 => cortex-a55}/Makefile (100%) create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_3568/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_3568/include/ns16550.h rename Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/{cortex-a72/uart_io_for_ok1028a-c => cortex-a55/uart_io_for_3568}/include/uart.h (100%) create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_3568/ns16550.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_3568/uart.c rename Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/{cortex-a55 => cortex-a72}/boot.S (100%) delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/Makefile delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/uart.c delete mode 100755 Ubiquitous/XiZi_AIoT/services/app/init.c rename Ubiquitous/XiZi_AIoT/services/boards/{ok1028a-c => 3568}/Makefile (84%) rename Ubiquitous/XiZi_AIoT/services/boards/{ok1028a-c => 3568}/arch_usyscall.c (100%) create mode 100644 Ubiquitous/XiZi_AIoT/services/boards/3568/libserial.c rename Ubiquitous/XiZi_AIoT/services/boards/{ok1028a-c => 3568}/stub.c (100%) delete mode 100644 Ubiquitous/XiZi_AIoT/services/boards/ok1028a-c/libserial.c rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/Makefile (100%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/hal/Makefile (79%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/hal/hal_base.c (99%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/hal/hal_bsp.c (100%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/hal/hal_cru.c (83%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/hal/hal_cru_rk3568.c (100%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/hal/hal_debug.c (100%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/hal/hal_gmac.c (97%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/hal/hal_gmac_3568.c (100%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/hal/hal_gpio.c (100%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/hal/hal_pinctrl_v2.c (100%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/hal/hal_timer.c (100%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/hal/system_rk3568.c (100%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/hal/test_gmac.c (71%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/include/hal_base.h (100%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/include/hal_bsp.h (100%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/include/hal_conf.h (100%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/include/hal_cru.h (100%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/include/hal_debug.h (100%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/include/hal_def.h (100%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/include/hal_driver.h (100%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/include/hal_gmac.h (95%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/include/hal_gpio.h (100%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/include/hal_list.h (100%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/include/hal_pinctrl.h (100%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/include/hal_pm.h (100%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/include/hal_timer.h (100%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/include/rk3568.h (99%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/include/soc.h (100%) rename Ubiquitous/XiZi_AIoT/services/drivers/{rk-3568 => 3568}/include/system_rk3568.h (100%) delete mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/ok1028a-c/Makefile diff --git a/Ubiquitous/XiZi_AIoT/Makefile b/Ubiquitous/XiZi_AIoT/Makefile index c5402b1ef..4bc6e3b00 100755 --- a/Ubiquitous/XiZi_AIoT/Makefile +++ b/Ubiquitous/XiZi_AIoT/Makefile @@ -4,7 +4,7 @@ MAKEFLAGS += --no-print-directory .PHONY:COMPILE_APP COMPILE_KERNEL riscv_support := -arm_support += imx6q-sabrelite zynq7000-zc702 ok1028a-c +arm_support += imx6q-sabrelite zynq7000-zc702 3568 emulator_support += support := $(riscv_support) $(arm_support) $(emulator_support) SRC_DIR := @@ -34,8 +34,8 @@ export UBIQUITOUS_ROOT ?= .. ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), ) include $(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_$(BOARD)/config.mk endif -ifneq ($(findstring $(BOARD), ok1028a-c), ) -include $(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_$(BOARD)/config.mk +ifneq ($(findstring $(BOARD), 3568), ) +include $(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_$(BOARD)/config.mk endif export BSP_BUILD_DIR := $(KERNEL_ROOT) export HOSTTOOLS_DIR ?= $(KERNEL_ROOT)/services/tools/hosttools diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/Makefile index 05e53ecfe..8f7703c39 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/Makefile @@ -1,5 +1,5 @@ # The following three platforms support compatiable instructions. -ifneq ($(findstring $(BOARD), ok1028a-c), ) +ifneq ($(findstring $(BOARD), 3568), ) SRC_DIR := armv8-a endif ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), ) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/Makefile index f0253e59d..f1319354d 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/Makefile @@ -1,6 +1,6 @@ # The following three platforms support compatiable instructions. -ifneq ($(findstring $(BOARD), ok1028a-c), ) -SRC_DIR := cortex-a72 +ifneq ($(findstring $(BOARD), 3568), ) +SRC_DIR := cortex-a55 endif diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/Makefile similarity index 100% rename from Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/Makefile rename to Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/Makefile diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/context_switch.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/context_switch.S similarity index 100% rename from Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/context_switch.S rename to Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/context_switch.S diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/core.c b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.c similarity index 93% rename from Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/core.c rename to Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.c index fd10e6264..e677d92d6 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/core.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.c @@ -29,7 +29,7 @@ Modification: 1. first version *************************************************/ -/*********cortex-a72 general register************ +/*********cortex-a55 general register************ EL0 | EL1 | EL2 | EL3 x0; @@ -63,7 +63,7 @@ Modification: x28; x29; x30; -*********cortex-a72 special register************ +*********cortex-a55 special register************ XZR PC SP_EL0 SP_EL1 SP_EL2 SP_EL3 diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/core.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.h similarity index 95% rename from Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/core.h rename to Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.h index 57d42c303..c9667450f 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/core.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.h @@ -12,7 +12,7 @@ /** * @file core.h - * @brief cortex-a72 core function + * @brief cortex-a55 core function * @version 1.0 * @author AIIT XUOS Lab * @date 2024.04.11 @@ -20,7 +20,7 @@ /************************************************* File name: core.h -Description: cortex-a72 core function +Description: cortex-a55 core function Others: History: Author: AIIT XUOS Lab @@ -71,7 +71,7 @@ Modification: #include #include -#include "cortex_a72.h" +#include "cortex_a55.h" #define NR_CPU 4 // maximum number of CPUs @@ -79,15 +79,6 @@ __attribute__((always_inline)) static inline uint64_t EL0_mode() // Set ARM mode { uint64_t val = 0; - __asm__ __volatile__( - "mrs %0, spsr_el1" - : "=r"(val) - : - :); - val &= ~DIS_INT; - val &= ~SPSR_MODE_MASK; - val |= ARM_MODE_EL0_t; - return val; } diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/3568.lds similarity index 77% rename from Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds rename to Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/3568.lds index 722ddf1e7..66e93e538 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/3568.lds @@ -45,30 +45,36 @@ ENTRY( _ENTRY ) ENTRY( _boot_start ) MEMORY { - phy_ddr3 (rwx) : ORIGIN = 0x0000000040000000, LENGTH = 1024M - vir_ddr3 (rwx) : ORIGIN = 0x0000006040635000, LENGTH = 1024M + phy_ddr3 (rwx) : ORIGIN = 0x0000000010000000, LENGTH = 1024M + vir_ddr3 (rwx) : ORIGIN = 0x000000601040E000, LENGTH = 1024M } SECTIONS { .start_sec : { - . = ALIGN(0x1000); + . = ORIGIN(phy_ddr3); /* initialization start checkpoint. */ - boot.o(.text) - bootmmu.o(.text .text.*) + _start_image_addr = .; - boot.o(.rodata .rodata.*) - bootmmu.o(.rodata .rodata.*) + boot.o(.text) + bootmmu.o(.text .text.*) + /* ns16550.o(.text .text.*) */ - boot.o(.data .data.*) - bootmmu.o(.data .data.*) + boot.o(.rodata .rodata.*) + bootmmu.o(.rodata .rodata.*) + /* ns16550.o(.rodata .rodata.*) */ - PROVIDE(boot_start_addr = .); + boot.o(.data .data.*) + bootmmu.o(.data .data.*) + /* ns16550.o(.data .data.*) */ - boot.o(.bss .bss.* COMMON) - bootmmu.o(.bss .bss.* COMMON) + PROVIDE(boot_start_addr = .); + + boot.o(.bss .bss.* COMMON) + bootmmu.o(.bss .bss.* COMMON) + /* ns16550.o(.bss .bss.* COMMON) */ /* stack for booting code. */ . = ALIGN(0x1000); @@ -81,7 +87,7 @@ SECTIONS PROVIDE(boot_end_addr = .); } > phy_ddr3 - .text : AT(0x40635000) { + .text : AT(0x1040E000) { . = ALIGN(0x1000); *(.text .text.* .gnu.linkonce.t.*) } > vir_ddr3 @@ -103,17 +109,19 @@ SECTIONS PROVIDE(_binary_default_fs_start = .); *(.rawdata_memfs*) PROVIDE(_binary_default_fs_end = .); + PROVIDE(__init_array_start = .); + PROVIDE(__init_array_end = .); } > vir_ddr3 . = ALIGN(0x1000); - PROVIDE(kernel_data_begin = .); + _image_size = . - 0x0000006010000000; - _image_size = . - 0x0000006040000000; .bss : { + PROVIDE(kernel_data_begin = .); PROVIDE(__bss_start__ = .); *(.bss .bss.* COMMON) + . = ALIGN(0x1000); PROVIDE(__bss_end__ = .); + PROVIDE(kernel_data_end = .); } > vir_ddr3 - . = ALIGN(0x1000); - PROVIDE(kernel_data_end = .); } \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/Makefile new file mode 100644 index 000000000..a195629ce --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/Makefile @@ -0,0 +1,6 @@ +SRC_FILES := boot.S \ + xizi_smp.S \ + smp.c \ + cortexA55.S + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/boot.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/boot.S new file mode 100644 index 000000000..bf9535a90 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/boot.S @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +#include "core.h" + +#define HCR_VALUE (1 << 31) +#define SPSR_EL2_VALUE (7 << 6) | (5 << 0) +#define SCTLR_EL1_VALUE (0x30D00800) + +.section ".text", "ax" +.global _boot_start +.global primary_cpu_init +.global el2_setup + +_boot_start: + bl el2_setup + + /* set NSACR, both Secure and Non-secure access are allowed to NEON */ + mov x0, #(3 << 20) + msr cpacr_el1, x0 + isb + + // clear some registers + msr elr_el1, XZR + + ldr x0, =stacks_top + mov x1, #MODE_STACK_SIZE + + // get cpu id, and subtract the offset from the stacks base address + mrs x2, mpidr_el1 + and x2, x2, #0xFFF + lsr x2, x2, #8 + mov x5, x2 + mul x3, x2, x1 + sub x0, x0, x3 + mov sp, x0 + + mov x2, #ARM_MODE_EL1_h | DIS_INT + msr spsr_el1, x2 + + // check cpu id - cpu0 is primary cpu + mrs x2, mpidr_el1 + and x2, x2, #0xFFF + lsr x2, x2, #8 + mov x5, x2 + cmp x5, #0 + beq primary_cpu_init + bl bootmain // for secondary cpus, jump to argument function pointer passed in by ROM + + bl . + +primary_cpu_init: + /* init .bss */ + /* clear the .bss section (zero init) */ + ldr x1, =boot_start_addr + ldr x2, =boot_end_addr + mov x3, #0 +1: + cmp x1, x2 + stp x3, x3, [x1], #16 + b.lt 1b + + bl bootmain + + .func el2_setup +el2_setup: + mrs x0, CurrentEL + lsr x0, x0, #2 + and x0, x0, #3 + cmp x0, #2 + beq 1f + ret + + /* Hyp configuration. */ +1: + mov x0, #(1 << 31) + msr hcr_el2, x0 + + /* Generic timers. */ + mrs x0, cnthctl_el2 + orr x0, x0, #3 // Enable EL1 physicaltimers + msr cnthctl_el2, x0 + + /* Populate ID registers. */ + mrs x0, midr_el1 + mrs x1, mpidr_el1 + msr vpidr_el2, x0 + msr vmpidr_el2, x1 + + /* Disable Coprocessor traps. */ + mov x0, #0x33ff + msr cptr_el2, x0 // Disable copro. traps to EL2 + + msr hstr_el2, xzr // Disable CP15 traps to EL2 + + mov x0, sp + msr sp_el1, x0 + + mrs x0, sctlr_el1 + orr x0, x0, #(1 << 0) + bic x0, x0, #(1 << 1) + orr x0, x0, #(1 << 2) + msr sctlr_el1, x0 + + /* spsr */ + mov x0, #SPSR_EL2_VALUE + msr spsr_el2, x0 + msr elr_el2, lr + eret + .endfunc + + .end \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/config.mk b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/config.mk similarity index 50% rename from Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/config.mk rename to Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/config.mk index 020fa3ca6..33b1f65a0 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/config.mk +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/config.mk @@ -1,8 +1,7 @@ export CROSS_COMPILE ?= aarch64-none-elf- -export DEVICE = -mtune=cortex-a72 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie -export CFLAGS := $(DEVICE) -Wall -Werror -O2 -g -fno-omit-frame-pointer -fPIC -# export AFLAGS := -c $(DEVICE) -x assembler-with-cpp -D__ASSEMBLY__ -gdwarf-2 -export LFLAGS := $(DEVICE) -Wl,-T -Wl,$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds -Wl,--start-group,-lgcc,-lc,--end-group +export DEVICE = -mtune=cortex-a55 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie +export CFLAGS := $(DEVICE) -Wall -Werror -O2 -g -fno-omit-frame-pointer -fPIC +export LFLAGS := $(DEVICE) -Wl,-T -Wl,$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/3568.lds -Wl,--start-group,-lgcc,-lc,--end-group export CXXFLAGS := export DEFINES := -DHAVE_CCONFIG_H -DCHIP_LS1028 diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/cortexA72.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/cortexA55.S similarity index 76% rename from Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/cortexA72.S rename to Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/cortexA55.S index 72cc33cad..1a63b65b5 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/cortexA72.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/cortexA55.S @@ -1,14 +1,14 @@ /*! - * @file cortexA72.s - * @brief This file contains cortexA72 functions + * @file cortexA55.s + * @brief This file contains cortexA55 functions * */ /************************************************* -File name: cortexA72.S +File name: cortexA55.S Description: This file contains cortexA9 functions Others: History: -1. Date: 202-05-08 +1. Date: 2024-05-08 Author: AIIT XUOS Lab Modification: 1. No modifications @@ -21,7 +21,8 @@ Modification: .func cpu_get_current cpu_get_current: mrs x0, mpidr_el1 - and x0, x0, #3 + and x0, x0, #0xFFF + lsr x0, x0, #8 ret .endfunc @@ -32,6 +33,6 @@ psci_call: # ------------------------------------------------------------ -# End of cortexA72.s +# End of cortexA55.s # ------------------------------------------------------------ .end \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/include/cortex_a72.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/include/cortex_a55.h similarity index 97% rename from Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/include/cortex_a72.h rename to Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/include/cortex_a55.h index 3358e8d12..ad90943d0 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/include/cortex_a72.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/include/cortex_a55.h @@ -28,16 +28,16 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** - * @file cortex_a72.h - * @brief some cortex A72 core functions + * @file cortex_a55.h + * @brief some cortex A55 core functions * @version 1.0 * @author AIIT XUOS Lab * @date 2024.04.24 */ /************************************************* -File name: cortex_a72.h -Description: some cortex A72 core functions +File name: cortex_a55.h +Description: some cortex A55 core functions Others: History: Author: AIIT XUOS Lab @@ -45,8 +45,8 @@ Modification: 1. No modifications *************************************************/ -#if !defined(__CORTEX_A72_H__) -#define __CORTEX_A72_H__ +#if !defined(__CORTEX_A55_H__) +#define __CORTEX_A55_H__ #include #include @@ -231,4 +231,4 @@ void scu_secure_invalidate(unsigned int cpu, unsigned int ways); } #endif -#endif //__CORTEX_A72_H__ \ No newline at end of file +#endif //__CORTEX_A55_H__ \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/include/registers.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/include/registers.h similarity index 100% rename from Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/include/registers.h rename to Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/include/registers.h diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/smp.c b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/smp.c similarity index 75% rename from Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/smp.c rename to Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/smp.c index c1e84b58c..395b3e32e 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/smp.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/smp.c @@ -48,12 +48,34 @@ Modification: #include #define PSCI_CPUON 0xc4000003 +struct xizi_smccc_res { + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; +}; extern void _boot_start(); -void psci_call(uint64_t fn, uint8_t cpuid, uint64_t entry, uint64_t ctxid); +extern void __print(); + +extern void __xizi_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2, + unsigned long a3, unsigned long a4, unsigned long a5, + unsigned long a6, unsigned long a7, struct xizi_smccc_res* res); + +static struct xizi_smccc_res __invoke_sip_fn_smc(unsigned long function_id, + unsigned long arg0, + unsigned long arg1, + unsigned long arg2) +{ + struct xizi_smccc_res res; + + __xizi_smccc_smc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res); + return res; +} + void cpu_start_secondary(uint8_t cpu_id) { - psci_call(PSCI_CPUON, cpu_id, (uintptr_t)&_boot_start, 0); + __invoke_sip_fn_smc(PSCI_CPUON, cpu_id, (uintptr_t)0xa00000, 0); } void start_smp_cache_broadcast(int cpu_id) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/xizi_smp.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/xizi_smp.S new file mode 100644 index 000000000..f6082b5e1 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/xizi_smp.S @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +.global __xizi_smccc_smc + +.func __xizi_smccc_smc +__xizi_smccc_smc: + smc #0 + ldr x4, [sp] + stp x0, x1, [x4, #0] + stp x2, x3, [x4, #16] + ldr x4, [sp, #8] + cbz x4, 1f /* no quirk structure */ + ldr x9, [x4, #0] + cmp x9, #1 + b.ne 1f + str x6, [x4, 8] +1: ret +.endfunc \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/boot.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/boot.S similarity index 100% rename from Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/boot.S rename to Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/boot.S diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/Makefile deleted file mode 100644 index 6cd6837c6..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -SRC_FILES := boot.S \ - smp.c \ - cortexA72.S - -include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/boot.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/boot.S deleted file mode 100644 index 2f88de747..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/boot.S +++ /dev/null @@ -1,81 +0,0 @@ -// #include "memlayout.h" -#include "core.h" -// #include "registers.h" -// #include "cortex_a72.h" - // qemu -kernel loads the kernel at 0x40000000 - // and causes each CPU to jump there. - // kernel.ld causes the following code to - // be placed at 0x40000000. -.section ".text" -//.global _entry -.global _boot_start -.global primary_cpu_init - -_boot_start: - // set up a stack for C. - // stack0 is declared in start.c, - // with a 4096-byte stack per CPU. - // sp = stack0 + ((cpuid+1) * 4096) - // cpuid = mpidr_el1 & 0xff - // save r0 for cores 1-3, r0 arg field passed by ROM - // r0 is a function pointer for secondary cpus - - // mov x4, x0 - - mrs x0, spsr_el1 /* Enter EL1 (Exception Level 1) */ - bic x0, x0, #0x1f - MOV x1, #0xC5 - ORR x0, x0, x1 - msr spsr_el1, x0 - - - /* set NSACR, both Secure and Non-secure access are allowed to NEON */ - MRS X1, CPACR_EL1 - ORR X1, X1, #(0X3 << 20) - MSR CPACR_EL1, X1 - ISB - - // clear some registers - msr elr_el1, XZR - - ldr x0, =stacks_top - mov x1, #MODE_STACK_SIZE - - // get cpu id, and subtract the offset from the stacks base address - mrs x2, mpidr_el1 - and x2, x2, #0x3 - mov x5, x2 - mul x3, x2, x1 - sub x0, x0, x3 - - MOV X2, #ARM_MODE_EL1_h | DIS_INT - MSR SPSR_EL1, X2 - mov sp, x0 - SUB x0, x0,x1 - - // check cpu id - cpu0 is primary cpu - cmp x5, #0 - beq primary_cpu_init - bl bootmain // for secondary cpus, jump to argument function pointer passed in by ROM - - bl . - -primary_cpu_init: - /* init .bss */ - /* clear the .bss section (zero init) */ - ldr x1, =boot_start_addr - ldr x2, =boot_end_addr - mov x3, #0 - 1: - cmp x1, x2 - stp x3, x3, [x1], #16 - b.lt 1b - - // branch to c library entry point - mov x0, #0 // argc - mov x1, #0 // argv - mov x2, #0 // env - - bl bootmain - - .end diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/Makefile index 2e244bef0..c87f4ca4a 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/Makefile @@ -1,8 +1,8 @@ ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), ) SRC_DIR := cortex-a9 endif -ifneq ($(findstring $(BOARD), ok1028a-c), ) -SRC_DIR := cortex-a72 +ifneq ($(findstring $(BOARD), 3568), ) +SRC_DIR := cortex-a55 endif include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a55/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a55/Makefile new file mode 100644 index 000000000..11407977e --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a55/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := l1_cache.c cache.S + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a55/cache.S b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a55/cache.S new file mode 100644 index 000000000..95596c6ce --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a55/cache.S @@ -0,0 +1,336 @@ +/* + * (C) Copyright 2013 + * David Feng + * + * This file is based on sample code from ARMv8 ARM. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#define ASM_NL ; + +#define SYMBOL_NAME(X) X + +// #define SYMBOL_NAME_LABEL(X) X##: + +#define SYMBOL_NAME_LABEL(X) X: + +#ifndef __ALIGN +#define __ALIGN .align 4 +#endif + +#ifndef __ALIGN_STR +#define __ALIGN_STR ".align 4" +#endif + +#define ALIGN __ALIGN +#define ALIGN_STR __ALIGN_STR + +#define LENTRY(name) \ + ALIGN ASM_NL \ + SYMBOL_NAME_LABEL(name) + +#define ENTRY(name) \ + .globl SYMBOL_NAME(name) ASM_NL \ + LENTRY(name) + +#define WEAK(name) \ + .weak SYMBOL_NAME(name) ASM_NL \ + LENTRY(name) + + +#define END(name) \ + .size name, .-name + +#define ENDPROC(name) \ + .type name STT_FUNC ASM_NL \ + END(name) + +#define CR_M (1 << 0) /* MMU enable */ +#define CR_A (1 << 1) /* Alignment abort enable */ +#define CR_C (1 << 2) /* Dcache enable */ +#define CR_SA (1 << 3) /* Stack Alignment Check Enable */ +#define CR_I (1 << 12) /* Icache enable */ +#define CR_WXN (1 << 19) /* Write Permision Imply XN */ +#define CR_EE (1 << 25) /* Exception (Big) Endian */ + +.macro switch_el, xreg, el3_label, el2_label, el1_label + mrs \xreg, CurrentEL + cmp \xreg, 0xc + b.eq \el3_label + cmp \xreg, 0x8 + b.eq \el2_label + cmp \xreg, 0x4 + b.eq \el1_label +.endm + + +/* + * void __asm_dcache_level(level) + * flush or invalidate one level cache. + * + * x0: cache level + * x1: 0 clean & invalidate, 1 invalidate only + * x2~x9: clobbered + */ +ENTRY(__asm_dcache_level) + lsl x12, x0, #1 + msr csselr_el1, x12 /* select cache level */ + isb /* sync change of cssidr_el1 */ + mrs x6, ccsidr_el1 /* read the new cssidr_el1 */ + and x2, x6, #7 /* x2 <- log2(cache line size)-4 */ + add x2, x2, #4 /* x2 <- log2(cache line size) */ + mov x3, #0x3ff + and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */ + clz w5, w3 /* bit position of #ways */ + mov x4, #0x7fff + and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */ + /* x12 <- cache level << 1 */ + /* x2 <- line length offset */ + /* x3 <- number of cache ways - 1 */ + /* x4 <- number of cache sets - 1 */ + /* x5 <- bit position of #ways */ + +loop_set: + mov x6, x3 /* x6 <- working copy of #ways */ +loop_way: + lsl x7, x6, x5 + orr x9, x12, x7 /* map way and level to cisw value */ + lsl x7, x4, x2 + orr x9, x9, x7 /* map set number to cisw value */ + tbz w1, #0, 1f + dc isw, x9 + b 2f +1: dc cisw, x9 /* clean & invalidate by set/way */ +2: subs x6, x6, #1 /* decrement the way */ + b.ge loop_way + subs x4, x4, #1 /* decrement the set */ + b.ge loop_set + + ret +ENDPROC(__asm_dcache_level) + + +/* + * void __asm_flush_dcache_all(int invalidate_only) + * + * x0: 0 clean & invalidate, 1 invalidate only + * + * flush or invalidate all data cache by SET/WAY. + */ + +ENTRY(__asm_dcache_all) + mov x1, x0 + dsb sy + mrs x10, clidr_el1 /* read clidr_el1 */ + lsr x11, x10, #24 + and x11, x11, #0x7 /* x11 <- loc */ + cbz x11, finished /* if loc is 0, exit */ + mov x15, lr + mov x0, #0 /* start flush at cache level 0 */ + /* x0 <- cache level */ + /* x10 <- clidr_el1 */ + /* x11 <- loc */ + /* x15 <- return address */ + +loop_level: + lsl x12, x0, #1 + add x12, x12, x0 /* x0 <- tripled cache level */ + lsr x12, x10, x12 + and x12, x12, #7 /* x12 <- cache type */ + cmp x12, #2 + b.lt skip /* skip if no cache or icache */ + bl __asm_dcache_level /* x1 = 0 flush, 1 invalidate */ +skip: + add x0, x0, #1 /* increment cache level */ + cmp x11, x0 + b.gt loop_level + + mov x0, #0 + msr csselr_el1, x0 /* restore csselr_el1 */ + dsb sy + isb + mov lr, x15 + +finished: + ret +ENDPROC(__asm_dcache_all) + + +ENTRY(__asm_flush_dcache_all) + mov x0, #0 + b __asm_dcache_all +ENDPROC(__asm_flush_dcache_all) + + +ENTRY(__asm_invalidate_dcache_all) + mov x0, #0x1 + b __asm_dcache_all +ENDPROC(__asm_invalidate_dcache_all) + + +/* + * void __asm_flush_dcache_range(start, end) + * + * clean & invalidate data cache in the range + * + * x0: start address + * x1: end address + */ + +ENTRY(__asm_flush_dcache_range) + isb + mrs x3, ctr_el0 + lsr x3, x3, #16 + and x3, x3, #0xf + mov x2, #4 + lsl x2, x2, x3 /* cache line size */ + + /* x2 <- minimal cache line size in cache system */ + sub x3, x2, #1 + bic x0, x0, x3 +1: dc civac, x0 /* clean & invalidate data or unified cache */ + add x0, x0, x2 + cmp x0, x1 + b.lo 1b + dsb sy + isb + ret +ENDPROC(__asm_flush_dcache_range) + +/* + * void __asm_invalidate_dcache_range(start, end) + * + * invalidate data cache in the range + * + * x0: start address + * x1: end address + */ + +ENTRY(__asm_invalidate_dcache_range) + mrs x3, ctr_el0 + ubfm x3, x3, #16, #19 + mov x2, #4 + lsl x2, x2, x3 /* cache line size */ + + /* x2 <- minimal cache line size in cache system */ + sub x3, x2, #1 + bic x0, x0, x3 +1: dc ivac, x0 /* invalidate data or unified cache */ + add x0, x0, x2 + cmp x0, x1 + b.lo 1b + dsb sy + isb + ret +ENDPROC(__asm_invalidate_dcache_range) + + +/* + * void __asm_invalidate_icache_all(void) + * + * invalidate all tlb entries. + */ + +ENTRY(__asm_invalidate_icache_all) + ic ialluis + isb sy + ret +ENDPROC(__asm_invalidate_icache_all) + + + +ENTRY(__asm_invalidate_l3_dcache) + mov x0, #0 /* return status as success */ + ret +ENDPROC(__asm_invalidate_l3_dcache) + .weak __asm_invalidate_l3_dcache + + + +ENTRY(__asm_flush_l3_dcache) + mov x0, #0 /* return status as success */ + ret +ENDPROC(__asm_flush_l3_dcache) + .weak __asm_flush_l3_dcache + + + +ENTRY(__asm_invalidate_l3_icache) + mov x0, #0 /* return status as success */ + ret +ENDPROC(__asm_invalidate_l3_icache) + .weak __asm_invalidate_l3_icache + + +/* + * void __asm_switch_ttbr(ulong new_ttbr) + * + * Safely switches to a new page table. + */ + +ENTRY(__asm_switch_ttbr) + /* x2 = SCTLR (alive throghout the function) */ + switch_el x4, 3f, 2f, 1f +3: mrs x2, sctlr_el3 + b 0f +2: mrs x2, sctlr_el2 + b 0f +1: mrs x2, sctlr_el1 +0: + + /* Unset CR_M | CR_C | CR_I from SCTLR to disable all caches */ + movn x1, #(CR_M | CR_C | CR_I) + and x1, x2, x1 + switch_el x4, 3f, 2f, 1f +3: msr sctlr_el3, x1 + b 0f +2: msr sctlr_el2, x1 + b 0f +1: msr sctlr_el1, x1 +0: isb + + /* This call only clobbers x30 (lr) and x9 (unused) */ + mov x3, x30 + bl __asm_invalidate_tlb_all + + /* From here on we're running safely with caches disabled */ + + /* Set TTBR to our first argument */ + switch_el x4, 3f, 2f, 1f +3: msr ttbr0_el3, x0 + b 0f +2: msr ttbr0_el2, x0 + b 0f +1: msr ttbr0_el1, x0 +0: isb + + /* Restore original SCTLR and thus enable caches again */ + switch_el x4, 3f, 2f, 1f +3: msr sctlr_el3, x2 + b 0f +2: msr sctlr_el2, x2 + b 0f +1: msr sctlr_el1, x2 +0: isb + + ret x3 +ENDPROC(__asm_switch_ttbr) + +ENTRY(__asm_invalidate_tlb_all) + switch_el x9, 3f, 2f, 1f +3: tlbi alle3 + dsb sy + isb + b 0f +2: tlbi alle2 + dsb sy + isb + b 0f +1: tlbi vmalle1 + dsb sy + isb +0: + ret +ENDPROC(__asm_invalidate_tlb_all) \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a72/l1_cache.c b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a55/l1_cache.c similarity index 88% rename from Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a72/l1_cache.c rename to Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a55/l1_cache.c index eb2dfd2ee..5d9b26ed7 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a72/l1_cache.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a55/l1_cache.c @@ -20,6 +20,10 @@ Modification: *************************************************/ #include "l1_cache.h" +extern void __asm_flush_dcache_all(); +extern void __asm_flush_l3_dcache(); +extern void __asm_invalidate_icache_all(); +extern void __asm_invalidate_l3_icache(); void InvalidateL1Dcache(uintptr_t start, uintptr_t end) { @@ -153,34 +157,14 @@ void FlushL1Dcache(uintptr_t start, uintptr_t end) void FlushL1DcacheAll(void) { - uint64_t ccsidr_el1; // Cache Size ID - int num_sets; // number of sets - int num_ways; // number of ways - uint32_t wayset; // wayset parameter - - __asm__ __volatile__("mrs %0, ccsidr_el1" : "=r"(ccsidr_el1)); // Read Cache Size ID - - // Fill number of sets and number of ways from ccsidr_el1 register This walues are decremented by 1 - num_sets = ((ccsidr_el1 >> 32) & 0x7FFF) + 1; - num_ways = ((ccsidr_el1 >> 0) & 0x7FFF) + 1; - - // clean and invalidate all lines (all Sets in all ways) - for (int way = 0; way < num_ways; way++) { - for (int set = 0; set < num_sets; set++) { - wayset = (way << 30) | (set << 5); - __asm__ __volatile__("dc cisw, %0" : : "r"(wayset)); - } - } - - // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete - DSB(); + __asm_flush_dcache_all(); + __asm_flush_l3_dcache(); } void InvalidateL1IcacheAll() { - __asm__ __volatile__("ic iallu\n\t"); - // synchronize context on this processor - ISB(); + __asm_invalidate_icache_all(); + __asm_invalidate_l3_icache(); } void InvalidateL1Icache(uintptr_t start, uintptr_t end) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a72/l1_cache.h b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a55/l1_cache.h similarity index 100% rename from Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a72/l1_cache.h rename to Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a55/l1_cache.h diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a72/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a72/Makefile deleted file mode 100644 index 23bc22506..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a72/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -SRC_FILES := l1_cache.c - -include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/cache/cache_common_ope.c b/Ubiquitous/XiZi_AIoT/hardkernel/cache/cache_common_ope.c index 8b19d959f..e2b9e8465 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/cache/cache_common_ope.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/cache/cache_common_ope.c @@ -92,7 +92,7 @@ static inline void invalidate_icache(uintptr_t start, uintptr_t end) static inline void invalidate_icache_all(void) { - // InvalidateL1IcacheAll(); + InvalidateL1IcacheAll(); } /**************************************************************************** @@ -151,7 +151,7 @@ static inline void flush_dcache(uintptr_t start, uintptr_t end) static inline void flush_dcache_all(void) { - // FlushL1DcacheAll(); + FlushL1DcacheAll(); // FlushL2CacheAll(); } diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/Makefile index dcf1ed644..dec44c751 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/Makefile @@ -1,4 +1,4 @@ -ifneq ($(findstring $(BOARD), ok1028a-c), ) +ifneq ($(findstring $(BOARD), 3568), ) SRC_DIR := armv8-a endif ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), ) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/Makefile index 63aabbcc4..37af2eae1 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/Makefile @@ -1,5 +1,5 @@ -ifneq ($(findstring $(BOARD), ok1028a-c), ) -SRC_DIR := cortex-a72 +ifneq ($(findstring $(BOARD), 3568), ) +SRC_DIR := cortex-a55 endif diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a72/ok1028a-c/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a55/3568/Makefile similarity index 100% rename from Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a72/ok1028a-c/Makefile rename to Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a55/3568/Makefile diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a72/ok1028a-c/clock.c b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a55/3568/clock.c similarity index 87% rename from Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a72/ok1028a-c/clock.c rename to Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a55/3568/clock.c index 1c401bdcc..39d2995d6 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a72/ok1028a-c/clock.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a55/3568/clock.c @@ -22,27 +22,27 @@ static void enable_timer() { - uint32_t c = r_cntv_ctl_el0(); + uint32_t c = r_cntp_ctl_el0(); c |= CNTV_CTL_ENABLE; c &= ~CNTV_CTL_IMASK; - w_cntv_ctl_el0(c); + w_cntp_ctl_el0(c); } static void disable_timer() { - uint32_t c = r_cntv_ctl_el0(); + uint32_t c = r_cntp_ctl_el0(); c |= CNTV_CTL_IMASK; c &= ~CNTV_CTL_ENABLE; - w_cntv_ctl_el0(c); + w_cntp_ctl_el0(c); } static void reload_timer() { - // interval 100ms - static uint32_t ms = 10; + // interval 1ms + static uint32_t ms = 1; uint32_t interval = ms * 1000; uint32_t interval_clk = interval * (r_cntfrq_el0() / 1000000); - w_cntv_tval_el0(interval_clk); + w_cntp_tval_el0(interval_clk); } void _sys_clock_init() @@ -54,7 +54,7 @@ void _sys_clock_init() static uint32_t _get_clock_int() { - return 27; + return 30; } static uint64_t _get_tick() @@ -64,7 +64,7 @@ static uint64_t _get_tick() static uint64_t _get_second() { - return 0; + return _get_tick() / r_cntfrq_el0(); } static bool _is_timer_expired() diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a72/ok1028a-c/include/generic_timer.h b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a55/3568/include/generic_timer.h similarity index 69% rename from Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a72/ok1028a-c/include/generic_timer.h rename to Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a55/3568/include/generic_timer.h index c01e54c6c..a5d4ce6b1 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a72/ok1028a-c/include/generic_timer.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a55/3568/include/generic_timer.h @@ -15,28 +15,28 @@ #include // armv8 generic timer -static inline uint32_t r_cntv_ctl_el0() +static inline uint32_t r_cntp_ctl_el0() { uint32_t x; - __asm__ volatile("mrs %0, cntv_ctl_el0" : "=r"(x)); + __asm__ volatile("mrs %0, cntp_ctl_el0" : "=r"(x)); return x; } -static inline void w_cntv_ctl_el0(uint32_t x) +static inline void w_cntp_ctl_el0(uint32_t x) { - __asm__ volatile("msr cntv_ctl_el0, %0" : : "r"(x)); + __asm__ volatile("msr cntp_ctl_el0, %0" : : "r"(x)); } -static inline uint32_t r_cntv_tval_el0() +static inline uint32_t r_cntp_tval_el0() { uint32_t x; - __asm__ volatile("mrs %0, cntv_tval_el0" : "=r"(x)); + __asm__ volatile("mrs %0, cntp_tval_el0" : "=r"(x)); return x; } -static inline void w_cntv_tval_el0(uint32_t x) +static inline void w_cntp_tval_el0(uint32_t x) { - __asm__ volatile("msr cntv_tval_el0, %0" : : "r"(x)); + __asm__ volatile("msr cntp_tval_el0, %0" : : "r"(x)); } static inline uint64_t r_cntvct_el0() diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a72/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a55/Makefile similarity index 100% rename from Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a72/Makefile rename to Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a55/Makefile diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/hardkernel_init.c b/Ubiquitous/XiZi_AIoT/hardkernel/hardkernel_init.c index 13f6fe7ab..d2d0a6f14 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/hardkernel_init.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/hardkernel_init.c @@ -220,6 +220,7 @@ bool secondary_cpu_hardkernel_init(int cpu_id, struct TraceTag* _hardkernel_tag) p_icache_driver->enable(); p_dcache_driver->enable(); // clock + p_clock_driver->sys_clock_init(); p_intr_driver->single_irq_enable(p_clock_driver->get_clock_int(), cpu_id, 0); // mmu secondary_cpu_load_kern_pgdir(&init_mmu_tag, &init_intr_tag); diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/Makefile index dcf1ed644..dec44c751 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/Makefile @@ -1,4 +1,4 @@ -ifneq ($(findstring $(BOARD), ok1028a-c), ) +ifneq ($(findstring $(BOARD), 3568), ) SRC_DIR := armv8-a endif ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), ) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/Makefile index 63683be72..9daa7e117 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/Makefile @@ -1,3 +1,3 @@ -SRC_DIR := cortex-a72 +SRC_DIR := cortex-a55 include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/exception_registers.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/exception_registers.h similarity index 100% rename from Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/exception_registers.h rename to Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/exception_registers.h diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/irq_numbers.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/irq_numbers.h similarity index 100% rename from Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/irq_numbers.h rename to Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/irq_numbers.h diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/trap.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/trap.c similarity index 78% rename from Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/trap.c rename to Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/trap.c index 9c05f5794..194dc6f93 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/trap.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/trap.c @@ -28,13 +28,16 @@ Modification: *************************************************/ #include +#include "exception_registers.h" + #include "assert.h" #include "core.h" -#include "exception_registers.h" #include "multicores.h" #include "syscall.h" #include "task.h" +#include "mmu.h" + extern void dabort_handler(struct trapframe* r); extern void iabort_handler(struct trapframe* r); @@ -73,7 +76,6 @@ void syscall_arch_handler(struct trapframe* tf) uint64_t esr = r_esr_el1(); uint64_t ec = (esr >> 0x1A) & 0x3F; - w_esr_el1(0); switch (ec) { case 0B010101: software_irq_dispatch(tf); @@ -87,11 +89,30 @@ void syscall_arch_handler(struct trapframe* tf) iabort_handler(tf); break; default: { - ERROR("USYSCALL: unexpected ec: %016lx", esr); + ERROR("USYSCALL: unexpected\n"); + ERROR(" esr: %016lx\n", esr); ERROR(" elr = %016lx far = %016lx\n", r_elr_el1(), r_far_el1()); + w_esr_el1(0); + extern void dump_tf(struct trapframe * tf); + dump_tf(tf); + + uint32_t sctlr = 0; + SCTLR_R(sctlr); + DEBUG("SCTLR: %x\n", sctlr); + uint32_t spsr = 0; + __asm__ volatile("mrs %0, spsr_el1" : "=r"(spsr)::"memory"); + DEBUG("SPSR: %x\n", spsr); + uint64_t tcr = 0; + __asm__ volatile("mrs %0, tcr_el1" : "=r"(tcr)::"memory"); + DEBUG("TCR: %x\n", tcr); + uint64_t mair = 0; + __asm__ volatile("mrs %0, mair_el1" : "=r"(mair)::"memory"); + DEBUG("MAIR: %x\n", mair); + // kill error task xizi_enter_kernel(); assert(cur_cpu()->task != NULL); + ERROR("Error Task: %s\n", cur_cpu()->task->name); sys_exit(cur_cpu()->task); context_switch(&cur_cpu()->task->thread_context.context, cur_cpu()->scheduler); panic("dabort end should never be reashed.\n"); diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/trap_common.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/trap_common.c similarity index 99% rename from Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/trap_common.c rename to Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/trap_common.c index 328634f27..354e2d2ee 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/trap_common.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/trap_common.c @@ -29,7 +29,7 @@ Modification: #include #include "core.h" -#include "cortex_a72.h" +#include "cortex_a55.h" #include "exception_registers.h" #include "gicv3_common_opa.h" #include "trap_common.h" diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/Makefile similarity index 70% rename from Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/Makefile rename to Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/Makefile index 016576eed..ca24fcc00 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/Makefile @@ -1,6 +1,6 @@ SRC_FILES := trampoline.S $(BOARD)/trap_common.c $(BOARD)/trap.c error_debug.c hard_spinlock.S -ifeq ($(BOARD), ok1028a-c) +ifeq ($(BOARD), 3568) SRC_DIR := gicv3 SRC_FILES += $(BOARD)/ endif diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/error_debug.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/error_debug.c similarity index 74% rename from Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/error_debug.c rename to Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/error_debug.c index f32c42814..53b2f0eb0 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/error_debug.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/error_debug.c @@ -39,51 +39,53 @@ Modification: 2. Modify iabort and dabort handler(in dabort_handler() and iabort_handler()) *************************************************/ #include +#include + +#include "exception_registers.h" #include "assert.h" #include "core.h" #include "log.h" #include "multicores.h" -#include "spinlock.h" #include "task.h" #include "trap_common.h" void dump_tf(struct trapframe* tf) { - KPrintf(" sp: 0x%x\n", tf->sp); - KPrintf(" pc: 0x%x\n", tf->pc); - KPrintf(" spsr: 0x%x\n", tf->spsr); - KPrintf(" x0: 0x%x\n", tf->x0); - KPrintf(" x1: 0x%x\n", tf->x1); - KPrintf(" x2: 0x%x\n", tf->x2); - KPrintf(" x3: 0x%x\n", tf->x3); - KPrintf(" x4: 0x%x\n", tf->x4); - KPrintf(" x5: 0x%x\n", tf->x5); - KPrintf(" x6: 0x%x\n", tf->x6); - KPrintf(" x7: 0x%x\n", tf->x7); - KPrintf(" x8: 0x%x\n", tf->x8); - KPrintf(" x9: 0x%x\n", tf->x9); - KPrintf(" x10: 0x%x\n", tf->x10); - KPrintf(" x11: 0x%x\n", tf->x11); - KPrintf(" x12: 0x%x\n", tf->x12); - KPrintf(" x13: 0x%x\n", tf->x13); - KPrintf(" x14: 0x%x\n", tf->x14); - KPrintf(" x15: 0x%x\n", tf->x15); - KPrintf(" x16: 0x%x\n", tf->x16); - KPrintf(" x17: 0x%x\n", tf->x17); - KPrintf(" x18: 0x%x\n", tf->x18); - KPrintf(" x19: 0x%x\n", tf->x19); - KPrintf(" x20: 0x%x\n", tf->x20); - KPrintf(" x21: 0x%x\n", tf->x21); - KPrintf(" x22: 0x%x\n", tf->x22); - KPrintf(" x23: 0x%x\n", tf->x23); - KPrintf(" x24: 0x%x\n", tf->x24); - KPrintf(" x25: 0x%x\n", tf->x25); - KPrintf(" x26: 0x%x\n", tf->x26); - KPrintf(" x27: 0x%x\n", tf->x27); - KPrintf(" x28: 0x%x\n", tf->x28); - KPrintf(" x29: 0x%x\n", tf->x29); - KPrintf(" x30: 0x%x\n", tf->x30); + KPrintf(" sp: 0x%016lx\n", tf->sp); + KPrintf(" pc: 0x%016lx\n", tf->pc); + KPrintf(" spsr: 0x%016lx\n", tf->spsr); + KPrintf(" x0: 0x%016lx\n", tf->x0); + KPrintf(" x1: 0x%016lx\n", tf->x1); + KPrintf(" x2: 0x%016lx\n", tf->x2); + KPrintf(" x3: 0x%016lx\n", tf->x3); + KPrintf(" x4: 0x%016lx\n", tf->x4); + KPrintf(" x5: 0x%016lx\n", tf->x5); + KPrintf(" x6: 0x%016lx\n", tf->x6); + KPrintf(" x7: 0x%016lx\n", tf->x7); + KPrintf(" x8: 0x%016lx\n", tf->x8); + KPrintf(" x9: 0x%016lx\n", tf->x9); + KPrintf(" x10: 0x%016lx\n", tf->x10); + KPrintf(" x11: 0x%016lx\n", tf->x11); + KPrintf(" x12: 0x%016lx\n", tf->x12); + KPrintf(" x13: 0x%016lx\n", tf->x13); + KPrintf(" x14: 0x%016lx\n", tf->x14); + KPrintf(" x15: 0x%016lx\n", tf->x15); + KPrintf(" x16: 0x%016lx\n", tf->x16); + KPrintf(" x17: 0x%016lx\n", tf->x17); + KPrintf(" x18: 0x%016lx\n", tf->x18); + KPrintf(" x19: 0x%016lx\n", tf->x19); + KPrintf(" x20: 0x%016lx\n", tf->x20); + KPrintf(" x21: 0x%016lx\n", tf->x21); + KPrintf(" x22: 0x%016lx\n", tf->x22); + KPrintf(" x23: 0x%016lx\n", tf->x23); + KPrintf(" x24: 0x%016lx\n", tf->x24); + KPrintf(" x25: 0x%016lx\n", tf->x25); + KPrintf(" x26: 0x%016lx\n", tf->x26); + KPrintf(" x27: 0x%016lx\n", tf->x27); + KPrintf(" x28: 0x%016lx\n", tf->x28); + KPrintf(" x29: 0x%016lx\n", tf->x29); + KPrintf(" x30: 0x%016lx\n", tf->x30); } void dabort_reason(struct trapframe* r) @@ -91,8 +93,9 @@ void dabort_reason(struct trapframe* r) uint32_t fault_status, fault_address; __asm__ __volatile__("mrs %0, esr_el1" : "=r"(fault_status)); __asm__ __volatile__("mrs %0, far_el1" : "=r"(fault_address)); - LOG("program counter: 0x%x caused\n", r->pc); - LOG("data abort at 0x%x, status 0x%x\n", fault_address, fault_status); + w_esr_el1(0); + LOG("program counter: 0x%016lx caused\n", r->pc); + LOG("data abort at 0x%016lx, status 0x%016lx\n", fault_address, fault_status); if ((fault_status & 0x3f) == 0x21) // Alignment failure KPrintf("reason: alignment\n"); else if ((fault_status & 0x3f) == 0x4) // Translation fault, level 0 @@ -131,8 +134,9 @@ void iabort_reason(struct trapframe* r) uint32_t fault_status, fault_address; __asm__ __volatile__("mrs %0, esr_el1" : "=r"(fault_status)); __asm__ __volatile__("mrs %0, far_el1" : "=r"(fault_address)); - LOG("program counter: 0x%x caused\n", r->pc); - LOG("data abort at 0x%x, status 0x%x\n", fault_address, fault_status); + LOG("program counter: 0x%016lx caused\n", r->pc); + LOG("data abort at 0x%016lx, status 0x%016lx\n", fault_address, fault_status); + w_esr_el1(0); if ((fault_status & 0x3f) == 0x21) // Alignment failure KPrintf("reason: alignment\n"); else if ((fault_status & 0x3f) == 0x4) // Translation fault, level 0 diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/gicv3/Makefile similarity index 100% rename from Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/Makefile rename to Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/gicv3/Makefile diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/gicv3.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/gicv3/gicv3.c similarity index 100% rename from Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/gicv3.c rename to Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/gicv3/gicv3.c diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/gicv3_common_opa.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/gicv3/gicv3_common_opa.h similarity index 100% rename from Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/gicv3_common_opa.h rename to Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/gicv3/gicv3_common_opa.h diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/gicv3_registers.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/gicv3/gicv3_registers.h similarity index 93% rename from Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/gicv3_registers.h rename to Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/gicv3/gicv3_registers.h index eb89191b4..389d6a5b1 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/gicv3_registers.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/gicv3/gicv3_registers.h @@ -30,8 +30,8 @@ Modification: // clang-format off // interrupt controller GICv3 -#define GICV3 MMIO_P2V_WO(0x08000000ULL) -#define GICV3_REDIST MMIO_P2V_WO(0x080a0000ULL) +#define GICV3 MMIO_P2V_WO(0xFD400000ULL) +#define GICV3_REDIST MMIO_P2V_WO(0xFD460000ULL) #define D_CTLR 0x0 #define D_TYPER 0x4 diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/hard_spinlock.S b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/hard_spinlock.S similarity index 63% rename from Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/hard_spinlock.S rename to Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/hard_spinlock.S index 1f568e62c..94c30939c 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/hard_spinlock.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/hard_spinlock.S @@ -55,62 +55,56 @@ Modification: #define UNLOCKED 0xFF // int spinlock_lock(spinlock_t * lock, uint64_t timeout) .global _spinlock_lock - .func _spinlock_lock +.func _spinlock_lock _spinlock_lock: -mov w2, #1 + mov w2, #1 + sevl +1: + wfe -sevl -wfe +2: + ldaxrb w1, [x0] // check if the spinlock is currently unlocked + cmp w1, #UNLOCKED + bne 1b -ldaxrb w1, [x0] // check if the spinlock is currently unlocked -cmp w1, #UNLOCKED -bne _spinlock_lock + mrs x1, mpidr_el1 // get our CPU ID + and x1, x1, #0xFFF + lsr x1, x1, #8 + stxrb w2, w1, [x0] + cmp x2, #0 + bne 2b // check if the write was successful, if the write failed, start over -mrs x1, mpidr_el1 // get our CPU ID -and x1, x1, #3 -stxrb w2, w1, [x0] -cmp x2, #0 -bne _spinlock_lock // check if the write was successful, if the write failed, start over + dmb ish // Ensure that accesses to shared resource have completed -dmb ish // Ensure that accesses to shared resource have completed - -mov x0, #0 -ret - - .endfunc + mov x0, #0 + ret +.endfunc // void spinlock_unlock(spinlock_t * lock) .global _spinlock_unlock .func _spinlock_unlock _spinlock_unlock: + mrs x1, mpidr_el1 // get our CPU ID + and x1, x1, #0xFFF + lsr x1, x1, #8 -mrs x1, mpidr_el1 // get our CPU ID -and x1, x1, #3 + ldr w2, [x0] + cmp w1, w2 + bne 1f //doesn't match,jump to 1 -ldr w2, [x0] -cmp w1, w2 -bne 1f //doesn't match,jump to 1 - - -dmb ish - -mov w1, #UNLOCKED -str w1, [x0] - -dsb ish //Ensure that no instructions following the barrier execute until - // all memory accesses prior to the barrier have completed. - - -sevl // send event to wake up other cores waiting on spinlock - -mov x0, #0 // return success -ret + dmb ish + mov w1, #UNLOCKED + str w1, [x0] + dsb ish //Ensure that no instructions following the barrier execute until + // all memory accesses prior to the barrier have completed. + sevl // send event to wake up other cores waiting on spinlock + mov x0, #0 // return success + ret 1: -mov x0, #1 //doesn't match, so exit with failure -ret - + mov x0, #1 //doesn't match, so exit with failure + ret .endfunc .end diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/trampoline.S b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/trampoline.S similarity index 95% rename from Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/trampoline.S rename to Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/trampoline.S index c365de082..82b11c0c7 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/trampoline.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/trampoline.S @@ -143,13 +143,13 @@ Modification: .balign 0x800 alltraps: // Current EL with sp0 - b . + b badtrap .balign 0x80 - b . + b badtrap .balign 0x80 - b . + b badtrap .balign 0x80 - b . + b badtrap // Current EL with spx .balign 0x80 @@ -157,9 +157,9 @@ alltraps: .balign 0x80 b el1irq .balign 0x80 - b . + b badtrap .balign 0x80 - b . + b badtrap // Lower EL using aarch64 .balign 0x80 @@ -167,32 +167,34 @@ alltraps: .balign 0x80 b el0irq .balign 0x80 - b . + b badtrap .balign 0x80 - b . + b badtrap // Lower EL using aarch32 .balign 0x80 - b . + b badtrap .balign 0x80 - b . + b badtrap .balign 0x80 - b . + b badtrap .balign 0x80 - b . + b badtrap + +badtrap: + savereg + mov x0, sp + bl kernel_intr_handler + b . el1sync: - msr daifset, #0xf savereg - mov x0, sp bl kernel_abort_handler b . el1irq: - msr daifset, #0xf usavereg - mov x0, sp bl intr_irq_dispatch @@ -201,9 +203,7 @@ el1irq: eret el0sync: - msr daifset, #0xf usavereg - mov x0, sp bl syscall_arch_handler @@ -212,9 +212,7 @@ el0sync: eret el0irq: - msr daifset, #0xf usavereg - mov x0, sp bl intr_irq_dispatch diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/spinlock.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/spinlock.c index 0f2e09764..1153e5c78 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/spinlock.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/spinlock.c @@ -59,7 +59,7 @@ __attribute__((optimize("O0"))) void spinlock_init(struct spinlock* lock, char* } extern int _spinlock_lock(struct spinlock* lock, uint32_t timeout); -extern void _spinlock_unlock(struct spinlock* lock); +extern int _spinlock_unlock(struct spinlock* lock); __attribute__((optimize("O0"))) void spinlock_lock(struct spinlock* lock) { @@ -88,7 +88,9 @@ __attribute__((optimize("O0"))) void spinlock_unlock(struct spinlock* lock) _double_list_del(p_lock_node->prev, p_lock_node->next); _spinlock_unlock(&request_lock); - _spinlock_unlock(lock); + if (_spinlock_unlock(lock) != 0) { + ERROR("Core %d trying to unlock a lock belongs to %d.\n", cur_cpuid(), lock->owner_cpu); + } } __attribute__((optimize("O0"))) bool spinlock_try_lock(struct spinlock* lock) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/Makefile index ba7b06cc4..ea7da0fa1 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/Makefile @@ -1,4 +1,4 @@ -ifneq ($(findstring $(BOARD), ok1028a-c), ) +ifneq ($(findstring $(BOARD), 3568), ) SRC_DIR := armv8-a endif ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), ) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/bootmmu.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/bootmmu.c index bc5b48a2c..dd89b959a 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/bootmmu.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/bootmmu.c @@ -48,7 +48,7 @@ uint32_t boot_pgdir[NR_PDE_ENTRIES] __attribute__((aligned(0x4000))) = { 0 }; static void build_boot_pgdir() { // dev mem - uint32_t dev_mem_end_idx = (DEV_PHYMEM_BASE + DEV_MEM_SZ) >> LEVEL3_PDE_SHIFT; + uint32_t dev_mem_end_idx = (DEV_PHYMEM_BASE + DEV_MEM_SIZE) >> LEVEL3_PDE_SHIFT; for (uint32_t i = DEV_PHYMEM_BASE >> LEVEL3_PDE_SHIFT; i < dev_mem_end_idx; i++) { boot_pgdir[i] = (i << LEVEL3_PDE_SHIFT) | L1_TYPE_SEC | L1_SECT_DEV | L1_SECT_AP0; boot_pgdir[MMIO_P2V_WO(i << LEVEL3_PDE_SHIFT) >> LEVEL3_PDE_SHIFT] = (i << LEVEL3_PDE_SHIFT) | L1_TYPE_SEC | L1_SECT_DEV | L1_SECT_AP0; diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/imx6q-sabrelite/memlayout.h b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/imx6q-sabrelite/memlayout.h index 3d7969f92..0a31e0241 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/imx6q-sabrelite/memlayout.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/imx6q-sabrelite/memlayout.h @@ -67,7 +67,7 @@ Modification: /* Deivce memory layout */ #define DEV_PHYMEM_BASE (0x00000000) #define DEV_VRTMEM_BASE (0x80000000) -#define DEV_MEM_SZ (0x10000000) +#define DEV_MEM_SIZE (0x10000000) /* Kernel memory layout */ #define KERN_MEM_BASE (0x90000000) // First kernel virtual address diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/zynq7000-zc702/memlayout.h b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/zynq7000-zc702/memlayout.h index cf480c399..099fd1487 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/zynq7000-zc702/memlayout.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/zynq7000-zc702/memlayout.h @@ -66,7 +66,7 @@ Modification: /* Deivce memory layout */ #define DEV_PHYMEM_BASE (0xE0000000) #define DEV_VRTMEM_BASE (0x80000000) -#define DEV_MEM_SZ (0x1FFFFFFF) +#define DEV_MEM_SIZE (0x1FFFFFFF) /* Kernel memory layout */ #define KERN_MEM_BASE (0xA0000000) // First kernel virtual address diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/Makefile index 7a9b17009..b2a497f23 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/Makefile @@ -1,3 +1,3 @@ -SRC_DIR := cortex-a72 +SRC_DIR := cortex-a55 include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/ok1028a-c/memlayout.h b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/3568/memlayout.h similarity index 78% rename from Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/ok1028a-c/memlayout.h rename to Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/3568/memlayout.h index b916887dd..ef7e8ef24 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/ok1028a-c/memlayout.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/3568/memlayout.h @@ -33,11 +33,11 @@ Modification: #define ARCH_BIT 64 -/* A72 physical memory layout */ -#define PHY_MEM_BASE (0x0000000040000000ULL) -#define PHY_USER_FREEMEM_BASE (0x0000000046000000ULL) -#define PHY_USER_FREEMEM_TOP (0x0000000048000000ULL) -#define PHY_MEM_STOP (0x0000000048000000ULL) +/* A55 physical memory layout */ +#define PHY_MEM_BASE (0x0000000010000000ULL) +#define PHY_USER_FREEMEM_BASE (0x0000000040000000ULL) +#define PHY_USER_FREEMEM_TOP (0x00000000e0000000ULL) +#define PHY_MEM_STOP (0x00000000e0000000ULL) /* PTE-PAGE_SIZE */ #define LEVEL4_PTE_SHIFT 12 @@ -58,23 +58,23 @@ Modification: #define NUM_TOPLEVEL_PDE NUM_LEVEL2_PDE #define PAGE_SIZE LEVEL4_PTE_SIZE -#define MAX_NR_FREE_PAGES ((PHY_MEM_STOP - PHY_MEM_BASE) >> LEVEL4_PTE_SHIFT) +#define MAX_NR_FREE_PAGES ((PHY_USER_FREEMEM_BASE - PHY_MEM_BASE) >> LEVEL4_PTE_SHIFT) /* Deivce memory layout */ -#define DEV_PHYMEM_BASE (0x0000000000000000ULL) -#define DEV_VRTMEM_BASE (0x0000004000000000ULL) -#define DEV_MEM_SZ (0x0000000010000000ULL) +#define DEV_PHYMEM_BASE (0x00000000F0000000ULL) +#define DEV_VRTMEM_BASE (0x00000040F0000000ULL) +#define DEV_MEM_SIZE (0x0000000010000000ULL) /* User memory layout */ #define USER_STACK_SIZE PAGE_SIZE #define USER_MEM_BASE (0x0000000000000000ULL) -#define USER_MEM_TOP DEV_VRTMEM_BASE +#define USER_MEM_TOP (0x0000004000000000ULL) #define USER_IPC_SPACE_BASE (0x0000003000000000ULL) #define USER_IPC_USE_ALLOCATOR_WATERMARK (0x0000003000010000ULL) #define USER_IPC_SPACE_TOP (USER_IPC_SPACE_BASE + 0x10000000ULL) /* Kernel memory layout */ -#define KERN_MEM_BASE (0x0000006040000000ULL) // First kernel virtual address +#define KERN_MEM_BASE (0x0000006010000000ULL) // First kernel virtual address #define KERN_OFFSET (KERN_MEM_BASE - PHY_MEM_BASE) #define V2P(a) (((uint64_t)(a)) - KERN_OFFSET) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/Makefile similarity index 100% rename from Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/Makefile rename to Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/Makefile diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/bootmmu.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/bootmmu.c similarity index 53% rename from Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/bootmmu.c rename to Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/bootmmu.c index b01be9923..47a37d422 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/bootmmu.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/bootmmu.c @@ -51,9 +51,9 @@ extern uint64_t kernel_data_begin[]; #define L4_PTE_NORMAL ((0b01) << 2) // Device memory #define L4_PTE_AF (1 << 10) // Data Access Permissions -#define L4_PTE_PXN (1UL << 53) // Privileged eXecute Never -#define L4_PTE_UXN (1UL << 54) // Unprivileged(user) eXecute Never -#define L4_PTE_XN (PTE_PXN|PTE_UXN) // eXecute Never +#define L4_PTE_PXN (1UL << 53) // Privileged eXecute Never +#define L4_PTE_UXN (1UL << 54) // Unprivileged(user) eXecute Never +#define L4_PTE_XN (PTE_PXN|PTE_UXN) // eXecute Never #define IDX_MASK (0b111111111) #define L3_PDE_INDEX(idx) ((idx << LEVEL3_PDE_SHIFT) & L3_IDX_MASK) @@ -62,64 +62,69 @@ extern uint64_t kernel_data_begin[]; uint64_t boot_l2pgdir[NUM_LEVEL2_PDE] __attribute__((aligned(0x1000))) = { 0 }; uint64_t boot_dev_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 }; -uint64_t boot_virt_dev_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 }; uint64_t boot_kern_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 }; -uint64_t boot_virt_kern_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 }; uint64_t boot_dev_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 }; uint64_t boot_kern_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 }; static void build_boot_pgdir() { - uint64_t dev_phy_mem_base = DEV_PHYMEM_BASE; - // dev mem - boot_l2pgdir[(dev_phy_mem_base >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID; - boot_l2pgdir[(MMIO_P2V_WO(dev_phy_mem_base) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID; + static bool built = false; + if (!built) { + uint64_t dev_phy_mem_base = DEV_PHYMEM_BASE; - uint64_t cur_mem_paddr = ALIGNDOWN((uint64_t)DEV_PHYMEM_BASE, PAGE_SIZE); - for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) { - boot_dev_l3pgdir[i] = (uint64_t)boot_dev_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID; + // dev mem + boot_l2pgdir[(dev_phy_mem_base >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID; + boot_l2pgdir[(MMIO_P2V_WO(dev_phy_mem_base) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID; - for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) { - boot_dev_l4pgdirs[i][j] = cur_mem_paddr | L4_TYPE_PAGE | L4_PTE_DEV | L4_PTE_AF | L4_PTE_XN; + uint64_t cur_mem_paddr = ALIGNDOWN((uint64_t)DEV_PHYMEM_BASE, LEVEL2_PDE_SIZE); + for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) { + boot_dev_l3pgdir[i] = (uint64_t)boot_dev_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID; - cur_mem_paddr += PAGE_SIZE; + for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) { + boot_dev_l4pgdirs[i][j] = cur_mem_paddr | L4_TYPE_PAGE | L4_PTE_DEV | L4_PTE_AF | L4_PTE_XN; + if (cur_mem_paddr >= DEV_PHYMEM_BASE && cur_mem_paddr < DEV_PHYMEM_BASE + DEV_MEM_SIZE) { + boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x403; + } else { + boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x403; + } + + cur_mem_paddr += PAGE_SIZE; + } } - } - // identical mem - boot_l2pgdir[(PHY_MEM_BASE >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID; - boot_l2pgdir[(P2V_WO(PHY_MEM_BASE) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID; + // identical mem + boot_l2pgdir[(PHY_MEM_BASE >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID; + boot_l2pgdir[(P2V_WO(PHY_MEM_BASE) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID; - cur_mem_paddr = ALIGNDOWN((uint64_t)PHY_MEM_BASE, PAGE_SIZE); - for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) { - boot_kern_l3pgdir[i] = (uint64_t)boot_kern_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID; + cur_mem_paddr = ALIGNDOWN((uint64_t)0x00000000ULL, PAGE_SIZE); + for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) { + boot_kern_l3pgdir[i] = (uint64_t)boot_kern_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID; - for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) { - boot_kern_l4pgdirs[i][j] = cur_mem_paddr | L4_TYPE_PAGE | L4_PTE_NORMAL | L4_PTE_AF; + for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) { + boot_kern_l4pgdirs[i][j] = cur_mem_paddr | 0x713; - cur_mem_paddr += PAGE_SIZE; + cur_mem_paddr += PAGE_SIZE; + } } + + built = true; } } static void load_boot_pgdir() { - uint64_t val; TTBR0_W((uintptr_t)boot_l2pgdir); TTBR1_W(0); - TCR_W(TCR_VALUE); - MAIR_W((MT_DEVICE_nGnRnE << (8 * AI_DEVICE_nGnRnE_IDX)) | (MT_NORMAL_NC << (8 * AI_NORMAL_NC_IDX))); +#define TCR_TRUE_VALUE (0x0000000080813519ULL) + uint64_t tcr = 0; + TCR_R(tcr); + tcr &= (uint64_t)~0xFF; + tcr |= 0x19; + TCR_W(tcr); - // Enable paging using read/modify/write - SCTLR_R(val); - val |= (1 << 0); // EL1 and EL0 stage 1 address translation enabled. - SCTLR_W(val); - - // flush all TLB - DSB(); CLEARTLB(0); ISB(); } @@ -130,7 +135,7 @@ void bootmain() { build_boot_pgdir(); load_boot_pgdir(); - __asm__ __volatile__("add sp, sp, %0" ::"r"(KERN_MEM_BASE - PHY_MEM_BASE)); + __asm__ __volatile__("add sp, sp, %0" ::"r"(KERN_OFFSET)); if (!_bss_inited) { memset(&kernel_data_begin, 0x00, (size_t)((uint64_t)kernel_data_end - (uint64_t)kernel_data_begin)); _bss_inited = true; diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/include/mmu.h b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/include/mmu.h similarity index 91% rename from Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/include/mmu.h rename to Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/include/mmu.h index e68042bc1..aaec82a3c 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/include/mmu.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/include/mmu.h @@ -61,35 +61,36 @@ void GetPdeAttr(uintptr_t* attr); /* Enable MMU, cache, write buffer, etc. */ -#define SCTLR_R(val) __asm__ volatile("mrs %0, sctlr_el1" : "=r"(val)) -#define SCTLR_W(val) __asm__ volatile("msr sctlr_el1, %0" ::"r"(val)) +#define SCTLR_R(val) __asm__ volatile("mrs %0, sctlr_el1" : "=r"(val)::"memory") +#define SCTLR_W(val) __asm__ volatile("msr sctlr_el1, %0" ::"r"(val) : "memory") /* Read and write mmu pagetable register base addr */ -#define TTBR0_R(val) __asm__ volatile("mrs %0, ttbr0_el1" : "=r"(val)) -#define TTBR0_W(val) __asm__ volatile("msr ttbr0_el1, %0" ::"r"(val)) +#define TTBR0_R(val) __asm__ volatile("mrs %0, ttbr0_el1" : "=r"(val)::"memory") +#define TTBR0_W(val) __asm__ volatile("msr ttbr0_el1, %0" ::"r"(val) : "memory") /* Read and write mmu pagetable register base addr */ -#define TTBR1_R(val) __asm__ volatile("mrs %0, ttbr1_el1" : "=r"(val)) -#define TTBR1_W(val) __asm__ volatile("msr ttbr1_el1, %0" ::"r"(val)) +#define TTBR1_R(val) __asm__ volatile("mrs %0, ttbr1_el1" : "=r"(val)::"memory") +#define TTBR1_W(val) __asm__ volatile("msr ttbr1_el1, %0" ::"r"(val) : "memory") /* Translation Control Register（TCR） */ -#define TCR_R(val) __asm__ volatile("mrs %0, tcr_el1" : "=r"(val)) -#define TCR_W(val) __asm__ volatile("msr tcr_el1, %0" ::"r"(val)) +#define TCR_R(val) __asm__ volatile("mrs %0, tcr_el1" : "=r"(val)::"memory") +#define TCR_W(val) __asm__ volatile("msr tcr_el1, %0" ::"r"(val) : "memory") -#define MAIR_R(val) __asm__ volatile("mrs %0, mair_el1" : "=r"(val)) -#define MAIR_W(val) __asm__ volatile("msr mair_el1, %0" ::"r"(val)) +#define MAIR_R(val) __asm__ volatile("mrs %0, mair_el1" : "=r"(val)::"memory") +#define MAIR_W(val) __asm__ volatile("msr mair_el1, %0" ::"r"(val) : "memory") /* Flush TLB when loading a new page table. @note If nG is not set in the pte attribute, process switching need flush tlb. */ -#define CLEARTLB(val) __asm__ volatile("tlbi vmalle1") +// #define CLEARTLB(val) __asm__ volatile("tlbi vmalle1" ::: "memory") +#define CLEARTLB(val) __asm__ volatile("tlbi vmalle1is" ::: "memory") /* When nG is set in the pte attribute, the process is assigned an ASID, which is stored in the lower 8 bits of the CONTEXTIDR register. diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/mmu.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/mmu.c similarity index 99% rename from Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/mmu.c rename to Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/mmu.c index 336d074e6..6067c4dc9 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/mmu.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/mmu.c @@ -45,7 +45,9 @@ void load_pgdir(uintptr_t pgdir_paddr) struct DCacheDone* p_dcache_done = AchieveResource(&right_group.dcache_driver_tag); TTBR0_W((uint64_t)pgdir_paddr); + DSB(); CLEARTLB(0); + ISB(); p_icache_done->invalidateall(); p_dcache_done->flushall(); } diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/pagetable_attr.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/pagetable_attr.c similarity index 78% rename from Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/pagetable_attr.c rename to Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/pagetable_attr.c index 18c065897..8085ad036 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/pagetable_attr.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/pagetable_attr.c @@ -52,22 +52,26 @@ Modification: void GetUsrPteAttr(uintptr_t* attr) { - *attr = ARMV8_PTE_AP_U | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_NORMAL | ARMV8_PTE_VALID; + // *attr = ARMV8_PTE_AP_U | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_NORMAL | ARMV8_PTE_VALID; + *attr = 0x713 | ARMV8_PTE_AP_U; } void GetUsrDevPteAttr(uintptr_t* attr) { - *attr = ARMV8_PTE_AP_U | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_DEVICE | ARMV8_PTE_XN | ARMV8_PTE_VALID; + // *attr = ARMV8_PTE_AP_U | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_DEVICE | ARMV8_PTE_XN | ARMV8_PTE_VALID; + *attr = 0x403 | ARMV8_PTE_AP_U; } void GetDevPteAttr(uintptr_t* attr) { - *attr = ARMV8_PTE_AP_K | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_DEVICE | ARMV8_PTE_XN | ARMV8_PTE_VALID; + // *attr = ARMV8_PTE_AP_K | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_DEVICE | ARMV8_PTE_XN | ARMV8_PTE_VALID; + *attr = 0x403ULL; } void GetKernPteAttr(uintptr_t* attr) { - *attr = ARMV8_PTE_AP_K | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_NORMAL | ARMV8_PTE_VALID; + // *attr = ARMV8_PTE_AP_K | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_NORMAL | ARMV8_PTE_VALID; + *attr = 0x713ULL; } void GetPdeAttr(uintptr_t* attr) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/Makefile index 05e53ecfe..8f7703c39 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/Makefile @@ -1,5 +1,5 @@ # The following three platforms support compatiable instructions. -ifneq ($(findstring $(BOARD), ok1028a-c), ) +ifneq ($(findstring $(BOARD), 3568), ) SRC_DIR := armv8-a endif ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), ) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/Makefile index 9d15ca4c3..0597d0d36 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/Makefile @@ -1,4 +1,4 @@ # The following three platforms support compatiable instructions. -SRC_DIR := cortex-a72 +SRC_DIR := cortex-a55 include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/Makefile similarity index 100% rename from Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/Makefile rename to Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/Makefile diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_3568/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_3568/Makefile new file mode 100644 index 000000000..a8661f85c --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_3568/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := uart.c ns16550.c + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_3568/include/ns16550.h b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_3568/include/ns16550.h new file mode 100644 index 000000000..8847befca --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_3568/include/ns16550.h @@ -0,0 +1,198 @@ +/* + * NS16550 Serial Port + * originally from linux source (arch/powerpc/boot/ns16550.h) + * + * Cleanup and unification + * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH + * + * modified slightly to + * have addresses as offsets from CONFIG_SYS_ISA_BASE + * added a few more definitions + * added prototypes for ns16550.c + * reduced no of com ports to 2 + * modifications (c) Rob Taylor, Flying Pig Systems. 2000. + * + * added support for port on 64-bit bus + * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems + */ + +/* + * Note that the following macro magic uses the fact that the compiler + * will not allocate storage for arrays of size 0 + */ + +#include + +/* + * For driver model we always use one byte per register, and sort out the + * differences in the driver + */ +#define CONFIG_SYS_NS16550_REG_SIZE (-1) + +#define UART_REG(x) \ + unsigned char x; \ + unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; + +/** + * struct ns16550_platdata - information about a NS16550 port + * + * @base: Base register address + * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...) + * @clock: UART base clock speed in Hz + */ +struct ns16550_platdata { + unsigned long base; + int reg_shift; + int clock; + int reg_offset; + uint32_t fcr; +}; + +struct udevice; + +struct NS16550 { + UART_REG(rbr); /* 0 */ + UART_REG(ier); /* 1 */ + UART_REG(fcr); /* 2 */ + UART_REG(lcr); /* 3 */ + UART_REG(mcr); /* 4 */ + UART_REG(lsr); /* 5 */ + UART_REG(msr); /* 6 */ + UART_REG(spr); /* 7 */ +#ifdef CONFIG_SOC_DA8XX + UART_REG(reg8); /* 8 */ + UART_REG(reg9); /* 9 */ + UART_REG(revid1); /* A */ + UART_REG(revid2); /* B */ + UART_REG(pwr_mgmt); /* C */ + UART_REG(mdr1); /* D */ +#else + UART_REG(mdr1); /* 8 */ + UART_REG(reg9); /* 9 */ + UART_REG(regA); /* A */ + UART_REG(regB); /* B */ + UART_REG(regC); /* C */ + UART_REG(regD); /* D */ + UART_REG(regE); /* E */ + UART_REG(uasr); /* F */ + UART_REG(scr); /* 10*/ + UART_REG(ssr); /* 11*/ +#endif +#ifdef CONFIG_DM_SERIAL + struct ns16550_platdata* plat; +#endif +}; + +#define thr rbr +#define iir fcr +#define dll rbr +#define dlm ier + +typedef struct NS16550* NS16550_t; + +/* + * These are the definitions for the FIFO Control Register + */ +#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ + +#define UART_FCR_RXSR 0x02 /* Receiver soft reset */ +#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ + +/* Ingenic JZ47xx specific UART-enable bit. */ +#define UART_FCR_UME 0x10 + +/* Clear & enable FIFOs */ +#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR) + +/* + * These are the definitions for the Modem Control Register + */ +#define UART_MCR_DTR 0x01 /* DTR */ +#define UART_MCR_RTS 0x02 /* RTS */ +#define UART_MCR_OUT1 0x04 /* Out 1 */ +#define UART_MCR_OUT2 0x08 /* Out 2 */ +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */ + +#define UART_MCR_DMA_EN 0x04 +#define UART_MCR_TX_DFR 0x08 + +/* + * These are the definitions for the Line Control Register + * + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting + * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. + */ +#define UART_LCR_WLS_MSK 0x03 /* character length select mask */ +#define UART_LCR_WLS_5 0x00 /* 5 bit character length */ +#define UART_LCR_WLS_6 0x01 /* 6 bit character length */ +#define UART_LCR_WLS_7 0x02 /* 7 bit character length */ +#define UART_LCR_WLS_8 0x03 /* 8 bit character length */ +#define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */ +#define UART_LCR_PEN 0x08 /* Parity eneble */ +#define UART_LCR_EPS 0x10 /* Even Parity Select */ +#define UART_LCR_STKP 0x20 /* Stick Parity */ +#define UART_LCR_SBRK 0x40 /* Set Break */ +#define UART_LCR_BKSE 0x80 /* Bank select enable */ +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ + +/* + * These are the definitions for the Line Status Register + */ +#define UART_LSR_DR 0x01 /* Data ready */ +#define UART_LSR_OE 0x02 /* Overrun */ +#define UART_LSR_PE 0x04 /* Parity error */ +#define UART_LSR_FE 0x08 /* Framing error */ +#define UART_LSR_BI 0x10 /* Break */ +#define UART_LSR_THRE 0x20 /* Xmit holding register empty */ +#define UART_LSR_TEMT 0x40 /* Xmitter empty */ +#define UART_LSR_ERR 0x80 /* Error */ + +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ +#define UART_MSR_RI 0x40 /* Ring Indicator */ +#define UART_MSR_DSR 0x20 /* Data Set Ready */ +#define UART_MSR_CTS 0x10 /* Clear to Send */ +#define UART_MSR_DDCD 0x08 /* Delta DCD */ +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ +#define UART_MSR_DDSR 0x02 /* Delta DSR */ +#define UART_MSR_DCTS 0x01 /* Delta CTS */ + +/* + * These are the definitions for the Interrupt Identification Register + */ +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ + +#define UART_IIR_MSI 0x00 /* Modem status interrupt */ +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ + +/* + * These are the definitions for the Interrupt Enable Register + */ +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ + +/* useful defaults for LCR */ +#define UART_LCR_8N1 0x03 + +void NS16550_init(NS16550_t com_port, int baud_divisor); +void NS16550_putc(NS16550_t com_port, char c); +char NS16550_getc(NS16550_t com_port); +int NS16550_tstc(NS16550_t com_port); +void NS16550_reinit(NS16550_t com_port, int baud_divisor); + +void _debug_uart_init(void); +void _debug_uart_putc(int ch); +int _debug_uart_getc(void); \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/include/uart.h b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_3568/include/uart.h similarity index 100% rename from Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/include/uart.h rename to Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_3568/include/uart.h diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_3568/ns16550.c b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_3568/ns16550.c new file mode 100644 index 000000000..9631fbf50 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_3568/ns16550.c @@ -0,0 +1,103 @@ +/* + * COM1 NS16550 support + * originally from linux source (arch/powerpc/boot/ns16550.c) + * modified to use CONFIG_SYS_ISA_MEM and new defines + */ + +#include + +#include "mmio_access.h" +#include "ns16550.h" + +#define UART_ADDR MMIO_P2V_WO(0xFE660000) +// #define UART_ADDR (0xFE660000) + +#define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ +#define UART_MCRVAL (UART_MCR_DTR | UART_MCR_RTS) /* RTS/DTR */ + +#define out_le32(a, v) (*(volatile uint32_t*)(a) = (v)) +#define in_le32(a) (*(volatile uint32_t*)(a)) + +#ifndef CONFIG_SYS_NS16550_IER +#define CONFIG_SYS_NS16550_IER 0x00 +#endif /* CONFIG_SYS_NS16550_IER */ + +#define serial_dout(reg, value) \ + serial_out_shift((char*)com_port + ((char*)reg - (char*)com_port) * (1 << 2), \ + 2, value) +#define serial_din(reg) \ + serial_in_shift((char*)com_port + ((char*)reg - (char*)com_port) * (1 << 2), \ + 2) + +static inline void serial_out_shift(void* addr, int shift, int value) +{ + out_le32(addr, value); +} + +static inline int serial_in_shift(void* addr, int shift) +{ + return in_le32(addr); +} + +#ifndef CONFIG_SYS_NS16550_CLK +#define CONFIG_SYS_NS16550_CLK 0 +#endif + +#define DIV_ROUND_CLOSEST(x, divisor) ( \ + { \ + typeof(x) __x = x; \ + typeof(divisor) __d = divisor; \ + (((typeof(x))-1) > 0 || ((typeof(divisor))-1) > 0 || (__x) > 0) ? (((__x) + ((__d) / 2)) / (__d)) : (((__x) - ((__d) / 2)) / (__d)); \ + }) + +int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate) +{ + const unsigned int mode_x_div = 16; + + return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate); +} + +void _debug_uart_init(void) +{ + struct NS16550* com_port = (struct NS16550*)UART_ADDR; + + /* + * We copy the code from above because it is already horribly messy. + * Trying to refactor to nicely remove the duplication doesn't seem + * feasible. The better fix is to move all users of this driver to + * driver model. + */ + int baud_divisor = ns16550_calc_divisor(com_port, 24000000, + 1500000); + serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER); + serial_dout(&com_port->mcr, UART_MCRVAL); + serial_dout(&com_port->fcr, UART_FCR_DEFVAL); + + serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL); + serial_dout(&com_port->dll, baud_divisor & 0xff); + serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff); + serial_dout(&com_port->lcr, UART_LCRVAL); +} + +void _debug_uart_putc(int ch) +{ + static struct NS16550* com_port = (struct NS16550*)UART_ADDR; + + if (ch == '\n') { + _debug_uart_putc('\r'); + } + + while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) + ; + serial_dout(&com_port->thr, ch); +} + +int _debug_uart_getc(void) +{ + static struct NS16550* com_port = (struct NS16550*)UART_ADDR; + + while (!(serial_din(&com_port->lsr) & UART_LSR_DR)) + ; + + return serial_din(&com_port->rbr); +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_3568/uart.c b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_3568/uart.c new file mode 100644 index 000000000..de03611a2 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_3568/uart.c @@ -0,0 +1,45 @@ +// +// low-level driver routines for pl011 UART. +// + +#include "uart.h" +#include "actracer.h" +#include "ns16550.h" +#include "uart_common_ope.h" + +// the UART control registers are memory-mapped +// at address UART0. this macro returns the +// address of one of the registers. + +void uartinit(void) +{ + _debug_uart_init(); +} + +void uartputc(uint8_t c) +{ + _debug_uart_putc((int)c); +} + +static uint8_t uartgetc(void) +{ + return (uint8_t)_debug_uart_getc(); +} + +static uint32_t UartGetIrqnum() +{ + return 0; +} + +static struct XiziSerialDriver hardkernel_serial_driver = { + .sys_serial_init = uartinit, + .get_serial_irqnum = UartGetIrqnum, + .putc = uartputc, + .getc = uartgetc, +}; + +struct XiziSerialDriver* hardkernel_uart_init(struct TraceTag* hardkernel_tag) +{ + hardkernel_serial_driver.sys_serial_init(); + return &hardkernel_serial_driver; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/boot.S b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/boot.S similarity index 100% rename from Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/boot.S rename to Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/boot.S diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/Makefile deleted file mode 100644 index 7544324de..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -SRC_FILES := uart.c - -include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/uart.c b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/uart.c deleted file mode 100644 index 8324eb35e..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/uart.c +++ /dev/null @@ -1,128 +0,0 @@ -// -// low-level driver routines for pl011 UART. -// - -#include "uart.h" -#include "actracer.h" -#include "uart_common_ope.h" - -// the UART control registers are memory-mapped -// at address UART0. this macro returns the -// address of one of the registers. - -// the transmit output buffer. -#define UART_TX_BUF_SIZE 32 -static char uart_tx_buf[UART_TX_BUF_SIZE]; -uint64_t uart_tx_w; // write next to uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE] -uint64_t uart_tx_r; // read next from uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE] - -void uartinit(void) -{ - // disable uart - UART_WRITE_REG(CR, 0); - - // disable interrupts. - UART_WRITE_REG(IMSC, 0); - - // in qemu, it is not necessary to set baudrate. - // enable FIFOs. - // set word length to 8 bits, no parity. - UART_WRITE_REG(LCRH, LCRH_FEN | LCRH_WLEN_8BIT); - - // enable RXE, TXE and enable uart. - UART_WRITE_REG(CR, 0x301); - - // enable transmit and receive interrupts. - UART_WRITE_REG(IMSC, INT_RX_ENABLE | INT_TX_ENABLE); -} - -// if the UART is idle, and a character is waiting -// in the transmit buffer, send it. -// caller must hold uart_tx_lock. -// called from both the top- and bottom-half. -void uartstart() -{ - while (1) { - if (uart_tx_w == uart_tx_r) { - // transmit buffer is empty. - return; - } - - if (UART_READ_REG(FR) & FR_TXFF) { - // the UART transmit holding register is full, - // so we cannot give it another byte. - // it will interrupt when it's ready for a new byte. - return; - } - - int c = uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE]; - uart_tx_r += 1; - - // maybe uartputc() is waiting for space in the buffer. - - UART_WRITE_REG(DR, c); - } -} - -// add a character to the output buffer and tell the -// UART to start sending if it isn't already. -// blocks if the output buffer is full. -// because it may block, it can't be called -// from interrupts; it's only suitable for use -// by write(). -void uartputc(uint8_t c) -{ - while (uart_tx_w == uart_tx_r + UART_TX_BUF_SIZE) - ; - uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE] = c; - uart_tx_w += 1; - uartstart(); - return; -} - -// read one input character from the UART. -// return -1 if none is waiting. -static uint8_t uartgetc(void) -{ - if (UART_READ_REG(FR) & FR_RXFE) - return 0xFF; - else - return UART_READ_REG(DR); -} - -// handle a uart interrupt, raised because input has -// arrived, or the uart is ready for more output, or -// both. called from trap.c. -void uartintr(void) -{ - // read and process incoming characters. - while (1) { - int c = uartgetc(); - if (c == 0xFF) - break; - } - - // send buffered characters. - uartstart(); - - // clear transmit and receive interrupts. - UART_WRITE_REG(ICR, INT_RX_ENABLE | INT_TX_ENABLE); -} - -static uint32_t UartGetIrqnum() -{ - return 0; -} - -static struct XiziSerialDriver hardkernel_serial_driver = { - .sys_serial_init = uartinit, - .get_serial_irqnum = UartGetIrqnum, - .putc = uartputc, - .getc = uartgetc, -}; - -struct XiziSerialDriver* hardkernel_uart_init(struct TraceTag* hardkernel_tag) -{ - hardkernel_serial_driver.sys_serial_init(); - return &hardkernel_serial_driver; -} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/kernel_actracer/actracer.c b/Ubiquitous/XiZi_AIoT/kernel_actracer/actracer.c index 8412f6f59..f74596559 100644 --- a/Ubiquitous/XiZi_AIoT/kernel_actracer/actracer.c +++ b/Ubiquitous/XiZi_AIoT/kernel_actracer/actracer.c @@ -147,7 +147,7 @@ void* AchieveResource(TraceTag* tag) bool CreateResourceTag(TraceTag* new_tag, TraceTag* owner, char* name, tracemeta_ac_type type, void* p_resource) { - assert(new_tag != NULL && owner != NULL); + assert(owner != NULL); if (owner->meta == NULL) { ERROR("Tracer: Empty owner\n"); return false; @@ -168,7 +168,9 @@ bool CreateResourceTag(TraceTag* new_tag, TraceTag* owner, char* name, tracemeta doubleListAddOnHead(&new_node->list_node, &owner->meta->children_guard); new_node->parent = owner->meta; - new_tag->meta = new_node; + if (new_tag != NULL) { + new_tag->meta = new_node; + } return true; } @@ -187,12 +189,42 @@ bool DeleteResource(TraceTag* target, TraceTag* owner) if (target->meta->name != NULL) { slab_free(&sys_tracer.node_name_allocator, target->meta->name); } + // delete all children - /// @attention currently donot allow multilevel resource deletion if (target->meta->type == TRACER_OWNER) { - assert(IS_DOUBLE_LIST_EMPTY(&target->meta->children_guard)); + while (!IS_DOUBLE_LIST_EMPTY(&target->meta->children_guard)) { + TraceTag tmp_node = { + .meta = DOUBLE_LIST_ENTRY(target->meta->children_guard.next, TracerNode, list_node), + }; + DeleteResource(&tmp_node, target); + } } slab_free(&sys_tracer.node_allocator, target->meta); target->meta = NULL; return true; +} + +void debug_list_tracetree_inner(TracerNode* cur_node) +{ + DEBUG("[%s] ", cur_node->name); + TracerNode* tmp = NULL; + DOUBLE_LIST_FOR_EACH_ENTRY(tmp, &cur_node->children_guard, list_node) + { + if (tmp->name != NULL) { + DEBUG("%s ", tmp->name); + } else { + DEBUG("ANON "); + } + } + DEBUG("\n"); + DOUBLE_LIST_FOR_EACH_ENTRY(tmp, &cur_node->children_guard, list_node) + { + debug_list_tracetree_inner(tmp); + } +} + +void debug_list_tracetree() +{ + TracerNode* ref_root = RequireRootTag()->meta; + debug_list_tracetree_inner(ref_root); } \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/path_kernel.mk b/Ubiquitous/XiZi_AIoT/path_kernel.mk index a7b626018..2a8bca965 100755 --- a/Ubiquitous/XiZi_AIoT/path_kernel.mk +++ b/Ubiquitous/XiZi_AIoT/path_kernel.mk @@ -38,20 +38,20 @@ KERNELPATHS += \ -I$(KERNEL_ROOT)/hardkernel/cache/L2/pl310/ endif -ifeq ($(BOARD), ok1028a-c) +ifeq ($(BOARD), 3568) KERNELPATHS += \ - -I$(KERNEL_ROOT)/hardkernel/clock/arm/armv8-a/cortex-a72/$(BOARD)/include \ - -I$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_$(BOARD)/include \ - -I$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a72/ \ - -I$(KERNEL_ROOT)/hardkernel/mmu/arm/armv8-a/cortex-a72/$(BOARD) \ - -I$(KERNEL_ROOT)/hardkernel/mmu/arm/armv8-a/cortex-a72/include \ - -I$(KERNEL_ROOT)/hardkernel/clock/arm/armv8-a/cortex-a72/include \ - -I$(KERNEL_ROOT)/hardkernel/intr/arm/armv8-a/cortex-a72/ \ - -I$(KERNEL_ROOT)/hardkernel/intr/arm/armv8-a/cortex-a72/$(BOARD) \ - -I$(KERNEL_ROOT)/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3 \ - -I$(KERNEL_ROOT)/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_$(BOARD)/include \ - -I$(KERNEL_ROOT)/hardkernel/uart/arm/armv8-a/cortex-a72/ \ - -I$(KERNEL_ROOT)/hardkernel/cache/L1/arm/cortex-a72/ + -I$(KERNEL_ROOT)/hardkernel/clock/arm/armv8-a/cortex-a55/$(BOARD)/include \ + -I$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_$(BOARD)/include \ + -I$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a55/ \ + -I$(KERNEL_ROOT)/hardkernel/mmu/arm/armv8-a/cortex-a55/$(BOARD) \ + -I$(KERNEL_ROOT)/hardkernel/mmu/arm/armv8-a/cortex-a55/include \ + -I$(KERNEL_ROOT)/hardkernel/clock/arm/armv8-a/cortex-a55/include \ + -I$(KERNEL_ROOT)/hardkernel/intr/arm/armv8-a/cortex-a55/ \ + -I$(KERNEL_ROOT)/hardkernel/intr/arm/armv8-a/cortex-a55/$(BOARD) \ + -I$(KERNEL_ROOT)/hardkernel/intr/arm/armv8-a/cortex-a55/gicv3 \ + -I$(KERNEL_ROOT)/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_$(BOARD)/include \ + -I$(KERNEL_ROOT)/hardkernel/uart/arm/armv8-a/cortex-a55/ \ + -I$(KERNEL_ROOT)/hardkernel/cache/L1/arm/cortex-a55/ endif KERNELPATHS += \ diff --git a/Ubiquitous/XiZi_AIoT/services/app/Makefile b/Ubiquitous/XiZi_AIoT/services/app/Makefile index 50d9aca5b..2b5808fe6 100644 --- a/Ubiquitous/XiZi_AIoT/services/app/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/app/Makefile @@ -10,10 +10,10 @@ cflags = -std=c11 -O2 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs - board_specs = stub.o #cflags = -Wall -g -std=c11 endif -ifeq ($(BOARD), ok1028a-c) +ifeq ($(BOARD), 3568) toolchain ?= aarch64-none-elf- user_ldflags = -N -Ttext 0 -cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +cflags = -Wall -O2 -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie board_specs = stub.o endif @@ -43,9 +43,9 @@ INC_DIR = -I$(KERNEL_ROOT)/services/shell/letter-shell \ -I$(KERNEL_ROOT)/services/app ifeq ($(BOARD), imx6q-sabrelite) -all: init test_fault simple_client simple_server shell fs_server semaphore_server test_semaphore test_ipc_null test_thread test_irq_hdlr test_irq_block test_irq_send eth_driver epit_server test_net lwip readme.txt | bin +all: test_fault simple_client simple_server shell fs_server semaphore_server test_semaphore test_ipc_null test_thread test_irq_hdlr test_irq_block test_irq_send eth_driver epit_server test_net lwip readme.txt | bin else -all: init test_fault simple_client simple_server shell fs_server semaphore_server test_ipc_null test_thread test_semaphore test_net lwip readme.txt eth_hal | bin +all: test_fault simple_client simple_server shell fs_server semaphore_server test_ipc_null test_thread test_semaphore test_net lwip readme.txt eth_hal | bin endif ../tools/mkfs/mkfs ./fs.img $^ @mv $(filter-out readme.txt, $^) bin @@ -97,10 +97,6 @@ shell: shell_port.o libserial.o printf.o shell_cmd_list.o shell.o shell_ext.o li @${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs} @${objdump} -S $@ > $@.asm -init: init.o libfs.o libipc.o session.o libserial.o printf.o usyscall.o arch_usyscall.o libmem.o - @${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs} - @${objdump} -S $@ > $@.asm - test_fault: test_fault.o libserial.o printf.o usyscall.o arch_usyscall.o @${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs} @${objdump} -S $@ > $@.asm diff --git a/Ubiquitous/XiZi_AIoT/services/app/init.c b/Ubiquitous/XiZi_AIoT/services/app/init.c deleted file mode 100755 index dbedd4795..000000000 --- a/Ubiquitous/XiZi_AIoT/services/app/init.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ -// init: The initial user-level program -#include - -#include "libfs.h" -#include "libserial.h" -#include "usyscall.h" - -int main(int argc, char* argv[]) -{ - struct Session session; - printf("init: connecting MemFS\n"); - while (connect_session(&session, "MemFS", 8092) < 0) - ; - printf("init: connect MemFS success\n"); - - int fd; - char* shell_task_param[2] = { "/shell", 0 }; - if ((fd = open(&session, shell_task_param[0])) < 0) { - printf("Open %s failed\n", shell_task_param[0]); - exit(1); - } - - if (spawn(&session, fd, read, fsize, shell_task_param[0], shell_task_param) < 0) { - printf("Syscall Spawn shell failed\n"); - } - - close(&session, fd); - - exit(0); - return 0; -} diff --git a/Ubiquitous/XiZi_AIoT/services/app/shell_port.c b/Ubiquitous/XiZi_AIoT/services/app/shell_port.c index 785ad8b6e..7f9c286c4 100644 --- a/Ubiquitous/XiZi_AIoT/services/app/shell_port.c +++ b/Ubiquitous/XiZi_AIoT/services/app/shell_port.c @@ -50,7 +50,7 @@ int main(void) shellInit(&shell, shellBuffer, 512); - while (connect_session(&session_fs, "MemFS", 8092) < 0) + while (connect_session(&session_fs, "MemFS", 0x10000) < 0) ; if (!session_fs.buf) { printf("session connect faield\n"); diff --git a/Ubiquitous/XiZi_AIoT/services/app/simple_client.c b/Ubiquitous/XiZi_AIoT/services/app/simple_client.c index 2a23acb6a..191e580d7 100755 --- a/Ubiquitous/XiZi_AIoT/services/app/simple_client.c +++ b/Ubiquitous/XiZi_AIoT/services/app/simple_client.c @@ -108,7 +108,7 @@ int main(int argc, char** argv) struct Session fs_session; static char id_buf[33] = { 0 }; if (id > 1) { - if (connect_session(&fs_session, "MemFS", 8192) < 0) { + if (connect_session(&fs_session, "MemFS", 0x4000) < 0) { printf("connect fs_session failed\n"); } else { int fd; diff --git a/Ubiquitous/XiZi_AIoT/services/app/simple_server.c b/Ubiquitous/XiZi_AIoT/services/app/simple_server.c index e6eafe275..2ae2d9e12 100755 --- a/Ubiquitous/XiZi_AIoT/services/app/simple_server.c +++ b/Ubiquitous/XiZi_AIoT/services/app/simple_server.c @@ -30,8 +30,7 @@ int IPC_DO_SERVE_FUNC(Ipc_hello_string)(char* buf, int* len) return 0; } -// IPC_SERVER_INTERFACE(Ipc_add, 2); -IPC_SERVER_THREAD_INTERFACE(Ipc_add, 2); +IPC_SERVER_INTERFACE(Ipc_add, 2); IPC_SERVER_INTERFACE(Ipc_hello_string, 2); IPC_SERVER_REGISTER_INTERFACES(IpcSimpleServer, 2, Ipc_hello_string, Ipc_add); diff --git a/Ubiquitous/XiZi_AIoT/services/boards/ok1028a-c/Makefile b/Ubiquitous/XiZi_AIoT/services/boards/3568/Makefile similarity index 84% rename from Ubiquitous/XiZi_AIoT/services/boards/ok1028a-c/Makefile rename to Ubiquitous/XiZi_AIoT/services/boards/3568/Makefile index 856202b4b..f7c02d433 100644 --- a/Ubiquitous/XiZi_AIoT/services/boards/ok1028a-c/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/boards/3568/Makefile @@ -8,10 +8,10 @@ toolchain ?= arm-xilinx-eabi- user_ldflags = -N -Ttext 0 cflags = -march=armv7-a -std=c11 -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie endif -ifeq ($(BOARD), ok1028a-c) +ifeq ($(BOARD), 3568) toolchain ?= aarch64-none-elf- user_ldflags = -N -Ttext 0 -cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie endif cc = ${toolchain}gcc diff --git a/Ubiquitous/XiZi_AIoT/services/boards/ok1028a-c/arch_usyscall.c b/Ubiquitous/XiZi_AIoT/services/boards/3568/arch_usyscall.c similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/boards/ok1028a-c/arch_usyscall.c rename to Ubiquitous/XiZi_AIoT/services/boards/3568/arch_usyscall.c diff --git a/Ubiquitous/XiZi_AIoT/services/boards/3568/libserial.c b/Ubiquitous/XiZi_AIoT/services/boards/3568/libserial.c new file mode 100644 index 000000000..15c5dbd2a --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/boards/3568/libserial.c @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/// this file is only used for debug +#include +#include + +#include "libserial.h" +#include "usyscall.h" + +/* + * For driver model we always use one byte per register, and sort out the + * differences in the driver + */ +#define CONFIG_SYS_NS16550_REG_SIZE (-1) + +#define UART_REG(x) \ + unsigned char x; \ + unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; + +/** + * struct ns16550_platdata - information about a NS16550 port + * + * @base: Base register address + * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...) + * @clock: UART base clock speed in Hz + */ +struct ns16550_platdata { + unsigned long base; + int reg_shift; + int clock; + int reg_offset; + uint32_t fcr; +}; + +struct udevice; + +struct NS16550 { + UART_REG(rbr); /* 0 */ + UART_REG(ier); /* 1 */ + UART_REG(fcr); /* 2 */ + UART_REG(lcr); /* 3 */ + UART_REG(mcr); /* 4 */ + UART_REG(lsr); /* 5 */ + UART_REG(msr); /* 6 */ + UART_REG(spr); /* 7 */ +#ifdef CONFIG_SOC_DA8XX + UART_REG(reg8); /* 8 */ + UART_REG(reg9); /* 9 */ + UART_REG(revid1); /* A */ + UART_REG(revid2); /* B */ + UART_REG(pwr_mgmt); /* C */ + UART_REG(mdr1); /* D */ +#else + UART_REG(mdr1); /* 8 */ + UART_REG(reg9); /* 9 */ + UART_REG(regA); /* A */ + UART_REG(regB); /* B */ + UART_REG(regC); /* C */ + UART_REG(regD); /* D */ + UART_REG(regE); /* E */ + UART_REG(uasr); /* F */ + UART_REG(scr); /* 10*/ + UART_REG(ssr); /* 11*/ +#endif +#ifdef CONFIG_DM_SERIAL + struct ns16550_platdata* plat; +#endif +}; + +#define thr rbr +#define iir fcr +#define dll rbr +#define dlm ier + +typedef struct NS16550* NS16550_t; + +/* + * These are the definitions for the FIFO Control Register + */ +#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ + +#define UART_FCR_RXSR 0x02 /* Receiver soft reset */ +#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ + +/* Ingenic JZ47xx specific UART-enable bit. */ +#define UART_FCR_UME 0x10 + +/* Clear & enable FIFOs */ +#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR) + +/* + * These are the definitions for the Modem Control Register + */ +#define UART_MCR_DTR 0x01 /* DTR */ +#define UART_MCR_RTS 0x02 /* RTS */ +#define UART_MCR_OUT1 0x04 /* Out 1 */ +#define UART_MCR_OUT2 0x08 /* Out 2 */ +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */ + +#define UART_MCR_DMA_EN 0x04 +#define UART_MCR_TX_DFR 0x08 + +/* + * These are the definitions for the Line Control Register + * + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting + * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. + */ +#define UART_LCR_WLS_MSK 0x03 /* character length select mask */ +#define UART_LCR_WLS_5 0x00 /* 5 bit character length */ +#define UART_LCR_WLS_6 0x01 /* 6 bit character length */ +#define UART_LCR_WLS_7 0x02 /* 7 bit character length */ +#define UART_LCR_WLS_8 0x03 /* 8 bit character length */ +#define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */ +#define UART_LCR_PEN 0x08 /* Parity eneble */ +#define UART_LCR_EPS 0x10 /* Even Parity Select */ +#define UART_LCR_STKP 0x20 /* Stick Parity */ +#define UART_LCR_SBRK 0x40 /* Set Break */ +#define UART_LCR_BKSE 0x80 /* Bank select enable */ +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ + +/* + * These are the definitions for the Line Status Register + */ +#define UART_LSR_DR 0x01 /* Data ready */ +#define UART_LSR_OE 0x02 /* Overrun */ +#define UART_LSR_PE 0x04 /* Parity error */ +#define UART_LSR_FE 0x08 /* Framing error */ +#define UART_LSR_BI 0x10 /* Break */ +#define UART_LSR_THRE 0x20 /* Xmit holding register empty */ +#define UART_LSR_TEMT 0x40 /* Xmitter empty */ +#define UART_LSR_ERR 0x80 /* Error */ + +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ +#define UART_MSR_RI 0x40 /* Ring Indicator */ +#define UART_MSR_DSR 0x20 /* Data Set Ready */ +#define UART_MSR_CTS 0x10 /* Clear to Send */ +#define UART_MSR_DDCD 0x08 /* Delta DCD */ +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ +#define UART_MSR_DDSR 0x02 /* Delta DSR */ +#define UART_MSR_DCTS 0x01 /* Delta CTS */ + +/* + * These are the definitions for the Interrupt Identification Register + */ +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ + +#define UART_IIR_MSI 0x00 /* Modem status interrupt */ +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ + +/* + * These are the definitions for the Interrupt Enable Register + */ +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ + +/* useful defaults for LCR */ +#define UART_LCR_8N1 0x03 + +#define UART_ADDR (0xFE660000) + +#define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ +#define UART_MCRVAL (UART_MCR_DTR | UART_MCR_RTS) /* RTS/DTR */ + +#define out_le32(a, v) (*(volatile uint32_t*)(a) = (v)) +#define in_le32(a) (*(volatile uint32_t*)(a)) + +#ifndef CONFIG_SYS_NS16550_IER +#define CONFIG_SYS_NS16550_IER 0x00 +#endif /* CONFIG_SYS_NS16550_IER */ + +#define serial_dout(reg, value) \ + serial_out_shift((char*)com_port + ((char*)reg - (char*)com_port) * (1 << 2), \ + 2, value) +#define serial_din(reg) \ + serial_in_shift((char*)com_port + ((char*)reg - (char*)com_port) * (1 << 2), \ + 2) + +static inline void serial_out_shift(void* addr, int shift, int value) +{ + out_le32(addr, value); +} + +static inline int serial_in_shift(void* addr, int shift) +{ + return in_le32(addr); +} + +#ifndef CONFIG_SYS_NS16550_CLK +#define CONFIG_SYS_NS16550_CLK 0 +#endif + +bool init_uart_mmio() +{ + static int mapped = 0; + if (mapped == 0) { + if (-1 == mmap(UART_ADDR, UART_ADDR, 4096, true)) { + return false; + } + mapped = 1; + } + return true; +} + +void putc(char ch) +{ + static struct NS16550* com_port = (struct NS16550*)UART_ADDR; + + if (ch == '\n') { + putc('\r'); + } + + while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) + ; + serial_dout(&com_port->thr, ch); +} + +char getc(void) +{ + static struct NS16550* com_port = (struct NS16550*)UART_ADDR; + + while (!(serial_din(&com_port->lsr) & UART_LSR_DR)) + ; + + return serial_din(&com_port->rbr); +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/boards/ok1028a-c/stub.c b/Ubiquitous/XiZi_AIoT/services/boards/3568/stub.c similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/boards/ok1028a-c/stub.c rename to Ubiquitous/XiZi_AIoT/services/boards/3568/stub.c diff --git a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/Makefile b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/Makefile index 8704dbb0a..9a4022521 100644 --- a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/Makefile @@ -8,10 +8,10 @@ toolchain ?= arm-xilinx-eabi- user_ldflags = -N -Ttext 0 cflags = -march=armv7-a -std=c11 -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie endif -ifeq ($(BOARD), ok1028a-c) +ifeq ($(BOARD), 3568) toolchain ?= aarch64-none-elf- user_ldflags = -N -Ttext 0 -cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie endif cc = ${toolchain}gcc diff --git a/Ubiquitous/XiZi_AIoT/services/boards/ok1028a-c/libserial.c b/Ubiquitous/XiZi_AIoT/services/boards/ok1028a-c/libserial.c deleted file mode 100644 index 57cb02b86..000000000 --- a/Ubiquitous/XiZi_AIoT/services/boards/ok1028a-c/libserial.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ - -/// this file is only used for debug -#include "libserial.h" -#include "usyscall.h" - -#define USER_UART_BASE 0x6FFFF000 - -#define UART0_BASE (0x09000000ULL) -#define UART0_REG(reg) ((volatile uint32_t*)(USER_UART_BASE + reg)) - -// the UART control registers. -// pl011 -#define DR 0x00 -#define FR 0x18 -#define FR_RXFE (1 << 4) // recieve fifo empty -#define FR_TXFF (1 << 5) // transmit fifo full -#define FR_RXFF (1 << 6) // recieve fifo full -#define FR_TXFE (1 << 7) // transmit fifo empty -#define IBRD 0x24 -#define FBRD 0x28 -#define LCRH 0x2c -#define LCRH_FEN (1 << 4) -#define LCRH_WLEN_8BIT (3 << 5) -#define CR 0x30 -#define IMSC 0x38 -#define INT_RX_ENABLE (1 << 4) -#define INT_TX_ENABLE (1 << 5) -#define ICR 0x44 - -#define UART_READ_REG(reg) (*(UART0_REG(reg))) -#define UART_WRITE_REG(reg, v) (*(UART0_REG(reg)) = (v)) - -#define UART_TX_BUF_SIZE 32 -static char uart_tx_buf[UART_TX_BUF_SIZE]; -uint64_t uart_tx_w; // write next to uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE] -uint64_t uart_tx_r; // read next from uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE] - -bool init_uart_mmio() -{ - static int mapped = 0; - if (mapped == 0) { - if (-1 == mmap(USER_UART_BASE, UART0_BASE, 4096, true)) { - return false; - } - mapped = 1; - } - return true; -} - -// if the UART is idle, and a character is waiting -// in the transmit buffer, send it. -// caller must hold uart_tx_lock. -// called from both the top- and bottom-half. -void uartstart() -{ - while (1) { - if (uart_tx_w == uart_tx_r) { - // transmit buffer is empty. - return; - } - - if (UART_READ_REG(FR) & FR_TXFF) { - // the UART transmit holding register is full, - // so we cannot give it another byte. - // it will interrupt when it's ready for a new byte. - return; - } - - int c = uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE]; - uart_tx_r += 1; - - // maybe uartputc() is waiting for space in the buffer. - - UART_WRITE_REG(DR, c); - } -} - -// add a character to the output buffer and tell the -// UART to start sending if it isn't already. -// blocks if the output buffer is full. -// because it may block, it can't be called -// from interrupts; it's only suitable for use -// by write(). -void putc(char c) -{ - while (uart_tx_w == uart_tx_r + UART_TX_BUF_SIZE) - ; - uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE] = c; - uart_tx_w += 1; - uartstart(); - return; -} - -// read one input character from the UART. -// return -1 if none is waiting. -char getc(void) -{ - if (UART_READ_REG(FR) & FR_RXFE) - return 0xFF; - else - return UART_READ_REG(DR); -} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/boards/zynq7000-zc702/Makefile b/Ubiquitous/XiZi_AIoT/services/boards/zynq7000-zc702/Makefile index d40f0aa3e..699cb7e32 100644 --- a/Ubiquitous/XiZi_AIoT/services/boards/zynq7000-zc702/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/boards/zynq7000-zc702/Makefile @@ -9,10 +9,10 @@ user_ldflags = --start-group,-lgcc,-lc,--end-group cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie #cflags = -Wall -g -std=c11 endif -ifeq ($(BOARD), ok1028a-c) +ifeq ($(BOARD), 3568) toolchain ?= aarch64-none-elf- user_ldflags = -N -Ttext 0 -cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie endif cc = ${toolchain}gcc diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/3568/Makefile similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/Makefile rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/Makefile diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/Makefile similarity index 79% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/Makefile rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/Makefile index 5db88ceb8..17eb018d0 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/Makefile @@ -19,6 +19,13 @@ cflags = -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -stati board_specs = stub.o endif +ifeq ($(BOARD), 3568) +toolchain ?= aarch64-none-elf- +user_ldflags = -N -Ttext 0 +cflags = -Wall -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +board_specs = $(KERNEL_ROOT)/services/app/stub.o +endif + cc = ${toolchain}gcc ld = ${toolchain}g++ objdump = ${toolchain}objdump @@ -28,7 +35,7 @@ c_useropts = -O2 INC_DIR = -I$(KERNEL_ROOT)/services/app \ -I$(KERNEL_ROOT)/services/boards/$(BOARD) \ -I$(KERNEL_ROOT)/services/lib/serial \ - -I$(KERNEL_ROOT)/services/drivers/rk-3568/include \ + -I$(KERNEL_ROOT)/services/drivers/3568/include \ -I$(KERNEL_ROOT)/services/lib/usyscall \ -I$(KERNEL_ROOT)/services/lib/ipc \ -I$(KERNEL_ROOT)/services/lib/memory diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_base.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_base.c similarity index 99% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_base.c rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_base.c index 14df77768..f83f62cfe 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_base.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_base.c @@ -122,12 +122,10 @@ __attribute__((always_inline)) static inline HAL_Status TimerDelayUs(uint32_t us from = HAL_TIMER_GetCount(SYS_TIMER); count = PLL_INPUT_OSC_RATE / 1000000 * us; - do { now = HAL_TIMER_GetCount(SYS_TIMER); pass = now > from ? now - from : from - now; } while (pass < count); - return HAL_OK; } #endif @@ -314,13 +312,13 @@ __attribute__((weak)) HAL_Status HAL_DelayMs(uint32_t ms) */ HAL_Status HAL_DelayUs(uint32_t us) { -#if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED) +// #if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED) - return TimerDelayUs(us); -#else +// return TimerDelayUs(us); +// #else return HAL_CPUDelayUs(us); -#endif +// #endif } /** diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_bsp.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_bsp.c similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_bsp.c rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_bsp.c diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_cru.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_cru.c similarity index 83% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_cru.c rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_cru.c index 8a48a630c..c685a6149 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_cru.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_cru.c @@ -956,268 +956,6 @@ HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup) } #endif -#ifdef CRU_CLK_USE_CON_BANK -static const struct HAL_CRU_DEV *CRU_GetInfo(void) -{ - return &g_cruDev; -} - -HAL_Check HAL_CRU_ClkIsEnabled(uint32_t clk) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); - uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); - uint32_t bank = CLK_GATE_GET_REG_BANK(clk); - uint32_t reg; - HAL_Check ret; - - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].gateOffset + index * 4; - ret = (HAL_Check)(!((CRU_READ(reg) & (1 << shift)) >> shift)); - - return ret; -} - -HAL_Status HAL_CRU_ClkEnable(uint32_t clk) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); - uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); - uint32_t bank = CLK_GATE_GET_REG_BANK(clk); - uint32_t reg; - - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].gateOffset + index * 4; - CRU_WRITE(reg, shift, 1U << shift, 0U); - - return HAL_OK; -} - -HAL_Status HAL_CRU_ClkDisable(uint32_t clk) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); - uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); - uint32_t bank = CLK_GATE_GET_REG_BANK(clk); - uint32_t reg; - - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].gateOffset + index * 4; - CRU_WRITE(reg, shift, 1U << shift, 1U); - - return HAL_OK; -} - -HAL_Status HAL_CRU_ClkDisableUnused(uint32_t bank, uint32_t index, uint32_t val) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t reg; - - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].gateOffset + index * 4; - CRU_WRITE(reg, 0, 0, val); - - return HAL_OK; -} - -HAL_Check HAL_CRU_ClkIsReset(uint32_t clk) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); - uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); - uint32_t bank = CLK_GATE_GET_REG_BANK(clk); - uint32_t reg; - HAL_Check ret; - - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4; - ret = (HAL_Check)((CRU_READ(reg) & (1 << shift)) >> shift); - - return ret; -} - -HAL_Status HAL_CRU_ClkResetAssert(uint32_t clk) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t index = CLK_RESET_GET_REG_OFFSET(clk); - uint32_t shift = CLK_RESET_GET_BITS_SHIFT(clk); - uint32_t bank = CLK_GATE_GET_REG_BANK(clk); - uint32_t reg; - - HAL_ASSERT(shift < 16); - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4; - CRU_WRITE(reg, shift, 1U << shift, 1U); - - return HAL_OK; -} - -HAL_Status HAL_CRU_ClkResetDeassert(uint32_t clk) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t index = CLK_RESET_GET_REG_OFFSET(clk); - uint32_t shift = CLK_RESET_GET_BITS_SHIFT(clk); - uint32_t bank = CLK_GATE_GET_REG_BANK(clk); - uint32_t reg; - - HAL_ASSERT(shift < 16); - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4; - CRU_WRITE(reg, shift, 1U << shift, 0U); - - return HAL_OK; -} - -HAL_Status HAL_CRU_ClkResetSyncAssert(int numClks, uint32_t *clks) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t index = CLK_RESET_GET_REG_OFFSET(clks[0]); - uint32_t bank = CLK_GATE_GET_REG_BANK(clks[0]); - uint32_t val = 0; - uint32_t reg; - int i; - - for (i = 0; i < numClks; i++) { - val |= HAL_BIT(CLK_RESET_GET_BITS_SHIFT(clks[i])); - if (index != CLK_RESET_GET_REG_OFFSET(clks[i])) { - return HAL_ERROR; - } - } - - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4; - CRU_WRITE(reg, 0, val, val); - HAL_DBG("%s: index: 0x%lx, val: 0x%lx\n", __func__, index, val); - - return HAL_OK; -} - -HAL_Status HAL_CRU_ClkResetSyncDeassert(int numClks, uint32_t *clks) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t index = CLK_RESET_GET_REG_OFFSET(clks[0]); - uint32_t bank = CLK_GATE_GET_REG_BANK(clks[0]); - uint32_t val = 0; - uint32_t reg; - int i; - - for (i = 0; i < numClks; i++) { - val |= HAL_BIT(CLK_RESET_GET_BITS_SHIFT(clks[i])); - if (index != CLK_RESET_GET_REG_OFFSET(clks[i])) { - return HAL_ERROR; - } - } - - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4; - CRU_WRITE(reg, 0, val, 0); - HAL_DBG("%s: index: 0x%lx, val: 0x%lx\n", __func__, index, val); - - return HAL_OK; -} - -HAL_Status HAL_CRU_ClkSetDiv(uint32_t divName, uint32_t divValue) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t shift, mask, index; - uint32_t reg, bank; - - index = CLK_DIV_GET_REG_OFFSET(divName); - shift = CLK_DIV_GET_BITS_SHIFT(divName); - HAL_ASSERT(shift < 16); - mask = CLK_DIV_GET_MASK(divName); - if (divValue > mask) { - divValue = mask; - } - - bank = CLK_DIV_GET_BANK(divName); - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4; - CRU_WRITE(reg, shift, mask, (divValue - 1U)); - - return HAL_OK; -} - -uint32_t HAL_CRU_ClkGetDiv(uint32_t divName) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t shift, mask, index, divValue; - uint32_t reg, bank; - - index = CLK_DIV_GET_REG_OFFSET(divName); - shift = CLK_DIV_GET_BITS_SHIFT(divName); - HAL_ASSERT(shift < 16); - mask = CLK_DIV_GET_MASK(divName); - bank = CLK_DIV_GET_BANK(divName); - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4; - divValue = ((CRU_READ(reg) & mask) >> shift) + 1; - - return divValue; -} - -HAL_SECTION_SRAM_CODE -HAL_Status HAL_CRU_ClkSetMux(uint32_t muxName, uint32_t muxValue) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t shift, mask, index; - uint32_t reg, bank; - - index = CLK_MUX_GET_REG_OFFSET(muxName); - shift = CLK_MUX_GET_BITS_SHIFT(muxName); - HAL_ASSERT(shift < 16); - mask = CLK_MUX_GET_MASK(muxName); - bank = CLK_MUX_GET_BANK(muxName); - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4; - CRU_WRITE(reg, shift, mask, muxValue); - - return HAL_OK; -} - -HAL_SECTION_SRAM_CODE -uint32_t HAL_CRU_ClkGetMux(uint32_t muxName) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t shift, mask, index, muxValue; - uint32_t reg, bank; - - index = CLK_MUX_GET_REG_OFFSET(muxName); - shift = CLK_MUX_GET_BITS_SHIFT(muxName); - HAL_ASSERT(shift < 16); - mask = CLK_MUX_GET_MASK(muxName); - bank = CLK_MUX_GET_BANK(muxName); - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4; - muxValue = ((CRU_READ(reg) & mask) >> shift); - - return muxValue; -} - -HAL_Status HAL_CRU_ClkSetFracDiv(uint32_t fracDivName, - uint32_t numerator, - uint32_t denominator) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t reg, bank; - uint32_t index; - - index = CLK_DIV_GET_REG_OFFSET(fracDivName); - bank = CLK_DIV_GET_BANK(fracDivName); - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4; - CRU_WRITE(reg, 0, 0, ((numerator << 16) | denominator)); - - return HAL_OK; -} - -HAL_Status HAL_CRU_ClkGetFracDiv(uint32_t fracDivName, - uint32_t *numerator, - uint32_t *denominator) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t reg, bank; - uint32_t index; - uint32_t val; - - index = CLK_DIV_GET_REG_OFFSET(fracDivName); - bank = CLK_DIV_GET_BANK(fracDivName); - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4; - val = CRU_READ(reg); - - *numerator = (val & 0xffff0000) >> 16; - *denominator = (val & 0x0000ffff); - - return HAL_OK; -} -#else /* CRU_CLK_USE_CON_BANK */ - HAL_Check HAL_CRU_ClkIsEnabled(uint32_t clk) { uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); @@ -1575,7 +1313,7 @@ HAL_Status HAL_CRU_ClkGetFracDiv(uint32_t fracDivName, return HAL_OK; } -#endif /* CRU_CLK_USE_CON_BANK */ + HAL_Status HAL_CRU_FracdivGetConfig(uint32_t rateOut, uint32_t rate, uint32_t *numerator, diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_cru_rk3568.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_cru_rk3568.c similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_cru_rk3568.c rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_cru_rk3568.c diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_debug.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_debug.c similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_debug.c rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_debug.c diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_gmac.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_gmac.c similarity index 97% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_gmac.c rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_gmac.c index ccd9c5dac..f4fdeb357 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_gmac.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_gmac.c @@ -284,7 +284,6 @@ #define GMAC_DESC3_LD (0x1 << 28) #define GMAC_DESC3_BUF1V (0x1 << 24) -#define DES3_ERROR_SUMMARY (1 << 15) #define DES3_ERROR_SUMMARY (1 << 15) /* Generic MII registers. */ @@ -1515,19 +1514,24 @@ void HAL_GMAC_DisableDmaIRQ(struct GMAC_HANDLE *pGMAC) */ HAL_Status HAL_GMAC_DMATxDescInit(struct GMAC_HANDLE *pGMAC, struct GMAC_Desc *txDescs, - uint8_t *txBuff, uint32_t count) + struct GMAC_Desc *txDescs_dma, + uint8_t *txBuff, uint8_t *txBuff_dma, uint32_t count) { struct GMAC_Desc *desc; uint32_t i = 0; HAL_ASSERT(pGMAC != NULL); HAL_ASSERT(txDescs != NULL); + HAL_ASSERT(txDescs_dma != NULL); HAL_ASSERT(txBuff != NULL); + HAL_ASSERT(txBuff_dma != NULL); pGMAC->txDescIdx = 0; pGMAC->txDescs = txDescs; + pGMAC->txDescs_dma = txDescs_dma; pGMAC->txBuf = txBuff; + pGMAC->txBuf_dma = txBuff_dma; pGMAC->txSize = count; /* Fill each DMATxDesc descriptor with the right values */ @@ -1557,19 +1561,24 @@ HAL_Status HAL_GMAC_DMATxDescInit(struct GMAC_HANDLE *pGMAC, */ HAL_Status HAL_GMAC_DMARxDescInit(struct GMAC_HANDLE *pGMAC, struct GMAC_Desc *rxDescs, - uint8_t *rxBuff, uint32_t count) + struct GMAC_Desc *rxDescs_dma, + uint8_t *rxBuff, uint8_t *rxBuff_dma, uint32_t count) { struct GMAC_Desc *desc; uint32_t i = 0; HAL_ASSERT(pGMAC != NULL); HAL_ASSERT(rxDescs != NULL); + HAL_ASSERT(rxDescs_dma != NULL); HAL_ASSERT(rxBuff != NULL); + HAL_ASSERT(rxBuff_dma != NULL); pGMAC->rxDescIdx = 0; pGMAC->rxDescs = rxDescs; + pGMAC->rxDescs_dma = rxDescs_dma; pGMAC->rxBuf = rxBuff; + pGMAC->rxBuf_dma = rxBuff_dma; pGMAC->rxSize = count; /* Fill each DMARxDesc descriptor with the right values */ @@ -1577,7 +1586,7 @@ HAL_Status HAL_GMAC_DMARxDescInit(struct GMAC_HANDLE *pGMAC, /* Get the pointer on the ith member of the Rx Desc list */ desc = rxDescs + i; - desc->des0 = (uint64_t)(rxBuff + i * HAL_GMAC_MAX_PACKET_SIZE); + desc->des0 = (uint32_t)(uint64_t)(rxBuff_dma + i * HAL_GMAC_MAX_PACKET_SIZE); desc->des1 = 0; desc->des2 = 0; desc->des3 = GMAC_DESC3_OWN | GMAC_DESC3_BUF1V | GMAC_DESC3_IOC; @@ -1771,7 +1780,7 @@ HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr) /* DMA init */ WRITE_REG(pGMAC->pReg->DMA_SYSBUS_MODE, DMA_SYSBUS_MODE_BLEN16 | - DMA_SYSBUS_MODE_BLEN8 | DMA_SYSBUS_MODE_BLEN4); + DMA_SYSBUS_MODE_BLEN8 | DMA_SYSBUS_MODE_BLEN4 | 1 << 12 | 1 << 14); /* Mask interrupts by writing to CSR7 */ WRITE_REG(pGMAC->pReg->DMA_CH0_INTERRUPT_ENABLE, DMA_CHAN_INTR_DEFAULT_MASK); @@ -1787,9 +1796,9 @@ HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr) value |= (rxFifosz << DMA_CH0_RX_CONTROL_RBSZ_SHIFT) & DMA_CH0_RX_CONTROL_RBSZ_MASK; value = value | (8 << DMA_CH0_RX_CONTROL_RXPBL_SHIFT); WRITE_REG(pGMAC->pReg->DMA_CH0_RX_CONTROL, value); - WRITE_REG(pGMAC->pReg->DMA_CH0_RXDESC_LIST_ADDRESS, (uint64_t)pGMAC->rxDescs); + WRITE_REG(pGMAC->pReg->DMA_CH0_RXDESC_LIST_ADDRESS, (uint32_t)(uint64_t)pGMAC->rxDescs_dma); WRITE_REG(pGMAC->pReg->DMA_CH0_RXDESC_TAIL_POINTER, - (uint64_t)(pGMAC->rxDescs + pGMAC->rxSize)); + (uint32_t)(uint64_t)(pGMAC->rxDescs_dma + pGMAC->rxSize)); /* init tx chan */ value = READ_REG(pGMAC->pReg->DMA_CH0_TX_CONTROL); @@ -1797,8 +1806,8 @@ HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr) value |= DMA_CH0_TX_CONTROL_OSF; WRITE_REG(pGMAC->pReg->DMA_CH0_TX_CONTROL, value); - WRITE_REG(pGMAC->pReg->DMA_CH0_TXDESC_LIST_ADDRESS, (uint64_t)pGMAC->txDescs); - WRITE_REG(pGMAC->pReg->DMA_CH0_TXDESC_TAIL_POINTER, (uint64_t)pGMAC->txDescs); + WRITE_REG(pGMAC->pReg->DMA_CH0_TXDESC_LIST_ADDRESS, (uint32_t)(uint64_t)pGMAC->txDescs_dma); + WRITE_REG(pGMAC->pReg->DMA_CH0_TXDESC_TAIL_POINTER, (uint32_t)(uint64_t)pGMAC->txDescs_dma); HAL_GMAC_WriteHWAddr(pGMAC, addr); @@ -1935,6 +1944,12 @@ uint8_t *HAL_GMAC_GetTXBuffer(struct GMAC_HANDLE *pGMAC) return pGMAC->txBuf + pGMAC->txDescIdx * HAL_GMAC_MAX_PACKET_SIZE; } +uint8_t *HAL_GMAC_GetTXBufferDMA(struct GMAC_HANDLE *pGMAC) +{ + HAL_ASSERT(pGMAC != NULL); + + return pGMAC->txBuf_dma + pGMAC->txDescIdx * HAL_GMAC_MAX_PACKET_SIZE; +} /** * @brief Get current RX buffer. * @param pGMAC: pointer to a GMAC_HANDLE structure that contains @@ -1949,6 +1964,13 @@ uint8_t *HAL_GMAC_GetRXBuffer(struct GMAC_HANDLE *pGMAC) return pGMAC->rxBuf + pGMAC->rxDescIdx * HAL_GMAC_MAX_PACKET_SIZE; } +uint8_t *HAL_GMAC_GetRXBufferDMA(struct GMAC_HANDLE *pGMAC) +{ + HAL_ASSERT(pGMAC != NULL); + + return pGMAC->rxBuf_dma + pGMAC->rxDescIdx * HAL_GMAC_MAX_PACKET_SIZE; +} + /** * @brief Send a packet with the length, clean packet' dcached memory before send. * @param pGMAC: pointer to a GMAC_HANDLE structure that contains @@ -1977,8 +1999,8 @@ HAL_Status HAL_GMAC_Send(struct GMAC_HANDLE *pGMAC, void *packet, pGMAC->txDescIdx++; pGMAC->txDescIdx %= pGMAC->txSize; - - desc->des0 = (uint64_t)packet; + + desc->des0 = (uint32_t)(uint64_t)packet; desc->des1 = 0; desc->des2 = length; /* @@ -1986,9 +2008,8 @@ HAL_Status HAL_GMAC_Send(struct GMAC_HANDLE *pGMAC, void *packet, * writes to the rest of the descriptor too. */ desc->des3 = GMAC_DESC3_OWN | GMAC_DESC3_FD | GMAC_DESC3_LD; - WRITE_REG(pGMAC->pReg->DMA_CH0_TXDESC_TAIL_POINTER, - (uint64_t)(pGMAC->txDescs + pGMAC->txDescIdx)); + (uint32_t)(uint64_t)(pGMAC->txDescs_dma + pGMAC->txDescIdx)); for (i = 0; i < 1000000; i++) { if (!(desc->des3 & GMAC_DESC3_OWN)) { @@ -2025,6 +2046,7 @@ uint8_t *HAL_GMAC_Recv(struct GMAC_HANDLE *pGMAC, int32_t *length) *length = 0; desc = pGMAC->rxDescs + pGMAC->rxDescIdx; + HAL_DBG("Rx at %p\n", desc->des0); des3 = desc->des3; if (des3 & GMAC_DESC3_OWN) { HAL_DBG("%s: RX packet not available\n", __func__); @@ -2072,18 +2094,22 @@ uint8_t *HAL_GMAC_Recv(struct GMAC_HANDLE *pGMAC, int32_t *length) void HAL_GMAC_CleanRX(struct GMAC_HANDLE *pGMAC) { struct GMAC_Desc *desc; + struct GMAC_Desc *desc_dma; HAL_ASSERT(pGMAC != NULL); /* Get the pointer on the ith member of the Tx Desc list */ desc = pGMAC->rxDescs + pGMAC->rxDescIdx; - desc->des0 = (uint64_t)(pGMAC->rxBuf + (pGMAC->rxDescIdx * + desc->des0 = (uint32_t)(uint64_t)(pGMAC->rxBuf_dma + (pGMAC->rxDescIdx * HAL_GMAC_MAX_PACKET_SIZE)); desc->des1 = 0; desc->des2 = 0; desc->des3 = GMAC_DESC3_OWN | GMAC_DESC3_BUF1V | GMAC_DESC3_IOC; - WRITE_REG(pGMAC->pReg->DMA_CH0_RXDESC_TAIL_POINTER, (uint64_t)desc); + HAL_DBG("Clean buff %p\n", desc->des0); + desc_dma = pGMAC->rxDescs_dma + pGMAC->rxDescIdx; + HAL_DBG("Clean desc %p\n", desc_dma); + WRITE_REG(pGMAC->pReg->DMA_CH0_RXDESC_TAIL_POINTER, (uint32_t)(uint64_t)desc_dma); pGMAC->rxDescIdx++; pGMAC->rxDescIdx %= pGMAC->rxSize; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_gmac_3568.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_gmac_3568.c similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_gmac_3568.c rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_gmac_3568.c diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_gpio.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_gpio.c similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_gpio.c rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_gpio.c diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_pinctrl_v2.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_pinctrl_v2.c similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_pinctrl_v2.c rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_pinctrl_v2.c diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_timer.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_timer.c similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_timer.c rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_timer.c diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/system_rk3568.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/system_rk3568.c similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/system_rk3568.c rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/system_rk3568.c diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/test_gmac.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/test_gmac.c similarity index 71% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/test_gmac.c rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/test_gmac.c index 740b49e30..35d9bb0fa 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/test_gmac.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/test_gmac.c @@ -6,7 +6,7 @@ #include "hal_bsp.h" #include "hal_base.h" #include "hal_gmac.h" - +#include "usyscall.h" #if (defined(HAL_GMAC_MODULE_ENABLED) || defined(HAL_GMAC1000_MODULE_ENABLED)) /*************************** GMAC DRIVER ****************************/ @@ -14,11 +14,6 @@ /***************************** MACRO Definition ******************************/ #define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') -#define CONFIG_SYS_NONCACHED_MEMORY (4 << 20) /* 4M */ - -/* 1MB granularity */ -#define MMU_SECTION_SIZE (1 << 20) - /***************************** Structure Definition **************************/ /***************************** Function Declare ******************************/ @@ -51,7 +46,7 @@ #define BMCR_RESET 0x8000 /* Reset to default state */ #define BMCR_SPEED10 0x0000 /* Select 10Mbps */ -#define GMAC_TEST_TIMES 1600 +#define GMAC_TEST_TIMES 16 /********************* Private Structure Definition **************************/ /* GMAC consumer config data. */ @@ -74,33 +69,23 @@ struct GMAC_ETH_CONFIG { int32_t rxDelay; struct GMAC_Desc *txDescs; + struct GMAC_Desc *txDescs_dma; struct GMAC_Desc *rxDescs; + struct GMAC_Desc *rxDescs_dma; uint8_t *txBuff; + uint8_t *txBuff_dma; uint8_t *rxBuff; + uint8_t *rxBuff_dma; /* MAC address info, hw address */ uint8_t macAddr[6]; }; /********************* Private Variable Definition ***************************/ -#ifdef NC_MEM_BASE -static const unsigned long os_no_cache_start = (unsigned long)NC_MEM_BASE; -#else -static const unsigned long os_no_cache_start = 0; -#endif -/* - * Reserve one MMU section worth of address space below the malloc() area that - * will be mapped uncached. - */ -static unsigned long noncached_start; -static unsigned long noncached_end; -static unsigned long noncached_next; -static unsigned int m_nocachemem_inited = 0; - -static uint8_t dstAddr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; +static uint8_t dstAddr[6] = { 0x00, 0x0C, 0x29, 0xf8, 0x7a, 0x6b }; #if defined(HAL_GMAC_MODULE_ENABLED) && defined(SOC_RK3568) static struct GMAC_ETH_CONFIG ethConfigTable[] = @@ -113,31 +98,30 @@ static struct GMAC_ETH_CONFIG ethConfigTable[] = .extClk = false, - .resetGpioBank = GPIO2, - .resetGpioNum = GPIO_PIN_D3, + .resetGpioBank = GPIO3, + .resetGpioNum = GPIO_PIN_A4, .resetDelayMs = { 0, 20, 100 }, - .txDelay = 0x3C, - .rxDelay = 0x2f, + .txDelay = 0x2f, + .rxDelay = 0x00, }, -#ifdef HAL_GMAC1 - { - .halDev = &g_gmac1Dev, - .mode = PHY_INTERFACE_MODE_RGMII, - .maxSpeed = 1000, - .phyAddr = 1, - .extClk = false, + // { + // .halDev = &g_gmac1Dev, + // .mode = PHY_INTERFACE_MODE_RGMII, + // .maxSpeed = 1000, + // .phyAddr = 1, - .resetGpioBank = GPIO2, - .resetGpioNum = GPIO_PIN_D1, - .resetDelayMs = { 0, 20, 100 }, + // .extClk = false, - .txDelay = 0x4f, - .rxDelay = 0x26, - }, -#endif + // .resetGpioBank = GPIO4, + // .resetGpioNum = GPIO_PIN_B6, + // .resetDelayMs = { 0, 20, 100 }, + + // .txDelay = 0x4f, + // .rxDelay = 0x26, + // }, }; #endif @@ -223,31 +207,6 @@ static void Dump_Regs(struct GMAC_HANDLE *pGMAC) } } -static void PHY_Read(struct GMAC_HANDLE *pGMAC, uint32_t phyReg) -{ - int data; - - data = HAL_GMAC_MDIORead(pGMAC, pGMAC->phyConfig.phyAddress, phyReg); - if (data >= 0) { - printf("PHY_Read: %02lX --> %08X\n", phyReg, data); - } else { - printf("PHY_Read: %02lX --> faild\n", phyReg); - } -} - -static void PHY_Write(struct GMAC_HANDLE *pGMAC, uint32_t phyReg, uint32_t data) -{ - // struct GMAC_HANDLE *pGMAC; - int status; - - status = HAL_GMAC_MDIOWrite(pGMAC, pGMAC->phyConfig.phyAddress, phyReg, data); - if (!status) { - printf("PHY_Write: %02lX --> %08lX\n", phyReg, data); - } else { - printf("PHY_Write: %02lX --> faild\n", phyReg); - } -} - static void PHY_Dump(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE *pGMAC) { int data, i; @@ -277,14 +236,11 @@ static void GMAC_PHY_Reset(struct GMAC_ETH_CONFIG *config) HAL_GPIO_SetPinLevel(config->resetGpioBank, config->resetGpioNum, GPIO_HIGH); - HAL_DelayMs(config->resetDelayMs[0]); - HAL_GPIO_SetPinLevel(config->resetGpioBank, config->resetGpioNum, GPIO_LOW); HAL_DelayMs(config->resetDelayMs[1]); - HAL_GPIO_SetPinLevel(config->resetGpioBank, config->resetGpioNum, GPIO_HIGH); @@ -294,15 +250,12 @@ static void GMAC_PHY_Reset(struct GMAC_ETH_CONFIG *config) static inline void NET_Random_ETHAddr(uint8_t *addr) { - unsigned int seed = HAL_TIMER_GetCount(SYS_TIMER) | 0xffffffff; - uint8_t i; - - for (i = 0; i < 6; i++) { - addr[i] = rand(); - } - - addr[0] &= 0xfe; /* clear multicast bit */ - addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ + addr[0] = 0xe6; + addr[1] = 0x47; + addr[2] = 0xcd; + addr[3] = 0x20; + addr[4] = 0xcf; + addr[5] = 0xd9; } static inline void NET_Random_Package(uint8_t *addr, uint16_t len) @@ -326,7 +279,7 @@ static void PHY_Update_Links(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE *pG return; } - HAL_DelayMs(7000); + HAL_DelayMs(10000); status = HAL_GMAC_PHYUpdateLink(pGMAC); if (status == HAL_OK) { @@ -383,74 +336,42 @@ static HAL_Status GMAC_ETH_IRQ(struct GMAC_HANDLE *pGMAC) /* rt_interrupt_leave(); */ } -static HAL_Status noncached_init(void) -{ - unsigned long start, end; - size_t size; - if (os_no_cache_start <= 0) { - printf("Noncached_init failed, plase defined no cached memort\n"); - return -1; - } - - start = HAL_GMAC_ALIGN(os_no_cache_start, 64); - size = HAL_GMAC_ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE); - end = start + size; - - noncached_start = start; - noncached_end = end; - noncached_next = start; - m_nocachemem_inited = 1; - - return 0; -} - -static unsigned long noncached_alloc(size_t size, size_t align) -{ - if (!m_nocachemem_inited) { - if (noncached_init()) - return (unsigned long)NULL; - } - - unsigned long next = HAL_GMAC_ALIGN(noncached_next, align); - - if (next >= noncached_end || (noncached_end - next) < size) { - return 0; - } - - noncached_next = next + size; - - return next; -} - -static void *malloc_align(size_t size, size_t align) +static void *malloc_align(size_t size, size_t align, uintptr_t va, uintptr_t *pa) { void *align_ptr; - void *ptr; + // void *ptr; size_t align_size; /* align the alignment size to 4 byte */ align = ((align + 0x03) & ~0x03); /* get total aligned size */ - align_size = ((size + 0x03) & ~0x03) + align; + align_size = ((size + 0x03) & ~0x03); /* allocate memory block from heap */ - ptr = malloc(align_size); - if (ptr != NULL) { - /* the allocated memory block is aligned */ - if (((uint64_t)ptr & (align - 1)) == 0) { - align_ptr = (void *)((uint64_t)ptr + align); - } else { - align_ptr = (void *)(((uint64_t)ptr + (align - 1)) & ~(align - 1)); - } + HAL_DBG("size: %d, align:%d\n",align_size, align); + // ptr = malloc(align_size); - /* set the pointer before alignment pointer to the real pointer */ - *((uint64_t *)((uint64_t)align_ptr - sizeof(void *))) = (uint64_t)ptr; - - ptr = align_ptr; + if (naive_mmap(&va, pa, align_size, true) < 0){ + HAL_DBG("Alloc failed\n"); } + // printf("%p,%p\n",(void *)va, *pa); + // void* ptr = (void *)va; + // if (ptr != 0) { + // /* the allocated memory block is aligned */ + // if (((uint64_t)ptr & (align - 1)) == 0) { + // align_ptr = (void *)((uint64_t)ptr + align); + // } else { + // align_ptr = (void *)(((uint64_t)ptr + (align - 1)) & ~(align - 1)); + // } - return ptr; + // /* set the pointer before alignment pointer to the real pointer */ + // *((uint64_t *)((uint64_t)align_ptr - sizeof(void *))) = (uint64_t)ptr; + + // ptr = align_ptr; + // } + + return (void *)va; } static void free_align(void *ptr) @@ -459,6 +380,7 @@ static void free_align(void *ptr) real_ptr = (void *)*(uint64_t *)((uint64_t)ptr - sizeof(void *)); free(real_ptr); + } /********************* Public Function Definition ****************************/ @@ -470,6 +392,7 @@ static HAL_Status GMAC_Send_Test(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE HAL_Status status; if (!pGMAC->phyStatus.link) { + HAL_DBG("pGMAC->phyStatus.link: %d", pGMAC->phyStatus.link); return -1; } @@ -479,6 +402,7 @@ static HAL_Status GMAC_Send_Test(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE } ptr = (uint8_t *)HAL_GMAC_GetTXBuffer(pGMAC); + HAL_DBG("txPtr:%p\n", ptr); memcpy(ptr, dstAddr, 6); memcpy(ptr + 6, eth->macAddr, 6); ptr[12] = 0x40; @@ -493,14 +417,16 @@ static HAL_Status GMAC_Send_Test(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE } /* dump packages */ - Dump_Hex("Tx", ptr, len); + // Dump_Hex("Tx", ptr, len); // HAL_DCACHE_CleanByRange((uint64_t)ptr, len); - status = HAL_GMAC_Send(pGMAC, ptr, len); + uint8_t * ptr_dma = (uint8_t *)HAL_GMAC_GetTXBufferDMA(pGMAC); + status = HAL_GMAC_Send(pGMAC, ptr_dma, len); if (status) { printf("GMAC send failed: %d\n", status); } - + + print_desc(pGMAC); return status; } @@ -511,12 +437,14 @@ static uint16_t GMAC_Recv_Test(struct GMAC_HANDLE *pGMAC) int32_t size; if (!pGMAC->phyStatus.link) { + HAL_DBG("pGMAC->phyStatus.link: %d", pGMAC->phyStatus.link); return -1; } status = GMAC_ETH_IRQ(pGMAC); ptr = HAL_GMAC_Recv(pGMAC, &size); while (status && ptr) { + print_desc(pGMAC); if (size > 0 && ptr) { /* dump packages */ Dump_Hex("Rx", ptr, size); @@ -529,35 +457,59 @@ static uint16_t GMAC_Recv_Test(struct GMAC_HANDLE *pGMAC) } ptr = HAL_GMAC_Recv(pGMAC, &size); } - return 0; } static HAL_Status GMAC_Memory_Init(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE *pGMAC) -{ - eth->rxDescs = (struct GMAC_Desc *)noncached_alloc(GMAC_DESC_RX_SIZE, ARCH_DMA_MINALIGN); - eth->txDescs = (struct GMAC_Desc *)noncached_alloc(GMAC_DESC_TX_SIZE, ARCH_DMA_MINALIGN); +{ + uintptr_t rx_va = 0x1000000000, rx_pa = 0; + if (naive_mmap(&rx_va, &rx_pa, GMAC_DESC_RX_SIZE, true) < 0){ + HAL_DBG("RX Desc alloc failed\n"); + } + eth->rxDescs = (struct GMAC_Desc *)0x1000000000; + eth->rxDescs_dma = (struct GMAC_Desc *)rx_pa; - if (!eth->rxDescs || !eth->txDescs) + uintptr_t tx_va = 0x1000400000, tx_pa = 0; + if (naive_mmap(&tx_va, &tx_pa, GMAC_DESC_TX_SIZE, true) < 0){ + HAL_DBG("TX Desc alloc failed\n"); + } + eth->txDescs = (struct GMAC_Desc *)0x1000400000; + eth->txDescs_dma = (struct GMAC_Desc *)tx_pa; + + if (!eth->rxDescs || !eth->txDescs_dma || + !eth->txDescs || !eth->txDescs_dma){ return -1; + } + + HAL_DBG("rx:%p, %p\n",eth->rxDescs, eth->rxDescs_dma); + HAL_DBG("tx:%p, %p\n",eth->txDescs, eth->txDescs_dma); - eth->rxBuff = malloc_align(GMAC_RX_BUFFER_SIZE, ARCH_DMA_MINALIGN); - eth->txBuff = malloc_align(GMAC_TX_BUFFER_SIZE, ARCH_DMA_MINALIGN); - - if (!eth->rxBuff || !eth->txBuff) + uintptr_t rxbuf_va = 0x1000800000, rxbuf_pa = 0; + uintptr_t txbuf_va = 0x1000C00000, txbuf_pa = 0; + eth->rxBuff = malloc_align(GMAC_RX_BUFFER_SIZE, ARCH_DMA_MINALIGN, rxbuf_va, &rxbuf_pa); + eth->rxBuff = (void *)0x1000800000; + eth->rxBuff_dma = (void *)rxbuf_pa; + eth->txBuff = malloc_align(GMAC_TX_BUFFER_SIZE, ARCH_DMA_MINALIGN, txbuf_va, &txbuf_pa); + eth->txBuff = (void *)0x1000C00000; + eth->txBuff_dma = (void *)txbuf_pa; + + if (!eth->rxBuff || !eth->txBuff || + !eth->rxBuff_dma || !eth->txBuff_dma){ return -1; - + } + HAL_DBG("rx_buff:%p,%p\n",eth->rxBuff, eth->rxBuff_dma); + HAL_DBG("tx_buff:%p,%p,\n",eth->txBuff, eth->txBuff_dma); + HAL_DBG("GMAC_DESC_RX_SIZE:%d\n", GMAC_DESC_RX_SIZE); + HAL_DBG("GMAC_RX_BUFFER_SIZE:%d\n", GMAC_RX_BUFFER_SIZE); memset(eth->rxDescs, 0, GMAC_DESC_RX_SIZE); memset(eth->txDescs, 0, GMAC_DESC_TX_SIZE); - memset(eth->rxBuff, 0, GMAC_RX_BUFFER_SIZE); // HAL_DCACHE_InvalidateByRange((uint64_t)eth->rxBuff, GMAC_RX_BUFFER_SIZE); - memset(eth->txBuff, 0, GMAC_TX_BUFFER_SIZE); // HAL_DCACHE_CleanByRange((uint64_t)eth->txBuff, GMAC_TX_BUFFER_SIZE); - HAL_GMAC_DMARxDescInit(pGMAC, eth->rxDescs, eth->rxBuff, GMAC_DESCRIPTORS_RX); - HAL_GMAC_DMATxDescInit(pGMAC, eth->txDescs, eth->txBuff, GMAC_DESCRIPTORS_TX); + HAL_GMAC_DMARxDescInit(pGMAC, eth->rxDescs, eth->rxDescs_dma, eth->rxBuff, eth->rxBuff_dma, GMAC_DESCRIPTORS_RX); + HAL_GMAC_DMATxDescInit(pGMAC, eth->txDescs, eth->txDescs_dma, eth->txBuff, eth->txBuff_dma, GMAC_DESCRIPTORS_TX); print_desc(pGMAC); @@ -619,7 +571,6 @@ static HAL_Status GMAC_Init(uint8_t id) } /*************************** GMAC TEST ****************************/ -#define GMAC_MAX_DEVICES 2 #ifdef SOC_RK3568 /** @@ -631,8 +582,8 @@ static void GMAC0_Iomux_Config(void) HAL_PINCTRL_SetIOMUX(GPIO_BANK2, GPIO_PIN_B6, /* gmac0_rxd0 */ PIN_CONFIG_MUX_FUNC1); - HAL_PINCTRL_SetIOMUX(GPIO_BANK2, + GPIO_PIN_C0 | ///* eth0_refclko25m */ GPIO_PIN_C3 | /* gmac0_mdc */ GPIO_PIN_C4 | /* gmac0_mdio */ GPIO_PIN_C0 | /* gmac0_rxdvcrs */ @@ -643,7 +594,6 @@ static void GMAC0_Iomux_Config(void) GPIO_PIN_A7 | /* gmac0_txd3 */ GPIO_PIN_A5, /* gmac0_rxclk */ PIN_CONFIG_MUX_FUNC2); - HAL_PINCTRL_SetIOMUX(GPIO_BANK2, GPIO_PIN_B3 | /* gmac0_txd0 */ GPIO_PIN_B4 | /* gmac0_txd1 */ @@ -658,16 +608,6 @@ static void GMAC0_Iomux_Config(void) GPIO_PIN_B0, PIN_CONFIG_MUX_FUNC2 | PIN_CONFIG_DRV_LEVEL1); -#if 0 - /* io-domian: 1.8v or 3.3v for vccio4 */ - WRITE_REG_MASK_WE(GRF->IO_VSEL0, - GRF_IO_VSEL0_POC_VCCIO4_SEL18_MASK, - (1 << GRF_IO_VSEL0_POC_VCCIO4_SEL18_SHIFT)); - - WRITE_REG_MASK_WE(GRF->IO_VSEL1, - GRF_IO_VSEL1_POC_VCCIO4_SEL33_MASK, - (0 << GRF_IO_VSEL1_POC_VCCIO4_SEL33_SHIFT)); -#endif } #endif @@ -682,75 +622,131 @@ static void GMAC_Iomux_Config(uint8_t id) } - - - - /*************************** GMAC TEST MAIN ****************************/ +#include "usyscall.h" + +// IPC_SERVER_INTERFACE(Ipc_intr, 1); +// IPC_SERVER_REGISTER_INTERFACES(IpIntrHandler, 1, Ipc_intr); + int main() { struct GMAC_ETH_CONFIG *eth; struct GMAC_HANDLE *pGMAC; int32_t bus, num = 0, i; - HAL_DBG("\n"); - HAL_DBG("%s\n", __func__); - HAL_DBG(" GMAC Test:\n"); + HAL_DBG("GMAC Test:\n"); num = sizeof(ethConfigTable) / sizeof(struct GMAC_ETH_CONFIG); - HAL_DBG(" GMAC Num: %ld\n", num); + HAL_DBG("GMAC Num: %ld\n", num); for (bus = 0; bus < num; bus++) { eth = ðConfigTable[bus]; + HAL_DBG("new pGmac\n"); if (eth) { pGMAC = ð->instance; } else { return -1; } + HAL_DBG("map GMAC0\n"); + if (!mmap(0x2000000000ULL+ GMAC0_BASE, GMAC0_BASE, 0x10000, true)) { + printf("eth_hal: mmap GMAC0(%8x) failed\n", GMAC0); + exit(1); + } + HAL_DBG("map GPIO2\n"); + if (!mmap(0x2000000000ULL + GPIO2_BASE, GPIO2_BASE, 0x10000, true)) { + printf("eth_hal: mmap GPIO2(%8x) failed\n", GPIO2); + exit(1); + } + HAL_DBG("map GPIO3\n"); + if (!mmap(0x2000000000ULL + GPIO3_BASE, GPIO3_BASE, 0x10000, true)) { + printf("eth_hal: mmap GPIO2(%8x) failed\n", GPIO2); + exit(1); + } + if (!mmap(0x2000000000ULL + GRF_BASE, GRF_BASE, 0x50000, true)) { + printf("eth_hal: mmap GRF(%8x) failed\n", GRF); + exit(1); + } + + if (!mmap(0x2000000000ULL + CRU_BASE, CRU_BASE, 0x10000, true)) { + printf("eth_hal: mmap GRF(%8x) failed\n", GRF); + exit(1); + } + if (!mmap(0x2000000000ULL + TIMER5_BASE, CRU_BASE, 32, true)) { + printf("eth_hal: mmap GRF(%8x) failed\n", GRF); + exit(1); + } + if (!mmap(0x2000000000ULL + PMUCRU_BASE, PMUCRU_BASE, 0x10000, true)) { + printf("eth_hal: mmap GRF(%8x) failed\n", GRF); + exit(1); + } + + HAL_DBG("config iomux\n"); /* ionmux */ GMAC_Iomux_Config(bus); - + HAL_DBG("config cru\n"); HAL_CRU_ClkEnable(eth->halDev->pclkGateID); HAL_CRU_ClkEnable(eth->halDev->clkGateID); - + /* Register irq */ - + // register_irq(eth->halDev->irqNum, ); /* PHY reset */ + HAL_DBG("reset phy\n"); GMAC_PHY_Reset(eth); - + /* GMAC Init */ + HAL_DBG("init gmac\n"); GMAC_Init(bus); + HAL_DBG("init memory\n"); GMAC_Memory_Init(eth, pGMAC); - + /* Enable GMAC and DMA transmission and reception */ + HAL_DBG("start gmac\n"); HAL_GMAC_Start(pGMAC, eth->macAddr); - + // print_desc(pGMAC); /* Update links information */ + HAL_DBG("phy update link\n"); PHY_Update_Links(eth, pGMAC, bus); - + // print_desc(pGMAC); /* Dump MAC Regs */ Dump_Regs(pGMAC); /* Dump PHY Regs */ - PHY_Dump(eth, pGMAC); - + // PHY_Dump(eth, pGMAC); + HAL_DBG("Init Down\n"); for (i = 0; i < GMAC_TEST_TIMES; i++) { + HAL_DBG("TEST Send %d\n", i); /* GMAC Send 64 bytes */ - GMAC_Send_Test(eth, pGMAC, 64); + // GMAC_Send_Test(eth, pGMAC, 64); /* GMAC Send 1500 bytes */ GMAC_Send_Test(eth, pGMAC, 1500); HAL_DelayMs(1000); - + HAL_DBG("TEST Recv %d\n", i); /* GMAC Recv */ GMAC_Recv_Test(pGMAC); } - + Dump_Regs(pGMAC); HAL_CRU_ClkDisable(eth->halDev->pclkGateID); HAL_CRU_ClkDisable(eth->halDev->clkGateID); - free_align(eth->txBuff); - free_align(eth->rxBuff); + // free_align(eth->txBuff); + // free_align(eth->rxBuff); + HAL_DBG("done\n"); } + exit(0); return 0; } + +// typedef void (*isr_handler_t)(int vector, void *param); +// typedef void (*NVIC_IRQHandler)(void); + +// isr_handler_t interrupt_install(int vector, +// isr_handler_t handler, +// void *param, +// const char *name) +// { + +// HAL_NVIC_SetIRQHandler(vector, (NVIC_IRQHandler)handler); +// return handler; +// } + diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_base.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_base.h similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_base.h rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_base.h diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_bsp.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_bsp.h similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_bsp.h rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_bsp.h diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_conf.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_conf.h similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_conf.h rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_conf.h diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_cru.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_cru.h similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_cru.h rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_cru.h diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_debug.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_debug.h similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_debug.h rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_debug.h diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_def.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_def.h similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_def.h rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_def.h diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_driver.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_driver.h similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_driver.h rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_driver.h diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_gmac.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_gmac.h similarity index 95% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_gmac.h rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_gmac.h index c7fbfb38c..5f6c731e4 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_gmac.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_gmac.h @@ -269,9 +269,13 @@ struct GMAC_HANDLE { struct GMAC_DMAStats extraStatus; /**< GMAC DMA transfer status */ struct GMAC_Desc *rxDescs; /**< First Rx descriptor pointer */ + struct GMAC_Desc *rxDescs_dma; struct GMAC_Desc *txDescs; /**< First Tx descriptor pointer */ + struct GMAC_Desc *txDescs_dma; uint8_t *txBuf; /**< First Tx buffer pointer */ + uint8_t *txBuf_dma; uint8_t *rxBuf; /**< First Tx buffer pointer */ + uint8_t *rxBuf_dma; uint32_t txDescIdx; /**< Current Tx descriptor index */ uint32_t rxDescIdx; /**< Current Rx descriptor pointer */ uint32_t txSize; /**< Tx descriptor size*/ @@ -307,17 +311,21 @@ void HAL_GMAC_EnableDmaIRQ(struct GMAC_HANDLE *pGMAC); void HAL_GMAC_DisableDmaIRQ(struct GMAC_HANDLE *pGMAC); HAL_Status HAL_GMAC_DMATxDescInit(struct GMAC_HANDLE *pGMAC, struct GMAC_Desc *txDescs, - uint8_t *txBuff, uint32_t txBuffCount); + struct GMAC_Desc *txDescs_dma, + uint8_t *txBuff, uint8_t *txBuff_dma, uint32_t txBuffCount); HAL_Status HAL_GMAC_DMARxDescInit(struct GMAC_HANDLE *pGMAC, struct GMAC_Desc *rxDescs, - uint8_t *rxBuff, uint32_t rxBuffCount); + struct GMAC_Desc *rxDescs_dma, + uint8_t *rxBuff, uint8_t *rxBuff_dma, uint32_t rxBuffCount); eGMAC_IRQ_Status HAL_GMAC_IRQHandler(struct GMAC_HANDLE *pGMAC); HAL_Status HAL_GMAC_AdjustLink(struct GMAC_HANDLE *pGMAC, int32_t txDelay, int32_t rxDelay); uint32_t HAL_GMAC_GetTXIndex(struct GMAC_HANDLE *pGMAC); uint32_t HAL_GMAC_GetRXIndex(struct GMAC_HANDLE *pGMAC); uint8_t *HAL_GMAC_GetTXBuffer(struct GMAC_HANDLE *pGMAC); +uint8_t *HAL_GMAC_GetTXBufferDMA(struct GMAC_HANDLE *pGMAC); uint8_t *HAL_GMAC_GetRXBuffer(struct GMAC_HANDLE *pGMAC); +uint8_t *HAL_GMAC_GetRXBufferDMA(struct GMAC_HANDLE *pGMAC); HAL_Status HAL_GMAC_Send(struct GMAC_HANDLE *pGMAC, void *packet, uint32_t length); uint8_t *HAL_GMAC_Recv(struct GMAC_HANDLE *pGMAC, int32_t *length); diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_gpio.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_gpio.h similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_gpio.h rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_gpio.h diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_list.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_list.h similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_list.h rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_list.h diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_pinctrl.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_pinctrl.h similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_pinctrl.h rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_pinctrl.h diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_pm.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_pm.h similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_pm.h rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_pm.h diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_timer.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_timer.h similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_timer.h rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_timer.h diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/rk3568.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/rk3568.h similarity index 99% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/rk3568.h rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/include/rk3568.h index e7c2c2163..09e399c20 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/rk3568.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/rk3568.h @@ -1235,11 +1235,11 @@ struct INTMUX_REG { /****************************************************************************************/ /* Module Variable Define */ -#define GRF ((struct GRF_REG *) GRF_BASE) -#define PMUCRU ((struct PMUCRU_REG *) PMUCRU_BASE) +#define GRF ((struct GRF_REG *) (GRF_BASE + 0x2000000000ULL)) +#define PMUCRU ((struct PMUCRU_REG *) (PMUCRU_BASE + 0x2000000000ULL)) #define TIMER6 ((struct TIMER_REG *) TIMER6_BASE) #define TIMER7 ((struct TIMER_REG *) TIMER7_BASE) -#define CRU ((struct CRU_REG *) CRU_BASE) +#define CRU ((struct CRU_REG *) (CRU_BASE + 0x2000000000ULL)) #define I2C0 ((struct I2C_REG *) I2C0_BASE) #define UART0 ((struct UART_REG *) UART0_BASE) #define GPIO0 ((struct GPIO_REG *) GPIO0_BASE) @@ -1247,7 +1247,7 @@ struct INTMUX_REG { #define PMU ((struct PMU_REG *) PMU_BASE) #define SPINLOCK ((struct SPINLOCK_REG *) SPINLOCK_BASE) #define GMAC1 ((struct GMAC_REG *) GMAC1_BASE) -#define GMAC0 ((struct GMAC_REG *) GMAC0_BASE) +#define GMAC0 ((struct GMAC_REG *) (GMAC0_BASE + 0x2000000000ULL)) #define MMC ((struct MMC_REG *) MMC_BASE) #define FSPI ((struct FSPI_REG *) FSPI_BASE) #define DMA0 ((struct DMA_REG *) DMA0_BASE) @@ -1265,7 +1265,7 @@ struct INTMUX_REG { #define TIMER2 ((struct TIMER_REG *) TIMER2_BASE) #define TIMER3 ((struct TIMER_REG *) TIMER3_BASE) #define TIMER4 ((struct TIMER_REG *) TIMER4_BASE) -#define TIMER5 ((struct TIMER_REG *) TIMER5_BASE) +#define TIMER5 ((struct TIMER_REG *) (TIMER5_BASE + 0x2000000000ULL)) #define WDT ((struct WDT_REG *) WDT_BASE) #define SPI0 ((struct SPI_REG *) SPI0_BASE) #define SPI1 ((struct SPI_REG *) SPI1_BASE) @@ -1286,8 +1286,8 @@ struct INTMUX_REG { #define TSADC ((struct TSADC_REG *) TSADC_BASE) #define SARADC ((struct SARADC_REG *) SARADC_BASE) #define GPIO1 ((struct GPIO_REG *) GPIO1_BASE) -#define GPIO2 ((struct GPIO_REG *) GPIO2_BASE) -#define GPIO3 ((struct GPIO_REG *) GPIO3_BASE) +#define GPIO2 ((struct GPIO_REG *) (GPIO2_BASE + 0x2000000000ULL)) +#define GPIO3 ((struct GPIO_REG *) (GPIO3_BASE + 0x2000000000ULL)) #define GPIO4 ((struct GPIO_REG *) GPIO4_BASE) #define MBOX0 ((struct MBOX_REG *) MBOX0_BASE) #define INTMUX ((struct INTMUX_REG *) INTMUX_BASE) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/soc.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/soc.h similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/soc.h rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/include/soc.h diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/system_rk3568.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/system_rk3568.h similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/system_rk3568.h rename to Ubiquitous/XiZi_AIoT/services/drivers/3568/include/system_rk3568.h diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/Makefile index a84ea238f..1c8d601c7 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/drivers/Makefile @@ -1,4 +1,4 @@ -SRC_DIR := $(BOARD) usb rk-3568 +SRC_DIR := $(BOARD) include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/clock/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/clock/Makefile index ab423f013..cf73c47ca 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/clock/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/clock/Makefile @@ -8,10 +8,10 @@ toolchain ?= arm-xilinx-eabi- cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie user_ldflags = -N -Ttext 0 endif -ifeq ($(BOARD), ok1028a-c) +ifeq ($(BOARD), 3568) toolchain ?= aarch64-none-elf- user_ldflags = -N -Ttext 0 -cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie endif cc = ${toolchain}gcc ld = ${toolchain}g++ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/enet/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/enet/Makefile index 40096c142..0a382c704 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/enet/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/enet/Makefile @@ -9,14 +9,8 @@ ld = ${toolchain}g++ objdump = ${toolchain}objdump user_ldflags = -N -Ttext 0 -cflags = -std=c11 -march=armv7-a -mcpu=cortex-a9 -mtune=cortex-a9 -g \ - -Wno-unused -Wno-format -fno-common -ffreestanding -fno-builtin -static \ - -Wno-unaligned-access -fdce -Wall -Werror -Wno-uninitialized -Wno-strict-aliasing -fdiagnostics-show-option \ - -mapcs -marm -mfpu=neon -ftree-vectorize -fno-math-errno -funsafe-math-optimizations -fno-signed-zeros -mfloat-abi=softfp \ - -fno-omit-frame-pointer -fno-stack-protector -fno-pie - -# cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic \ -# -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic \ + -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie c_useropts = -O0 diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/gpio/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/gpio/Makefile index 58a266a78..9e260c4b4 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/gpio/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/gpio/Makefile @@ -8,10 +8,10 @@ toolchain ?= arm-xilinx-eabi- cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie user_ldflags = -N -Ttext 0 endif -ifeq ($(BOARD), ok1028a-c) +ifeq ($(BOARD), 3568) toolchain ?= aarch64-none-elf- user_ldflags = -N -Ttext 0 -cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie endif cc = ${toolchain}gcc diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/lib/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/lib/Makefile index 654685df5..6dfe8d3e5 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/lib/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/lib/Makefile @@ -8,10 +8,10 @@ toolchain ?= arm-xilinx-eabi- cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie user_ldflags = -N -Ttext 0 endif -ifeq ($(BOARD), ok1028a-c) +ifeq ($(BOARD), 3568) toolchain ?= aarch64-none-elf- user_ldflags = -N -Ttext 0 -cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie endif cc = ${toolchain}gcc diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/ok1028a-c/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/ok1028a-c/Makefile deleted file mode 100644 index b14224115..000000000 --- a/Ubiquitous/XiZi_AIoT/services/drivers/ok1028a-c/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -SRC_DIR := - -include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/fs/fs_server/Makefile b/Ubiquitous/XiZi_AIoT/services/fs/fs_server/Makefile index d167f1015..9267ae0a5 100644 --- a/Ubiquitous/XiZi_AIoT/services/fs/fs_server/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/fs/fs_server/Makefile @@ -9,10 +9,10 @@ user_ldflags = --start-group,-lgcc,-lc,--end-group cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie #cflags = -Wall -g -std=c11 endif -ifeq ($(BOARD), ok1028a-c) +ifeq ($(BOARD), 3568) toolchain ?= aarch64-none-elf- user_ldflags = -N -Ttext 0 -cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie endif cc = ${toolchain}gcc diff --git a/Ubiquitous/XiZi_AIoT/services/fs/libfs/Makefile b/Ubiquitous/XiZi_AIoT/services/fs/libfs/Makefile index 0301ce421..dbbeb93e9 100644 --- a/Ubiquitous/XiZi_AIoT/services/fs/libfs/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/fs/libfs/Makefile @@ -8,10 +8,10 @@ toolchain ?= arm-xilinx-eabi- cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie user_ldflags = -N -Ttext 0 endif -ifeq ($(BOARD), ok1028a-c) +ifeq ($(BOARD), 3568) toolchain ?= aarch64-none-elf- user_ldflags = -N -cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie endif cc = ${toolchain}gcc diff --git a/Ubiquitous/XiZi_AIoT/services/lib/ipc/Makefile b/Ubiquitous/XiZi_AIoT/services/lib/ipc/Makefile index c65c4a8ba..f8e1072cd 100644 --- a/Ubiquitous/XiZi_AIoT/services/lib/ipc/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/lib/ipc/Makefile @@ -9,10 +9,10 @@ user_ldflags = --start-group,-lgcc,-lc,--end-group cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie #cflags = -Wall -g -std=c11 endif -ifeq ($(BOARD), ok1028a-c) +ifeq ($(BOARD), 3568) toolchain ?= aarch64-none-elf- user_ldflags = -N -Ttext 0 -cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie endif cc = ${toolchain}gcc diff --git a/Ubiquitous/XiZi_AIoT/services/lib/ipc/libipc.c b/Ubiquitous/XiZi_AIoT/services/lib/ipc/libipc.c index 2f0f3b95f..0ff25461f 100644 --- a/Ubiquitous/XiZi_AIoT/services/lib/ipc/libipc.c +++ b/Ubiquitous/XiZi_AIoT/services/lib/ipc/libipc.c @@ -182,7 +182,6 @@ void ipc_server_loop(struct IpcNode* ipc_node) /* handle each session */ for (int i = 0; i < NR_MAX_SESSION; i++) { if (session_list[i].buf == NULL) { - yield(SYS_TASK_YIELD_NO_REASON); break; } cur_sess_id = session_list[i].id; diff --git a/Ubiquitous/XiZi_AIoT/services/lib/memory/Makefile b/Ubiquitous/XiZi_AIoT/services/lib/memory/Makefile index 42e73cbc4..a9516161f 100644 --- a/Ubiquitous/XiZi_AIoT/services/lib/memory/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/lib/memory/Makefile @@ -8,10 +8,10 @@ toolchain ?= arm-xilinx-eabi- cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie user_ldflags = -N -Ttext 0 endif -ifeq ($(BOARD), ok1028a-c) +ifeq ($(BOARD), 3568) toolchain ?= aarch64-none-elf- user_ldflags = -N -Ttext 0 -cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie endif cc = ${toolchain}gcc diff --git a/Ubiquitous/XiZi_AIoT/services/lib/serial/Makefile b/Ubiquitous/XiZi_AIoT/services/lib/serial/Makefile index 4d2c0554f..ac290a6eb 100644 --- a/Ubiquitous/XiZi_AIoT/services/lib/serial/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/lib/serial/Makefile @@ -8,10 +8,10 @@ toolchain ?= arm-xilinx-eabi- cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie user_ldflags = -N -Ttext 0 endif -ifeq ($(BOARD), ok1028a-c) +ifeq ($(BOARD), 3568) toolchain ?= aarch64-none-elf- user_ldflags = -N -Ttext 0 -cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie endif cc = ${toolchain}gcc diff --git a/Ubiquitous/XiZi_AIoT/services/lib/usyscall/Makefile b/Ubiquitous/XiZi_AIoT/services/lib/usyscall/Makefile index d72b77259..9cedf87e8 100644 --- a/Ubiquitous/XiZi_AIoT/services/lib/usyscall/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/lib/usyscall/Makefile @@ -8,10 +8,10 @@ toolchain ?= arm-xilinx-eabi- cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie user_ldflags = -N -Ttext 0 endif -ifeq ($(BOARD), ok1028a-c) +ifeq ($(BOARD), 3568) toolchain ?= aarch64-none-elf- user_ldflags = -N -Ttext 0 -cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie endif cc = ${toolchain}gcc diff --git a/Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.c b/Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.c index 48cfdd30b..8bdf03709 100644 --- a/Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.c +++ b/Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.c @@ -1,141 +1,156 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ -#include "usyscall.h" -#include "libmem.h" - -int spawn(struct Session* session, int fd, ipc_read_fn ipc_read, ipc_fsize_fn ipc_fsize, char* name, char** argv) -{ - /* read elf image */ - int file_size = ipc_fsize(session, fd); - void* img = malloc(file_size); - int read_len = 0; - while (read_len < file_size) { - int cur_read_len = file_size - read_len < 4096 ? file_size - read_len : 4096; - if (cur_read_len < 0) { - return -1; - } - read_len += ipc_read(session, fd, (char*)((uintptr_t)img + read_len), read_len, cur_read_len); - } - /* sys call */ - int ret = syscall(SYSCALL_SPAWN, (uintptr_t)img, (uintptr_t)name, (uintptr_t)argv, 0); - free(img); - return ret; -} - -int thread(void* entry, const char* name, char** argv) -{ - return syscall(SYSCALL_THREAD, (uintptr_t)entry, (uintptr_t)name, (uintptr_t)argv, 0); -} - -void exit(int status) -{ - syscall(SYSCALL_EXIT, (uintptr_t)status, 0, 0, 0); -} - -int yield(task_yield_reason reason) -{ - return syscall(SYSCALL_YIELD, (uintptr_t)reason, 0, 0, 0); -} - -int kill(int pid) -{ - return syscall(SYSCALL_KILL, (intptr_t)pid, 0, 0, 0); -} - -int register_server(char* name) -{ - return syscall(SYSCALL_SERVER, (intptr_t)name, 0, 0, 0); -} - -int session(char* path, int capacity, struct Session* user_session) -{ - return syscall(SYSCALL_SESSION, (intptr_t)path, (intptr_t)capacity, (intptr_t)user_session, 0); -} - -int poll_session(struct Session* userland_session_arr, int arr_capacity) -{ - return syscall(SYSCALL_POLL_SESSION, (intptr_t)userland_session_arr, (intptr_t)arr_capacity, 0, 0); -} - -int close_session(struct Session* session) -{ - return syscall(SYSCALL_CLOSE_SESSION, (intptr_t)session, 0, 0, 0); -} - -int get_memblock_info(sys_state_info* info) -{ - return syscall(SYSCALL_SYS_STATE, SYS_STATE_MEMBLOCK_INFO, (intptr_t)info, 0, 0); -} - -int set_priority(sys_state_info* info) -{ - return syscall(SYSCALL_SYS_STATE, SYS_STATE_SET_TASK_PRIORITY, (intptr_t)info, 0, 0); -} - -int task_heap_base() -{ - return syscall(SYSCALL_SYS_STATE, SYS_STATE_GET_HEAP_BASE, 0, 0, 0); -} - -int show_task() -{ - return syscall(SYSCALL_SYS_STATE, SYS_STATE_SHOW_TASKS, 0, 0, 0); -} - -int show_mem() -{ - return syscall(SYSCALL_SYS_STATE, SYS_STATE_SHOW_MEM_INFO, 0, 0, 0); -} - -int show_cpu() -{ - return syscall(SYSCALL_SYS_STATE, SYS_STATE_SHOW_CPU_INFO, 0, 0, 0); -} - -uintptr_t mmap(uintptr_t vaddr, uintptr_t paddr, int len, bool is_dev) -{ - uintptr_t vaddr_inner = vaddr, paddr_inner = paddr; - if (syscall(SYSCALL_MMAP, (intptr_t)&vaddr_inner, (intptr_t)&paddr_inner, (intptr_t)len, (intptr_t)is_dev) < 0) { - return (uintptr_t)NULL; - } - return vaddr_inner; -} - -int naive_mmap(uintptr_t* vaddr, uintptr_t* paddr, int len, bool is_dev) -{ - return syscall(SYSCALL_MMAP, (uintptr_t)vaddr, (intptr_t)paddr, (intptr_t)len, (intptr_t)is_dev); -} - -int register_irq(int irq, int opcode) -{ - return syscall(SYSCALL_REGISTER_IRQ, (intptr_t)irq, (intptr_t)opcode, 0, 0); -} - -int semaphore_new(int val) -{ - return syscall(SYSCALL_SEMAPHORE, (intptr_t)SYS_SEM_NEW, (intptr_t)val, 0, 0); -} - -bool semaphore_free(int sem_id) -{ - return syscall(SYSCALL_SEMAPHORE, (intptr_t)SYS_SEM_FREE, (intptr_t)sem_id, 0, 0); -} - -bool semaphore_wait(int sem_id) -{ - return syscall(SYSCALL_SEMAPHORE, (intptr_t)SYS_SEM_WAIT, (intptr_t)sem_id, 0, 0); -} - -bool semaphore_signal(int sem_id) -{ - return syscall(SYSCALL_SEMAPHORE, (intptr_t)SYS_SEM_SIGNAL, (intptr_t)sem_id, 0, 0); +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +#include "usyscall.h" +#include "libmem.h" + +int spawn(struct Session* session, int fd, ipc_read_fn ipc_read, ipc_fsize_fn ipc_fsize, char* name, char** argv) +{ + /* read elf image */ + int max_communicate_size = session->capacity - 0x1000; + int file_size = ipc_fsize(session, fd); + void* img = malloc(file_size); + int read_len = 0; + while (read_len < file_size) { + int cur_read_len = file_size - read_len < max_communicate_size ? file_size - read_len : max_communicate_size; + if (cur_read_len < 0) { + return -1; + } + read_len += ipc_read(session, fd, (char*)((uintptr_t)img + read_len), read_len, cur_read_len); + } + /* sys call */ + int ret = syscall(SYSCALL_SPAWN, (uintptr_t)img, (uintptr_t)name, (uintptr_t)argv, 0); + free(img); + return ret; +} + +int thread(void* entry, const char* name, char** argv) +{ + return syscall(SYSCALL_THREAD, (uintptr_t)entry, (uintptr_t)name, (uintptr_t)argv, 0); +} + +void exit(int status) +{ + syscall(SYSCALL_EXIT, (uintptr_t)status, 0, 0, 0); +} + +int yield(task_yield_reason reason) +{ + return syscall(SYSCALL_YIELD, (uintptr_t)reason, 0, 0, 0); +} + +int kill(int pid) +{ + return syscall(SYSCALL_KILL, (intptr_t)pid, 0, 0, 0); +} + +int register_server(char* name) +{ + return syscall(SYSCALL_SERVER, (intptr_t)name, 0, 0, 0); +} + +int session(char* path, int capacity, struct Session* user_session) +{ + return syscall(SYSCALL_SESSION, (intptr_t)path, (intptr_t)capacity, (intptr_t)user_session, 0); +} + +int poll_session(struct Session* userland_session_arr, int arr_capacity) +{ + return syscall(SYSCALL_POLL_SESSION, (intptr_t)userland_session_arr, (intptr_t)arr_capacity, 0, 0); +} + +int close_session(struct Session* session) +{ + return syscall(SYSCALL_CLOSE_SESSION, (intptr_t)session, 0, 0, 0); +} + +int get_memblock_info(sys_state_info* info) +{ + return syscall(SYSCALL_SYS_STATE, SYS_STATE_MEMBLOCK_INFO, (intptr_t)info, 0, 0); +} + +int set_priority(sys_state_info* info) +{ + return syscall(SYSCALL_SYS_STATE, SYS_STATE_SET_TASK_PRIORITY, (intptr_t)info, 0, 0); +} + +int task_heap_base() +{ + return syscall(SYSCALL_SYS_STATE, SYS_STATE_GET_HEAP_BASE, 0, 0, 0); +} + +int show_task() +{ + return syscall(SYSCALL_SYS_STATE, SYS_STATE_SHOW_TASKS, 0, 0, 0); +} + +int show_mem() +{ + return syscall(SYSCALL_SYS_STATE, SYS_STATE_SHOW_MEM_INFO, 0, 0, 0); +} + +int show_cpu() +{ + return syscall(SYSCALL_SYS_STATE, SYS_STATE_SHOW_CPU_INFO, 0, 0, 0); +} + +uintptr_t get_second() +{ + sys_state_info info; + syscall(SYSCALL_SYS_STATE, SYS_STATE_GET_CURRENT_SECOND, (intptr_t)&info, 0, 0); + return info.current_second; +} + +uintptr_t get_tick() +{ + sys_state_info info; + syscall(SYSCALL_SYS_STATE, SYS_STATE_GET_CURRENT_TICK, (intptr_t)&info, 0, 0); + return info.current_tick; +} + +uintptr_t mmap(uintptr_t vaddr, uintptr_t paddr, int len, bool is_dev) +{ + uintptr_t vaddr_inner = vaddr, paddr_inner = paddr; + if (syscall(SYSCALL_MMAP, (intptr_t)&vaddr_inner, (intptr_t)&paddr_inner, (intptr_t)len, (intptr_t)is_dev) < 0) { + return (uintptr_t)NULL; + } + return vaddr_inner; +} + +int naive_mmap(uintptr_t* vaddr, uintptr_t* paddr, int len, bool is_dev) +{ + return syscall(SYSCALL_MMAP, (uintptr_t)vaddr, (intptr_t)paddr, (intptr_t)len, (intptr_t)is_dev); +} + +int register_irq(int irq, int opcode) +{ + return syscall(SYSCALL_REGISTER_IRQ, (intptr_t)irq, (intptr_t)opcode, 0, 0); +} + +int semaphore_new(int val) +{ + return syscall(SYSCALL_SEMAPHORE, (intptr_t)SYS_SEM_NEW, (intptr_t)val, 0, 0); +} + +bool semaphore_free(int sem_id) +{ + return syscall(SYSCALL_SEMAPHORE, (intptr_t)SYS_SEM_FREE, (intptr_t)sem_id, 0, 0); +} + +bool semaphore_wait(int sem_id) +{ + return syscall(SYSCALL_SEMAPHORE, (intptr_t)SYS_SEM_WAIT, (intptr_t)sem_id, 0, 0); +} + +bool semaphore_signal(int sem_id) +{ + return syscall(SYSCALL_SEMAPHORE, (intptr_t)SYS_SEM_SIGNAL, (intptr_t)sem_id, 0, 0); } \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.h b/Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.h index 8adca0de8..e76f684a1 100644 --- a/Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.h +++ b/Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.h @@ -1,105 +1,108 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ -#pragma once -#include - -#include "libserial.h" -#include "session.h" - -// clang-format off -#define SYSCALL_TEST 0 -#define SYSCALL_SPAWN 1 // generate a brand new task to run elf -#define SYSCALL_EXIT 2 // exit task, delete the task cb -#define SYSCALL_YIELD 3 // yield task, go to scheduler - -#define SYSCALL_MMAP 4 // map a virt page to phy page -#define SYSCALL_SERVER 5 // register current task as a server -#define SYSCALL_SESSION 6 // create a session to a server -#define SYSCALL_POLL_SESSION 7 // server poll for it's server sessions -#define SYSCALL_CLOSE_SESSION 8 // client close it's client sessions - -#define SYSCALL_THREAD 9 // generate a thread using old memspace -#define SYSCALL_SYS_STATE 10 // run system state -#define SYSCALL_REGISTER_IRQ 11 // - -#define SYSCALL_KILL 12 // kill the task by id - -#define SYSCALL_SEMAPHORE 13 // semaphore related operations -// clang-format on - -typedef enum { - SYS_STATE_TEST = 0, - SYS_STATE_SET_TASK_PRIORITY, - SYS_STATE_GET_HEAP_BASE, - SYS_STATE_MEMBLOCK_INFO, - SYS_STATE_SHOW_TASKS, - SYS_STATE_SHOW_MEM_INFO, - SYS_STATE_SHOW_CPU_INFO, - SYS_STATE_GET_CURRENT_TICK, - SYS_STATE_GET_CURRENT_SECOND, -} sys_state_option; - -typedef enum { - SYS_TASK_YIELD_NO_REASON = 0x0, - SYS_TASK_YIELD_FOREVER = 0x1, - SYS_TASK_YIELD_BLOCK_IPC = 0x2, -} task_yield_reason; - -typedef union { - struct { - uintptr_t memblock_start; - uintptr_t memblock_end; - } memblock_info; - int priority; - uintptr_t current_tick; - uintptr_t current_second; -} sys_state_info; - -typedef enum { - SYS_SEM_NEW = 0, - SYS_SEM_FREE, - SYS_SEM_SIGNAL, - SYS_SEM_WAIT, -} sys_sem_option; - -typedef int (*ipc_read_fn)(struct Session* session, int fd, char* dst, int offset, int len); -typedef int (*ipc_fsize_fn)(struct Session* session, int fd); -typedef int (*ipc_write_fn)(struct Session* session, int fd, char* src, int offset, int len); - -int syscall(int sys_num, intptr_t a1, intptr_t a2, intptr_t a3, intptr_t a4); - -int spawn(struct Session* session, int fd, ipc_read_fn ipc_read, ipc_fsize_fn ipc_fsize, char* name, char** argv); -int thread(void* entry, const char* name, char** argv); -void exit(int status); -int yield(task_yield_reason reason); -int kill(int pid); - -int register_server(char* name); -int session(char* path, int capacity, struct Session* user_session); -int poll_session(struct Session* userland_session_arr, int arr_capacity); -int close_session(struct Session* session); -int register_irq(int irq, int opcode); - -uintptr_t mmap(uintptr_t vaddr, uintptr_t paddr, int len, bool is_dev); -int naive_mmap(uintptr_t* vaddr, uintptr_t* paddr, int len, bool is_dev); - -int task_heap_base(); -int get_memblock_info(sys_state_info* info); -int set_priority(sys_state_info* info); -int show_task(); -int show_mem(); -int show_cpu(); - -int semaphore_new(int val); -bool semaphore_free(int sem_id); -bool semaphore_wait(int sem_id); +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +#pragma once +#include + +#include "libserial.h" +#include "session.h" + +// clang-format off +#define SYSCALL_TEST 0 +#define SYSCALL_SPAWN 1 // generate a brand new task to run elf +#define SYSCALL_EXIT 2 // exit task, delete the task cb +#define SYSCALL_YIELD 3 // yield task, go to scheduler + +#define SYSCALL_MMAP 4 // map a virt page to phy page +#define SYSCALL_SERVER 5 // register current task as a server +#define SYSCALL_SESSION 6 // create a session to a server +#define SYSCALL_POLL_SESSION 7 // server poll for it's server sessions +#define SYSCALL_CLOSE_SESSION 8 // client close it's client sessions + +#define SYSCALL_THREAD 9 // generate a thread using old memspace +#define SYSCALL_SYS_STATE 10 // run system state +#define SYSCALL_REGISTER_IRQ 11 // + +#define SYSCALL_KILL 12 // kill the task by id + +#define SYSCALL_SEMAPHORE 13 // semaphore related operations +// clang-format on + +typedef enum { + SYS_STATE_TEST = 0, + SYS_STATE_SET_TASK_PRIORITY, + SYS_STATE_GET_HEAP_BASE, + SYS_STATE_MEMBLOCK_INFO, + SYS_STATE_SHOW_TASKS, + SYS_STATE_SHOW_MEM_INFO, + SYS_STATE_SHOW_CPU_INFO, + SYS_STATE_GET_CURRENT_TICK, + SYS_STATE_GET_CURRENT_SECOND, +} sys_state_option; + +typedef enum { + SYS_TASK_YIELD_NO_REASON = 0x0, + SYS_TASK_YIELD_FOREVER = 0x1, + SYS_TASK_YIELD_BLOCK_IPC = 0x2, +} task_yield_reason; + +typedef union { + struct { + uintptr_t memblock_start; + uintptr_t memblock_end; + } memblock_info; + int priority; + uintptr_t current_tick; + uintptr_t current_second; +} sys_state_info; + +typedef enum { + SYS_SEM_NEW = 0, + SYS_SEM_FREE, + SYS_SEM_SIGNAL, + SYS_SEM_WAIT, +} sys_sem_option; + +typedef int (*ipc_read_fn)(struct Session* session, int fd, char* dst, int offset, int len); +typedef int (*ipc_fsize_fn)(struct Session* session, int fd); +typedef int (*ipc_write_fn)(struct Session* session, int fd, char* src, int offset, int len); + +int syscall(int sys_num, intptr_t a1, intptr_t a2, intptr_t a3, intptr_t a4); + +int spawn(struct Session* session, int fd, ipc_read_fn ipc_read, ipc_fsize_fn ipc_fsize, char* name, char** argv); +int thread(void* entry, const char* name, char** argv); +void exit(int status); +int yield(task_yield_reason reason); +int kill(int pid); + +int register_server(char* name); +int session(char* path, int capacity, struct Session* user_session); +int poll_session(struct Session* userland_session_arr, int arr_capacity); +int close_session(struct Session* session); +int register_irq(int irq, int opcode); + +uintptr_t mmap(uintptr_t vaddr, uintptr_t paddr, int len, bool is_dev); +int naive_mmap(uintptr_t* vaddr, uintptr_t* paddr, int len, bool is_dev); + +int task_heap_base(); +int get_memblock_info(sys_state_info* info); +int set_priority(sys_state_info* info); +int show_task(); +int show_mem(); +int show_cpu(); + +uintptr_t get_second(); +uintptr_t get_tick(); + +int semaphore_new(int val); +bool semaphore_free(int sem_id); +bool semaphore_wait(int sem_id); bool semaphore_signal(int sem_id); \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/net/libnet/Makefile b/Ubiquitous/XiZi_AIoT/services/net/libnet/Makefile index 2d82f5957..980f671c9 100644 --- a/Ubiquitous/XiZi_AIoT/services/net/libnet/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/net/libnet/Makefile @@ -17,6 +17,13 @@ cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic - board_specs = stub.o endif +ifeq ($(BOARD), 3568) +toolchain ?= aarch64-none-elf- +user_ldflags = -N -Ttext 0 +cflags = -Wall -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +board_specs = $(KERNEL_ROOT)/services/app/stub.o +endif + cc = ${toolchain}gcc ld = ${toolchain}g++ objdump = ${toolchain}objdump diff --git a/Ubiquitous/XiZi_AIoT/services/net/net_server/lwip.mk b/Ubiquitous/XiZi_AIoT/services/net/net_server/lwip.mk index 0dc3e5777..a2ebd6f78 100644 --- a/Ubiquitous/XiZi_AIoT/services/net/net_server/lwip.mk +++ b/Ubiquitous/XiZi_AIoT/services/net/net_server/lwip.mk @@ -18,6 +18,13 @@ cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic - board_specs = $(KERNEL_ROOT)/services/app/stub.o endif +ifeq ($(BOARD), 3568) +toolchain ?= aarch64-none-elf- +user_ldflags = -N -Ttext 0 +cflags = -Wall -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +board_specs = $(KERNEL_ROOT)/services/app/stub.o +endif + cc = ${toolchain}gcc ld = ${toolchain}g++ objdump = ${toolchain}objdump diff --git a/Ubiquitous/XiZi_AIoT/services/semaphore/Makefile b/Ubiquitous/XiZi_AIoT/services/semaphore/Makefile index 3ae7b2674..66082c1f5 100644 --- a/Ubiquitous/XiZi_AIoT/services/semaphore/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/semaphore/Makefile @@ -9,10 +9,10 @@ user_ldflags = --start-group,-lgcc,-lc,--end-group cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie #cflags = -Wall -g -std=c11 endif -ifeq ($(BOARD), ok1028a-c) +ifeq ($(BOARD), 3568) toolchain ?= aarch64-none-elf- user_ldflags = -N -Ttext 0 -cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie endif cc = ${toolchain}gcc diff --git a/Ubiquitous/XiZi_AIoT/services/shell/letter-shell/Makefile b/Ubiquitous/XiZi_AIoT/services/shell/letter-shell/Makefile index d08b80739..4c22e10af 100644 --- a/Ubiquitous/XiZi_AIoT/services/shell/letter-shell/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/shell/letter-shell/Makefile @@ -8,10 +8,10 @@ toolchain ?= arm-xilinx-eabi- cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie user_ldflags = -N -Ttext 0 endif -ifeq ($(BOARD), ok1028a-c) +ifeq ($(BOARD), 3568) toolchain ?= aarch64-none-elf- user_ldflags = -N -Ttext 0 -cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie endif cc = ${toolchain}gcc diff --git a/Ubiquitous/XiZi_AIoT/softkernel/include/buddy.h b/Ubiquitous/XiZi_AIoT/softkernel/include/buddy.h index 3a657aec1..4b73e7cd4 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/include/buddy.h +++ b/Ubiquitous/XiZi_AIoT/softkernel/include/buddy.h @@ -32,12 +32,11 @@ Modification: #include "list.h" #include "memlayout.h" #include "spinlock.h" -#include "pagetable.h" #include #include -#define MAX_BUDDY_ORDER (10) +#define MAX_BUDDY_ORDER (14) #define FREE_LIST_INDEX(order) \ (1 << order) diff --git a/Ubiquitous/XiZi_AIoT/softkernel/include/kalloc.h b/Ubiquitous/XiZi_AIoT/softkernel/include/kalloc.h index 98e55333e..66ec4cddd 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/include/kalloc.h +++ b/Ubiquitous/XiZi_AIoT/softkernel/include/kalloc.h @@ -34,6 +34,7 @@ Modification: bool module_phymem_init(); char* kalloc(size_t size); bool kfree(char* vaddr); +bool raw_kfree(char* paddr); char* raw_alloc(size_t size); bool raw_free(char* paddr); diff --git a/Ubiquitous/XiZi_AIoT/softkernel/include/memspace.h b/Ubiquitous/XiZi_AIoT/softkernel/include/memspace.h index 41ae50482..44cc9575c 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/include/memspace.h +++ b/Ubiquitous/XiZi_AIoT/softkernel/include/memspace.h @@ -27,8 +27,16 @@ Author: AIIT XUOS Lab Modification: 1. first version *************************************************/ +#pragma once -#include "task.h" +#include "actracer.h" +#include "bitmap64.h" +#include "buddy.h" +#include "list.h" + +struct TopLevelPageDirectory { + uintptr_t* pd_addr; +}; struct ThreadStackPointer { int argc; @@ -37,6 +45,24 @@ struct ThreadStackPointer { uintptr_t user_stack_vaddr; }; +struct MemSpace { + /* trace node */ + TraceTag tag; + /* task memory resources */ + struct TopLevelPageDirectory pgdir; // [phy] vm pgtbl base address + uintptr_t heap_base; // mem size of proc used(allocated by kernel) + uintptr_t mem_size; + /* task communication mem resources */ + struct KBuddy* massive_ipc_allocator; + + /* thread using this memspace */ + struct bitmap64 thread_stack_idx_bitmap; + struct double_list_node thread_list_guard; + + // thread to notify when sub-thread exit + struct Thread* thread_to_notify; +}; + struct MemSpace* alloc_memspace(); void free_memspace(struct MemSpace* pmemspace); uintptr_t* load_memspace(struct MemSpace* pmemspace, char* img_start); diff --git a/Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h b/Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h index 802ba5442..e0938d322 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h +++ b/Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h @@ -33,11 +33,12 @@ Modification: #include #include "memlayout.h" - -#include "actracer.h" #include "mmu.h" #include "mmu_common.h" +#include "actracer.h" +#include "memspace.h" + // clang-format off #define ALIGNUP(size, align) (((uintptr_t)(size) + (uintptr_t)(align) - 1) & ~((uintptr_t)(align) - 1)) #define ALIGNDOWN(size, align) ((uintptr_t)(size) & ~((uintptr_t)(align) - 1)) @@ -49,10 +50,6 @@ Modification: #define TOPLEVLE_PAGEDIR_SIZE sizeof(uintptr_t) * NUM_TOPLEVEL_PDE // clang-format on -struct TopLevelPageDirectory { - uintptr_t* pd_addr; -}; - struct PagerRightGroup { struct TraceTag mmu_driver_tag; }; @@ -60,10 +57,10 @@ struct PagerRightGroup { struct XiziPageManager { bool (*new_pgdir)(struct TopLevelPageDirectory* pgdir); void (*free_user_pgdir)(struct TopLevelPageDirectory* pgdir); - bool (*map_pages)(uintptr_t* pd_addr, uintptr_t vaddr, uintptr_t paddr, int len, bool is_dev); + bool (*map_pages)(struct MemSpace* pmemspace, uintptr_t vaddr, uintptr_t paddr, int len, bool is_dev); bool (*unmap_pages)(uintptr_t* pd_addr, uintptr_t vaddr, int len); - uintptr_t (*resize_user_pgdir)(struct TopLevelPageDirectory* pgdir, uintptr_t old_size, uintptr_t new_size); + uintptr_t (*resize_user_pgdir)(struct MemSpace* pmemspace, uintptr_t old_size, uintptr_t new_size); uintptr_t (*address_translate)(struct TopLevelPageDirectory* pgdir, uintptr_t vaddr); uintptr_t (*cross_vspace_data_copy)(struct TopLevelPageDirectory* pgdir, uintptr_t cross_dest, uintptr_t src, uintptr_t len); }; diff --git a/Ubiquitous/XiZi_AIoT/softkernel/include/syscall.h b/Ubiquitous/XiZi_AIoT/softkernel/include/syscall.h index 13e5e845d..14e2ddc7e 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/include/syscall.h +++ b/Ubiquitous/XiZi_AIoT/softkernel/include/syscall.h @@ -1,116 +1,116 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ -/** - * @file syscall.h - * @brief syscall header - * @version 3.0 - * @author AIIT XUOS Lab - * @date 2023.08.25 - */ - -/************************************************* -File name: syscall.h -Description: syscall header -Others: -History: -1. Date: 2023-08-28 -Author: AIIT XUOS Lab -Modification: -1. first version -*************************************************/ -#pragma once - -// clang-format off -#define SYSCALL_TEST 0 -#define SYSCALL_SPAWN 1 // generate a brand new task to run elf -#define SYSCALL_EXIT 2 // exit task, delete the task cb -#define SYSCALL_YIELD 3 // yield task, go to scheduler - -#define SYSCALL_MMAP 4 // map a virt page to phy page -#define SYSCALL_SERVER 5 // register current task as a server -#define SYSCALL_SESSION 6 // create a session to a server -#define SYSCALL_POLL_SESSION 7 // server poll for it's server sessions -#define SYSCALL_CLOSE_SESSION 8 // client close it's client sessions - -#define SYSCALL_THREAD 9 // generate a thread using old memspace -#define SYSCALL_SYS_STATE 10 // run system state -#define SYSCALL_REGISTER_IRQ 11 // - -#define SYSCALL_KILL 12 // kill the task by id - -#define SYSCALL_SEMAPHORE 13 // semaphore related operations -// clang-format on - -#ifndef __ASSEMBLER__ -#include - -#include "share_page.h" -#include "task.h" - -typedef enum { - SYS_STATE_TEST = 0, - SYS_STATE_SET_TASK_PRIORITY, - SYS_STATE_GET_HEAP_BASE, - SYS_STATE_MEMBLOCK_INFO, - SYS_STATE_SHOW_TASKS, - SYS_STATE_SHOW_MEM_INFO, - SYS_STATE_SHOW_CPU_INFO, - SYS_STATE_GET_CURRENT_TICK, - SYS_STATE_GET_CURRENT_SECOND, -} sys_state_option; - -typedef enum { - SYS_TASK_YIELD_NO_REASON = 0x0, - SYS_TASK_YIELD_FOREVER = 0x1, - SYS_TASK_YIELD_BLOCK_IPC = 0x2, -} task_yield_reason; - -typedef union { - struct { - uintptr_t memblock_start; - uintptr_t memblock_end; - } memblock_info; - int priority; - uintptr_t current_tick; - uintptr_t current_second; -} sys_state_info; - -typedef enum { - SYS_SEM_NEW = 0, - SYS_SEM_FREE, - SYS_SEM_SIGNAL, - SYS_SEM_WAIT, -} sys_sem_option; - -int syscall(int sys_num, uintptr_t param1, uintptr_t param2, uintptr_t param3, uintptr_t param4); - -int sys_spawn(char* img_start, char* name, char** argv); -int sys_thread(uintptr_t entry, char* name, char** argv); -int sys_exit(struct Thread* ptask); -int sys_yield(task_yield_reason reason); -int sys_kill(int id); - -int sys_register_as_server(char* name); -int sys_connect_session(char* path, int capacity, struct Session* user_session); -int sys_poll_session(struct Session* userland_session_arr, int arr_capacity); -int sys_close_session(struct Thread* task, struct Session* session); - -int sys_exec(char* img_start, char* name, char** argv); -int sys_state(sys_state_option option, sys_state_info* info); -int sys_mmap(uintptr_t* vaddr, uintptr_t* paddr, int len, int is_dev); - -int sys_register_irq(int irq_num, int irq_opcode); -int sys_unbind_irq_all(struct Thread* task); -int sys_unbind_irq(struct Thread* task, int irq_num); - -int sys_semaphore(sys_sem_option op, int sem_id); -#endif +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file syscall.h + * @brief syscall header + * @version 3.0 + * @author AIIT XUOS Lab + * @date 2023.08.25 + */ + +/************************************************* +File name: syscall.h +Description: syscall header +Others: +History: +1. Date: 2023-08-28 +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#pragma once + +// clang-format off +#define SYSCALL_TEST 0 +#define SYSCALL_SPAWN 1 // generate a brand new task to run elf +#define SYSCALL_EXIT 2 // exit task, delete the task cb +#define SYSCALL_YIELD 3 // yield task, go to scheduler + +#define SYSCALL_MMAP 4 // map a virt page to phy page +#define SYSCALL_SERVER 5 // register current task as a server +#define SYSCALL_SESSION 6 // create a session to a server +#define SYSCALL_POLL_SESSION 7 // server poll for it's server sessions +#define SYSCALL_CLOSE_SESSION 8 // client close it's client sessions + +#define SYSCALL_THREAD 9 // generate a thread using old memspace +#define SYSCALL_SYS_STATE 10 // run system state +#define SYSCALL_REGISTER_IRQ 11 // + +#define SYSCALL_KILL 12 // kill the task by id + +#define SYSCALL_SEMAPHORE 13 // semaphore related operations +// clang-format on + +#ifndef __ASSEMBLER__ +#include + +#include "share_page.h" +#include "task.h" + +typedef enum { + SYS_STATE_TEST = 0, + SYS_STATE_SET_TASK_PRIORITY, + SYS_STATE_GET_HEAP_BASE, + SYS_STATE_MEMBLOCK_INFO, + SYS_STATE_SHOW_TASKS, + SYS_STATE_SHOW_MEM_INFO, + SYS_STATE_SHOW_CPU_INFO, + SYS_STATE_GET_CURRENT_TICK, + SYS_STATE_GET_CURRENT_SECOND, +} sys_state_option; + +typedef enum { + SYS_TASK_YIELD_NO_REASON = 0x0, + SYS_TASK_YIELD_FOREVER = 0x1, + SYS_TASK_YIELD_BLOCK_IPC = 0x2, +} task_yield_reason; + +typedef union { + struct { + uintptr_t memblock_start; + uintptr_t memblock_end; + } memblock_info; + int priority; + uintptr_t current_tick; + uintptr_t current_second; +} sys_state_info; + +typedef enum { + SYS_SEM_NEW = 0, + SYS_SEM_FREE, + SYS_SEM_SIGNAL, + SYS_SEM_WAIT, +} sys_sem_option; + +int syscall(int sys_num, uintptr_t param1, uintptr_t param2, uintptr_t param3, uintptr_t param4); + +int sys_spawn(char* img_start, char* name, char** argv); +int sys_thread(uintptr_t entry, char* name, char** argv); +int sys_exit(struct Thread* ptask); +int sys_yield(task_yield_reason reason); +int sys_kill(int id); + +int sys_register_as_server(char* name); +int sys_connect_session(char* path, int capacity, struct Session* user_session); +int sys_poll_session(struct Session* userland_session_arr, int arr_capacity); +int sys_close_session(struct Thread* task, struct Session* session); + +int sys_exec(char* img_start, char* name, char** argv); +int sys_state(sys_state_option option, sys_state_info* info); +int sys_mmap(uintptr_t* vaddr, uintptr_t* paddr, int len, int is_dev); + +int sys_register_irq(int irq_num, int irq_opcode); +int sys_unbind_irq_all(struct Thread* task); +int sys_unbind_irq(struct Thread* task, int irq_num); + +int sys_semaphore(sys_sem_option op, int sem_id); +#endif diff --git a/Ubiquitous/XiZi_AIoT/softkernel/include/task.h b/Ubiquitous/XiZi_AIoT/softkernel/include/task.h index 56320be0f..accfb513a 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/include/task.h +++ b/Ubiquitous/XiZi_AIoT/softkernel/include/task.h @@ -31,10 +31,10 @@ Modification: #include "core.h" -#include "bitmap64.h" #include "buddy.h" #include "ksemaphore.h" #include "list.h" +#include "memspace.h" #include "object_allocator.h" #include "pagetable.h" #include "share_page.h" @@ -54,19 +54,6 @@ enum ProcState { NEVER_RUN, }; -struct MemSpace { - /* task memory resources */ - struct TopLevelPageDirectory pgdir; // [phy] vm pgtbl base address - uintptr_t heap_base; // mem size of proc used(allocated by kernel) - uintptr_t mem_size; - /* task communication mem resources */ - struct KBuddy* massive_ipc_allocator; - - /* thread using this memspace */ - struct bitmap64 thread_stack_idx_bitmap; - struct double_list_node thread_list_guard; -}; - /* Thread Control Block */ struct ThreadContext { struct Thread* task; // process of current thread @@ -105,8 +92,8 @@ struct Thread { /* task communication resources */ struct double_list_node cli_sess_listhead; struct double_list_node svr_sess_listhead; - bool current_ipc_handled; struct TraceTag server_identifier; + bool advance_unblock; /* task schedule attributes */ struct double_list_node node; @@ -122,6 +109,7 @@ struct SchedulerRightGroup { }; struct XiziTaskManager { + TraceTag tag; /* thead schedule lists */ struct double_list_node task_list_head[TASK_MAX_PRIORITY]; /* list of task control blocks that are allocated */ struct double_list_node task_running_list_head; @@ -162,5 +150,4 @@ extern uint32_t ready_task_priority; extern struct Thread* next_task_emergency; extern struct XiziTaskManager xizi_task_manager; -int spawn_embedded_task(char* img_start, char* name, char** argv); -bool module_task_manager_init(void); +bool module_task_manager_init(TraceTag* softkernel_tag); diff --git a/Ubiquitous/XiZi_AIoT/softkernel/init/softkernel_init.c b/Ubiquitous/XiZi_AIoT/softkernel/init/softkernel_init.c index dd5c1d22d..53e3d4291 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/init/softkernel_init.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/init/softkernel_init.c @@ -48,7 +48,7 @@ bool softkernel_init(struct TraceTag* _hardkernel_tag, struct TraceTag* _softker AchieveResourceTag(&intr_driver_tag, _hardkernel_tag, "intr-ac-resource"); load_kern_pgdir(&mmu_driver_tag, &intr_driver_tag); // enter kernel virtmem space - module_task_manager_init(); // init task + module_task_manager_init(_softkernel_tag); // init task struct SharePageRightGroup sp_rights; AchieveResourceTag(&sp_rights.dcache_driver_tag, _hardkernel_tag, "dcache-ac-resource"); diff --git a/Ubiquitous/XiZi_AIoT/softkernel/load_apps.S b/Ubiquitous/XiZi_AIoT/softkernel/load_apps.S index 71d5278bd..597d60af0 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/load_apps.S +++ b/Ubiquitous/XiZi_AIoT/softkernel/load_apps.S @@ -35,7 +35,7 @@ user_apps: .section .rawdata_init .globl initapp initapp: - .incbin "../services/app/bin/init" + .incbin "../services/app/bin/shell" .section .rawdata_memfs .globl memfs diff --git a/Ubiquitous/XiZi_AIoT/softkernel/main.c b/Ubiquitous/XiZi_AIoT/softkernel/main.c index dd61c4666..d19f63d67 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/main.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/main.c @@ -42,11 +42,20 @@ extern uintptr_t _binary_init_start[], _binary_default_fs_start[]; extern int sys_spawn(char* img_start, char* name, char** argv); static struct TraceTag hardkernel_tag, softkernel_tag; -static volatile int core_init_done = 0; +static volatile int core_para_init = 0; + +static void main_sync_cores() +{ + while (core_para_init != ((1 << NR_CPU) - 1)) + ; + return; +} + int main(void) { /* init tracer */ uint32_t cpu_id = cur_cpuid(); + core_para_init |= (1 << cpu_id); if (cpu_id == 0) { /* init memory management first */ @@ -80,26 +89,27 @@ int main(void) for (int i = 1; i < NR_CPU; i++) { // start secondary cpus + while ((core_para_init & (1 << (i - 1))) == 0) + ; cpu_start_secondary(i); } /* start first task */ - char* init_task_param[2] = { "/app/init", 0 }; - sys_spawn((char*)_binary_init_start, "init", init_task_param); + char* init_task_param[2] = { "/app/shell", 0 }; + sys_spawn((char*)_binary_init_start, "shell", init_task_param); char* fs_server_task_param[2] = { "/app/fs_server", 0 }; sys_spawn((char*)_binary_default_fs_start, "memfs", fs_server_task_param); } - /* start scheduler */ struct SchedulerRightGroup scheduler_rights; assert(AchieveResourceTag(&scheduler_rights.mmu_driver_tag, &hardkernel_tag, "mmu-ac-resource")); assert(AchieveResourceTag(&scheduler_rights.intr_driver_tag, &hardkernel_tag, "intr-ac-resource")); - core_init_done |= (1 << cpu_id); LOG_PRINTF("CPU %d init done\n", cpu_id); spinlock_unlock(&whole_kernel_lock); // sync memory __sync_synchronize(); + main_sync_cores(); start_smp_cache_broadcast(cpu_id); // enter kernel seriously xizi_enter_kernel(); diff --git a/Ubiquitous/XiZi_AIoT/softkernel/memory/Makefile b/Ubiquitous/XiZi_AIoT/softkernel/memory/Makefile index 392e4ee0a..67cd1ed69 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/memory/Makefile +++ b/Ubiquitous/XiZi_AIoT/softkernel/memory/Makefile @@ -2,7 +2,7 @@ #include $(KERNEL_ROOT)/compiler.mk -ifneq ($(findstring $(BOARD), ok1028a-c), ) +ifneq ($(findstring $(BOARD), 3568), ) SRC_FILES := kalloc.c pagetable.c pagetable_level3.c buddy.c object_allocator.c share_page.c endif ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), ) diff --git a/Ubiquitous/XiZi_AIoT/softkernel/memory/kalloc.c b/Ubiquitous/XiZi_AIoT/softkernel/memory/kalloc.c index 17d9aeba5..4bed55c1d 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/memory/kalloc.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/memory/kalloc.c @@ -43,12 +43,13 @@ bool module_phymem_init() uintptr_t kern_freemem_end = PHY_USER_FREEMEM_BASE; uintptr_t user_freemem_start = PHY_USER_FREEMEM_BASE; uintptr_t user_freemem_end = PHY_MEM_STOP; + user_phy_freemem_buddy.pages = NULL; KBuddySysInit(&kern_virtmem_buddy, kern_freemem_start, kern_freemem_end); KBuddyInit(&user_phy_freemem_buddy, user_freemem_start, user_freemem_end); return true; } -char* kalloc(size_t size) +char* kalloc(uintptr_t size) { char* mem_alloc = KBuddyAlloc(&kern_virtmem_buddy, size); if (mem_alloc == NULL) { @@ -68,6 +69,11 @@ bool kfree(char* vaddr) return KBuddyFree(&kern_virtmem_buddy, V2P_WO(vaddr)); } +bool raw_kfree(char* paddr) +{ + return KBuddyFree(&kern_virtmem_buddy, paddr); +} + char* raw_alloc(size_t size) { char* mem_alloc = KBuddyAlloc(&user_phy_freemem_buddy, size); diff --git a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable.c b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable.c index dd2d4df4c..53404786f 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable.c @@ -51,7 +51,7 @@ static bool _new_pgdir(struct TopLevelPageDirectory* pgdir) return true; } -static bool _map_pages(uintptr_t* pgdir, uintptr_t vaddr, uintptr_t paddr, int len, uintptr_t attr) +static bool _map_pages(uintptr_t* pgdir, uintptr_t vaddr, uintptr_t paddr, intptr_t len, uintptr_t attr) { assert(len >= 0); vaddr = ALIGNDOWN(vaddr, LEVEL4_PTE_SIZE); @@ -61,12 +61,12 @@ static bool _map_pages(uintptr_t* pgdir, uintptr_t vaddr, uintptr_t paddr, int l while (true) { uintptr_t* pte = NULL; if ((pte = _page_walk(pgdir, vaddr, true)) == NULL) { - ERROR("pte not found for vaddr %x.\n", vaddr); + ERROR("pte not found for vaddr %p.\n", vaddr); return false; } if (UNLIKELY(*pte != 0)) { - ERROR("remapping: vaddr: %x | paddr: %x | pte: %x |\n", vaddr, paddr, *pte); + ERROR("remapping: vaddr: %p | paddr: %p | pte: %p |\n", vaddr, paddr, *pte); return false; } @@ -93,12 +93,12 @@ static bool _unmap_pages(uintptr_t* pgdir, uintptr_t vaddr, int len) while (true) { uintptr_t* pte = NULL; if ((pte = _page_walk(pgdir, vaddr, false)) == NULL) { - ERROR("pte not found for vaddr %x.\n", vaddr); + ERROR("pte not found for vaddr %p.\n", vaddr); return false; } if (*pte == 0) { - ERROR("unmap a unmapped page, vaddr: %x, pte: %x\n", vaddr, *pte); + ERROR("unmap a unmapped page, vaddr: %p, pte: %p\n", vaddr, *pte); return false; } @@ -122,7 +122,7 @@ static bool _unmap_pages(uintptr_t* pgdir, uintptr_t vaddr, int len) /// @param len /// @param is_dev /// @return -static bool _map_user_pages(uintptr_t* pgdir, uintptr_t vaddr, uintptr_t paddr, int len, bool is_dev) +static bool _map_user_pages(struct MemSpace* pmemspace, uintptr_t vaddr, uintptr_t paddr, int len, bool is_dev) { if (len < 0) { return false; @@ -140,13 +140,13 @@ static bool _map_user_pages(uintptr_t* pgdir, uintptr_t vaddr, uintptr_t paddr, _p_pgtbl_mmu_access->MmuUsrDevPteAttr(&mem_attr); } - return _map_pages(pgdir, vaddr, paddr, len, mem_attr); + return _map_pages(pmemspace->pgdir.pd_addr, vaddr, paddr, (intptr_t)len, mem_attr); } /// assume that a user pagedir is allocated from [0, size) /// if new_size > old_size, allocate more space, /// if old_size > new_size, free extra space, to avoid unnecessary alloc/free. -static uintptr_t _resize_user_pgdir(struct TopLevelPageDirectory* pgdir, uintptr_t old_size, uintptr_t new_size) +static uintptr_t _resize_user_pgdir(struct MemSpace* pmemspace, uintptr_t old_size, uintptr_t new_size) { if (UNLIKELY(new_size > USER_MEM_TOP)) { ERROR("user size out of range.\n"); @@ -158,20 +158,18 @@ static uintptr_t _resize_user_pgdir(struct TopLevelPageDirectory* pgdir, uintptr } uintptr_t cur_size = ALIGNUP(old_size, PAGE_SIZE); + uintptr_t size_needed = ALIGNUP(new_size, PAGE_SIZE) - cur_size; - while (cur_size < new_size) { - char* new_page = kalloc(PAGE_SIZE); - if (new_page == NULL) { - ERROR("No memory\n"); - return cur_size; - } - memset(new_page, 0, PAGE_SIZE); - - if (!xizi_pager.map_pages(pgdir->pd_addr, cur_size, V2P(new_page), PAGE_SIZE, false)) { - return cur_size; - } - cur_size += PAGE_SIZE; + char* new_page = kalloc(size_needed); + if (new_page == NULL) { + ERROR("No memory\n"); + return cur_size; } + memset(new_page, 0, size_needed); + if (!xizi_pager.map_pages(pmemspace, cur_size, V2P(new_page), size_needed, false)) { + return cur_size; + } + CreateResourceTag(NULL, &pmemspace->tag, NULL, TRACER_MEM_FROM_BUDDY_AC_RESOURCE, V2P_WO(new_page)); return new_size; } @@ -269,7 +267,7 @@ void load_kern_pgdir(struct TraceTag* mmu_driver_tag, struct TraceTag* intr_driv // kern mem _map_pages((uintptr_t*)kern_pgdir.pd_addr, KERN_MEM_BASE, PHY_MEM_BASE, (PHY_MEM_STOP - PHY_MEM_BASE), kern_attr); // dev mem - _map_pages((uintptr_t*)kern_pgdir.pd_addr, DEV_VRTMEM_BASE, DEV_PHYMEM_BASE, DEV_MEM_SZ, dev_attr); + _map_pages((uintptr_t*)kern_pgdir.pd_addr, DEV_VRTMEM_BASE, DEV_PHYMEM_BASE, DEV_MEM_SIZE, dev_attr); _p_pgtbl_mmu_access->LoadPgdir((uintptr_t)V2P(kern_pgdir.pd_addr)); } diff --git a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_level2.c b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_level2.c index d04736611..2ab5375aa 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_level2.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_level2.c @@ -65,31 +65,12 @@ uintptr_t* _page_walk(uintptr_t* pgdir, uintptr_t vaddr, bool alloc) void _free_user_pgdir(struct TopLevelPageDirectory* pgdir) { - uintptr_t low_bound = kern_virtmem_buddy.mem_start, high_bound = kern_virtmem_buddy.mem_end; - uintptr_t user_low_bound = user_phy_freemem_buddy.mem_start, user_high_bound = user_phy_freemem_buddy.mem_end; uintptr_t end_idx = USER_MEM_TOP >> LEVEL3_PDE_SHIFT; for (uintptr_t level4_entry_idx = 0; level4_entry_idx < end_idx; level4_entry_idx++) { // free each level4 page table uintptr_t* pgtbl_paddr = (uintptr_t*)LEVEL4_PTE_ADDR(pgdir->pd_addr[level4_entry_idx]); if (pgtbl_paddr != NULL) { - // free each page - for (uintptr_t page_entry_idx = 0; page_entry_idx < NUM_LEVEL4_PTE; page_entry_idx++) { - uintptr_t vaddr = (level4_entry_idx << LEVEL3_PDE_SHIFT) | (page_entry_idx << LEVEL4_PTE_SHIFT); - - // get page paddr - uintptr_t* page_paddr = (uintptr_t*)ALIGNDOWN(((uintptr_t*)P2V(pgtbl_paddr))[page_entry_idx], PAGE_SIZE); - if (page_paddr != NULL) { - // IPC vaddr should not be addressed here. - assert(vaddr < USER_IPC_SPACE_BASE || vaddr >= USER_IPC_SPACE_TOP); - - if (LIKELY((uintptr_t)page_paddr >= low_bound && (uintptr_t)page_paddr < high_bound)) { - kfree(P2V(page_paddr)); - } else if (LIKELY((uintptr_t)page_paddr >= user_low_bound && (uintptr_t)page_paddr < user_high_bound)) { - raw_free((char*)page_paddr); - } - } - } kfree(P2V(pgtbl_paddr)); } } diff --git a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_level3.c b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_level3.c index f0795177f..f9501b6f8 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_level3.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_level3.c @@ -48,7 +48,7 @@ uintptr_t* _page_walk(uintptr_t* pgdir, uintptr_t vaddr, bool alloc) uintptr_t* l3_pde_vaddr; if (*l2_pde_ptr != 0) { - uintptr_t l3_table_paddr = (*l2_pde_ptr) & ~pde_attr; + uintptr_t l3_table_paddr = ALIGNDOWN(*l2_pde_ptr, PAGE_SIZE); l3_pde_vaddr = (uintptr_t*)P2V(l3_table_paddr); } else { if (!alloc || !(l3_pde_vaddr = (uintptr_t*)kalloc(sizeof(uintptr_t) * NUM_LEVEL3_PDE))) { @@ -63,7 +63,7 @@ uintptr_t* _page_walk(uintptr_t* pgdir, uintptr_t vaddr, bool alloc) uintptr_t* l4_pte_vaddr; if (*l3_pde_ptr != 0) { - uintptr_t l4_table_paddr = (*l3_pde_ptr) & ~pde_attr; + uintptr_t l4_table_paddr = ALIGNDOWN(*l3_pde_ptr, PAGE_SIZE); l4_pte_vaddr = (uintptr_t*)P2V(l4_table_paddr); } else { if (!alloc || !(l4_pte_vaddr = (uintptr_t*)kalloc(sizeof(uintptr_t) * NUM_LEVEL4_PTE))) { @@ -83,8 +83,6 @@ void _free_user_pgdir(struct TopLevelPageDirectory* pgdir) return; } - uintptr_t low_bound = kern_virtmem_buddy.mem_start, high_bound = kern_virtmem_buddy.mem_end; - uintptr_t user_low_bound = user_phy_freemem_buddy.mem_start, user_high_bound = user_phy_freemem_buddy.mem_end; uintptr_t end_idx = (USER_MEM_TOP >> LEVEL2_PDE_SHIFT) & (NUM_LEVEL2_PDE - 1); for (uintptr_t l2_entry_idx = 0; l2_entry_idx < end_idx; l2_entry_idx++) { @@ -95,23 +93,6 @@ void _free_user_pgdir(struct TopLevelPageDirectory* pgdir) for (uintptr_t l3_entry_idx = 0; l3_entry_idx < NUM_LEVEL3_PDE; l3_entry_idx++) { uintptr_t* l4_table_paddr = (uintptr_t*)LEVEL4_PTE_ADDR(l3_table_vaddr[l3_entry_idx]); if (l4_table_paddr != NULL) { - uintptr_t* l4_table_vaddr = P2V(l4_table_paddr); - for (uintptr_t page_entry_idx = 0; page_entry_idx < NUM_LEVEL4_PTE; page_entry_idx++) { - uintptr_t vaddr = (l2_entry_idx << LEVEL2_PDE_SHIFT) | (l3_entry_idx << LEVEL3_PDE_SHIFT) | (page_entry_idx << LEVEL4_PTE_SHIFT); - - // get page paddr - uintptr_t* page_paddr = (uintptr_t*)ALIGNDOWN((l4_table_vaddr)[page_entry_idx], PAGE_SIZE); - if (page_paddr != NULL) { - // Ensure the virtual address is not in the IPC address space - assert(vaddr < USER_IPC_SPACE_BASE || vaddr >= USER_IPC_SPACE_TOP); - - if (LIKELY((uintptr_t)page_paddr >= low_bound && (uintptr_t)page_paddr < high_bound)) { - kfree(P2V(page_paddr)); - } else if (LIKELY((uintptr_t)page_paddr >= user_low_bound && (uintptr_t)page_paddr < user_high_bound)) { - raw_free((char*)page_paddr); - } - } - } kfree(P2V(l4_table_paddr)); } } diff --git a/Ubiquitous/XiZi_AIoT/softkernel/memory/share_page.c b/Ubiquitous/XiZi_AIoT/softkernel/memory/share_page.c index aa9ff1fcf..a728cfb3f 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/memory/share_page.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/memory/share_page.c @@ -111,7 +111,7 @@ static uintptr_t map_task_share_page(struct Thread* task, const uintptr_t paddr, vaddr = alloc_share_page_addr(task, nr_pages * 2); // time to use buddy - if (vaddr >= USER_IPC_USE_ALLOCATOR_WATERMARK) { + if (vaddr + (2 * nr_pages * PAGE_SIZE) >= USER_IPC_USE_ALLOCATOR_WATERMARK) { task->memspace->massive_ipc_allocator = (struct KBuddy*)slab_alloc(&xizi_task_manager.task_buddy_allocator); if (!task->memspace->massive_ipc_allocator) { ERROR("Alloc task buddy failed.\n"); @@ -133,12 +133,12 @@ static uintptr_t map_task_share_page(struct Thread* task, const uintptr_t paddr, } // map first area - if (!xizi_pager.map_pages(task->memspace->pgdir.pd_addr, vaddr, paddr, nr_pages * PAGE_SIZE, false)) { + if (!xizi_pager.map_pages(task->memspace, vaddr, paddr, nr_pages * PAGE_SIZE, false)) { return (uintptr_t)NULL; } // map second area - if (!xizi_pager.map_pages(task->memspace->pgdir.pd_addr, vaddr + (nr_pages * PAGE_SIZE), paddr, nr_pages * PAGE_SIZE, false)) { + if (!xizi_pager.map_pages(task->memspace, vaddr + (nr_pages * PAGE_SIZE), paddr, nr_pages * PAGE_SIZE, false)) { xizi_pager.unmap_pages(task->memspace->pgdir.pd_addr, vaddr, nr_pages * PAGE_SIZE); return (uintptr_t)NULL; } @@ -161,9 +161,9 @@ uintptr_t task_map_pages(struct Thread* task, const uintptr_t vaddr, const uintp bool ret = false; if (is_dev) { - ret = xizi_pager.map_pages(task->memspace->pgdir.pd_addr, vaddr, paddr, nr_pages * PAGE_SIZE, true); + ret = xizi_pager.map_pages(task->memspace, vaddr, paddr, nr_pages * PAGE_SIZE, true); } else { - ret = xizi_pager.map_pages(task->memspace->pgdir.pd_addr, vaddr, paddr, nr_pages * PAGE_SIZE, false); + ret = xizi_pager.map_pages(task->memspace, vaddr, paddr, nr_pages * PAGE_SIZE, false); } if (!ret) { diff --git a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_kill.c b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_kill.c index dbb11d0e1..9510ca226 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_kill.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_kill.c @@ -53,6 +53,17 @@ int sys_kill(int id) } } + struct ksemaphore* sem = NULL; + DOUBLE_LIST_FOR_EACH_ENTRY(sem, &xizi_task_manager.semaphore_pool.sem_list_guard, sem_list_node) + { + task = NULL; + DOUBLE_LIST_FOR_EACH_ENTRY(task, &sem->wait_list_guard, node) + { + sys_exit(task); + return 0; + } + } + // check if task is a ready one for (int prio = 0; prio < TASK_MAX_PRIORITY; prio++) { DOUBLE_LIST_FOR_EACH_ENTRY(task, &xizi_task_manager.task_list_head[prio], node) diff --git a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_mmap.c b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_mmap.c index 432d910e6..becf0b9d7 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_mmap.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_mmap.c @@ -1,71 +1,72 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ -/** - * @file sys_mmap.c - * @brief map task phy address to virt address - * @version 3.0 - * @author AIIT XUOS Lab - * @date 2023.08.25 - */ - -/************************************************* -File name: sys_mmap.c -Description: map task phy address to virt address -Others: -History: -1. Date: 2023-08-28 -Author: AIIT XUOS Lab -Modification: -1. first version -*************************************************/ -#include - -#include "assert.h" -#include "kalloc.h" -#include "multicores.h" -#include "share_page.h" -#include "syscall.h" -#include "task.h" - -int sys_mmap(uintptr_t* vaddr, uintptr_t* paddr, int len, int is_dev) -{ - struct Thread* cur_task = cur_cpu()->task; - assert(cur_task != NULL); - - int true_len = ALIGNUP(len, PAGE_SIZE); - - if (*paddr != (uintptr_t)NULL) { - if (xizi_share_page_manager.task_map_pages(cur_task, *vaddr, *paddr, true_len / PAGE_SIZE, is_dev) == (uintptr_t)NULL) { - return -1; - } - } else { - int load_len = 0; - uintptr_t load_vaddr = *vaddr; - while (load_len < true_len) { - char* new_paddr = raw_alloc(PAGE_SIZE); - if (new_paddr == NULL) { - return -1; - } - if (xizi_share_page_manager.task_map_pages(cur_task, load_vaddr, (uintptr_t)new_paddr, 1, false) == (uintptr_t)NULL) { - raw_free(new_paddr); - return -1; - } - load_vaddr += PAGE_SIZE; - load_len += PAGE_SIZE; - *paddr = (uintptr_t)new_paddr; - } - } - - cur_task->memspace->mem_size += true_len; - *vaddr = *vaddr + true_len; - return 0; +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file sys_mmap.c + * @brief map task phy address to virt address + * @version 3.0 + * @author AIIT XUOS Lab + * @date 2023.08.25 + */ + +/************************************************* +File name: sys_mmap.c +Description: map task phy address to virt address +Others: +History: +1. Date: 2023-08-28 +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#include + +#include "assert.h" +#include "kalloc.h" +#include "multicores.h" +#include "share_page.h" +#include "syscall.h" +#include "task.h" + +int sys_mmap(uintptr_t* vaddr, uintptr_t* paddr, int len, int is_dev) +{ + struct Thread* cur_task = cur_cpu()->task; + assert(cur_task != NULL); + + int true_len = ALIGNUP(len, PAGE_SIZE); + + if (*paddr != (uintptr_t)NULL) { + if (*paddr >= PHY_MEM_BASE && *paddr < PHY_MEM_STOP && cur_task->tid > 1) { + ERROR("mapping invalid memory: 0x%p\n", *paddr); + return -1; + } + + if (xizi_share_page_manager.task_map_pages(cur_task, *vaddr, *paddr, true_len / PAGE_SIZE, is_dev) == (uintptr_t)NULL) { + return -1; + } + } else { + uintptr_t load_vaddr = *vaddr; + char* new_paddr = raw_alloc(true_len); + if (new_paddr == NULL) { + return -1; + } + if (xizi_share_page_manager.task_map_pages(cur_task, load_vaddr, (uintptr_t)new_paddr, true_len / PAGE_SIZE, false) == (uintptr_t)NULL) { + raw_free(new_paddr); + return -1; + } + CreateResourceTag(NULL, &cur_task->memspace->tag, NULL, TRACER_MEM_FROM_BUDDY_AC_RESOURCE, new_paddr); + *paddr = (uintptr_t)new_paddr; + } + + cur_task->memspace->mem_size += true_len; + *vaddr = *vaddr + true_len; + return 0; } \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_poll_session.c b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_poll_session.c index b1c751719..55451238e 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_poll_session.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_poll_session.c @@ -52,6 +52,7 @@ int sys_poll_session(struct Session* userland_session_arr, int arr_capacity) struct double_list_node* cur_node = NULL; struct server_session* server_session = NULL; + /* update old sessions */ for (int i = 0; i < arr_capacity; i++) { if (UNLIKELY(userland_session_arr[i].buf == NULL)) { @@ -70,7 +71,7 @@ int sys_poll_session(struct Session* userland_session_arr, int arr_capacity) if (client->state == BLOCKED) { xizi_task_manager.task_unblock(client); } else { - client->current_ipc_handled = true; + client->advance_unblock = true; } } server_session->head = userland_session_arr[i].head; @@ -111,17 +112,22 @@ int sys_poll_session(struct Session* userland_session_arr, int arr_capacity) }; struct IpcMsg* msg = IPCSESSION_MSG(&userland_session_arr[session_idx]); - if (is_msg_needed(msg)) { + if (msg != NULL && is_msg_needed(msg)) { nr_sessions_need_to_handle++; } session_idx++; } + if (session_idx < arr_capacity) { userland_session_arr[session_idx].buf = NULL; if (!has_middle_delete && nr_sessions_need_to_handle == 0) { - xizi_task_manager.task_yield_noschedule(cur_task, false); - xizi_task_manager.task_block(&xizi_task_manager.task_blocked_list_head, cur_task); + if (cur_task->advance_unblock) { + cur_task->advance_unblock = false; + } else { + xizi_task_manager.task_yield_noschedule(cur_task, false); + xizi_task_manager.task_block(&xizi_task_manager.task_blocked_list_head, cur_task); + } } } diff --git a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_state.c b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_state.c index 47817ea14..67aea6b05 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_state.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_state.c @@ -1,190 +1,190 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ -/** - * @file sys_state.c - * @brief task ask for kernel status(for debug perpose) - * @version 3.0 - * @author AIIT XUOS Lab - * @date 2023.08.25 - */ - -/************************************************* -File name: sys_state.c -Description: task ask for kernel status(for debug perpose) -Others: -History: -1. Date: 2023-08-28 -Author: AIIT XUOS Lab -Modification: -1. first version -*************************************************/ -#include -#include - -#include "assert.h" -#include "buddy.h" -#include "log.h" -#include "multicores.h" -#include "pagetable.h" -#include "syscall.h" -#include "task.h" - -extern uint8_t _binary_fs_img_start[], _binary_fs_img_end[]; - -#define SHOWINFO_BORDER_LINE() LOG_PRINTF("******************************************************\n"); -#define SHOWTASK_TASK_BASE_INFO(task) LOG_PRINTF(" %-6d %-16s %-4d 0x%x(%-d)\n", task->tid, task->name, task->priority, task->memspace->mem_size >> 10, task->memspace->mem_size >> 10) - -void show_tasks(void) -{ - struct Thread* task = NULL; - SHOWINFO_BORDER_LINE(); - for (int i = 0; i < NR_CPU; i++) { - LOG_PRINTF("CPU %-2d: %s\n", i, (global_cpus[i].task == NULL ? "NULL" : global_cpus[i].task->name)); - } - SHOWINFO_BORDER_LINE(); - LOG_PRINTF("%-8s %-6s %-16s %-4s %-8s\n", "STAT", "ID", "TASK", "PRI", "MEM(KB)"); - DOUBLE_LIST_FOR_EACH_ENTRY(task, &xizi_task_manager.task_running_list_head, node) - { - LOG_PRINTF("%-8s", "RUNNING"); - SHOWTASK_TASK_BASE_INFO(task); - } - - for (int i = 0; i < TASK_MAX_PRIORITY; i++) { - if (IS_DOUBLE_LIST_EMPTY(&xizi_task_manager.task_list_head[i])) { - continue; - } - DOUBLE_LIST_FOR_EACH_ENTRY(task, &xizi_task_manager.task_list_head[i], node) - { - switch (task->state) { - case INIT: - LOG_PRINTF("%-8s", "INIT"); - break; - case READY: - LOG_PRINTF("%-8s", "READY"); - break; - case RUNNING: - LOG_PRINTF("%-8s", "RUNNING"); - break; - case DEAD: - LOG_PRINTF("%-8s", "DEAD"); - break; - default: - break; - } - - SHOWTASK_TASK_BASE_INFO(task); - } - } - - DOUBLE_LIST_FOR_EACH_ENTRY(task, &xizi_task_manager.task_blocked_list_head, node) - { - LOG_PRINTF("%-8s", "BLOCK"); - SHOWTASK_TASK_BASE_INFO(task); - } - - struct ksemaphore* sem = NULL; - DOUBLE_LIST_FOR_EACH_ENTRY(sem, &xizi_task_manager.semaphore_pool.sem_list_guard, sem_list_node) - { - task = NULL; - DOUBLE_LIST_FOR_EACH_ENTRY(task, &sem->wait_list_guard, node) - { - LOG_PRINTF("%-8s", "BLOCK"); - SHOWTASK_TASK_BASE_INFO(task); - } - } - - SHOWINFO_BORDER_LINE(); - return; -} - -extern struct KBuddy user_phy_freemem_buddy; -extern struct KBuddy kern_virtmem_buddy; -extern uintptr_t kernel_data_end[]; -void show_mem(void) -{ - SHOWINFO_BORDER_LINE(); - - uint64_t total = (PHY_MEM_STOP - V2P(kernel_data_end)); - uint64_t user_dynamic_free = 0; - uint64_t kernel_free = 0; - for (int j = 0; j < MAX_BUDDY_ORDER; j++) { - user_dynamic_free += user_phy_freemem_buddy.free_list[j].n_free_pages * (1 << j) * PAGE_SIZE; - kernel_free += kern_virtmem_buddy.free_list[j].n_free_pages * (1 << j) * PAGE_SIZE; - } - LOG_PRINTF("%-16s 0x%016lx\n", "TOTAL(B)", total); - LOG_PRINTF("%-16s 0x%016lx\n", "KERNEL USED(B)", (kern_virtmem_buddy.mem_end - kern_virtmem_buddy.mem_start - kernel_free)); - LOG_PRINTF("%-16s 0x%016lx\n", "LIBMEM USED(B)", (user_phy_freemem_buddy.mem_end - user_phy_freemem_buddy.mem_start - user_dynamic_free)); - LOG_PRINTF("%-16s 0x%016lx\n", "FREE(B)", user_dynamic_free + kernel_free); - - SHOWINFO_BORDER_LINE(); - return; -} - -void show_cpu(void) -{ - LOG_PRINTF("**********************************************************\n"); -#ifdef ARCH_SMP - /// @todo support smp - KPrintf(" cpu VALUE \n"); -#endif - - int cpu_id = 0; - - struct Thread* current_task = cur_cpu()->task; - assert(current_task != NULL); - - LOG_PRINTF(" ID COMMAND USED_TICKS FREE_TICKS \n"); - LOG_PRINTF(" %d %s %d %d\n", cpu_id, current_task->name, TASK_CLOCK_TICK - current_task->remain_tick, current_task->remain_tick); - - LOG_PRINTF("***********************************************************\n"); - return; -} - -int sys_state(sys_state_option option, sys_state_info* info) -{ - switch (option) { - case SYS_STATE_MEMBLOCK_INFO: { - info->memblock_info.memblock_start = (uintptr_t)V2P(_binary_fs_img_start); - info->memblock_info.memblock_end = (uintptr_t)V2P(_binary_fs_img_end); - break; - } - case SYS_STATE_GET_HEAP_BASE: - return cur_cpu()->task->memspace->heap_base; - case SYS_STATE_SET_TASK_PRIORITY: - xizi_task_manager.set_cur_task_priority(info->priority); - break; - case SYS_STATE_SHOW_TASKS: - show_tasks(); - break; - case SYS_STATE_SHOW_MEM_INFO: - show_mem(); - break; - case SYS_STATE_SHOW_CPU_INFO: - show_cpu(); - break; - case SYS_STATE_GET_CURRENT_TICK: { - extern void hw_current_tick(uintptr_t * tick); - hw_current_tick(&info->current_tick); - break; - } - case SYS_STATE_GET_CURRENT_SECOND: { - extern void hw_current_second(uintptr_t * tick); - hw_current_second(&info->current_second); - break; - } - case SYS_STATE_TEST: - default: - break; - } - - return 0; +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file sys_state.c + * @brief task ask for kernel status(for debug perpose) + * @version 3.0 + * @author AIIT XUOS Lab + * @date 2023.08.25 + */ + +/************************************************* +File name: sys_state.c +Description: task ask for kernel status(for debug perpose) +Others: +History: +1. Date: 2023-08-28 +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#include +#include + +#include "assert.h" +#include "buddy.h" +#include "log.h" +#include "multicores.h" +#include "pagetable.h" +#include "syscall.h" +#include "task.h" + +extern uint8_t _binary_fs_img_start[], _binary_fs_img_end[]; + +#define SHOWINFO_BORDER_LINE() LOG_PRINTF("******************************************************\n"); +#define SHOWTASK_TASK_BASE_INFO(task) LOG_PRINTF(" %-6d %-16s %-4d 0x%x(%-d)\n", task->tid, task->name, task->priority, task->memspace->mem_size >> 10, task->memspace->mem_size >> 10) + +void show_tasks(void) +{ + struct Thread* task = NULL; + SHOWINFO_BORDER_LINE(); + for (int i = 0; i < NR_CPU; i++) { + LOG_PRINTF("CPU %-2d: %s\n", i, (global_cpus[i].task == NULL ? "NULL" : global_cpus[i].task->name)); + } + SHOWINFO_BORDER_LINE(); + LOG_PRINTF("%-8s %-6s %-16s %-4s %-8s\n", "STAT", "ID", "TASK", "PRI", "MEM(KB)"); + DOUBLE_LIST_FOR_EACH_ENTRY(task, &xizi_task_manager.task_running_list_head, node) + { + LOG_PRINTF("%-8s", "RUNNING"); + SHOWTASK_TASK_BASE_INFO(task); + } + + for (int i = 0; i < TASK_MAX_PRIORITY; i++) { + if (IS_DOUBLE_LIST_EMPTY(&xizi_task_manager.task_list_head[i])) { + continue; + } + DOUBLE_LIST_FOR_EACH_ENTRY(task, &xizi_task_manager.task_list_head[i], node) + { + switch (task->state) { + case INIT: + LOG_PRINTF("%-8s", "INIT"); + break; + case READY: + LOG_PRINTF("%-8s", "READY"); + break; + case RUNNING: + LOG_PRINTF("%-8s", "RUNNING"); + break; + case DEAD: + LOG_PRINTF("%-8s", "DEAD"); + break; + default: + break; + } + + SHOWTASK_TASK_BASE_INFO(task); + } + } + + DOUBLE_LIST_FOR_EACH_ENTRY(task, &xizi_task_manager.task_blocked_list_head, node) + { + LOG_PRINTF("%-8s", "BLOCK"); + SHOWTASK_TASK_BASE_INFO(task); + } + + struct ksemaphore* sem = NULL; + DOUBLE_LIST_FOR_EACH_ENTRY(sem, &xizi_task_manager.semaphore_pool.sem_list_guard, sem_list_node) + { + task = NULL; + DOUBLE_LIST_FOR_EACH_ENTRY(task, &sem->wait_list_guard, node) + { + LOG_PRINTF("%-8s", "BLOCK"); + SHOWTASK_TASK_BASE_INFO(task); + } + } + + SHOWINFO_BORDER_LINE(); + return; +} + +extern struct KBuddy user_phy_freemem_buddy; +extern struct KBuddy kern_virtmem_buddy; +extern uintptr_t kernel_data_end[]; +void show_mem(void) +{ + SHOWINFO_BORDER_LINE(); + + uint64_t total = (PHY_MEM_STOP - V2P(kernel_data_end)); + uint64_t user_dynamic_free = 0; + uint64_t kernel_free = 0; + for (int j = 0; j < MAX_BUDDY_ORDER; j++) { + user_dynamic_free += user_phy_freemem_buddy.free_list[j].n_free_pages * (1 << j) * PAGE_SIZE; + kernel_free += kern_virtmem_buddy.free_list[j].n_free_pages * (1 << j) * PAGE_SIZE; + } + LOG_PRINTF("%-16s 0x%016lx\n", "TOTAL(B)", total); + LOG_PRINTF("%-16s 0x%016lx\n", "KERNEL USED(B)", (kern_virtmem_buddy.mem_end - kern_virtmem_buddy.mem_start - kernel_free)); + LOG_PRINTF("%-16s 0x%016lx\n", "LIBMEM USED(B)", (user_phy_freemem_buddy.mem_end - user_phy_freemem_buddy.mem_start - user_dynamic_free)); + LOG_PRINTF("%-16s 0x%016lx\n", "FREE(B)", user_dynamic_free + kernel_free); + + SHOWINFO_BORDER_LINE(); + return; +} + +void show_cpu(void) +{ + LOG_PRINTF("**********************************************************\n"); +#ifdef ARCH_SMP + /// @todo support smp + KPrintf(" cpu VALUE \n"); +#endif + + int cpu_id = 0; + + struct Thread* current_task = cur_cpu()->task; + assert(current_task != NULL); + + LOG_PRINTF(" ID COMMAND USED_TICKS FREE_TICKS \n"); + LOG_PRINTF(" %d %s %d %d\n", cpu_id, current_task->name, TASK_CLOCK_TICK - current_task->remain_tick, current_task->remain_tick); + + LOG_PRINTF("***********************************************************\n"); + return; +} + +int sys_state(sys_state_option option, sys_state_info* info) +{ + switch (option) { + case SYS_STATE_MEMBLOCK_INFO: { + info->memblock_info.memblock_start = (uintptr_t)V2P(_binary_fs_img_start); + info->memblock_info.memblock_end = (uintptr_t)V2P(_binary_fs_img_end); + break; + } + case SYS_STATE_GET_HEAP_BASE: + return cur_cpu()->task->memspace->heap_base; + case SYS_STATE_SET_TASK_PRIORITY: + xizi_task_manager.set_cur_task_priority(info->priority); + break; + case SYS_STATE_SHOW_TASKS: + show_tasks(); + break; + case SYS_STATE_SHOW_MEM_INFO: + show_mem(); + break; + case SYS_STATE_SHOW_CPU_INFO: + show_cpu(); + break; + case SYS_STATE_GET_CURRENT_TICK: { + extern void hw_current_tick(uintptr_t * tick); + hw_current_tick(&info->current_tick); + break; + } + case SYS_STATE_GET_CURRENT_SECOND: { + extern void hw_current_second(uintptr_t * tick); + hw_current_second(&info->current_second); + break; + } + case SYS_STATE_TEST: + default: + break; + } + + return 0; } \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_thread.c b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_thread.c index 5d08d655e..f98ed1c81 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_thread.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_thread.c @@ -65,6 +65,11 @@ int sys_new_thread(struct MemSpace* pmemspace, struct Thread* task, uintptr_t en // init pcb schedule attributes xizi_task_manager.task_set_default_schedule_attr(task); + // thread init done by here + if (pmemspace->thread_to_notify == NULL) { + pmemspace->thread_to_notify = task; + } + return task->tid; } diff --git a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_yield.c b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_yield.c index 0db107e04..45c3f468f 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_yield.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_yield.c @@ -40,21 +40,22 @@ int sys_yield(task_yield_reason reason) // handle ipc block if ((reason & SYS_TASK_YIELD_BLOCK_IPC) != 0) { - if (cur_task->current_ipc_handled) { - cur_task->current_ipc_handled = false; + if (cur_task->advance_unblock) { + cur_task->advance_unblock = false; + return 0; } else { xizi_task_manager.task_block(&xizi_task_manager.task_blocked_list_head, cur_task); } - } - // wake up all possible server - struct client_session* client_session = NULL; - DOUBLE_LIST_FOR_EACH_ENTRY(client_session, &cur_task->cli_sess_listhead, node) - { - assert(client_session != NULL); - struct session_backend* session_backend = CLIENT_SESSION_BACKEND(client_session); - if (session_backend->server->state == BLOCKED) { - xizi_task_manager.task_unblock(session_backend->server); + // wake up all possible server + struct client_session* client_session = NULL; + DOUBLE_LIST_FOR_EACH_ENTRY(client_session, &cur_task->cli_sess_listhead, node) + { + assert(client_session != NULL); + struct session_backend* session_backend = CLIENT_SESSION_BACKEND(client_session); + if (session_backend->server->state == BLOCKED) { + xizi_task_manager.task_unblock(session_backend->server); + } } } diff --git a/Ubiquitous/XiZi_AIoT/softkernel/syscall/syscall.c b/Ubiquitous/XiZi_AIoT/softkernel/syscall/syscall.c index f5cd4c528..d3ae51f67 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/syscall/syscall.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/syscall/syscall.c @@ -1,90 +1,90 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ -/** - * @file syscall.c - * @brief syscall distributor - * @version 3.0 - * @author AIIT XUOS Lab - * @date 2023.08.25 - */ - -/************************************************* -File name: syscall.c -Description: syscall distributor -Others: -History: -1. Date: 2023-08-28 -Author: AIIT XUOS Lab -Modification: -1. first version -*************************************************/ -#include "log.h" -#include "multicores.h" -#include "trap_common.h" - -#include "syscall.h" - -int syscall(int sys_num, uintptr_t param1, uintptr_t param2, uintptr_t param3, uintptr_t param4) -{ - int ret = -1; - - switch (sys_num) { - case SYSCALL_TEST: - ret = 0; - break; - case SYSCALL_SPAWN: - ret = sys_spawn((char*)param1, (char*)param2, (char**)param3); - break; - case SYSCALL_THREAD: - ret = sys_thread((uintptr_t)param1, (char*)param2, (char**)param3); - break; - case SYSCALL_EXIT: - ret = sys_exit(cur_cpu()->task); - break; - case SYSCALL_YIELD: - ret = sys_yield((task_yield_reason)param1); - break; - case SYSCALL_SERVER: - ret = sys_register_as_server((char*)param1); - break; - case SYSCALL_SESSION: - ret = sys_connect_session((char*)param1, (int)param2, (struct Session*)param3); - break; - case SYSCALL_POLL_SESSION: - ret = sys_poll_session((struct Session*)param1, (int)param2); - break; - case SYSCALL_CLOSE_SESSION: - ret = sys_close_session(cur_cpu()->task, (struct Session*)param1); - break; - case SYSCALL_SYS_STATE: - ret = sys_state(param1, (sys_state_info*)param2); - break; - case SYSCALL_MMAP: - ret = sys_mmap((uintptr_t*)param1, (uintptr_t*)param2, (int)param3, (int)param4); - break; - case SYSCALL_REGISTER_IRQ: - ret = sys_register_irq((int)param1, (int)param2); - break; - case SYSCALL_KILL: - ret = sys_kill((int)param1); - break; - case SYSCALL_SEMAPHORE: - ret = sys_semaphore((sys_sem_option)param1, (int)param2); - break; - default: - ERROR("Unsurport syscall(%d) right now\n", sys_num); - ret = -1; - break; - } - - return ret; +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file syscall.c + * @brief syscall distributor + * @version 3.0 + * @author AIIT XUOS Lab + * @date 2023.08.25 + */ + +/************************************************* +File name: syscall.c +Description: syscall distributor +Others: +History: +1. Date: 2023-08-28 +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#include "log.h" +#include "multicores.h" +#include "trap_common.h" + +#include "syscall.h" + +int syscall(int sys_num, uintptr_t param1, uintptr_t param2, uintptr_t param3, uintptr_t param4) +{ + int ret = -1; + + switch (sys_num) { + case SYSCALL_TEST: + ret = 0; + break; + case SYSCALL_SPAWN: + ret = sys_spawn((char*)param1, (char*)param2, (char**)param3); + break; + case SYSCALL_THREAD: + ret = sys_thread((uintptr_t)param1, (char*)param2, (char**)param3); + break; + case SYSCALL_EXIT: + ret = sys_exit(cur_cpu()->task); + break; + case SYSCALL_YIELD: + ret = sys_yield((task_yield_reason)param1); + break; + case SYSCALL_SERVER: + ret = sys_register_as_server((char*)param1); + break; + case SYSCALL_SESSION: + ret = sys_connect_session((char*)param1, (int)param2, (struct Session*)param3); + break; + case SYSCALL_POLL_SESSION: + ret = sys_poll_session((struct Session*)param1, (int)param2); + break; + case SYSCALL_CLOSE_SESSION: + ret = sys_close_session(cur_cpu()->task, (struct Session*)param1); + break; + case SYSCALL_SYS_STATE: + ret = sys_state(param1, (sys_state_info*)param2); + break; + case SYSCALL_MMAP: + ret = sys_mmap((uintptr_t*)param1, (uintptr_t*)param2, (int)param3, (int)param4); + break; + case SYSCALL_REGISTER_IRQ: + ret = sys_register_irq((int)param1, (int)param2); + break; + case SYSCALL_KILL: + ret = sys_kill((int)param1); + break; + case SYSCALL_SEMAPHORE: + ret = sys_semaphore((sys_sem_option)param1, (int)param2); + break; + default: + ERROR("Unsurport syscall(%d) right now\n", sys_num); + ret = -1; + break; + } + + return ret; } \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/softkernel/task/memspace.c b/Ubiquitous/XiZi_AIoT/softkernel/task/memspace.c index a16509eed..3fce45d05 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/task/memspace.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/task/memspace.c @@ -32,11 +32,11 @@ Modification: #include #include +#include "assert.h" #include "bitmap64.h" #include "execelf.h" #include "kalloc.h" #include "memspace.h" -#include "pagetable.h" #include "task.h" #define MAX_SUPPORT_PARAMS 32 @@ -55,6 +55,8 @@ struct MemSpace* alloc_memspace() pmemspace->heap_base = 0; pmemspace->mem_size = 0; pmemspace->pgdir.pd_addr = 0; + pmemspace->thread_to_notify = NULL; + CreateResourceTag(&pmemspace->tag, &xizi_task_manager.tag, NULL, TRACER_OWNER, (void*)pmemspace); return pmemspace; } @@ -67,12 +69,24 @@ void free_memspace(struct MemSpace* pmemspace) xizi_pager.free_user_pgdir(&pmemspace->pgdir); } + TracerNode* tmp_node = NULL; + DOUBLE_LIST_FOR_EACH_ENTRY(tmp_node, &pmemspace->tag.meta->children_guard, list_node) + { + assert((uintptr_t)tmp_node->p_resource >= PHY_MEM_BASE && (uintptr_t)tmp_node->p_resource < PHY_MEM_STOP); + if ((uintptr_t)tmp_node->p_resource < PHY_USER_FREEMEM_BASE) { + kfree(P2V(tmp_node->p_resource)); + } else { + raw_free(tmp_node->p_resource); + } + } + /* free ipc virt address allocator */ if (pmemspace->massive_ipc_allocator != NULL) { KBuddyDestory(pmemspace->massive_ipc_allocator); slab_free(&xizi_task_manager.task_buddy_allocator, (void*)pmemspace->massive_ipc_allocator); } + DeleteResource(&pmemspace->tag, &xizi_task_manager.tag); slab_free(&xizi_task_manager.memspace_allocator, (void*)pmemspace); } @@ -100,14 +114,12 @@ uintptr_t* load_memspace(struct MemSpace* pmemspace, char* img_start) /* allocate a pgdir */ /* only supports first inited memspace */ assert(pmemspace->pgdir.pd_addr == NULL); - struct TopLevelPageDirectory pgdir; - pgdir.pd_addr = NULL; - if (UNLIKELY(!xizi_pager.new_pgdir(&pgdir))) { + if (UNLIKELY(!xizi_pager.new_pgdir(&pmemspace->pgdir))) { ERROR("Create new pgdir failed.\n"); goto error_exec; } /* copy kernel pagetable so that interrupt and syscall wont corrupt */ - memcpy(pgdir.pd_addr, kern_pgdir.pd_addr, TOPLEVLE_PAGEDIR_SIZE); + memcpy(pmemspace->pgdir.pd_addr, kern_pgdir.pd_addr, TOPLEVLE_PAGEDIR_SIZE); // read elf file by (header, section) uintptr_t load_size = 0; @@ -125,7 +137,7 @@ uintptr_t* load_memspace(struct MemSpace* pmemspace, char* img_start) // read section // 1. alloc space - if ((load_size = xizi_pager.resize_user_pgdir(&pgdir, load_size, ph.vaddr + ph.memsz)) + if ((load_size = xizi_pager.resize_user_pgdir(pmemspace, load_size, ph.vaddr + ph.memsz)) != ph.vaddr + ph.memsz) { ERROR("Add uspace size failed.\n"); goto error_exec; @@ -134,10 +146,11 @@ uintptr_t* load_memspace(struct MemSpace* pmemspace, char* img_start) if (ph.vaddr % PAGE_SIZE != 0) { LOG("Unsupported elf file, try use flag -N to compile.\n"); } + for (int addr_offset = 0; addr_offset < ph.filesz; addr_offset += PAGE_SIZE) { - uintptr_t page_paddr = xizi_pager.address_translate(&pgdir, ph.vaddr + addr_offset); + uintptr_t page_paddr = xizi_pager.address_translate(&pmemspace->pgdir, ph.vaddr + addr_offset); if (page_paddr == 0) { - ERROR("copy elf file to unmapped addr: %x(pgdir: %x)\n", ph.vaddr + addr_offset, pgdir.pd_addr); + ERROR("copy elf file to unmapped addr: %x(pgdir: %x)\n", ph.vaddr + addr_offset, pmemspace->pgdir.pd_addr); goto error_exec; } uintptr_t read_size = (ph.filesz - addr_offset < PAGE_SIZE ? ph.filesz - addr_offset : PAGE_SIZE); @@ -147,15 +160,15 @@ uintptr_t* load_memspace(struct MemSpace* pmemspace, char* img_start) /// elf file content now in memory // memspace will use this page dir - pmemspace->pgdir = pgdir; pmemspace->heap_base = ALIGNUP(load_size, PAGE_SIZE); pmemspace->mem_size = pmemspace->heap_base; return (uintptr_t*)elf.entry; error_exec: - if (pgdir.pd_addr != NULL) { - xizi_pager.free_user_pgdir(&pgdir); + if (pmemspace->pgdir.pd_addr != NULL) { + xizi_pager.free_user_pgdir(&pmemspace->pgdir); + pmemspace->pgdir.pd_addr = NULL; } ERROR("Error loading memspace.\n"); return NULL; @@ -208,7 +221,7 @@ struct ThreadStackPointer load_user_stack(struct MemSpace* pmemspace, char** arg } /* map memory to user stack space in memspace*/ - if (!xizi_pager.map_pages(pmemspace->pgdir.pd_addr, USER_MEM_TOP - ((stack_idx + 1) * USER_STACK_SIZE), V2P(stack_bottom), USER_STACK_SIZE, false)) { + if (!xizi_pager.map_pages(pmemspace, USER_MEM_TOP - ((stack_idx + 1) * USER_STACK_SIZE), V2P(stack_bottom), USER_STACK_SIZE, false)) { /* this could only fail due to inner page directory's allocation failure */ ERROR("User stack map failed\n"); handle_error_stack_loading(pmemspace, stack_idx, stack_bottom, false); @@ -246,8 +259,8 @@ struct ThreadStackPointer load_user_stack(struct MemSpace* pmemspace, char** arg pmemspace->mem_size += USER_STACK_SIZE; loaded_sp.argc = argc; - loaded_sp.stack_idx = stack_idx; loaded_sp.user_sp = user_vspace_sp; loaded_sp.user_stack_vaddr = (uintptr_t)stack_bottom; + loaded_sp.stack_idx = stack_idx; return loaded_sp; } \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/softkernel/task/task.c b/Ubiquitous/XiZi_AIoT/softkernel/task/task.c index bf8d7903d..27df0e16e 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/task/task.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/task/task.c @@ -179,6 +179,19 @@ static void _dealloc_task_cb(struct Thread* task) /* free memspace if needed to */ if (task->memspace != NULL) { + // awake deamon in this memspace + if (task->memspace->thread_to_notify != NULL) { + if (task->memspace->thread_to_notify != task) { + if (task->memspace->thread_to_notify->state == BLOCKED) { + xizi_task_manager.task_unblock(task->memspace->thread_to_notify); + } else { + task->memspace->thread_to_notify->advance_unblock = true; + } + } else if (task->memspace->thread_to_notify == task) { + task->memspace->thread_to_notify = NULL; + } + } + doubleListDel(&task->memspace_list_node); /* free memspace if thread is the last one using it */ if (IS_DOUBLE_LIST_EMPTY(&task->memspace->thread_list_guard)) { @@ -290,13 +303,8 @@ static void _scheduler(struct SchedulerRightGroup right_group) /* if there's not a runnable task, wait for one */ if (next_task == NULL) { xizi_leave_kernel(); - // there is no task to run, into low power mode - cpu_into_low_power(); - /* leave kernel for other cores, so they may create a runnable task */ xizi_enter_kernel(); - // activate cpu - cpu_leave_low_power(); continue; } @@ -342,7 +350,7 @@ static void _task_unblock(struct Thread* task) assert(task->state == BLOCKED); task_node_leave_list(task); task->state = READY; - task_node_add_to_ready_list_head(task); + task_node_add_to_ready_list_back(task); } /// @brief @warning not tested function @@ -381,8 +389,9 @@ struct XiziTaskManager xizi_task_manager = { .set_cur_task_priority = _set_cur_task_priority }; -bool module_task_manager_init(void) +bool module_task_manager_init(TraceTag* softkernel_tag) { + CreateResourceTag(&xizi_task_manager.tag, softkernel_tag, "KTaskManager", TRACER_OWNER, &xizi_task_manager); xizi_task_manager.init(); return true; } diff --git a/Ubiquitous/XiZi_AIoT/softkernel/trap/clock_irq_handler.c b/Ubiquitous/XiZi_AIoT/softkernel/trap/clock_irq_handler.c index 7ab8808b8..eba875e07 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/trap/clock_irq_handler.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/trap/clock_irq_handler.c @@ -1,82 +1,82 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ -/** - * @file clock_irq_handler.c - * @brief clock interrupt handler - * @version 3.0 - * @author AIIT XUOS Lab - * @date 2023.08.25 - */ - -/************************************************* -File name: clock_irq_handler.c -Description: clock interrupt handler -Others: -History: -1. Date: 2023-08-28 -Author: AIIT XUOS Lab -Modification: -1. first version -*************************************************/ -#include "clock_common_op.h" - -#include "actracer.h" -#include "assert.h" -#include "multicores.h" -#include "task.h" - -static struct TraceTag clock_driver_tag; -static struct XiziClockDriver* p_clock_driver = NULL; - -bool clock_intr_handler_init(struct TraceTag* p_clock_driver_tag) -{ - clock_driver_tag = *p_clock_driver_tag; - p_clock_driver = AchieveResource(p_clock_driver_tag); - return p_clock_driver != NULL; -} - -void hw_current_tick(uintptr_t* tick) -{ - if (p_clock_driver == NULL) { - *tick = 0; - return; - } - *tick = p_clock_driver->get_tick(); -} - -void hw_current_second(uintptr_t* second) -{ - if (p_clock_driver == NULL) { - *second = 0; - return; - } - *second = p_clock_driver->get_second(); -} - -uint64_t global_tick = 0; -int xizi_clock_handler(int irq, void* tf, void* arg) -{ - /* handle clock interrupt using driver */ - if (p_clock_driver->is_timer_expired()) { - p_clock_driver->clear_clock_intr(); - global_tick++; - struct Thread* current_task = cur_cpu()->task; - if (current_task) { - current_task->remain_tick--; - current_task->maxium_tick--; - if (current_task->remain_tick == 0) { - xizi_task_manager.task_yield_noschedule(current_task, false); - } - } - } - return 0; +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file clock_irq_handler.c + * @brief clock interrupt handler + * @version 3.0 + * @author AIIT XUOS Lab + * @date 2023.08.25 + */ + +/************************************************* +File name: clock_irq_handler.c +Description: clock interrupt handler +Others: +History: +1. Date: 2023-08-28 +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#include "clock_common_op.h" + +#include "actracer.h" +#include "assert.h" +#include "multicores.h" +#include "task.h" + +static struct TraceTag clock_driver_tag; +static struct XiziClockDriver* p_clock_driver = NULL; + +bool clock_intr_handler_init(struct TraceTag* p_clock_driver_tag) +{ + clock_driver_tag = *p_clock_driver_tag; + p_clock_driver = AchieveResource(p_clock_driver_tag); + return p_clock_driver != NULL; +} + +void hw_current_tick(uintptr_t* tick) +{ + if (p_clock_driver == NULL) { + *tick = 0; + return; + } + *tick = p_clock_driver->get_tick(); +} + +void hw_current_second(uintptr_t* second) +{ + if (p_clock_driver == NULL) { + *second = 0; + return; + } + *second = p_clock_driver->get_second(); +} + +uint64_t global_tick = 0; +int xizi_clock_handler(int irq, void* tf, void* arg) +{ + /* handle clock interrupt using driver */ + if (p_clock_driver->is_timer_expired()) { + p_clock_driver->clear_clock_intr(); + global_tick++; + struct Thread* current_task = cur_cpu()->task; + if (current_task) { + current_task->remain_tick--; + current_task->maxium_tick--; + if (current_task->remain_tick == 0) { + xizi_task_manager.task_yield_noschedule(current_task, false); + } + } + } + return 0; } \ No newline at end of file From d3fb123c29c419f15c7ddf226c70276e62a7fc1e Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Thu, 15 Aug 2024 19:55:16 +0800 Subject: [PATCH 130/198] usb code is adapted to rk3568. --- Ubiquitous/XiZi_AIoT/services/drivers/Makefile | 2 +- Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/Makefile index 1c8d601c7..00581353f 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/drivers/Makefile @@ -1,4 +1,4 @@ -SRC_DIR := $(BOARD) +SRC_DIR := $(BOARD) usb include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk index 20415ddbd..21d6d5b7b 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk @@ -15,6 +15,12 @@ user_ldflags = -N -Ttext 0 cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie board_specs = $(KERNEL_ROOT)/services/app/stub.o endif +ifeq ($(BOARD), 3568) +toolchain ?= aarch64-none-elf- +user_ldflags = -N -Ttext 0 +cflags = -Wall -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +board_specs = $(KERNEL_ROOT)/services/app/stub.o +endif cc = ${toolchain}gcc ld = ${toolchain}g++ From 27247f7d00275e29234e00c6e9722a9a01539d12 Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 15 Aug 2024 19:38:29 -0700 Subject: [PATCH 131/198] sleep function --- .../services/drivers/usb/components/osal/usb_osal.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c index e65d50ed6..0f6b7c988 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c @@ -330,4 +330,11 @@ size_t usb_osal_enter_critical_section(void){ void usb_osal_leave_critical_section(size_t flag){ +} + + +void usb_osal_msleep(uint32_t delay){ + if(delay > 0){ + + } } \ No newline at end of file From dd3104c4a159e88c6cfd628a47ba767ddb4ffd15 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 16 Aug 2024 18:05:19 +0800 Subject: [PATCH 132/198] Modify the usb main function. --- .../drivers/usb/components/core/usbh_core.c | 4 ++ .../usb/components/port/xhci/usb_hc_xhci.c | 1 + .../usb/components/port/xhci/usb_hc_xhci.h | 1 + .../drivers/usb/usb_service/usb_host.c | 55 +++++++++++++++++-- 4 files changed, 56 insertions(+), 5 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c index 7e5535504..038a26258 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c @@ -884,6 +884,10 @@ int usbh_control_transfer_xiuos(struct usbh_hubport *hport, usbh_pipe_t pipe, st int ret; urb = usb_malloc(sizeof(struct usbh_urb)); + if (NULL == urb) { + USB_LOG_ERR("No memory to alloc for usbh_urb\r\n"); + return -ENOMEM; + } memset(urb, 0, sizeof(struct usbh_urb)); usbh_control_urb_fill_xiuos(urb, hport, pipe, setup, buffer, setup->wLength, CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT, NULL, NULL); diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index 8ccf71ace..c0d7df4da 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -869,6 +869,7 @@ int xhci_usbh_pipe_alloc(usbh_pipe_t *pipe, const struct usbh_endpoint_cfg *ep_c struct usb_mem_page ring_page; if (NULL == ppipe) { + USB_LOG_ERR("XHCI %s could not allocate xhci endpoint\n", xhci->name ); return -ENOMEM; } diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h index eaef45fea..15a0a2ec1 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h @@ -54,6 +54,7 @@ extern "C" { * USB3_ADDR_OFFSET_UPPER_BOUND can be found in Part 2, * Table 16-1 USB3 Address Mapping. */ +#define USB3_NUM 2 #define USB3_0_ID 0 #define USB3_1_ID 1 #define USB3_0_BASE_ADDR 0xFCC00000 diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c index 336b0a142..709b2097c 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c @@ -1,9 +1,13 @@ #include "usb_host.h" #include "usb_mem.h" +#include "usb_hc_xhci.h" #include "usyscall.h" #include "libipc.h" #include "rndis_service.h" #include "lwip_rndis_service.h" +#include + +static struct usbh_bus usb[USB3_NUM]; /* IPC rndis server */ int IPC_DO_SERVE_FUNC(Ipc_usbh_rndis_eth_tx)(void *dataptr, size_t *tot_len){ @@ -19,7 +23,7 @@ IPC_SERVER_INTERFACE(Ipc_usbh_rndis_eth_control, 3); IPC_SERVER_REGISTER_INTERFACES(IpcRndisServer, 2, Ipc_usbh_rndis_eth_tx, Ipc_usbh_rndis_eth_control); -int ipc_rndis_server_init(void) +int ipc_rndis_server_init(void *para) { if (register_server("RndisServer") < 0) { printf("register server name: %s failed.\n", "RndisServer"); @@ -38,8 +42,12 @@ int ipc_lwip_client_init(void) struct Session *session; session = usb_malloc(sizeof(struct Session)); + if (NULL == session) { + printf("No memory to alloc for LWIPServer session\r\n"); + return -ENOMEM; + } if(connect_session(session, "LWIPServer", 4096) < 0) { - printf("connect session failed\n"); + printf("connect LWIPServer session failed\n"); return -1; } g_session_lwip = session; @@ -53,10 +61,47 @@ int lwip_rndis_data_recv(void *dataptr, size_t len) return ipc_lwip_rndis_data_recv(session, dataptr, len); } -/* usb main*/ -int main(){ +void ipc_rndis_init(void){ + int tid; + ipc_lwip_client_init(); - ipc_rndis_server_init(); + tid = thread(ipc_rndis_server_init, "ipc_rndis_server", NULL); + if(tid < 0){ + printf("create thread ipc_rndis_server failed.\r\n"); + } +} + +static void usb_init(int id) +{ + if (0 == usbh_initialize(id, &usb[id])){ + printf("Init cherryusb host successfully.\r\n"); + } + else{ + printf("Init cherryusb host failed.\r\n"); + } +} + +/* usb main*/ +int main(int argc, char* argv[]) +{ + int id = USB3_0_ID; + + if (argc >= 2) { + id = atoi(argv[1]); + if (id >= USB3_NUM) { + printf("Invalid usb3 id(%d).\r\n", id); + return -EINVAL; + } + } + printf("usb3 id % init.\n", id); + usb_init(id); + + ipc_rndis_init(); + + while (1){ + usb_osal_msleep(1000); + } + return 0; } From 7a7318734be643eeb1d47f88e6c31c5d09549d27 Mon Sep 17 00:00:00 2001 From: xj Date: Fri, 16 Aug 2024 05:32:32 -0700 Subject: [PATCH 133/198] adding usb_assert --- .../services/drivers/usb/components/osal/usb_osal.c | 6 ++++++ .../services/drivers/usb/components/port/xhci/usb_hc_xhci.c | 4 +++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c index 0f6b7c988..ab3ae16f0 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c @@ -337,4 +337,10 @@ void usb_osal_msleep(uint32_t delay){ if(delay > 0){ } +} + + +void usb_assert(const char *filename, int linenum){ + printf("%s, %d\n", filename, linenum); + exit(-1); } \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index c0d7df4da..999c290d9 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -578,7 +578,7 @@ void USBH_IRQHandler(void *param) usbsts |= XHCI_USBSTS_EINT; writel(usbsts, xhci->op + XHCI_OP_USBSTS); - /* ack interrupt */ + /* ack interrupt */xhci_usbh_roothub_control runtime = readl(xhci->run + XHCI_RUN_IR_IMAN ( 0 )); runtime |= XHCI_RUN_IR_IMAN_IP; writel (runtime, xhci->run + XHCI_RUN_IR_IMAN ( 0 )); @@ -1123,3 +1123,5 @@ int create_xhci_intr_service(void *para){ return 0; } + + From 721763bb00f3701ce2be55a079906afdd46805ae Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Mon, 19 Aug 2024 19:17:50 +0800 Subject: [PATCH 134/198] usb class info is created when initialized. --- .../usb/components/class/hub/usbh_hub.c | 37 ++++++++++--------- .../components/class/wireless/usbh_rndis.c | 8 +++- .../components/class/wireless/usbh_rndis.h | 1 + .../drivers/usb/components/core/usbh_core.c | 20 ++++++++-- .../drivers/usb/components/core/usbh_core.h | 9 +++++ 5 files changed, 53 insertions(+), 22 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c index fef242ee0..7fb1a7ff8 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c @@ -731,8 +731,28 @@ void usbh_roothub_thread_wakeup(uint32_t usb_id, uint8_t port) usbh_hub_thread_wakeup(roothub); } +#if CONFIG_USBHOST_MAX_EXTHUBS > 0 +const struct usbh_class_driver hub_class_driver = { + .driver_name = "hub", + .connect = usbh_hub_connect, + .disconnect = usbh_hub_disconnect +}; + +CLASS_INFO_DEFINE struct usbh_class_info hub_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS, + .class = USB_DEVICE_CLASS_HUB, + .subclass = 0, + .protocol = 0, + .vid = 0x00, + .pid = 0x00, + .class_driver = &hub_class_driver +}; +#endif + int usbh_hub_initialize(struct usbh_bus *usb) { + usbh_class_info_set(USBH_CLASS_INFO_HUB, &hub_class_info); + usbh_roothub_register(usb); usb->hub_mq = usb_osal_mq_create(7); @@ -749,20 +769,3 @@ int usbh_hub_initialize(struct usbh_bus *usb) return 0; } -#if CONFIG_USBHOST_MAX_EXTHUBS > 0 -const struct usbh_class_driver hub_class_driver = { - .driver_name = "hub", - .connect = usbh_hub_connect, - .disconnect = usbh_hub_disconnect -}; - -CLASS_INFO_DEFINE const struct usbh_class_info hub_class_info = { - .match_flags = USB_CLASS_MATCH_INTF_CLASS, - .class = USB_DEVICE_CLASS_HUB, - .subclass = 0, - .protocol = 0, - .vid = 0x00, - .pid = 0x00, - .class_driver = &hub_class_driver -}; -#endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c index 96bcb47f5..2f3457ec2 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c @@ -467,7 +467,7 @@ static const struct usbh_class_driver rndis_class_driver = { .disconnect = usbh_rndis_disconnect }; -CLASS_INFO_DEFINE const struct usbh_class_info rndis_class_info = { +CLASS_INFO_DEFINE struct usbh_class_info rndis_class_info = { .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, .class = USB_DEVICE_CLASS_WIRELESS, .subclass = 0x01, @@ -476,3 +476,9 @@ CLASS_INFO_DEFINE const struct usbh_class_info rndis_class_info = { .pid = 0x00, .class_driver = &rndis_class_driver }; + +int usbh_rndis_initialize(struct usbh_bus *usb) +{ + usbh_class_info_set(USBH_CLASS_INFO_RNDIS, &rndis_class_info); + return 0; +} diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.h index 2f7e293c9..0face3263 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.h @@ -46,6 +46,7 @@ struct usbh_rndis { #ifdef __cplusplus extern "C" { #endif +int usbh_rndis_initialize(struct usbh_bus *usb); int usbh_rndis_bulk_out_transfer(struct usbh_rndis *rndis_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout); int usbh_rndis_bulk_in_transfer(struct usbh_rndis *rndis_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout); diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c index 038a26258..7e966bcb3 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c @@ -34,7 +34,9 @@ Modification: usb core uses naive_mmap to assign virtual and physical addresses #include "usbh_hub.h" #include "usb_hc_xhci.h" #include "usyscall.h" +#include "usbh_rndis.h" +CLASS_INFO_DEFINE struct usbh_class_info usbh_class_info_table[USBH_CLASS_INFO_MAX] = {0}; struct usbh_class_info *usbh_class_info_table_begin = NULL; struct usbh_class_info *usbh_class_info_table_end = NULL; @@ -826,10 +828,8 @@ int usbh_initialize(uint32_t id, struct usbh_bus *usb) usbh_class_info_table_begin = (struct usbh_class_info *)&usbh_class_info$$Base; usbh_class_info_table_end = (struct usbh_class_info *)&usbh_class_info$$Limit; #elif defined(__GNUC__) - extern uint32_t __usbh_class_info_start__; - extern uint32_t __usbh_class_info_end__; - usbh_class_info_table_begin = (struct usbh_class_info *)&__usbh_class_info_start__; - usbh_class_info_table_end = (struct usbh_class_info *)&__usbh_class_info_end__; + usbh_class_info_table_begin = (struct usbh_class_info *)&usbh_class_info_table[0]; + usbh_class_info_table_end = (struct usbh_class_info *)&usbh_class_info_table[USBH_CLASS_INFO_MAX]; #elif defined(__ICCARM__) || defined(__ICCRX__) usbh_class_info_table_begin = (struct usbh_class_info *)__section_begin("usbh_class_info"); usbh_class_info_table_end = (struct usbh_class_info *)__section_end("usbh_class_info"); @@ -856,6 +856,7 @@ int usbh_initialize(uint32_t id, struct usbh_bus *usb) usb_slist_add_tail(&usb_buses, &(usb->list)); usbh_hub_initialize(usb); + usbh_rndis_initialize(usb); return 0; } @@ -994,6 +995,17 @@ int lsusb(int argc, char **argv) return 0; } +/* Set usb class info */ +int usbh_class_info_set(enum usbh_class_info_type class_type, struct usbh_class_info *class_info) +{ + if(!(class_type >=0 && class_type < USBH_CLASS_INFO_MAX)) { + USB_LOG_ERR("invalid usb class info type %d \r\n", class_type); + return -EINVAL; + } + memcpy(&usbh_class_info_table[class_type], class_info, sizeof(struct usbh_class_info)); + return 0; +} + /* xhci hardware init */ int usb_hc_init(uint32_t id) { diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h index 919c6f737..ee0e4ff5e 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.h @@ -57,6 +57,13 @@ extern "C" { #define USB_HC_XHCI 5 #define USB_HC_DWC3 6 +/** Supported usb class types */ +enum usbh_class_info_type { + USBH_CLASS_INFO_HUB = 0, + USBH_CLASS_INFO_RNDIS = 1, + USBH_CLASS_INFO_MAX = 2 +}; + #define USB_CLASS_MATCH_VENDOR 0x0001 #define USB_CLASS_MATCH_PRODUCT 0x0002 #define USB_CLASS_MATCH_INTF_CLASS 0x0004 @@ -372,6 +379,8 @@ struct usbh_hubport *usbh_find_hubport(uint32_t id, uint8_t dev_addr); void *usbh_find_class_instance(const char *devname); int lsusb(int argc, char **argv); +int usbh_class_info_set(enum usbh_class_info_type class_type, struct usbh_class_info *class_info); + #ifdef __cplusplus } #endif From 398c2590c7a5140c67d31084a1f78643b8a583dd Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Mon, 19 Aug 2024 19:30:52 +0800 Subject: [PATCH 135/198] Fix compilation issues --- .../drivers/usb/components/port/xhci/xhci.c | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index bcb0815a3..4786c6c83 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -2944,3 +2944,28 @@ void xhci_event_process(struct xhci_host *xhci) { return; } + + +/* Dump Port status */ +void xhci_dump_port_status(uint32_t port, uint32_t portsc) { +} + +/* Dump input context */ +void xhci_dump_input_ctx( struct xhci_host *xhci, const struct xhci_endpoint *endpoint, const void *input) { +} + +/* Dump Endpoint */ +void xhci_dump_endpoint(const struct xhci_endpoint *ep) { +} + +/* Dump endpoint context */ +void xhci_dump_ep_ctx(const struct xhci_endpoint_context *ep) { +} + +/* Dump TRB */ +void xhci_dump_trbs(const union xhci_trb *trbs, unsigned int count) { +} + +/* Dump slot context */ +void xhci_dump_slot_ctx(const struct xhci_slot_context *const sc) { +} From 5168e889116db8fbe39ce04bc950280e7774a9fa Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Mon, 19 Aug 2024 19:45:22 +0800 Subject: [PATCH 136/198] Generate the usb_driver_service program. --- Ubiquitous/XiZi_AIoT/services/Makefile | 2 +- .../services/drivers/usb/usb_service/Makefile | 22 ++++++++++++++++++- 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/Makefile b/Ubiquitous/XiZi_AIoT/services/Makefile index b3a5f2c41..cbd4ba28a 100644 --- a/Ubiquitous/XiZi_AIoT/services/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/Makefile @@ -1,5 +1,5 @@ -SRC_DIR := fs shell lib boards drivers semaphore drivers tools net app +SRC_DIR := fs shell lib boards semaphore drivers tools net app include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/Makefile index 3e4ac9f01..dac4fd694 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/Makefile @@ -3,8 +3,28 @@ include $(KERNEL_ROOT)/services/drivers/usb/components/usb.mk objs = usb_host.o objs += $(KERNEL_ROOT)/services/net/libnet/lwip_rndis_service.o -all: ${objs} +libserial = $(KERNEL_ROOT)/services/app/libserial.o +printf = $(KERNEL_ROOT)/services/app/printf.o +libmem = $(KERNEL_ROOT)/services/app/libmem.o +usyscall = $(KERNEL_ROOT)/services/app/usyscall.o +arch_usyscall = $(KERNEL_ROOT)/services/app/arch_usyscall.o +session = $(KERNEL_ROOT)/services/app/session.o +libipc = $(KERNEL_ROOT)/services/app/libipc.o +libsem = $(KERNEL_ROOT)/services/app/libsemaphore.o + +usb_components = $(KERNEL_ROOT)/services/drivers/usb/components/rndis_host.o \ + $(KERNEL_ROOT)/services/drivers/usb/components/usb_hc_xhci.o \ + $(KERNEL_ROOT)/services/drivers/usb/components/usb_mem.o \ + $(KERNEL_ROOT)/services/drivers/usb/components/usb_osal.o \ + $(KERNEL_ROOT)/services/drivers/usb/components/usbh_core.o \ + $(KERNEL_ROOT)/services/drivers/usb/components/usbh_hub.o \ + $(KERNEL_ROOT)/services/drivers/usb/components/usbh_rndis.o \ + $(KERNEL_ROOT)/services/drivers/usb/components/xhci.o + +usb_driver_service: ${objs} @echo "generate $^" + @${ld} ${user_ldflags} -e main -o $@ $^ ${usb_components} ${libserial} ${printf} ${libmem} ${usyscall} ${arch_usyscall} ${session} ${libipc} ${libsem} ${board_specs} + @${objdump} -S $@ > $@.asm %.o: %.c @echo "cc $^" From 72ceb7fd2689f853293c36386d33db716c41c6fd Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 20 Aug 2024 09:35:11 +0800 Subject: [PATCH 137/198] Compile usb_driver_service into fs.img. --- Ubiquitous/XiZi_AIoT/services/app/Makefile | 2 +- Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/Makefile | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/app/Makefile b/Ubiquitous/XiZi_AIoT/services/app/Makefile index 2b5808fe6..98ee6c136 100644 --- a/Ubiquitous/XiZi_AIoT/services/app/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/app/Makefile @@ -45,7 +45,7 @@ INC_DIR = -I$(KERNEL_ROOT)/services/shell/letter-shell \ ifeq ($(BOARD), imx6q-sabrelite) all: test_fault simple_client simple_server shell fs_server semaphore_server test_semaphore test_ipc_null test_thread test_irq_hdlr test_irq_block test_irq_send eth_driver epit_server test_net lwip readme.txt | bin else -all: test_fault simple_client simple_server shell fs_server semaphore_server test_ipc_null test_thread test_semaphore test_net lwip readme.txt eth_hal | bin +all: test_fault simple_client simple_server shell fs_server semaphore_server test_ipc_null test_thread test_semaphore test_net lwip readme.txt eth_hal usb_driver_service | bin endif ../tools/mkfs/mkfs ./fs.img $^ @mv $(filter-out readme.txt, $^) bin diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/Makefile index dac4fd694..ca7596a97 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/Makefile @@ -25,6 +25,8 @@ usb_driver_service: ${objs} @echo "generate $^" @${ld} ${user_ldflags} -e main -o $@ $^ ${usb_components} ${libserial} ${printf} ${libmem} ${usyscall} ${arch_usyscall} ${session} ${libipc} ${libsem} ${board_specs} @${objdump} -S $@ > $@.asm + @mv $@ $(KERNEL_ROOT)/services/app + @mv $@.asm $(KERNEL_ROOT)/services/app %.o: %.c @echo "cc $^" From 3f80e39695b0681efbea09cd222705514e412fe8 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 20 Aug 2024 10:11:27 +0800 Subject: [PATCH 138/198] rndis waits for LWIPServer in thread. --- .../drivers/usb/usb_service/usb_host.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c index 709b2097c..623c6b53e 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c @@ -37,7 +37,7 @@ int ipc_rndis_server_init(void *para) /* IPC lwip client */ struct Session *g_session_lwip = NULL; -int ipc_lwip_client_init(void) +int ipc_lwip_client_init(void *para) { struct Session *session; @@ -46,10 +46,11 @@ int ipc_lwip_client_init(void) printf("No memory to alloc for LWIPServer session\r\n"); return -ENOMEM; } - if(connect_session(session, "LWIPServer", 4096) < 0) { - printf("connect LWIPServer session failed\n"); - return -1; + + while (connect_session(session, "LWIPServer", 4096) < 0) { + usb_osal_msleep(1000); } + printf("connect LWIPServer session success.\r\n"); g_session_lwip = session; return 0; @@ -63,12 +64,17 @@ int lwip_rndis_data_recv(void *dataptr, size_t len) void ipc_rndis_init(void){ int tid; + int tid_client; - ipc_lwip_client_init(); tid = thread(ipc_rndis_server_init, "ipc_rndis_server", NULL); if(tid < 0){ printf("create thread ipc_rndis_server failed.\r\n"); } + + tid_client = thread(ipc_lwip_client_init, "ipc_rndis_lwip_client", NULL); + if(tid < 0){ + printf("create thread ipc_rndis_server failed.\r\n"); + } } static void usb_init(int id) @@ -93,7 +99,7 @@ int main(int argc, char* argv[]) return -EINVAL; } } - printf("usb3 id % init.\n", id); + printf("main usb3 id(%d) init.\r\n", id); usb_init(id); ipc_rndis_init(); From aa7c708a4b292c2f7ff0b53c644cfbcdf0cdaa9d Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Wed, 21 Aug 2024 09:16:54 +0800 Subject: [PATCH 139/198] Set usb hc type USB_HC_XHCI in usb init --- .../services/drivers/usb/components/core/usbh_core.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c index 7e966bcb3..f03bb21ad 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c @@ -845,6 +845,10 @@ int usbh_initialize(uint32_t id, struct usbh_bus *usb) usb->hub_class_head.next = NULL; usb->id = id; + if (USB3_0_ID == id || USB3_1_ID == id) { + usb->usb_hc_type = USB_HC_XHCI; + } + /* ep0_request_buffer allocate virtual address and physical address*/ rc = naive_mmap(&vaddr, &paddr, CONFIG_USBHOST_REQUEST_BUFFER_LEN, false); if(rc != 0){ From 883cd6e4d5e3e7608479feb4a39c75af3dc639f2 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Wed, 21 Aug 2024 09:23:26 +0800 Subject: [PATCH 140/198] Modify usb log level to Debug --- Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_config.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_config.h index 355a5813e..31a4ae7f5 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_config.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_config.h @@ -45,7 +45,7 @@ extern "C" // #define usb_align(align, size) usb_hc_malloc_align(align, size) #ifndef CONFIG_USB_DBG_LEVEL - #define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR + #define CONFIG_USB_DBG_LEVEL USB_DBG_LOG #endif #ifndef CONFIG_USB_PRINTF From bdfdc65bf633dae91414a715217aea2fb878f3a1 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Wed, 21 Aug 2024 10:45:34 +0800 Subject: [PATCH 141/198] usb memory virtual address reference XiZi, and modify naive_mmap usage method. --- .../usb/components/class/hub/usbh_hub.c | 5 +- .../components/class/wireless/rndis_host.c | 10 +-- .../components/class/wireless/usbh_rndis.c | 10 +-- .../drivers/usb/components/core/usbh_core.c | 5 +- .../drivers/usb/components/mem/usb_mem.c | 11 +++- .../drivers/usb/components/mem/usb_mem.h | 4 ++ .../drivers/usb/components/port/xhci/xhci.c | 62 +++++++++++-------- 7 files changed, 68 insertions(+), 39 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c index 7fb1a7ff8..78768e91d 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c @@ -335,12 +335,13 @@ static int usbh_hub_connect(struct usbh_hubport *hport, uint8_t intf) hub->index = index; /* g_hub_buf allocate virtual address and physical address*/ - rc = naive_mmap(&vaddr, &paddr, 32, false); + vaddr = USB_MEM_VIRADDR_ALLOC; + hub->g_hub_buf = (uint8_t *)vaddr; + rc = naive_mmap(&vaddr, &paddr, 32, true); if(rc != 0){ USB_LOG_ERR("g_hub_buf allocate error, ret: %d\n", rc); return -ENOMEM; } - hub->g_hub_buf = (uint8_t *)vaddr; hub->g_hub_buf_phy = (uint8_t *)paddr; hport->config.intf[intf].priv = hub; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c index addf77d12..49dec828d 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c @@ -148,20 +148,22 @@ void usbh_rndis_run(struct usbh_rndis *rndis_class) s_rndis_class_ptr = rndis_class; - ret = naive_mmap(&vaddr, &paddr, RNDIS_ETH_BUFFER_LEN, false); + vaddr = USB_MEM_VIRADDR_ALLOC; + tx_buffer = (uint8_t *)vaddr; + ret = naive_mmap(&vaddr, &paddr, RNDIS_ETH_BUFFER_LEN, true); if(ret != 0){ USB_LOG_ERR("tx_buf_ptr allocate error, ret: %d\n", ret); return; } - tx_buffer = (uint8_t *)vaddr; tx_buffer_phy = (uint8_t *)paddr; - ret = naive_mmap(&vaddr, &paddr, RNDIS_RXETH_BUFFER_LEN, false); + vaddr = USB_MEM_VIRADDR_ALLOC; + rx_buffer = (uint8_t *)vaddr; + ret = naive_mmap(&vaddr, &paddr, RNDIS_RXETH_BUFFER_LEN, true); if(ret != 0){ USB_LOG_ERR("rx_buf_ptr allocate error, ret: %d\n", ret); return; } - rx_buffer = (uint8_t *)vaddr; rx_buffer_phy = (uint8_t *)paddr; mutex_sem_handle = usb_osal_sem_create(0); diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c index 2f3457ec2..73dbee68d 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c @@ -291,20 +291,22 @@ static int usbh_rndis_connect(struct usbh_hubport *hport, uint8_t intf) rndis_class->data_intf = intf + 1; /* allocate virtual address and physical address*/ - ret = naive_mmap(&vaddr, &paddr, 4096, false); + vaddr = USB_MEM_VIRADDR_ALLOC; + g_rndis_buf = (uint8_t *)vaddr; + ret = naive_mmap(&vaddr, &paddr, 4096, true); if(ret != 0){ USB_LOG_ERR("g_rndis_buf allocate error, ret: %d\n", ret); return -ENOMEM; } - g_rndis_buf = (uint8_t *)vaddr; g_rndis_buf_phy = (uint8_t *)paddr; - ret = naive_mmap(&vaddr, &paddr, 4096, false); + vaddr = USB_MEM_VIRADDR_ALLOC; + g_rndis_keepalive_buf = (uint8_t *)vaddr; + ret = naive_mmap(&vaddr, &paddr, 4096, true); if(ret != 0){ USB_LOG_ERR("g_rndis_keepalive_buf allocate error, ret: %d\n", ret); return -ENOMEM; } - g_rndis_keepalive_buf = (uint8_t *)vaddr; g_rndis_keepalive_buf_phy = (uint8_t *)paddr; hport->config.intf[intf].priv = rndis_class; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c index f03bb21ad..051fc04dd 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c @@ -850,12 +850,13 @@ int usbh_initialize(uint32_t id, struct usbh_bus *usb) } /* ep0_request_buffer allocate virtual address and physical address*/ - rc = naive_mmap(&vaddr, &paddr, CONFIG_USBHOST_REQUEST_BUFFER_LEN, false); + vaddr = USB_MEM_VIRADDR_ALLOC; + usb->ep0_request_buffer = (uint8_t *)vaddr; + rc = naive_mmap(&vaddr, &paddr, CONFIG_USBHOST_REQUEST_BUFFER_LEN, true); if(rc != 0){ USB_LOG_ERR("ep0_request_buffer allocate error, ret: %d\n", rc); return -ENOMEM; } - usb->ep0_request_buffer = (uint8_t *)vaddr; usb->ep0_request_buffer_phy = (uint8_t *)paddr; usb_slist_add_tail(&usb_buses, &(usb->list)); diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c index 8ff4ac44d..a3e79d2c7 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.c @@ -10,7 +10,14 @@ History: 1. Date: 2024-06-12 Author: AIIT XUOS Lab Modification: re-develop usb_hc_malloc, usb_hc_malloc_align and usb_hc_free functions +2. Date: 2024-08-21 +Author: AIIT XUOS Lab +Modification: The usb memory virtual address base address uses 0x1000000000, refer to XiZi virtual memory distribution. *************************************************/ + +/* The usb memory virtual address base address uses 0x1000000000, refer to XiZi virtual memory distribution.*/ +uintptr_t usb_mem_base_viraddr = 0x1000000000; + struct usb_mem_pool usb_mem_data_pool; @@ -63,12 +70,14 @@ int usb_mem_data_pool_init(){ count = 0; while(count < MEM_POOL_SIZE){ + vir_addr = USB_MEM_VIRADDR_ALLOC; + usb_mem_data_pool.pages[count].vir_addr = vir_addr; + rc = naive_mmap(&vir_addr, &phy_addr, 4096, true); if(rc != 0) goto mmap_error; - usb_mem_data_pool.pages[count].vir_addr = vir_addr; usb_mem_data_pool.pages[count].phy_addr = phy_addr; count++; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h index 238b8f1ec..53aeccc6f 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/mem/usb_mem.h @@ -31,6 +31,10 @@ Modification: Use usb_malloc, usb_free and usb_align functions #define USB_MEM_ALIGNX __attribute__((aligned(CONFIG_USB_ALIGN_SIZE))) +/*The usb virtual address offset 0x1000 corresponds to the function naive_mmap. */ +extern uintptr_t usb_mem_base_viraddr; +#define USB_MEM_VIRADDR_ALLOC (usb_mem_base_viraddr += 0x1000) + #define MEM_POOL_SIZE 128 void *usb_hc_malloc(size_t size); diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 4786c6c83..9e91f0075 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -692,8 +692,9 @@ static int xhci_dcbaa_alloc ( struct xhci_host *xhci ) { xhci->dcbaa.context = NULL; - - rc = naive_mmap(&dcbaap_addr, &dcbaap_phy, len, false); + dcbaap_addr = USB_MEM_VIRADDR_ALLOC; + xhci->dcbaa_addr = dcbaap_addr; + rc = naive_mmap(&dcbaap_addr, &dcbaap_phy, len, true); if(rc != 0){ USB_LOG_ERR("XHCI %s could not allocate DCBAA\n", xhci->name ); @@ -701,9 +702,8 @@ static int xhci_dcbaa_alloc ( struct xhci_host *xhci ) { goto err_alloc; } - xhci->dcbaa_addr = dcbaap_addr; xhci->dcbaa_phy = dcbaap_phy; - xhci->dcbaa.context = (void *)dcbaap_addr; + xhci->dcbaa.context = (void *)xhci->dcbaa_addr; #if 0 if ( ! xhci->dcbaa.context ) { @@ -757,10 +757,12 @@ static int xhci_scratchpad_alloc ( struct xhci_host *xhci ) { return 0; } - /* Allocate buffer to store */ - array_len = scratch->count * sizeof ( scratch->array[0] ); + /* Allocate buffer to store */ + array_len = scratch->count * sizeof ( scratch->array[0] ); + vir_addr = USB_MEM_VIRADDR_ALLOC; + scratch->array_addr = (void *)vir_addr; - rc = naive_mmap(&vir_addr, &phy_addr, array_len, false); + rc = naive_mmap(&vir_addr, &phy_addr, array_len, true); if(rc != 0){ USB_LOG_ERR("XHCI %s could not allocate scratch buffer\n", xhci->name ); @@ -768,8 +770,7 @@ static int xhci_scratchpad_alloc ( struct xhci_host *xhci ) { goto err_alloc; } - scratch->array_addr = (void *)vir_addr; - memset(scratch->array_addr, 0, array_len); + memset(scratch->array_addr, 0, array_len); scratch->array_phy = phy_addr; @@ -789,14 +790,16 @@ static int xhci_scratchpad_alloc ( struct xhci_host *xhci ) { * Allocate physical page one by one, and store its physical address in vir_addr. */ for(i = 0; i < scratch->count; i++){ - rc = naive_mmap(&vir_page_addr, &phy_page_addr, xhci->pagesize, false); + vir_page_addr = USB_MEM_VIRADDR_ALLOC; + scratch->sp_buffers[i] = (void *)vir_page_addr; + + rc = naive_mmap(&vir_page_addr, &phy_page_addr, xhci->pagesize, true); if(rc != 0){ USB_LOG_ERR("XHCI %s could not allocate scratchpad buffers\n", xhci->name ); goto err_alloc_array_vir; } - scratch->sp_buffers[i] = (void *)vir_page_addr; scratch->array_addr[i] = phy_page_addr; } @@ -884,7 +887,10 @@ static int xhci_command_alloc ( struct xhci_host *xhci ) { #endif len = sizeof(*xhci->cmds); - rc = naive_mmap(&cmds_addr, &cmds_phy, len, false); + cmds_addr = USB_MEM_VIRADDR_ALLOC; + xhci->cmds_addr = cmds_addr; + + rc = naive_mmap(&cmds_addr, &cmds_phy, len, true); if(rc != 0){ USB_LOG_ERR("XHCI %s could not allocate CMD RING\n", xhci->name ); @@ -892,10 +898,9 @@ static int xhci_command_alloc ( struct xhci_host *xhci ) { goto err_ring_alloc; } - xhci->cmds_addr = cmds_addr; xhci->cmds_phy = cmds_phy; - xhci->cmds = (struct xhci_ring *)cmds_addr; + xhci->cmds = (struct xhci_ring *)xhci->cmds_addr; memset(xhci->cmds, 0U, sizeof(*xhci->cmds)); xhci->cmds->lock = usb_osal_mutex_create(); @@ -950,7 +955,10 @@ static int xhci_event_alloc ( struct xhci_host *xhci ) { /* Allocate event ring */ len = sizeof(*xhci->evts); - rc = naive_mmap(&evts_addr, &evts_phy, len, false); + evts_addr = USB_MEM_VIRADDR_ALLOC; + xhci->evts_addr = evts_addr; + + rc = naive_mmap(&evts_addr, &evts_phy, len, true); if(rc != 0){ USB_LOG_ERR("XHCI %s could not allocate Event RING\n", xhci->name ); @@ -966,16 +974,17 @@ static int xhci_event_alloc ( struct xhci_host *xhci ) { goto err_alloc_trb; } #endif - xhci->evts_addr = evts_addr; xhci->evts_phy = evts_phy; - xhci->evts = (struct xhci_ring *)evts_addr; + xhci->evts = (struct xhci_ring *)xhci->evts_addr; memset(xhci->evts, 0U, sizeof(*xhci->evts)); /* Allocate event ring segment table */ len = sizeof(*xhci->eseg); - rc = naive_mmap(&eseg_addr, &eseg_phy, len, false); + eseg_addr = USB_MEM_VIRADDR_ALLOC; + xhci->eseg_addr = eseg_addr; + rc = naive_mmap(&eseg_addr, &eseg_phy, len, true); if(rc != 0){ USB_LOG_ERR("XHCI %s could not allocate Event Segment\n", xhci->name ); rc = -ENOMEM; @@ -990,10 +999,9 @@ static int xhci_event_alloc ( struct xhci_host *xhci ) { } #endif - xhci->eseg_addr = eseg_addr; xhci->eseg_phy = eseg_phy; - xhci->eseg = (struct xhci_er_seg *)eseg_addr; + xhci->eseg = (struct xhci_er_seg *)xhci->eseg_addr; memset(xhci->eseg, 0U, sizeof(*xhci->eseg)); xhci->eseg->base = CPU_TO_LE64 ( ( (uintptr_t)xhci->evts ) ); @@ -1809,14 +1817,15 @@ static int xhci_context ( struct xhci_host *xhci, struct xhci_slot *slot, goto err_alloc; } #endif - rc = naive_mmap(&input_vir, &input_phy, len, false); + input_vir = USB_MEM_VIRADDR_ALLOC; + input = (void *)input_vir; + memset ( input, 0, len ); + rc = naive_mmap(&input_vir, &input_phy, len, true); if(rc != 0){ USB_LOG_ERR("XHCI %s could not allocate xhci context\n", xhci->name ); rc = -ENOMEM; goto err_alloc; } - input = (void *)input_vir; - memset ( input, 0, len ); /* Populate input context */ populate ( xhci, slot, ep, input ); @@ -2073,15 +2082,16 @@ int xhci_device_open ( struct xhci_host *xhci, struct xhci_endpoint *ep, int *sl goto err_alloc_context; } #endif - rc = naive_mmap(&context_vir, &context_phy, len, false); + context_vir = USB_MEM_VIRADDR_ALLOC; + slot->context_vir = context_vir; + rc = naive_mmap(&context_vir, &context_phy, len, true); if(rc != 0){ USB_LOG_ERR("XHCI %s could not allocate xhci device context\n", xhci->name ); rc = -ENOMEM; goto err_alloc; } - slot->context_vir = context_vir; slot->context_phy = context_phy; - slot->context = (struct xhci_slot_context *)context_vir; + slot->context = (struct xhci_slot_context *)slot->context_vir; memset ( slot->context, 0, len ); /* Set device context base address */ From 2f03186b0b738bcf182df0514ea4fc33f8ec65ec Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Wed, 21 Aug 2024 11:24:06 +0800 Subject: [PATCH 142/198] Fix a register issue. --- .../drivers/usb/components/port/xhci/xhci.c | 16 +++++++++++----- .../services/drivers/usb/usb_service/usb_host.c | 2 +- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 9e91f0075..dec0faded 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -401,7 +401,8 @@ static void xhci_legacy_claim ( struct xhci_host *xhci ) { */ USB_LOG_DBG("XHCI %s could not claim ownership from BIOS: forcibly " "disabling SMIs\n", xhci->name ); - writel ( 0, xhci->cap + xhci->legacy + XHCI_USBLEGSUP_CTLSTS ); +// writel ( 0, xhci->cap + xhci->legacy + XHCI_USBLEGSUP_CTLSTS ); + writel ( 0, xhci->cap_addr + xhci->legacy + XHCI_USBLEGSUP_CTLSTS ); } /** Prevent the release of ownership back to BIOS */ @@ -601,10 +602,13 @@ static unsigned int xhci_port_protocol ( struct xhci_host *xhci, /* Describe port protocol */ #if XHCI_DUMP { - name.raw = CPU_TO_LE32 ( readl ( xhci->cap + supported + +// name.raw = CPU_TO_LE32 ( readl ( xhci->cap + supported + +// XHCI_SUPPORTED_NAME ) ); + name.raw = CPU_TO_LE32 ( readl ( xhci->cap_addr + supported + XHCI_SUPPORTED_NAME ) ); name.text[4] = '\0'; - slot = readl ( xhci->cap + supported + XHCI_SUPPORTED_SLOT ); +// slot = readl ( xhci->cap + supported + XHCI_SUPPORTED_SLOT ); + slot = readl ( xhci->cap_addr + supported + XHCI_SUPPORTED_SLOT ); type = XHCI_SUPPORTED_SLOT_TYPE ( slot ); USB_LOG_DBG("XHCI %s-%d %sv%04x type %d \r\n", xhci->name, port, name.text, protocol, type ); @@ -1118,7 +1122,8 @@ static void xhci_event_free ( struct xhci_host *xhci ) { static void xhci_command_free ( struct xhci_host *xhci ) { /* Sanity check */ - USB_ASSERT ( ( readl ( xhci->op + XHCI_OP_CRCR ) & XHCI_CRCR_CRR ) == 0 ); +// USB_ASSERT ( ( readl ( xhci->op + XHCI_OP_CRCR ) & XHCI_CRCR_CRR ) == 0 ); + USB_ASSERT ( ( readl ( xhci->op_addr + XHCI_OP_CRCR ) & XHCI_CRCR_CRR ) == 0 ); /* Clear command ring control register */ // xhci_writeq ( xhci, 0, xhci->op + XHCI_OP_CRCR ); @@ -1647,7 +1652,8 @@ static void xhci_abort ( struct xhci_host *xhci ) { usb_osal_msleep ( XHCI_COMMAND_ABORT_DELAY_MS ); /* Sanity check */ - USB_ASSERT ( ( readl ( xhci->op + XHCI_OP_CRCR ) & XHCI_CRCR_CRR ) == 0 ); +// USB_ASSERT ( ( readl ( xhci->op + XHCI_OP_CRCR ) & XHCI_CRCR_CRR ) == 0 ); + USB_ASSERT ( ( readl ( xhci->op_addr + XHCI_OP_CRCR ) & XHCI_CRCR_CRR ) == 0 ); /* Consume (and ignore) any final command status */ int cc = xhci_event_wait(xhci, xhci->cur_cmd_pipe, xhci->cmds); diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c index 623c6b53e..14b2f8a76 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c @@ -99,7 +99,7 @@ int main(int argc, char* argv[]) return -EINVAL; } } - printf("main usb3 id(%d) init.\r\n", id); + printf("main usb3 id=%d init.\r\n", id); usb_init(id); ipc_rndis_init(); From 083277e5000dc1828def066a96b72c44c1287bb5 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Wed, 21 Aug 2024 17:22:54 +0800 Subject: [PATCH 143/198] The paddr parameter needs to be 0 in the naive_mmap function. --- .../usb/components/class/hub/usbh_hub.c | 2 ++ .../components/class/wireless/rndis_host.c | 4 ++++ .../components/class/wireless/usbh_rndis.c | 4 ++++ .../drivers/usb/components/core/usbh_core.c | 2 ++ .../drivers/usb/components/port/xhci/xhci.c | 21 ++++++++++++++++--- 5 files changed, 30 insertions(+), 3 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c index 78768e91d..b98c3b7f9 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c @@ -336,6 +336,7 @@ static int usbh_hub_connect(struct usbh_hubport *hport, uint8_t intf) /* g_hub_buf allocate virtual address and physical address*/ vaddr = USB_MEM_VIRADDR_ALLOC; + paddr = 0; hub->g_hub_buf = (uint8_t *)vaddr; rc = naive_mmap(&vaddr, &paddr, 32, true); if(rc != 0){ @@ -343,6 +344,7 @@ static int usbh_hub_connect(struct usbh_hubport *hport, uint8_t intf) return -ENOMEM; } hub->g_hub_buf_phy = (uint8_t *)paddr; + USB_LOG_DBG("usbh_hub_connect hub->g_hub_buf=%lx hub->g_hub_buf_phy=%08lx\n", hub->g_hub_buf, hub->g_hub_buf_phy); hport->config.intf[intf].priv = hub; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c index 49dec828d..657057c00 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/rndis_host.c @@ -149,6 +149,7 @@ void usbh_rndis_run(struct usbh_rndis *rndis_class) s_rndis_class_ptr = rndis_class; vaddr = USB_MEM_VIRADDR_ALLOC; + paddr = 0; tx_buffer = (uint8_t *)vaddr; ret = naive_mmap(&vaddr, &paddr, RNDIS_ETH_BUFFER_LEN, true); if(ret != 0){ @@ -156,8 +157,10 @@ void usbh_rndis_run(struct usbh_rndis *rndis_class) return; } tx_buffer_phy = (uint8_t *)paddr; + USB_LOG_DBG("usbh_rndis_run tx_buffer=%lx tx_buffer_phy=%08lx\n", tx_buffer, tx_buffer_phy); vaddr = USB_MEM_VIRADDR_ALLOC; + paddr = 0; rx_buffer = (uint8_t *)vaddr; ret = naive_mmap(&vaddr, &paddr, RNDIS_RXETH_BUFFER_LEN, true); if(ret != 0){ @@ -165,6 +168,7 @@ void usbh_rndis_run(struct usbh_rndis *rndis_class) return; } rx_buffer_phy = (uint8_t *)paddr; + USB_LOG_DBG("usbh_rndis_run rx_buffer=%lx rx_buffer_phy=%08lx\n", rx_buffer, rx_buffer_phy); mutex_sem_handle = usb_osal_sem_create(0); if (NULL == mutex_sem_handle) { diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c index 73dbee68d..40da39f94 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/wireless/usbh_rndis.c @@ -292,6 +292,7 @@ static int usbh_rndis_connect(struct usbh_hubport *hport, uint8_t intf) /* allocate virtual address and physical address*/ vaddr = USB_MEM_VIRADDR_ALLOC; + paddr = 0; g_rndis_buf = (uint8_t *)vaddr; ret = naive_mmap(&vaddr, &paddr, 4096, true); if(ret != 0){ @@ -299,8 +300,10 @@ static int usbh_rndis_connect(struct usbh_hubport *hport, uint8_t intf) return -ENOMEM; } g_rndis_buf_phy = (uint8_t *)paddr; + USB_LOG_DBG("usbh_rndis_connect g_rndis_buf=%lx g_rndis_buf_phy=%08lx\n", g_rndis_buf, g_rndis_buf_phy); vaddr = USB_MEM_VIRADDR_ALLOC; + paddr = 0; g_rndis_keepalive_buf = (uint8_t *)vaddr; ret = naive_mmap(&vaddr, &paddr, 4096, true); if(ret != 0){ @@ -308,6 +311,7 @@ static int usbh_rndis_connect(struct usbh_hubport *hport, uint8_t intf) return -ENOMEM; } g_rndis_keepalive_buf_phy = (uint8_t *)paddr; + USB_LOG_DBG("usbh_rndis_connect g_rndis_keepalive_buf=%lx g_rndis_keepalive_buf_phy=%08lx\n", g_rndis_keepalive_buf, g_rndis_keepalive_buf_phy); hport->config.intf[intf].priv = rndis_class; hport->config.intf[intf + 1].priv = NULL; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c index 051fc04dd..9e038cdff 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c @@ -851,6 +851,7 @@ int usbh_initialize(uint32_t id, struct usbh_bus *usb) /* ep0_request_buffer allocate virtual address and physical address*/ vaddr = USB_MEM_VIRADDR_ALLOC; + paddr = 0; usb->ep0_request_buffer = (uint8_t *)vaddr; rc = naive_mmap(&vaddr, &paddr, CONFIG_USBHOST_REQUEST_BUFFER_LEN, true); if(rc != 0){ @@ -858,6 +859,7 @@ int usbh_initialize(uint32_t id, struct usbh_bus *usb) return -ENOMEM; } usb->ep0_request_buffer_phy = (uint8_t *)paddr; + USB_LOG_DBG("usbh_initialize ep0_request_buffer=%lx ep0_request_buffer_phy=%08lx\n", usb->ep0_request_buffer, usb->ep0_request_buffer_phy); usb_slist_add_tail(&usb_buses, &(usb->list)); usbh_hub_initialize(usb); diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index dec0faded..00116df51 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -697,6 +697,7 @@ static int xhci_dcbaa_alloc ( struct xhci_host *xhci ) { xhci->dcbaa.context = NULL; dcbaap_addr = USB_MEM_VIRADDR_ALLOC; + dcbaap_phy = 0; xhci->dcbaa_addr = dcbaap_addr; rc = naive_mmap(&dcbaap_addr, &dcbaap_phy, len, true); @@ -708,6 +709,7 @@ static int xhci_dcbaa_alloc ( struct xhci_host *xhci ) { xhci->dcbaa_phy = dcbaap_phy; xhci->dcbaa.context = (void *)xhci->dcbaa_addr; + USB_LOG_DBG("xhci_dcbaa_alloc xhci->dcbaa_addr=%lx xhci->dcbaa_phy=%08lx\n", xhci->dcbaa_addr, xhci->dcbaa_phy); #if 0 if ( ! xhci->dcbaa.context ) { @@ -729,7 +731,7 @@ static int xhci_dcbaa_alloc ( struct xhci_host *xhci ) { USB_LOG_DBG("XHCI %s DCBAA at [%08lx,%08lx)\n", xhci->name, ( xhci->dcbaa.context ), - ( ( xhci->dcbaa.context ) + len ) ); + ( ( (uintptr_t)xhci->dcbaa.context ) + len ) ); return 0; err_writeq: @@ -764,6 +766,7 @@ static int xhci_scratchpad_alloc ( struct xhci_host *xhci ) { /* Allocate buffer to store */ array_len = scratch->count * sizeof ( scratch->array[0] ); vir_addr = USB_MEM_VIRADDR_ALLOC; + phy_addr = 0; scratch->array_addr = (void *)vir_addr; rc = naive_mmap(&vir_addr, &phy_addr, array_len, true); @@ -773,11 +776,11 @@ static int xhci_scratchpad_alloc ( struct xhci_host *xhci ) { rc = -ENOMEM; goto err_alloc; } + USB_LOG_DBG("xhci_scratchpad_alloc vir_addr=%lx phy_addr=%08lx\n", vir_addr, phy_addr); memset(scratch->array_addr, 0, array_len); scratch->array_phy = phy_addr; - /* * Allocate memory for storing all virtual address of physical pages allocated to xHCI as scratchpad buffer. */ @@ -795,6 +798,7 @@ static int xhci_scratchpad_alloc ( struct xhci_host *xhci ) { */ for(i = 0; i < scratch->count; i++){ vir_page_addr = USB_MEM_VIRADDR_ALLOC; + phy_page_addr = 0; scratch->sp_buffers[i] = (void *)vir_page_addr; rc = naive_mmap(&vir_page_addr, &phy_page_addr, xhci->pagesize, true); @@ -805,6 +809,7 @@ static int xhci_scratchpad_alloc ( struct xhci_host *xhci ) { goto err_alloc_array_vir; } scratch->array_addr[i] = phy_page_addr; + USB_LOG_DBG("xhci_scratchpad_alloc i=%d scratch->sp_buffers=%lx scratch->array_addr=%08lx\n", i, scratch->sp_buffers[i], scratch->array_addr[i]); } /* @@ -892,6 +897,7 @@ static int xhci_command_alloc ( struct xhci_host *xhci ) { len = sizeof(*xhci->cmds); cmds_addr = USB_MEM_VIRADDR_ALLOC; + cmds_phy = 0; xhci->cmds_addr = cmds_addr; rc = naive_mmap(&cmds_addr, &cmds_phy, len, true); @@ -901,6 +907,7 @@ static int xhci_command_alloc ( struct xhci_host *xhci ) { rc = -ENOMEM; goto err_ring_alloc; } + USB_LOG_DBG("xhci_command_alloc cmds_addr=%lx cmds_phy=%08lx\n", cmds_addr, cmds_phy); xhci->cmds_phy = cmds_phy; @@ -960,6 +967,7 @@ static int xhci_event_alloc ( struct xhci_host *xhci ) { /* Allocate event ring */ len = sizeof(*xhci->evts); evts_addr = USB_MEM_VIRADDR_ALLOC; + evts_phy = 0; xhci->evts_addr = evts_addr; rc = naive_mmap(&evts_addr, &evts_phy, len, true); @@ -979,6 +987,7 @@ static int xhci_event_alloc ( struct xhci_host *xhci ) { } #endif xhci->evts_phy = evts_phy; + USB_LOG_DBG("xhci_event_alloc xhci->evts_addr=%lx xhci->evts_phy=%08lx\n", xhci->evts_addr, xhci->evts_phy); xhci->evts = (struct xhci_ring *)xhci->evts_addr; memset(xhci->evts, 0U, sizeof(*xhci->evts)); @@ -987,6 +996,7 @@ static int xhci_event_alloc ( struct xhci_host *xhci ) { len = sizeof(*xhci->eseg); eseg_addr = USB_MEM_VIRADDR_ALLOC; + eseg_phy = 0; xhci->eseg_addr = eseg_addr; rc = naive_mmap(&eseg_addr, &eseg_phy, len, true); if(rc != 0){ @@ -1004,6 +1014,7 @@ static int xhci_event_alloc ( struct xhci_host *xhci ) { #endif xhci->eseg_phy = eseg_phy; + USB_LOG_DBG("xhci_event_alloc xhci->eseg_addr=%lx xhci->eseg_phy=%08lx\n", xhci->eseg_addr, xhci->eseg_phy); xhci->eseg = (struct xhci_er_seg *)xhci->eseg_addr; @@ -1824,14 +1835,16 @@ static int xhci_context ( struct xhci_host *xhci, struct xhci_slot *slot, } #endif input_vir = USB_MEM_VIRADDR_ALLOC; + input_phy = 0; input = (void *)input_vir; - memset ( input, 0, len ); rc = naive_mmap(&input_vir, &input_phy, len, true); if(rc != 0){ USB_LOG_ERR("XHCI %s could not allocate xhci context\n", xhci->name ); rc = -ENOMEM; goto err_alloc; } + USB_LOG_DBG("xhci_context input_vir=%lx input_phy=%08lx\n", input_vir, input_phy); + memset ( input, 0, len ); /* Populate input context */ populate ( xhci, slot, ep, input ); @@ -2089,6 +2102,7 @@ int xhci_device_open ( struct xhci_host *xhci, struct xhci_endpoint *ep, int *sl } #endif context_vir = USB_MEM_VIRADDR_ALLOC; + context_phy = 0; slot->context_vir = context_vir; rc = naive_mmap(&context_vir, &context_phy, len, true); if(rc != 0){ @@ -2097,6 +2111,7 @@ int xhci_device_open ( struct xhci_host *xhci, struct xhci_endpoint *ep, int *sl goto err_alloc; } slot->context_phy = context_phy; + USB_LOG_DBG("xhci_device_open slot->context_vir=%lx slot->context_phy=%08lx\n", slot->context_vir, slot->context_phy); slot->context = (struct xhci_slot_context *)slot->context_vir; memset ( slot->context, 0, len ); From 21f454fd87fdaea6cd2918eb3e6f0dd3766c3e93 Mon Sep 17 00:00:00 2001 From: xj Date: Sun, 25 Aug 2024 20:03:11 -0700 Subject: [PATCH 144/198] merge codes --- .../arch/arm/armv7-a/cortex-a9/core.h | 2 +- .../arm/armv8-a/cortex-a55/3568/memlayout.h | 4 +- .../services/drivers/3568/3568/Makefile | 4 + .../services/drivers/3568/3568/hal/Makefile | 62 + .../services/drivers/3568/3568/hal/hal_base.c | 454 + .../services/drivers/3568/3568/hal/hal_bsp.c | 420 + .../services/drivers/3568/3568/hal/hal_cru.c | 1739 ++ .../drivers/3568/3568/hal/hal_cru_rk3568.c | 1113 ++ .../drivers/3568/3568/hal/hal_debug.c | 227 + .../services/drivers/3568/3568/hal/hal_gmac.c | 2256 +++ .../drivers/3568/3568/hal/hal_gmac_3568.c | 205 + .../services/drivers/3568/3568/hal/hal_gpio.c | 606 + .../drivers/3568/3568/hal/hal_pinctrl_v2.c | 565 + .../drivers/3568/3568/hal/hal_timer.c | 307 + .../drivers/3568/3568/hal/system_rk3568.c | 91 + .../drivers/3568/3568/hal/test_gmac.c | 753 + .../drivers/3568/3568/include/hal_base.h | 105 + .../drivers/3568/3568/include/hal_bsp.h | 75 + .../drivers/3568/3568/include/hal_conf.h | 71 + .../drivers/3568/3568/include/hal_cru.h | 500 + .../drivers/3568/3568/include/hal_debug.h | 94 + .../drivers/3568/3568/include/hal_def.h | 205 + .../drivers/3568/3568/include/hal_driver.h | 282 + .../drivers/3568/3568/include/hal_gmac.h | 360 + .../drivers/3568/3568/include/hal_gpio.h | 170 + .../drivers/3568/3568/include/hal_list.h | 181 + .../drivers/3568/3568/include/hal_pinctrl.h | 1267 ++ .../drivers/3568/3568/include/hal_pm.h | 200 + .../drivers/3568/3568/include/hal_timer.h | 64 + .../drivers/3568/3568/include/rk3568.h | 16518 ++++++++++++++++ .../services/drivers/3568/3568/include/soc.h | 449 + .../drivers/3568/3568/include/system_rk3568.h | 29 + 32 files changed, 29375 insertions(+), 3 deletions(-) create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_base.c create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_bsp.c create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_cru.c create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_cru_rk3568.c create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_debug.c create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_gmac.c create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_gmac_3568.c create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_gpio.c create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_pinctrl_v2.c create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_timer.c create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/system_rk3568.c create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/test_gmac.c create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_base.h create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_bsp.h create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_conf.h create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_cru.h create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_debug.h create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_def.h create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_driver.h create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_gmac.h create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_gpio.h create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_list.h create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_pinctrl.h create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_pm.h create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_timer.h create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/rk3568.h create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/soc.h create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/system_rk3568.h diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/core.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/core.h index 01c5623bf..2115c3633 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/core.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/core.h @@ -74,7 +74,7 @@ Modification: #include "cortex_a9.h" -#define NR_CPU 4 +#define NR_CPU 1 __attribute__((always_inline, optimize("O0"))) static inline uint32_t user_mode() { diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/3568/memlayout.h b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/3568/memlayout.h index ef7e8ef24..5979533bb 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/3568/memlayout.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/3568/memlayout.h @@ -36,8 +36,8 @@ Modification: /* A55 physical memory layout */ #define PHY_MEM_BASE (0x0000000010000000ULL) #define PHY_USER_FREEMEM_BASE (0x0000000040000000ULL) -#define PHY_USER_FREEMEM_TOP (0x00000000e0000000ULL) -#define PHY_MEM_STOP (0x00000000e0000000ULL) +#define PHY_USER_FREEMEM_TOP (0x00000000E0000000ULL) +#define PHY_MEM_STOP (0x00000000E0000000ULL) /* PTE-PAGE_SIZE */ #define LEVEL4_PTE_SHIFT 12 diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/Makefile new file mode 100644 index 000000000..2c285fffa --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/Makefile @@ -0,0 +1,4 @@ + +SRC_DIR := hal + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/Makefile new file mode 100644 index 000000000..17eb018d0 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/Makefile @@ -0,0 +1,62 @@ +ifeq ($(BOARD), imx6q-sabrelite) +toolchain ?= arm-none-eabi- +user_ldflags = --specs=nosys.specs -Wl,-Map=user.map,-cref -N +cflags = -std=c11 -O2 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +endif + +ifeq ($(BOARD), zynq7000-zc702) +toolchain ?= arm-xilinx-eabi- +user_ldflags = -Wl,--start-group,-lgcc,-lc,--end-group -N +cflags = -std=c11 -O2 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +board_specs = stub.o +#cflags = -Wall -g -std=c11 +endif + +ifeq ($(BOARD), ok1028a-c) +toolchain ?= aarch64-none-elf- +user_ldflags = -N -Ttext 0 +cflags = -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -Werror -ggdb -Wno-unused -fno-omit-frame-pointer -fno-stack-protector -fno-pie +board_specs = stub.o +endif + +ifeq ($(BOARD), 3568) +toolchain ?= aarch64-none-elf- +user_ldflags = -N -Ttext 0 +cflags = -Wall -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +board_specs = $(KERNEL_ROOT)/services/app/stub.o +endif + +cc = ${toolchain}gcc +ld = ${toolchain}g++ +objdump = ${toolchain}objdump +c_useropts = -O2 +# c_useropts = -O0 + +INC_DIR = -I$(KERNEL_ROOT)/services/app \ + -I$(KERNEL_ROOT)/services/boards/$(BOARD) \ + -I$(KERNEL_ROOT)/services/lib/serial \ + -I$(KERNEL_ROOT)/services/drivers/3568/include \ + -I$(KERNEL_ROOT)/services/lib/usyscall \ + -I$(KERNEL_ROOT)/services/lib/ipc \ + -I$(KERNEL_ROOT)/services/lib/memory + + +objs = hal_gmac.o \ + hal_gmac_3568.o \ + test_gmac.o \ + hal_base.o \ + hal_bsp.o \ + hal_pinctrl_v2.o \ + hal_cru.o \ + hal_gpio.o \ + hal_timer.o \ + hal_cru_rk3568.o \ + hal_debug.o \ + system_rk3568.o \ + +all: ${objs} + @mv $^ $(KERNEL_ROOT)/services/app + +%.o: %.c + @echo "cc $^" + @${cc} ${cflags} ${c_useropts} ${INC_DIR} -o $@ -c $^ \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_base.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_base.c new file mode 100644 index 000000000..2719e598d --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_base.c @@ -0,0 +1,454 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup HAL_BASE + * @{ + */ + +/** @defgroup HAL_BASE_How_To_Use How To Use + * @{ + + HAL system support is including delay system, HAL tick system and global system clock, + + HAL system tick setting: + + - Attach HAL_IncTick() to system tick interrupt handler; + - Notify the HAL system the system's tick frequency by calling HAL_SetTickFreq() unless + it is the same as default value HAL_TICK_FREQ_1KHZ; + - If you need a more accurate delay system, specify SYS_TIMER in hal_conf.h. + + Init HAL system: + + - Initialize the HAL system by calling HAL_Init(): + + Reset when SOC system is changed: + + - Update system with new core clock and new SysTick clock source by calling HAL_SystemCoreClockUpdate(); + + APIs: + + - Get system time by calling HAL_GetTick(). + - Delay for a certain length of time, HAL_DelayMs(), HAL_DelayUs(), and HAL_CPUDelayUs(). + - Blocking for a certain period of time to continuously query HW status, use HAL_GetTick() + to do timeout, this will be more accurate. + - Get current cpu usage by calling HAL_GetCPUUsage(). + + @} */ + +/** @defgroup HAL_BASE_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ + +#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ + +/********************* Private Structure Definition **************************/ + +/********************* Private Variable Definition ***************************/ + +static __IO uint32_t uwTick; +static eHAL_tickFreq uwTickFreq = HAL_TICK_FREQ_DEFAULT; + +/********************* Private Function Definition ***************************/ +#if defined(__CORTEX_A) || defined(__CORTEX_M) +#if __CORTEX_M == 0U || !defined(__GNUC__) +static void CPUCycleLoop(uint32_t cycles) +{ + uint32_t count; + + if (cycles < 100U) { + return; + } + + count = cycles / 3; + while (count-- > 0) { + __asm volatile ("nop"); + } +} +#else +static void CPUCycleLoop(uint32_t cycles) +{ + __ASM volatile ( + "mov r0, %0\n\t" + "adds r0, r0, #2\n\t" // 1 2 Round to the nearest multiple of 4. + "lsrs r0, r0, #2\n\t" // 1 2 Divide by 4 and set flags. + "beq 2f\n\t" // 2 2 Skip if 0. + ".align 4\n\t" + "1:\n\t" + "adds r0, r0, #1\n\t" // 1 2 Increment the counter. + "subs r0, r0, #2\n\t" // 1 2 Decrement the counter by 2. + "bne 1b\n\t" // (1)2 2 2 CPU cycles (if branch is taken). + "nop\n\t" // 1 2 Loop alignment padding. + "2:" + : : "r" (cycles) + ); +} +#endif +#elif defined(__RISC_V) +static void CPUCycleLoop(uint32_t cycles) +{ + asm volatile ( + "mv a0, %0\n\t" + "addi a0, a0, 2\n\t" // 1 2 Round to the nearest multiple of 4. + "li a1, 4\n\t" + "div a0, a0, a1\n\t" // 1 2 Divide by 4 and set flags. + "li a1, 2\n\t" + "bnez a0, 1f\n\t" // 2 2 Skip if 0. + "j 2f\n\t" + ".align 6\n\t" + "1:\n\t" + "addi a0, a0, 1\n\t" // 1 2 Increment the counter. + "sub a0, a0, a1\n\t" // 1 2 Decrement the counter by 2. + "bnez a0, 1b\n\t" // (1)2 2 2 CPU cycles (if branch is taken). + "nop\n\t" // 1 2 Loop alignment padding. + "2:" + : : "r" (cycles) + ); +} +#endif + +#if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED) +__attribute__((always_inline)) static inline HAL_Status TimerDelayUs(uint32_t us) +{ + uint64_t count, from, now, pass; + + from = HAL_TIMER_GetCount(SYS_TIMER); + count = PLL_INPUT_OSC_RATE / 1000000 * us; + do { + now = HAL_TIMER_GetCount(SYS_TIMER); + pass = now > from ? now - from : from - now; + } while (pass < count); + return HAL_OK; +} +#endif + +/** @} */ +/********************* Public Function Definition ***************************/ +/** @defgroup HAL_BASE_Exported_Functions_Group4 Init and DeInit Functions + + This section provides functions allowing to init and deinit the module: + + * @{ + */ + +/** + * @brief Init HAL driver basic code. + * @return HAL_OK. + */ +HAL_Status HAL_Init(void) +{ +#ifdef __CORTEX_M +#ifdef HAL_NVIC_MODULE_ENABLED + /* Set Interrupt Group Priority */ + HAL_NVIC_Init(); + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_DEFAULT); +#endif +#endif + +#if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED) + HAL_TIMER_SysTimerInit(SYS_TIMER); +#endif + +#ifdef HAL_PINCTRL_MODULE_ENABLED + HAL_PINCTRL_Init(); +#endif + + return HAL_OK; +} + +/** + * @brief HAL system update with new core clock and systick clock source. + * @param hz: new core clock. + * @param clkSource: new systick clock source. + * @return HAL_OK. + */ +HAL_Status HAL_SystemCoreClockUpdate(uint32_t hz, eHAL_systickClkSource clkSource) +{ + uint32_t rate = hz; + HAL_Status ret = HAL_OK; + +#if defined(__CORTEX_M) && defined(HAL_SYSTICK_MODULE_ENABLED) + ret = HAL_SYSTICK_CLKSourceConfig(clkSource); + if (ret == HAL_OK && clkSource == HAL_SYSTICK_CLKSRC_EXT) { + rate = PLL_INPUT_OSC_RATE; + } + HAL_SYSTICK_Config(rate / (1000 / HAL_GetTickFreq())); + ret = HAL_OK; +#endif + + if (ret == HAL_OK) { + SystemCoreClock = rate; /* Update global SystemCoreClock */ + } + + return ret; +} + +/** + * @brief HAL deinit. + * @return HAL_Status: HAL_OK. + */ +HAL_Status HAL_DeInit(void) +{ + /* TO-DO */ + + return HAL_OK; +} + +/** @} */ + +/** @defgroup HAL_BASE_Exported_Functions_Group5 Other Functions + * @{ + */ + +/** + * @brief Count plus tickFreq when interrupt occurs. + * @return HAL_Status: HAL_OK. + */ +HAL_Status HAL_IncTick(void) +{ + uwTick += uwTickFreq; + + return HAL_OK; +} + +/** + * @brief Provides tick value in millisecond. + * @return uint32_t: tick value in millisecond. + * @attention this API allow direct use in the HAL layer. + */ +uint32_t HAL_GetTick(void) +{ +#if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED) + uint64_t tick = HAL_TIMER_GetCount(SYS_TIMER); + uint32_t base = PLL_INPUT_OSC_RATE / 1000; + + if (tick >> 62) { + tick = ~tick; + } + + return (uint32_t)HAL_DivU64(tick, base); +#else + + return uwTick; +#endif +} + +/** + * @brief Provides system timer count. + * @return uint64_t: timer count. + * @attention this API allow direct use in the HAL layer. + */ +uint64_t HAL_GetSysTimerCount(void) +{ +#if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED) + uint64_t count = HAL_TIMER_GetCount(SYS_TIMER); + if (count >> 62) { + count = ~count; + } + + return count; +#else + + return 0LLU; +#endif +} + +/** + * @brief Set new tick frequency. + * @return HAL_Status. + */ +HAL_Status HAL_SetTickFreq(eHAL_tickFreq freq) +{ + HAL_ASSERT(IS_TICKFREQ(freq)); + + uwTickFreq = freq; + + return HAL_OK; +} + +/** + * @brief Return tick frequency. + * @return uint32_t: tick period in Hz. + * @attention this API allow direct use in the HAL layer. + */ +eHAL_tickFreq HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief SysTick mdelay. + * @param ms: mdelay count. + * @return HAL_Status: HAL_OK. + * @attention this API allow direct use in the HAL layer. Blocking for a + * certain period of time to continuously query HW status, use HAL_GetTick + * to do timeout, that will be more accurate. + */ +__attribute__((weak)) HAL_Status HAL_DelayMs(uint32_t ms) +{ + for (uint32_t i = 0; i < ms; i++) { + HAL_DelayUs(1000); + } + + return HAL_OK; +} + +/** + * @brief SysTick udelay. + * @param us: udelay count. + * @return HAL_Status: HAL_OK. + * @attention this API allow direct use in the HAL layer. The longer the delay, + * the more accurate. Actual delay is greater than the parameter. + */ +HAL_Status HAL_DelayUs(uint32_t us) +{ +#if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED) + + return TimerDelayUs(us); +#else + return HAL_CPUDelayUs(us); +#endif +} + +/** + * @brief CPU loop udelay. + * @param us: udelay count. + * @return HAL_Status: HAL_OK. + * @attention this API allow direct use in the HAL layer. The longer the delay, + * the more accurate. Actual delay is greater than the parameter. + * During delay, CPU rate change result in delay imprecise, so call it in + * following case: + * 1.IRQ disable + * 2.CRU code + */ +HAL_Status HAL_CPUDelayUs(uint32_t us) +{ + volatile uint32_t cycles; + +#if (__CORTEX_M == 0) + cycles = (uint32_t)HAL_DivU64((uint64_t)SystemCoreClock, 1000000) * us; /* Add few cycles penalty */ +#else + cycles = SystemCoreClock / 1000000 * us; /* Add few cycles penalty */ +#endif + + CPUCycleLoop(cycles); + + return HAL_OK; +} + +#if defined(HAL_CPU_USAGE_ENABLED) +static uint64_t g_last_enter_idle_time = 0; /* Last time current CPU entered the idle state. */ +static uint64_t g_total_idle_time = 0; /* Total time for current CPU to enter idle state. */ +static uint64_t g_last_elapsed_time = 0; /* Last elapsed time for current CPU. */ + +/** + * @brief Get current CPU usage. + * @return 0-100 + * @attention The cpu usage function depends on HAL_CPUEnterIdle function. + */ +uint32_t HAL_GetCPUUsage(void) +{ + uint64_t elapsed_time, active_time, current_time; + uint32_t usage; + + current_time = HAL_GetSysTimerCount(); + elapsed_time = current_time - g_last_elapsed_time; + + /* Prevent the risk of dividing by 0 caused by repeated calls for a short time. */ + if (!elapsed_time) { + return 0; + } + + HAL_ASSERT(elapsed_time > g_total_idle_time); + active_time = elapsed_time - g_total_idle_time; + usage = (active_time * 100) / elapsed_time; + g_total_idle_time = 0; + g_last_elapsed_time = current_time; + + return usage; +} +#endif + +/** + * @brief CPU enter idle. + */ +void HAL_CPU_EnterIdle(void) +{ +#if defined(HAL_CPU_USAGE_ENABLED) + uint64_t idle_time; + + __disable_irq(); + g_last_enter_idle_time = HAL_GetSysTimerCount(); +#endif + + // __asm__ volatile ("wfi"); + +#if defined(HAL_CPU_USAGE_ENABLED) + idle_time = HAL_GetSysTimerCount() - g_last_enter_idle_time; + g_total_idle_time += idle_time; + __enable_irq(); +#endif +} + +/** @} */ + +/** @} */ + +/** @} */ +/********************* Public Function Definition ***************************/ +/** @defgroup HAL_BASE_EX_Exported_Functions_Group5 Other Functions + * @{ + */ + +/** + * @brief uint64_t numerator / uint32_t denominator with remainder + * @param numerator + * @param denominator + * @param pRemainder [out] pointer to unsigned 32bit remainder + * @return uint64_t result. sets *pRemainder if pRemainder is not null + */ +uint64_t HAL_DivU64Rem(uint64_t numerator, uint32_t denominator, uint32_t *pRemainder) +{ + uint64_t remainder = numerator; + uint64_t b = denominator; + uint64_t result; + uint64_t d = 1; + uint32_t high = numerator >> 32; + + result = 0; + if (high >= denominator) { + high /= denominator; + result = (uint64_t)high << 32; + remainder -= (uint64_t)(high * denominator) << 32; + } + + while ((int64_t)b > 0 && b < remainder) { + b = b + b; + d = d + d; + } + + do { + if (remainder >= b) { + remainder -= b; + result += d; + } + b >>= 1; + d >>= 1; + } while (d); + + if (pRemainder) { + *pRemainder = remainder; + } + + return result; +} diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_bsp.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_bsp.c new file mode 100644 index 000000000..1fcf721b8 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_bsp.c @@ -0,0 +1,420 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_bsp.h" + +#ifdef HAL_PL330_MODULE_ENABLED +struct HAL_PL330_DEV g_pl330Dev0 = +{ + .pReg = DMA0, + .peripReqType = BURST, + .irq[0] = DMAC0_IRQn, + .irq[1] = DMAC0_ABORT_IRQn, + .pd = 0, +}; + +struct HAL_PL330_DEV g_pl330Dev1 = +{ + .pReg = DMA1, + .peripReqType = BURST, + .irq[0] = DMAC1_IRQn, + .irq[1] = DMAC1_ABORT_IRQn, + .pd = 0, +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +const struct HAL_SPI_DEV g_spi0Dev = { + .base = SPI0_BASE, + .clkId = CLK_SPI0, + .clkGateID = CLK_SPI0_GATE, + .pclkGateID = PCLK_SPI0_GATE, + .irqNum = SPI0_IRQn, + .isSlave = false, + .txDma = { + .channel = DMA_REQ_SPI0_TX, + .direction = DMA_MEM_TO_DEV, + .addr = SPI0_BASE + 0x400, + .dmac = DMA0, + }, + .rxDma = { + .channel = DMA_REQ_SPI0_RX, + .direction = DMA_DEV_TO_MEM, + .addr = SPI0_BASE + 0x800, + .dmac = DMA0, + }, +}; + +const struct HAL_SPI_DEV g_spi1Dev = { + .base = SPI1_BASE, + .clkId = CLK_SPI1, + .clkGateID = CLK_SPI1_GATE, + .pclkGateID = PCLK_SPI1_GATE, + .irqNum = SPI1_IRQn, + .isSlave = false, + .txDma = { + .channel = DMA_REQ_SPI1_TX, + .direction = DMA_MEM_TO_DEV, + .addr = SPI1_BASE + 0x400, + .dmac = DMA0, + }, + .rxDma = { + .channel = DMA_REQ_SPI1_RX, + .direction = DMA_DEV_TO_MEM, + .addr = SPI1_BASE + 0x800, + .dmac = DMA0, + }, +}; + +const struct HAL_SPI_DEV g_spi2Dev = { + .base = SPI2_BASE, + .clkId = CLK_SPI2, + .clkGateID = CLK_SPI2_GATE, + .pclkGateID = PCLK_SPI2_GATE, + .irqNum = SPI2_IRQn, + .isSlave = false, + .txDma = { + .channel = DMA_REQ_SPI2_TX, + .direction = DMA_MEM_TO_DEV, + .addr = SPI2_BASE + 0x400, + .dmac = DMA0, + }, + .rxDma = { + .channel = DMA_REQ_SPI2_RX, + .direction = DMA_DEV_TO_MEM, + .addr = SPI2_BASE + 0x800, + .dmac = DMA0, + }, +}; + +const struct HAL_SPI_DEV g_spi3Dev = { + .base = SPI3_BASE, + .clkId = CLK_SPI3, + .clkGateID = CLK_SPI3_GATE, + .pclkGateID = PCLK_SPI3_GATE, + .irqNum = SPI3_IRQn, + .isSlave = false, + .txDma = { + .channel = DMA_REQ_SPI3_TX, + .direction = DMA_MEM_TO_DEV, + .addr = SPI3_BASE + 0x400, + .dmac = DMA0, + }, + .rxDma = { + .channel = DMA_REQ_SPI3_RX, + .direction = DMA_DEV_TO_MEM, + .addr = SPI3_BASE + 0x800, + .dmac = DMA0, + }, +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +const struct HAL_UART_DEV g_uart0Dev = +{ + .pReg = UART0, + .sclkID = CLK_UART0, + .irqNum = UART0_IRQn, + .isAutoFlow = false, +}; + +const struct HAL_UART_DEV g_uart1Dev = +{ + .pReg = UART1, + .sclkID = CLK_UART1, + .sclkGateID = SCLK_UART1_GATE, + .pclkGateID = PCLK_UART1_GATE, + .irqNum = UART1_IRQn, + .isAutoFlow = false, +}; + +const struct HAL_UART_DEV g_uart2Dev = +{ + .pReg = UART2, + .sclkID = CLK_UART2, + .sclkGateID = SCLK_UART2_GATE, + .pclkGateID = PCLK_UART2_GATE, + .irqNum = UART2_IRQn, + .isAutoFlow = false, +}; + +const struct HAL_UART_DEV g_uart3Dev = +{ + .pReg = UART3, + .sclkID = CLK_UART3, + .sclkGateID = SCLK_UART3_GATE, + .pclkGateID = PCLK_UART3_GATE, + .irqNum = UART3_IRQn, + .isAutoFlow = false, +}; + +const struct HAL_UART_DEV g_uart4Dev = +{ + .pReg = UART4, + .sclkID = CLK_UART4, + .sclkGateID = SCLK_UART4_GATE, + .pclkGateID = PCLK_UART4_GATE, + .irqNum = UART4_IRQn, + .isAutoFlow = false, +}; + +const struct HAL_UART_DEV g_uart5Dev = +{ + .pReg = UART5, + .sclkID = CLK_UART5, + .sclkGateID = SCLK_UART5_GATE, + .pclkGateID = PCLK_UART5_GATE, + .irqNum = UART5_IRQn, + .isAutoFlow = false, +}; + +const struct HAL_UART_DEV g_uart6Dev = +{ + .pReg = UART6, + .sclkID = CLK_UART6, + .sclkGateID = SCLK_UART6_GATE, + .pclkGateID = PCLK_UART6_GATE, + .irqNum = UART6_IRQn, + .isAutoFlow = false, +}; + +const struct HAL_UART_DEV g_uart7Dev = +{ + .pReg = UART7, + .sclkID = CLK_UART7, + .sclkGateID = SCLK_UART7_GATE, + .pclkGateID = PCLK_UART7_GATE, + .irqNum = UART7_IRQn, + .isAutoFlow = false, +}; + +const struct HAL_UART_DEV g_uart8Dev = +{ + .pReg = UART8, + .sclkID = CLK_UART8, + .sclkGateID = SCLK_UART8_GATE, + .pclkGateID = PCLK_UART8_GATE, + .irqNum = UART8_IRQn, + .isAutoFlow = false, +}; + +const struct HAL_UART_DEV g_uart9Dev = +{ + .pReg = UART9, + .sclkID = CLK_UART9, + .sclkGateID = SCLK_UART9_GATE, + .pclkGateID = PCLK_UART9_GATE, + .irqNum = UART9_IRQn, + .isAutoFlow = false, +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +const struct HAL_I2C_DEV g_i2c0Dev = +{ + .pReg = I2C0, + .irqNum = I2C0_IRQn, + .clkID = CLK_I2C, + .clkGateID = CLK_I2C0_GATE, + .pclkGateID = PCLK_I2C0_GATE, + .runtimeID = PM_RUNTIME_ID_I2C0, +}; + +const struct HAL_I2C_DEV g_i2c1Dev = +{ + .pReg = I2C1, + .irqNum = I2C1_IRQn, + .clkID = CLK_I2C, + .clkGateID = CLK_I2C1_GATE, + .pclkGateID = PCLK_I2C1_GATE, + .runtimeID = PM_RUNTIME_ID_I2C1, +}; + +const struct HAL_I2C_DEV g_i2c2Dev = +{ + .pReg = I2C2, + .irqNum = I2C2_IRQn, + .clkID = CLK_I2C, + .clkGateID = CLK_I2C2_GATE, + .pclkGateID = PCLK_I2C2_GATE, + .runtimeID = PM_RUNTIME_ID_I2C2, +}; + +const struct HAL_I2C_DEV g_i2c3Dev = +{ + .pReg = I2C3, + .irqNum = I2C3_IRQn, + .clkID = CLK_I2C, + .clkGateID = CLK_I2C3_GATE, + .pclkGateID = PCLK_I2C3_GATE, + .runtimeID = PM_RUNTIME_ID_I2C3, +}; + +const struct HAL_I2C_DEV g_i2c4Dev = +{ + .pReg = I2C4, + .irqNum = I2C4_IRQn, + .clkID = CLK_I2C, + .clkGateID = CLK_I2C4_GATE, + .pclkGateID = PCLK_I2C4_GATE, + .runtimeID = PM_RUNTIME_ID_I2C4, +}; + +const struct HAL_I2C_DEV g_i2c5Dev = +{ + .pReg = I2C5, + .irqNum = I2C5_IRQn, + .clkID = CLK_I2C, + .clkGateID = CLK_I2C5_GATE, + .pclkGateID = PCLK_I2C5_GATE, + .runtimeID = PM_RUNTIME_ID_I2C5, +}; +#endif + +#ifdef HAL_FSPI_MODULE_ENABLED +struct HAL_FSPI_HOST g_fspi0Dev = +{ + .instance = FSPI, + .sclkGate = SCLK_SFC_GATE, + .hclkGate = HCLK_SFC_GATE, + .xipClkGate = 0, + .sclkID = 0, + .irqNum = FSPI0_IRQn, + .xipMemCode = 0, + .xipMemData = 0, + .xmmcDev[0] = + { + .type = 0, + }, +}; +#endif + +#ifdef HAL_CANFD_MODULE_ENABLED +const struct HAL_CANFD_DEV g_can0Dev = +{ + .pReg = CAN0, + .sclkID = CLK_CAN0, + .sclkGateID = CLK_CAN0_GATE, + .pclkGateID = PCLK_CAN0_GATE, + .irqNum = CAN0_IRQn, +}; + +const struct HAL_CANFD_DEV g_can1Dev = +{ + .pReg = CAN1, + .sclkID = CLK_CAN1, + .sclkGateID = CLK_CAN1_GATE, + .pclkGateID = PCLK_CAN1_GATE, + .irqNum = CAN1_IRQn, +}; + +const struct HAL_CANFD_DEV g_can2Dev = +{ + .pReg = CAN2, + .sclkID = CLK_CAN2, + .sclkGateID = CLK_CAN2_GATE, + .pclkGateID = PCLK_CAN2_GATE, + .irqNum = CAN2_IRQn, +}; +#endif + +#ifdef HAL_GMAC_MODULE_ENABLED +// const struct HAL_GMAC_DEV g_gmac0Dev = +// { +// .pReg = GMAC0, +// .clkID = CLK_MAC0_2TOP, +// .clkGateID = CLK_MAC0_2TOP_GATE, +// .pclkID = PCLK_PHP, +// .pclkGateID = PCLK_GMAC0_GATE, +// .irqNum = GMAC0_IRQn, +// }; +const struct HAL_GMAC_DEV g_gmac0Dev = +{ + .pReg = GMAC0, + .clkID125M = CLK_MAC0_2TOP, + .clkID50M = CLK_MAC0_2TOP, + .clkGateID125M = CLK_MAC0_2TOP_GATE, + .clkGateID50M = CLK_MAC0_2TOP_GATE, + .pclkID = PCLK_PHP, + .pclkGateID = PCLK_GMAC0_GATE, + .irqNum = GMAC0_IRQn, +}; + +// const struct HAL_GMAC_DEV g_gmac1Dev = +// { +// .pReg = GMAC1, +// .clkID = CLK_MAC1_2TOP, +// .clkGateID = CLK_MAC1_2TOP_GATE, +// .pclkID = PCLK_USB, +// .pclkGateID = PCLK_GMAC1_GATE, +// .irqNum = GMAC1_IRQn, +// }; +const struct HAL_GMAC_DEV g_gmac1Dev = +{ + .pReg = GMAC1, + .clkID125M = CLK_MAC1_2TOP, + .clkID50M = CLK_MAC1_2TOP, + .clkGateID125M = CLK_MAC1_2TOP_GATE, + .clkGateID50M = CLK_MAC1_2TOP_GATE, + .pclkID = PCLK_USB, + .pclkGateID = PCLK_GMAC1_GATE, + .irqNum = GMAC1_IRQn, +}; +#endif + +#ifdef HAL_PCIE_MODULE_ENABLED +struct HAL_PCIE_DEV g_pcieDev = +{ + .apbBase = PCIE3X2_APB_BASE, + .dbiBase = PCIE3X2_DBI_BASE, + .cfgBase = 0xF0000000, + .lanes = 2, + .gen = 3, + .firstBusNo = 0x20, + .legacyIrqNum = PCIE30x2_LEGACY_IRQn, +}; +#endif + +#ifdef HAL_PWM_MODULE_ENABLED +const struct HAL_PWM_DEV g_pwm0Dev = +{ + .pReg = PWM0, + .clkID = 0, + .clkGateID = CLK_PWM0_GATE, + .pclkGateID = PCLK_PWM0_GATE, + .irqNum = PWM_PMU_IRQn, +}; + +const struct HAL_PWM_DEV g_pwm1Dev = +{ + .pReg = PWM1, + .clkID = CLK_PWM1, + .clkGateID = CLK_PWM1_GATE, + .pclkGateID = PCLK_PWM1_GATE, + .irqNum = PWM1_IRQn, +}; + +const struct HAL_PWM_DEV g_pwm2Dev = +{ + .pReg = PWM2, + .clkID = CLK_PWM2, + .clkGateID = CLK_PWM2_GATE, + .pclkGateID = PCLK_PWM2_GATE, + .irqNum = PWM2_IRQn, +}; + +const struct HAL_PWM_DEV g_pwm3Dev = +{ + .pReg = PWM3, + .clkID = CLK_PWM3, + .clkGateID = CLK_PWM3_GATE, + .pclkGateID = PCLK_PWM3_GATE, + .irqNum = PWM3_IRQn, +}; +#endif + +void BSP_Init(void) +{ +} diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_cru.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_cru.c new file mode 100644 index 000000000..56fa83e86 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_cru.c @@ -0,0 +1,1739 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#ifdef HAL_CRU_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup CRU + * @{ + */ + +/** @defgroup CRU_How_To_Use How To Use + * @{ + + The CRU driver can be used as follows: + + - Invoke cru functions to set clk rate, enable or disable clk, reset clk in each device. + - The gate and soft reset id is include register offset and shift information: + + con_offset: id /16 + shift: id %16 + + - The mux and div id is include register offset, shift, mask information: + + [15:0]: con + [23:16]: shift + [31:24]: width + + - CRU driver is just responsible for passing simple command data, And + the usecount is the user's responsibility. Protection the usecount at the driver layer. + - More details refer to APIs' descriptions as below. + + @} */ + +/** @defgroup CRU_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ +#if defined(SOC_RV1108) +#define PWRDOWN_SHIFT 0 +#define PWRDOWN_MASK 1 << PWRDOWN_SHIFT +#define PLL_POSTDIV1_SHIFT 8 +#define PLL_POSTDIV1_MASK 0x7 << PLL_POSTDIV1_SHIFT +#define PLL_FBDIV_SHIFT 0 +#define PLL_FBDIV_MASK 0xfff << PLL_FBDIV_SHIFT +#define PLL_POSTDIV2_SHIFT 12 +#define PLL_POSTDIV2_MASK 0x7 << PLL_POSTDIV2_SHIFT +#define PLL_REFDIV_SHIFT 0 +#define PLL_REFDIV_MASK 0x3f << PLL_REFDIV_SHIFT +#define PLL_DSMPD_SHIFT 3 +#define PLL_DSMPD_MASK 1 << PLL_DSMPD_SHIFT +#define PLL_FRAC_SHIFT 0 +#define PLL_FRAC_MASK 0xffffff << PLL_FRAC_SHIFT +#elif defined(SOC_RK3588) +#define PLLCON0_M_SHIFT 0 +#define PLLCON0_M_MASK 0x3ff << PLLCON0_M_SHIFT +#define PLLCON1_P_SHIFT 0 +#define PLLCON1_P_MASK 0x3f << PLLCON1_P_SHIFT +#define PLLCON1_S_SHIFT 6 +#define PLLCON1_S_MASK 0x7 << PLLCON1_S_SHIFT +#define PLLCON2_K_SHIFT 0 +#define PLLCON2_K_MASK 0xffff << PLLCON2_K_SHIFT +#define PLLCON1_PWRDOWN BIT(13) +#define PLLCON6_LOCK_STATUS BIT(15) + +#define BYPASS_SHIFT 15 +#define BYPASS_MASK (1 << BYPASS_SHIFT) + +#define PWRDOWN_SHIFT 13 +#define PWRDOWN_MASK (1 << PWRDOWN_SHIFT) + +#else +#define PWRDOWN_SHIFT 13 +#define PWRDOWN_MASK 1 << PWRDOWN_SHIFT +#define PLL_POSTDIV1_SHIFT 12 +#define PLL_POSTDIV1_MASK 0x7 << PLL_POSTDIV1_SHIFT +#define PLL_FBDIV_SHIFT 0 +#define PLL_FBDIV_MASK 0xfff << PLL_FBDIV_SHIFT +#define PLL_POSTDIV2_SHIFT 6 +#define PLL_POSTDIV2_MASK 0x7 << PLL_POSTDIV2_SHIFT +#define PLL_REFDIV_SHIFT 0 +#define PLL_REFDIV_MASK 0x3f << PLL_REFDIV_SHIFT +#define PLL_DSMPD_SHIFT 12 +#define PLL_DSMPD_MASK 1 << PLL_DSMPD_SHIFT +#define PLL_FRAC_SHIFT 0 +#define PLL_FRAC_MASK 0xffffff << PLL_FRAC_SHIFT +#endif + +#define MIN_FOUTVCO_FREQ (800 * MHZ) +#define MAX_FOUTVCO_FREQ (2000 * MHZ) +#define MIN_FOUT_FREQ (24 * MHZ) +#define MAX_FOUT_FREQ (1600 * MHZ) + +#define EXPONENT_OF_FRAC_PLL 24 +#define RK_PLL_MODE_SLOW 0 +#define RK_PLL_MODE_NORMAL 1 +#define RK_PLL_MODE_DEEP 2 +#define PLL_GET_PLLMODE(val, shift, mask) (((uint32_t)(val) & mask) >> shift) + +#define PLL_GET_FBDIV(x) (((uint32_t)(x) & (PLL_FBDIV_MASK)) >> PLL_FBDIV_SHIFT) +#define PLL_GET_REFDIV(x) \ + (((uint32_t)(x) & (PLL_REFDIV_MASK)) >> PLL_REFDIV_SHIFT) +#define PLL_GET_POSTDIV1(x) \ + (((uint32_t)(x) & (PLL_POSTDIV1_MASK)) >> PLL_POSTDIV1_SHIFT) +#define PLL_GET_POSTDIV2(x) \ + (((uint32_t)(x) & (PLL_POSTDIV2_MASK)) >> PLL_POSTDIV2_SHIFT) +#define PLL_GET_DSMPD(x) (((uint32_t)(x) & (PLL_DSMPD_MASK)) >> PLL_DSMPD_SHIFT) +#define PLL_GET_FRAC(x) (((uint32_t)(x) & (PLL_FRAC_MASK)) >> PLL_FRAC_SHIFT) + +#define CRU_PLL_ROUND_UP_TO_KHZ(x) (HAL_DIV_ROUND_UP((x), KHZ) * KHZ) + +#define CRU_READ(r) (*(volatile uint32_t *)((uintptr_t)(r))) +#define CRU_WRITE(r, b, w, v) (*(volatile uint32_t *)((uintptr_t)(r)) = ((w) << (16) | (v) << (b))) + +/********************* Private Structure Definition **************************/ +static struct PLL_CONFIG g_rockchipAutoTable; +__attribute__((weak)) const struct HAL_CRU_DEV g_cruDev; + +/********************* Private Variable Definition ***************************/ +/********************* Private Function Definition ***************************/ + +/** Calculate the greatest common divisor */ +static uint32_t CRU_Gcd(uint32_t m, uint32_t n) +{ + int t; + + while (m > 0) { + if (n > m) { + t = m; + m = n; + n = t; + } + m -= n; + } + + return n; +} + +static int isBetterFreq(uint32_t now, uint32_t new, uint32_t best) +{ + return (new <= now && new > best); +} + +int HAL_CRU_FreqGetMuxArray(uint32_t freq, uint32_t *table, int num) +{ + uint32_t best = 0, mux = 0; + int i; + + for (i = 0; i < num; i++) { + if (isBetterFreq(freq, table[i], best)) { + best = table[i]; + mux = i; + break; + } + } + + return mux; +} + +int HAL_CRU_FreqGetMux4(uint32_t freq, uint32_t freq0, uint32_t freq1, + uint32_t freq2, uint32_t freq3) +{ + uint32_t best = 0; + + if (isBetterFreq(freq, freq0, best)) { + best = freq0; + } + + if (isBetterFreq(freq, freq1, best)) { + best = freq1; + } + + if (isBetterFreq(freq, freq2, best)) { + best = freq2; + } + + if (isBetterFreq(freq, freq3, best)) { + best = freq3; + } + + if (best == freq0) { + return 0; + } else if (best == freq1) { + return 1; + } else if (best == freq2) { + return 2; + } else if (best == freq3) { + return 3; + } + + return HAL_INVAL; +} + +int HAL_CRU_FreqGetMux3(uint32_t freq, uint32_t freq0, uint32_t freq1, uint32_t freq2) +{ + return HAL_CRU_FreqGetMux4(freq, freq0, freq1, freq2, freq2); +} + +int HAL_CRU_FreqGetMux2(uint32_t freq, uint32_t freq0, uint32_t freq1) +{ + return HAL_CRU_FreqGetMux4(freq, freq0, freq1, freq1, freq1); +} + +uint32_t HAL_CRU_MuxGetFreqArray(uint32_t muxName, uint32_t *table, int num) +{ + uint32_t mux = HAL_CRU_ClkGetMux(muxName); + + if (mux <= (uint32_t)num) { + return table[mux]; + } else { + return HAL_INVAL; + } +} + +uint32_t HAL_CRU_MuxGetFreq4(uint32_t muxName, uint32_t freq0, uint32_t freq1, + uint32_t freq2, uint32_t freq3) +{ + switch (HAL_CRU_ClkGetMux(muxName)) { + case 0: + + return freq0; + case 1: + + return freq1; + case 2: + + return freq2; + case 3: + + return freq3; + } + + return HAL_INVAL; +} + +uint32_t HAL_CRU_MuxGetFreq3(uint32_t muxName, uint32_t freq0, + uint32_t freq1, uint32_t freq2) +{ + return HAL_CRU_MuxGetFreq4(muxName, freq0, freq1, freq2, freq2); +} + +uint32_t HAL_CRU_MuxGetFreq2(uint32_t muxName, uint32_t freq0, uint32_t freq1) +{ + return HAL_CRU_MuxGetFreq4(muxName, freq0, freq1, freq1, freq1); +} + +int HAL_CRU_RoundFreqGetMuxArray(uint32_t freq, uint32_t *table, int num, uint32_t *pFreqOut, bool is_div) +{ + uint32_t mux = 0; + int i = 0; + + for (i = 0; i < num; i++) { + if (is_div) { + if (table[i] && (table[i] % freq == 0)) { + mux = i; + break; + } + } else { + if (table[i] && (table[i] == freq)) { + mux = i; + break; + } + } + } + + *pFreqOut = table[mux]; + + return mux; +} + +int HAL_CRU_RoundFreqGetMux4(uint32_t freq, uint32_t pFreq0, + uint32_t pFreq1, uint32_t pFreq2, + uint32_t pFreq3, uint32_t *pFreqOut) +{ + uint32_t mux; + + if (pFreq3 && (pFreq3 % freq == 0)) { + *pFreqOut = pFreq3; + mux = 3; + } else if (pFreq2 && (pFreq2 % freq == 0)) { + *pFreqOut = pFreq2; + mux = 2; + } else if (pFreq1 % freq == 0) { + *pFreqOut = pFreq1; + mux = 1; + } else { + *pFreqOut = pFreq0; + mux = 0; + } + + return mux; +} + +int HAL_CRU_RoundFreqGetMux3(uint32_t freq, uint32_t pFreq0, + uint32_t pFreq1, uint32_t pFreq2, uint32_t *pFreqOut) +{ + return HAL_CRU_RoundFreqGetMux4(freq, pFreq0, pFreq1, pFreq2, 0, pFreqOut); +} + +int HAL_CRU_RoundFreqGetMux2(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1, uint32_t *pFreqOut) +{ + return HAL_CRU_RoundFreqGetMux4(freq, pFreq0, pFreq1, 0, 0, pFreqOut); +} + +#if defined(SOC_RK3588) +/** + * @brief Get pll parameter by auto. + * @param finHz: pll intput freq + * @param foutHz: pll output freq + * @return struct PLL_CONFIG. + * How to calculate the PLL: + * FFVCO = ((m + k / 65536) * FFIN) / p + * FFOUT = ((m + k / 65536) * FFIN) / (p * 2^s) + */ +static const struct PLL_CONFIG *CRU_PllSetByAuto(uint32_t finHz, uint32_t foutHz) +{ + struct PLL_CONFIG *rateTable = &g_rockchipAutoTable; + uint64_t fvcoMin = 2250ULL * MHZ, fvcoMax = 4500ULL * MHZ; + uint64_t foutMin = 37ULL * MHZ, foutMax = 4500ULL * MHZ; + uint64_t fvco, fref, fout, ffrac; + uint32_t p, m, s; + + if (finHz == 0 || foutHz == 0 || foutHz == finHz) { + return NULL; + } + + if (foutHz > foutMax || foutHz < foutMin) { + return NULL; + } + + if (finHz / MHZ * MHZ == finHz && foutHz / MHZ * MHZ == foutHz) { + for (s = 0; s <= 6; s++) { + fvco = (uint64_t)foutHz << s; + if (fvco < fvcoMin || fvco > fvcoMax) { + continue; + } + + for (p = 2; p <= 4; p++) { + for (m = 64; m <= 1023; m++) { + if (fvco == m * finHz / p) { + rateTable->p = p; + rateTable->m = m; + rateTable->s = s; + rateTable->k = 0; + + return rateTable; + } + } + } + } + } else { + for (s = 0; s <= 6; s++) { + fvco = (uint64_t)foutHz << s; + if (fvco < fvcoMin || fvco > fvcoMax) { + continue; + } + + for (p = 1; p <= 4; p++) { + for (m = 64; m <= 1023; m++) { + if ((fvco >= m * finHz / p) && (fvco < (m + 1) * finHz / p)) { + rateTable->p = p; + rateTable->m = m; + rateTable->s = s; + fref = finHz / p; + ffrac = fvco - (m * fref); + fout = ffrac * 65536; + rateTable->k = fout / fref; + + return rateTable; + } + } + } + } + } + + return NULL; +} + +#else +/** + * @brief Rockchip pll clk set postdiv. + * @param foutHz: output freq + * @param *postDiv1: pll postDiv1 + * @param *postDiv2: pll postDiv2 + * @param *foutVco: pll vco + * @return HAL_Status. + * How to calculate the PLL: + * Formulas also embedded within the fractional PLL Verilog model: + * If DSMPD = 1 (DSM is disabled, "integer mode") + * FOUTVCO = FREF / REFDIV * FBDIV + * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 + * Where: + * FOUTVCO = fractional PLL non-divided output frequency + * FOUTPOSTDIV = fractional PLL divided output frequency + * (output of second post divider) + */ +static HAL_Status CRU_PllSetPostDiv(uint32_t foutHz, uint32_t *postDiv1, + uint32_t *postDiv2, uint32_t *foutVco) +{ + uint32_t freq; + + if (foutHz < MIN_FOUTVCO_FREQ) { + for (*postDiv1 = 1; *postDiv1 <= 7; (*postDiv1)++) { + for (*postDiv2 = 1; *postDiv2 <= 7; (*postDiv2)++) { + freq = foutHz * (*postDiv1) * (*postDiv2); + if (freq >= MIN_FOUTVCO_FREQ && freq <= MAX_FOUTVCO_FREQ) { + *foutVco = freq; + + return HAL_OK; + } + } + } + + return HAL_ERROR; + } else { + *postDiv1 = 1; + *postDiv2 = 1; + + return HAL_OK; + } +} + +/** + * @brief Get pll parameter by auto. + * @param finHz: pll intput freq + * @param foutHz: pll output freq + * @return struct PLL_CONFIG. + * How to calculate the PLL: + * Formulas also embedded within the fractional PLL Verilog model: + * If DSMPD = 1 (DSM is disabled, "integer mode") + * FOUTVCO = FREF / REFDIV * FBDIV + * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 + * Where: + * FOUTVCO = fractional PLL non-divided output frequency + * FOUTPOSTDIV = fractional PLL divided output frequency + * (output of second post divider) + * FREF = fractional PLL input reference frequency, (the OSC_HZ 24MHz input) + * REFDIV = fractional PLL input reference clock divider + * FBDIV = Integer value programmed into feedback divide + */ +static const struct PLL_CONFIG *CRU_PllSetByAuto(uint32_t finHz, + uint32_t foutHz) +{ + struct PLL_CONFIG *rateTable = &g_rockchipAutoTable; + uint32_t foutVco = foutHz; + uint64_t fin64, frac64; + uint32_t postDiv1, postDiv2; + uint32_t clkGcd = 0; + HAL_Status error; + + if (finHz == 0 || foutHz == 0 || foutHz == finHz) { + return NULL; + } + + error = CRU_PllSetPostDiv(foutHz, &postDiv1, &postDiv2, &foutVco); + if (error) { + return NULL; + } + rateTable->postDiv1 = postDiv1; + rateTable->postDiv2 = postDiv2; + rateTable->dsmpd = 1; + + if (finHz / MHZ * MHZ == finHz && foutHz / MHZ * MHZ == foutHz) { + finHz /= MHZ; + foutVco /= MHZ; + clkGcd = CRU_Gcd(finHz, foutVco); + rateTable->refDiv = finHz / clkGcd; + rateTable->fbDiv = foutVco / clkGcd; + + rateTable->frac = 0; + } else if (finHz / MHZ * MHZ != finHz) { + clkGcd = foutHz / finHz; + rateTable->fbDiv = clkGcd; + rateTable->refDiv = 1; + rateTable->postDiv1 = 1; + rateTable->postDiv2 = 1; + + fin64 = foutHz * rateTable->refDiv; + fin64 = HAL_DivU64(fin64 << EXPONENT_OF_FRAC_PLL, finHz); + frac64 = rateTable->fbDiv; + frac64 = rateTable->fbDiv << EXPONENT_OF_FRAC_PLL; + frac64 = fin64 - frac64; + rateTable->frac = frac64; + if (rateTable->frac > 0) { + rateTable->dsmpd = 0; + } + } else { + clkGcd = CRU_Gcd(finHz / MHZ, foutVco / MHZ); + rateTable->refDiv = finHz / MHZ / clkGcd; + rateTable->fbDiv = foutVco / MHZ / clkGcd; + rateTable->frac = 0; + + frac64 = (foutVco % MHZ); + fin64 = finHz; + frac64 = frac64 * rateTable->refDiv; + frac64 = HAL_DivU64(frac64 << EXPONENT_OF_FRAC_PLL, fin64); + rateTable->frac = frac64; + if (rateTable->frac > 0) { + rateTable->dsmpd = 0; + } + } + + return rateTable; +} +#endif + +/** + * @brief Get pll parameter by rateTable. + * @param *pSetup: struct PLL_SETUP struct, Contains PLL register parameters + * @param rate: pll target rate. + * @return struct PLL_CONFIG. + * How to calculate the PLL: + * Look up the rateTable to get the PLL config parameter + */ +static const struct PLL_CONFIG *CRU_PllGetSettings(struct PLL_SETUP *pSetup, + uint32_t rate) +{ + const struct PLL_CONFIG *rateTable = pSetup->rateTable; + + if (rateTable == NULL) { + return CRU_PllSetByAuto(PLL_INPUT_OSC_RATE, rate); + } + + while (rateTable->rate) { + if (rateTable->rate == rate) { + break; + } + rateTable++; + } + if (rateTable->rate != rate) { + return CRU_PllSetByAuto(PLL_INPUT_OSC_RATE, rate); + } else { + return rateTable; + } +} +/** @} */ +/********************* Public Function Definition ****************************/ + +/** @defgroup CRU_Exported_Functions_Group5 Other Functions + * @attention these APIs allow direct use in the HAL layer. + * @{ + */ + +#if defined(SOC_RV1108) +/* + * Formulas also embedded within the fractional PLL Verilog model: + * If DSMPD = 1 (DSM is disabled, "integer mode") + * FOUTVCO = FREF / REFDIV * FBDIV + * FOUT = FOUTVCO / POSTDIV1 / POSTDIV2 + * If DSMPD = 0 (DSM is enabled, "fractional mode") + * FOUTVCO = (FREF / REFDIV) * (FBDIV + FRAC / (2^24)) + * FOUTPOSTDIV = FOUTVCO / (POSTDIV1*POSTDIV2) + * FOUT = FOUTVCO / POSTDIV1 / POSTDIV2 + */ +uint32_t HAL_CRU_GetPllFreq(struct PLL_SETUP *pSetup) +{ + uint32_t refDiv, fbDiv, postdDv1, postDiv2, frac, dsmpd; + uint32_t mode = 0, rate = PLL_INPUT_OSC_RATE; + + mode = PLL_GET_PLLMODE(READ_REG(*(pSetup->modeOffset)), pSetup->modeShift, + pSetup->modeMask); + + switch (mode) { + case RK_PLL_MODE_SLOW: + rate = PLL_INPUT_OSC_RATE; + break; + case RK_PLL_MODE_NORMAL: + fbDiv = PLL_GET_FBDIV(READ_REG(*(pSetup->conOffset0))); + postdDv1 = PLL_GET_POSTDIV1(READ_REG(*(pSetup->conOffset1))); + postDiv2 = PLL_GET_POSTDIV2(READ_REG(*(pSetup->conOffset1))); + refDiv = PLL_GET_REFDIV(READ_REG(*(pSetup->conOffset1))); + dsmpd = PLL_GET_DSMPD(READ_REG(*(pSetup->conOffset3))); + frac = PLL_GET_FRAC(READ_REG(*(pSetup->conOffset2))); + rate = (rate / refDiv) * fbDiv; + if (dsmpd == 0) { + uint64_t fracRate = PLL_INPUT_OSC_RATE; + + fracRate *= frac; + fracRate = fracRate >> EXPONENT_OF_FRAC_PLL; + fracRate = fracRate / refDiv; + rate += fracRate; + } + rate = rate / (postdDv1 * postDiv2); + rate = CRU_PLL_ROUND_UP_TO_KHZ(rate); + break; + case RK_PLL_MODE_DEEP: + default: + rate = 32768; + break; + } + + return rate; +} + +/* + * Force PLL into slow mode + * Pll Power down + * Pll Config fbDiv, refDiv, postdDv1, postDiv2, dsmpd, frac + * Pll Power up + * Waiting for pll lock + * Force PLL into normal mode + */ +HAL_Status HAL_CRU_SetPllFreq(struct PLL_SETUP *pSetup, uint32_t rate) +{ + const struct PLL_CONFIG *pConfig; + int delay = 2400; + + if (rate == HAL_CRU_GetPllFreq(pSetup)) { + return HAL_OK; + } else if (rate < MIN_FOUT_FREQ) { + return HAL_INVAL; + } else if (rate > MAX_FOUT_FREQ) { + return HAL_INVAL; + } + + pConfig = CRU_PllGetSettings(pSetup, rate); + if (!pConfig) { + return HAL_ERROR; + } + + /* Force PLL into slow mode to ensure output stable clock */ + WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_SLOW << pSetup->modeShift); + + /* Pll Power down */ + WRITE_REG_MASK_WE(*(pSetup->conOffset3), PWRDOWN_MASK, 1 << PWRDOWN_SHIFT); + + /* Pll Config */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_POSTDIV2_MASK, pConfig->postDiv2 << PLL_POSTDIV2_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_REFDIV_MASK, pConfig->refDiv << PLL_REFDIV_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_POSTDIV1_MASK, pConfig->postDiv1 << PLL_POSTDIV1_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset0), PLL_FBDIV_MASK, pConfig->fbDiv << PLL_FBDIV_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset3), PLL_DSMPD_MASK, pConfig->dsmpd << PLL_DSMPD_SHIFT); + + if (pConfig->frac) { + WRITE_REG(*(pSetup->conOffset2), (READ_REG(*(pSetup->conOffset2)) & 0xff000000) | pConfig->frac); + } + + WRITE_REG_MASK_WE(*(pSetup->conOffset3), PWRDOWN_MASK, 0 << PWRDOWN_SHIFT); + + /* Waiting for pll lock */ + while (delay > 0) { + if (READ_REG(*(pSetup->conOffset2)) & (1 << pSetup->lockShift)) { + break; + } + HAL_CPUDelayUs(1000); + delay--; + } + if (delay == 0) { + return HAL_TIMEOUT; + } + + /* Force PLL into normal mode */ + WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_NORMAL << pSetup->modeShift); + + return HAL_OK; +} + +HAL_Status HAL_CRU_SetPllPowerUp(struct PLL_SETUP *pSetup) +{ + int delay = 2400; + + /* Pll Power up */ + WRITE_REG_MASK_WE(*(pSetup->conOffset3), PWRDOWN_MASK, 0 << PWRDOWN_SHIFT); + + /* Waiting for pll lock */ + while (delay > 0) { + if (READ_REG(*(pSetup->conOffset2)) & (1 << pSetup->lockShift)) { + break; + } + HAL_CPUDelayUs(1000); + delay--; + } + if (delay == 0) { + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup) +{ + /* Pll Power down */ + WRITE_REG_MASK_WE(*(pSetup->conOffset3), PWRDOWN_MASK, 1 << PWRDOWN_SHIFT); + + return HAL_OK; +} + +#elif defined(SOC_RK3588) +/* + * Formulas also embedded within the fractional PLL Verilog model: + * If K = 0 (DSM is disabled, "integer mode") + * FOUTVCO = FREF / P * M + * FOUT = FOUTVCO / 2^S + * If K > 0 (DSM is enabled, "fractional mode") + * FOUTVCO = (FREF / P) * (M + K / 65536) + * FOUT = FOUTVCO / 2^S + */ +uint32_t HAL_CRU_GetPllFreq(struct PLL_SETUP *pSetup) +{ + uint32_t m, p, s, k; + uint64_t rate = PLL_INPUT_OSC_RATE; + uint32_t mode = 0; + + if (pSetup->modeMask) { + mode = PLL_GET_PLLMODE(READ_REG(*(pSetup->modeOffset)), pSetup->modeShift, + pSetup->modeMask); + } else { + mode = RK_PLL_MODE_NORMAL; + } + + switch (mode) { + case RK_PLL_MODE_SLOW: + rate = PLL_INPUT_OSC_RATE; + break; + + case RK_PLL_MODE_NORMAL: + m = (READ_REG(*(pSetup->conOffset0)) & PLLCON0_M_MASK) >> PLLCON0_M_SHIFT; + p = (READ_REG(*(pSetup->conOffset1)) & PLLCON1_P_MASK) >> PLLCON1_P_SHIFT; + s = (READ_REG(*(pSetup->conOffset1)) & PLLCON1_S_MASK) >> PLLCON1_S_SHIFT; + k = (READ_REG(*(pSetup->conOffset2)) & PLLCON2_K_MASK) >> PLLCON2_K_SHIFT; + + rate *= m; + rate = rate / p; + if (k) { + /* fractional mode */ + uint64_t frac = PLL_INPUT_OSC_RATE / p; + + frac *= k; + frac = frac / 65536; + rate += frac; + } + rate = rate >> s; + break; + + case RK_PLL_MODE_DEEP: + default: + rate = 32768; + break; + } + + return rate; +} + +/* + * Force PLL into slow mode + * Pll Power down + * Pll Config M, P, S, K + * Pll Power up + * Waiting for pll lock + * Force PLL into normal mode + */ +HAL_Status HAL_CRU_SetPllFreq(struct PLL_SETUP *pSetup, uint32_t rate) +{ + const struct PLL_CONFIG *pConfig; + int delay = 24000000; + + if (rate == HAL_CRU_GetPllFreq(pSetup)) { + return HAL_OK; + } else if (rate < MIN_FOUT_FREQ) { + return HAL_INVAL; + } else if (rate > MAX_FOUT_FREQ) { + return HAL_INVAL; + } + + pConfig = CRU_PllGetSettings(pSetup, rate); + if (!pConfig) { + return HAL_ERROR; + } + + /* Force PLL into slow mode to ensure output stable clock */ + if (pSetup->modeMask) { + WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_SLOW << pSetup->modeShift); + } + + /* Pll Power down */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 1 << PWRDOWN_SHIFT); + + /* Pll Config */ + WRITE_REG_MASK_WE(*(pSetup->conOffset0), PLLCON0_M_MASK, pConfig->m << PLLCON0_M_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLLCON1_P_MASK, pConfig->p << PLLCON1_P_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLLCON1_S_MASK, pConfig->s << PLLCON1_S_SHIFT); + if (pConfig->k) { + WRITE_REG_MASK_WE(*(pSetup->conOffset2), PLLCON2_K_MASK, pConfig->k << PLLCON2_K_SHIFT); + } + + /* Pll Power up */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 0 << PWRDOWN_SHIFT); + + /* Waiting for pll lock */ + while (delay > 0) { + if (READ_REG(*(pSetup->conOffset6)) & (1 << pSetup->lockShift)) { + break; + } + delay--; + } + if (delay == 0) { + return HAL_TIMEOUT; + } + + /* Force PLL into normal mode */ + if (pSetup->modeMask) { + WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_NORMAL << pSetup->modeShift); + } + + /* + * PLL operates normally. + * + * ATF system suspend requires memory repair operation which would + * bypass the pll, let's ensure it's on normal mode. + */ + WRITE_REG_MASK_WE(*(pSetup->conOffset0), BYPASS_MASK, 0 << BYPASS_SHIFT); + + return HAL_OK; +} + +HAL_Status HAL_CRU_SetPllPowerUp(struct PLL_SETUP *pSetup) +{ + int delay = 2400; + + /* Pll Power up */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 0 << PWRDOWN_SHIFT); + + /* Waiting for pll lock */ + while (delay > 0) { + if (READ_REG(*(pSetup->conOffset6)) & (1 << pSetup->lockShift)) { + break; + } + HAL_CPUDelayUs(1000); + delay--; + } + if (delay == 0) { + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup) +{ + /* Pll Power down */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 1 << PWRDOWN_SHIFT); + + return HAL_OK; +} + +#else +/* + * Formulas also embedded within the fractional PLL Verilog model: + * If DSMPD = 1 (DSM is disabled, "integer mode") + * FOUTVCO = FREF / REFDIV * FBDIV + * FOUT = FOUTVCO / POSTDIV1 / POSTDIV2 + * If DSMPD = 0 (DSM is enabled, "fractional mode") + * FOUTVCO = (FREF / REFDIV) * (FBDIV + FRAC / (2^24)) + * FOUTPOSTDIV = FOUTVCO / (POSTDIV1*POSTDIV2) + * FOUT = FOUTVCO / POSTDIV1 / POSTDIV2 + */ +uint32_t HAL_CRU_GetPllFreq(struct PLL_SETUP *pSetup) +{ + uint64_t refDiv, fbDiv, postdDv1, postDiv2, frac, dsmpd; + uint32_t mode = 0, rate = PLL_INPUT_OSC_RATE; + + mode = PLL_GET_PLLMODE(READ_REG(*(pSetup->modeOffset)), pSetup->modeShift, + pSetup->modeMask); + + switch (mode) { + case RK_PLL_MODE_SLOW: + rate = PLL_INPUT_OSC_RATE; + break; + case RK_PLL_MODE_NORMAL: + postdDv1 = PLL_GET_POSTDIV1(READ_REG(*(pSetup->conOffset0))); + fbDiv = PLL_GET_FBDIV(READ_REG(*(pSetup->conOffset0))); + postDiv2 = PLL_GET_POSTDIV2(READ_REG(*(pSetup->conOffset1))); + refDiv = PLL_GET_REFDIV(READ_REG(*(pSetup->conOffset1))); + dsmpd = PLL_GET_DSMPD(READ_REG(*(pSetup->conOffset1))); + frac = PLL_GET_FRAC(READ_REG(*(pSetup->conOffset2))); + rate = (rate / refDiv) * fbDiv; + if (dsmpd == 0) { + uint64_t fracRate = PLL_INPUT_OSC_RATE; + + fracRate *= frac; + fracRate = fracRate >> EXPONENT_OF_FRAC_PLL; + fracRate = fracRate / refDiv; + rate += fracRate; + } + rate = rate / (postdDv1 * postDiv2); + rate = CRU_PLL_ROUND_UP_TO_KHZ(rate); + break; + case RK_PLL_MODE_DEEP: + default: + rate = 32768; + break; + } + + return rate; +} + +/* + * Force PLL into slow mode + * Pll Power down + * Pll Config fbDiv, refDiv, postdDv1, postDiv2, dsmpd, frac + * Pll Power up + * Waiting for pll lock + * Force PLL into normal mode + */ +HAL_Status HAL_CRU_SetPllFreq(struct PLL_SETUP *pSetup, uint32_t rate) +{ + const struct PLL_CONFIG *pConfig; + int delay = 2400; + + if (rate == HAL_CRU_GetPllFreq(pSetup)) { + return HAL_OK; + } else if (rate < MIN_FOUT_FREQ) { + return HAL_INVAL; + } else if (rate > MAX_FOUT_FREQ) { + return HAL_INVAL; + } + + pConfig = CRU_PllGetSettings(pSetup, rate); + if (!pConfig) { + return HAL_ERROR; + } + + /* Force PLL into slow mode to ensure output stable clock */ + WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_SLOW << pSetup->modeShift); + + /* Pll Power down */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 1 << PWRDOWN_SHIFT); + + /* Pll Config */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_POSTDIV2_MASK, pConfig->postDiv2 << PLL_POSTDIV2_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_REFDIV_MASK, pConfig->refDiv << PLL_REFDIV_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset0), PLL_POSTDIV1_MASK, pConfig->postDiv1 << PLL_POSTDIV1_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset0), PLL_FBDIV_MASK, pConfig->fbDiv << PLL_FBDIV_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_DSMPD_MASK, pConfig->dsmpd << PLL_DSMPD_SHIFT); + + if (pConfig->frac) { + WRITE_REG(*(pSetup->conOffset2), (READ_REG(*(pSetup->conOffset2)) & 0xff000000) | pConfig->frac); + } + + /* Pll Power up */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 0 << PWRDOWN_SHIFT); + + /* Waiting for pll lock */ + while (delay > 0) { + if (pSetup->stat0) { + if (READ_REG(*(pSetup->stat0)) & (1 << pSetup->lockShift)) { + break; + } + } else { + if (READ_REG(*(pSetup->conOffset1)) & (1 << pSetup->lockShift)) { + break; + } + } + HAL_CPUDelayUs(1000); + delay--; + } + if (delay == 0) { + return HAL_TIMEOUT; + } + + /* Force PLL into normal mode */ + WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_NORMAL << pSetup->modeShift); + + return HAL_OK; +} + +HAL_Status HAL_CRU_SetPllPowerUp(struct PLL_SETUP *pSetup) +{ + int delay = 2400; + + /* Pll Power up */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 0 << PWRDOWN_SHIFT); + + /* Waiting for pll lock */ + while (delay > 0) { + if (pSetup->stat0) { + if (READ_REG(*(pSetup->stat0)) & (1 << pSetup->lockShift)) { + break; + } + } else { + if (READ_REG(*(pSetup->conOffset1)) & (1 << pSetup->lockShift)) { + break; + } + } + HAL_CPUDelayUs(1000); + delay--; + } + if (delay == 0) { + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup) +{ + /* Pll Power down */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 1 << PWRDOWN_SHIFT); + + return HAL_OK; +} +#endif + +#ifdef CRU_CLK_USE_CON_BANK +static const struct HAL_CRU_DEV *CRU_GetInfo(void) +{ + return &g_cruDev; +} + +HAL_Check HAL_CRU_ClkIsEnabled(uint32_t clk) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); + uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); + uint32_t bank = CLK_GATE_GET_REG_BANK(clk); + uint32_t reg; + HAL_Check ret; + + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].gateOffset + index * 4; + ret = (HAL_Check)(!((CRU_READ(reg) & (1 << shift)) >> shift)); + + return ret; +} + +HAL_SECTION_SRAM_CODE +HAL_Status HAL_CRU_ClkEnable(uint32_t clk) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); + uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); + uint32_t bank = CLK_GATE_GET_REG_BANK(clk); + uint32_t reg; + + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].gateOffset + index * 4; + CRU_WRITE(reg, shift, 1U << shift, 0U); + + return HAL_OK; +} + +HAL_Status HAL_CRU_ClkDisable(uint32_t clk) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); + uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); + uint32_t bank = CLK_GATE_GET_REG_BANK(clk); + uint32_t reg; + + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].gateOffset + index * 4; + CRU_WRITE(reg, shift, 1U << shift, 1U); + + return HAL_OK; +} + +HAL_Status HAL_CRU_ClkDisableUnused(uint32_t bank, uint32_t index, uint32_t val) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t reg; + + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].gateOffset + index * 4; + CRU_WRITE(reg, 0, 0, val); + + return HAL_OK; +} + +HAL_Check HAL_CRU_ClkIsReset(uint32_t clk) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); + uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); + uint32_t bank = CLK_GATE_GET_REG_BANK(clk); + uint32_t reg; + HAL_Check ret; + + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4; + ret = (HAL_Check)((CRU_READ(reg) & (1 << shift)) >> shift); + + return ret; +} + +HAL_Status HAL_CRU_ClkResetAssert(uint32_t clk) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t index = CLK_RESET_GET_REG_OFFSET(clk); + uint32_t shift = CLK_RESET_GET_BITS_SHIFT(clk); + uint32_t bank = CLK_GATE_GET_REG_BANK(clk); + uint32_t reg; + + HAL_ASSERT(shift < 16); + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4; + CRU_WRITE(reg, shift, 1U << shift, 1U); + + return HAL_OK; +} + +HAL_Status HAL_CRU_ClkResetDeassert(uint32_t clk) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t index = CLK_RESET_GET_REG_OFFSET(clk); + uint32_t shift = CLK_RESET_GET_BITS_SHIFT(clk); + uint32_t bank = CLK_GATE_GET_REG_BANK(clk); + uint32_t reg; + + HAL_ASSERT(shift < 16); + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4; + CRU_WRITE(reg, shift, 1U << shift, 0U); + + return HAL_OK; +} + +HAL_Status HAL_CRU_ClkResetSyncAssert(int numClks, uint32_t *clks) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t index = CLK_RESET_GET_REG_OFFSET(clks[0]); + uint32_t bank = CLK_GATE_GET_REG_BANK(clks[0]); + uint32_t val = 0; + uint32_t reg; + int i; + + for (i = 0; i < numClks; i++) { + val |= HAL_BIT(CLK_RESET_GET_BITS_SHIFT(clks[i])); + if (index != CLK_RESET_GET_REG_OFFSET(clks[i])) { + return HAL_ERROR; + } + } + + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4; + CRU_WRITE(reg, 0, val, val); + HAL_DBG("%s: index: 0x%lx, val: 0x%lx\n", __func__, index, val); + + return HAL_OK; +} + +HAL_Status HAL_CRU_ClkResetSyncDeassert(int numClks, uint32_t *clks) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t index = CLK_RESET_GET_REG_OFFSET(clks[0]); + uint32_t bank = CLK_GATE_GET_REG_BANK(clks[0]); + uint32_t val = 0; + uint32_t reg; + int i; + + for (i = 0; i < numClks; i++) { + val |= HAL_BIT(CLK_RESET_GET_BITS_SHIFT(clks[i])); + if (index != CLK_RESET_GET_REG_OFFSET(clks[i])) { + return HAL_ERROR; + } + } + + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4; + CRU_WRITE(reg, 0, val, 0); + HAL_DBG("%s: index: 0x%lx, val: 0x%lx\n", __func__, index, val); + + return HAL_OK; +} + +HAL_SECTION_SRAM_CODE +HAL_Status HAL_CRU_ClkSetDiv(uint32_t divName, uint32_t divValue) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t shift, mask, index; + uint32_t reg, bank, maxDiv; + + index = CLK_DIV_GET_REG_OFFSET(divName); + shift = CLK_DIV_GET_BITS_SHIFT(divName); + HAL_ASSERT(shift < 16); + mask = CLK_DIV_GET_MASK(divName); + maxDiv = CLK_DIV_GET_MAXDIV(divName) + 1; + if (divValue > maxDiv) { + divValue = maxDiv; + } + + bank = CLK_DIV_GET_BANK(divName); + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4; + CRU_WRITE(reg, shift, mask, (divValue - 1U)); + + return HAL_OK; +} + +uint32_t HAL_CRU_ClkGetDiv(uint32_t divName) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t shift, mask, index, divValue; + uint32_t reg, bank; + + index = CLK_DIV_GET_REG_OFFSET(divName); + shift = CLK_DIV_GET_BITS_SHIFT(divName); + HAL_ASSERT(shift < 16); + mask = CLK_DIV_GET_MASK(divName); + bank = CLK_DIV_GET_BANK(divName); + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4; + divValue = ((CRU_READ(reg) & mask) >> shift) + 1; + + return divValue; +} + +HAL_SECTION_SRAM_CODE +HAL_Status HAL_CRU_ClkSetMux(uint32_t muxName, uint32_t muxValue) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t shift, mask, index; + uint32_t reg, bank; + + index = CLK_MUX_GET_REG_OFFSET(muxName); + shift = CLK_MUX_GET_BITS_SHIFT(muxName); + HAL_ASSERT(shift < 16); + mask = CLK_MUX_GET_MASK(muxName); + bank = CLK_MUX_GET_BANK(muxName); + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4; + CRU_WRITE(reg, shift, mask, muxValue); + + return HAL_OK; +} + +HAL_SECTION_SRAM_CODE +uint32_t HAL_CRU_ClkGetMux(uint32_t muxName) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t shift, mask, index, muxValue; + uint32_t reg, bank; + + index = CLK_MUX_GET_REG_OFFSET(muxName); + shift = CLK_MUX_GET_BITS_SHIFT(muxName); + HAL_ASSERT(shift < 16); + mask = CLK_MUX_GET_MASK(muxName); + bank = CLK_MUX_GET_BANK(muxName); + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4; + muxValue = ((CRU_READ(reg) & mask) >> shift); + + return muxValue; +} + +HAL_Status HAL_CRU_ClkSetFracDiv(uint32_t fracDivName, + uint32_t numerator, + uint32_t denominator) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t reg, bank; + uint32_t index; + + index = CLK_DIV_GET_REG_OFFSET(fracDivName); + bank = CLK_DIV_GET_BANK(fracDivName); + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4; + CRU_WRITE(reg, 0, 0, ((numerator << 16) | denominator)); + + return HAL_OK; +} + +HAL_Status HAL_CRU_ClkGetFracDiv(uint32_t fracDivName, + uint32_t *numerator, + uint32_t *denominator) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t reg, bank; + uint32_t index; + uint32_t val; + + index = CLK_DIV_GET_REG_OFFSET(fracDivName); + bank = CLK_DIV_GET_BANK(fracDivName); + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4; + val = CRU_READ(reg); + + *numerator = (val & 0xffff0000) >> 16; + *denominator = (val & 0x0000ffff); + + return HAL_OK; +} +#else /* CRU_CLK_USE_CON_BANK */ + +HAL_Check HAL_CRU_ClkIsEnabled(uint32_t clk) +{ + uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); + uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); + HAL_Check ret; + +#ifdef CRU_GATE_CON_CNT + if (index < CRU_GATE_CON_CNT) { + ret = (HAL_Check)(!((CRU->CRU_CLKGATE_CON[index] & (1 << shift)) >> shift)); + } else { +#ifdef PMUCRU_BASE + ret = (HAL_Check)(!((PMUCRU->CRU_CLKGATE_CON[index - CRU_GATE_CON_CNT] & (1 << shift)) >> shift)); +#else + ret = (HAL_Check)(!((CRU->PMU_CLKGATE_CON[index - CRU_GATE_CON_CNT] & (1 << shift)) >> shift)); +#endif + } +#else + ret = (HAL_Check)(!((CRU->CRU_CLKGATE_CON[index] & (1 << shift)) >> shift)); +#endif + + return ret; +} + +HAL_Status HAL_CRU_ClkEnable(uint32_t clk) +{ + uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); + uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); + +#ifdef CRU_GATE_CON_CNT + if (index < CRU_GATE_CON_CNT) { + CRU->CRU_CLKGATE_CON[index] = VAL_MASK_WE(1U << shift, 0U << shift); + } else { +#ifdef PMUCRU_BASE + PMUCRU->CRU_CLKGATE_CON[index - CRU_GATE_CON_CNT] = VAL_MASK_WE(1U << shift, 0U << shift); +#else + CRU->PMU_CLKGATE_CON[index - CRU_GATE_CON_CNT] = VAL_MASK_WE(1U << shift, 0U << shift); +#endif + } +#else + CRU->CRU_CLKGATE_CON[index] = VAL_MASK_WE(1U << shift, 0U << shift); +#endif + + return HAL_OK; +} + +HAL_Status HAL_CRU_ClkDisable(uint32_t clk) +{ + uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); + uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); + +#ifdef CRU_GATE_CON_CNT + if (index < CRU_GATE_CON_CNT) { + CRU->CRU_CLKGATE_CON[index] = VAL_MASK_WE(1U << shift, 1U << shift); + } else { +#ifdef PMUCRU_BASE + PMUCRU->CRU_CLKGATE_CON[index - CRU_GATE_CON_CNT] = VAL_MASK_WE(1U << shift, 1U << shift); +#else + CRU->PMU_CLKGATE_CON[index - CRU_GATE_CON_CNT] = VAL_MASK_WE(1U << shift, 1U << shift); +#endif + } +#else + CRU->CRU_CLKGATE_CON[index] = VAL_MASK_WE(1U << shift, 1U << shift); +#endif + + return HAL_OK; +} + +HAL_Status HAL_CRU_ClkDisableUnused(uint32_t bank, uint32_t index, uint32_t val) +{ +#ifdef CRU_GATE_CON_CNT + if (index < CRU_GATE_CON_CNT) { + CRU->CRU_CLKGATE_CON[index] = val; + } else { +#ifdef PMUCRU_BASE + PMUCRU->CRU_CLKGATE_CON[index - CRU_GATE_CON_CNT] = val; +#else + CRU->PMU_CLKGATE_CON[index - CRU_GATE_CON_CNT] = val; +#endif + } +#else + CRU->CRU_CLKGATE_CON[index] = val; +#endif + + return HAL_OK; +} + +HAL_Check HAL_CRU_ClkIsReset(uint32_t clk) +{ + uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); + uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); + HAL_Check ret; + +#ifdef CRU_SRST_CON_CNT + if (index < CRU_SRST_CON_CNT) { + ret = (HAL_Check)((CRU->CRU_CLKGATE_CON[index] & (1 << shift)) >> shift); + } else { + ret = (HAL_Check)((PMUCRU->CRU_CLKGATE_CON[index - CRU_SRST_CON_CNT] & (1 << shift)) >> shift); + } +#else + ret = (HAL_Check)((CRU->CRU_CLKGATE_CON[index] & (1 << shift)) >> shift); +#endif + + return ret; +} + +HAL_Status HAL_CRU_ClkResetAssert(uint32_t clk) +{ + uint32_t index = CLK_RESET_GET_REG_OFFSET(clk); + uint32_t shift = CLK_RESET_GET_BITS_SHIFT(clk); + + HAL_ASSERT(shift < 16); +#ifdef CRU_SRST_CON_CNT + if (index < CRU_SRST_CON_CNT) { + CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(1U << shift, 1U << shift); + } else { + PMUCRU->CRU_SOFTRST_CON[index - CRU_SRST_CON_CNT] = VAL_MASK_WE(1U << shift, 1U << shift); + } +#else + CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(1U << shift, 1U << shift); +#endif + + return HAL_OK; +} + +HAL_Status HAL_CRU_ClkResetDeassert(uint32_t clk) +{ + uint32_t index = CLK_RESET_GET_REG_OFFSET(clk); + uint32_t shift = CLK_RESET_GET_BITS_SHIFT(clk); + + HAL_ASSERT(shift < 16); +#ifdef CRU_SRST_CON_CNT + if (index < CRU_SRST_CON_CNT) { + CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(1U << shift, 0U << shift); + } else { + PMUCRU->CRU_SOFTRST_CON[index - CRU_SRST_CON_CNT] = VAL_MASK_WE(1U << shift, 0U << shift); + } +#else + CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(1U << shift, 0U << shift); +#endif + + return HAL_OK; +} + +HAL_Status HAL_CRU_ClkResetSyncAssert(int numClks, uint32_t *clks) +{ + uint32_t index = CLK_RESET_GET_REG_OFFSET(clks[0]); + uint32_t val = 0; + int i; + + for (i = 0; i < numClks; i++) { + val |= HAL_BIT(CLK_RESET_GET_BITS_SHIFT(clks[i])); + if (index != CLK_RESET_GET_REG_OFFSET(clks[i])) { + return HAL_ERROR; + } + } + +#ifdef CRU_SRST_CON_CNT + if (index < CRU_SRST_CON_CNT) { + CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(val, val); + } else { + PMUCRU->CRU_SOFTRST_CON[index - CRU_SRST_CON_CNT] = VAL_MASK_WE(val, val); + } +#else + CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(val, val); +#endif + HAL_DBG("%s: index: 0x%lx, val: 0x%lx\n", __func__, index, val); + + return HAL_OK; +} + +HAL_Status HAL_CRU_ClkResetSyncDeassert(int numClks, uint32_t *clks) +{ + uint32_t index = CLK_RESET_GET_REG_OFFSET(clks[0]); + uint32_t val = 0; + int i; + + for (i = 0; i < numClks; i++) { + val |= HAL_BIT(CLK_RESET_GET_BITS_SHIFT(clks[i])); + if (index != CLK_RESET_GET_REG_OFFSET(clks[i])) { + return HAL_ERROR; + } + } + +#ifdef CRU_SRST_CON_CNT + if (index < CRU_SRST_CON_CNT) { + CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(val, 0); + } else { + PMUCRU->CRU_SOFTRST_CON[index - CRU_SRST_CON_CNT] = VAL_MASK_WE(val, 0); + } +#else + CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(val, 0); +#endif + HAL_DBG("%s: index: 0x%lx, val: 0x%lx\n", __func__, index, val); + + return HAL_OK; +} + +HAL_SECTION_SRAM_CODE +HAL_Status HAL_CRU_ClkSetDiv(uint32_t divName, uint32_t divValue) +{ + uint32_t shift, mask, index, maxDiv; + + index = CLK_DIV_GET_REG_OFFSET(divName); + shift = CLK_DIV_GET_BITS_SHIFT(divName); + HAL_ASSERT(shift < 16); + mask = CLK_DIV_GET_MASK(divName); + maxDiv = CLK_DIV_GET_MAXDIV(divName) + 1; + if (divValue > maxDiv) { + divValue = maxDiv; + } + +#ifdef CRU_CLK_DIV_CON_CNT + if (index < CRU_CLK_DIV_CON_CNT) { + CRU->CRU_CLKSEL_CON[index] = VAL_MASK_WE(mask, (divValue - 1U) << shift); + } else { +#ifdef PMUCRU_BASE + PMUCRU->CRU_CLKSEL_CON[index - CRU_CLK_DIV_CON_CNT] = VAL_MASK_WE(mask, (divValue - 1U) << shift); +#else + CRU->PMU_CLKSEL_CON[index - CRU_CLK_DIV_CON_CNT] = VAL_MASK_WE(mask, (divValue - 1U) << shift); +#endif + } +#else + CRU->CRU_CLKSEL_CON[index] = VAL_MASK_WE(mask, (divValue - 1U) << shift); +#endif + + return HAL_OK; +} + +uint32_t HAL_CRU_ClkGetDiv(uint32_t divName) +{ + uint32_t shift, mask, index, divValue; + + index = CLK_DIV_GET_REG_OFFSET(divName); + shift = CLK_DIV_GET_BITS_SHIFT(divName); + HAL_ASSERT(shift < 16); + mask = CLK_DIV_GET_MASK(divName); + +#ifdef CRU_CLK_DIV_CON_CNT + if (index < CRU_CLK_DIV_CON_CNT) { + divValue = ((((CRU->CRU_CLKSEL_CON[index]) & mask) >> shift) + 1); + } else { +#ifdef PMUCRU_BASE + divValue = ((((PMUCRU->CRU_CLKSEL_CON[index - CRU_CLK_DIV_CON_CNT]) & mask) >> shift) + 1); +#else + divValue = ((((CRU->PMU_CLKSEL_CON[index - CRU_CLK_DIV_CON_CNT]) & mask) >> shift) + 1); +#endif + } +#else + divValue = ((((CRU->CRU_CLKSEL_CON[index]) & mask) >> shift) + 1); +#endif + + return divValue; +} + +HAL_SECTION_SRAM_CODE +HAL_Status HAL_CRU_ClkSetMux(uint32_t muxName, uint32_t muxValue) +{ + uint32_t shift, mask, index; + + index = CLK_MUX_GET_REG_OFFSET(muxName); + shift = CLK_MUX_GET_BITS_SHIFT(muxName); + HAL_ASSERT(shift < 16); + mask = CLK_MUX_GET_MASK(muxName); + +#ifdef CRU_CLK_SEL_CON_CNT + if (index < CRU_CLK_DIV_CON_CNT) { + CRU->CRU_CLKSEL_CON[index] = VAL_MASK_WE(mask, muxValue << shift); + } else { +#ifdef PMUCRU_BASE + PMUCRU->CRU_CLKSEL_CON[index - CRU_CLK_SEL_CON_CNT] = VAL_MASK_WE(mask, muxValue << shift); +#else + CRU->PMU_CLKSEL_CON[index - CRU_CLK_SEL_CON_CNT] = VAL_MASK_WE(mask, muxValue << shift); +#endif + } +#else + CRU->CRU_CLKSEL_CON[index] = VAL_MASK_WE(mask, muxValue << shift); +#endif + + return HAL_OK; +} + +HAL_SECTION_SRAM_CODE +uint32_t HAL_CRU_ClkGetMux(uint32_t muxName) +{ + uint32_t shift, mask, index, muxValue; + + index = CLK_MUX_GET_REG_OFFSET(muxName); + shift = CLK_MUX_GET_BITS_SHIFT(muxName); + HAL_ASSERT(shift < 16); + mask = CLK_MUX_GET_MASK(muxName); + +#ifdef CRU_CLK_SEL_CON_CNT + if (index < CRU_CLK_SEL_CON_CNT) { + muxValue = ((CRU->CRU_CLKSEL_CON[index] & mask) >> shift); + } else { +#ifdef PMUCRU_BASE + muxValue = ((PMUCRU->CRU_CLKSEL_CON[index - CRU_CLK_SEL_CON_CNT] & mask) >> shift); +#else + muxValue = ((CRU->PMU_CLKSEL_CON[index - CRU_CLK_SEL_CON_CNT] & mask) >> shift); +#endif + } +#else + muxValue = ((CRU->CRU_CLKSEL_CON[index] & mask) >> shift); +#endif + + return muxValue; +} + +HAL_Status HAL_CRU_ClkSetFracDiv(uint32_t fracDivName, + uint32_t numerator, + uint32_t denominator) +{ + uint32_t index; + + index = CLK_DIV_GET_REG_OFFSET(fracDivName); +#ifdef CRU_CLK_DIV_CON_CNT + if (index < CRU_CLK_DIV_CON_CNT) { + CRU->CRU_CLKSEL_CON[index] = (numerator << 16) | denominator; + } else { +#ifdef PMUCRU_BASE + PMUCRU->CRU_CLKSEL_CON[index - CRU_CLK_DIV_CON_CNT] = (numerator << 16) | denominator; +#else + CRU->PMU_CLKSEL_CON[index - CRU_CLK_DIV_CON_CNT] = (numerator << 16) | denominator; +#endif + } +#else + CRU->CRU_CLKSEL_CON[index] = (numerator << 16) | denominator; +#endif + + return HAL_OK; +} + +HAL_Status HAL_CRU_ClkGetFracDiv(uint32_t fracDivName, + uint32_t *numerator, + uint32_t *denominator) +{ + uint32_t index; + uint32_t val; + + index = CLK_DIV_GET_REG_OFFSET(fracDivName); +#ifdef CRU_CLK_DIV_CON_CNT + if (index < CRU_CLK_DIV_CON_CNT) { + val = CRU->CRU_CLKSEL_CON[index]; + } else { +#ifdef PMUCRU_BASE + val = PMUCRU->CRU_CLKSEL_CON[index - CRU_CLK_DIV_CON_CNT]; +#else + val = CRU->CRU_CLKSEL_CON[index - CRU_CLK_DIV_CON_CNT]; +#endif + } +#else + val = CRU->CRU_CLKSEL_CON[index]; +#endif + + *numerator = (val & 0xffff0000) >> 16; + *denominator = (val & 0x0000ffff); + + return HAL_OK; +} +#endif /* CRU_CLK_USE_CON_BANK */ + +HAL_Status HAL_CRU_FracdivGetConfig(uint32_t rateOut, uint32_t rate, + uint32_t *numerator, + uint32_t *denominator) +{ + uint32_t gcdVal; + + gcdVal = CRU_Gcd(rate, rateOut); + if (!gcdVal) { + return HAL_ERROR; + } + + *numerator = rateOut / gcdVal; + *denominator = rate / gcdVal; + + if (*numerator < 4) { + *numerator *= 4; + *denominator *= 4; + } + if (*numerator > 0xffff || *denominator > 0xffff) { + return HAL_INVAL; + } + + return HAL_OK; +} + +HAL_Status HAL_CRU_FracdivGetConfigV2(uint32_t rateOut, uint32_t rate, + uint32_t *numerator, + uint32_t *denominator) +{ + uint32_t gcdVal; + + gcdVal = CRU_Gcd(rate, rateOut); + if (!gcdVal) { + return HAL_ERROR; + } + + *numerator = rateOut / gcdVal; + *denominator = rate / gcdVal; + + if (*numerator < 4) { + *numerator *= 4; + *denominator *= 4; + } + if (*numerator > 0xffffff || *denominator > 0xffffff) { + return HAL_INVAL; + } + + return HAL_OK; +} + +HAL_Status HAL_CRU_ClkNp5BestDiv(eCLOCK_Name clockName, uint32_t rate, uint32_t pRate, uint32_t *bestdiv) +{ + uint32_t div = CLK_GET_DIV(clockName); + uint32_t maxDiv = CLK_DIV_GET_MASK(div); + uint32_t i; + + for (i = 0; i < maxDiv; i++) { + if (((pRate * 2) == (rate * (i * 2 + 3)))) { + *bestdiv = i; + + return HAL_OK; + } + } + + return HAL_ERROR; +} + +__attribute__((weak)) HAL_Status HAL_CRU_VopDclkEnable(uint32_t gateId) +{ + HAL_CRU_ClkEnable(gateId); + + return HAL_OK; +} + +__attribute__((weak)) HAL_Status HAL_CRU_VopDclkDisable(uint32_t gateId) +{ + HAL_CRU_ClkDisable(gateId); + + return HAL_OK; +} + +HAL_Status HAL_CRU_SetGlbSrst(eCRU_GlbSrstType type) +{ +#ifdef CRU_GLB_SRST_FST_VALUE_OFFSET + if (type == GLB_SRST_FST) { + CRU->GLB_SRST_FST_VALUE = GLB_SRST_FST; + } +#endif +#ifdef CRU_GLB_SRST_SND_VALUE_OFFSET + if (type == GLB_SRST_SND) { + CRU->GLB_SRST_SND_VALUE = GLB_SRST_SND; + } +#endif + + return HAL_INVAL; +} + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_CRU_MODULE_ENABLED */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_cru_rk3568.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_cru_rk3568.c new file mode 100644 index 000000000..fc850a03d --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_cru_rk3568.c @@ -0,0 +1,1113 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#if defined(SOC_RK3568) && defined(HAL_CRU_MODULE_ENABLED) + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup CRU + * @{ + */ + +/** @defgroup CRU_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ +/********************* Private Structure Definition **************************/ + +static struct PLL_CONFIG PLL_TABLE[] = { + /* _mhz, _refDiv, _fbDiv, _postdDv1, _postDiv2, _dsmpd, _frac */ + RK_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), + RK_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0), + RK_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0), + RK_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), + RK_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), + RK_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0), + RK_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), + RK_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0), + { /* sentinel */ }, +}; + +static struct PLL_SETUP APLL = { + .conOffset0 = &(CRU->APLL_CON[0]), + .conOffset1 = &(CRU->APLL_CON[1]), + .conOffset2 = &(CRU->APLL_CON[2]), + .conOffset3 = &(CRU->APLL_CON[3]), + .modeOffset = &(CRU->MODE_CON00), + .modeShift = 0, + .lockShift = 10, + .modeMask = 0x3, + .rateTable = PLL_TABLE, +}; + +static struct PLL_SETUP CPLL = { + .conOffset0 = &(CRU->CPLL_CON[0]), + .conOffset1 = &(CRU->CPLL_CON[1]), + .conOffset2 = &(CRU->CPLL_CON[2]), + .conOffset3 = &(CRU->CPLL_CON[3]), + .modeOffset = &(CRU->MODE_CON00), + .modeShift = 4, + .lockShift = 10, + .modeMask = 0x3 << 4, + .rateTable = PLL_TABLE, +}; + +HAL_UNUSED static struct PLL_SETUP GPLL = { + .conOffset0 = &(CRU->GPLL_CON[0]), + .conOffset1 = &(CRU->GPLL_CON[1]), + .conOffset2 = &(CRU->GPLL_CON[2]), + .conOffset3 = &(CRU->GPLL_CON[3]), + .modeOffset = &(CRU->MODE_CON00), + .modeShift = 6, + .lockShift = 10, + .modeMask = 0x3 << 6, + .rateTable = PLL_TABLE, +}; + +static struct PLL_SETUP NPLL = { + .conOffset0 = &(CRU->NPLL_CON[0]), + .conOffset1 = &(CRU->NPLL_CON[1]), + .modeOffset = &(CRU->MODE_CON00), + .modeShift = 10, + .lockShift = 10, + .modeMask = 0x3 << 10, + .rateTable = PLL_TABLE, +}; + +static struct PLL_SETUP VPLL = { + .conOffset0 = &(CRU->VPLL_CON[0]), + .conOffset1 = &(CRU->VPLL_CON[1]), + .modeOffset = &(CRU->MODE_CON00), + .modeShift = 12, + .lockShift = 10, + .modeMask = 0x3 << 12, + .rateTable = PLL_TABLE, +}; + +static struct PLL_SETUP PPLL = { + .conOffset0 = &(PMUCRU->PPLL_CON[0]), + .conOffset1 = &(PMUCRU->PPLL_CON[1]), + .conOffset2 = &(PMUCRU->PPLL_CON[2]), + .conOffset3 = &(PMUCRU->PPLL_CON[3]), + .modeOffset = &(PMUCRU->MODE_CON00), + .modeShift = 0, + .lockShift = 10, + .modeMask = 0x3 << 0, + .rateTable = PLL_TABLE, +}; + +static struct PLL_SETUP HPLL = { + .conOffset0 = &(PMUCRU->HPLL_CON[0]), + .conOffset1 = &(PMUCRU->HPLL_CON[1]), + .conOffset2 = &(PMUCRU->HPLL_CON[2]), + .conOffset3 = &(PMUCRU->HPLL_CON[3]), + .modeOffset = &(PMUCRU->MODE_CON00), + .modeShift = 2, + .lockShift = 10, + .modeMask = 0x3 << 2, + .rateTable = PLL_TABLE, +}; + +/********************* Private Variable Definition ***************************/ + +static uint32_t s_apllFreq; +static uint32_t s_cpllFreq; +static uint32_t s_gpllFreq = 1188 * 1000 * 1000; +static uint32_t s_npllFreq; +static uint32_t s_vpllFreq; +static uint32_t s_ppllFreq; +static uint32_t s_hpllFreq; +static uint32_t s_clk_gmac_xpcs_mii; +static uint32_t s_clk_gmac_in; + +/********************* Private Function Definition ***************************/ + +/** @} */ +/********************* Public Function Definition ****************************/ + +/** @defgroup CRU_Exported_Functions_Group5 Other Functions + * @{ + */ + +/** + * @brief Get frac clk freq. + * @param clockName: CLOCK_Name id + * @return clk rate. + * How to calculate the Frac clk divider: + * numerator is frac register[31:16] + * denominator is frac register[15:0] + * clk rate = pRate * numerator / denominator + * for a better jitter, pRate > 20 * rate + */ +static uint32_t HAL_CRU_ClkFracGetFreq(eCLOCK_Name clockName) +{ + uint32_t freq = 0; + uint32_t muxSrc = 0, mux = CLK_GET_MUX(clockName); + uint32_t divSrc = 0, divFrac = 0; + uint32_t n, m, pRate; + + if (clockName == CLK_UART0) { + n = (PMUCRU->CRU_CLKSEL_CON[5] & 0xffff0000) >> 16; + m = PMUCRU->CRU_CLKSEL_CON[5] & 0x0000ffff; + muxSrc = (PMUCRU->CRU_CLKSEL_CON[4] & 0x0300) >> 8; + divSrc = PMUCRU->CRU_CLKSEL_CON[4] & 0x003f; + + switch (muxSrc) { + case 0: + pRate = s_ppllFreq / (divSrc + 1); + break; + case 1: + pRate = 480000000 / (divSrc + 1); + break; + case 2: + pRate = s_cpllFreq / (divSrc + 1); + break; + case 3: + pRate = s_gpllFreq / (divSrc + 1); + break; + default: + + return 0; + } + muxSrc = (PMUCRU->CRU_CLKSEL_CON[4] & 0x0c00) >> 10; + switch (muxSrc) { + case 0: + freq = pRate; + break; + case 1: + freq = (pRate / m) * n; + break; + case 2: + freq = PLL_INPUT_OSC_RATE; + break; + default: + + return 0; + } + + return freq; + } + + switch (clockName) { + case CLK_UART1: + muxSrc = CLK_GET_MUX(CLK_UART1_SRC); + divSrc = CLK_GET_DIV(CLK_UART1_SRC); + divFrac = CLK_GET_DIV(CLK_UART1_FRAC); + break; + case CLK_UART2: + muxSrc = CLK_GET_MUX(CLK_UART2_SRC); + divSrc = CLK_GET_DIV(CLK_UART2_SRC); + divFrac = CLK_GET_DIV(CLK_UART2_FRAC); + break; + case CLK_UART3: + muxSrc = CLK_GET_MUX(CLK_UART3_SRC); + divSrc = CLK_GET_DIV(CLK_UART3_SRC); + divFrac = CLK_GET_DIV(CLK_UART3_FRAC); + break; + case CLK_UART4: + muxSrc = CLK_GET_MUX(CLK_UART4_SRC); + divSrc = CLK_GET_DIV(CLK_UART4_SRC); + divFrac = CLK_GET_DIV(CLK_UART4_FRAC); + break; + case CLK_UART5: + muxSrc = CLK_GET_MUX(CLK_UART5_SRC); + divSrc = CLK_GET_DIV(CLK_UART5_SRC); + divFrac = CLK_GET_DIV(CLK_UART5_FRAC); + break; + case CLK_UART6: + muxSrc = CLK_GET_MUX(CLK_UART6_SRC); + divSrc = CLK_GET_DIV(CLK_UART6_SRC); + divFrac = CLK_GET_DIV(CLK_UART6_FRAC); + break; + case CLK_UART7: + muxSrc = CLK_GET_MUX(CLK_UART7_SRC); + divSrc = CLK_GET_DIV(CLK_UART7_SRC); + divFrac = CLK_GET_DIV(CLK_UART7_FRAC); + break; + case CLK_UART8: + muxSrc = CLK_GET_MUX(CLK_UART8_SRC); + divSrc = CLK_GET_DIV(CLK_UART8_SRC); + divFrac = CLK_GET_DIV(CLK_UART8_FRAC); + break; + case CLK_UART9: + muxSrc = CLK_GET_MUX(CLK_UART9_SRC); + divSrc = CLK_GET_DIV(CLK_UART9_SRC); + divFrac = CLK_GET_DIV(CLK_UART9_FRAC); + break; + default: + + return 0; + } + + n = (CRU->CRU_CLKSEL_CON[CLK_DIV_GET_REG_OFFSET(divFrac)] & 0xffff0000) >> 16; + m = CRU->CRU_CLKSEL_CON[CLK_DIV_GET_REG_OFFSET(divFrac)] & 0x0000ffff; + + if (HAL_CRU_ClkGetMux(muxSrc)) { + pRate = s_cpllFreq / HAL_CRU_ClkGetDiv(divSrc); + } else { + pRate = s_gpllFreq / HAL_CRU_ClkGetDiv(divSrc); + } + + if (HAL_CRU_ClkGetMux(mux) == 0) { + freq = pRate; + } else if (HAL_CRU_ClkGetMux(mux) == 1) { + freq = (pRate / m) * n; + } else if (HAL_CRU_ClkGetMux(mux) == 2) { + freq = PLL_INPUT_OSC_RATE; + } + + return freq; +} + +/** + * @brief Set frac clk freq. + * @param clockName: CLOCK_Name id. + * @param rate: clk set rate + * @return HAL_Status. + * How to calculate the Frac clk divider: + * if pRate > 20 * rate, select frac divider + * else select normal divider, but the clk rate may be not accurate + */ +static HAL_Status HAL_CRU_ClkFracSetFreq(eCLOCK_Name clockName, uint32_t rate) +{ + uint32_t muxSrc, mux = CLK_GET_MUX(clockName); + uint32_t divSrc, divFrac; + uint32_t n = 0, m = 0; + uint32_t gateId, fracGateId; + + if (clockName == CLK_UART0) { + if (PLL_INPUT_OSC_RATE == rate) { + PMUCRU->CRU_CLKSEL_CON[4] = 0x0cff0800; + } else if ((!(s_gpllFreq % rate)) && ((s_gpllFreq / rate) < 31)) { + divSrc = (s_gpllFreq / rate) - 1; + PMUCRU->CRU_CLKSEL_CON[4] = 0x003f0000 | divSrc; + PMUCRU->CRU_CLKSEL_CON[4] = 0x0f000300; + } else if ((!(s_cpllFreq % rate)) && ((s_cpllFreq / rate) < 31)) { + divSrc = (s_cpllFreq / rate) - 1; + PMUCRU->CRU_CLKSEL_CON[4] = 0x003f0000 | divSrc; + PMUCRU->CRU_CLKSEL_CON[4] = 0x0f000200; + } else { + HAL_CRU_FracdivGetConfig(rate, s_gpllFreq, &n, &m); + PMUCRU->CRU_CLKSEL_CON[5] = (n << 16) | m; + PMUCRU->CRU_CLKSEL_CON[4] = 0x0fff0700; + } + + return HAL_OK; + } + + switch (clockName) { + case CLK_UART1: + muxSrc = CLK_GET_MUX(CLK_UART1_SRC); + divSrc = CLK_GET_DIV(CLK_UART1_SRC); + divFrac = CLK_GET_DIV(CLK_UART1_FRAC); + gateId = CLK_UART1_GATE; + fracGateId = CLK_UART1_FRAC_GATE; + break; + case CLK_UART2: + muxSrc = CLK_GET_MUX(CLK_UART2_SRC); + divSrc = CLK_GET_DIV(CLK_UART2_SRC); + divFrac = CLK_GET_DIV(CLK_UART2_FRAC); + gateId = CLK_UART2_GATE; + fracGateId = CLK_UART2_FRAC_GATE; + break; + case CLK_UART3: + muxSrc = CLK_GET_MUX(CLK_UART3_SRC); + divSrc = CLK_GET_DIV(CLK_UART3_SRC); + divFrac = CLK_GET_DIV(CLK_UART3_FRAC); + gateId = CLK_UART3_GATE; + fracGateId = CLK_UART3_FRAC_GATE; + break; + case CLK_UART4: + muxSrc = CLK_GET_MUX(CLK_UART4_SRC); + divSrc = CLK_GET_DIV(CLK_UART4_SRC); + divFrac = CLK_GET_DIV(CLK_UART4_FRAC); + gateId = CLK_UART4_GATE; + fracGateId = CLK_UART4_FRAC_GATE; + break; + case CLK_UART5: + muxSrc = CLK_GET_MUX(CLK_UART5_SRC); + divSrc = CLK_GET_DIV(CLK_UART5_SRC); + divFrac = CLK_GET_DIV(CLK_UART5_FRAC); + gateId = CLK_UART5_GATE; + fracGateId = CLK_UART5_FRAC_GATE; + break; + case CLK_UART6: + muxSrc = CLK_GET_MUX(CLK_UART6_SRC); + divSrc = CLK_GET_DIV(CLK_UART6_SRC); + divFrac = CLK_GET_DIV(CLK_UART6_FRAC); + gateId = CLK_UART6_GATE; + fracGateId = CLK_UART6_FRAC_GATE; + break; + case CLK_UART7: + muxSrc = CLK_GET_MUX(CLK_UART7_SRC); + divSrc = CLK_GET_DIV(CLK_UART7_SRC); + divFrac = CLK_GET_DIV(CLK_UART7_FRAC); + gateId = CLK_UART7_GATE; + fracGateId = CLK_UART7_FRAC_GATE; + break; + case CLK_UART8: + muxSrc = CLK_GET_MUX(CLK_UART8_SRC); + divSrc = CLK_GET_DIV(CLK_UART8_SRC); + divFrac = CLK_GET_DIV(CLK_UART8_FRAC); + gateId = CLK_UART8_GATE; + fracGateId = CLK_UART8_FRAC_GATE; + break; + case CLK_UART9: + muxSrc = CLK_GET_MUX(CLK_UART9_SRC); + divSrc = CLK_GET_DIV(CLK_UART9_SRC); + divFrac = CLK_GET_DIV(CLK_UART9_FRAC); + gateId = CLK_UART9_GATE; + fracGateId = CLK_UART9_FRAC_GATE; + break; + default: + + return HAL_INVAL; + } + + HAL_CRU_ClkEnable(gateId); + HAL_CRU_ClkEnable(fracGateId); + if (PLL_INPUT_OSC_RATE == rate) { + HAL_CRU_ClkSetMux(mux, 2); + HAL_CRU_ClkDisable(gateId); + } else if ((!(s_gpllFreq % rate)) && ((s_gpllFreq / rate) < 31)) { + HAL_CRU_ClkSetDiv(divSrc, s_gpllFreq / rate); + HAL_CRU_ClkSetMux(muxSrc, 0); + HAL_CRU_ClkSetMux(mux, 0); + HAL_CRU_ClkDisable(fracGateId); + } else if ((!(s_cpllFreq % rate)) && ((s_cpllFreq / rate) < 31)) { + HAL_CRU_ClkSetDiv(divSrc, s_cpllFreq / rate); + HAL_CRU_ClkSetMux(muxSrc, 1); + HAL_CRU_ClkSetMux(mux, 0); + HAL_CRU_ClkDisable(fracGateId); + } else { + HAL_CRU_FracdivGetConfig(rate, s_gpllFreq, &n, &m); + HAL_CRU_ClkSetDiv(divSrc, 1); + HAL_CRU_ClkSetMux(muxSrc, 0); + CRU->CRU_CLKSEL_CON[CLK_DIV_GET_REG_OFFSET(divFrac)] = (n << 16) | m; + HAL_CRU_ClkSetMux(mux, 1); + } + + return HAL_OK; +} + +/** + * @brief Get gmac clk freq. + * @param clockName: CLOCK_Name id + * @return clk rate. + */ +static uint32_t HAL_CRU_ClkGmacGetFreq(eCLOCK_Name clockName) +{ + uint32_t clkMux = CLK_GET_MUX(clockName); + uint32_t clkDiv = CLK_GET_DIV(clockName); + uint32_t freq; + + switch (clockName) { + case ACLK_PHP: + case ACLK_USB: + if (HAL_CRU_ClkGetMux(clkMux) == 0) { + freq = 297000000; + } else if (HAL_CRU_ClkGetMux(clkMux) == 1) { + freq = 198000000; + } else if (HAL_CRU_ClkGetMux(clkMux) == 2) { + freq = 99000000; + } else { + freq = PLL_INPUT_OSC_RATE; + } + + return freq; + case HCLK_PHP: + case HCLK_USB: + if (HAL_CRU_ClkGetMux(clkMux) == 0) { + freq = 148500000; + } else if (HAL_CRU_ClkGetMux(clkMux) == 1) { + freq = 99000000; + } else if (HAL_CRU_ClkGetMux(clkMux) == 2) { + freq = 74250000; + } else { + freq = PLL_INPUT_OSC_RATE; + } + + return freq; + case PCLK_PHP: + freq = HAL_CRU_ClkGmacGetFreq(ACLK_PHP) / (HAL_CRU_ClkGetDiv(clkDiv)); + + return freq; + case PCLK_USB: + freq = HAL_CRU_ClkGmacGetFreq(ACLK_USB) / (HAL_CRU_ClkGetDiv(clkDiv)); + + return freq; + case CLK_MAC0_2TOP: + case CLK_MAC1_2TOP: + if (HAL_CRU_ClkGetMux(clkMux) == 0) { + freq = 125000000; + } else if (HAL_CRU_ClkGetMux(clkMux) == 1) { + freq = 50000000; + } else if (HAL_CRU_ClkGetMux(clkMux) == 2) { + freq = 25000000; + } else { + freq = HAL_CRU_ClkGetFreq(PLL_PPLL); + } + + return freq; + + case CLK_MAC0_OUT: + case CLK_MAC1_OUT: + if (HAL_CRU_ClkGetMux(clkMux) == 0) { + freq = 125000000; + } else if (HAL_CRU_ClkGetMux(clkMux) == 1) { + freq = 50000000; + } else if (HAL_CRU_ClkGetMux(clkMux) == 2) { + freq = 25000000; + } else { + freq = PLL_INPUT_OSC_RATE; + } + + return freq; + + case CLK_GMAC0_PTP_REF: + case CLK_GMAC1_PTP_REF: + if (HAL_CRU_ClkGetMux(clkMux) == 0) { + freq = 62500; + } else if (HAL_CRU_ClkGetMux(clkMux) == 1) { + freq = 100000000; + } else if (HAL_CRU_ClkGetMux(clkMux) == 2) { + freq = 50000000; + } else { + freq = PLL_INPUT_OSC_RATE; + } + + return freq; + + case SCLK_GMAC0_RGMII_SPEED: + if (HAL_CRU_ClkGetMux(clkMux) == 0) { + freq = HAL_CRU_ClkGetFreq(CLK_MAC0_2TOP); + } else if (HAL_CRU_ClkGetMux(clkMux) == 1) { + freq = HAL_CRU_ClkGetFreq(CLK_MAC0_2TOP); + } else if (HAL_CRU_ClkGetMux(clkMux) == 2) { + freq = HAL_CRU_ClkGetFreq(CLK_MAC0_2TOP) / 50; + } else { + freq = HAL_CRU_ClkGetFreq(CLK_MAC0_2TOP) / 5; + } + + return freq; + + case SCLK_GMAC1_RGMII_SPEED: + if (HAL_CRU_ClkGetMux(clkMux) == 0) { + freq = HAL_CRU_ClkGetFreq(CLK_MAC1_2TOP); + } else if (HAL_CRU_ClkGetMux(clkMux) == 1) { + freq = HAL_CRU_ClkGetFreq(CLK_MAC1_2TOP); + } else if (HAL_CRU_ClkGetMux(clkMux) == 2) { + freq = HAL_CRU_ClkGetFreq(CLK_MAC1_2TOP) / 50; + } else { + freq = HAL_CRU_ClkGetFreq(CLK_MAC1_2TOP) / 5; + } + + return freq; + + case SCLK_GMAC0_RMII_SPEED: + if (HAL_CRU_ClkGetMux(clkMux)) { + freq = HAL_CRU_ClkGetFreq(CLK_MAC0_2TOP) / 2; + } else { + freq = HAL_CRU_ClkGetFreq(CLK_MAC0_2TOP) / 20; + } + + return freq; + + case SCLK_GMAC1_RMII_SPEED: + if (HAL_CRU_ClkGetMux(clkMux)) { + freq = HAL_CRU_ClkGetFreq(CLK_MAC1_2TOP) / 2; + } else { + freq = HAL_CRU_ClkGetFreq(CLK_MAC1_2TOP) / 20; + } + + return freq; + case SCLK_GMAC0: + if (HAL_CRU_ClkGetMux(clkMux) == 0) { + freq = HAL_CRU_ClkGetFreq(CLK_MAC0_2TOP); + } else { + freq = s_clk_gmac_in; + } + + return freq; + + case SCLK_GMAC1: + if (HAL_CRU_ClkGetMux(clkMux) == 0) { + freq = HAL_CRU_ClkGetFreq(CLK_MAC1_2TOP); + } else { + freq = s_clk_gmac_in; + } + + return freq; + + case SCLK_GMAC0_RX_TX: + if (HAL_CRU_ClkGetMux(clkMux) == 0) { + freq = HAL_CRU_ClkGetFreq(SCLK_GMAC0_RGMII_SPEED); + } else if (HAL_CRU_ClkGetMux(clkMux) == 1) { + freq = HAL_CRU_ClkGetFreq(SCLK_GMAC0_RMII_SPEED); + } else { + freq = s_clk_gmac_xpcs_mii; + } + + return freq; + case SCLK_GMAC1_RX_TX: + if (HAL_CRU_ClkGetMux(clkMux) == 0) { + freq = HAL_CRU_ClkGetFreq(SCLK_GMAC1_RGMII_SPEED); + } else if (HAL_CRU_ClkGetMux(clkMux) == 1) { + freq = HAL_CRU_ClkGetFreq(SCLK_GMAC1_RMII_SPEED); + } else { + freq = s_clk_gmac_xpcs_mii; + } + + return freq; + default: + + return 0; + } +} + +/** + * @brief Set gmac clk freq. + * @param clockName: CLOCK_Name id. + * @param rate: clk set rate + * @return HAL_Status. + */ +static HAL_Status HAL_CRU_ClkGmacSetFreq(eCLOCK_Name clockName, uint32_t rate) +{ + uint32_t clkMux = CLK_GET_MUX(clockName); + uint32_t clkDiv = CLK_GET_DIV(clockName); + uint32_t mux = 0, div = 0; + + switch (clockName) { + case ACLK_PHP: + case ACLK_USB: + if (rate >= 297000000) { + mux = 0; + } else if (rate >= 198000000) { + mux = 1; + } else if (rate >= 99000000) { + mux = 2; + } else { + mux = 3; + } + break; + case HCLK_PHP: + case HCLK_USB: + if (rate >= 148500000) { + mux = 0; + } else if (rate >= 99000000) { + mux = 1; + } else if (rate >= 74250000) { + mux = 2; + } else { + mux = 3; + } + break; + case PCLK_PHP: + div = HAL_DIV_ROUND_UP(HAL_CRU_ClkGmacGetFreq(ACLK_PHP), rate); + + break; + case PCLK_USB: + div = HAL_DIV_ROUND_UP(HAL_CRU_ClkGmacGetFreq(ACLK_USB), rate); + + break; + + case CLK_MAC0_2TOP: + case CLK_MAC1_2TOP: + case CLK_MAC0_OUT: + case CLK_MAC1_OUT: + if (rate == 125000000) { + mux = 0; + } else if (rate == 50000000) { + mux = 1; + } else if (rate == 25000000) { + mux = 2; + } else { + mux = 3; + } + + break; + + case CLK_GMAC0_PTP_REF: + case CLK_GMAC1_PTP_REF: + if (rate == 62500) { + mux = 0; + } else if (rate == 100000000) { + mux = 1; + } else if (rate == 50000000) { + mux = 2; + } else { + mux = 3; + } + + break; + + case SCLK_GMAC0_RGMII_SPEED: + if (rate == HAL_CRU_ClkGetFreq(CLK_MAC0_2TOP) / 50) { + mux = 2; + } else if (rate == HAL_CRU_ClkGetFreq(CLK_MAC0_2TOP) / 5) { + mux = 3; + } else { + mux = 0; + } + break; + + case SCLK_GMAC1_RGMII_SPEED: + if (rate == HAL_CRU_ClkGetFreq(CLK_MAC1_2TOP) / 50) { + mux = 2; + } else if (rate == HAL_CRU_ClkGetFreq(CLK_MAC1_2TOP) / 5) { + mux = 3; + } else { + mux = 0; + } + break; + + case SCLK_GMAC0_RMII_SPEED: + if (rate == HAL_CRU_ClkGetFreq(CLK_MAC0_2TOP) / 2) { + mux = 1; + } else { + mux = 0; + } + break; + + case SCLK_GMAC1_RMII_SPEED: + if (rate == HAL_CRU_ClkGetFreq(CLK_MAC1_2TOP) / 2) { + mux = 1; + } else { + mux = 0; + } + break; + case SCLK_GMAC0: + if (rate == HAL_CRU_ClkGetFreq(CLK_MAC0_2TOP)) { + mux = 0; + } else { + mux = 1; + } + break; + + case SCLK_GMAC1: + if (rate == HAL_CRU_ClkGetFreq(CLK_MAC1_2TOP)) { + mux = 0; + } else { + mux = 1; + } + break; + + case SCLK_GMAC0_RX_TX: + if (rate == HAL_CRU_ClkGetFreq(SCLK_GMAC0_RGMII_SPEED)) { + mux = 0; + } else if (rate == HAL_CRU_ClkGetFreq(SCLK_GMAC0_RMII_SPEED)) { + mux = 1; + } else { + mux = 2; + } + break; + case SCLK_GMAC1_RX_TX: + if (rate == HAL_CRU_ClkGetFreq(SCLK_GMAC1_RGMII_SPEED)) { + mux = 0; + } else if (rate == HAL_CRU_ClkGetFreq(SCLK_GMAC1_RMII_SPEED)) { + mux = 1; + } else { + mux = 2; + } + break; + default: + + return HAL_INVAL; + } + + if (clkMux) { + HAL_CRU_ClkSetMux(clkMux, mux); + } + if (clkDiv) { + HAL_CRU_ClkSetDiv(clkDiv, div); + } + + return HAL_OK; +} + +/** + * @brief Get clk freq. + * @param clockName: CLOCK_Name id. + * @return rate. + * @attention these APIs allow direct use in the HAL layer. + */ +uint32_t HAL_CRU_ClkGetFreq(eCLOCK_Name clockName) +{ + uint32_t clkMux = CLK_GET_MUX(clockName); + uint32_t clkDiv = CLK_GET_DIV(clockName); + uint32_t pRate = 0, freq; + + if (!s_cpllFreq) { + s_cpllFreq = HAL_CRU_GetPllFreq(&CPLL); + } + + switch (clockName) { + case PLL_APLL: + freq = HAL_CRU_GetPllFreq(&APLL); + s_apllFreq = freq; + + return freq; + case PLL_CPLL: + freq = HAL_CRU_GetPllFreq(&CPLL); + s_cpllFreq = freq; + + return freq; + case PLL_NPLL: + freq = HAL_CRU_GetPllFreq(&NPLL); + s_npllFreq = freq; + + return freq; + case PLL_VPLL: + freq = HAL_CRU_GetPllFreq(&VPLL); + s_vpllFreq = freq; + + return freq; + case PLL_HPLL: + freq = HAL_CRU_GetPllFreq(&HPLL); + s_hpllFreq = freq; + + return freq; + case PLL_PPLL: + freq = HAL_CRU_GetPllFreq(&PPLL); + s_ppllFreq = freq; + + return freq; + case PLL_GPLL: + + return s_gpllFreq; + case CLK_WDT: + + return PLL_INPUT_OSC_RATE; + case CLK_I2C: + if (HAL_CRU_ClkGetMux(clkMux) == 0) { + freq = s_gpllFreq / 6; + } else if (HAL_CRU_ClkGetMux(clkMux) == 1) { + freq = s_gpllFreq / 12; + } else if (HAL_CRU_ClkGetMux(clkMux) == 2) { + freq = PLL_INPUT_OSC_RATE; + } else { + freq = s_cpllFreq / 10; + } + + return freq; + case CLK_PWM1: + case CLK_PWM2: + case CLK_PWM3: + if (HAL_CRU_ClkGetMux(clkMux) == 0) { + freq = s_gpllFreq / 12; + } else if (HAL_CRU_ClkGetMux(clkMux) == 1) { + freq = PLL_INPUT_OSC_RATE; + } else { + freq = s_cpllFreq / 10; + } + + return freq; + case CLK_SPI0: + case CLK_SPI1: + case CLK_SPI2: + case CLK_SPI3: + if (HAL_CRU_ClkGetMux(clkMux) == 0) { + freq = s_gpllFreq / 6; + } else if (HAL_CRU_ClkGetMux(clkMux) == 1) { + freq = PLL_INPUT_OSC_RATE; + } else { + freq = s_cpllFreq / 10; + } + + return freq; + case CLK_UART0: + case CLK_UART1: + case CLK_UART2: + case CLK_UART3: + case CLK_UART4: + case CLK_UART5: + case CLK_UART6: + case CLK_UART7: + case CLK_UART8: + case CLK_UART9: + freq = HAL_CRU_ClkFracGetFreq(clockName); + + return freq; + case CLK_CAN0: + case CLK_CAN1: + case CLK_CAN2: + if (HAL_CRU_ClkGetMux(clkMux)) { + pRate = s_cpllFreq; + } else { + pRate = s_gpllFreq; + } + + break; + + case CLK_TSADC_TSEN: + if (HAL_CRU_ClkGetMux(clkMux)) { + pRate = s_gpllFreq / 12; + } else { + pRate = PLL_INPUT_OSC_RATE; + } + + break; + case CLK_TSADC: + pRate = HAL_CRU_ClkGetFreq(CLK_TSADC_TSEN); + + break; + + case SCLK_SFC: + if (HAL_CRU_ClkGetMux(clkMux) == 1) { + freq = 50000000; + } else if (HAL_CRU_ClkGetMux(clkMux) == 2) { + freq = 75000000; + } else if (HAL_CRU_ClkGetMux(clkMux) == 3) { + freq = 100000000; + } else if (HAL_CRU_ClkGetMux(clkMux) == 4) { + freq = 125000000; + } else if (HAL_CRU_ClkGetMux(clkMux) == 5) { + freq = 150000000; + } else { + freq = PLL_INPUT_OSC_RATE; + } + + return freq; + case CLK_SDMMC0: + if (HAL_CRU_ClkGetMux(clkMux) == 1) { + freq = 400000000; + } else if (HAL_CRU_ClkGetMux(clkMux) == 2) { + freq = 300000000; + } else if (HAL_CRU_ClkGetMux(clkMux) == 3) { + freq = 100000000; + } else if (HAL_CRU_ClkGetMux(clkMux) == 4) { + freq = 50000000; + } else if (HAL_CRU_ClkGetMux(clkMux) == 5) { + freq = 750000; + } else { + freq = PLL_INPUT_OSC_RATE; + } + + return freq; + + case ACLK_USB: + case HCLK_USB: + case PCLK_USB: + case ACLK_PHP: + case HCLK_PHP: + case PCLK_PHP: + case CLK_MAC0_2TOP: + case CLK_MAC1_2TOP: + case CLK_MAC0_OUT: + case CLK_MAC1_OUT: + case CLK_GMAC0_PTP_REF: + case CLK_GMAC1_PTP_REF: + case SCLK_GMAC0_RGMII_SPEED: + case SCLK_GMAC1_RGMII_SPEED: + case SCLK_GMAC0_RMII_SPEED: + case SCLK_GMAC1_RMII_SPEED: + case SCLK_GMAC0_RX_TX: + case SCLK_GMAC1_RX_TX: + freq = HAL_CRU_ClkGmacGetFreq(clockName); + + return freq; + default: + break; + } + + if ((clkMux == 0) && (clkDiv == 0)) { + return 0; + } + + if (clkDiv) { + freq = pRate / (HAL_CRU_ClkGetDiv(clkDiv)); + } else { + freq = pRate; + } + + return freq; +} + +/** + * @brief Set clk freq. + * @param clockName: CLOCK_Name id. + * @param rate: clk rate. + * @return HAL_Status. + * @attention these APIs allow direct use in the HAL layer. + */ +HAL_Status HAL_CRU_ClkSetFreq(eCLOCK_Name clockName, uint32_t rate) +{ + HAL_Status error = HAL_OK; + uint32_t clkMux = CLK_GET_MUX(clockName); + uint32_t clkDiv = CLK_GET_DIV(clockName); + uint32_t mux = 0, div = 0, pRate = 0; + + if (!s_cpllFreq) { + s_cpllFreq = HAL_CRU_GetPllFreq(&CPLL); + } + + switch (clockName) { + case PLL_APLL: + + return error; + case PLL_CPLL: + error = HAL_CRU_SetPllFreq(&CPLL, rate); + s_cpllFreq = HAL_CRU_GetPllFreq(&CPLL); + + return error; + case PLL_HPLL: + + return error; + case PLL_GPLL: + + return error; + + case CLK_UART0: + case CLK_UART1: + case CLK_UART2: + case CLK_UART3: + case CLK_UART4: + case CLK_UART5: + case CLK_UART6: + case CLK_UART7: + case CLK_UART8: + case CLK_UART9: + error = HAL_CRU_ClkFracSetFreq(clockName, rate); + + return error; + + case CLK_CAN0: + case CLK_CAN1: + case CLK_CAN2: + if (s_cpllFreq % rate == 0) { + pRate = s_cpllFreq; + mux = 1; + } else { + pRate = s_gpllFreq; + mux = 0; + } + + break; + + case CLK_TSADC_TSEN: + if (PLL_INPUT_OSC_RATE % rate == 0) { + pRate = PLL_INPUT_OSC_RATE; + mux = 0; + } else { + pRate = s_gpllFreq / 12; + mux = 1; + } + + break; + case CLK_TSADC: + pRate = HAL_CRU_ClkGetFreq(CLK_TSADC_TSEN); + + break; + case SCLK_SFC: + if (rate == 50000000) { + mux = 1; + } else if (rate == 75000000) { + mux = 2; + } else if (rate == 100000000) { + mux = 3; + } else if (rate == 125000000) { + mux = 4; + } else if (rate == 150000000) { + mux = 5; + } else { + mux = 0; + } + + break; + case CLK_SDMMC0: + if (rate == 400000000) { + mux = 1; + } else if (rate == 750000) { + mux = 5; + } else if (rate == 50000000) { + mux = 4; + } else if (rate == 100000000) { + mux = 3; + } else if (rate == 300000000) { + mux = 2; + } else { + mux = 0; + } + + break; + case ACLK_USB: + case HCLK_USB: + case PCLK_USB: + case ACLK_PHP: + case HCLK_PHP: + case PCLK_PHP: + case CLK_MAC0_2TOP: + case CLK_MAC1_2TOP: + case CLK_MAC0_OUT: + case CLK_MAC1_OUT: + case CLK_GMAC0_PTP_REF: + case CLK_GMAC1_PTP_REF: + case SCLK_GMAC0_RGMII_SPEED: + case SCLK_GMAC1_RGMII_SPEED: + case SCLK_GMAC0_RMII_SPEED: + case SCLK_GMAC1_RMII_SPEED: + case SCLK_GMAC0_RX_TX: + case SCLK_GMAC1_RX_TX: + error = HAL_CRU_ClkGmacSetFreq(clockName, rate); + + return error; + + default: + break; + } + + if ((clkMux == 0) && (clkDiv == 0)) { + return HAL_INVAL; + } + + div = HAL_DIV_ROUND_UP(pRate, rate); + if (clkMux) { + HAL_CRU_ClkSetMux(clkMux, mux); + } + if (clkDiv) { + HAL_CRU_ClkSetDiv(clkDiv, div); + } + + return HAL_OK; +} + +/** + * @brief wdt glbrst enable. + * @param wdtType: wdt reset type. + * @return HAL_OK. + * @attention these APIs allow direct use in the HAL layer. + */ +HAL_Status HAL_CRU_WdtGlbRstEnable(eCRU_WdtRstType wdtType) +{ + uint32_t mask = CRU_GLB_RST_CON_WDT_GLB_SRST_CTRL_MASK; + uint32_t val = 0; + + switch (wdtType) { + case GLB_RST_FST_WDT0: + val |= (1 << CRU_GLB_RST_CON_WDT_GLB_SRST_CTRL_SHIFT); + break; + case GLB_RST_SND_WDT0: + break; + default: + + return HAL_INVAL; + } + + CRU->GLB_RST_CON = VAL_MASK_WE(mask, val); + + return HAL_OK; +} + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* SOC_RK3568 && HAL_CRU_MODULE_ENABLED */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_debug.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_debug.c new file mode 100644 index 000000000..2308b5796 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_debug.c @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup DEBUG + * @{ + */ + +/** @defgroup DEBUG_How_To_Use How To Use + * @{ + + The DEBUG driver can be used as follows: + + Implement DBG hook: + + - printf func: define new HAL_SYSLOG in hal_conf.h or use HAL_DBG_Printf() in default; + - assert func: redefine AssertFailed(). + + Define debug level in hal_conf.h: + + - HAL_DBG_ON: print master switch; + - HAL_DBG_INFO_ON: information printing switch; + - HAL_DBG_WRN_ON: information printing switch; + - HAL_DBG_ERR_ON: information printing switch; + - HAL_ASSERT_ON: Support assert. + + APIS: + + - printf information by calling HAL_DBG(); + - printf warning by calling HAL_DBG_WRN(); + - printf error by calling HAL_DBG_ERR(); + - do assert by calling HAL_ASSERT(). + + @} */ + +#include "hal_base.h" + +/** @defgroup DEBUG_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ + +/********************* Private Structure Definition **************************/ + +/********************* Private Variable Definition ***************************/ + +/********************* Private Function Definition ***************************/ + +/** @} */ +/********************* Public Function Definition ****************************/ + +/** @defgroup DEBUG_Exported_Functions_Group5 Other Functions + + This section provides functions allowing to init and deinit module as follows: + + * @{ + */ + +/** + * @brief Reports the name of the source file and the source line number + * where the HAL_ASSERT error has occurred. + * @param file: pointer to the source file name + * @param line: HAL_ASSERT error line source number + */ +__attribute__((weak)) void HAL_AssertFailed(const char *file, uint32_t line) +{ + HAL_DBG_ERR("assert failed at %s %lu\n", file, line); + while (1) { + ; + } +} + +/** + * @brief format hex print. + * @param s: head tag for every new line. + * @param buf: buffer for printing. + * @param width: every single printed object width. + * @param len: the number of printed objects. + * @return HAL_Status: HAL_OK. + * sum = width * len (BYTE). + */ +HAL_Status HAL_DBG_HEX(char *s, void *buf, uint32_t width, uint32_t len) +{ +#ifdef HAL_DBG_ON + uint32_t i, j; + unsigned char *p8 = (unsigned char *)buf; + unsigned short *p16 = (unsigned short *)buf; + uint32_t *p32 = (uint32_t *)buf; + + j = 0; + for (i = 0; i < len; i++) { + if (j == 0) { + HAL_SYSLOG("[HAL_DBG_HEX] %s %p + 0x%lx:", s, buf, i * width); + } + + if (width == 4) { + HAL_SYSLOG("0x%08lx,", p32[i]); + } else if (width == 2) { + HAL_SYSLOG("0x%04x,", p16[i]); + } else { + HAL_SYSLOG("0x%02x,", p8[i]); + } + + if (++j >= 16) { + j = 0; + HAL_SYSLOG("\n"); + } + } + HAL_SYSLOG("\n"); +#endif + + return HAL_OK; +} + +#ifdef HAL_DBG_USING_HAL_PRINTF +static void reverse(char *start, char *end) +{ + while (start < end) { + char temp = *start; + *start = *end; + *end = temp; + start++; + end--; + } +} + +#ifdef __GNUC__ +extern int _write(int fd, char *ptr, int len); +#endif + +/** + * @brief format and print data + * @param format: format printf param. only support: \%d, \%s, \%ld, \%lld + * @return int32_t. + */ +__attribute__((weak)) int32_t HAL_DBG_Printf(const char *format, ...) +{ + static char g_printf_buf[HAL_PRINTF_BUF_SIZE]; + char *str = g_printf_buf; + int32_t len = 0; + va_list args; + + va_start(args, format); + + while (*format != '\0') { + if (*format == '%') { + format++; + if (*format == 'd') { + int i = va_arg(args, int); + char *start = str; + do { + *str++ = '0' + (i % 10); + i /= 10; + } while (i > 0); + reverse(start, str - 1); + } else if (*format == 's') { + char *s = va_arg(args, char *); + while (*s) { + *str++ = *s++; + } + } else if (*format == 'l') { + format++; + if (*format == 'd') { + long i = va_arg(args, long); + char *start = str; + do { + *str++ = '0' + (i % 10); + i /= 10; + } while (i > 0); + reverse(start, str - 1); + } else if (*format == 'l') { + format++; + if (*format == 'd') { + long long int i = va_arg(args, long long int); + char *start = str; + do { + *str++ = '0' + (i % 10); + i /= 10; + } while (i > 0); + reverse(start, str - 1); + } + } + } + } else { + *str++ = *format; + } + format++; + } + + *str = '\0'; + + va_end(args); + len = str - g_printf_buf; + +#ifdef __GNUC__ + + return _write(2, g_printf_buf, len); +#else + for (int i = 0; i < len; i++) { + fputc(g_printf_buf[i], stdout); + } + + return len; +#endif +} +#else +/** + * @brief format and print data + * @param format: format printf param. + * @return int32_t. + */ +__attribute__((weak)) int32_t HAL_DBG_Printf(const char *format, ...) +{ + return 0; +} +#endif /* HAL_DBG_USING_HAL_PRINTF */ + +/** @} */ + +/** @} */ + +/** @} */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_gmac.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_gmac.c new file mode 100644 index 000000000..9fc881f71 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_gmac.c @@ -0,0 +1,2256 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#ifdef HAL_GMAC_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup GMAC + * @brief GMAC HAL module driver + * @{ + */ + +/** @defgroup GMAC_How_To_Use How To Use + * @{ + + The GMAC HAL driver can be used as follows: + + - Declare a GMAC_HANDLE handle structure, for example: + ``` + GMAC_HANDLE instance; + ``` + - Invoke HAL_GMAC_Init() API to initialize base address, csr clock and interface: + - Base register address; + - Pclk clock rate; + - Interface mode. + + - Invoke HAL_GMAC_PHYInit() API to connect PHY: + - Must implement PHY hardware reset before invoke this function; + - Interface mode; + - PHY address; + - Auto negotiation or not; + - Duplex mode configured if auto negotiation is disable; + - Alos config desired speed if it is disable auto negotiation; + - Max speed is optional. + + - Invoke HAL_GMAC_WriteHWAddr() API to write mac address: + + - Invoke HAL_GMAC_DMARxDescInit() and HAL_GMAC_DMATxDescInit() APIs to init desc and buffer: + - Desc memory must declare as uncached; + - Buffer memory use cached meory; + + - Invoke HAL_GMAC_Start() API to start gmac. + + - Invoke HAL_GMAC_PHYStartup() API to configure PHY and do negotiation. + - Invoke HAL_GMAC_PHYUpdateLink() API to get PHY is linked or not. + - Invoke HAL_GMAC_PHYParseLink() API to get PHY linked information: + - Linked speed; + - Linked duplex; + - Flow ctrl on or off. + + - Inloke HAL_GMAC_MDIORead() and HAL_GMAC_MDIOWrite() read/write phy reg value. + + - Invoke HAL_GMAC_Send() and HAL_GMAC_Recv() for transfer: + - Must clean the dcached memory before use HAL_GMAC_Send(); + - Must invalidate dcached memory after use HAL_GMAC_Recv(); + - Use HAL_GMAC_IRQHandler() to handle Tx/Rx interrupt; + - Use HAL_GMAC_GetTXBuffer() and HAL_GMAC_GetRXBuffer() to get current buffer; + - Use HAL_GMAC_CleanRX() to clean Rx dirty description. + + - Invoke HAL_GMAC_Stop() to stop transfer. + + - Invoke HAL_GMAC_DeInit() if necessary. + @} */ + +/** @defgroup GMAC_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ + +/* GMAC config */ +#define GMAC_CONFIG_GPSLCE (1 << GMAC_MAC_CONFIGURATION_GPSLCE_SHIFT) +#define GMAC_CONFIG_IPC (1 << GMAC_MAC_CONFIGURATION_IPC_SHIFT) +#define GMAC_CONFIG_2K (1 << GMAC_MAC_CONFIGURATION_S2KP_SHIFT) +#define GMAC_CONFIG_CST (1 << GMAC_MAC_CONFIGURATION_CST_SHIFT) +#define GMAC_CONFIG_ACS (1 << GMAC_MAC_CONFIGURATION_ACS_SHIFT) +#define GMAC_CONFIG_WD (1 << GMAC_MAC_CONFIGURATION_WD_SHIFT) +#define GMAC_CONFIG_BE (1 << GMAC_MAC_CONFIGURATION_BE_SHIFT) +#define GMAC_CONFIG_JD (1 << GMAC_MAC_CONFIGURATION_JD_SHIFT) +#define GMAC_CONFIG_JE (1 << GMAC_MAC_CONFIGURATION_JE_SHIFT) +#define GMAC_CONFIG_PS (1 << GMAC_MAC_CONFIGURATION_PS_SHIFT) +#define GMAC_CONFIG_FES (1 << GMAC_MAC_CONFIGURATION_FES_SHIFT) +#define GMAC_CONFIG_DM (1 << GMAC_MAC_CONFIGURATION_DM_SHIFT) +#define GMAC_CONFIG_DCRS (1 << GMAC_MAC_CONFIGURATION_DCRS_SHIFT) +#define GMAC_CONFIG_TE (1 << GMAC_MAC_CONFIGURATION_TE_SHIFT) +#define GMAC_CONFIG_RE (1 << GMAC_MAC_CONFIGURATION_RE_SHIFT) + +#define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | GMAC_CONFIG_ACS | \ + GMAC_CONFIG_BE | GMAC_CONFIG_DCRS) + +/* GMAC HW features1 bitmap */ +#define GMAC_HW_FEAT_AVSEL (1 << GMAC_MAC_HW_FEATURE1_AVSEL_SHIFT) +#define GMAC_HW_TSOEN (1 << GMAC_MAC_HW_FEATURE1_TSOEN_SHIFT) +#define GMAC_HW_TXFIFOSIZE_SHIFT GMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT +#define GMAC_HW_RXFIFOSIZE_SHIFT GMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT +#define GMAC_HW_TXFIFOSIZE (0x1f << GMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) +#define GMAC_HW_RXFIFOSIZE (0x1f << GMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) + +/* Flow Ctrl */ +#define GMAC_Q0_TX_FLOW_CTRL_PT_SHIFT GMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT +#define GMAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff +#define GMAC_Q0_TX_FLOW_CTRL_TFE (1 << GMAC_MAC_Q0_TX_FLOW_CTRL_TFE_SHIFT) +#define GMAC_RX_FLOW_CTRL_RFE (1 << GMAC_MAC_RX_FLOW_CTRL_RFE_SHIFT) + +#define HAL_PAUSE_TIME 0xffff + +/* MMC register */ +#define MMC_CNTRL_COUNTER_RESET (1 << GMAC_MMC_CONTROL_CNTRST_SHIFT) +/* When set, do not roll over zero after reaching the max value */ +#define MMC_CNTRL_COUNTER_STOP_ROLLOVER (1 << GMAC_MMC_CONTROL_CNTSTOPRO_SHIFT) +/* Reset after reading */ +#define MMC_CNTRL_RESET_ON_READ (1 << GMAC_MMC_CONTROL_RSTONRD_SHIFT) +/* Freeze counter values to the current value */ +#define MMC_CNTRL_COUNTER_FREEZER (1 << GMAC_MMC_CONTROL_CNTFREEZ_SHIFT) +#define MMC_CNTRL_PRESET (1 << GMAC_MMC_CONTROL_CNTPRST_SHIFT) +#define MMC_CNTRL_FULL_HALF_PRESET (1 << GMAC_MMC_CONTROL_CNTPRSTLVL_SHIFT) + +#define MMC_RX_INTR_MASK 0x0c /* MMC Interrupt Mask */ +#define MMC_TX_INTR_MASK 0x10 /* MMC Interrupt Mask */ +#define MMC_DEFAULT_MASK 0xffffffff + +/* Mdc/Mdio register */ +#define GMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */ +#define GMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */ +#define GMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */ +#define GMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */ +#define GMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */ +#define GMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */ + +#define GMAC_MDIO_ADDRESS_PA_SHIFT (GMAC_MAC_MDIO_ADDRESS_PA_SHIFT) +#define GMAC_MDIO_ADDRESS_RDA_SHIFT (GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) +#define GMAC_MDIO_ADDRESS_CR_SHIFT (GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) +#define GMAC_MDIO_ADDRESS_SKAP (0x1 << GMAC_MAC_MDIO_ADDRESS_SKAP_SHIFT) +#define GMAC_MDIO_ADDRESS_GOC_SHIFT (GMAC_MAC_MDIO_ADDRESS_GOC_0_SHIFT) +#define GMAC_MDIO_ADDRESS_GOC_READ (0x3 << GMAC_MAC_MDIO_ADDRESS_GOC_0_SHIFT) +#define GMAC_MDIO_ADDRESS_GOC_WRITE (0x1 << GMAC_MAC_MDIO_ADDRESS_GOC_0_SHIFT) +#define GMAC_MDIO_ADDRESS_C45E (0x1 << GMAC_MAC_MDIO_ADDRESS_C45E_SHIFT) +#define GMAC_MDIO_ADDRESS_GB (0x1 << GMAC_MAC_MDIO_ADDRESS_GB_SHIFT) + +#define GMAC_MDIO_DATA_GD_MASK 0xffff + +#define GMAC_MDIO_TIMEOUT 100 /* ms */ + +/* MTL */ +#define MTL_TXQ0_OPERATION_MODE_TSF (1 << GMAC_MTL_TXQ0_OPERATION_MODE_TSF_SHIFT) +#define MTL_TXQ0_OPERATION_MODE_FTQ (1 << GMAC_MTL_TXQ0_OPERATION_MODE_FTQ_SHIFT) + +#define MTL_TXQ0_DEBUG_TXQSTS (1 << GMAC_MTL_TXQ0_DEBUG_TXQSTS_SHIFT) +#define MTL_TXQ0_DEBUG_TRCSTS_SHIFT GMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT +#define MTL_TXQ0_DEBUG_TRCSTS_MASK GMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK + +#define MTL_RXQ0_OPERATION_MODE_EHFC (1 << GMAC_MTL_RXQ0_OPERATION_MODE_EHFC_SHIFT) +#define MTL_RXQ0_OPERATION_MODE_RSF (1 << GMAC_MTL_RXQ0_OPERATION_MODE_RSF_SHIFT) +#define MTL_RXQ0_OPERATION_MODE_FEP (1 << GMAC_MTL_RXQ0_OPERATION_MODE_FEP_SHIFT) +#define MTL_RXQ0_OPERATION_MODE_FUP (1 << GMAC_MTL_RXQ0_OPERATION_MODE_FUP_SHIFT) + +#define MTL_OP_MODE_TXQEN_MASK (3 << 2) +#define MTL_OP_MODE_TXQEN_AV (1 << 2) +#define MTL_OP_MODE_TXQEN (1 << 3) +#define MTL_OP_MODE_TSF (1 << 1) + +#define MTL_OP_MODE_TQS_MASK (0x1f<< 16) +#define MTL_OP_MODE_TQS_SHIFT 16 + +#define MTL_OP_MODE_TTC_MASK GMAC_MTL_TXQ0_OPERATION_MODE_TTC_MASK +#define MTL_OP_MODE_TTC_SHIFT GMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT + +#define MTL_OP_MODE_TTC_32 0 +#define MTL_OP_MODE_TTC_64 (1 << MTL_OP_MODE_TTC_SHIFT) +#define MTL_OP_MODE_TTC_96 (2 << MTL_OP_MODE_TTC_SHIFT) +#define MTL_OP_MODE_TTC_128 (3 << MTL_OP_MODE_TTC_SHIFT) +#define MTL_OP_MODE_TTC_192 (4 << MTL_OP_MODE_TTC_SHIFT) +#define MTL_OP_MODE_TTC_256 (5 << MTL_OP_MODE_TTC_SHIFT) +#define MTL_OP_MODE_TTC_384 (6 << MTL_OP_MODE_TTC_SHIFT) +#define MTL_OP_MODE_TTC_512 (7 << MTL_OP_MODE_TTC_SHIFT) + +#define MTL_OP_MODE_RQS_SHIFT 20 +#define MTL_OP_MODE_RQS_MASK (0x3ff <pReg->MAC_MDIO_ADDRESS) & GMAC_MDIO_ADDRESS_GB) == + GMAC_MDIO_ADDRESS_GB) { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > GMAC_MDIO_TIMEOUT) { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief reads the its ID by specified addr. + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * @param addr: PHY address on the MII bus. + * @param phyID: where to store the ID retrieved. + * + * @return HAL status + */ +static HAL_Status PHY_GetID(struct GMAC_HANDLE *pGMAC, int32_t addr, + uint32_t *phyID) +{ + int32_t phyReg; + + /* + * Grab the bits from PHYIR1, and put them + * in the upper half. + */ + phyReg = HAL_GMAC_MDIORead(pGMAC, addr, MII_PHYSID1); + if (phyReg < 0) { + return phyReg; + } + + *phyID = (phyReg & 0xffff) << 16; + + /* Grab the bits from PHYIR2, and put them in the lower half */ + phyReg = HAL_GMAC_MDIORead(pGMAC, addr, MII_PHYSID2); + + if (phyReg < 0) { + return phyReg; + } + + *phyID |= (phyReg & 0xffff); + + return HAL_OK; +} + +/** + * @brief Store the PHY status. + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * @param config: pointer to a PHY_Config structure that contains + * the configration for PHY. + * @param addr: PHY address on the MII bus. + * @param id: where to store the ID retrieved. + * + * @return HAL status + */ +static HAL_Status PHY_InfoCreate(struct GMAC_HANDLE *pGMAC, + struct GMAC_PHY_Config *config, + int32_t addr, uint32_t id) +{ + pGMAC->phyStatus.link = 0; + pGMAC->phyStatus.duplex = config->duplexMode; + pGMAC->phyStatus.interface = config->interface; + pGMAC->phyStatus.neg = config->neg; + pGMAC->phyStatus.speed = config->speed; + pGMAC->phyStatus.maxSpeed = config->maxSpeed; + + pGMAC->phyStatus.addr = addr; + pGMAC->phyStatus.phyID = id; + + return HAL_OK; +} + +/** + * @brief Connect the PHY by address. + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * @param config: pointer to a PHY_Config structure that contains + * the configration for PHY. + * @param addr: PHY address on the MII bus. + * + * @return HAL status + */ +static HAL_Status PHY_Connect(struct GMAC_HANDLE *pGMAC, + struct GMAC_PHY_Config *config, + int32_t addr) +{ + HAL_Status status; + uint32_t phyID = 0xffffffff; + + status = PHY_GetID(pGMAC, addr, &phyID); + if (status == HAL_OK && (phyID & 0x1fffffff) != 0x1fffffff) { + return PHY_InfoCreate(pGMAC, config, addr, phyID); + } + + return HAL_NODEV; +} + +/** + * @brief configures/forces speed/duplex from PHY status + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * + * @return HAL status + */ +static HAL_Status PHY_SetupForced(struct GMAC_HANDLE *pGMAC) +{ + int32_t ctl = BMCR_ANRESTART; + + if (PHY_SPEED_1000M == pGMAC->phyStatus.speed) { + ctl |= BMCR_SPEED1000; + } else if (PHY_SPEED_100M == pGMAC->phyStatus.speed) { + ctl |= BMCR_SPEED100; + } + + if (PHY_DUPLEX_FULL == pGMAC->phyStatus.duplex) { + ctl |= BMCR_FULLDPLX; + } + + return HAL_GMAC_MDIOWrite(pGMAC, pGMAC->phyStatus.addr, MII_BMCR, ctl); +} + +/** + * @brief configures PHY advert features + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * + * @return HAL status + */ +static int32_t PHY_ConfigAdvert(struct GMAC_HANDLE *pGMAC) +{ + uint32_t adverTise; + int32_t oldAdv, adv, bmsr; + int32_t err, changed = 0; + + /* Only allow advertising what this PHY supports */ + pGMAC->phyStatus.advertising &= pGMAC->phyStatus.supported; + adverTise = pGMAC->phyStatus.advertising; + + /* Setup standard advertisement */ + adv = HAL_GMAC_MDIORead(pGMAC, pGMAC->phyStatus.addr, MII_ADVERTISE); + if (adv < 0) { + return adv; + } + + oldAdv = adv; + adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | + ADVERTISE_PAUSE_ASYM); + if (adverTise & ADVERTISED_10baseT_Half) { + adv |= ADVERTISE_10HALF; + } + if (adverTise & ADVERTISED_10baseT_Full) { + adv |= ADVERTISE_10FULL; + } + if (adverTise & ADVERTISED_100baseT_Half) { + adv |= ADVERTISE_100HALF; + } + if (adverTise & ADVERTISED_100baseT_Full) { + adv |= ADVERTISE_100FULL; + } + if (adverTise & ADVERTISED_Pause) { + adv |= ADVERTISE_PAUSE_CAP; + } + if (adverTise & ADVERTISED_Asym_Pause) { + adv |= ADVERTISE_PAUSE_ASYM; + } + if (adverTise & ADVERTISED_1000baseX_Half) { + adv |= ADVERTISE_1000XHALF; + } + if (adverTise & ADVERTISED_1000baseX_Full) { + adv |= ADVERTISE_1000XFULL; + } + + if (adv != oldAdv) { + err = HAL_GMAC_MDIOWrite(pGMAC, pGMAC->phyStatus.addr, + MII_ADVERTISE, adv); + + if (err < 0) { + return err; + } + changed = 1; + } + + bmsr = HAL_GMAC_MDIORead(pGMAC, pGMAC->phyStatus.addr, MII_BMSR); + if (bmsr < 0) { + return bmsr; + } + + /* + * Per 802.3-2008, Section 22.2.4.2.16 Extended status all + * 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a + * logical 1. + */ + if (!(bmsr & BMSR_ESTATEN)) { + return changed; + } + + /* Configure gigabit if it's supported */ + adv = HAL_GMAC_MDIORead(pGMAC, pGMAC->phyStatus.addr, MII_CTRL1000); + if (adv < 0) { + return adv; + } + + oldAdv = adv; + + adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); + + if (pGMAC->phyStatus.supported & (HAL_GMAC_PHY_SUPPORTED_1000baseT_Half | + HAL_GMAC_PHY_SUPPORTED_1000baseT_Full)) { + if (adverTise & HAL_GMAC_PHY_SUPPORTED_1000baseT_Half) { + adv |= ADVERTISE_1000HALF; + } + if (adverTise & HAL_GMAC_PHY_SUPPORTED_1000baseT_Full) { + adv |= ADVERTISE_1000FULL; + } + } + + if (adv != oldAdv) { + changed = 1; + } + + err = HAL_GMAC_MDIOWrite(pGMAC, pGMAC->phyStatus.addr, MII_CTRL1000, adv); + if (err < 0) { + return err; + } + + return changed; +} + +/** + * @brief Enable and Restart auto-negotiation + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * + * @return HAL status + */ +static HAL_Status PHY_RestartAneg(struct GMAC_HANDLE *pGMAC) +{ + int32_t ctl; + + ctl = HAL_GMAC_MDIORead(pGMAC, pGMAC->phyStatus.addr, MII_BMCR); + if (ctl < 0) { + return ctl; + } + + ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); + /* Don't isolate the PHY if we're negotiating */ + ctl &= ~(BMCR_ISOLATE); + ctl = HAL_GMAC_MDIOWrite(pGMAC, pGMAC->phyStatus.addr, MII_BMCR, ctl); + + return ctl; +} + +/** + * @brief If auto-negotiation is enabled, we configure the + * advertising, and then restart auto-negotiation. If it is not + * enabled, then we write the BMCR. + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * + * @return HAL status + */ +static HAL_Status PHY_ConfigAneg(struct GMAC_HANDLE *pGMAC) +{ + HAL_Status result; + + if (PHY_AUTONEG_ENABLE != pGMAC->phyStatus.neg) { + return PHY_SetupForced(pGMAC); + } + + result = PHY_ConfigAdvert(pGMAC); + if (result < 0) { /* error */ + return result; + } + + if (result == 0) { + /* + * Advertisment hasn't changed, but maybe aneg was never on to + * begin with? Or maybe phy was isolated? + */ + int32_t ctl = HAL_GMAC_MDIORead(pGMAC, pGMAC->phyStatus.addr, MII_BMCR); + if (ctl < 0) { + return ctl; + } + + if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE)) { + result = 1; /* do restart aneg */ + } + } + + /* + * Only restart aneg if we are advertising something different + * than we were before. + */ + if (result > 0) { + result = PHY_RestartAneg(pGMAC); + } + + return result; +} + +/** + * @brief Set PHY max speed if provied + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * @param max_speed: max speed for PHY supported. + * + * @return HAL status + */ +static HAL_Status PHY_Setsupported(struct GMAC_HANDLE *pGMAC, uint32_t maxSpeed) +{ + pGMAC->phyStatus.supported &= HAL_GMAC_PHY_DEFAULT_FEATURES; + + switch (maxSpeed) { + default: + + return HAL_ERROR; + case PHY_SPEED_1000M: + pGMAC->phyStatus.supported |= HAL_GMAC_PHY_1000BT_FEATURES; + /* fall through */ + case PHY_SPEED_100M: + pGMAC->phyStatus.supported |= HAL_GMAC_PHY_100BT_FEATURES; + /* fall through */ + case PHY_SPEED_10M: + pGMAC->phyStatus.supported |= HAL_GMAC_PHY_10BT_FEATURES; + } + + return HAL_OK; +} + +/** + * @brief Configure PHY by features + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * + * @return HAL status + */ +static HAL_Status PHY_Config(struct GMAC_HANDLE *pGMAC) +{ + int32_t val = 0; + uint32_t features; + HAL_Status status; + + if (pGMAC->phyOps.config) { + status = pGMAC->phyOps.config(pGMAC); + if (status) { + return status; + } + } + + features = (HAL_GMAC_PHY_SUPPORTED_TP | HAL_GMAC_PHY_SUPPORTED_MII | + HAL_GMAC_PHY_SUPPORTED_AUI | HAL_GMAC_PHY_SUPPORTED_FIBRE | + HAL_GMAC_PHY_SUPPORTED_BNC); + + /* Do we support autonegotiation? */ + val = HAL_GMAC_MDIORead(pGMAC, pGMAC->phyStatus.addr, MII_BMSR); + if (val < 0) { + return val; + } + + if (val & BMSR_ANEGCAPABLE) { + features |= HAL_GMAC_PHY_SUPPORTED_Autoneg; + } + + if (val & BMSR_100FULL) { + features |= HAL_GMAC_PHY_SUPPORTED_100baseT_Full; + } + if (val & BMSR_100HALF) { + features |= HAL_GMAC_PHY_SUPPORTED_100baseT_Half; + } + if (val & BMSR_10FULL) { + features |= HAL_GMAC_PHY_SUPPORTED_10baseT_Full; + } + if (val & BMSR_10HALF) { + features |= HAL_GMAC_PHY_SUPPORTED_10baseT_Half; + } + + if (val & BMSR_ESTATEN) { + val = HAL_GMAC_MDIORead(pGMAC, pGMAC->phyStatus.addr, MII_ESTATUS); + if (val < 0) { + return val; + } + + if (val & ESTATUS_1000_TFULL) { + features |= HAL_GMAC_PHY_SUPPORTED_1000baseT_Full; + } + if (val & ESTATUS_1000_THALF) { + features |= HAL_GMAC_PHY_SUPPORTED_1000baseT_Half; + } + if (val & ESTATUS_1000_XFULL) { + features |= HAL_GMAC_PHY_SUPPORTED_1000baseX_Full; + } + if (val & ESTATUS_1000_XHALF) { + features |= HAL_GMAC_PHY_SUPPORTED_1000baseX_Half; + } + } + + pGMAC->phyStatus.supported &= features; + pGMAC->phyStatus.advertising &= features; + + PHY_ConfigAneg(pGMAC); + + return HAL_OK; +} + +/** + * @brief Configure GMAC flow ctrl + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * @param duplex: full duplex or half. + * @param fc: desired flow ctrl. + * @param pauseTime: time for pause. + * + * @return HAL status + */ +static HAL_Status GMAC_FlowCtrl(struct GMAC_HANDLE *pGMAC, int32_t duplex, + uint32_t fc, uint32_t pauseTime) +{ + unsigned int flow = 0; + + HAL_DBG("GMAC Flow-Control:\n"); + if (fc & HAL_GMAC_FLOW_RX) { + HAL_DBG("\tReceive Flow-Control ON\n"); + flow |= GMAC_RX_FLOW_CTRL_RFE; + } + WRITE_REG(pGMAC->pReg->MAC_RX_FLOW_CTRL, flow); + + if (fc & HAL_GMAC_FLOW_TX) { + HAL_DBG("\tTransmit Flow-Control ON\n"); + + if (duplex) { + HAL_DBG("\tduplex mode: PAUSE %ld\n", pauseTime); + } + + flow = GMAC_Q0_TX_FLOW_CTRL_TFE; + if (duplex) { + flow |= (pauseTime << GMAC_Q0_TX_FLOW_CTRL_PT_SHIFT); + } + + WRITE_REG(pGMAC->pReg->MAC_Q0_TX_FLOW_CTRL, flow); + } else { + WRITE_REG(pGMAC->pReg->MAC_Q0_TX_FLOW_CTRL, 0); + } + + return HAL_OK; +} + +/** + * @brief Configure DMA RX operation mode + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * @param mode: operation mode + * @param fifosz: Rx fifo size. + * + * @return HAL status + */ +static HAL_Status GMAC_DMARXOpMode(struct GMAC_HANDLE *pGMAC, int32_t mode, + int32_t fifosz) +{ + uint32_t rqs = fifosz / 256 - 1; + uint32_t mtlRXOP, mtlRXInt; + + mtlRXOP = READ_REG(pGMAC->pReg->MTL_RXQ0_OPERATION_MODE); + if (mode == SF_DMA_MODE) { + HAL_DBG("GMAC: enable RX store and forward mode\n"); + mtlRXOP |= MTL_RXQ0_OPERATION_MODE_RSF; + } else { + HAL_DBG("GMAC: disable RX SF mode (threshold %ld)\n", mode); + mtlRXOP &= ~MTL_RXQ0_OPERATION_MODE_RSF; + mtlRXOP &= MTL_OP_MODE_RTC_MASK; + if (mode <= 32) { + mtlRXOP |= MTL_OP_MODE_RTC_32; + } else if (mode <= 64) { + mtlRXOP |= MTL_OP_MODE_RTC_64; + } else if (mode <= 96) { + mtlRXOP |= MTL_OP_MODE_RTC_96; + } else { + mtlRXOP |= MTL_OP_MODE_RTC_128; + } + } + + mtlRXOP &= ~MTL_OP_MODE_RQS_MASK; + mtlRXOP |= rqs << MTL_OP_MODE_RQS_SHIFT; + + /* + * Enable flow control only if each channel gets 4 KiB or more FIFO and + * only if channel is not an AVB channel. + */ + if (fifosz >= 4096) { + uint32_t rfd, rfa; + + mtlRXOP |= MTL_RXQ0_OPERATION_MODE_EHFC; + + /* + * Set Threshold for Activating Flow Control to min 2 frames, + * i.e. 1500 * 2 = 3000 bytes. + * + * Set Threshold for Deactivating Flow Control to min 1 frame, + * i.e. 1500 bytes. + */ + switch (fifosz) { + case 4096: + /* + * This violates the above formula because of FIFO size + * limit therefore overflow may occur in spite of this. + */ + rfd = 0x03; /* Full-2.5K */ + rfa = 0x01; /* Full-1.5K */ + break; + + case 8192: + rfd = 0x06; /* Full-4K */ + rfa = 0x0a; /* Full-6K */ + break; + + case 16384: + rfd = 0x06; /* Full-4K */ + rfa = 0x12; /* Full-10K */ + break; + + default: + rfd = 0x06; /* Full-4K */ + rfa = 0x1e; /* Full-16K */ + break; + } + + mtlRXOP &= ~MTL_OP_MODE_RFD_MASK; + mtlRXOP |= rfd << MTL_OP_MODE_RFD_SHIFT; + + mtlRXOP &= ~MTL_OP_MODE_RFA_MASK; + mtlRXOP |= rfa << MTL_OP_MODE_RFA_SHIFT; + } + + WRITE_REG(pGMAC->pReg->MTL_RXQ0_OPERATION_MODE, mtlRXOP); + + /* Enable MTL RX overflow */ + mtlRXInt = READ_REG(pGMAC->pReg->MTL_Q0_INTERRUPT_CTRL_STATUS); + WRITE_REG(pGMAC->pReg->MTL_Q0_INTERRUPT_CTRL_STATUS, mtlRXInt | + MTL_RX_OVERFLOW_INT_EN); + + return HAL_OK; +} + +/** + * @brief Configure DMA TX operation mode + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * @param mode: operation mode + * @param fifosz: Tx fifo size. + * + * @return HAL status + */ +static HAL_Status GMAC_DMATXOpMode(struct GMAC_HANDLE *pGMAC, int32_t mode, + int32_t fifosz) +{ + uint32_t tqs = fifosz / 256 - 1; + uint32_t mtlTXOP; + + mtlTXOP = READ_REG(pGMAC->pReg->MTL_TXQ0_OPERATION_MODE); + + if (mode == SF_DMA_MODE) { + HAL_DBG("GMAC: enable TX store and forward mode\n"); + /* Transmit COE type 2 cannot be done in cut-through mode. */ + mtlTXOP |= MTL_OP_MODE_TSF; + } else { + HAL_DBG("GMAC: disabling TX SF (threshold %ld)\n", mode); + mtlTXOP &= ~MTL_OP_MODE_TSF; + mtlTXOP &= MTL_OP_MODE_TTC_MASK; + /* Set the transmit threshold */ + if (mode <= 32) { + mtlTXOP |= MTL_OP_MODE_TTC_32; + } else if (mode <= 64) { + mtlTXOP |= MTL_OP_MODE_TTC_64; + } else if (mode <= 96) { + mtlTXOP |= MTL_OP_MODE_TTC_96; + } else if (mode <= 128) { + mtlTXOP |= MTL_OP_MODE_TTC_128; + } else if (mode <= 192) { + mtlTXOP |= MTL_OP_MODE_TTC_192; + } else if (mode <= 256) { + mtlTXOP |= MTL_OP_MODE_TTC_256; + } else if (mode <= 384) { + mtlTXOP |= MTL_OP_MODE_TTC_384; + } else { + mtlTXOP |= MTL_OP_MODE_TTC_512; + } + } + /* + * For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO + * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE. + * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W + * with reset values: TXQEN off, TQS 256 bytes. + * + * TXQEN must be written for multi-channel operation and TQS must + * reflect the available fifo size per queue (total fifo size / number + * of enabled queues). + */ + mtlTXOP &= ~MTL_OP_MODE_TXQEN_MASK; + mtlTXOP |= MTL_OP_MODE_TXQEN; + + mtlTXOP &= ~MTL_OP_MODE_TQS_MASK; + mtlTXOP |= tqs << MTL_OP_MODE_TQS_SHIFT; + + WRITE_REG(pGMAC->pReg->MTL_TXQ0_OPERATION_MODE, mtlTXOP); + + return HAL_OK; +} + +/** @} */ + +/********************* Public Function Definition ****************************/ + +/** @defgroup GMAC_Exported_Functions_Group3 IO Functions + + This section provides functions allowing to IO controlling: + + * @{ + */ + +/** + * @brief Read MDIO bus data + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * @param mdioAddr: PHY address. + * @param mdioReg: register value. + * + * @return readen data + */ +int32_t HAL_GMAC_MDIORead(struct GMAC_HANDLE *pGMAC, int32_t mdioAddr, + int32_t mdioReg) +{ + HAL_Status status; + int32_t val; + + HAL_ASSERT(pGMAC != NULL); + + // HAL_DBG("Mdio Read addr=%ld, reg=%ld\n", mdioAddr, mdioReg); + status = Mdio_WaitIdle(pGMAC); + if (status) { + HAL_DBG("MDIO not idle at entry"); + + return status; + } + + val = READ_REG(pGMAC->pReg->MAC_MDIO_ADDRESS); + val &= GMAC_MDIO_ADDRESS_SKAP | + GMAC_MDIO_ADDRESS_C45E; + val |= (mdioAddr << GMAC_MDIO_ADDRESS_PA_SHIFT) | + (mdioReg << GMAC_MDIO_ADDRESS_RDA_SHIFT) | + (pGMAC->clkCSR << + GMAC_MDIO_ADDRESS_CR_SHIFT) | + GMAC_MDIO_ADDRESS_GOC_READ | + GMAC_MDIO_ADDRESS_GB; + WRITE_REG(pGMAC->pReg->MAC_MDIO_ADDRESS, val); + + status = Mdio_WaitIdle(pGMAC); + if (status) { + HAL_DBG("MDIO read didn't complete"); + + return status; + } + + val = READ_REG(pGMAC->pReg->MAC_MDIO_DATA); + val &= GMAC_MDIO_DATA_GD_MASK; + + return val; +} + +/** + * @brief Write MDIO bus data + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * @param mdioAddr: PHY address. + * @param mdioReg: register value. + * @param mdioVal: MDIO value be written. + * + * @return HAL status + */ +HAL_Status HAL_GMAC_MDIOWrite(struct GMAC_HANDLE *pGMAC, int32_t mdioAddr, + int32_t mdioReg, uint16_t mdioVal) +{ + HAL_Status status; + uint32_t val; + + HAL_ASSERT(pGMAC != NULL); + + // HAL_DBG("%s(addr=%lx, reg=%ld, val=%x):\n", __func__, + // mdioAddr, mdioReg, mdioVal); + status = Mdio_WaitIdle(pGMAC); + if (status) { + HAL_DBG("MDIO not idle at entry"); + + return status; + } + + WRITE_REG(pGMAC->pReg->MAC_MDIO_DATA, mdioVal); + val = READ_REG(pGMAC->pReg->MAC_MDIO_ADDRESS); + val &= GMAC_MDIO_ADDRESS_SKAP | + GMAC_MDIO_ADDRESS_C45E; + val |= (mdioAddr << GMAC_MDIO_ADDRESS_PA_SHIFT) | + (mdioReg << GMAC_MDIO_ADDRESS_RDA_SHIFT) | + (pGMAC->clkCSR << + GMAC_MDIO_ADDRESS_CR_SHIFT) | + GMAC_MDIO_ADDRESS_GOC_WRITE | + GMAC_MDIO_ADDRESS_GB; + + WRITE_REG(pGMAC->pReg->MAC_MDIO_ADDRESS, val); + + status = Mdio_WaitIdle(pGMAC); + if (status) { + HAL_DBG("MDIO read didn't complete"); + + return status; + } + + return HAL_OK; +} + +/** + * @brief Init PHY by config to connect PHY + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * @param config: pointer to a PHY_Config structure that contains + * the configuration. + * + * @return HAL status + */ +HAL_Status HAL_GMAC_PHYInit(struct GMAC_HANDLE *pGMAC, struct GMAC_PHY_Config *config) +{ + int32_t i, found = 0, timeout = 500; + HAL_Status status; + int32_t reg; + + HAL_ASSERT(pGMAC != NULL); + + if (!config->features) { + config->features = HAL_GMAC_PHY_GBIT_FEATURES | HAL_GMAC_PHY_SUPPORTED_MII | + HAL_GMAC_PHY_SUPPORTED_AUI | HAL_GMAC_PHY_SUPPORTED_FIBRE | + HAL_GMAC_PHY_SUPPORTED_BNC; + } + + pGMAC->phyStatus.advertising = pGMAC->phyStatus.supported = config->features; + + /* softreset */ + if (HAL_GMAC_MDIOWrite(pGMAC, config->phyAddress, MII_BMCR, BMCR_RESET) < 0) { + HAL_DBG("PHY reset failed\n"); + + return HAL_ERROR; + } + + reg = HAL_GMAC_MDIORead(pGMAC, config->phyAddress, MII_BMCR); + while ((reg & BMCR_RESET) && timeout--) { + reg = HAL_GMAC_MDIORead(pGMAC, config->phyAddress, MII_BMCR); + if (reg < 0) { + HAL_DBG("PHY status read failed\n"); + + return HAL_ERROR; + } + HAL_DelayUs(1000); + } + + if (reg & BMCR_RESET) { + HAL_DBG("PHY reset timed out\n"); + + return HAL_TIMEOUT; + } + + HAL_DelayUs(100000); + + if (config->phyAddress < 0) { + for (i = 0; i < 16; i++) { + status = PHY_Connect(pGMAC, config, i); + if (!status) { + found++; + break; + } + } + } else { + /* Use PHY addr to connect PHY */ + status = PHY_Connect(pGMAC, config, config->phyAddress); + if (!status) { + found = 1; + } + } + + if (!found) { + HAL_DBG("not PHY found\n"); + + return HAL_NODEV; + } else { + HAL_DBG("PHY found ID: 0x%lx\n", pGMAC->phyStatus.phyID); + } + + if (pGMAC->phyOps.init) { + status = pGMAC->phyOps.init(pGMAC); + } + + return status; +} + +/** + * @brief update link status up/down from PHY + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * + * @return HAL status + */ +HAL_Status HAL_GMAC_PHYUpdateLink(struct GMAC_HANDLE *pGMAC) +{ + int32_t reg; + + HAL_ASSERT(pGMAC != NULL); + + /* + * Wait if the link is up, and autonegotiation is in progress + * (ie - we're capable and it's not done) + */ + reg = HAL_GMAC_MDIORead(pGMAC, pGMAC->phyStatus.addr, MII_BMSR); + if (reg < 0) { + return reg; + } + + /* + * If we already saw the link up, and it hasn't gone down, then + * we don't need to wait for autoneg again + */ + if (pGMAC->phyStatus.link && reg & BMSR_LSTATUS) { + return HAL_OK; + } + + reg = HAL_GMAC_MDIORead(pGMAC, pGMAC->phyStatus.addr, MII_BMSR); + if (reg & BMSR_LSTATUS) { + pGMAC->phyStatus.link = 1; + } else { + pGMAC->phyStatus.link = 0; + } + + return HAL_OK; +} + +/** + * @brief Updates the speed and duplex. If autonegotiation is + * enabled, it uses the AND of the link partner's advertised + * capabilities and our advertised capabilities. If autonegotiation + * is disabled, we use the appropriate bits in the control register. + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * + * @return HAL status + */ +HAL_Status HAL_GMAC_PHYParseLink(struct GMAC_HANDLE *pGMAC) +{ + int32_t reg = HAL_GMAC_MDIORead(pGMAC, pGMAC->phyStatus.addr, MII_BMSR); + + HAL_ASSERT(pGMAC != NULL); + + /* We're using autonegotiation */ + if (pGMAC->phyStatus.neg == PHY_AUTONEG_ENABLE) { + uint32_t lpa = 0, estatus = 0; + int32_t gblpa = 0; + /* Check for gigabit capability */ + if (pGMAC->phyStatus.supported & (HAL_GMAC_PHY_SUPPORTED_1000baseT_Full | + HAL_GMAC_PHY_SUPPORTED_1000baseT_Half)) { + /* + * We want a list of states supported by + * both PHYs in the link + */ + gblpa = HAL_GMAC_MDIORead(pGMAC, pGMAC->phyStatus.addr, MII_STAT1000); + if (gblpa < 0) { + HAL_DBG("Could not read MII_STAT1000. Ignoring gigabit capability\n"); + gblpa = 0; + } + gblpa &= HAL_GMAC_MDIORead(pGMAC, pGMAC->phyStatus.addr, MII_CTRL1000) << 2; + } + + /* + * Set the baseline so we only have to set them + * if they're different + */ + pGMAC->phyStatus.speed = PHY_SPEED_10M; + pGMAC->phyStatus.duplex = PHY_DUPLEX_HALF; + + /* Check the gigabit fields */ + if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) { + pGMAC->phyStatus.speed = PHY_SPEED_1000M; + + if (gblpa & PHY_1000BTSR_1000FD) { + pGMAC->phyStatus.duplex = PHY_DUPLEX_FULL; + } + + /* We're done! */ + return HAL_OK; + } + + lpa = HAL_GMAC_MDIORead(pGMAC, pGMAC->phyStatus.addr, MII_ADVERTISE); + lpa &= HAL_GMAC_MDIORead(pGMAC, pGMAC->phyStatus.addr, MII_LPA); + + if (lpa & (LPA_100FULL | LPA_100HALF)) { + pGMAC->phyStatus.speed = PHY_SPEED_100M; + + if (lpa & LPA_100FULL) { + pGMAC->phyStatus.duplex = PHY_DUPLEX_FULL; + } + } else if (lpa & LPA_10FULL) { + pGMAC->phyStatus.duplex = PHY_DUPLEX_FULL; + } + + /* + * Extended status may indicate that the PHY supports + * 1000BASE-T/X even though the 1000BASE-T registers + * are missing. In this case we can't tell whether the + * peer also supports it, so we only check extended + * status if the 1000BASE-T registers are actually + * missing. + */ + if ((reg & BMSR_ESTATEN) && !(reg & BMSR_ERCAP)) { + estatus = HAL_GMAC_MDIORead(pGMAC, pGMAC->phyStatus.addr, MII_ESTATUS); + } + + if (estatus & (ESTATUS_1000_XFULL | ESTATUS_1000_XHALF | + ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) { + pGMAC->phyStatus.speed = PHY_SPEED_1000M; + if (estatus & (ESTATUS_1000_XFULL | ESTATUS_1000_TFULL)) { + pGMAC->phyStatus.duplex = PHY_DUPLEX_FULL; + } + } + + if (pGMAC->phyStatus.duplex == PHY_DUPLEX_FULL) { + pGMAC->phyStatus.pause = lpa & LPA_PAUSE_CAP ? 1 : 0; + } + } else { + uint32_t bmcr = HAL_GMAC_MDIORead(pGMAC, pGMAC->phyStatus.addr, MII_BMCR); + + pGMAC->phyStatus.speed = PHY_SPEED_10M; + pGMAC->phyStatus.duplex = PHY_DUPLEX_HALF; + + if (bmcr & BMCR_FULLDPLX) { + pGMAC->phyStatus.duplex = PHY_DUPLEX_FULL; + } + + if (bmcr & BMCR_SPEED1000) { + pGMAC->phyStatus.speed = PHY_SPEED_1000M; + } else if (bmcr & BMCR_SPEED100) { + pGMAC->phyStatus.speed = PHY_SPEED_100M; + } + + pGMAC->phyStatus.pause = 0; + } + + return HAL_OK; +} + +/** + * @brief Start the PHY after configuration + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * + * @return HAL status + */ +HAL_Status HAL_GMAC_PHYStartup(struct GMAC_HANDLE *pGMAC) +{ + HAL_Status status; + + HAL_ASSERT(pGMAC != NULL); + + if (pGMAC->phyStatus.maxSpeed) { + status = PHY_Setsupported(pGMAC, pGMAC->phyStatus.maxSpeed); + if (status) { + HAL_DBG_ERR("phy_set_supported() failed: %d", status); + + return status; + } + } + + status = PHY_Config(pGMAC); + if (status) { + HAL_DBG("PHY_ConfigAneg failed"); + + return status; + } + + if (pGMAC->phyOps.startup) { + status = pGMAC->phyOps.startup(pGMAC); + if (status) { + return status; + } + } + + return HAL_OK; +} + +/** + * @brief Enable DMA IRQ + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + */ +void HAL_GMAC_EnableDmaIRQ(struct GMAC_HANDLE *pGMAC) +{ + HAL_ASSERT(pGMAC != NULL); + WRITE_REG(pGMAC->pReg->DMA_CH0_INTERRUPT_ENABLE, + DMA_CHAN_INTR_DEFAULT_MASK); +} + +/** + * @brief Disable DMA IRQ + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + */ +void HAL_GMAC_DisableDmaIRQ(struct GMAC_HANDLE *pGMAC) +{ + HAL_ASSERT(pGMAC != NULL); + WRITE_REG(pGMAC->pReg->DMA_CH0_INTERRUPT_ENABLE, 0); +} + +/** + * @brief Initializes the DMA Tx descriptors in chain mode. + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * @param txDescs: DMATxDesc Pointer to the first Tx desc list + * @param txBuff: TxBuff Pointer to the first TxBuffer list + * @param count: Number of the used Tx desc in the list + * + * @retval HAL status + */ +HAL_Status HAL_GMAC_DMATxDescInit(struct GMAC_HANDLE *pGMAC, + struct GMAC_Desc *txDescs, + struct GMAC_Desc *txDescs_dma, + uint8_t *txBuff, uint8_t *txBuff_dma, uint32_t count) +{ + struct GMAC_Desc *desc; + uint32_t i = 0; + + HAL_ASSERT(pGMAC != NULL); + HAL_ASSERT(txDescs != NULL); + HAL_ASSERT(txDescs_dma != NULL); + HAL_ASSERT(txBuff != NULL); + HAL_ASSERT(txBuff_dma != NULL); + + pGMAC->txDescIdx = 0; + + pGMAC->txDescs = txDescs; + pGMAC->txDescs_dma = txDescs_dma; + pGMAC->txBuf = txBuff; + pGMAC->txBuf_dma = txBuff_dma; + pGMAC->txSize = count; + + /* Fill each DMATxDesc descriptor with the right values */ + for (i = 0; i < count; i++) { + /* Get the pointer on the ith member of the Tx Desc list */ + desc = txDescs + i; + + desc->des0 = 0; + desc->des1 = 0; + desc->des2 = 0; + desc->des3 = 0; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the DMA Rx descriptors in chain mode. + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * @param rxDescs: DMATxDesc Pointer to the first Rx desc list + * @param rxBuff: RxBuff Pointer to the first RxBuffer list + * @param count: Number of the used Rx desc in the list + * + * @retval HAL status + */ +HAL_Status HAL_GMAC_DMARxDescInit(struct GMAC_HANDLE *pGMAC, + struct GMAC_Desc *rxDescs, + struct GMAC_Desc *rxDescs_dma, + uint8_t *rxBuff, uint8_t *rxBuff_dma, uint32_t count) +{ + struct GMAC_Desc *desc; + uint32_t i = 0; + + HAL_ASSERT(pGMAC != NULL); + HAL_ASSERT(rxDescs != NULL); + HAL_ASSERT(rxDescs_dma != NULL); + HAL_ASSERT(rxBuff != NULL); + HAL_ASSERT(rxBuff_dma != NULL); + + pGMAC->rxDescIdx = 0; + + pGMAC->rxDescs = rxDescs; + pGMAC->rxDescs_dma = rxDescs_dma; + pGMAC->rxBuf = rxBuff; + pGMAC->rxBuf_dma = rxBuff_dma; + pGMAC->rxSize = count; + + /* Fill each DMARxDesc descriptor with the right values */ + for (i = 0; i < count; i++) { + /* Get the pointer on the ith member of the Rx Desc list */ + desc = rxDescs + i; + + desc->des0 = (uint32_t)(uint64_t)(rxBuff_dma + i * HAL_GMAC_MAX_PACKET_SIZE); + desc->des1 = 0; + desc->des2 = 0; + desc->des3 = GMAC_DESC3_OWN | GMAC_DESC3_BUF1V | GMAC_DESC3_IOC; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Handle GMAC interrupt for transfer. + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * + * @return IRQ status + */ +eGMAC_IRQ_Status HAL_GMAC_IRQHandler(struct GMAC_HANDLE *pGMAC) +{ + eGMAC_IRQ_Status status = DMA_UNKNOWN; + uint32_t intrStatus; + + HAL_ASSERT(pGMAC != NULL); + + intrStatus = READ_REG(pGMAC->pReg->DMA_CH0_STATUS); + /* ABNORMAL interrupts */ + if (intrStatus & DMA_CHAN_STATUS_AIS) { + if (intrStatus & DMA_CHAN_STATUS_RBU) { + pGMAC->extraStatus.rxBufUnavIRQ++; + status = DMA_RX_ERROR; + } + if (intrStatus & DMA_CHAN_STATUS_RPS) { + pGMAC->extraStatus.rxProcessStoppedIRQ++; + status = DMA_RX_ERROR; + } + if (intrStatus & DMA_CHAN_STATUS_RWT) { + pGMAC->extraStatus.rxWatchdogIRQ++; + status = DMA_RX_ERROR; + } + if (intrStatus & DMA_CHAN_STATUS_ETI) { + pGMAC->extraStatus.txEarlyIRQ++; + status = DMA_TX_ERROR; + } + if (intrStatus & DMA_CHAN_STATUS_TPS) { + pGMAC->extraStatus.rxProcessStoppedIRQ++; + status = DMA_TX_ERROR; + } + if (intrStatus & DMA_CHAN_STATUS_FBE) { + pGMAC->extraStatus.fatalBusErrorIRQ++; + status = DMA_TX_ERROR; + } + } + + /* TX/RX NORMAL interrupts */ + if (intrStatus & DMA_CHAN_STATUS_NIS) { + pGMAC->extraStatus.normalIRQN++; + if (intrStatus & DMA_CHAN_STATUS_RI) { + uint32_t value; + + value = READ_REG(pGMAC->pReg->DMA_CH0_INTERRUPT_ENABLE); + if (value & DMA_CHAN_INTR_ENA_RIE) { + pGMAC->extraStatus.rxNormalIRQN++; + status |= DMA_HANLE_RX; + } + } + if (intrStatus & DMA_CHAN_STATUS_TI) { + pGMAC->extraStatus.txNormallIRQN++; + status |= DMA_HANLE_TX; + } + if (intrStatus & DMA_CHAN_STATUS_ERI) { + pGMAC->extraStatus.rxEarlyIRQ++; + } + } + + /* + * Clear the interrupt by writing a logic 1 to the chanX interrupt + * status [21-0] expect reserved bits [5-3] + */ + WRITE_REG(pGMAC->pReg->DMA_CH0_STATUS, intrStatus & 0x3fffc7); + + return status; +} + +/** + * @brief Adjust timing register by link status. + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * @param txDelay: RGMII tx delayline, only available for RGMII, set to 0 if RMII. + * @param rxDelay: RGMII rx delayline, only available for RGMII, set to 0 if RMII. + * + * @return HAL status + */ +HAL_Status HAL_GMAC_AdjustLink(struct GMAC_HANDLE *pGMAC, int32_t txDelay, + int32_t rxDelay) +{ + uint32_t ctrl; + + HAL_ASSERT(pGMAC != NULL); + + ctrl = READ_REG(pGMAC->pReg->MAC_CONFIGURATION); + ctrl |= GMAC_CORE_INIT; + + /* Flow Control operation */ + if (pGMAC->phyStatus.pause) { + GMAC_FlowCtrl(pGMAC, pGMAC->phyStatus.duplex, HAL_GMAC_FLOW_AUTO, + HAL_PAUSE_TIME); + } + + if (!pGMAC->phyStatus.duplex) { + ctrl &= ~pGMAC->link.duplex; + } else { + ctrl |= pGMAC->link.duplex; + } + + ctrl &= ~pGMAC->link.speedMask; + switch (pGMAC->phyStatus.speed) { + case PHY_SPEED_1000M: + ctrl |= pGMAC->link.speed1000; + break; + case PHY_SPEED_100M: + ctrl |= pGMAC->link.speed100; + break; + case PHY_SPEED_10M: + ctrl |= pGMAC->link.speed10; + break; + default: + HAL_DBG("broken speed: %d\n", pGMAC->phyStatus.speed); + + return HAL_ERROR; + } + + switch (pGMAC->phyStatus.interface) { + case PHY_INTERFACE_MODE_RMII: + HAL_GMAC_SetToRMII(pGMAC); + HAL_GMAC_SetRMIISpeed(pGMAC, pGMAC->phyStatus.speed); + break; + case PHY_INTERFACE_MODE_RGMII: + HAL_GMAC_SetToRGMII(pGMAC, txDelay, rxDelay); + HAL_GMAC_SetRGMIISpeed(pGMAC, pGMAC->phyStatus.speed); + break; + default: + HAL_DBG("broken phy interface: %d\n", pGMAC->phyStatus.interface); + + return HAL_ERROR; + } + + ctrl |= GMAC_CONFIG_TE; + WRITE_REG(pGMAC->pReg->MAC_CONFIGURATION, ctrl); + + return HAL_OK; +} + +/** + * @brief Start the GMAC work after configuration. + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * @param addr: MAC address. + * + * @return HAL status + */ +#define GENMASK(h, l) (((1U << ((h) - (l) + 1)) - 1) << (l)) +#define DMA_AXI_WR_OSR_LMT GENMASK(27, 24) +#define DMA_AXI_WR_OSR_LMT_SHIFT 24 +#define DMA_AXI_RD_OSR_LMT GENMASK(19, 16) +#define DMA_AXI_RD_OSR_LMT_SHIFT 16 +#define DMA_AXI_OSR_MAX 0xf + +HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr) +{ + uint32_t mmc_mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | + MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; + uint32_t mode = SF_DMA_MODE; + uint32_t value; + int32_t limit = 10; + uint32_t hwCap; + int32_t rxFifosz; + int32_t txFifosz; + + HAL_ASSERT(pGMAC != NULL); + HAL_ASSERT(addr != NULL); + + /* GMAC Software Reset */ + value = READ_REG(pGMAC->pReg->DMA_MODE); + WRITE_REG(pGMAC->pReg->DMA_MODE, value | DMA_MODE_SWR); + /* Wait for software Reset */ + HAL_DelayMs(100); + while (limit--) { + if (!(READ_REG(pGMAC->pReg->DMA_MODE) & DMA_MODE_SWR)) { + break; + } + HAL_DelayMs(10); + } + if (limit <= 0) { + HAL_DBG("DMA_MODE_SWR stuck\n"); + + return HAL_TIMEOUT; + } + + HAL_DelayMs(100); + value = READ_REG(pGMAC->pReg->DMA_SYSBUS_MODE); + value &= ~DMA_AXI_WR_OSR_LMT; + value |= (0x0 & DMA_AXI_OSR_MAX) << DMA_AXI_WR_OSR_LMT_SHIFT; + + value &= ~DMA_AXI_RD_OSR_LMT; + value |= (0x2 & DMA_AXI_OSR_MAX) << DMA_AXI_RD_OSR_LMT_SHIFT; + + /* DMA init */ + WRITE_REG(pGMAC->pReg->DMA_SYSBUS_MODE, value | DMA_SYSBUS_MODE_BLEN16 | + DMA_SYSBUS_MODE_BLEN8 | DMA_SYSBUS_MODE_BLEN4); + + /* Mask interrupts by writing to CSR7 */ + WRITE_REG(pGMAC->pReg->DMA_CH0_INTERRUPT_ENABLE, DMA_CHAN_INTR_DEFAULT_MASK); + + hwCap = READ_REG(pGMAC->pReg->MAC_HW_FEATURE1); + /* Set the HW DMA mode and the COE */ + txFifosz = 128 << ((hwCap & GMAC_HW_TXFIFOSIZE) >> GMAC_HW_TXFIFOSIZE_SHIFT); + rxFifosz = 128 << ((hwCap & GMAC_HW_RXFIFOSIZE) >> GMAC_HW_RXFIFOSIZE_SHIFT); + + + /* init rx chan */ + value = READ_REG(pGMAC->pReg->DMA_CH0_RX_CONTROL); + value &= ~DMA_CH0_RX_CONTROL_RBSZ_MASK; + value |= (rxFifosz << DMA_CH0_RX_CONTROL_RBSZ_SHIFT) & DMA_CH0_RX_CONTROL_RBSZ_MASK; + value = value | (8 << DMA_CH0_RX_CONTROL_RXPBL_SHIFT); + WRITE_REG(pGMAC->pReg->DMA_CH0_RX_CONTROL, value); + WRITE_REG(pGMAC->pReg->DMA_CH0_RXDESC_LIST_ADDRESS, (uint32_t)(uint64_t)pGMAC->rxDescs_dma); + WRITE_REG(pGMAC->pReg->DMA_CH0_RXDESC_TAIL_POINTER, + (uint32_t)(uint64_t)(pGMAC->rxDescs_dma + pGMAC->rxSize)); + + value = READ_REG(pGMAC->pReg->DMA_CH0_CONTROL); + value = value | 1 << 16; + WRITE_REG(pGMAC->pReg->DMA_CH0_CONTROL, value); + + /* init tx chan */ + value = READ_REG(pGMAC->pReg->DMA_CH0_TX_CONTROL); + value = value | (32 << DMA_CH0_TX_CONTROL_TXPBL_SHIFT); + value |= DMA_CH0_TX_CONTROL_OSF; + WRITE_REG(pGMAC->pReg->DMA_CH0_TX_CONTROL, value); + + WRITE_REG(pGMAC->pReg->DMA_CH0_TXDESC_LIST_ADDRESS, (uint32_t)(uint64_t)pGMAC->txDescs_dma); + WRITE_REG(pGMAC->pReg->DMA_CH0_TXDESC_TAIL_POINTER, (uint32_t)(uint64_t)pGMAC->txDescs_dma); + + HAL_GMAC_WriteHWAddr(pGMAC, addr); + + /* core init */ + value = READ_REG(pGMAC->pReg->MAC_CONFIGURATION); + value |= GMAC_CORE_INIT; + WRITE_REG(pGMAC->pReg->MAC_CONFIGURATION, value); + + /* enable ipc */ + value = READ_REG(pGMAC->pReg->MAC_CONFIGURATION); + value |= GMAC_CONFIG_IPC; + WRITE_REG(pGMAC->pReg->MAC_CONFIGURATION, value); + + /* Enable the GMAC Rx/Tx */ + value = READ_REG(pGMAC->pReg->MAC_CONFIGURATION); + value |= GMAC_CONFIG_TE | GMAC_CONFIG_RE; + WRITE_REG(pGMAC->pReg->MAC_CONFIGURATION, value); + + GMAC_DMARXOpMode(pGMAC, mode, rxFifosz); + GMAC_DMATXOpMode(pGMAC, mode, txFifosz); + + WRITE_REG(pGMAC->pReg->MMC_RX_INTERRUPT_MASK, MMC_DEFAULT_MASK); + WRITE_REG(pGMAC->pReg->MMC_TX_INTERRUPT_MASK, MMC_DEFAULT_MASK); + WRITE_REG(pGMAC->pReg->MMC_IPC_RX_INTERRUPT_MASK, MMC_DEFAULT_MASK); + value = READ_REG(pGMAC->pReg->MMC_CONTROL); + value |= (mmc_mode & 0x3F); + WRITE_REG(pGMAC->pReg->MMC_CONTROL, value); + + HAL_ASSERT(pGMAC->txSize > 0); + HAL_ASSERT(pGMAC->rxSize > 0); + + /* Set TX and RX rings length */ + WRITE_REG(pGMAC->pReg->DMA_CH0_TXDESC_RING_LENGTH, pGMAC->txSize - 1); + WRITE_REG(pGMAC->pReg->DMA_CH0_RXDESC_RING_LENGTH, pGMAC->rxSize - 1); + + HAL_GMAC_EnableDmaIRQ(pGMAC); + + value = READ_REG(pGMAC->pReg->DMA_CH0_TX_CONTROL); + value |= DMA_CH0_TX_CONTROL_ST; + WRITE_REG(pGMAC->pReg->DMA_CH0_TX_CONTROL, value); + + value = READ_REG(pGMAC->pReg->DMA_CH0_RX_CONTROL); + value |= DMA_CH0_RX_CONTROL_SR; + WRITE_REG(pGMAC->pReg->DMA_CH0_RX_CONTROL, value); + + return HAL_OK; +} + +/** + * @brief Stop GMAC work. + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * + * @return HAL status + */ +HAL_Status HAL_GMAC_Stop(struct GMAC_HANDLE *pGMAC) +{ + struct GMAC_Desc *desc; + uint32_t value; + uint32_t i = 0; + + HAL_ASSERT(pGMAC != NULL); + + value = READ_REG(pGMAC->pReg->DMA_CH0_TX_CONTROL); + value &= ~DMA_CH0_TX_CONTROL_ST; + WRITE_REG(pGMAC->pReg->DMA_CH0_TX_CONTROL, value); + + value = READ_REG(pGMAC->pReg->DMA_CH0_RX_CONTROL); + value &= ~DMA_CH0_RX_CONTROL_SR; + WRITE_REG(pGMAC->pReg->DMA_CH0_RX_CONTROL, value); + + value = READ_REG(pGMAC->pReg->MAC_CONFIGURATION); + value &= ~(GMAC_CONFIG_TE | GMAC_CONFIG_RE); + WRITE_REG(pGMAC->pReg->MAC_CONFIGURATION, value); + + for (i = 0; i < pGMAC->txSize; i++) { + desc = pGMAC->txDescs + i; + desc->des0 = 0; + desc->des1 = 0; + desc->des2 = 0; + desc->des3 = 0; + } + + for (i = 0; i < pGMAC->rxSize; i++) { + desc = pGMAC->rxDescs + i; + desc->des0 = 0; + desc->des1 = 0; + desc->des2 = 0; + desc->des3 = 0; + } + + return HAL_OK; +} + +/** + * @brief Get current TX index in chain mode list. + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * + * @return current tx desc index + */ +uint32_t HAL_GMAC_GetTXIndex(struct GMAC_HANDLE *pGMAC) +{ + HAL_ASSERT(pGMAC != NULL); + + return pGMAC->txDescIdx; +} + +/** + * @brief Get current RX index in chain mode list. + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * + * @return current rx desc index + */ +uint32_t HAL_GMAC_GetRXIndex(struct GMAC_HANDLE *pGMAC) +{ + HAL_ASSERT(pGMAC != NULL); + + return pGMAC->txDescIdx; +} + +/** + * @brief Get current TX buffer. + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * + * @return HAL status + */ +uint8_t *HAL_GMAC_GetTXBuffer(struct GMAC_HANDLE *pGMAC) +{ + HAL_ASSERT(pGMAC != NULL); + + return pGMAC->txBuf + pGMAC->txDescIdx * HAL_GMAC_MAX_PACKET_SIZE; +} + +uint8_t *HAL_GMAC_GetTXBufferDMA(struct GMAC_HANDLE *pGMAC) +{ + HAL_ASSERT(pGMAC != NULL); + + return pGMAC->txBuf_dma + pGMAC->txDescIdx * HAL_GMAC_MAX_PACKET_SIZE; +} +/** + * @brief Get current RX buffer. + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * + * @return HAL status + */ +uint8_t *HAL_GMAC_GetRXBuffer(struct GMAC_HANDLE *pGMAC) +{ + HAL_ASSERT(pGMAC != NULL); + + return pGMAC->rxBuf + pGMAC->rxDescIdx * HAL_GMAC_MAX_PACKET_SIZE; +} + +uint8_t *HAL_GMAC_GetRXBufferDMA(struct GMAC_HANDLE *pGMAC) +{ + HAL_ASSERT(pGMAC != NULL); + + return pGMAC->rxBuf_dma + pGMAC->rxDescIdx * HAL_GMAC_MAX_PACKET_SIZE; +} + +/** + * @brief Send a packet with the length, clean packet' dcached memory before send. + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * @param packet: pointer to TX buffer. + * @param length: actual length for the packet. + * + * @return HAL status + */ +HAL_Status HAL_GMAC_Send(struct GMAC_HANDLE *pGMAC, void *packet, + uint32_t length) +{ + struct GMAC_Desc *desc; + uint32_t i; + + HAL_ASSERT(pGMAC != NULL); + HAL_ASSERT(packet != NULL); + + desc = pGMAC->txDescs + pGMAC->txDescIdx; + if (desc->des3 & GMAC_DESC3_OWN) { + HAL_DBG("%s(desc=%p, index=%ld) is busy\n", __func__, desc, + pGMAC->txDescIdx); + + return HAL_TIMEOUT; + } + + pGMAC->txDescIdx++; + pGMAC->txDescIdx %= pGMAC->txSize; + + desc->des0 = (uint32_t)(uint64_t)packet; + desc->des1 = 0; + desc->des2 = length | 1<<31; + /* + * Make sure that if HW sees the _OWN write below, it will see all the + * writes to the rest of the descriptor too. + */ + desc->des3 = GMAC_DESC3_OWN | GMAC_DESC3_FD | GMAC_DESC3_LD; + WRITE_REG(pGMAC->pReg->DMA_CH0_TXDESC_TAIL_POINTER, + (uint32_t)(uint64_t)(pGMAC->txDescs_dma + pGMAC->txDescIdx)); + + for (i = 0; i < 1000000; i++) { + if (!(desc->des3 & GMAC_DESC3_OWN)) { + return HAL_BUSY; + } + } + + if (desc->des3 & DES3_ERROR_SUMMARY) { + pGMAC->extraStatus.txErrors++; + } else { + pGMAC->extraStatus.txPktN++; + pGMAC->extraStatus.txBytesN += length; + } + + return HAL_OK; +} + +/** + * @brief Recvive a packet, invalidate packet's dcached memory after received. + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * @param length: pointer to length for RX packet. + * + * @return RX packet buffer pointer + */ +uint8_t *HAL_GMAC_Recv(struct GMAC_HANDLE *pGMAC, int32_t *length) +{ + struct GMAC_Desc *desc; + uint8_t *packet; + uint32_t des3; + + HAL_ASSERT(pGMAC != NULL); + HAL_ASSERT(length != NULL); + + *length = 0; + desc = pGMAC->rxDescs + pGMAC->rxDescIdx; + des3 = desc->des3; + if (des3 & GMAC_DESC3_OWN) { + HAL_DBG("%p: RX packet not available\n", desc->des0); + + return NULL; + } + + packet = pGMAC->rxBuf + (pGMAC->rxDescIdx * HAL_GMAC_MAX_PACKET_SIZE); + *length = des3 & 0x7fff; + + if (des3 & DES3_ERROR_SUMMARY) { + *length = 0; + pGMAC->extraStatus.rxErrors++; + + return NULL; + } + + /* + * If frame length is greater than skb buffer size + * (preallocated during init) then the packet is + * ignored + */ + if (*length > HAL_GMAC_MAX_FRAME_SIZE || *length <= ETH_FCS_LEN) { + HAL_DBG("len %ld is incorrect for max size (%d)\n", + *length, HAL_GMAC_MAX_FRAME_SIZE); + *length = 0; + pGMAC->extraStatus.rxErrors++; + + return NULL; + } + + *length -= ETH_FCS_LEN; + + pGMAC->extraStatus.rxPktN++; + pGMAC->extraStatus.rxBytesN += *length; + + return packet; +} + +/** + * @brief Clean dirty RX description. + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + */ +void HAL_GMAC_CleanRX(struct GMAC_HANDLE *pGMAC) +{ + struct GMAC_Desc *desc; + struct GMAC_Desc *desc_dma; + + HAL_ASSERT(pGMAC != NULL); + + /* Get the pointer on the ith member of the Tx Desc list */ + desc = pGMAC->rxDescs + pGMAC->rxDescIdx; + + desc->des0 = (uint32_t)(uint64_t)(pGMAC->rxBuf_dma + (pGMAC->rxDescIdx * + HAL_GMAC_MAX_PACKET_SIZE)); + desc->des1 = 0; + desc->des2 = 0; + desc->des3 = GMAC_DESC3_OWN | GMAC_DESC3_BUF1V | GMAC_DESC3_IOC; + + WRITE_REG(pGMAC->pReg->DMA_CH0_RXDESC_TAIL_POINTER, + (uint32_t)(uint64_t)(pGMAC->rxDescs_dma + pGMAC->rxDescIdx)); + + pGMAC->rxDescIdx++; + pGMAC->rxDescIdx %= pGMAC->rxSize; +} + +/** + * @brief Write MAC address to GMAC. + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * @param enetAddr: pointer to array for MAC address. + */ +void HAL_GMAC_WriteHWAddr(struct GMAC_HANDLE *pGMAC, uint8_t *enetAddr) +{ + uint32_t val = 0; + + HAL_ASSERT(pGMAC != NULL); + HAL_ASSERT(enetAddr != NULL); + + /* Update the GMAC address */ + val = (enetAddr[5] << 8) | + (enetAddr[4]); + WRITE_REG(pGMAC->pReg->MAC_ADDRESS0_HIGH, val); + + val = (enetAddr[3] << 24) | + (enetAddr[2] << 16) | + (enetAddr[1] << 8) | + (enetAddr[0]); + WRITE_REG(pGMAC->pReg->MAC_ADDRESS0_LOW, val); +} + +/** @} */ + +/** @defgroup GMAC_Exported_Functions_Group4 Init and DeInit Functions + + This section provides functions allowing to init and deinit the module: + + * @{ + */ + +/** + * @brief Initializes the Ethernet GMAC params including interface mode + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * @param pReg: base register for gmac controller. + * @param freq: pclk clock frequency rate. + * @param interface: RGMII or RMII. + * @param extClk: working clock from cru(output) or phy(external input clk). + * + * @retval HAL status + */ +HAL_Status HAL_GMAC_Init(struct GMAC_HANDLE *pGMAC, struct GMAC_REG *pReg, + uint32_t freq, eGMAC_PHY_Interface interface, + bool extClk) +{ + /* Check the GMAC handle allocation */ + HAL_ASSERT(pGMAC != NULL); + HAL_ASSERT(IS_GMAC_INSTANCE(pReg)); + + pGMAC->pReg = pReg; + + pGMAC->txDescIdx = 0; + pGMAC->rxDescIdx = 0; + /* Get CR bits depending on hclk value */ + if ((freq >= 20000000) && (freq < 35000000)) { + /* CSR Clock Range between 20-35 MHz */ + pGMAC->clkCSR = GMAC_CSR_20_35M; + } else if ((freq >= 35000000) && (freq < 60000000)) { + /* CSR Clock Range between 35-60 MHz */ + pGMAC->clkCSR = GMAC_CSR_35_60M; + } else if ((freq >= 60000000) && (freq < 100000000)) { + /* CSR Clock Range between 60-100 MHz */ + pGMAC->clkCSR = GMAC_CSR_60_100M; + } else if ((freq >= 100000000) && (freq < 150000000)) { + /* CSR Clock Range between 100-150 MHz */ + pGMAC->clkCSR = GMAC_CSR_100_150M; + } else if ((freq >= 150000000) && (freq < 250000000)) { + /* CSR Clock Range between 150-250 MHz */ + pGMAC->clkCSR = GMAC_CSR_150_250M; + } else { + /* CSR Clock Range between 250-300 MHz */ + pGMAC->clkCSR = GMAC_CSR_250_300M; + } + + pGMAC->link.duplex = GMAC_CONFIG_DM; + pGMAC->link.speed10 = GMAC_CONFIG_PS; + pGMAC->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS; + pGMAC->link.speed1000 = 0; + pGMAC->link.speedMask = GMAC_CONFIG_FES | GMAC_CONFIG_PS; + + pGMAC->mac.miiAddrShift = 21; + pGMAC->mac.miiAddrMask = 0x03e00000; + pGMAC->mac.miiRegShift = 16; + pGMAC->mac.miiRegMask = 0x001f0000; + pGMAC->mac.clkCsrShift = 8; + pGMAC->mac.clkCsrMask = 0xf00; + + if (interface == PHY_INTERFACE_MODE_RGMII) { + HAL_GMAC_SetToRGMII(pGMAC, 0, 0); /* update delayline at link */ + } else { + HAL_GMAC_SetToRMII(pGMAC); + } + + HAL_GMAC_SetExtclkSrc(pGMAC, extClk); + + return HAL_OK; +} + +/** + * @brief DeInitialize the GMAC peripheral. + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * @return HAL status + */ +HAL_Status HAL_GMAC_DeInit(struct GMAC_HANDLE *pGMAC) +{ + /* TO-DO */ + return HAL_OK; +} + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_GMAC_MODULE_ENABLED */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_gmac_3568.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_gmac_3568.c new file mode 100644 index 000000000..6da4c7675 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_gmac_3568.c @@ -0,0 +1,205 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#if defined(SOC_RK3568) && defined(HAL_GMAC_MODULE_ENABLED) + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup GMAC + * @{ + */ + +/** @defgroup GMAC_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ + +#define HIWORD_UPDATE(val, mask, shift) \ + ((val) << (shift) | (mask) << ((shift) + 16)) + +#define GRF_BIT(nr) (1 << (nr) | 1 << (nr+16)) +#define GRF_CLR_BIT(nr) (1 << (nr+16)) + +#define DELAY_ENABLE(soc, tx, rx) \ + (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ + ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) + +#define RK3568_GRF_GMAC0_CON0 0X0380 +#define RK3568_GRF_GMAC0_CON1 0X0384 +#define RK3568_GRF_GMAC1_CON0 0X0388 +#define RK3568_GRF_GMAC1_CON1 0X038c + +/* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */ +#define RK3568_GMAC_GMII_MODE GRF_BIT(7) +#define RK3568_GMAC_PHY_INTF_SEL_RGMII \ + (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) +#define RK3568_GMAC_PHY_INTF_SEL_RMII \ + (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) +#define RK3568_GMAC_FLOW_CTRL GRF_BIT(3) +#define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) +#define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) +#define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) +#define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) +#define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) + +/* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */ +#define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) +#define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) + +/********************* Private Structure Definition **************************/ + +/********************* Private Variable Definition ***************************/ + +/********************* Private Function Definition ***************************/ + +/** @} */ +/********************* Public Function Definition ****************************/ + +/** @defgroup GMAC_Exported_Functions_Group5 Other Functions + * @{ + */ + +/** + * @brief Set RGMII Mode. + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * @param txDelay: RGMII tx delayline + * @param rxDelay: RGMII rx delayline + */ +void HAL_GMAC_SetToRGMII(struct GMAC_HANDLE *pGMAC, + int32_t txDelay, int32_t rxDelay) +{ + uint32_t *con0, *con1; + + con0 = (uint32_t *)((pGMAC->pReg == GMAC1) ? &(GRF->MAC1_CON0) : + &(GRF->MAC0_CON0)); + con1 = (uint32_t *)((pGMAC->pReg == GMAC1) ? &(GRF->MAC1_CON1) : + &(GRF->MAC0_CON1)); + + WRITE_REG(*con1, + RK3568_GMAC_PHY_INTF_SEL_RGMII | + RK3568_GMAC_RXCLK_DLY_ENABLE | + RK3568_GMAC_TXCLK_DLY_ENABLE); + + WRITE_REG(*con0, + RK3568_GMAC_CLK_RX_DL_CFG(rxDelay) | + RK3568_GMAC_CLK_TX_DL_CFG(txDelay)); +} + +/** + * @brief Set RMII Mode. + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + */ +void HAL_GMAC_SetToRMII(struct GMAC_HANDLE *pGMAC) +{ + uint32_t *con1, *cruCon, val; + + con1 = (uint32_t *)((pGMAC->pReg == GMAC1) ? &(GRF->MAC1_CON1) : + &(GRF->MAC0_CON1)); + + WRITE_REG(*con1, RK3568_GMAC_PHY_INTF_SEL_RMII); + + cruCon = (uint32_t *)((pGMAC->pReg == GMAC1) ? &(CRU->CRU_CLKSEL_CON[33]) : + &(CRU->CRU_CLKSEL_CON[31])); + /* RMII mode */ + val = HIWORD_UPDATE(0x1, 0x3, 0); + /* clock from io if it was */ + /* val |= HIWORD_UPDATE(0x1, 0x1, 2); */ + /* ref clock sel 50M */ + val |= HIWORD_UPDATE(0x1, 0x3, 8); + /* clock speed 25M */ + val |= HIWORD_UPDATE(0x1, 0x1, 3); + WRITE_REG(*cruCon, val); +} + +/** + * @brief Set external clock source select. + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * @param extClk: 0: select clk_mac as the clock of mac + * 1: select external phy clock as the clock of mac + */ +void HAL_GMAC_SetExtclkSrc(struct GMAC_HANDLE *pGMAC, bool extClk) +{ + uint32_t *cruCon, val; + uint32_t clksel = 0; + + cruCon = (uint32_t *)((pGMAC->pReg == GMAC1) ? &(CRU->CRU_CLKSEL_CON[33]) : + &(CRU->CRU_CLKSEL_CON[31])); + + if (extClk) { + clksel = 1; + } + + val = HIWORD_UPDATE(clksel, 0x1, 2); + WRITE_REG(*cruCon, val); +} + +/** + * @brief Set RGMII speed. + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * @param speed: RGMII speed 10/100/1000 + */ +void HAL_GMAC_SetRGMIISpeed(struct GMAC_HANDLE *pGMAC, int32_t speed) +{ + eCLOCK_Name clkID; + uint32_t rate; + int32_t ret; + + switch (speed) { + case 10: + rate = 2500000; + break; + case 100: + rate = 25000000; + break; + case 1000: + rate = 125000000; + break; + default: + HAL_DBG_ERR("unknown speed value for GMAC speed=%ld", speed); + + return; + } + + if (pGMAC->phyStatus.interface == PHY_INTERFACE_MODE_RMII) { + clkID = (pGMAC->pReg == GMAC1) ? SCLK_GMAC1_RMII_SPEED : + SCLK_GMAC0_RMII_SPEED; + } else { + clkID = (pGMAC->pReg == GMAC1) ? SCLK_GMAC1_RGMII_SPEED : + SCLK_GMAC0_RGMII_SPEED; + } + + ret = HAL_CRU_ClkSetFreq(clkID, rate); + if (ret) { + HAL_DBG_ERR("%s: set clk_mac_speed rate %ld failed %ld\n", + __func__, rate, ret); + } +} + +/** + * @brief Set RGMII speed. + * @param pGMAC: pointer to a GMAC_HANDLE structure that contains + * the information for GMAC module. + * @param speed: RGMII speed 10/100 + */ +void HAL_GMAC_SetRMIISpeed(struct GMAC_HANDLE *pGMAC, int32_t speed) +{ + HAL_GMAC_SetRGMIISpeed(pGMAC, speed); +} + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* SOC_RK3568 && HAL_GMAC_MODULE_ENABLED */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_gpio.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_gpio.c new file mode 100644 index 000000000..da75ea17e --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_gpio.c @@ -0,0 +1,606 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#ifdef HAL_GPIO_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/** @defgroup GPIO_How_To_Use How To Use + * @{ + + The GPIO driver can be used as follows: + + APIs for GPIO io read write: + + 1. HAL_GPIO_GetPinLevel() to get EXT port level. + 2. HAL_GPIO_SetPinLevel() to set io level. + 3. HAL_GPIO_SetPinDirection() to set io direction. + + APIs for GPIO IRQ: + + 1. HAL_GPIO_EnableIRQ() to enable a GPIO IRQ. + 2. HAL_GPIO_DisableIRQ() to disable a GPIO IRQ. + 3. HAL_GPIO_IRQHandler() to handle GPIO IRQ isr. + 4. HAL_GPIO_IRQDispatch() to dispatch GPIO IRQ, should be implemented by User. + + Please open the macro definition HAL_GPIO_VIRTUAL_MODEL_FEATURE_ENABLED to support + + APIs for GPIO virtual model: + + 1. HAL_GPIO_EnableVirtualModel() to enable a GPIO virtual model. + 2. HAL_GPIO_DisableVirtualModel() to disable a GPIO virtual model. + 3. HAL_GPIO_SetVirtualModel() to configure GPIO pins virtual model. + + @} */ + +/** @defgroup GPIO_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ +#define UNUSED(X) (void)(X) /* To avoid gcc/g++ warnings */ + +/********************* Private Function Definition ***************************/ + +/** + * @brief Set the GPIO IRQ end of interrupt(EOI). + * @param pGPIO: The pointer of GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + */ +static void GPIO_SetEOI(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin) +{ +#if (GPIO_VER_ID >= 0x01000C2BU) + if (IS_GPIO_HIGH_PIN(pin)) { + pin &= 0xFFFF0000; + pGPIO->PORT_EOI_H = pin | (pin >> 16); + } else { + pin &= 0x0000FFFF; + pGPIO->PORT_EOI_L = pin | (pin << 16); + } +#else + { + pGPIO->PORTA_EOI = pin; + } +#endif +} + +/** + * @brief Get GPIO all pins irq type. + * @param pGPIO: the GPIO struct. + * @return uint32_t: type value. + */ +static uint32_t GPIO_GetIntType(struct GPIO_REG *pGPIO) +{ + uint32_t type; + +#if (GPIO_VER_ID >= 0x01000C2BU) + type = (pGPIO->INT_TYPE_L & 0xffff); + type |= ((pGPIO->INT_TYPE_H & 0xffff) << 16); + type |= (pGPIO->INT_BOTHEDGE_L & 0xffff); + type |= ((pGPIO->INT_BOTHEDGE_H & 0xffff) << 16); +#else + type = pGPIO->INTTYPE_LEVEL; + #ifdef GPIO_INT_BOTHEDGE_OFFSET + type |= pGPIO->INT_BOTHEDGE; + #endif +#endif + + return type; +} + +/** + * @brief Get GPIO all pins irq status. + * @param pGPIO: the GPIO struct. + * @return uint32_t: status value. + */ +static uint32_t GPIO_GetIntStatus(struct GPIO_REG *pGPIO) +{ + return pGPIO->INT_STATUS; +} + +/** @} */ +/********************* Public Function Definition ***************************/ + +/** @defgroup GPIO_Exported_Functions_Group1 State and Errors Functions + + This section provides functions allowing to get the status of the module: + + * @{ + */ + +/** + * @brief GPIO Configure IRQ trigger type. + * @param pGPIO: The pointer of GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + * @param mode: The value defined in @ref eGPIO_intType. + * @return HAL_Status. + */ +HAL_Status HAL_GPIO_SetIntType(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_intType mode) +{ + uint32_t both = 0, type = 0, plar = 0; + + UNUSED(both); + + switch (mode) { + case GPIO_INT_TYPE_EDGE_RISING: + type = 1; + plar = 1; + both = 0; + break; + case GPIO_INT_TYPE_EDGE_FALLING: + type = 1; + plar = 0; + both = 0; + break; + case GPIO_INT_TYPE_LEVEL_HIGH: + type = 0; + plar = 1; + both = 0; + break; + case GPIO_INT_TYPE_LEVEL_LOW: + type = 0; + plar = 0; + both = 0; + break; + case GPIO_INT_TYPE_EDGE_BOTH: + type = 0; + plar = 0; + both = 1; + break; + default: + + return HAL_INVAL; + } + +#if (GPIO_VER_ID >= 0x01000C2BU) + if (IS_GPIO_HIGH_PIN(pin)) { + pin &= 0xFFFF0000; + pGPIO->INT_TYPE_H = (type) ? (pin | (pin >> 16)) : (pin); + pGPIO->INT_POLARITY_H = (plar) ? (pin | (pin >> 16)) : (pin); + pGPIO->INT_BOTHEDGE_H = (both) ? (pin | (pin >> 16)) : (pin); + } else { + pin &= 0x0000FFFF; + pGPIO->INT_TYPE_L = (type) ? (pin | (pin << 16)) : (pin << 16); + pGPIO->INT_POLARITY_L = (plar) ? (pin | (pin << 16)) : (pin << 16); + pGPIO->INT_BOTHEDGE_L = (both) ? (pin | (pin << 16)) : (pin << 16); + } +#else + { + pGPIO->INTTYPE_LEVEL = (type) ? (pin) : (pGPIO->INTTYPE_LEVEL & ~(pin)); + pGPIO->INT_POLARITY = (plar) ? (pin) : (pGPIO->INT_POLARITY & ~(pin)); + #ifdef GPIO_INT_BOTHEDGE_OFFSET + pGPIO->INT_BOTHEDGE = (both) ? (pin) : (pGPIO->INT_BOTHEDGE & ~(pin)); + #endif + } +#endif + + return HAL_OK; +} + +/** + * @brief Set GPIO direction. + * @param pGPIO: the GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + * @param direction: direction value defined in @ref eGPIO_pinDirection. + * @return HAL_Status: HAL_OK if success. + */ +HAL_Status HAL_GPIO_SetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinDirection direction) +{ +#if (GPIO_VER_ID >= 0x01000C2BU) + if (IS_GPIO_HIGH_PIN(pin)) { + pin &= 0xFFFF0000; + pGPIO->SWPORT_DDR_H = (direction == GPIO_OUT) ? (pin | (pin >> 16)) : (pin); + } else { + pin &= 0x0000FFFF; + pGPIO->SWPORT_DDR_L = (direction == GPIO_OUT) ? (pin | (pin << 16)) : (pin << 16); + } +#else + if (direction == GPIO_OUT) { + pGPIO->SWPORTA_DDR |= pin; + } else { + pGPIO->SWPORTA_DDR &= ~pin; + } +#endif + + return HAL_OK; +} + +/** + * @brief Set GPIO direction. + * @param pGPIO: the GPIO struct. + * @param mPins: The pins defined in @ref ePINCTRL_GPIO_PINS. + * @param direction: value defined in @ref eGPIO_pinDirection. + * @return HAL_Status: HAL_OK if success. + */ +HAL_Status HAL_GPIO_SetPinsDirection(struct GPIO_REG *pGPIO, uint32_t mPins, eGPIO_pinDirection direction) +{ + uint8_t pin; + HAL_Status rc; + + HAL_ASSERT(IS_GPIO_INSTANCE(pGPIO)); + + for (pin = 0; pin < 32; pin++) { + if (mPins & (1 << pin)) { + rc = HAL_GPIO_SetPinDirection(pGPIO, (1 << pin), direction); + if (rc) { + return rc; + } + } + } + + return HAL_OK; +} + +/** + * @brief Get GPIO Pin data direction value. + * @param pGPIO: the GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + * @retval eGPIO_pinDirection: data direction value. + */ +eGPIO_pinDirection HAL_GPIO_GetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin) +{ + eGPIO_pinDirection direction; + uint32_t value; + +#if (GPIO_VER_ID >= 0x01000C2BU) + value = IS_GPIO_HIGH_PIN(pin) ? (pGPIO->SWPORT_DDR_H & (pin >> 16)) : (pGPIO->SWPORT_DDR_L & pin); +#else + value = pGPIO->SWPORTA_DDR & pin; +#endif + + if (value != (uint32_t)GPIO_IN) { + direction = GPIO_OUT; + } else { + direction = GPIO_IN; + } + + return direction; +} + +/** + * @brief Set GPIO pin level. + * @param pGPIO: The pointer of GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + * @param level: The level defined in @ref eGPIO_pinLevel. + * @return HAL_Status. + */ +HAL_Status HAL_GPIO_SetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinLevel level) +{ +#if (GPIO_VER_ID >= 0x01000C2BU) + if (IS_GPIO_HIGH_PIN(pin)) { + pin &= 0xFFFF0000; + pGPIO->SWPORT_DR_H = (level == GPIO_HIGH) ? (pin | (pin >> 16)) : (pin); + } else { + pin &= 0x0000FFFF; + pGPIO->SWPORT_DR_L = (level == GPIO_HIGH) ? (pin | (pin << 16)) : (pin << 16); + } +#else + if (level == GPIO_HIGH) { + pGPIO->SWPORTA_DR |= pin; + } else { + pGPIO->SWPORTA_DR &= ~pin; + } +#endif + + return HAL_OK; +} + +/** + * @brief Set GPIO pin level. + * @param pGPIO: The pointer of GPIO struct. + * @param mPins: The pins defined in @ref ePINCTRL_GPIO_PINS. + * @param level: The level defined in @ref eGPIO_pinLevel. + * @return HAL_Status. + */ +HAL_Status HAL_GPIO_SetPinsLevel(struct GPIO_REG *pGPIO, uint32_t mPins, eGPIO_pinLevel level) +{ + uint8_t pin; + HAL_Status rc; + + HAL_ASSERT(IS_GPIO_INSTANCE(pGPIO)); + + for (pin = 0; pin < 32; pin++) { + if (mPins & (1 << pin)) { + rc = HAL_GPIO_SetPinLevel(pGPIO, (1 << pin), level); + if (rc) { + return rc; + } + } + } + + return HAL_OK; +} + +/** @} */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO Functions + + This section provides functions allowing to IO controlling: + + * @{ + */ + +/** + * @brief Get GPIO Pin data value. + * @param pGPIO: the GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + * @retval eGPIO_pinLevel: data value. + */ +eGPIO_pinLevel HAL_GPIO_GetPinData(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin) +{ + eGPIO_pinLevel level; + uint32_t value; + +#if (GPIO_VER_ID >= 0x01000C2BU) + value = IS_GPIO_HIGH_PIN(pin) ? (pGPIO->SWPORT_DR_H & (pin >> 16)) : (pGPIO->SWPORT_DR_L & pin); +#else + value = pGPIO->SWPORTA_DR & pin; +#endif + + if (value != (uint32_t)GPIO_LOW) { + level = GPIO_HIGH; + } else { + level = GPIO_LOW; + } + + return level; +} + +/** + * @brief Get GPIO Pin ext bank level. + * @param pGPIO: the GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + * @retval GPIO_PinState: ext bank value. + */ +eGPIO_pinLevel HAL_GPIO_GetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin) +{ + uint32_t value; + +#if (GPIO_VER_ID >= 0x01000C2BU) + value = (pGPIO->EXT_PORT & pin); +#else + value = (pGPIO->EXT_PORTA & pin); +#endif + + return (value == (uint32_t)GPIO_LOW) ? GPIO_LOW : GPIO_HIGH; +} + +/** + * @brief Get GPIO Pin ext bank level. + * @param pGPIO: the GPIO struct. + * @retval uint32_t: ext bank value. + */ +uint32_t HAL_GPIO_GetBankLevel(struct GPIO_REG *pGPIO) +{ + uint32_t value; + +#if (GPIO_VER_ID >= 0x01000C2BU) + value = (pGPIO->EXT_PORT); +#else + value = (pGPIO->EXT_PORTA); +#endif + + return value; +} +/** @} */ + +/** @defgroup GPIO_Exported_Functions_Group3 Other Functions + * @{ + */ + +/** + * @brief Set GPIO irq enable. + * @param pGPIO: The pointer of GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + */ +void HAL_GPIO_EnableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin) +{ +#if (GPIO_VER_ID >= 0x01000C2BU) + if (IS_GPIO_HIGH_PIN(pin)) { + pin &= 0xFFFF0000; +#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED + pGPIO->INT_MASK_H = pin; +#endif + pGPIO->INT_EN_H = pin | (pin >> 16); + } else { + pin &= 0x0000FFFF; +#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED + pGPIO->INT_MASK_L = pin << 16; +#endif + pGPIO->INT_EN_L = pin | (pin << 16); + } +#else + { + pGPIO->INTEN |= pin; + pGPIO->INTMASK &= ~pin; + } +#endif +} + +/** + * @brief Set GPIO irq disable. + * @param pGPIO: The pointer of GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + */ +void HAL_GPIO_DisableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin) +{ +#if (GPIO_VER_ID >= 0x01000C2BU) + if (IS_GPIO_HIGH_PIN(pin)) { + pin &= 0xFFFF0000; + pGPIO->INT_EN_H = pin; +#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED + pGPIO->INT_MASK_H = pin | (pin >> 16); +#endif + } else { + pin &= 0x0000FFFF; + pGPIO->INT_EN_L = pin << 16; +#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED + pGPIO->INT_MASK_L = pin | (pin << 16); +#endif + } +#else + { + pGPIO->INTEN &= ~pin; + pGPIO->INTMASK |= pin; + } +#endif +} + +/** + * @brief GPIO IRQ callbacks. + * @param bank: The bank id. + * @param pin: The true pin index, 0~31. + * NOTE: This function Should not be modified, when the callback is needed, + * the HAL_GPIO_IRQDispatch could be implemented in the user file. + */ +__attribute__((weak)) void HAL_GPIO_IRQDispatch(eGPIO_bankId bank, uint32_t pin) +{ + UNUSED(bank); + UNUSED(pin); +} + +/** + * @brief GPIO IRQ hanlder. + * @param pGPIO: The pointer of GPIO struct. + * @param bank: The bank id. + */ +void HAL_GPIO_IRQHandler(struct GPIO_REG *pGPIO, eGPIO_bankId bank) +{ + uint32_t stat, type, clear; + uint32_t i; + uint32_t pin; + + stat = GPIO_GetIntStatus(pGPIO); + type = GPIO_GetIntType(pGPIO); + + /* Then process each pending GPIO interrupt */ + for (i = 0x0U; i < PIN_NUMBER_PER_BANK && stat != 0; i++) { + clear = 0x1U << i; + pin = HAL_BIT(i); + + if ((stat & clear) != 0x0U) { + /* If gpio is Edge-sensitive triggered, clear eoi */ + if (type & clear) { + GPIO_SetEOI(pGPIO, pin); + } + + /* Remove the pending interrupt bit from the clear */ + stat &= ~clear; + + /* And disptach the GPIO interrupt to the handler */ + HAL_GPIO_IRQDispatch(bank, i); + } + } +} + +#ifdef HAL_GPIO_VIRTUAL_MODEL_FEATURE_ENABLED + +/** + * @brief GPIO virtual model enable. + * @param pGPIO: The pointer of GPIO struct. + * @return HAL_Status. + */ +HAL_Status HAL_GPIO_EnableVirtualModel(struct GPIO_REG *pGPIO) +{ +#if (GPIO_VER_ID >= 0x01000C2BU) + pGPIO->GPIO_VIRTUAL_EN = 0x10001; + + return HAL_OK; +#endif + + return HAL_ERROR; +} + +/** + * @brief GPIO virtual model disable. + * @param pGPIO: The pointer of GPIO struct. + * @return HAL_Status. + */ +HAL_Status HAL_GPIO_DisableVirtualModel(struct GPIO_REG *pGPIO) +{ +#if (GPIO_VER_ID >= 0x01000C2BU) + pGPIO->GPIO_VIRTUAL_EN = 0x10000; + + return HAL_OK; +#endif + + return HAL_ERROR; +} + +/** + * @brief GPIO Configure pins for virtual model. + * @param pGPIO: The pointer of GPIO struct. + * @param pins: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + * @param vmode: The value defined in @ref eGPIO_VirtualModel. + * @return HAL_Status. + */ +HAL_Status HAL_GPIO_SetVirtualModel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_VirtualModel vmodel) +{ +#if (GPIO_VER_ID >= 0x01000C2BU) + uint32_t lowPins, highPins; + + lowPins = pin & 0x0000ffff; + highPins = (pin & 0xffff0000) >> 16; + +#if defined(GPIO0_EXP) + /* Support OS_A and OS_B */ + if (vmodel == GPIO_VIRTUAL_MODEL_OS_B) { + pGPIO->GPIO_REG_GROUP_L = lowPins << 16; + pGPIO->GPIO_REG_GROUP_H = highPins << 16; + } else { + pGPIO->GPIO_REG_GROUP_L = lowPins | (lowPins << 16); + pGPIO->GPIO_REG_GROUP_H = highPins | (highPins << 16); + } + + return HAL_OK; +#elif defined(GPIO0_EXP3) + /* Support 4 OS */ + switch (vmodel) { + case GPIO_VIRTUAL_MODEL_OS_A: + pGPIO->GPIO_REG_GROUP_L = lowPins | (lowPins << 16); + pGPIO->GPIO_REG_GROUP_H = highPins | (highPins << 16); + break; + case GPIO_VIRTUAL_MODEL_OS_B: + pGPIO->GPIO_REG_GROUP1_L = lowPins | (lowPins << 16); + pGPIO->GPIO_REG_GROUP1_H = highPins | (highPins << 16); + break; + case GPIO_VIRTUAL_MODEL_OS_C: + pGPIO->GPIO_REG_GROUP2_L = lowPins | (lowPins << 16); + pGPIO->GPIO_REG_GROUP2_H = highPins | (highPins << 16); + break; + case GPIO_VIRTUAL_MODEL_OS_D: + pGPIO->GPIO_REG_GROUP3_L = lowPins | (lowPins << 16); + pGPIO->GPIO_REG_GROUP3_H = highPins | (highPins << 16); + break; + default: + HAL_DBG("unknown gpio virtual model-%d\n", vmodel); + break; + } + + return HAL_OK; +#else +#error missing GPIO EXP register definition! +#endif +#endif + + return HAL_ERROR; +} + +#endif /* HAL_GPIO_VIRTUAL_MODEL_FEATURE_ENABLED */ + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_pinctrl_v2.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_pinctrl_v2.c new file mode 100644 index 000000000..9bc8590fa --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_pinctrl_v2.c @@ -0,0 +1,565 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#if defined(HAL_PINCTRL_MODULE_ENABLED) && (defined(SOC_RV1126) || defined(SOC_SWALLOW) || defined(SOC_RK3568) || defined(RKMCU_RK2106)) + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup PINCTRL + * @{ + */ + +/** @defgroup PINCTRL_How_To_Use How To Use + * @{ + + The pinctrl setting registers actually is bus grf registers, which include + iomux, drive strength, pull mode, slew rate and schmitt trigger. + + The pinctrl driver provides APIs: + - HAL_PINCTRL_SetIOMUX() to set pin iomux + - HAL_PINCTRL_SetParam() to set pin iomux/drive/pull/slewrate/schmitt/ie + + Example: + + HAL_PINCTRL_SetIOMUX(GPIO_BANK0, + GPIO_PIN_A0 | // I2S_IN_SCLK + GPIO_PIN_A1 | // I2S_IN_LRCK + GPIO_PIN_A2 | // I2S_IN_SDI0 + GPIO_PIN_A3, // I2S_IN_SDI1 + PIN_CONFIG_MUX_FUNC2); + + HAL_PINCTRL_SetParam(GPIO_BANK0, + GPIO_PIN_A0 | // I2S_IN_SCLK + GPIO_PIN_A1 | // I2S_IN_LRCK + GPIO_PIN_A2 | // I2S_IN_SDI0 + GPIO_PIN_A3, // I2S_IN_SDI1 + PIN_CONFIG_MUX_FUNC2 | + PIN_CONFIG_PUL_DOWN | + PIN_CONFIG_DRV_LEVEL2 | + PIN_CONFIG_SRT_FAST | + PIN_CONFIG_SMT_ENABLE); + @} */ + +/** @defgroup PINCTRL_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ + +#define _TO_MASK(w) ((1U << (w)) - 1U) +#define _TO_OFFSET(p, w) ((p) * (w)) +#define RK_GEN_VAL(p, v, w) ((_TO_MASK(w) << (_TO_OFFSET(p, w) + 16)) | (((v) & _TO_MASK(w)) << _TO_OFFSET(p, w))) + +/* + * Use HAL_DBG("pinctrl: write val = 0x%lx to register %p\n", VAL, ®); + * and HAL_DBG("pinctrl: readback register %p = 0x%lx\n", ®, REG); + * for debug + */ +#define _PINCTRL_WRITE(REG, DATA) \ +{ \ + REG = DATA; \ +} + +#if defined(GRF_GPIO0A_IOMUX_OFFSET) +#define IOMUX_BIT_PER_PIN (2) +#define IOMUX_PIN_PER_REG (16 / IOMUX_BIT_PER_PIN) +#define IOMUX_0(__B, __P) (GRF->GPIO##__B##__P##_IOMUX) +#define SET_IOMUX_0(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_0(_B, _P), RK_GEN_VAL(p, v, w)) +#define RK_SET_IOMUX_0(B, P, p, v) SET_IOMUX_0(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN) +#define SET_IOMUX(_GPIO, _PORT, pin, val) RK_SET_IOMUX_0(_GPIO, _PORT, pin, val) + +#elif defined(GRF_GPIO0A_IOMUX_H_OFFSET) +#define IOMUX_BIT_PER_PIN (4) +#define IOMUX_PIN_PER_REG (16 / IOMUX_BIT_PER_PIN) +#define IOMUX_0(__B, __P) (GRF->GPIO##__B##__P##_IOMUX_L) +#define IOMUX_1(__B, __P) (GRF->GPIO##__B##__P##_IOMUX_H) +#define SET_IOMUX_0(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_0(_B, _P), RK_GEN_VAL(p, v, w)) +#define SET_IOMUX_1(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_1(_B, _P), RK_GEN_VAL(p, v, w)) +#define RK_SET_IOMUX_0(B, P, p, v) SET_IOMUX_0(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN) +#define RK_SET_IOMUX_1(B, P, p, v) SET_IOMUX_1(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN) +#define SET_IOMUX(_GPIO, _PORT, pin, val) \ +{ \ + if ((pin % 8) < 4) { \ + RK_SET_IOMUX_0(_GPIO, _PORT, pin, val); \ + } else { \ + RK_SET_IOMUX_1(_GPIO, _PORT, pin, val); \ + } \ +} + +#elif defined(GRF_GPIO0A_IOMUX_0_OFFSET) +#define IOMUX_BIT_PER_PIN (8) +#define IOMUX_PIN_PER_REG (16 / IOMUX_BIT_PER_PIN) +#define IOMUX_0(__B, __P) (GRF->GPIO##__B##__P##_IOMUX_0) +#define IOMUX_1(__B, __P) (GRF->GPIO##__B##__P##_IOMUX_1) +#define IOMUX_2(__B, __P) (GRF->GPIO##__B##__P##_IOMUX_2) +#define IOMUX_3(__B, __P) (GRF->GPIO##__B##__P##_IOMUX_3) +#define SET_IOMUX_0(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_0(_B, _P), RK_GEN_VAL(p, v, w)) +#define SET_IOMUX_1(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_1(_B, _P), RK_GEN_VAL(p, v, w)) +#define SET_IOMUX_2(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_2(_B, _P), RK_GEN_VAL(p, v, w)) +#define SET_IOMUX_3(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_3(_B, _P), RK_GEN_VAL(p, v, w)) +#define RK_SET_IOMUX_0(B, P, p, v) SET_IOMUX_0(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN) +#define RK_SET_IOMUX_1(B, P, p, v) SET_IOMUX_1(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN) +#define RK_SET_IOMUX_2(B, P, p, v) SET_IOMUX_2(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN) +#define RK_SET_IOMUX_3(B, P, p, v) SET_IOMUX_3(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN) +#define SET_IOMUX(_GPIO, _PORT, pin, val) \ +{ \ + if ((pin % 8) < 2) { \ + RK_SET_IOMUX_0(_GPIO, _PORT, pin, val); \ + } else if ((pin % 8) < 4) { \ + RK_SET_IOMUX_1(_GPIO, _PORT, pin, val); \ + } else if ((pin % 8) < 6) { \ + RK_SET_IOMUX_2(_GPIO, _PORT, pin, val); \ + } else { \ + RK_SET_IOMUX_3(_GPIO, _PORT, pin, val); \ + } \ +} +#endif + +#if defined(GRF_GPIO0A_DS_OFFSET) +#define DS_BIT_PER_PIN (2) +#define DS_PIN_PER_REG (16 / DS_BIT_PER_PIN) +#define DS_0(__B, __P) (GRF->GPIO##__B##__P##_DS) +#define SET_DS_0(_B, _P, p, v, w) _PINCTRL_WRITE(DS_0(_B, _P), RK_GEN_VAL(p, v, w)) +#define RK_SET_DS_0(B, P, p, v) SET_DS_0(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN) +#define SET_DS(_GPIO, _PORT, pin, val) RK_SET_DS_0(_GPIO, _PORT, pin, val) + +#elif defined(GRF_GPIO0A_DS_H_OFFSET) +#define DS_BIT_PER_PIN (4) +#define DS_PIN_PER_REG (16 / DS_BIT_PER_PIN) +#define DS_0(__B, __P) (GRF->GPIO##__B##__P##_DS_L) +#define DS_1(__B, __P) (GRF->GPIO##__B##__P##_DS_L) +#define SET_DS_0(_B, _P, p, v, w) _PINCTRL_WRITE(DS_0(_B, _P), RK_GEN_VAL(p, v, w)) +#define SET_DS_1(_B, _P, p, v, w) _PINCTRL_WRITE(DS_1(_B, _P), RK_GEN_VAL(p, v, w)) +#define RK_SET_DS_0(B, P, p, v) SET_DS_0(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN) +#define RK_SET_DS_1(B, P, p, v) SET_DS_1(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN) +#define SET_DS(_GPIO, _PORT, pin, val) \ +{ \ + if ((pin % 8) < 4) { \ + RK_SET_DS_0(_GPIO, _PORT, pin, val); \ + } else { \ + RK_SET_DS_1(_GPIO, _PORT, pin, val); \ + } \ +} + +#elif defined(GRF_GPIO0A_DS_0_OFFSET) +#define DS_BIT_PER_PIN (8) +#define DS_PIN_PER_REG (16 / DS_BIT_PER_PIN) +#define DS_0(__B, __P) (GRF->GPIO##__B##__P##_DS_0) +#define DS_1(__B, __P) (GRF->GPIO##__B##__P##_DS_1) +#define DS_2(__B, __P) (GRF->GPIO##__B##__P##_DS_2) +#define DS_3(__B, __P) (GRF->GPIO##__B##__P##_DS_3) +#define SET_DS_0(_B, _P, p, v, w) _PINCTRL_WRITE(DS_0(_B, _P), RK_GEN_VAL(p, v, w)) +#define SET_DS_1(_B, _P, p, v, w) _PINCTRL_WRITE(DS_1(_B, _P), RK_GEN_VAL(p, v, w)) +#define SET_DS_2(_B, _P, p, v, w) _PINCTRL_WRITE(DS_2(_B, _P), RK_GEN_VAL(p, v, w)) +#define SET_DS_3(_B, _P, p, v, w) _PINCTRL_WRITE(DS_3(_B, _P), RK_GEN_VAL(p, v, w)) +#define RK_SET_DS_0(B, P, p, v) SET_DS_0(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN) +#define RK_SET_DS_1(B, P, p, v) SET_DS_1(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN) +#define RK_SET_DS_2(B, P, p, v) SET_DS_2(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN) +#define RK_SET_DS_3(B, P, p, v) SET_DS_3(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN) +#define SET_DS(_GPIO, _PORT, pin, val) \ +{ \ + if ((pin % 8) < 2) { \ + RK_SET_DS_0(_GPIO, _PORT, pin, val); \ + } else if ((pin % 8) < 4) { \ + RK_SET_DS_1(_GPIO, _PORT, pin, val); \ + } else if ((pin % 8) < 6) { \ + RK_SET_DS_2(_GPIO, _PORT, pin, val); \ + } else { \ + RK_SET_DS_3(_GPIO, _PORT, pin, val); \ + } \ +} +#endif + +#if defined(GRF_GPIO0A_P_OFFSET) +#define P_BIT_PER_PIN (2) +#define P_PIN_PER_REG (16 / P_BIT_PER_PIN) +#define P_0(__B, __P) (GRF->GPIO##__B##__P##_P) +#define SET_P_0(_B, _P, p, v, w) _PINCTRL_WRITE(P_0(_B, _P), RK_GEN_VAL(p, v, w)) +#define RK_SET_P_0(B, P, p, v) SET_P_0(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN) +#define SET_P(_GPIO, _PORT, pin, val) RK_SET_P_0(_GPIO, _PORT, pin, val) + +#elif defined(GRF_GPIO0A_P_H_OFFSET) +#define P_BIT_PER_PIN (4) +#define P_PIN_PER_REG (16 / P_BIT_PER_PIN) +#define P_0(__B, __P) (GRF->GPIO##__B##__P##_P_L) +#define P_1(__B, __P) (GRF->GPIO##__B##__P##_P_L) +#define SET_P_0(_B, _P, p, v, w) _PINCTRL_WRITE(P_0(_B, _P), RK_GEN_VAL(p, v, w)) +#define SET_P_1(_B, _P, p, v, w) _PINCTRL_WRITE(P_1(_B, _P), RK_GEN_VAL(p, v, w)) +#define RK_SET_P_0(B, P, p, v) SET_P_0(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN) +#define RK_SET_P_1(B, P, p, v) SET_P_1(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN) +#define SET_P(_GPIO, _PORT, pin, val) \ +{ \ + if ((pin % 8) < 4) { \ + RK_SET_P_0(_GPIO, _PORT, pin, val); \ + } else { \ + RK_SET_P_3(_GPIO, _PORT, pin, val); \ + } \ +} + +#elif defined(GRF_GPIO0A_P_0_OFFSET) +#define P_BIT_PER_PIN (8) +#define P_PIN_PER_REG (16 / P_BIT_PER_PIN) +#define P_0(__B, __P) (GRF->GPIO##__B##__P##_P_0) +#define P_1(__B, __P) (GRF->GPIO##__B##__P##_P_1) +#define P_2(__B, __P) (GRF->GPIO##__B##__P##_P_2) +#define P_3(__B, __P) (GRF->GPIO##__B##__P##_P_3) +#define SET_P_0(_B, _P, p, v, w) _PINCTRL_WRITE(P_0(_B, _P), RK_GEN_VAL(p, v, w)) +#define SET_P_1(_B, _P, p, v, w) _PINCTRL_WRITE(P_1(_B, _P), RK_GEN_VAL(p, v, w)) +#define SET_P_2(_B, _P, p, v, w) _PINCTRL_WRITE(P_2(_B, _P), RK_GEN_VAL(p, v, w)) +#define SET_P_3(_B, _P, p, v, w) _PINCTRL_WRITE(P_3(_B, _P), RK_GEN_VAL(p, v, w)) +#define RK_SET_P_0(B, P, p, v) SET_P_0(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN) +#define RK_SET_P_1(B, P, p, v) SET_P_1(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN) +#define RK_SET_P_2(B, P, p, v) SET_P_2(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN) +#define RK_SET_P_3(B, P, p, v) SET_P_3(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN) +#define SET_P(_GPIO, _PORT, pin, val) \ +{ \ + if ((pin % 8) < 2) { \ + RK_SET_P_0(_GPIO, _PORT, pin, val); \ + } else if ((pin % 8) < 4) { \ + RK_SET_P_1(_GPIO, _PORT, pin, val); \ + } else if ((pin % 8) < 6) { \ + RK_SET_P_2(_GPIO, _PORT, pin, val); \ + } else { \ + RK_SET_P_3(_GPIO, _PORT, pin, val); \ + } \ +} +#endif + +#ifdef SET_IOMUX +#define PINCTRL_SET_IOMUX(bank, pin, val) \ +{ \ + if (pin < 8) { \ + SET_IOMUX(bank, A, pin, val); \ + } else if (pin < 16) { \ + SET_IOMUX(bank, B, pin, val); \ + } else if (pin < 24) { \ + SET_IOMUX(bank, C, pin, val); \ + } else { \ + SET_IOMUX(bank, D, pin, val); \ + } \ +} +#endif + +#ifdef SET_DS +#define PINCTRL_SET_DS(bank, pin, val) \ +{ \ + if (pin < 8) { \ + SET_DS(bank, A, pin, val); \ + } else if (pin < 16) { \ + SET_DS(bank, B, pin, val); \ + } else if (pin < 24) { \ + SET_DS(bank, C, pin, val); \ + } else { \ + SET_DS(bank, D, pin, val); \ + } \ +} +#endif + +#ifdef SET_P +#define PINCTRL_SET_P(bank, pin, val) \ +{ \ + if (pin < 8) { \ + SET_P(bank, A, pin, val); \ + } else if (pin < 16) { \ + SET_P(bank, B, pin, val); \ + } else if (pin < 24) { \ + SET_P(bank, C, pin, val); \ + } else { \ + SET_P(bank, D, pin, val); \ + } \ +} +#endif + +/********************* Private Variable Definition ***************************/ + +/********************* Private Function Definition ***************************/ + +/** + * @brief Private function to set iomux for one pin. + * @param bank: pin bank channel. + * @param pin: pin index, 0~31. + * @param param: value to write. + * @return HAL_Status. + */ +static HAL_Status PINCTRL_SetIOMUX(eGPIO_bankId bank, uint8_t pin, uint32_t data) +{ +#ifdef PINCTRL_SET_IOMUX + switch (bank) { +#ifdef GPIO0 + case 0: + PINCTRL_SET_IOMUX(0, pin, data); + break; +#endif +#ifdef GPIO1 + case 1: + PINCTRL_SET_IOMUX(1, pin, data); + break; +#endif +#ifdef GPIO2 + case 2: + PINCTRL_SET_IOMUX(2, pin, data); + break; +#endif +#ifdef GPIO3 + case 3: + PINCTRL_SET_IOMUX(3, pin, data); + break; +#endif +#ifdef GPIO4 + case 4: + #ifdef SOC_RV1126 + if (pin < 2) { + GRF->GPIO4A_IOMUX_L = RK_GEN_VAL(pin % IOMUX_PIN_PER_REG, data, IOMUX_BIT_PER_PIN); + } + #else + PINCTRL_SET_IOMUX(4, pin, data); + #endif + break; +#endif + default: + HAL_DBG("unknown gpio%d\n", bank); + break; + } + + return HAL_OK; +#else + + return HAL_ERROR; +#endif +} + +/** + * @brief Private function to set drive strength for one pin. + * @param bank: pin bank channel. + * @param pin: pin index, 0~31. + * @param param: value to write. + * @return HAL_Status. + */ +static HAL_Status PINCTRL_SetDS(eGPIO_bankId bank, uint8_t pin, uint32_t data) +{ +#ifdef PINCTRL_SET_DS + switch (bank) { +#ifdef GPIO0 + case 0: + PINCTRL_SET_DS(0, pin, data); + break; +#endif +#ifdef GPIO1 + case 1: + PINCTRL_SET_DS(1, pin, data); + break; +#endif +#ifdef GPIO2 + case 2: + PINCTRL_SET_DS(2, pin, data); + break; +#endif +#ifdef GPIO3 + case 3: + PINCTRL_SET_DS(3, pin, data); + break; +#endif +#ifdef GPIO4 + case 4: + #ifdef SOC_RV1126 + if (pin < 2) { + GRF->GPIO4A_DS_L = RK_GEN_VAL(pin % DS_PIN_PER_REG, data, DS_BIT_PER_PIN); + } + #else + PINCTRL_SET_DS(4, pin, data); + #endif + break; +#endif + default: + HAL_DBG("unknown gpio%d\n", bank); + break; + } + + return HAL_OK; +#else + + return HAL_ERROR; +#endif +} + +/** + * @brief Private function to set pupd for one pin. + * @param bank: pin bank channel. + * @param pin: pin index, 0~31. + * @param param: value to write. + * @return HAL_Status. + */ +static HAL_Status PINCTRL_SetPUPD(eGPIO_bankId bank, uint8_t pin, uint32_t data) +{ +#ifdef PINCTRL_SET_P + switch (bank) { +#ifdef GPIO0 + case 0: + #ifdef SOC_RV1126 + if (pin < 8) { + SET_P(0, A, pin, data); + } else if (pin < 16) { + SET_P(0, B, pin, data); + } else if (pin < 20) { + GRF->GPIO0C_P_L = RK_GEN_VAL(pin % P_PIN_PER_REG, data, P_BIT_PER_PIN); + } else if (pin < 24) { + GRF->GPIO0C_P_H = RK_GEN_VAL(pin % P_PIN_PER_REG, data, P_BIT_PER_PIN); + } else { + SET_P(0, D, pin, data); + } + #else + PINCTRL_SET_P(0, pin, data); + #endif + break; +#endif +#ifdef GPIO1 + case 1: + PINCTRL_SET_P(1, pin, data); + break; +#endif +#ifdef GPIO2 + case 2: + PINCTRL_SET_P(2, pin, data); + break; +#endif +#ifdef GPIO3 + case 3: + PINCTRL_SET_P(3, pin, data); + break; +#endif +#ifdef GPIO4 + case 4: + #ifdef SOC_RV1126 + if (pin < 2) { + GRF->GPIO4A_P = RK_GEN_VAL(pin % P_PIN_PER_REG, data, P_BIT_PER_PIN); + } + #else + PINCTRL_SET_P(4, pin, data); + #endif + break; +#endif + default: + HAL_DBG("unknown gpio%d\n", bank); + break; + } + + return HAL_OK; +#else + + return HAL_ERROR; +#endif +} + +/** + * @brief Private function to configure one pin. + * @param bank: pin bank channel defined in @ref eGPIO_bankId. + * @param pin: pin index, 0~31. + * @param param: multi params defined in @ref ePINCTRL_configParam, + * @return HAL_Status. + */ +static HAL_Status PINCTRL_SetPinParam(eGPIO_bankId bank, uint8_t pin, uint32_t param) +{ + HAL_Status rc = HAL_OK; + + if (param & FLAG_MUX) { + rc |= PINCTRL_SetIOMUX(bank, pin, (uint8_t)((param & MASK_MUX) >> SHIFT_MUX)); + } + + if (param & FLAG_PUL) { + rc |= PINCTRL_SetPUPD(bank, pin, (uint8_t)((param & MASK_PUL) >> SHIFT_PUL)); + } + + if (param & FLAG_DRV) { + rc |= PINCTRL_SetDS(bank, pin, (uint8_t)((param & MASK_DRV) >> SHIFT_DRV)); + } + + return rc; +} +/** @} */ + +/********************* Public Function Definition ****************************/ + +/** @defgroup PINCTRL_Exported_Functions_Group1 Suspend and Resume Functions + + This section provides functions allowing to suspend and resume the module: + + * @{ + */ + +/** @} */ + +/** @defgroup PINCTRL_Exported_Functions_Group2 Init and DeInit Functions + + This section provides functions allowing to init and deinit the module: + + * @{ + */ +HAL_Status HAL_PINCTRL_Init(void) +{ + return HAL_OK; +} + +HAL_Status HAL_PINCTRL_DeInit(void) +{ + return HAL_OK; +} +/** @} */ + +/** @defgroup PINCTRL_Exported_Functions_Group3 IO Functions + + * @{ + */ + +/** + * @brief Public function to configure for multi pins. + * @param bank: pin bank channel defined in eGPIO_bankId. + * @param mPins: multi pins defined in @ref ePINCTRL_GPIO_PINS. + * @param param: multi params defined in @ref ePINCTRL_configParam. + * @return HAL_Status. + */ +HAL_Status HAL_PINCTRL_SetParam(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param) +{ + uint8_t pin; + HAL_Status rc; + + HAL_ASSERT(bank < GPIO_BANK_NUM); + + if (!(param & (FLAG_MUX | FLAG_PUL | FLAG_DRV | FLAG_SRT | FLAG_SMT))) { + return HAL_OK; + } + + for (pin = 0; pin < 32; pin++) { + if (mPins & (1 << pin)) { + rc = PINCTRL_SetPinParam(bank, pin, param); + if (rc) { + return rc; + } + } + } + + return HAL_OK; +} + +/** + * @brief Public function to set iomux for multi pins. + * @param bank: pin bank channel defined in eGPIO_bankId. + * @param mPins: multi pins defined in @ref ePINCTRL_GPIO_PINS. + * @param param: multi params defined in @ref ePINCTRL_configParam. + * @return HAL_Status. + */ +HAL_Status HAL_PINCTRL_SetIOMUX(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param) +{ + return HAL_PINCTRL_SetParam(bank, mPins, param); +} +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_PINCTRL_MODULE_ENABLED */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_timer.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_timer.c new file mode 100644 index 000000000..6ff6860c4 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_timer.c @@ -0,0 +1,307 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#ifdef HAL_TIMER_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup TIMER + * @{ + */ + +/** @defgroup TIMER_How_To_Use How To Use + * @{ + + The TIMER driver can be used as follows: + + - IT mode: Resgister TIMER handler. + - Initialize the TIMER by calling HAL_TIMER_Init(): + - Set TIMER count by calling HAL_TIMER_SetCount(). + - Start the TIMER by calling HAL_TIMER_Start() or HAL_TIMER_Start_IT(). + - Stop the TIMER by calling HAL_TIMER_Stop() or HAL_TIMER_Stop_IT(). + + SYS_TIMER + + - SYS_TIMER is a rk timer fixed to serve the delay system. Invoke HAL_TIMER_SysTimerInit() to init. + + @} */ + +/** @defgroup TIMER_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ +#define TIMER_CONTROLREG_TIMER_MODE_FREE_RUNNING (0x0U << TIMER_CONTROLREG_TIMER_MODE_SHIFT) + +#define TIMER_CONTROLREG_TIMER_ENABLE_ENABLED (0x1U << TIMER_CONTROLREG_TIMER_ENABLE_SHIFT) +#define TIMER_CONTROLREG_TIMER_ENABLE_DISABLED (0x0U << TIMER_CONTROLREG_TIMER_ENABLE_SHIFT) + +#define TIMER_CONTROLREG_TIMER_INT_MASK_UNMASK (0x1U << TIMER_CONTROLREG_TIMER_INT_MASK_SHIFT) + +/********************* Private Structure Definition **************************/ + +/********************* Private Variable Definition ***************************/ + +/********************* Private Function Definition ***************************/ + +/** @} */ +/********************* Public Function Definition ****************************/ + +/** @defgroup TIMER_Exported_Functions_Group4 Init and DeInit Functions + + This section provides functions allowing to init and deinit module as follows: + + * @{ + */ + +/** + * @brief Timer init. + * @param pReg: Choose TIMER. + * @param mode: Choose TIMER mode. + * @return HAL_Status. + */ +HAL_Status HAL_TIMER_Init(struct TIMER_REG *pReg, eTIMER_MODE mode) +{ + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); +#ifdef SYS_TIMER + if (pReg == SYS_TIMER) { + return HAL_BUSY; + } +#endif + + WRITE_REG(pReg->CONTROLREG, mode << TIMER_CONTROLREG_TIMER_MODE_SHIFT); + + return HAL_OK; +} + +/** + * @brief System Timer init. + * @return HAL_Status. + * @attention this API allow direct use in the HAL layer. SYS_TTIMER is used for delay system. + */ +HAL_Status HAL_TIMER_SysTimerInit(struct TIMER_REG *pReg) +{ + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); + + if (READ_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK)) { + return HAL_OK; + } + + WRITE_REG(pReg->CONTROLREG, TIMER_FREE_RUNNING); + pReg->LOAD_COUNT[0] = 0xFFFFFFFFU; + pReg->LOAD_COUNT[1] = 0xFFFFFFFFU; + CLEAR_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_INT_MASK_MASK); + SET_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK); + + return HAL_OK; +} + +/** + * @brief Timer deinit. + * @param pReg: Choose TIMER. + * @return HAL_Status. + */ +HAL_Status HAL_TIMER_DeInit(struct TIMER_REG *pReg) +{ + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); +#ifdef SYS_TIMER + if (pReg == SYS_TIMER) { + return HAL_BUSY; + } +#endif + + WRITE_REG(pReg->CONTROLREG, 0); + + return HAL_OK; +} + +/** @} */ + +/** @defgroup TIMER_Exported_Functions_Group5 Other Functions + * @{ + */ + +/** + * @brief Start TIMER counter. + * @param pReg: Choose TIMER. + * @return HAL_Status. + */ +HAL_Status HAL_TIMER_Start(struct TIMER_REG *pReg) +{ + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); +#ifdef SYS_TIMER + if (pReg == SYS_TIMER) { + return HAL_BUSY; + } +#endif + + CLEAR_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_INT_MASK_MASK); + SET_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK); + + return HAL_OK; +} + +/** + * @brief Stop TIMER counter. + * @param pReg: Choose TIMER. + * @return HAL_Status. + * Just disable TIMER, and keep TIMER configuration. + */ +HAL_Status HAL_TIMER_Stop(struct TIMER_REG *pReg) +{ + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); +#ifdef SYS_TIMER + if (pReg == SYS_TIMER) { + return HAL_BUSY; + } +#endif + + CLEAR_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK); + + return HAL_OK; +} + +/** + * @brief Start TIMER counter in interrupt mode. + * @param pReg: Choose TIMER. + * @return HAL_Status. + */ +HAL_Status HAL_TIMER_Start_IT(struct TIMER_REG *pReg) +{ + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); +#ifdef SYS_TIMER + if (pReg == SYS_TIMER) { + return HAL_BUSY; + } +#endif + + SET_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_ENABLED | TIMER_CONTROLREG_TIMER_INT_MASK_UNMASK); + + return HAL_OK; +} + +/** + * @brief Stop TIMER counter in interrupt mode. + * @param pReg: Choose TIMER. + * @return HAL_Status. + * Just disable TIMER, and keep TIMER configuration. + */ +HAL_Status HAL_TIMER_Stop_IT(struct TIMER_REG *pReg) +{ + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); +#ifdef SYS_TIMER + if (pReg == SYS_TIMER) { + return HAL_BUSY; + } +#endif + + CLEAR_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK); + + return HAL_OK; +} + +/** + * @brief Set TIMER count number. + * @param pReg: Choose TIMER. + * @param timerCount: TIMER counter loading number. + * @return HAL_Status. + * Set timer count number. + */ +HAL_Status HAL_TIMER_SetCount(struct TIMER_REG *pReg, uint64_t timerCount) +{ + uint64_t loadCount = 0; + + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); +#ifdef SYS_TIMER + if (pReg == SYS_TIMER) { + return HAL_BUSY; + } +#endif + + loadCount = timerCount; + pReg->LOAD_COUNT[0] = (loadCount & 0xffffffff); + pReg->LOAD_COUNT[1] = ((loadCount >> 32) & 0xffffffff); + + return HAL_OK; +} + +/** + * @brief Get TIMER count number. + * @param pReg: Choose TIMER. + * @return uint64_t: Current conut number. + */ +HAL_SECTION_SRAM_CODE +uint64_t HAL_TIMER_GetCount(struct TIMER_REG *pReg) +{ + uint32_t high, low, temp; + + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); + + do { + high = pReg->CURRENT_VALUE[1]; + low = pReg->CURRENT_VALUE[0]; + temp = pReg->CURRENT_VALUE[1]; + } while (high != temp); + + return ((uint64_t)high << 32) | low; +} + +/** + * @brief Clear TIMER interrupt status. + * @param pReg: Choose TIMER. + * @return HAL_Status: HAL_OK. + */ +HAL_Status HAL_TIMER_ClrInt(struct TIMER_REG *pReg) +{ + uint32_t timeOut = 1000; + + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); + + pReg->INTSTATUS = 0x1; + while (pReg->INTSTATUS && timeOut) { + timeOut--; + } + + if (timeOut == 0) { + return HAL_TIMEOUT; + } else { + return HAL_OK; + } +} + +/** + * @brief TIMER0 interrupt handler. + * @return HAL_Status: HAL_OK. + * Clear interrupt status. + */ +__attribute__((weak)) HAL_Status HAL_TIMER0_Handler(void) +{ + HAL_TIMER_ClrInt(TIMER0); + + return HAL_OK; +} + +/** + * @brief TIMER1 interrupt handler. + * @return HAL_Status: HAL_OK. + * Clear interrupt status. + */ +__attribute__((weak)) HAL_Status HAL_TIMER1_Handler(void) +{ + HAL_TIMER_ClrInt(TIMER1); + + return HAL_OK; +} + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_TIMER_MODULE_ENABLED */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/system_rk3568.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/system_rk3568.c new file mode 100644 index 000000000..a8c33ec56 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/system_rk3568.c @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" +#include "soc.h" + +/* The frequency of SYSTEM_CLOCK is determined by the previous firmware. */ +#define SYSTEM_CLOCK 816000000U + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System Initialization + *----------------------------------------------------------------------------*/ +// void SystemInit (void) +// { +// #if defined(HAL_AP_CORE) && defined(HAL_DCACHE_MODULE_ENABLED) +// /* do not use global variables because this function is called before +// reaching pre-main. RW section may be overwritten afterwards. */ + +// // Invalidate entire Unified TLB +// __set_TLBIALL(0); + +// // Invalidate entire branch predictor array +// __set_BPIALL(0); +// __DSB(); +// __ISB(); + +// // Invalidate instruction cache and flush branch target cache +// __set_ICIALLU(0); +// __DSB(); +// __ISB(); + +// // Invalidate data cache +// L1C_InvalidateDCacheAll(); +// #endif + +// #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) +// // Enable FPU +// __FPU_Enable(); +// #endif + +// #if defined(HAL_AP_CORE) && defined(HAL_DCACHE_MODULE_ENABLED) +// // Create Translation Table +// MMU_CreateTranslationTable(); + +// // Enable MMU +// MMU_Enable(); + +// // Enable Caches +// L1C_EnableCaches(); +// L1C_EnableBTAC(); +// #endif + +// #if defined(HAL_MCU_CORE) && defined(HAL_INTMUX_MODULE_ENABLED) +// HAL_INTMUX_Init(); +// #endif +// } + +// void DataInit (void) +// { +// #ifdef HAL_AP_CORE + +// typedef struct { +// unsigned long* dest; +// unsigned long wlen; +// } __zero_table_t; + +// extern const __zero_table_t __zero_table_start__; +// extern const __zero_table_t __zero_table_end__; + +// for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { +// for (unsigned long i = 0u; i < pTable->wlen; ++i) { +// pTable->dest[i] = 0u; +// } +// } +// #endif /* HAL_AP_CORE */ +// } diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/test_gmac.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/test_gmac.c new file mode 100644 index 000000000..6edd00727 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/test_gmac.c @@ -0,0 +1,753 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_bsp.h" +#include "hal_base.h" +#include "hal_gmac.h" +#include "usyscall.h" +#if (defined(HAL_GMAC_MODULE_ENABLED) || defined(HAL_GMAC1000_MODULE_ENABLED)) + +/*************************** GMAC DRIVER ****************************/ + +/***************************** MACRO Definition ******************************/ +#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') + +/***************************** Structure Definition **************************/ + +/***************************** Function Declare ******************************/ + +/********************* Private MACRO Definition ******************************/ +#define GMAC_BUS_MAX 2 + +#define ARCH_DMA_MINALIGN 64 + +#define GMAC_DESCRIPTOR_SIZE 16 +#define GMAC_DESCRIPTORS_TX 8 +#define GMAC_DESCRIPTORS_RX 8 +#define GMAC_DESC_TX_SIZE HAL_GMAC_ALIGN(GMAC_DESCRIPTORS_TX * GMAC_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN) +#define GMAC_DESC_RX_SIZE HAL_GMAC_ALIGN(GMAC_DESCRIPTORS_RX * GMAC_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN) + +#define GMAC_RX_BUFFER_SIZE (GMAC_DESCRIPTORS_RX * HAL_GMAC_MAX_PACKET_SIZE) +#define GMAC_TX_BUFFER_SIZE (GMAC_DESCRIPTORS_TX * HAL_GMAC_MAX_PACKET_SIZE) + +/* Basic mode control register. */ +#define BMCR_RESV 0x003f /* Unused... */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_CTST 0x0080 /* Collision test */ +#define BMCR_FULLDPLX 0x0100 /* Full duplex */ +#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ +#define BMCR_ISOLATE 0x0400 /* Isolate data paths from MII */ +#define BMCR_PDOWN 0x0800 /* Enable low power state */ +#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ +#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ +#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ +#define BMCR_RESET 0x8000 /* Reset to default state */ +#define BMCR_SPEED10 0x0000 /* Select 10Mbps */ + +#define GMAC_TEST_TIMES 16 + +/********************* Private Structure Definition **************************/ +/* GMAC consumer config data. */ +struct GMAC_ETH_CONFIG { + struct GMAC_HANDLE instance; + const struct HAL_GMAC_DEV *halDev; + eGMAC_PHY_Interface mode; + uint32_t speed; + uint32_t maxSpeed; + uint16_t phyAddr; + + bool extClk; + + /* phy reset gpio */ + struct GPIO_REG *resetGpioBank; + ePINCTRL_GPIO_PINS resetGpioNum; + uint32_t resetDelayMs[3]; + + int32_t txDelay; + int32_t rxDelay; + + struct GMAC_Desc *txDescs; + struct GMAC_Desc *txDescs_dma; + struct GMAC_Desc *rxDescs; + struct GMAC_Desc *rxDescs_dma; + + uint8_t *txBuff; + uint8_t *txBuff_dma; + uint8_t *rxBuff; + uint8_t *rxBuff_dma; + + /* MAC address info, hw address */ + uint8_t macAddr[6]; +}; + +/********************* Private Variable Definition ***************************/ + + +static uint8_t dstAddr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; + +#if defined(HAL_GMAC_MODULE_ENABLED) && defined(SOC_RK3568) +static struct GMAC_ETH_CONFIG ethConfigTable[] = +{ + { + .halDev = &g_gmac0Dev, + .mode = PHY_INTERFACE_MODE_RGMII, + .maxSpeed = 1000, + .phyAddr = 1, + + .extClk = false, + + .resetGpioBank = GPIO3, + .resetGpioNum = GPIO_PIN_A4, + .resetDelayMs = { 0, 20, 100 }, + + .txDelay = 0x2f, + .rxDelay = 0x00, + }, + + + // { + // .halDev = &g_gmac1Dev, + // .mode = PHY_INTERFACE_MODE_RGMII, + // .maxSpeed = 1000, + // .phyAddr = 1, + + // .extClk = false, + + // .resetGpioBank = GPIO4, + // .resetGpioNum = GPIO_PIN_B6, + // .resetDelayMs = { 0, 20, 100 }, + + // .txDelay = 0x4f, + // .rxDelay = 0x26, + // }, +}; +#endif + + + + +#endif + +/********************* Private Function Definition ***************************/ + +static void Dump_Hex(char *message, uint8_t *ptr, uint16_t buflen) +{ + unsigned char *buf = (unsigned char *)ptr; + int i, j; + + printf("%s package at %p, len: %d: \n", message, ptr, buflen); + for (i = 0; i < buflen; i += 16) { + printf("%08X: ", i); + + for (j = 0; j < 16; j++) { + if (i + j < buflen) { + printf("%02X ", buf[i + j]); + } else { + printf(" "); + } + } + printf(" "); + + for (j = 0; j < 16; j++) { + if (i + j < buflen) { + printf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.'); + } + } + printf("\n"); + } +} + +static void print_desc(struct GMAC_HANDLE *pGMAC) +{ + struct GMAC_Desc *desc; + int nIndex; + + printf("\n"); + + if (pGMAC->rxDescs) { + desc = pGMAC->rxDescs; + for (nIndex = 0; nIndex < pGMAC->rxSize; nIndex++) { + desc = pGMAC->rxDescs + nIndex; + printf("rx_desc[%d]@0x%08lx={0x%lx, 0x%lx, 0x%lx, 0x%lx};\n", + nIndex, (uint64_t)desc, desc->des0, desc->des1, desc->des2, desc->des3); + } + } + + if (pGMAC->txDescs) { + desc = pGMAC->txDescs; + for (nIndex = 0; nIndex < pGMAC->txSize; nIndex++) { + desc = pGMAC->txDescs + nIndex; + printf("tx_desc[%d]@0x%08lx={0x%lx, 0x%lx, 0x%lx, 0x%lx};\n", + nIndex, (uint64_t)desc, desc->des0, desc->des1, desc->des2, desc->des3); + } + } +} + +static void Dump_Regs(struct GMAC_HANDLE *pGMAC) +{ + uint32_t *reg = (uint32_t *)pGMAC->pReg; + int i; + + printf("\n"); + + for (i = 0; i < (0x200 / 0x4); i++) { + printf("offset_0x%08x: %08lx %08lx %08lx %08lx\n", i * 0x10, + *((volatile const uint32_t *)(reg + 0x4 * i)), *(volatile const uint32_t *)((reg + 0x4 * i + 1)), + *((volatile const uint32_t *)(reg + 0x4 * i + 2)), *((volatile const uint32_t *)(reg + 0x4 * i + 3))); + } + + reg = reg + 0x1000 / 4; + + for (i = 0; i < (0x100 / 0x4); i++) { + printf("offset_0x%08x: %08lx %08lx %08lx %08lx\n", i * 0x10 + 0x1000, + *((volatile const uint32_t *)(reg + 0x4 * i)), *((volatile const uint32_t *)(reg + 0x4 * i + 1)), + *((volatile const uint32_t *)(reg + 0x4 * i + 2)), *((volatile const uint32_t *)(reg + 0x4 * i + 3))); + } +} + +static void PHY_Dump(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE *pGMAC) +{ + int data, i; + + for (i = 0; i < 32; i++) { + data = HAL_GMAC_MDIORead(pGMAC, eth->phyAddr, i); + if (data < 0) { + printf("phy_dump: %d --> faild\n", i); + break; + } + + if (i % 8 == 7) { + printf("%d --> %08X\n ", i, data); + } else { + printf("%d --> %08X\n\n", i, data); + } + } + printf("\n"); +} + +static void GMAC_PHY_Reset(struct GMAC_ETH_CONFIG *config) +{ + if (config->resetGpioBank) { + HAL_GPIO_SetPinDirection(config->resetGpioBank, + config->resetGpioNum, + GPIO_OUT); + HAL_GPIO_SetPinLevel(config->resetGpioBank, + config->resetGpioNum, + GPIO_HIGH); + HAL_DelayMs(config->resetDelayMs[0]); + HAL_GPIO_SetPinLevel(config->resetGpioBank, + config->resetGpioNum, + GPIO_LOW); + HAL_DelayMs(config->resetDelayMs[1]); + HAL_GPIO_SetPinLevel(config->resetGpioBank, + config->resetGpioNum, + GPIO_HIGH); + HAL_DelayMs(config->resetDelayMs[2]); + } +} + +static inline void NET_Random_ETHAddr(uint8_t *addr) +{ + addr[0] = 0xe6; + addr[1] = 0x47; + addr[2] = 0xcd; + addr[3] = 0x20; + addr[4] = 0xcf; + addr[5] = 0xd9; +} + +static inline void NET_Random_Package(uint8_t *addr, uint16_t len) +{ + unsigned int seed = HAL_TIMER_GetCount(SYS_TIMER) | 0xffffffff; + uint16_t i; + + for (i = 0; i < len; i++) { + addr[i] = rand(); + } +} + +static void PHY_Update_Links(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE *pGMAC, + uint8_t id) +{ + HAL_Status status; + + status = HAL_GMAC_PHYStartup(pGMAC); + if (status) { + printf("HAL_PHY_Startup() failed: %d\n", status); + + return; + } + HAL_DelayMs(10000); + + status = HAL_GMAC_PHYUpdateLink(pGMAC); + if (status == HAL_OK) { + if (pGMAC->phyStatus.link) { + status = HAL_GMAC_PHYParseLink(pGMAC); + if (PHY_SPEED_1000M == pGMAC->phyStatus.speed) { + printf("Phy%d: 1000M link speed\n", id); + } else if (PHY_SPEED_100M == pGMAC->phyStatus.speed) { + printf("Phy%d: 100M link speed\n", id); + } else { + printf("Phy%d: 10M link speed\n", id); + } + + if (PHY_DUPLEX_HALF == pGMAC->phyStatus.duplex) { + printf("Phy%d: half dumplex\n", id); + } else { + printf("Phy%d: full dumplex\n", id); + } + + if (pGMAC->phyStatus.pause) { + printf("Phy%d: flow control rx/tx\n", id); + } else { + printf("Phy%d: flow control off\n", id); + } + + status = HAL_GMAC_AdjustLink(pGMAC, eth->txDelay, eth->rxDelay); + if (status != HAL_OK) { + printf("HAL_GMAC_AdjustLink() failed: %d\n", status); + } + + printf("Phy%d: link up.\n", id); + } else { + printf("Phy%d: link down.\n", id); + } + } +} + +/* interrupt service routine polling */ +static HAL_Status GMAC_ETH_IRQ(struct GMAC_HANDLE *pGMAC) +{ + HAL_Status status; + + /* enter interrupt */ + /* rt_interrupt_enter(); */ + status = HAL_GMAC_IRQHandler(pGMAC); + + if (status & DMA_HANLE_RX) { + /* a frame has been received */ + return 1; + } + + return 0; + /* leave interrupt */ + /* rt_interrupt_leave(); */ +} + + +static void *malloc_align(size_t size, size_t align, uintptr_t va, uintptr_t *pa) +{ + void *align_ptr; + // void *ptr; + size_t align_size; + + /* align the alignment size to 4 byte */ + align = ((align + 0x03) & ~0x03); + + /* get total aligned size */ + align_size = ((size + 0x03) & ~0x03); + /* allocate memory block from heap */ + // ptr = malloc(align_size); + + if (naive_mmap(&va, pa, align_size, true) < 0){ + HAL_DBG("Alloc failed\n"); + } + // printf("%p,%p\n",(void *)va, *pa); + // void* ptr = (void *)va; + // if (ptr != 0) { + // /* the allocated memory block is aligned */ + // if (((uint64_t)ptr & (align - 1)) == 0) { + // align_ptr = (void *)((uint64_t)ptr + align); + // } else { + // align_ptr = (void *)(((uint64_t)ptr + (align - 1)) & ~(align - 1)); + // } + + // /* set the pointer before alignment pointer to the real pointer */ + // *((uint64_t *)((uint64_t)align_ptr - sizeof(void *))) = (uint64_t)ptr; + + // ptr = align_ptr; + // } + + return (void *)va; +} + +static void free_align(void *ptr) +{ + void *real_ptr; + + real_ptr = (void *)*(uint64_t *)((uint64_t)ptr - sizeof(void *)); + free(real_ptr); + +} + +/********************* Public Function Definition ****************************/ + +static HAL_Status GMAC_Send_Test(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE *pGMAC, + uint16_t len) +{ + uint8_t *ptr = NULL; + HAL_Status status; + + if (!pGMAC->phyStatus.link) { + HAL_DBG("pGMAC->phyStatus.link: %d", pGMAC->phyStatus.link); + return -1; + } + + /* Check the frame length. */ + if (len > HAL_GMAC_MAX_FRAME_SIZE) { + return -1; + } + + ptr = (uint8_t *)HAL_GMAC_GetTXBuffer(pGMAC); + HAL_DBG("txPtr:%p\n", ptr); + memcpy(ptr, dstAddr, 6); + memcpy(ptr + 6, eth->macAddr, 6); + ptr[12] = 0x40; + ptr[13] = 0x06; + ptr[14] = 0x00; + ptr[15] = 0x01; + NET_Random_Package(ptr + 16, len - 16); + + if (len > 60) { + /* index */ + ptr[50] = pGMAC->txDescIdx; + } + + /* dump packages */ + Dump_Hex("Tx", ptr, len); + + // HAL_DCACHE_CleanByRange((uint64_t)ptr, len); + uint8_t * ptr_dma = (uint8_t *)HAL_GMAC_GetTXBufferDMA(pGMAC); + status = HAL_GMAC_Send(pGMAC, ptr_dma, len); + if (status) { + printf("GMAC send failed: %d\n", status); + } + + return status; +} + +static uint16_t GMAC_Recv_Test(struct GMAC_HANDLE *pGMAC) +{ + uint8_t *ptr = NULL; + HAL_Status status; + int32_t size; + + if (!pGMAC->phyStatus.link) { + HAL_DBG("pGMAC->phyStatus.link: %d", pGMAC->phyStatus.link); + return -1; + } + + status = GMAC_ETH_IRQ(pGMAC); + ptr = HAL_GMAC_Recv(pGMAC, &size); + while (status && ptr) { + if (size > 0 && ptr) { + /* dump packages */ + Dump_Hex("Rx", ptr, size); + // HAL_DCACHE_InvalidateByRange((uint64_t)ptr, size); + HAL_GMAC_CleanRX(pGMAC); + } else { + printf("GMAC recv failed: %ld\n", size); + + return -1; + } + ptr = HAL_GMAC_Recv(pGMAC, &size); + } + return 0; +} + +static HAL_Status GMAC_Memory_Init(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE *pGMAC) +{ + + uintptr_t tx_va = 0x1000000000, tx_pa = 0; + if (naive_mmap(&tx_va, &tx_pa, GMAC_DESC_TX_SIZE, true) < 0){ + HAL_DBG("TX Desc alloc failed\n"); + } + eth->txDescs = (struct GMAC_Desc *)0x1000000000; + eth->txDescs_dma = (struct GMAC_Desc *)tx_pa; + + uintptr_t rx_va = 0x1000400000, rx_pa = 0; + if (naive_mmap(&rx_va, &rx_pa, GMAC_DESC_RX_SIZE, true) < 0){ + HAL_DBG("RX Desc alloc failed\n"); + } + eth->rxDescs = (struct GMAC_Desc *)0x1000400000; + eth->rxDescs_dma = (struct GMAC_Desc *)rx_pa; + + if (!eth->rxDescs || !eth->txDescs_dma || + !eth->txDescs || !eth->txDescs_dma){ + return -1; + } + + HAL_DBG("rx:%p, %p\n",eth->rxDescs, eth->rxDescs_dma); + HAL_DBG("tx:%p, %p\n",eth->txDescs, eth->txDescs_dma); + + + uintptr_t txbuf_va = 0x1000800000, txbuf_pa = 0; + eth->txBuff = malloc_align(GMAC_TX_BUFFER_SIZE, ARCH_DMA_MINALIGN, txbuf_va, &txbuf_pa); + eth->txBuff = (void *)0x1000800000; + eth->txBuff_dma = (void *)txbuf_pa; + + uintptr_t rxbuf_va = 0x1000c00000, rxbuf_pa = 0; + eth->rxBuff = malloc_align(GMAC_RX_BUFFER_SIZE, ARCH_DMA_MINALIGN, rxbuf_va, &rxbuf_pa); + eth->rxBuff = (void *)0x1000c00000; + eth->rxBuff_dma = (void *)rxbuf_pa; + + if (!eth->rxBuff || !eth->txBuff || + !eth->rxBuff_dma || !eth->txBuff_dma){ + return -1; + } + HAL_DBG("rx_buff:%p,%p\n",eth->rxBuff, eth->rxBuff_dma); + HAL_DBG("tx_buff:%p,%p,\n",eth->txBuff, eth->txBuff_dma); + memset(eth->rxDescs, 0, GMAC_DESC_RX_SIZE); + memset(eth->txDescs, 0, GMAC_DESC_TX_SIZE); + memset(eth->rxBuff, 0, GMAC_RX_BUFFER_SIZE); + // HAL_DCACHE_InvalidateByRange((uint64_t)eth->rxBuff, GMAC_RX_BUFFER_SIZE); + memset(eth->txBuff, 0, GMAC_TX_BUFFER_SIZE); + // HAL_DCACHE_CleanByRange((uint64_t)eth->txBuff, GMAC_TX_BUFFER_SIZE); + + HAL_GMAC_DMARxDescInit(pGMAC, eth->rxDescs, eth->rxDescs_dma, eth->rxBuff, eth->rxBuff_dma, GMAC_DESCRIPTORS_RX); + HAL_GMAC_DMATxDescInit(pGMAC, eth->txDescs, eth->txDescs_dma, eth->txBuff, eth->txBuff_dma, GMAC_DESCRIPTORS_TX); + + print_desc(pGMAC); + + return 0; +} + +static HAL_Status GMAC_Init(uint8_t id) +{ + struct GMAC_ETH_CONFIG *eth; + struct GMAC_HANDLE *pGMAC; + const struct HAL_GMAC_DEV *gmacDev; + struct GMAC_PHY_Config config; + eGMAC_PHY_Interface interface; + HAL_Status status; + uint32_t freq; + + HAL_ASSERT(id < GMAC_BUS_MAX); + + eth = ðConfigTable[id]; + if (!eth) { + return HAL_ERROR; + } + + pGMAC = ð->instance; + gmacDev = eth->halDev; + + /* MAC init */ + interface = eth->mode; + + if (interface == PHY_INTERFACE_MODE_RGMII) { + HAL_CRU_ClkSetFreq(gmacDev->clkID125M, 125000000); + } else { + HAL_CRU_ClkSetFreq(gmacDev->clkID50M, 50000000); + } + + freq = HAL_CRU_ClkGetFreq(gmacDev->pclkID); + HAL_GMAC_Init(pGMAC, gmacDev->pReg, freq, interface, eth->extClk); + + /* PHY Init */ + config.speed = eth->speed; + config.maxSpeed = eth->maxSpeed; + config.duplexMode = PHY_DUPLEX_FULL; + config.neg = PHY_AUTONEG_ENABLE; + config.interface = interface; + config.phyAddress = eth->phyAddr; + config.features = 0; + status = HAL_GMAC_PHYInit(pGMAC, &config); + if (status) { + printf("HAL_PHY_Init() failed: %d\n", status); + + return status; + } + + /* MAC Address */ + NET_Random_ETHAddr(eth->macAddr); + HAL_GMAC_WriteHWAddr(ð->instance, eth->macAddr); + + return 0; +} + +/*************************** GMAC TEST ****************************/ + +#ifdef SOC_RK3568 +/** + * @brief Config iomux for GMAC0 + */ +static void GMAC0_Iomux_Config(void) +{ + /* GMAC0 iomux */ + HAL_PINCTRL_SetIOMUX(GPIO_BANK2, + GPIO_PIN_B6, /* gmac0_rxd0 */ + PIN_CONFIG_MUX_FUNC1); + HAL_PINCTRL_SetIOMUX(GPIO_BANK2, + GPIO_PIN_C3 | /* gmac0_mdc */ + GPIO_PIN_C4 | /* gmac0_mdio */ + GPIO_PIN_C0 | /* gmac0_rxdvcrs */ + GPIO_PIN_B7 | /* gmac0_rxd1 */ + GPIO_PIN_A3 | /* gmac0_rxd2 */ + GPIO_PIN_A4 | /* gmac0_rxd3 */ + GPIO_PIN_A6 | /* gmac0_txd2 */ + GPIO_PIN_A7 | /* gmac0_txd3 */ + GPIO_PIN_A5, /* gmac0_rxclk */ + PIN_CONFIG_MUX_FUNC2); + HAL_PINCTRL_SetIOMUX(GPIO_BANK2, + GPIO_PIN_B3 | /* gmac0_txd0 */ + GPIO_PIN_B4 | /* gmac0_txd1 */ + GPIO_PIN_B5, /* gmac0_txen */ + PIN_CONFIG_MUX_FUNC1 | PIN_CONFIG_DRV_LEVEL2); + + HAL_PINCTRL_SetIOMUX(GPIO_BANK2, + GPIO_PIN_A7 | /* gmac0_txd3 */ + GPIO_PIN_A6, /* gmac0_txd2 */ + PIN_CONFIG_MUX_FUNC2 | PIN_CONFIG_DRV_LEVEL2); + HAL_PINCTRL_SetIOMUX(GPIO_BANK2, /* gmac0_txclk */ + GPIO_PIN_B0, + PIN_CONFIG_MUX_FUNC2 | PIN_CONFIG_DRV_LEVEL1); + +} +#endif + + +static void GMAC_Iomux_Config(uint8_t id) +{ + // if (id == 1) { + // GMAC1_M1_Iomux_Config(); + // } else if (id == 0) { + GMAC0_Iomux_Config(); + // } +} + + +/*************************** GMAC TEST MAIN ****************************/ + +#include "usyscall.h" + +// IPC_SERVER_INTERFACE(Ipc_intr, 1); +// IPC_SERVER_REGISTER_INTERFACES(IpIntrHandler, 1, Ipc_intr); + +int main() { + struct GMAC_ETH_CONFIG *eth; + struct GMAC_HANDLE *pGMAC; + int32_t bus, num = 0, i; + + HAL_DBG("GMAC Test:\n"); + + num = sizeof(ethConfigTable) / sizeof(struct GMAC_ETH_CONFIG); + HAL_DBG("GMAC Num: %ld\n", num); + for (bus = 0; bus < num; bus++) { + eth = ðConfigTable[bus]; + HAL_DBG("new pGmac\n"); + if (eth) { + pGMAC = ð->instance; + } else { + return -1; + } + + if (!mmap(0x2000000000ULL+ GMAC0_BASE, GMAC0_BASE, 0x10000, true)) { + printf("eth_hal: mmap GMAC0(%8x) failed\n", GMAC0); + exit(1); + } + + if (!mmap(0x2000000000ULL + GPIO2_BASE, GPIO2_BASE, 0x10000, true)) { + printf("eth_hal: mmap GPIO2(%8x) failed\n", GPIO2); + exit(1); + } + + if (!mmap(0x2000000000ULL + GPIO3_BASE, GPIO3_BASE, 0x10000, true)) { + printf("eth_hal: mmap GPIO3(%8x) failed\n", GPIO3); + exit(1); + } + + if (!mmap(0x2000000000ULL + GRF_BASE, GRF_BASE, 0x50000, true)) { + printf("eth_hal: mmap GRF(%8x) failed\n", GRF); + exit(1); + } + + if (!mmap(0x2000000000ULL + CRU_BASE, CRU_BASE, 0x10000, true)) { + printf("eth_hal: mmap CRU(%8x) failed\n", CRU); + exit(1); + } + if (!mmap(0x2000000000ULL + TIMER5_BASE, TIMER5_BASE, 32, true)) { + printf("eth_hal: mmap TIMER5(%8x) failed\n", TIMER5); + exit(1); + } + if (!mmap(0x2000000000ULL + PMUCRU_BASE, PMUCRU_BASE, 0x10000, true)) { + printf("eth_hal: mmap PMUCRU(%8x) failed\n", PMUCRU); + exit(1); + } + + HAL_TIMER_SysTimerInit(TIMER5); + + /* ionmux */ + GMAC_Iomux_Config(bus); + HAL_CRU_ClkEnable(eth->halDev->pclkGateID); + HAL_CRU_ClkEnable(eth->halDev->clkGateID125M); + HAL_CRU_ClkEnable(eth->halDev->clkGateID50M); + + /* Register irq */ + // register_irq(eth->halDev->irqNum, ); + /* PHY reset */ + GMAC_PHY_Reset(eth); + + /* GMAC Init */ + GMAC_Init(bus); + + GMAC_Memory_Init(eth, pGMAC); + + /* Enable GMAC and DMA transmission and reception */ + HAL_GMAC_Start(pGMAC, eth->macAddr); + + /* Update links information */ + PHY_Update_Links(eth, pGMAC, bus); + + /* Dump MAC Regs */ + Dump_Regs(pGMAC); + + /* Dump PHY Regs */ + // PHY_Dump(eth, pGMAC); + for (i = 0; i < GMAC_TEST_TIMES; i++) { + HAL_DBG("TEST %d\n", i); + + /* GMAC Send 64 bytes */ + HAL_DBG("--------------GMAC_Send_Test START!--------------\n"); + GMAC_Send_Test(eth, pGMAC, 64); + HAL_DBG("--------------GMAC_Send_Test END!--------------\n"); + + HAL_DelayMs(1000); + print_desc(pGMAC); + + /* GMAC Recv */ + HAL_DBG("--------------GMAC_Recv_Test START! -------------- \n"); + GMAC_Recv_Test(pGMAC); + HAL_DBG("--------------GMAC_Recv_Test END!!-------------- \n"); + + HAL_DelayMs(1000); + Dump_Regs(pGMAC); + } + HAL_CRU_ClkDisable(eth->halDev->pclkGateID); + HAL_CRU_ClkDisable(eth->halDev->clkGateID125M); + HAL_CRU_ClkDisable(eth->halDev->clkGateID50M); + + // free_align(eth->txBuff); + // free_align(eth->rxBuff); + HAL_DBG("done\n"); + } + exit(0); + return 0; +} + + +// typedef void (*isr_handler_t)(int vector, void *param); +// typedef void (*NVIC_IRQHandler)(void); + +// isr_handler_t interrupt_install(int vector, +// isr_handler_t handler, +// void *param, +// const char *name) +// { + +// HAL_NVIC_SetIRQHandler(vector, (NVIC_IRQHandler)handler); +// return handler; +// } + diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_base.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_base.h new file mode 100644 index 000000000..e131a5a08 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_base.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup HAL_BASE + * @{ + */ + +#ifndef _HAL_BASE_H_ +#define _HAL_BASE_H_ + +#include "hal_conf.h" +#include "hal_driver.h" +#include "hal_debug.h" + +/***************************** MACRO Definition ******************************/ + +/** @defgroup HAL_BASE_Exported_Definition_Group1 Basic Definition + * @{ + */ + +/** enter markrom usb upgrade */ +#define SYS_UPGRADE_FLAG (0xEF08A53C) +/** enter loader usb upgrade */ +#define LDR_UPGRADE_FLAG (0x5242C301) + +#define IS_TICKFREQ(f) (((f) == HAL_TICK_FREQ_1KHZ) || ((f) == HAL_TICK_FREQ_100HZ) || ((f) == HAL_TICK_FREQ_10HZ)) + +/***************************** Structure Definition **************************/ +typedef enum { + HAL_TICK_FREQ_10HZ = 100U, /**< 10 ticks per second, so it's 100ms/tick */ + HAL_TICK_FREQ_100HZ = 10U, /**< 100 ticks per second, so it's 10ms/tick */ + HAL_TICK_FREQ_1KHZ = 1U, /**< 1000 ticks per second, so it's 1ms/tick */ + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} eHAL_tickFreq; + +/** @} */ + +/***************************** Function Declare ******************************/ +/** @defgroup HAL_BASE_Public_Function_Declare Public Function Declare + * @{ + */ + +HAL_Status HAL_Init(void); +HAL_Status HAL_DeInit(void); +HAL_Status HAL_InitTick(uint32_t tickPriority); +HAL_Status HAL_IncTick(void); +uint32_t HAL_GetTick(void); +HAL_Status HAL_SetTickFreq(eHAL_tickFreq freq); +eHAL_tickFreq HAL_GetTickFreq(void); + +HAL_Status HAL_DelayUs(uint32_t us); +HAL_Status HAL_DelayMs(uint32_t ms); +HAL_Status HAL_CPUDelayUs(uint32_t us); +HAL_Status HAL_SystemCoreClockUpdate(uint32_t hz, eHAL_systickClkSource clkSource); + +uint64_t HAL_DivU64Rem(uint64_t numerator, uint32_t denominator, uint32_t *pRemainder); +uint64_t HAL_GetSysTimerCount(void); + +void HAL_CPU_EnterIdle(void); +#if defined(HAL_CPU_USAGE_ENABLED) +uint32_t HAL_GetCPUUsage(void); +#endif + +/** @} */ + +/********************* Public Function Definition ***************************/ +/** @defgroup HAL_BASE_Exported_Functions_Group5 Other Functions + * @{ + */ + +/** + * @brief uint64_t numerator / uint32_t denominator + * @param numerator + * @param denominator + * @return uint64_t result + */ +static inline uint64_t HAL_DivU64(uint64_t numerator, uint32_t denominator) +{ + return HAL_DivU64Rem(numerator, denominator, NULL); +} + +/** + * @brief uint32_t numerator / uint32_t denominator rounded to nearest integer + * @param numerator + * @param denominator + * @return uint32_t result rounded to nearest integer + */ +static inline uint32_t HAL_DivRoundClosest(uint32_t numerator, uint32_t denominator) +{ + return (numerator + (denominator / 2)) / denominator; +} + +/** @} */ + +#endif + +/** @} */ + +/** @} */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_bsp.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_bsp.h new file mode 100644 index 000000000..7ab0da026 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_bsp.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef __BSP_H__ +#define __BSP_H__ + +#include "hal_base.h" + +/***************************** MACRO Definition ******************************/ + +/***************************** Structure Definition **************************/ +#ifdef HAL_PL330_MODULE_ENABLED +extern struct HAL_PL330_DEV g_pl330Dev0; +extern struct HAL_PL330_DEV g_pl330Dev1; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +extern const struct HAL_SPI_DEV g_spi0Dev; +extern const struct HAL_SPI_DEV g_spi1Dev; +extern const struct HAL_SPI_DEV g_spi2Dev; +extern const struct HAL_SPI_DEV g_spi3Dev; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +extern const struct HAL_UART_DEV g_uart0Dev; +extern const struct HAL_UART_DEV g_uart1Dev; +extern const struct HAL_UART_DEV g_uart2Dev; +extern const struct HAL_UART_DEV g_uart3Dev; +extern const struct HAL_UART_DEV g_uart4Dev; +extern const struct HAL_UART_DEV g_uart5Dev; +extern const struct HAL_UART_DEV g_uart6Dev; +extern const struct HAL_UART_DEV g_uart7Dev; +extern const struct HAL_UART_DEV g_uart8Dev; +extern const struct HAL_UART_DEV g_uart9Dev; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +extern const struct HAL_I2C_DEV g_i2c0Dev; +extern const struct HAL_I2C_DEV g_i2c1Dev; +extern const struct HAL_I2C_DEV g_i2c2Dev; +extern const struct HAL_I2C_DEV g_i2c3Dev; +extern const struct HAL_I2C_DEV g_i2c4Dev; +extern const struct HAL_I2C_DEV g_i2c5Dev; +#endif + +#ifdef HAL_FSPI_MODULE_ENABLED +extern struct HAL_FSPI_HOST g_fspi0Dev; +#endif +#ifdef HAL_CANFD_MODULE_ENABLED +extern const struct HAL_CANFD_DEV g_can0Dev; +extern const struct HAL_CANFD_DEV g_can1Dev; +extern const struct HAL_CANFD_DEV g_can2Dev; +#endif + +#ifdef HAL_GMAC_MODULE_ENABLED +extern const struct HAL_GMAC_DEV g_gmac0Dev; +extern const struct HAL_GMAC_DEV g_gmac1Dev; +#endif + +#ifdef HAL_PCIE_MODULE_ENABLED +extern struct HAL_PCIE_DEV g_pcieDev; +#endif + +#ifdef HAL_PWM_MODULE_ENABLED +extern const struct HAL_PWM_DEV g_pwm0Dev; +extern const struct HAL_PWM_DEV g_pwm1Dev; +extern const struct HAL_PWM_DEV g_pwm2Dev; +extern const struct HAL_PWM_DEV g_pwm3Dev; +#endif +/***************************** Function Declare ******************************/ +void BSP_Init(void); + +#endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_conf.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_conf.h new file mode 100644 index 000000000..d1d3c8d52 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_conf.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + + +#ifndef _HAL_CONF_H_ +#define _HAL_CONF_H_ + +/* HAL CPU config */ +#define SOC_RK3568 +#define HAL_AP_CORE +#define SYS_TIMER TIMER5 /* System timer designation (RK TIMER) */ + +/* HAL Driver Config */ +// #define HAL_CACHE_ECC_MODULE_ENABLED +// #define HAL_CPU_TOPOLOGY_MODULE_ENABLED +#define HAL_CRU_MODULE_ENABLED +// #define HAL_DCACHE_MODULE_ENABLED +// #define HAL_DDR_ECC_MODULE_ENABLED +// #define HAL_FSPI_MODULE_ENABLED +// #define HAL_GIC_MODULE_ENABLED +#define HAL_GMAC_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +// #define HAL_GPIO_IRQ_GROUP_MODULE_ENABLED +// #define HAL_SPINLOCK_MODULE_ENABLED +// #define HAL_HWSPINLOCK_MODULE_ENABLED +// #define HAL_I2C_MODULE_ENABLED +// #define HAL_IRQ_HANDLER_MODULE_ENABLED +// #define HAL_MBOX_MODULE_ENABLED +// #define HAL_PCIE_MODULE_ENABLED +#define HAL_PINCTRL_MODULE_ENABLED +// #define HAL_PL330_MODULE_ENABLED +// #define HAL_PWM_MODULE_ENABLED +// #define HAL_SARADC_MODULE_ENABLED +// #define HAL_SMCCC_MODULE_ENABLED +// #define HAL_SNOR_MODULE_ENABLED +// #define HAL_SPI_MODULE_ENABLED +#define HAL_TIMER_MODULE_ENABLED +// #define HAL_TSADC_MODULE_ENABLED +// #define HAL_UART_MODULE_ENABLED +// #define HAL_WDT_MODULE_ENABLED +// #define HAL_CANFD_MODULE_ENABLED + +/* HAL_DBG SUB CONFIG */ +#define HAL_DBG_USING_LIBC_PRINTF +#define HAL_DBG_ON +#define HAL_DBG_INFO_ON +#define HAL_DBG_WRN_ON +#define HAL_DBG_ERR_ON +#define HAL_ASSERT_ON + +#ifdef HAL_SNOR_MODULE_ENABLED +#define HAL_SNOR_FSPI_HOST +#endif + +#ifdef HAL_GIC_MODULE_ENABLED +#define HAL_GIC_AMP_FEATURE_ENABLED +#define HAL_GIC_PREEMPT_FEATURE_ENABLED +//#define HAL_GIC_WAIT_LINUX_INIT_ENABLED +#endif + +#ifdef HAL_GPIO_MODULE_ENABLED +#define HAL_GPIO_IRQ_DISPATCH_FEATURE_ENABLED +#endif + +#ifdef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED +#define HAL_GPIO_IRQ_GROUP_PRIO_LEVEL_MAX (3) +#endif + +#endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_cru.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_cru.h new file mode 100644 index 000000000..95b309f91 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_cru.h @@ -0,0 +1,500 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +#ifdef HAL_CRU_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup CRU + * @{ + */ + +#ifndef _HAL_CRU_H_ +#define _HAL_CRU_H_ + +#include "hal_def.h" + +/*************************** MACRO Definition ****************************/ +/** @defgroup CRU_Exported_Definition_Group1 Basic Definition + * @{ + */ + +#ifdef HAL_CRU_DBG_ON +#define HAL_CRU_DBG(fmt, arg...) HAL_SYSLOG("[HAL CRU] " fmt, ##arg) +#else +#define HAL_CRU_DBG(fmt, arg...) do { if (0) HAL_SYSLOG("[HAL CRU] " fmt, ##arg); } while (0) +#endif + +#define MHZ 1000000 +#define KHZ 1000 + +#ifndef PLL_INPUT_OSC_RATE +#define PLL_INPUT_OSC_RATE (24 * MHZ) +#endif + +#define GENVAL_D16(x, h, l) ((uint32_t)(((x) & HAL_GENMASK(h, l)) / 16)) +#define GENVAL_D16_REM(x, h, l) ((uint32_t)(((x) & HAL_GENMASK(h, l)) % 16)) +#define WIDTH_TO_MASK(w) ((1 << (w)) - 1) + +/* + * RESET/GATE fields: + * [31:16]: reserved + * [15:12]: bank + * [11:0]: id + */ +#define CLK_RESET_GET_REG_OFFSET(x) GENVAL_D16(x, 11, 0) +#define CLK_RESET_GET_BITS_SHIFT(x) GENVAL_D16_REM(x, 11, 0) +#define CLK_RESET_GET_REG_BANK(x) HAL_GENVAL(x, 15, 12) + +#define CLK_GATE_GET_REG_OFFSET(x) CLK_RESET_GET_REG_OFFSET(x) +#define CLK_GATE_GET_BITS_SHIFT(x) CLK_RESET_GET_BITS_SHIFT(x) +#define CLK_GATE_GET_REG_BANK(x) CLK_RESET_GET_REG_BANK(x) + +/* + * MUX/DIV fields: + * [31:24]: width + * [23:16]: shift + * [15:12]: reserved + * [11:8]: bank + * [7:0]: reg + */ +#define CLK_MUX_GET_REG_OFFSET(x) HAL_GENVAL(x, 7, 0) +#define CLK_MUX_GET_BANK(x) HAL_GENVAL(x, 11, 8) +#define CLK_MUX_GET_BITS_SHIFT(x) HAL_GENVAL(x, 23, 16) +#define CLK_MUX_GET_WIDTH(x) HAL_GENVAL(x, 31, 24) +#define CLK_MUX_GET_MASK(x) (WIDTH_TO_MASK(CLK_MUX_GET_WIDTH(x)) << CLK_MUX_GET_BITS_SHIFT(x)) + +#define CLK_DIV_GET_REG_OFFSET(x) CLK_MUX_GET_REG_OFFSET(x) +#define CLK_DIV_GET_BANK(x) CLK_MUX_GET_BANK(x) +#define CLK_DIV_GET_BITS_SHIFT(x) CLK_MUX_GET_BITS_SHIFT(x) +#define CLK_DIV_GET_WIDTH(x) CLK_MUX_GET_WIDTH(x) +#define CLK_DIV_GET_MASK(x) CLK_MUX_GET_MASK(x) +#define CLK_DIV_GET_MAXDIV(x) ((1 << CLK_DIV_GET_WIDTH(x)) - 1) + +/* + * v64 mux = v32 | bank(in bit[35:32]) + * v64 div = v32 | bank(in bit[39:36]) + */ +#ifdef CRU_CLK_USE_CON_BANK +#define CLK_GET_MUX(v64) ((uint32_t)(((v64) & 0xFFFFFFFF00000000) >> 32)) +#define CLK_GET_DIV(v64) ((uint32_t)((v64) & 0x00000000FFFFFFFF)) +#else +#define CLK_GET_MUX(v32) ((uint32_t)((v32) & 0x0F0F00FFU)) +#define CLK_GET_DIV(v32) ((uint32_t)((((v32) & 0x0000FF00U) >> 8) | \ + (((v32) & 0xF0F00000U) >> 4))) +#endif + +#define RK_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, \ + _frac) \ + { \ + .rate = _rate##U, .fbDiv = _fbdiv, .postDiv1 = _postdiv1, \ + .refDiv = _refdiv, .postDiv2 = _postdiv2, .dsmpd = _dsmpd, \ + .frac = _frac, \ + } + +#define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \ + { \ + .rate = _rate##U, .p = _p, .m = _m, \ + .s = _s, .k = _k, \ + } + +#define CRU_BANK_CFG_FLAGS(reg, sel, gate, soft) \ + { \ + .cruBase = reg, \ + .selOffset = sel, \ + .gateOffset = gate, \ + .softOffset = soft, \ + } + +struct PLL_CONFIG { + uint32_t rate; + + union { + struct { + uint32_t fbDiv; + uint32_t postDiv1; + uint32_t refDiv; + uint32_t postDiv2; + uint32_t dsmpd; + uint32_t frac; + }; + struct { + uint32_t m; + uint32_t p; + uint32_t s; + uint32_t k; + }; + }; +}; + +struct PLL_SETUP { + __IO uint32_t *conOffset0; + __IO uint32_t *conOffset1; + __IO uint32_t *conOffset2; + __IO uint32_t *conOffset3; + __IO uint32_t *conOffset6; + __IO uint32_t *modeOffset; + __I uint32_t *stat0; + uint32_t modeShift; + uint32_t lockShift; + uint32_t modeMask; + const struct PLL_CONFIG *rateTable; +}; + +typedef enum { + GLB_SRST_FST = 0xfdb9, + GLB_SRST_SND = 0xeca8, +} eCRU_GlbSrstType; + +typedef enum { + GLB_RST_FST_WDT0 = 0U, + GLB_RST_SND_WDT0, + GLB_RST_FST_WDT1, + GLB_RST_SND_WDT1, + GLB_RST_FST_WDT2, + GLB_RST_SND_WDT2, + GLB_RST_FST_WDT3, + GLB_RST_SND_WDT3, + GLB_RST_FST_WDT4, + GLB_RST_SND_WDT4, + +} eCRU_WdtRstType; + +struct CRU_BANK_INFO { + uint32_t cruBase; + uint32_t selOffset; + uint32_t gateOffset; + uint32_t softOffset; +}; + +struct HAL_CRU_DEV { + const struct CRU_BANK_INFO *banks; + uint8_t banksNum; +}; + +extern const struct HAL_CRU_DEV g_cruDev; + +/***************************** Structure Definition **************************/ + +/** @} */ +/***************************** Function Declare ******************************/ +/** @defgroup CRU_Private_Function_Declare Private Function Declare + * @{ + */ + +#define _MHZ(n) ((n) * 1000000) +#define DIV_NO_REM(pFreq, freq, maxDiv) \ + ((!((pFreq) % (freq))) && ((pFreq) / (freq) <= (maxDiv))) + +int HAL_CRU_FreqGetMux4(uint32_t freq, uint32_t freq0, uint32_t freq1, + uint32_t freq2, uint32_t freq3); +int HAL_CRU_FreqGetMux3(uint32_t freq, uint32_t freq0, uint32_t freq1, + uint32_t freq2); +int HAL_CRU_FreqGetMux2(uint32_t freq, uint32_t freq0, uint32_t freq1); +int HAL_CRU_FreqGetMuxArray(uint32_t freq, uint32_t *table, int num); + +uint32_t HAL_CRU_MuxGetFreq4(uint32_t muxName, uint32_t freq0, uint32_t freq1, + uint32_t freq2, uint32_t freq3); +uint32_t HAL_CRU_MuxGetFreq3(uint32_t muxName, uint32_t freq0, uint32_t freq1, + uint32_t freq2); +uint32_t HAL_CRU_MuxGetFreq2(uint32_t muxName, uint32_t freq0, uint32_t freq1); +uint32_t HAL_CRU_MuxGetFreqArray(uint32_t muxName, uint32_t *table, int num); + +int HAL_CRU_RoundFreqGetMux4(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1, + uint32_t pFreq2, uint32_t pFreq3, uint32_t *pFreqOut); +int HAL_CRU_RoundFreqGetMux3(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1, + uint32_t pFreq2, uint32_t *pFreqOut); +int HAL_CRU_RoundFreqGetMux2(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1, + uint32_t *pFreqOut); +int HAL_CRU_RoundFreqGetMuxArray(uint32_t freq, uint32_t *table, int num, uint32_t *pFreqOut, bool is_div); + +/** @} */ + +/** @defgroup CRU_Public_Function_Declare Public Function Declare + * @{ + */ + +/** + * @brief Get pll freq. + * @param pSetup: Contains PLL register parameters + * @return pll rate. + */ +uint32_t HAL_CRU_GetPllFreq(struct PLL_SETUP *pSetup); + +/** + * @brief Set pll freq. + * @param pSetup: Contains PLL register parameters + * @param rate: pll set + * @return HAL_Status. + */ +HAL_Status HAL_CRU_SetPllFreq(struct PLL_SETUP *pSetup, uint32_t rate); + +/** + * @brief Set pll power up. + * @param pSetup: Contains PLL register parameters + * @return HAL_Status. + */ +HAL_Status HAL_CRU_SetPllPowerUp(struct PLL_SETUP *pSetup); + +/** + * @brief Set pll power down. + * @param pSetup: Contains PLL register parameters + * @return HAL_Status. + */ +HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup); + +/** + * @brief Check if clk is enabled + * @param clk: clock to check + * @return HAL_Check. + */ +HAL_Check HAL_CRU_ClkIsEnabled(uint32_t clk); + +/** + * @brief Enable clk + * @param clk: clock to set + * @return HAL_Status. + */ +HAL_Status HAL_CRU_ClkEnable(uint32_t clk); + +/** + * @brief Disable unused clk + * @param bank: cru bank id + * @param index: gate con offset + * @param val: gate value + * @return HAL_Status. + */ +HAL_Status HAL_CRU_ClkDisableUnused(uint32_t bank, uint32_t index, uint32_t val); + +/** + * @brief Disable clk + * @param clk: clock to set + * @return HAL_Status. + */ +HAL_Status HAL_CRU_ClkDisable(uint32_t clk); + +/** + * @brief Check if clk is reset + * @param clk: clock to check + * @return HAL_Check. + */ +HAL_Check HAL_CRU_ClkIsReset(uint32_t clk); + +/** + * @brief Assert the reset to the clk + * @param clk: clock to assert + * @return HAL_Status. + */ +HAL_Status HAL_CRU_ClkResetAssert(uint32_t clk); + +/** + * @brief Deassert the reset to the clk + * @param clk: clock to deassert + * @return HAL_Status. + */ +HAL_Status HAL_CRU_ClkResetDeassert(uint32_t clk); + +/** + * @brief Sync Assert the resets to the clk + * @param numClks: num clocks to assert + * @param clks: clocks to assert + * @return HAL_Status. + */ +HAL_Status HAL_CRU_ClkResetSyncAssert(int numClks, uint32_t *clks); + +/** + * @brief Sync Deassert the resets to the clk + * @param numClks: num clocks to assert + * @param clks: clocks to deassert + * @return HAL_Status. + */ +HAL_Status HAL_CRU_ClkResetSyncDeassert(int numClks, uint32_t *clks); + +/** + * @brief Set frac div + * @param fracDivName: frac div id(Contains div offset, shift, mask information) + * @param numerator: the numerator to set. + * @param denominator: the denominator to set. + * @return HAL_Status + */ +HAL_Status HAL_CRU_ClkSetFracDiv(uint32_t fracDivName, + uint32_t numerator, + uint32_t denominator); + +/** + * @brief Get frac div + * @param fracDivName: frac div id(Contains div offset, shift, mask information) + * @param numerator: the returned numerator. + * @param denominator: the returned denominator. + * @return HAL_Status + */ +HAL_Status HAL_CRU_ClkGetFracDiv(uint32_t fracDivName, + uint32_t *numerator, + uint32_t *denominator); + +/** + * @brief Set integer div + * @param divName: div id(Contains div offset, shift, mask information) + * @param divValue: div value + * @return NONE + */ +HAL_Status HAL_CRU_ClkSetDiv(uint32_t divName, uint32_t divValue); + +/** + * @brief Get integer div + * @param divName: div id (Contains div offset, shift, mask information) + * @return div value + */ +uint32_t HAL_CRU_ClkGetDiv(uint32_t divName); + +/** + * @brief Set mux + * @param muxName: mux id (Contains mux offset, shift, mask information) + * @param muxValue: mux value + * @return NONE + */ +HAL_Status HAL_CRU_ClkSetMux(uint32_t muxName, uint32_t muxValue); + +/** + * @brief Get mux + * @param muxName: mux id (Contains mux offset, shift, mask information) + * @return mux value + */ +uint32_t HAL_CRU_ClkGetMux(uint32_t muxName); + +/** + * @brief Get frac div config. + * @param rateOut: clk out rate. + * @param rate: clk src rate. + * @param numerator: the returned numerator. + * @param denominator: the returned denominator. + * @return HAL_Status. + */ +HAL_Status HAL_CRU_FracdivGetConfig(uint32_t rateOut, uint32_t rate, + uint32_t *numerator, + uint32_t *denominator); + + +/** + * @brief Get frac div config V2(24bit). + * @param rateOut: clk out rate. + * @param rate: clk src rate. + * @param numerator: the returned numerator. + * @param denominator: the returned denominator. + * @return HAL_Status. + */ +HAL_Status HAL_CRU_FracdivGetConfigV2(uint32_t rateOut, uint32_t rate, + uint32_t *numerator, + uint32_t *denominator); + + +/** + * @brief Get clk freq. + * @param clockName: CLOCK_Name id. + * @return rate. + * @attention these APIs allow direct use in the HAL layer. + */ +uint32_t HAL_CRU_ClkGetFreq(eCLOCK_Name clockName); + +/** + * @brief Set clk freq. + * @param clockName: CLOCK_Name id. + * @param rate: clk rate. + * @return HAL_Status. + * @attention these APIs allow direct use in the HAL layer. + */ +HAL_Status HAL_CRU_ClkSetFreq(eCLOCK_Name clockName, uint32_t rate); + +/** + * @brief vop dclk enable. + * @param gateId: gate id + * @return HAL_Status. + * @attention these APIs allow direct use in the HAL layer. + */ +HAL_Status HAL_CRU_VopDclkEnable(uint32_t gateId); + +/** + * @brief vop dclk disable. + * @param gateId: gate id + * @return HAL_Status. + * @attention these APIs allow direct use in the HAL layer. + */ +HAL_Status HAL_CRU_VopDclkDisable(uint32_t gateId); + +/** + * @brief Get Np5 best div. + * @param clockName: clk id. + * @param rate: clk rate. + * @param pRate: clk parent rate + * @param bestdiv: the returned bestdiv. + * @return HAL_Status. + */ +HAL_Status HAL_CRU_ClkNp5BestDiv(eCLOCK_Name clockName, uint32_t rate, uint32_t pRate, uint32_t *bestdiv); + +/** + * @brief assert CRU global software reset. + * @param type: global software reset type. + * @return HAL_INVAL if the SoC does not support. + */ +HAL_Status HAL_CRU_SetGlbSrst(eCRU_GlbSrstType type); + +/** + * @brief wdt glbrst enable. + * @param wdtType: wdt reset type. + * @return HAL_OK. + * @attention these APIs allow direct use in the HAL layer. + */ +HAL_Status HAL_CRU_WdtGlbRstEnable(eCRU_WdtRstType wdtType); + +/** + * @brief pll output freq Compensation. + * @param clockName: CLOCK_Name id. + * @param ppm: Efforts to compensate. + * @return HAL_OK. + * @attention these APIs allow direct use in the HAL layer. + */ +HAL_Status HAL_CRU_PllCompensation(eCLOCK_Name clockName, int ppm); + +/** + * @brief CRU suspend. + * @return HAL_Status. + * @attention these APIs allow direct use in the HAL layer. + */ +HAL_Status HAL_CRU_Suspend(void); + +/** + * @brief CRU resume. + * @return HAL_Status. + * @attention these APIs allow direct use in the HAL layer. + */ +HAL_Status HAL_CRU_Resume(void); + +#ifdef HAL_CRU_AS_FEATURE_ENABLED +/** + * @brief it is for AS init. + */ +void HAL_CRU_AsInit(void); + +/** + * @brief it is for AS enable. + * @param ch: channel + * @param en: 1 is enable, 0 is disable. + */ +void HAL_CRU_AsEnable(uint8_t ch, uint8_t en); +#endif + +/** @} */ + +#endif + +/** @} */ + +/** @} */ + +#endif /* HAL_CRU_MODULE_ENABLED */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_debug.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_debug.h new file mode 100644 index 000000000..a4e018d2d --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_debug.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2018-2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef _HAL_DEBUG_H_ +#define _HAL_DEBUG_H_ + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup DEBUG + * @{ + */ + +/***************************** MACRO Definition ******************************/ + +/* Run only for debugging, please refer to how-to-use for the definition of the specification. */ +//#define HAL_DBG_USING_RTT_SERIAL +//#define HAL_DBG_USING_LIBC_PRINTF +//#define HAL_DBG_USING_HAL_PRINTF +#ifdef HAL_DBG_USING_RTT_SERIAL +#include +#include + +#define HAL_SYSLOG rt_kprintf +#elif defined(HAL_DBG_USING_LIBC_PRINTF) +#define HAL_SYSLOG printf +#elif defined(HAL_DBG_USING_HAL_PRINTF) +#define HAL_SYSLOG HAL_DBG_Printf +#ifndef HAL_PRINTF_BUF_SIZE +#define HAL_PRINTF_BUF_SIZE 128 +#endif +#endif + +/** @defgroup DEBUG_Exported_Definition_Group1 Basic Definition + * @{ + */ + +#ifndef HAL_SYSLOG +#define HAL_SYSLOG HAL_DBG_Printf +#endif + +#if defined(HAL_DBG_ON) && defined(HAL_DBG_INFO_ON) +#define HAL_DBG(fmt, arg...) HAL_SYSLOG("[HAL INFO] " fmt, ##arg) +#else +#define HAL_DBG(fmt, arg...) do { if (0) HAL_SYSLOG("[HAL INFO] " fmt, ##arg); } while (0) +#endif + +#if defined(HAL_DBG_ON) && defined(HAL_DBG_WRN_ON) +#define HAL_DBG_WRN(fmt, arg...) HAL_SYSLOG("[HAL WARNING] " fmt, ##arg) +#else +#define HAL_DBG_WRN(fmt, arg...) do { if (0) HAL_SYSLOG("[HAL WARNING] " fmt, ##arg); } while (0) +#endif + +#if defined(HAL_DBG_ON) && defined(HAL_DBG_ERR_ON) +#define HAL_DBG_ERR(fmt, arg...) HAL_SYSLOG("[HAL ERROR] " fmt, ##arg) +#else +#define HAL_DBG_ERR(fmt, arg...) do { if (0) HAL_SYSLOG("[HAL ERROR] " fmt, ##arg); } while (0) +#endif + +#if defined(HAL_DBG_ON) && defined(HAL_ASSERT_ON) +#define HAL_ASSERT(expr) \ + do { \ + if (!(expr)) \ + HAL_AssertFailed((const char *)__FILE__, __LINE__); \ + } while (0) +#else +#define HAL_ASSERT(expr) +#endif + +/***************************** Structure Definition **************************/ + +/** @} */ +/***************************** Function Declare ******************************/ +/** @defgroup DEBUG_Public_Function_Declare Public Function Declare + * @{ + */ + +void HAL_AssertFailed(const char *file, uint32_t line); +HAL_Status HAL_DBG_HEX(char *s, void *buf, uint32_t width, uint32_t len); +#ifdef __GNUC__ +__attribute__((__format__(printf, 1, 2))) +#endif +int32_t HAL_DBG_Printf(const char *format, ...); + +/** @} */ + +#endif + +/** @} */ + +/** @} */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_def.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_def.h new file mode 100644 index 000000000..f61871607 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_def.h @@ -0,0 +1,205 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup HAL_DEF + * @{ + */ + +#ifndef _HAL_DEF_H_ +#define _HAL_DEF_H_ + +#include "libserial.h" +#include +#include +#include +#include +#include + +#include "soc.h" +#include "hal_list.h" + +/***************************** MACRO Definition ******************************/ +/** @defgroup HAL_DEF_Exported_Definition_Group1 Basic Definition + * @{ + */ + +#define SET_BIT(REG, BIT) ((*(volatile uint32_t *)&(REG)) |= (BIT)) /**< Set 1 to the register specific bit field */ +#define CLEAR_BIT(REG, MASK) ((*(volatile uint32_t *)&(REG)) &= ~(MASK)) /**< Clear the specific bits filed from the register */ +#define READ_BIT(REG, MASK) ((*(volatile const uint32_t *)&(REG)) & (MASK)) /**< Read the value of a specific bits field from the register */ +#define CLEAR_REG(REG) ((*(volatile uint32_t *)&(REG)) = (0x0)) /**< Write 0 to the register */ +#define WRITE_REG(REG, VAL) ((*(volatile uint32_t *)&(REG)) = (VAL)) /**< Write the register */ +#define READ_REG(REG) ((*(volatile const uint32_t *)&(REG))) /**< Read the register */ +#define MODIFY_REG(REG, CLEARMASK, SETMASK) \ + WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) /**< Clear and set the value of a specific bits field from the register */ +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + +#if defined(__GNUC__) || defined(__CC_ARM) +#define MASK_TO_WE(msk) (__builtin_constant_p(msk) ? ((msk) > 0xFFFFU ? 0 : ((msk) << 16)) : ((msk) << 16)) +#else +#define MASK_TO_WE(msk) ((msk) << 16) +#endif +#define VAL_MASK_WE(msk, val) ((MASK_TO_WE(msk)) | (val)) +#define WRITE_REG_MASK_WE(reg, msk, val) WRITE_REG(reg, (VAL_MASK_WE(msk, val))) + +/* Misc OPS Marco */ +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define RESET 0 +#define HAL_IS_BIT_SET(REG, MASK) (((*(volatile uint32_t *)&(REG)) & (MASK)) != RESET) /**< Check if the the specific bits filed from the register is valid */ +#define HAL_IS_BIT_CLR(REG, MASK) (((*(volatile uint32_t *)&(REG)) & (MASK)) == RESET) /**< Check if the the specific bits filed from the register is isvalid */ + +#define HAL_BIT(nr) (1UL << (nr)) +#define HAL_ARRAY_SIZE(a) (sizeof((a)) / sizeof((a)[0])) +#define HAL_MAX(x, y) ((x) > (y) ? (x) : (y)) +#define HAL_MIN(x, y) ((x) < (y) ? (x) : (y)) + +#define HAL_DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) + +#define HAL_IS_ALIGNED(x, a) (((x) & (a - 1)) == 0) +#ifdef CACHE_LINE_SIZE +#define HAL_IS_CACHELINE_ALIGNED(x) HAL_IS_ALIGNED((uint32_t)(x), CACHE_LINE_SIZE) +#else +#define HAL_IS_CACHELINE_ALIGNED(x) HAL_IS_ALIGNED((uint32_t)(x), 4) +#endif + +/* Compiller Macro */ +#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM) || defined(__ICCARM__) +#define HAL_UNUSED __attribute__((__unused__)) +#else +#define HAL_UNUSED +#endif + +#ifdef CACHE_LINE_SIZE +#define HAL_CACHELINE_ALIGNED __ALIGNED(CACHE_LINE_SIZE) +#else +#define HAL_CACHELINE_ALIGNED +#endif + +#ifdef HAL_SRAM_SECTION_ENABLED +#define HAL_SECTION_SRAM_CODE __attribute__((section(".sram_code"))) +#define HAL_SECTION_SRAM_RODATA __attribute__((section(".sram_rodata"))) +#define HAL_SECTION_SRAM_DATA __attribute__((section(".sram_data"))) +#define HAL_SECTION_SRAM_BSS __attribute__((section(".sram_bss"))) +#else +#define HAL_SECTION_SRAM_CODE +#define HAL_SECTION_SRAM_RODATA +#define HAL_SECTION_SRAM_DATA +#define HAL_SECTION_SRAM_BSS +#endif + +#ifdef HAL_PSRAM_SECTION_ENABLED +#define HAL_SECTION_PSRAM_CODE __attribute__((section(".psram_code"))) +#define HAL_SECTION_PSRAM_RODATA __attribute__((section(".psram_rodata"))) +#define HAL_SECTION_PSRAM_DATA __attribute__((section(".psram_data"))) +#define HAL_SECTION_PSRAM_BSS __attribute__((section(".psram_bss"))) +#else +#define HAL_SECTION_PSRAM_CODE +#define HAL_SECTION_PSRAM_RODATA +#define HAL_SECTION_PSRAM_DATA +#define HAL_SECTION_PSRAM_BSS +#endif + +#ifdef HAL_XIP_SECTION_ENABLED +#define HAL_SECTION_XIP_CODE __attribute__((section(".xip_code"))) +#define HAL_SECTION_XIP_RODATA __attribute__((section(".xip_rodata"))) +#else +#define HAL_SECTION_XIP_CODE +#define HAL_SECTION_XIP_RODATA +#endif + +#define HAL_GENMASK(h, l) (((~0U) << (l)) & (~0U >> (32 - 1 - (h)))) +#define HAL_GENVAL(x, h, l) ((uint32_t)(((x) & HAL_GENMASK(h, l)) >> (l))) +#define HAL_GENMASK_ULL(h, l) (((~0ULL) << (l)) & (~0ULL >> (64 - 1 - (h)))) +#define HAL_GENVAL_ULL(x, h, l) ((uint64_t)(((x) & HAL_GENMASK_ULL(h, l)) >> (l))) + +/** MCU systick clock source */ +typedef enum { + HAL_SYSTICK_CLKSRC_CORE, + HAL_SYSTICK_CLKSRC_EXT +} eHAL_systickClkSource; + +/** Check if is MCU systick clock source */ +#define IS_SYSTICK_SOURCE(s) (((s) == HAL_SYSTICK_CLKSRC_CORE) || ((s) == HAL_SYSTICK_CLKSRC_EXT)) + +/***************************** Structure Definition **************************/ +/** HAL boolean type definition */ +typedef enum { + HAL_FALSE = 0x00U, + HAL_TRUE = 0x01U +} HAL_Check; + +/** HAL error code definition */ +typedef enum { + HAL_OK = 0x00U, + HAL_ERROR = (-1), + HAL_BUSY = (-16), + HAL_NODEV = (-19), + HAL_INVAL = (-22), + HAL_NOSYS = (-38), + HAL_TIMEOUT = (-110) +} HAL_Status; + +/** HAL functional status definition */ +typedef enum { + HAL_DISABLE = 0x00U, + HAL_ENABLE = 0x01U +} HAL_FuncStatus; + +/** HAL lock structures definition */ +typedef enum { + HAL_UNLOCKED = 0x00U, + HAL_LOCKED = 0x01U +} HAL_LockStatus; + +/** RK GPIO bank definition */ +typedef enum { +#ifdef GPIO0 + GPIO_BANK0 = 0, +#endif +#ifdef GPIO1 + GPIO_BANK1 = 1, +#endif +#ifdef GPIO2 + GPIO_BANK2 = 2, +#endif +#ifdef GPIO3 + GPIO_BANK3 = 3, +#endif +#ifdef GPIO4 + GPIO_BANK4 = 4, +#endif +#ifdef GPIO0_EXP + GPIO_BANK0_EXP = 5, +#endif +#ifdef GPIO1_EXP + GPIO_BANK1_EXP = 6, +#endif +#ifdef GPIO2_EXP + GPIO_BANK2_EXP = 7, +#endif +#ifdef GPIO3_EXP + GPIO_BANK3_EXP = 8, +#endif +#ifdef GPIO4_EXP + GPIO_BANK4_EXP = 9, +#endif + GPIO_BANK_NUM +} eGPIO_bankId; + +/** HAL function type definition */ +typedef void (*pFunc)(void); + +/** @} */ +/***************************** Function Declare ******************************/ + +#endif + +/** @} */ + +/** @} */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_driver.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_driver.h new file mode 100644 index 000000000..cb81609a6 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_driver.h @@ -0,0 +1,282 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2018-2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef _HAL_DRIVER_H_ +#define _HAL_DRIVER_H_ + +#include "hal_pm.h" + +#ifdef HAL_ACDCDIG_MODULE_ENABLED +#include "hal_acdcdig.h" +#endif + +#ifdef HAL_ACODEC_MODULE_ENABLED +#include "hal_acodec.h" +#endif + +#ifdef HAL_ARCHTIMER_MODULE_ENABLED +#include "hal_archtimer.h" +#endif + +#ifdef HAL_AUDIOPWM_MODULE_ENABLED +#include "hal_audiopwm.h" +#endif + +// #include "hal_cache.h" + +#ifdef HAL_BUFMGR_MODULE_ENABLED +#include "hal_bufmgr.h" +#endif + +#ifdef HAL_CANFD_MODULE_ENABLED +#include "hal_canfd.h" +#endif + +#ifdef HAL_CKCAL_MODULE_ENABLED +#include "hal_ckcal.h" +#endif + +#ifdef HAL_CACHE_ECC_MODULE_ENABLED +#include "hal_cache_ecc.h" +#endif + +#ifdef HAL_CPU_TOPOLOGY_MODULE_ENABLED +#include "hal_cpu_topology.h" +#endif + +#ifdef HAL_CRU_MODULE_ENABLED +#include "hal_cru.h" +#endif + +#ifdef HAL_CRYPTO_MODULE_ENABLED +#include "hal_crypto.h" +#endif + +#ifdef HAL_DSI_MODULE_ENABLED +#include "hal_display.h" +#include "hal_dsi.h" +#endif + +#ifdef HAL_DEMO_MODULE_ENABLED +#include "hal_demo.h" +#endif + +#ifdef HAL_DDR_ECC_MODULE_ENABLED +#include "hal_ddr_ecc.h" +#endif + +#ifdef HAL_DSP_MODULE_ENABLED +#include "hal_dsp.h" +#endif + +// #include "hal_dma.h" + +#ifdef HAL_DWDMA_MODULE_ENABLED +#include "hal_dwdma.h" +#endif + +#ifdef HAL_EFUSE_MODULE_ENABLED +#include "hal_efuse.h" +#endif + +#if defined(HAL_GMAC_MODULE_ENABLED) || defined(HAL_GMAC1000_MODULE_ENABLED) +#include "hal_gmac.h" +#endif + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "hal_gpio.h" +#endif + +#ifdef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED +#include "hal_gpio_irq_group.h" +#endif + +#ifdef HAL_PINCTRL_MODULE_ENABLED +#include "hal_pinctrl.h" +#endif + +#if defined(HAL_HCD_MODULE_ENABLED) || defined(HAL_PCD_MODULE_ENABLED) +#include "hal_usb_core.h" +#include "hal_usb_phy.h" +#endif + +#if defined(HAL_EHCI_MODULE_ENABLED) || defined(HAL_OHCI_MODULE_ENABLED) +#include "hal_usbh.h" +#endif + +#ifdef HAL_HCD_MODULE_ENABLED +#include "hal_hcd.h" +#endif + +#ifdef HAL_HWSPINLOCK_MODULE_ENABLED +#include "hal_hwspinlock.h" +#endif + +#ifdef HAL_HYPERPSRAM_MODULE_ENABLED +#include "hal_hyperpsram.h" +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +#include "hal_i2c.h" +#endif + +#ifdef HAL_I2S_MODULE_ENABLED +#include "hal_i2s.h" +#endif + +#ifdef HAL_I2STDM_MODULE_ENABLED +#include "hal_i2stdm.h" +#endif + +#ifdef HAL_INTC_MODULE_ENABLED +#include "hal_intc.h" +#endif + +#ifdef HAL_INTMUX_MODULE_ENABLED +#include "hal_intmux.h" +#endif + +#ifdef HAL_IRQ_HANDLER_MODULE_ENABLED +#include "hal_irq_handler.h" +#endif + +#ifdef HAL_GIC_MODULE_ENABLED +#include "hal_gic.h" +#endif + +#ifdef HAL_MBOX_MODULE_ENABLED +#include "hal_mbox.h" +#endif + +#ifdef HAL_NVIC_MODULE_ENABLED +#include "hal_nvic.h" +#endif + +#ifdef HAL_PCD_MODULE_ENABLED +#include "hal_pcd.h" +#endif + +#ifdef HAL_PCIE_MODULE_ENABLED +#include "hal_pci_core.h" +#include "hal_pcie_dma.h" +#include "hal_pcie.h" +#endif + +#ifdef HAL_PDM_MODULE_ENABLED +#include "hal_pdm.h" +#endif + +#ifdef HAL_PL330_MODULE_ENABLED +#include "hal_pl330.h" +#endif + +#ifdef HAL_PMU_MODULE_ENABLED +#include "hal_pd.h" +#endif + +#ifdef HAL_PVTM_MODULE_ENABLED +#include "hal_pvtm.h" +#endif + +#ifdef HAL_PWM_MODULE_ENABLED +#include "hal_pwm.h" +#endif + +// #include "hal_pwr.h" + +#ifdef HAL_RISCVIC_MODULE_ENABLED +#include "hal_riscvic.h" +#endif + +#ifdef HAL_SDIO_MODULE_ENABLED +#include "hal_sdio.h" +#endif + +#ifdef HAL_SNOR_MODULE_ENABLED +#include "hal_spi_mem.h" +#include "hal_snor.h" +#endif + +#ifdef HAL_SFC_MODULE_ENABLED +#include "hal_sfc.h" +#endif + +#ifdef HAL_SPINAND_MODULE_ENABLED +#include "hal_spi_mem.h" +#include "hal_spinand.h" +#endif + +#ifdef HAL_SPINLOCK_MODULE_ENABLED +#include "hal_spinlock.h" +#endif + +#ifdef HAL_SYSTICK_MODULE_ENABLED +#include "hal_systick.h" +#endif + +#ifdef HAL_FSPI_MODULE_ENABLED +#include "hal_spi_mem.h" +#include "hal_fspi.h" +#endif + +#ifdef HAL_QPIPSRAM_MODULE_ENABLED +#include "hal_spi_mem.h" +#include "hal_qpipsram.h" +#endif + +#ifdef HAL_TOUCHKEY_MODULE_ENABLED +#include "hal_touchkey.h" +#endif + +#ifdef HAL_TSADC_MODULE_ENABLED +#include "hal_tsadc.h" +#endif + +#ifdef HAL_SARADC_MODULE_ENABLED +#include "hal_saradc.h" +#endif + +#ifdef HAL_SMCCC_MODULE_ENABLED +#include "hal_smccc.h" +#endif + +#ifdef HAL_KEYCTRL_MODULE_ENABLED +#include "hal_keyctrl.h" +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +#include "hal_spi.h" +#endif + +#ifdef HAL_SPI2APB_MODULE_ENABLED +#include "hal_spi2apb.h" +#endif + +#ifdef HAL_TIMER_MODULE_ENABLED +#include "hal_timer.h" +#endif + +#ifdef HAL_UART_MODULE_ENABLED +#include "hal_uart.h" +#endif + +#ifdef HAL_VAD_MODULE_ENABLED +#include "hal_vad.h" +#endif + +#ifdef HAL_VICAP_MODULE_ENABLED +#include "hal_vicap.h" +#endif + +#ifdef HAL_VOP_MODULE_ENABLED +#include "hal_display.h" +#include "hal_vop.h" +#endif + +#ifdef HAL_WDT_MODULE_ENABLED +#include "hal_wdt.h" +#endif + +#endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_gmac.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_gmac.h new file mode 100644 index 000000000..de369dd03 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_gmac.h @@ -0,0 +1,360 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +#if (defined(HAL_GMAC_MODULE_ENABLED) || defined(HAL_GMAC1000_MODULE_ENABLED)) + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup GMAC + * @{ + */ + +#ifndef __HAL_GMAC_H +#define __HAL_GMAC_H + +#include "hal_def.h" +#include "hal_base.h" + +/***************************** MACRO Definition ******************************/ +/** @defgroup GMAC_Exported_Definition_Group1 Basic Definition + * @{ + */ + +/* GMAC PHY indicates what features are supported by the interface. */ +#define HAL_GMAC_PHY_SUPPORTED_10baseT_Half (1 << 0) +#define HAL_GMAC_PHY_SUPPORTED_10baseT_Full (1 << 1) +#define HAL_GMAC_PHY_SUPPORTED_100baseT_Half (1 << 2) +#define HAL_GMAC_PHY_SUPPORTED_100baseT_Full (1 << 3) +#define HAL_GMAC_PHY_SUPPORTED_1000baseT_Half (1 << 4) +#define HAL_GMAC_PHY_SUPPORTED_1000baseT_Full (1 << 5) +#define HAL_GMAC_PHY_SUPPORTED_Autoneg (1 << 6) +#define HAL_GMAC_PHY_SUPPORTED_TP (1 << 7) +#define HAL_GMAC_PHY_SUPPORTED_AUI (1 << 8) +#define HAL_GMAC_PHY_SUPPORTED_MII (1 << 9) +#define HAL_GMAC_PHY_SUPPORTED_FIBRE (1 << 10) +#define HAL_GMAC_PHY_SUPPORTED_BNC (1 << 11) +#define HAL_GMAC_PHY_SUPPORTED_10000baseT_Full (1 << 12) +#define HAL_GMAC_PHY_SUPPORTED_Pause (1 << 13) +#define HAL_GMAC_PHY_SUPPORTED_Asym_Pause (1 << 14) +#define HAL_GMAC_PHY_SUPPORTED_2500baseX_Full (1 << 15) +#define HAL_GMAC_PHY_SUPPORTED_Backplane (1 << 16) +#define HAL_GMAC_PHY_SUPPORTED_1000baseKX_Full (1 << 17) +#define HAL_GMAC_PHY_SUPPORTED_10000baseKX4_Full (1 << 18) +#define HAL_GMAC_PHY_SUPPORTED_10000baseKR_Full (1 << 19) +#define HAL_GMAC_PHY_SUPPORTED_10000baseR_FEC (1 << 20) +#define HAL_GMAC_PHY_SUPPORTED_1000baseX_Half (1 << 21) +#define HAL_GMAC_PHY_SUPPORTED_1000baseX_Full (1 << 22) + +#define HAL_GMAC_PHY_DEFAULT_FEATURES (HAL_GMAC_PHY_SUPPORTED_Autoneg | \ + HAL_GMAC_PHY_SUPPORTED_TP | \ + HAL_GMAC_PHY_SUPPORTED_MII) + +#define HAL_GMAC_PHY_10BT_FEATURES (HAL_GMAC_PHY_SUPPORTED_10baseT_Half | \ + HAL_GMAC_PHY_SUPPORTED_10baseT_Full) + +#define HAL_GMAC_PHY_100BT_FEATURES (HAL_GMAC_PHY_SUPPORTED_100baseT_Half | \ + HAL_GMAC_PHY_SUPPORTED_100baseT_Full) + +#define HAL_GMAC_PHY_1000BT_FEATURES (HAL_GMAC_PHY_SUPPORTED_1000baseT_Half | \ + HAL_GMAC_PHY_SUPPORTED_1000baseT_Full) + +#define HAL_GMAC_PHY_BASIC_FEATURES (HAL_GMAC_PHY_10BT_FEATURES | \ + HAL_GMAC_PHY_100BT_FEATURES | \ + HAL_GMAC_PHY_DEFAULT_FEATURES) + +#define HAL_GMAC_PHY_GBIT_FEATURES (HAL_GMAC_PHY_BASIC_FEATURES | \ + HAL_GMAC_PHY_1000BT_FEATURES) + +/* GMAC flow ctrl Definition */ +#define HAL_GMAC_FLOW_OFF 0 +#define HAL_GMAC_FLOW_RX 1 +#define HAL_GMAC_FLOW_TX 2 +#define HAL_GMAC_FLOW_AUTO (HAL_GMAC_FLOW_TX | HAL_GMAC_FLOW_RX) + +/* GMAC descriptions and buffers Definition */ +#define HAL_GMAC_ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) +#define HAL_GMAC_DESCRIPTOR_WORDS 4 +#define HAL_GMAC_DESCRIPTOR_SIZE (HAL_GMAC_DESCRIPTOR_WORDS * 4) +#define HAL_GMAC_BUFFER_ALIGN 64 +#define HAL_GMAC_MAX_FRAME_SIZE 1518 +#define HAL_GMAC_MAX_PACKET_SIZE HAL_GMAC_ALIGN(HAL_GMAC_MAX_FRAME_SIZE, HAL_GMAC_BUFFER_ALIGN) + +/***************************** Structure Definition **************************/ +struct GMAC_HANDLE; + +/** + * @brief GMAC PHY Speed + */ +typedef enum { + PHY_SPEED_10M = 10, + PHY_SPEED_100M = 100, + PHY_SPEED_1000M = 1000, +} eGMAC_PHY_SPEED; + +/** + * @brief GMAC PHY Duplex + */ +typedef enum { + PHY_DUPLEX_HALF = 0, + PHY_DUPLEX_FULL = 1, +} eGMAC_PHY_DUPLEX; + +/** + * @brief GMAC PHY Auto Negrotetion + */ +typedef enum { + PHY_AUTONEG_DISABLE = 0, + PHY_AUTONEG_ENABLE = 1, +} eGMAC_PHY_NEGROTETION; + +/** + * @brief GMAC PHY Interface Mode + */ +typedef enum { + PHY_INTERFACE_MODE_MII, + PHY_INTERFACE_MODE_RMII, + PHY_INTERFACE_MODE_RGMII, + PHY_INTERFACE_MODE_NONE, +} eGMAC_PHY_Interface; + +/** + * @brief GMAC DMA IRQ Status + */ +typedef enum { + DMA_UNKNOWN = 0x0, + DMA_HANLE_RX = 0x1, + DMA_HANLE_TX = 0x2, + DMA_TX_ERROR = 0x10, + DMA_RX_ERROR = 0x20, +} eGMAC_IRQ_Status; + +/** + * @brief GMAC PHY OPS Structure Definition + */ +struct GMAC_PHY_OPS { + HAL_Status (*init)(struct GMAC_HANDLE *pGMAC); /**< Will be called during HAL_GMAC_PHYInit(). */ + HAL_Status (*config)(struct GMAC_HANDLE *pGMAC); /**< Called to configure the PHY, and modify the PHY, + based on the results. Should be called after HAL_GMAC_PHYInit(). */ + HAL_Status (*startup)(struct GMAC_HANDLE *pGMAC); /**< Called when starting up the PHY */ + HAL_Status (*shutdown)(struct GMAC_HANDLE *pGMAC); /**< Called when bringing down the PHY */ + HAL_Status (*reset)(struct GMAC_HANDLE *pGMAC); /**< Called when hardware reset */ + HAL_Status (*softreset)(struct GMAC_HANDLE *pGMAC);/**< Called when soft reset */ +}; + +/** + * @brief GMAC PHY Config Structure Definition + */ +struct GMAC_PHY_Config { + eGMAC_PHY_Interface interface;/**< Ethernet interface mode. */ + int16_t phyAddress; /**< Ethernet PHY address, + This parameter must be a number between Min = 0 and Max = 31 */ + eGMAC_PHY_NEGROTETION neg; /**< Selects or disable the AutoNegotiation mode for the external PHY, + The AutoNegotiation allows an automatic setting of the Speed + (10/100/1000 Mbps) and the mode (half/full-duplex). */ + eGMAC_PHY_SPEED speed; /**< Sets the Ethernet speed: 10/100/1000 Mbps + while disable AutoNegotiation. */ + eGMAC_PHY_DUPLEX duplexMode; /**< Selects the Ethernet duplex mode: Half-Duplex or + Full-Duplex mode while disable AutoNegotiation. */ + eGMAC_PHY_SPEED maxSpeed; /**< Sets the Ethernet max speed: 10/100/1000 Mbps. */ + uint32_t features; /**< Sets the Ethernet PHY features. */ +}; + +/** + * @brief GMAC PHY Status Structure Definition + */ +struct GMAC_PHY_STATUS { + eGMAC_PHY_Interface interface; /**< Ethernet interface mode. */ + + /* forced speed & duplex (no autoneg) + * partner speed & duplex & pause (autoneg) + */ + eGMAC_PHY_SPEED speed; /**< Ethernet speed. */ + eGMAC_PHY_DUPLEX duplex; /**< Ethernet duplex. */ + eGMAC_PHY_SPEED maxSpeed; /**< Ethernet max speed. */ + eGMAC_PHY_NEGROTETION neg; /**< Ethernet AutoNegotiation or not. */ + + /* The most recently read link state */ + int link; /**< Ethernet current link. */ + int oldLink; /**< Store the Ethernet last link. */ + + uint32_t features; /**< Ethernet PHY actual features. */ + uint32_t advertising; /**< Ethernet PHY advertising features. */ + uint32_t supported; /**< Ethernet PHY supported features. */ + + int16_t addr; /**< Ethernet PHY address. */ + int16_t pause; /**< Ethernet PHY address. */ + uint32_t phyID; /**< Ethernet PHY ID. */ +}; + +/** + * @brief GMAC Link Config Structure Definition + */ +struct GMAC_Link { + uint32_t speedMask; + uint32_t speed10; + uint32_t speed100; + uint32_t speed1000; + uint32_t duplex; +}; + +/** + * @brief GMAC DMA Descriptors Data Structure Definition + */ +struct GMAC_Desc { + volatile uint32_t des0; /**< DMA Descriptors first word */ + volatile uint32_t des1; /**< DMA Descriptors second word */ + volatile uint32_t des2; /**< DMA Descriptors third word */ + volatile uint32_t des3; /**< DMA Descriptors four word */ +}; + +/** + * @brief GMAC DMA Transfer Status Structure Definition + */ +struct GMAC_DMAStats { + uint32_t txUndeflowIRQ; + uint32_t txProcessStoppedIRQ; + uint32_t txJabberIRQ; + uint32_t rxOverflowIRQ; + uint32_t rxBufUnavIRQ; + uint32_t rxProcessStoppedIRQ; + uint32_t rxWatchdogIRQ; + uint32_t txEarlyIRQ; + uint32_t fatalBusErrorIRQ; + uint32_t normalIRQN; + uint32_t rxNormalIRQN; + uint32_t txNormallIRQN; + + uint32_t rxEarlyIRQ; + uint32_t thresHold; + uint32_t txPktN; + uint32_t rxPktN; + uint32_t txBytesN; + uint32_t rxBytesN; + uint32_t txErrors; + uint32_t rxErrors; +}; + +/** + * @brief GMAC device information Structure Definition + */ +struct GMAC_DEVICE_INFO { + uint32_t miiAddrShift; + uint32_t miiAddrMask; + uint32_t miiRegShift; + uint32_t miiRegMask; + uint32_t clkCsrShift; + uint32_t clkCsrMask; +}; + +/** + * @brief GMAC Handle Structure Definition + */ +struct GMAC_HANDLE { + struct GMAC_REG *pReg; /**< Register base address */ + uint32_t clkCSR; /**< clock csr value, div for MDC clock */ + + struct GMAC_DEVICE_INFO mac; /**< MAC information */ + + struct GMAC_PHY_OPS phyOps; /**< phy ops callback function */ + struct GMAC_PHY_Config phyConfig; /**< phy config provied by user */ + struct GMAC_PHY_STATUS phyStatus; /**< phy status */ + + struct GMAC_Link link; /**< GMAC link config */ + struct GMAC_DMAStats extraStatus; /**< GMAC DMA transfer status */ + + struct GMAC_Desc *rxDescs; /**< First Rx descriptor pointer */ + struct GMAC_Desc *rxDescs_dma; + struct GMAC_Desc *txDescs; /**< First Tx descriptor pointer */ + struct GMAC_Desc *txDescs_dma; + uint8_t *txBuf; /**< First Tx buffer pointer */ + uint8_t *txBuf_dma; + uint8_t *rxBuf; /**< First Tx buffer pointer */ + uint8_t *rxBuf_dma; + uint32_t txDescIdx; /**< Current Tx descriptor index */ + uint32_t rxDescIdx; /**< Current Rx descriptor pointer */ + uint32_t txSize; /**< Tx descriptor size*/ + uint32_t rxSize; /**< Rx descriptor size */ +}; + +/** + * @brief GMAC HW Information Definition + */ +struct HAL_GMAC_DEV { + struct GMAC_REG *pReg; + eCLOCK_Name clkID125M; + eCLOCK_Name clkID50M; + uint32_t clkGateID125M; + uint32_t clkGateID50M; + eCLOCK_Name pclkID; + uint32_t pclkGateID; + IRQn_Type irqNum; + ePM_RUNTIME_ID runtimeID; +}; + +/** @} */ + +/***************************** Function Declare ******************************/ +/** @defgroup GMAC_Public_Function_Declare Public Function Declare + * @{ + */ +HAL_Status HAL_GMAC_Init(struct GMAC_HANDLE *pGMAC, struct GMAC_REG *pReg, + uint32_t freq, eGMAC_PHY_Interface interface, + bool extClk); +HAL_Status HAL_GMAC_DeInit(struct GMAC_HANDLE *pGMAC); +HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr); +HAL_Status HAL_GMAC_Stop(struct GMAC_HANDLE *pGMAC); +void HAL_GMAC_EnableDmaIRQ(struct GMAC_HANDLE *pGMAC); +void HAL_GMAC_DisableDmaIRQ(struct GMAC_HANDLE *pGMAC); +HAL_Status HAL_GMAC_DMATxDescInit(struct GMAC_HANDLE *pGMAC, + struct GMAC_Desc *txDescs, + struct GMAC_Desc *txDescs_dma, + uint8_t *txBuff, uint8_t *txBuff_dma, uint32_t txBuffCount); +HAL_Status HAL_GMAC_DMARxDescInit(struct GMAC_HANDLE *pGMAC, + struct GMAC_Desc *rxDescs, + struct GMAC_Desc *rxDescs_dma, + uint8_t *rxBuff, uint8_t *rxBuff_dma, uint32_t rxBuffCount); +eGMAC_IRQ_Status HAL_GMAC_IRQHandler(struct GMAC_HANDLE *pGMAC); +HAL_Status HAL_GMAC_AdjustLink(struct GMAC_HANDLE *pGMAC, int32_t txDelay, + int32_t rxDelay); +uint32_t HAL_GMAC_GetTXIndex(struct GMAC_HANDLE *pGMAC); +uint32_t HAL_GMAC_GetRXIndex(struct GMAC_HANDLE *pGMAC); +uint8_t *HAL_GMAC_GetTXBuffer(struct GMAC_HANDLE *pGMAC); +uint8_t *HAL_GMAC_GetTXBufferDMA(struct GMAC_HANDLE *pGMAC); +uint8_t *HAL_GMAC_GetRXBuffer(struct GMAC_HANDLE *pGMAC); +uint8_t *HAL_GMAC_GetRXBufferDMA(struct GMAC_HANDLE *pGMAC); +HAL_Status HAL_GMAC_Send(struct GMAC_HANDLE *pGMAC, + void *packet, uint32_t length); +uint8_t *HAL_GMAC_Recv(struct GMAC_HANDLE *pGMAC, int32_t *length); +void HAL_GMAC_CleanRX(struct GMAC_HANDLE *pGMAC); +void HAL_GMAC_WriteHWAddr(struct GMAC_HANDLE *pGMAC, uint8_t *enetAddr); +HAL_Status HAL_GMAC_PHYInit(struct GMAC_HANDLE *pGMAC, + struct GMAC_PHY_Config *config); +HAL_Status HAL_GMAC_PHYStartup(struct GMAC_HANDLE *pGMAC); +HAL_Status HAL_GMAC_PHYUpdateLink(struct GMAC_HANDLE *pGMAC); +HAL_Status HAL_GMAC_PHYParseLink(struct GMAC_HANDLE *pGMAC); +int32_t HAL_GMAC_MDIORead(struct GMAC_HANDLE *pGMAC, int32_t mdioAddr, + int32_t mdioReg); +HAL_Status HAL_GMAC_MDIOWrite(struct GMAC_HANDLE *pGMAC, int32_t mdioAddr, + int32_t mdioReg, uint16_t mdioVal); +void HAL_GMAC_SetToRGMII(struct GMAC_HANDLE *pGMAC, + int32_t txDelay, int32_t rxDelay); +void HAL_GMAC_SetToRMII(struct GMAC_HANDLE *pGMAC); +void HAL_GMAC_SetRGMIISpeed(struct GMAC_HANDLE *pGMAC, int32_t speed); +void HAL_GMAC_SetRMIISpeed(struct GMAC_HANDLE *pGMAC, int32_t speed); +void HAL_GMAC_SetExtclkSrc(struct GMAC_HANDLE *pGMAC, bool extClk); + +/** @} */ + +#endif + +/** @} */ + +/** @} */ + +#endif /* HAL_GMAC_MODULE_ENABLED */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_gpio.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_gpio.h new file mode 100644 index 000000000..ec0a0a39f --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_gpio.h @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +#ifndef __HAL_GPIO_H +#define __HAL_GPIO_H + +#include "hal_def.h" +#include "hal_pinctrl.h" + +/***************************** MACRO Definition ******************************/ +/** @defgroup GPIO_Exported_Definition_Group1 Basic Definition + * @{ + */ + +#ifndef GPIO_VER_ID +#define GPIO_VER_ID (0U) +#endif + +#define PIN_NUMBER_PER_BANK (32) + +#define GPIO_PIN_SHIFT (0) /**< Bits 0-4: GPIO Pin number: 0 - 31 */ +#define GPIO_PIN_MASK (0x1f << GPIO_PIN_SHIFT) +#define GPIO_BANK_SHIFT (5) /**< Bits 5-7: GPIO Port number: 0 - 7 */ +#define GPIO_BANK_MASK (0x7 << GPIO_BANK_SHIFT) + +#define BANK_PIN(BANK, PIN) ((((BANK) << GPIO_BANK_SHIFT) & GPIO_BANK_MASK) + (((PIN) << GPIO_PIN_SHIFT) & GPIO_PIN_MASK)) + +/***************************** Structure Definition **************************/ +/** GPIO pin level definition */ +typedef enum { + GPIO_LOW, + GPIO_HIGH +} eGPIO_pinLevel; + +/** GPIO pin direction definition */ +typedef enum { + GPIO_IN, + GPIO_OUT +} eGPIO_pinDirection; + +/** GPIO pin debounce definition */ +typedef enum { + GPIO_DEBOUNCE_DIS, + GPIO_DEBOUNCE_EN +} eGPIO_pinDebounce; + +/** GPIO pin interrupt enable definition */ +typedef enum { + GPIO_INT_DISABLE, + GPIO_INT_ENABLE +} eGPIO_intEnable; + +/** GPIO pin interrupt type definition */ +typedef enum { + GPIO_INT_TYPE_NONE = 0x00000000, + GPIO_INT_TYPE_EDGE_RISING = 0x00000001, + GPIO_INT_TYPE_EDGE_FALLING = 0x00000002, + GPIO_INT_TYPE_EDGE_BOTH = (GPIO_INT_TYPE_EDGE_FALLING | GPIO_INT_TYPE_EDGE_RISING), + GPIO_INT_TYPE_LEVEL_HIGH = 0x00000004, + GPIO_INT_TYPE_LEVEL_LOW = 0x00000008, + GPIO_INT_TYPE_LEVEL_MASK = (GPIO_INT_TYPE_LEVEL_LOW | GPIO_INT_TYPE_LEVEL_HIGH), + GPIO_INT_TYPE_SENSE_MASK = 0x0000000f, + GPIO_INT_TYPE_DEFAULT = GPIO_INT_TYPE_SENSE_MASK, +} eGPIO_intType; + +/** GPIO pin interrupt mode definition */ +typedef enum { + GPIO_INT_MODE_EDGE_RISING, + GPIO_INT_MODE_EDGE_FALLING, + GPIO_INT_MODE_EDGE_RISING_FALLING, + GPIO_INT_MODE_LEVEL_HIGH, + GPIO_INT_MODE_LEVEL_LOW, + GPIO_INT_MODE_INVALID +} eGPIO_intMode; + +/** GPIO pin virtual model definition */ +typedef enum { + GPIO_VIRTUAL_MODEL_OS_A, + GPIO_VIRTUAL_MODEL_OS_B, + GPIO_VIRTUAL_MODEL_OS_C, + GPIO_VIRTUAL_MODEL_OS_D, +} eGPIO_VirtualModel; + +#define IS_GPIO_PIN_DIR(ACTION) (((ACTION) == GPIO_IN) || ((ACTION) == GPIO_OUT)) +#define IS_GPIO_PIN_LEVEL(ACTION) (((ACTION) == GPIO_LOW) || ((ACTION) == GPIO_HIGH)) + +#define IS_GPIO_PIN(PIN) ((PIN) != 0x00000000U) +#define IS_GPIO_HIGH_PIN(PIN) IS_GPIO_PIN(((PIN) & 0xFFFF0000U)) + +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_PIN_A0) || \ + ((PIN) == GPIO_PIN_A1) || \ + ((PIN) == GPIO_PIN_A2) || \ + ((PIN) == GPIO_PIN_A3) || \ + ((PIN) == GPIO_PIN_A4) || \ + ((PIN) == GPIO_PIN_A5) || \ + ((PIN) == GPIO_PIN_A6) || \ + ((PIN) == GPIO_PIN_A7) || \ + ((PIN) == GPIO_PIN_B0) || \ + ((PIN) == GPIO_PIN_B1) || \ + ((PIN) == GPIO_PIN_B2) || \ + ((PIN) == GPIO_PIN_B3) || \ + ((PIN) == GPIO_PIN_B4) || \ + ((PIN) == GPIO_PIN_B5) || \ + ((PIN) == GPIO_PIN_B6) || \ + ((PIN) == GPIO_PIN_B7) || \ + ((PIN) == GPIO_PIN_C0) || \ + ((PIN) == GPIO_PIN_C1) || \ + ((PIN) == GPIO_PIN_C2) || \ + ((PIN) == GPIO_PIN_C3) || \ + ((PIN) == GPIO_PIN_C4) || \ + ((PIN) == GPIO_PIN_C5) || \ + ((PIN) == GPIO_PIN_C6) || \ + ((PIN) == GPIO_PIN_C7) || \ + ((PIN) == GPIO_PIN_D0) || \ + ((PIN) == GPIO_PIN_D1) || \ + ((PIN) == GPIO_PIN_D2) || \ + ((PIN) == GPIO_PIN_D3) || \ + ((PIN) == GPIO_PIN_D4) || \ + ((PIN) == GPIO_PIN_D5) || \ + ((PIN) == GPIO_PIN_D6) || \ + ((PIN) == GPIO_PIN_D7)) + +/** @} */ +/***************************** Function Declare ******************************/ +/** @defgroup GPIO_Exported_Definition_Group2 Public Functions Declare. + * @{ + */ +eGPIO_pinDirection HAL_GPIO_GetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin); +eGPIO_pinLevel HAL_GPIO_GetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin); +eGPIO_pinLevel HAL_GPIO_GetPinData(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin); +uint32_t HAL_GPIO_GetBankLevel(struct GPIO_REG *pGPIO); + +HAL_Status HAL_GPIO_SetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinLevel level); +HAL_Status HAL_GPIO_SetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinDirection direction); +HAL_Status HAL_GPIO_SetIntType(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_intType mode); + +HAL_Status HAL_GPIO_SetPinsLevel(struct GPIO_REG *pGPIO, uint32_t mPins, eGPIO_pinLevel level); +HAL_Status HAL_GPIO_SetPinsDirection(struct GPIO_REG *pGPIO, uint32_t mPins, eGPIO_pinDirection direction); + +void HAL_GPIO_EnableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin); +void HAL_GPIO_DisableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin); +void HAL_GPIO_IRQHandler(struct GPIO_REG *pGPIO, eGPIO_bankId bank); + +#ifdef HAL_GPIO_VIRTUAL_MODEL_FEATURE_ENABLED +HAL_Status HAL_GPIO_EnableVirtualModel(struct GPIO_REG *pGPIO); +HAL_Status HAL_GPIO_DisableVirtualModel(struct GPIO_REG *pGPIO); +HAL_Status HAL_GPIO_SetVirtualModel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_VirtualModel vmodel); +#endif + +/* The parameter pin for this function is special, it's 0~31. */ +void HAL_GPIO_IRQDispatch(eGPIO_bankId bank, uint32_t pin); + +/** @} */ + +#endif +/** @} */ + +/** @} */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_list.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_list.h new file mode 100644 index 000000000..a71fc343e --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_list.h @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef _HAL_LIST_H_ +#define _HAL_LIST_H_ + +/***************************** Structure Definition **************************/ + +/** double list struct */ +struct HAL_LIST_NODE { + struct HAL_LIST_NODE *next; + struct HAL_LIST_NODE *prev; +}; + +typedef struct HAL_LIST_NODE HAL_LIST; + +/***************************** Function Declare ******************************/ +/** + * @brief cast a member of a structure out to the containing structure + * @param ptr: the pointer to the member. + * @param type: the type of the container struct this is embedded in. + * @param member: the name of the member within the struct. + */ +#define HAL_CONTAINER_OF(ptr, type, member) \ + ((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member))) + +/** + * @brief initialize a list object + * @param object: object itself. + */ +#define HAL_LIST_OBJECT_INIT(object) { &(object), &(object) } + +#define HAL_LIST_HEAD_INIT(name) { &(name), &(name) } + +/** + * @brief initialize a list head + * @param name: list name.. + */ +#define HAL_LIST_HEAD(name) \ + struct HAL_LIST_NODE name = HAL_LIST_HEAD_INIT(name) + +/** + * @brief initialize a list + * @param l: list to be initialized + */ +static inline void HAL_LIST_Init(HAL_LIST *l) +{ + l->next = l->prev = l; +} + +/** + * @brief insert a node after a list + * @param l: list to insert it + * @param n: new node to be inserted + */ +static inline void HAL_LIST_InsertAfter(HAL_LIST *l, HAL_LIST *n) +{ + l->next->prev = n; + n->next = l->next; + + l->next = n; + n->prev = l; +} + +/** + * @brief insert a node before a list + * @param n: new node to be inserted + * @param l: list to insert it + */ +static inline void HAL_LIST_InsertBefore(HAL_LIST *l, HAL_LIST *n) +{ + l->prev->next = n; + n->prev = l->prev; + + l->prev = n; + n->next = l; +} + +/** + * @brief remove node from list. + * @param n: the node to remove from the list. + */ +static inline void HAL_LIST_Remove(HAL_LIST *n) +{ + n->next->prev = n->prev; + n->prev->next = n->next; + + n->next = n->prev = n; +} + +/** + * @brief tests whether a list is empty + * @param l: the list to test. + */ +static inline int HAL_LIST_IsEmpty(const HAL_LIST *l) +{ + return l->next == l; +} + +/** + * @brief get the list length + * @param l: the list to get. + */ +static inline uint32_t HAL_LIST_Len(const HAL_LIST *l) +{ + uint32_t len = 0; + const HAL_LIST *p = l; + + while (p->next != l) { + p = p->next; + len++; + } + + return len; +} + +/** + * @brief get the struct for this entry + * @param node: the entry point + * @param type: the type of structure + * @param member: the name of list in structure + */ +#define HAL_LIST_ENTRY(node, type, member) \ + HAL_CONTAINER_OF(node, type, member) + +/** + * @brief iterate over a list + * @param pos: the rt_list_t * to use as a loop cursor. + * @param head: the head for your list. + */ +#define HAL_LIST_FOR_EACH(pos, head) \ + for (pos = (head)->next; pos != (head); pos = pos->next) + +/** + * @brief iterate over a list safe against removal of list entry + * @param pos: the rt_list_t * to use as a loop cursor. + * @param n: another rt_list_t * to use as temporary storage + * @param head: the head for your list. + */ +#define HAL_LIST_FOR_EACH_SAFE(pos, n, head) \ + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) + +/** + * @brief iterate over list of given type + * @param pos: the type * to use as a loop cursor. + * @param head: the head for your list. + * @param member: the name of the list_struct within the struct. + */ +#define HAL_LIST_FOR_EACH_ENTRY(pos, head, member) \ + for (pos = HAL_LIST_ENTRY((head)->next, __typeof__(*pos), member); \ + &pos->member != (head); \ + pos = HAL_LIST_ENTRY(pos->member.next, __typeof__(*pos), member)) + +/** + * @brief iterate over list of given type safe against removal of list entry + * @param pos: the type * to use as a loop cursor. + * @param n: another type * to use as temporary storage + * @param head: the head for your list. + * @param member: the name of the list_struct within the struct. + */ +#define HAL_LIST_FOR_EACH_ENTRY_SAFE(pos, n, head, member) \ + for (pos = HAL_LIST_ENTRY((head)->next, __typeof__(*pos), member), \ + n = HAL_LIST_ENTRY(pos->member.next, __typeof__(*pos), member); \ + &pos->member != (head); \ + pos = n, n = HAL_LIST_ENTRY(n->member.next, __typeof__(*n), member)) + +/** + * @brief get the first element from a list + * @param ptr: the list head to take the element from. + * @param type: the type of the struct this is embedded in. + * @param member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define HAL_LIST_FIRST_ENTRY(ptr, type, member) \ + HAL_LIST_ENTRY((ptr)->next, type, member) + +#endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_pinctrl.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_pinctrl.h new file mode 100644 index 000000000..ed07eab61 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_pinctrl.h @@ -0,0 +1,1267 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup PINCTRL + * @{ + */ + +#ifndef __HAL_PINCTRL_H__ +#define __HAL_PINCTRL_H__ + +#include "hal_def.h" + +/***************************** MACRO Definition ******************************/ +/** @defgroup PINCTRL_Exported_Definition_Group1 Basic Definition + * @{ + */ + +/** PINCTRL IOFUNC Select definition */ +typedef enum { + IOFUNC_SEL_M0, + IOFUNC_SEL_M1, + IOFUNC_SEL_M2, +} eIOFUNC_SEL; + +typedef enum { +#if defined(GPIO0) + GPIO0_A0 = 0, + GPIO0_A1, + GPIO0_A2, + GPIO0_A3, + GPIO0_A4, + GPIO0_A5, + GPIO0_A6, + GPIO0_A7, + GPIO0_B0 = 8, + GPIO0_B1, + GPIO0_B2, + GPIO0_B3, + GPIO0_B4, + GPIO0_B5, + GPIO0_B6, + GPIO0_B7, + GPIO0_C0 = 16, + GPIO0_C1, + GPIO0_C2, + GPIO0_C3, + GPIO0_C4, + GPIO0_C5, + GPIO0_C6, + GPIO0_C7, + GPIO0_D0 = 24, + GPIO0_D1, + GPIO0_D2, + GPIO0_D3, + GPIO0_D4, + GPIO0_D5, + GPIO0_D6, + GPIO0_D7, +#endif +#if defined(GPIO1) + GPIO1_A0 = 32, + GPIO1_A1, + GPIO1_A2, + GPIO1_A3, + GPIO1_A4, + GPIO1_A5, + GPIO1_A6, + GPIO1_A7, + GPIO1_B0 = 40, + GPIO1_B1, + GPIO1_B2, + GPIO1_B3, + GPIO1_B4, + GPIO1_B5, + GPIO1_B6, + GPIO1_B7, + GPIO1_C0 = 48, + GPIO1_C1, + GPIO1_C2, + GPIO1_C3, + GPIO1_C4, + GPIO1_C5, + GPIO1_C6, + GPIO1_C7, + GPIO1_D0 = 56, + GPIO1_D1, + GPIO1_D2, + GPIO1_D3, + GPIO1_D4, + GPIO1_D5, + GPIO1_D6, + GPIO1_D7, +#endif +#if defined(GPIO2) + GPIO2_A0 = 64, + GPIO2_A1, + GPIO2_A2, + GPIO2_A3, + GPIO2_A4, + GPIO2_A5, + GPIO2_A6, + GPIO2_A7, + GPIO2_B0 = 72, + GPIO2_B1, + GPIO2_B2, + GPIO2_B3, + GPIO2_B4, + GPIO2_B5, + GPIO2_B6, + GPIO2_B7, + GPIO2_C0 = 80, + GPIO2_C1, + GPIO2_C2, + GPIO2_C3, + GPIO2_C4, + GPIO2_C5, + GPIO2_C6, + GPIO2_C7, + GPIO2_D0 = 88, + GPIO2_D1, + GPIO2_D2, + GPIO2_D3, + GPIO2_D4, + GPIO2_D5, + GPIO2_D6, + GPIO2_D7, +#endif +#if defined(GPIO3) + GPIO3_A0 = 96, + GPIO3_A1, + GPIO3_A2, + GPIO3_A3, + GPIO3_A4, + GPIO3_A5, + GPIO3_A6, + GPIO3_A7, + GPIO3_B0 = 104, + GPIO3_B1, + GPIO3_B2, + GPIO3_B3, + GPIO3_B4, + GPIO3_B5, + GPIO3_B6, + GPIO3_B7, + GPIO3_C0 = 112, + GPIO3_C1, + GPIO3_C2, + GPIO3_C3, + GPIO3_C4, + GPIO3_C5, + GPIO3_C6, + GPIO3_C7, + GPIO3_D0 = 120, + GPIO3_D1, + GPIO3_D2, + GPIO3_D3, + GPIO3_D4, + GPIO3_D5, + GPIO3_D6, + GPIO3_D7, +#endif +#if defined(GPIO4) + GPIO4_A0 = 128, + GPIO4_A1, + GPIO4_A2, + GPIO4_A3, + GPIO4_A4, + GPIO4_A5, + GPIO4_A6, + GPIO4_A7, + GPIO4_B0 = 136, + GPIO4_B1, + GPIO4_B2, + GPIO4_B3, + GPIO4_B4, + GPIO4_B5, + GPIO4_B6, + GPIO4_B7, + GPIO4_C0 = 144, + GPIO4_C1, + GPIO4_C2, + GPIO4_C3, + GPIO4_C4, + GPIO4_C5, + GPIO4_C6, + GPIO4_C7, + GPIO4_D0 = 152, + GPIO4_D1, + GPIO4_D2, + GPIO4_D3, + GPIO4_D4, + GPIO4_D5, + GPIO4_D6, + GPIO4_D7, +#endif +#if defined(GPIO0_EXP) + GPIO0_EXP_A0 = 160, + GPIO0_EXP_A1, + GPIO0_EXP_A2, + GPIO0_EXP_A3, + GPIO0_EXP_A4, + GPIO0_EXP_A5, + GPIO0_EXP_A6, + GPIO0_EXP_A7, + GPIO0_EXP_B0 = 168, + GPIO0_EXP_B1, + GPIO0_EXP_B2, + GPIO0_EXP_B3, + GPIO0_EXP_B4, + GPIO0_EXP_B5, + GPIO0_EXP_B6, + GPIO0_EXP_B7, + GPIO0_EXP_C0 = 176, + GPIO0_EXP_C1, + GPIO0_EXP_C2, + GPIO0_EXP_C3, + GPIO0_EXP_C4, + GPIO0_EXP_C5, + GPIO0_EXP_C6, + GPIO0_EXP_C7, + GPIO0_EXP_D0 = 184, + GPIO0_EXP_D1, + GPIO0_EXP_D2, + GPIO0_EXP_D3, + GPIO0_EXP_D4, + GPIO0_EXP_D5, + GPIO0_EXP_D6, + GPIO0_EXP_D7, +#endif +#if defined(GPIO1_EXP) + GPIO1_EXP_A0 = 192, + GPIO1_EXP_A1, + GPIO1_EXP_A2, + GPIO1_EXP_A3, + GPIO1_EXP_A4, + GPIO1_EXP_A5, + GPIO1_EXP_A6, + GPIO1_EXP_A7, + GPIO1_EXP_B0 = 200, + GPIO1_EXP_B1, + GPIO1_EXP_B2, + GPIO1_EXP_B3, + GPIO1_EXP_B4, + GPIO1_EXP_B5, + GPIO1_EXP_B6, + GPIO1_EXP_B7, + GPIO1_EXP_C0 = 208, + GPIO1_EXP_C1, + GPIO1_EXP_C2, + GPIO1_EXP_C3, + GPIO1_EXP_C4, + GPIO1_EXP_C5, + GPIO1_EXP_C6, + GPIO1_EXP_C7, + GPIO1_EXP_D0 = 216, + GPIO1_EXP_D1, + GPIO1_EXP_D2, + GPIO1_EXP_D3, + GPIO1_EXP_D4, + GPIO1_EXP_D5, + GPIO1_EXP_D6, + GPIO1_EXP_D7, +#endif +#if defined(GPIO2_EXP) + GPIO2_EXP_A0 = 224, + GPIO2_EXP_A1, + GPIO2_EXP_A2, + GPIO2_EXP_A3, + GPIO2_EXP_A4, + GPIO2_EXP_A5, + GPIO2_EXP_A6, + GPIO2_EXP_A7, + GPIO2_EXP_B0 = 232, + GPIO2_EXP_B1, + GPIO2_EXP_B2, + GPIO2_EXP_B3, + GPIO2_EXP_B4, + GPIO2_EXP_B5, + GPIO2_EXP_B6, + GPIO2_EXP_B7, + GPIO2_EXP_C0 = 240, + GPIO2_EXP_C1, + GPIO2_EXP_C2, + GPIO2_EXP_C3, + GPIO2_EXP_C4, + GPIO2_EXP_C5, + GPIO2_EXP_C6, + GPIO2_EXP_C7, + GPIO2_EXP_D0 = 248, + GPIO2_EXP_D1, + GPIO2_EXP_D2, + GPIO2_EXP_D3, + GPIO2_EXP_D4, + GPIO2_EXP_D5, + GPIO2_EXP_D6, + GPIO2_EXP_D7, +#endif +#if defined(GPIO3_EXP) + GPIO3_EXP_A0 = 256, + GPIO3_EXP_A1, + GPIO3_EXP_A2, + GPIO3_EXP_A3, + GPIO3_EXP_A4, + GPIO3_EXP_A5, + GPIO3_EXP_A6, + GPIO3_EXP_A7, + GPIO3_EXP_B0 = 264, + GPIO3_EXP_B1, + GPIO3_EXP_B2, + GPIO3_EXP_B3, + GPIO3_EXP_B4, + GPIO3_EXP_B5, + GPIO3_EXP_B6, + GPIO3_EXP_B7, + GPIO3_EXP_C0 = 272, + GPIO3_EXP_C1, + GPIO3_EXP_C2, + GPIO3_EXP_C3, + GPIO3_EXP_C4, + GPIO3_EXP_C5, + GPIO3_EXP_C6, + GPIO3_EXP_C7, + GPIO3_EXP_D0 = 280, + GPIO3_EXP_D1, + GPIO3_EXP_D2, + GPIO3_EXP_D3, + GPIO3_EXP_D4, + GPIO3_EXP_D5, + GPIO3_EXP_D6, + GPIO3_EXP_D7, +#endif +#if defined(GPIO4_EXP) + GPIO4_EXP_A0 = 288, + GPIO4_EXP_A1, + GPIO4_EXP_A2, + GPIO4_EXP_A3, + GPIO4_EXP_A4, + GPIO4_EXP_A5, + GPIO4_EXP_A6, + GPIO4_EXP_A7, + GPIO4_EXP_B0 = 296, + GPIO4_EXP_B1, + GPIO4_EXP_B2, + GPIO4_EXP_B3, + GPIO4_EXP_B4, + GPIO4_EXP_B5, + GPIO4_EXP_B6, + GPIO4_EXP_B7, + GPIO4_EXP_C0 = 304, + GPIO4_EXP_C1, + GPIO4_EXP_C2, + GPIO4_EXP_C3, + GPIO4_EXP_C4, + GPIO4_EXP_C5, + GPIO4_EXP_C6, + GPIO4_EXP_C7, + GPIO4_EXP_D0 = 312, + GPIO4_EXP_D1, + GPIO4_EXP_D2, + GPIO4_EXP_D3, + GPIO4_EXP_D4, + GPIO4_EXP_D5, + GPIO4_EXP_D6, + GPIO4_EXP_D7, +#endif +#if defined(GPIO0_EXP1) + GPIO0_EXP1_A0 = 160, + GPIO0_EXP1_A1, + GPIO0_EXP1_A2, + GPIO0_EXP1_A3, + GPIO0_EXP1_A4, + GPIO0_EXP1_A5, + GPIO0_EXP1_A6, + GPIO0_EXP1_A7, + GPIO0_EXP1_B0 = 168, + GPIO0_EXP1_B1, + GPIO0_EXP1_B2, + GPIO0_EXP1_B3, + GPIO0_EXP1_B4, + GPIO0_EXP1_B5, + GPIO0_EXP1_B6, + GPIO0_EXP1_B7, + GPIO0_EXP1_C0 = 176, + GPIO0_EXP1_C1, + GPIO0_EXP1_C2, + GPIO0_EXP1_C3, + GPIO0_EXP1_C4, + GPIO0_EXP1_C5, + GPIO0_EXP1_C6, + GPIO0_EXP1_C7, + GPIO0_EXP1_D0 = 184, + GPIO0_EXP1_D1, + GPIO0_EXP1_D2, + GPIO0_EXP1_D3, + GPIO0_EXP1_D4, + GPIO0_EXP1_D5, + GPIO0_EXP1_D6, + GPIO0_EXP1_D7, +#endif +#if defined(GPIO1_EXP1) + GPIO1_EXP1_A0 = 192, + GPIO1_EXP1_A1, + GPIO1_EXP1_A2, + GPIO1_EXP1_A3, + GPIO1_EXP1_A4, + GPIO1_EXP1_A5, + GPIO1_EXP1_A6, + GPIO1_EXP1_A7, + GPIO1_EXP1_B0 = 200, + GPIO1_EXP1_B1, + GPIO1_EXP1_B2, + GPIO1_EXP1_B3, + GPIO1_EXP1_B4, + GPIO1_EXP1_B5, + GPIO1_EXP1_B6, + GPIO1_EXP1_B7, + GPIO1_EXP1_C0 = 208, + GPIO1_EXP1_C1, + GPIO1_EXP1_C2, + GPIO1_EXP1_C3, + GPIO1_EXP1_C4, + GPIO1_EXP1_C5, + GPIO1_EXP1_C6, + GPIO1_EXP1_C7, + GPIO1_EXP1_D0 = 216, + GPIO1_EXP1_D1, + GPIO1_EXP1_D2, + GPIO1_EXP1_D3, + GPIO1_EXP1_D4, + GPIO1_EXP1_D5, + GPIO1_EXP1_D6, + GPIO1_EXP1_D7, +#endif +#if defined(GPIO2_EXP1) + GPIO2_EXP1_A0 = 224, + GPIO2_EXP1_A1, + GPIO2_EXP1_A2, + GPIO2_EXP1_A3, + GPIO2_EXP1_A4, + GPIO2_EXP1_A5, + GPIO2_EXP1_A6, + GPIO2_EXP1_A7, + GPIO2_EXP1_B0 = 232, + GPIO2_EXP1_B1, + GPIO2_EXP1_B2, + GPIO2_EXP1_B3, + GPIO2_EXP1_B4, + GPIO2_EXP1_B5, + GPIO2_EXP1_B6, + GPIO2_EXP1_B7, + GPIO2_EXP1_C0 = 240, + GPIO2_EXP1_C1, + GPIO2_EXP1_C2, + GPIO2_EXP1_C3, + GPIO2_EXP1_C4, + GPIO2_EXP1_C5, + GPIO2_EXP1_C6, + GPIO2_EXP1_C7, + GPIO2_EXP1_D0 = 248, + GPIO2_EXP1_D1, + GPIO2_EXP1_D2, + GPIO2_EXP1_D3, + GPIO2_EXP1_D4, + GPIO2_EXP1_D5, + GPIO2_EXP1_D6, + GPIO2_EXP1_D7, +#endif +#if defined(GPIO3_EXP1) + GPIO3_EXP1_A0 = 256, + GPIO3_EXP1_A1, + GPIO3_EXP1_A2, + GPIO3_EXP1_A3, + GPIO3_EXP1_A4, + GPIO3_EXP1_A5, + GPIO3_EXP1_A6, + GPIO3_EXP1_A7, + GPIO3_EXP1_B0 = 264, + GPIO3_EXP1_B1, + GPIO3_EXP1_B2, + GPIO3_EXP1_B3, + GPIO3_EXP1_B4, + GPIO3_EXP1_B5, + GPIO3_EXP1_B6, + GPIO3_EXP1_B7, + GPIO3_EXP1_C0 = 272, + GPIO3_EXP1_C1, + GPIO3_EXP1_C2, + GPIO3_EXP1_C3, + GPIO3_EXP1_C4, + GPIO3_EXP1_C5, + GPIO3_EXP1_C6, + GPIO3_EXP1_C7, + GPIO3_EXP1_D0 = 280, + GPIO3_EXP1_D1, + GPIO3_EXP1_D2, + GPIO3_EXP1_D3, + GPIO3_EXP1_D4, + GPIO3_EXP1_D5, + GPIO3_EXP1_D6, + GPIO3_EXP1_D7, +#endif +#if defined(GPIO4_EXP1) + GPIO4_EXP1_A0 = 288, + GPIO4_EXP1_A1, + GPIO4_EXP1_A2, + GPIO4_EXP1_A3, + GPIO4_EXP1_A4, + GPIO4_EXP1_A5, + GPIO4_EXP1_A6, + GPIO4_EXP1_A7, + GPIO4_EXP1_B0 = 296, + GPIO4_EXP1_B1, + GPIO4_EXP1_B2, + GPIO4_EXP1_B3, + GPIO4_EXP1_B4, + GPIO4_EXP1_B5, + GPIO4_EXP1_B6, + GPIO4_EXP1_B7, + GPIO4_EXP1_C0 = 304, + GPIO4_EXP1_C1, + GPIO4_EXP1_C2, + GPIO4_EXP1_C3, + GPIO4_EXP1_C4, + GPIO4_EXP1_C5, + GPIO4_EXP1_C6, + GPIO4_EXP1_C7, + GPIO4_EXP1_D0 = 312, + GPIO4_EXP1_D1, + GPIO4_EXP1_D2, + GPIO4_EXP1_D3, + GPIO4_EXP1_D4, + GPIO4_EXP1_D5, + GPIO4_EXP1_D6, + GPIO4_EXP1_D7, +#endif +#if defined(GPIO0_EXP2) + GPIO0_EXP2_A0 = 320, + GPIO0_EXP2_A1, + GPIO0_EXP2_A2, + GPIO0_EXP2_A3, + GPIO0_EXP2_A4, + GPIO0_EXP2_A5, + GPIO0_EXP2_A6, + GPIO0_EXP2_A7, + GPIO0_EXP2_B0 = 328, + GPIO0_EXP2_B1, + GPIO0_EXP2_B2, + GPIO0_EXP2_B3, + GPIO0_EXP2_B4, + GPIO0_EXP2_B5, + GPIO0_EXP2_B6, + GPIO0_EXP2_B7, + GPIO0_EXP2_C0 = 336, + GPIO0_EXP2_C1, + GPIO0_EXP2_C2, + GPIO0_EXP2_C3, + GPIO0_EXP2_C4, + GPIO0_EXP2_C5, + GPIO0_EXP2_C6, + GPIO0_EXP2_C7, + GPIO0_EXP2_D0 = 344, + GPIO0_EXP2_D1, + GPIO0_EXP2_D2, + GPIO0_EXP2_D3, + GPIO0_EXP2_D4, + GPIO0_EXP2_D5, + GPIO0_EXP2_D6, + GPIO0_EXP2_D7, +#endif +#if defined(GPIO1_EXP2) + GPIO1_EXP2_A0 = 352, + GPIO1_EXP2_A1, + GPIO1_EXP2_A2, + GPIO1_EXP2_A3, + GPIO1_EXP2_A4, + GPIO1_EXP2_A5, + GPIO1_EXP2_A6, + GPIO1_EXP2_A7, + GPIO1_EXP2_B0 = 360, + GPIO1_EXP2_B1, + GPIO1_EXP2_B2, + GPIO1_EXP2_B3, + GPIO1_EXP2_B4, + GPIO1_EXP2_B5, + GPIO1_EXP2_B6, + GPIO1_EXP2_B7, + GPIO1_EXP2_C0 = 368, + GPIO1_EXP2_C1, + GPIO1_EXP2_C2, + GPIO1_EXP2_C3, + GPIO1_EXP2_C4, + GPIO1_EXP2_C5, + GPIO1_EXP2_C6, + GPIO1_EXP2_C7, + GPIO1_EXP2_D0 = 376, + GPIO1_EXP2_D1, + GPIO1_EXP2_D2, + GPIO1_EXP2_D3, + GPIO1_EXP2_D4, + GPIO1_EXP2_D5, + GPIO1_EXP2_D6, + GPIO1_EXP2_D7, +#endif +#if defined(GPIO2_EXP2) + GPIO2_EXP2_A0 = 384, + GPIO2_EXP2_A1, + GPIO2_EXP2_A2, + GPIO2_EXP2_A3, + GPIO2_EXP2_A4, + GPIO2_EXP2_A5, + GPIO2_EXP2_A6, + GPIO2_EXP2_A7, + GPIO2_EXP2_B0 = 392, + GPIO2_EXP2_B1, + GPIO2_EXP2_B2, + GPIO2_EXP2_B3, + GPIO2_EXP2_B4, + GPIO2_EXP2_B5, + GPIO2_EXP2_B6, + GPIO2_EXP2_B7, + GPIO2_EXP2_C0 = 400, + GPIO2_EXP2_C1, + GPIO2_EXP2_C2, + GPIO2_EXP2_C3, + GPIO2_EXP2_C4, + GPIO2_EXP2_C5, + GPIO2_EXP2_C6, + GPIO2_EXP2_C7, + GPIO2_EXP2_D0 = 408, + GPIO2_EXP2_D1, + GPIO2_EXP2_D2, + GPIO2_EXP2_D3, + GPIO2_EXP2_D4, + GPIO2_EXP2_D5, + GPIO2_EXP2_D6, + GPIO2_EXP2_D7, +#endif +#if defined(GPIO3_EXP2) + GPIO3_EXP2_A0 = 416, + GPIO3_EXP2_A1, + GPIO3_EXP2_A2, + GPIO3_EXP2_A3, + GPIO3_EXP2_A4, + GPIO3_EXP2_A5, + GPIO3_EXP2_A6, + GPIO3_EXP2_A7, + GPIO3_EXP2_B0 = 424, + GPIO3_EXP2_B1, + GPIO3_EXP2_B2, + GPIO3_EXP2_B3, + GPIO3_EXP2_B4, + GPIO3_EXP2_B5, + GPIO3_EXP2_B6, + GPIO3_EXP2_B7, + GPIO3_EXP2_C0 = 432, + GPIO3_EXP2_C1, + GPIO3_EXP2_C2, + GPIO3_EXP2_C3, + GPIO3_EXP2_C4, + GPIO3_EXP2_C5, + GPIO3_EXP2_C6, + GPIO3_EXP2_C7, + GPIO3_EXP2_D0 = 440, + GPIO3_EXP2_D1, + GPIO3_EXP2_D2, + GPIO3_EXP2_D3, + GPIO3_EXP2_D4, + GPIO3_EXP2_D5, + GPIO3_EXP2_D6, + GPIO3_EXP2_D7, +#endif +#if defined(GPIO4_EXP2) + GPIO4_EXP2_A0 = 448, + GPIO4_EXP2_A1, + GPIO4_EXP2_A2, + GPIO4_EXP2_A3, + GPIO4_EXP2_A4, + GPIO4_EXP2_A5, + GPIO4_EXP2_A6, + GPIO4_EXP2_A7, + GPIO4_EXP2_B0 = 456, + GPIO4_EXP2_B1, + GPIO4_EXP2_B2, + GPIO4_EXP2_B3, + GPIO4_EXP2_B4, + GPIO4_EXP2_B5, + GPIO4_EXP2_B6, + GPIO4_EXP2_B7, + GPIO4_EXP2_C0 = 464, + GPIO4_EXP2_C1, + GPIO4_EXP2_C2, + GPIO4_EXP2_C3, + GPIO4_EXP2_C4, + GPIO4_EXP2_C5, + GPIO4_EXP2_C6, + GPIO4_EXP2_C7, + GPIO4_EXP2_D0 = 472, + GPIO4_EXP2_D1, + GPIO4_EXP2_D2, + GPIO4_EXP2_D3, + GPIO4_EXP2_D4, + GPIO4_EXP2_D5, + GPIO4_EXP2_D6, + GPIO4_EXP2_D7, +#endif +#if defined(GPIO0_EXP3) + GPIO0_EXP3_A0 = 480, + GPIO0_EXP3_A1, + GPIO0_EXP3_A2, + GPIO0_EXP3_A3, + GPIO0_EXP3_A4, + GPIO0_EXP3_A5, + GPIO0_EXP3_A6, + GPIO0_EXP3_A7, + GPIO0_EXP3_B0 = 488, + GPIO0_EXP3_B1, + GPIO0_EXP3_B2, + GPIO0_EXP3_B3, + GPIO0_EXP3_B4, + GPIO0_EXP3_B5, + GPIO0_EXP3_B6, + GPIO0_EXP3_B7, + GPIO0_EXP3_C0 = 496, + GPIO0_EXP3_C1, + GPIO0_EXP3_C2, + GPIO0_EXP3_C3, + GPIO0_EXP3_C4, + GPIO0_EXP3_C5, + GPIO0_EXP3_C6, + GPIO0_EXP3_C7, + GPIO0_EXP3_D0 = 504, + GPIO0_EXP3_D1, + GPIO0_EXP3_D2, + GPIO0_EXP3_D3, + GPIO0_EXP3_D4, + GPIO0_EXP3_D5, + GPIO0_EXP3_D6, + GPIO0_EXP3_D7, +#endif +#if defined(GPIO1_EXP3) + GPIO1_EXP3_A0 = 512, + GPIO1_EXP3_A1, + GPIO1_EXP3_A2, + GPIO1_EXP3_A3, + GPIO1_EXP3_A4, + GPIO1_EXP3_A5, + GPIO1_EXP3_A6, + GPIO1_EXP3_A7, + GPIO1_EXP3_B0 = 520, + GPIO1_EXP3_B1, + GPIO1_EXP3_B2, + GPIO1_EXP3_B3, + GPIO1_EXP3_B4, + GPIO1_EXP3_B5, + GPIO1_EXP3_B6, + GPIO1_EXP3_B7, + GPIO1_EXP3_C0 = 528, + GPIO1_EXP3_C1, + GPIO1_EXP3_C2, + GPIO1_EXP3_C3, + GPIO1_EXP3_C4, + GPIO1_EXP3_C5, + GPIO1_EXP3_C6, + GPIO1_EXP3_C7, + GPIO1_EXP3_D0 = 536, + GPIO1_EXP3_D1, + GPIO1_EXP3_D2, + GPIO1_EXP3_D3, + GPIO1_EXP3_D4, + GPIO1_EXP3_D5, + GPIO1_EXP3_D6, + GPIO1_EXP3_D7, +#endif +#if defined(GPIO2_EXP3) + GPIO2_EXP3_A0 = 544, + GPIO2_EXP3_A1, + GPIO2_EXP3_A2, + GPIO2_EXP3_A3, + GPIO2_EXP3_A4, + GPIO2_EXP3_A5, + GPIO2_EXP3_A6, + GPIO2_EXP3_A7, + GPIO2_EXP3_B0 = 552, + GPIO2_EXP3_B1, + GPIO2_EXP3_B2, + GPIO2_EXP3_B3, + GPIO2_EXP3_B4, + GPIO2_EXP3_B5, + GPIO2_EXP3_B6, + GPIO2_EXP3_B7, + GPIO2_EXP3_C0 = 560, + GPIO2_EXP3_C1, + GPIO2_EXP3_C2, + GPIO2_EXP3_C3, + GPIO2_EXP3_C4, + GPIO2_EXP3_C5, + GPIO2_EXP3_C6, + GPIO2_EXP3_C7, + GPIO2_EXP3_D0 = 568, + GPIO2_EXP3_D1, + GPIO2_EXP3_D2, + GPIO2_EXP3_D3, + GPIO2_EXP3_D4, + GPIO2_EXP3_D5, + GPIO2_EXP3_D6, + GPIO2_EXP3_D7, +#endif +#if defined(GPIO3_EXP3) + GPIO3_EXP3_A0 = 576, + GPIO3_EXP3_A1, + GPIO3_EXP3_A2, + GPIO3_EXP3_A3, + GPIO3_EXP3_A4, + GPIO3_EXP3_A5, + GPIO3_EXP3_A6, + GPIO3_EXP3_A7, + GPIO3_EXP3_B0 = 584, + GPIO3_EXP3_B1, + GPIO3_EXP3_B2, + GPIO3_EXP3_B3, + GPIO3_EXP3_B4, + GPIO3_EXP3_B5, + GPIO3_EXP3_B6, + GPIO3_EXP3_B7, + GPIO3_EXP3_C0 = 592, + GPIO3_EXP3_C1, + GPIO3_EXP3_C2, + GPIO3_EXP3_C3, + GPIO3_EXP3_C4, + GPIO3_EXP3_C5, + GPIO3_EXP3_C6, + GPIO3_EXP3_C7, + GPIO3_EXP3_D0 = 600, + GPIO3_EXP3_D1, + GPIO3_EXP3_D2, + GPIO3_EXP3_D3, + GPIO3_EXP3_D4, + GPIO3_EXP3_D5, + GPIO3_EXP3_D6, + GPIO3_EXP3_D7, +#endif +#if defined(GPIO4_EXP3) + GPIO4_EXP3_A0 = 608, + GPIO4_EXP3_A1, + GPIO4_EXP3_A2, + GPIO4_EXP3_A3, + GPIO4_EXP3_A4, + GPIO4_EXP3_A5, + GPIO4_EXP3_A6, + GPIO4_EXP3_A7, + GPIO4_EXP3_B0 = 616, + GPIO4_EXP3_B1, + GPIO4_EXP3_B2, + GPIO4_EXP3_B3, + GPIO4_EXP3_B4, + GPIO4_EXP3_B5, + GPIO4_EXP3_B6, + GPIO4_EXP3_B7, + GPIO4_EXP3_C0 = 624, + GPIO4_EXP3_C1, + GPIO4_EXP3_C2, + GPIO4_EXP3_C3, + GPIO4_EXP3_C4, + GPIO4_EXP3_C5, + GPIO4_EXP3_C6, + GPIO4_EXP3_C7, + GPIO4_EXP3_D0 = 632, + GPIO4_EXP3_D1, + GPIO4_EXP3_D2, + GPIO4_EXP3_D3, + GPIO4_EXP3_D4, + GPIO4_EXP3_D5, + GPIO4_EXP3_D6, + GPIO4_EXP3_D7, +#endif + GPIO_NUM_MAX +} ePINCTRL_PIN; + +/** PINCTRL IOMUX definition */ +typedef enum { + PINCTRL_IOMUX_FUNC0, + PINCTRL_IOMUX_FUNC1, + PINCTRL_IOMUX_FUNC2, + PINCTRL_IOMUX_FUNC3, + PINCTRL_IOMUX_FUNC4, + PINCTRL_IOMUX_FUNC5, + PINCTRL_IOMUX_FUNC6, + PINCTRL_IOMUX_FUNC7, + PINCTRL_IOMUX_FUNC8, + PINCTRL_IOMUX_FUNC9, + PINCTRL_IOMUX_FUNC10, + PINCTRL_IOMUX_FUNC11, + PINCTRL_IOMUX_FUNC12, + PINCTRL_IOMUX_FUNC13, + PINCTRL_IOMUX_FUNC14, + PINCTRL_IOMUX_FUNC15 +} ePINCTRL_iomuxFunc; + +/** PINCTRL PULL definition */ +typedef enum { + PINCTRL_PULL_OD, + PINCTRL_PULL_UP, + PINCTRL_PULL_DOWN, + PINCTRL_PULL_KEEP +} ePINCTRL_pullMode; + +/** PINCTRL Drive Strength definition */ +typedef enum { + PINCTRL_DRIVE_LEVEL0, + PINCTRL_DRIVE_LEVEL1, + PINCTRL_DRIVE_LEVEL2, + PINCTRL_DRIVE_LEVEL3, + PINCTRL_DRIVE_LEVEL4, + PINCTRL_DRIVE_LEVEL5, + PINCTRL_DRIVE_LEVEL6, + PINCTRL_DRIVE_LEVEL7 +} ePINCTRL_driveLevel; + +/** PINCTRL Slew Rate definition */ +typedef enum { + PINCTRL_SLEWRATE_SLOW, + PINCTRL_SLEWRATE_FAST +} ePINCTRL_slewRate; + +/** PINCTRL Schmitt enable definition */ +typedef enum { + PINCTRL_SCHMITT_DIS, + PINCTRL_SCHMITT_EN +} ePINCTRL_schmitt; + +#define FLAG_MUX HAL_BIT(31) +#define FLAG_PUL HAL_BIT(30) +#define FLAG_DRV HAL_BIT(29) +#define FLAG_SRT HAL_BIT(28) +#define FLAG_SMT HAL_BIT(27) +#define SHIFT_MUX (0) +#define SHIFT_PUL (4) +#define SHIFT_DRV (8) +#define SHIFT_SRT (16) +#define SHIFT_SMT (18) +#define MASK_MUX (0xFU << SHIFT_MUX) +#define MASK_PUL (0xFU << SHIFT_PUL) +#define MASK_DRV (0xFFU << SHIFT_DRV) +#define MASK_SRT (0x3U << SHIFT_SRT) +#define MASK_SMT (0x3U << SHIFT_SMT) + +/** @brief PIN Configuration Mode + * Elements values convention: gggg g000 0000 ttrr dddd dddd pppp xxxx + * - ggggg : Flag to set Mux/Pull/Drive/Slewrate/Schmitt + * - tt : Schmitt value + * - rr : Slewrate value + * - dddddddd : Drive value + * - pppp : Pull value + * - xxxx : Mux mode value + */ +typedef enum { + PIN_CONFIG_MUX_FUNC0 = (0x0 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC1 = (0x1 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC2 = (0x2 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC3 = (0x3 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC4 = (0x4 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC5 = (0x5 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC6 = (0x6 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC7 = (0x7 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC8 = (0x8 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC9 = (0x9 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC10 = (0xa << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC11 = (0xb << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC12 = (0xc << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC13 = (0xd << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC14 = (0xe << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC15 = (0xf << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_DEFAULT = PIN_CONFIG_MUX_FUNC0, + +#if defined(SOC_SWALLOW) + PIN_CONFIG_PUL_NORMAL = (0x1 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_DEFAULT = (0x0 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_UP = PIN_CONFIG_PUL_DEFAULT, + PIN_CONFIG_PUL_DOWN = PIN_CONFIG_PUL_DEFAULT, + PIN_CONFIG_PUL_KEEP = PIN_CONFIG_PUL_DEFAULT, +#elif defined(SOC_RK3588) || defined(SOC_RK3576) + PIN_CONFIG_PUL_NORMAL = (0x0 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_DOWN = (0x1 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_KEEP = (0x2 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_UP = (0x3 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_DEFAULT = PIN_CONFIG_PUL_NORMAL, +#else + PIN_CONFIG_PUL_NORMAL = (0x0 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_UP = (0x1 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_DOWN = (0x2 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_KEEP = (0x3 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_DEFAULT = PIN_CONFIG_PUL_NORMAL, +#endif + +#if defined(SOC_RK3568) || defined(SOC_RV1106) || defined(SOC_RK3562) || defined(RKMCU_RK2118) + PIN_CONFIG_DRV_LEVEL0 = (0x1 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL1 = (0x3 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL2 = (0x7 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL3 = (0xf << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL4 = (0x1f << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL5 = (0x3f << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL_DEFAULT = PIN_CONFIG_DRV_LEVEL2, +#elif defined(SOC_RK3588) + PIN_CONFIG_DRV_LEVEL0 = (0x0 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL1 = (0x2 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL2 = (0x1 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL3 = (0x3 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL_DEFAULT = PIN_CONFIG_DRV_LEVEL2, +#elif defined(SOC_RK3576) + PIN_CONFIG_DRV_LEVEL0 = (0x0 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL1 = (0x4 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL2 = (0x2 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL3 = (0x6 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL4 = (0x1 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL5 = (0x5 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL_DEFAULT = PIN_CONFIG_DRV_LEVEL2, +#else + PIN_CONFIG_DRV_LEVEL0 = (0x0 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL1 = (0x1 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL2 = (0x2 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL3 = (0x3 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL4 = (0x4 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL5 = (0x5 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL6 = (0x6 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL7 = (0x7 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL_DEFAULT = PIN_CONFIG_DRV_LEVEL2, +#endif + +#if defined(SOC_RV1106) + PIN_CONFIG_SRT_SLOW = (0x0 << SHIFT_SRT | FLAG_SRT), + PIN_CONFIG_SRT_FAST = (0x3 << SHIFT_SRT | FLAG_SRT), + PIN_CONFIG_SRT_DEFAULT = PIN_CONFIG_SRT_FAST, +#elif defined(SOC_RK3562) + PIN_CONFIG_SRT_LEVEL0 = (0x0 << SHIFT_SRT | FLAG_SRT), + PIN_CONFIG_SRT_LEVEL1 = (0x1 << SHIFT_SRT | FLAG_SRT), + PIN_CONFIG_SRT_LEVEL2 = (0x2 << SHIFT_SRT | FLAG_SRT), + PIN_CONFIG_SRT_LEVEL3 = (0x3 << SHIFT_SRT | FLAG_SRT), + PIN_CONFIG_SRT_DEFAULT = PIN_CONFIG_SRT_LEVEL3, +#else + PIN_CONFIG_SRT_SLOW = (0x0 << SHIFT_SRT | FLAG_SRT), + PIN_CONFIG_SRT_FAST = (0x1 << SHIFT_SRT | FLAG_SRT), + PIN_CONFIG_SRT_DEFAULT = PIN_CONFIG_SRT_SLOW, +#endif + +#if defined(SOC_RK3562) + PIN_CONFIG_SMT_DISABLE_ALL = (0x0 << SHIFT_SMT | FLAG_SMT), + PIN_CONFIG_SMT_DISABLE_IE = (0x1 << SHIFT_SMT | FLAG_SMT), + PIN_CONFIG_SMT_ENABLE_ALL = (0x2 << SHIFT_SMT | FLAG_SMT), + PIN_CONFIG_SMT_DEFAULT = PIN_CONFIG_SMT_DISABLE_IE, +#else + PIN_CONFIG_SMT_DISABLE = (0x0 << SHIFT_SMT | FLAG_SMT), + PIN_CONFIG_SMT_ENABLE = (0x1 << SHIFT_SMT | FLAG_SMT), + PIN_CONFIG_SMT_DEFAULT = PIN_CONFIG_SMT_DISABLE, +#endif + + PIN_CONFIG_MAX = 0xFFFFFFFFU, +} ePINCTRL_configParam; + +typedef enum { + GRF_MUX_INFO = 0, + GRF_PUL_INFO, + GRF_DRV_INFO, + GRF_SRT_INFO, + GRF_SMT_INFO, + GRF_INFO_NUM +} ePIN_GRF_INFO_ID; + +#define PIN_BANK_CFG_FLAGS(chn, cnt, reg, \ + offset0, bpp0, ppr0, \ + offset1, bpp1, ppr1, \ + offset2, bpp2, ppr2, \ + offset3, bpp3, ppr3, \ + offset4, bpp4, ppr4) \ + { \ + .channel = chn, \ + .pinCount = cnt, \ + .grfBase = reg, \ + .GRFInfo[GRF_MUX_INFO] = { .offset = offset0, .bitsPerPin = bpp0, .pinsPerReg = ppr0 }, \ + .GRFInfo[GRF_PUL_INFO] = { .offset = offset1, .bitsPerPin = bpp1, .pinsPerReg = ppr1 }, \ + .GRFInfo[GRF_DRV_INFO] = { .offset = offset2, .bitsPerPin = bpp2, .pinsPerReg = ppr2 }, \ + .GRFInfo[GRF_SRT_INFO] = { .offset = offset3, .bitsPerPin = bpp3, .pinsPerReg = ppr3 }, \ + .GRFInfo[GRF_SMT_INFO] = { .offset = offset4, .bitsPerPin = bpp4, .pinsPerReg = ppr4 }, \ + } + +/** @defgroup ePINCTRL_GPIO_PINS Pins Definition + * @{ + */ +typedef enum { + GPIO_PIN_A0 = 0x00000001U, /*!< Pin 0 selected */ + GPIO_PIN_A1 = 0x00000002U, /*!< Pin 1 selected */ + GPIO_PIN_A2 = 0x00000004U, /*!< Pin 2 selected */ + GPIO_PIN_A3 = 0x00000008U, /*!< Pin 3 selected */ + GPIO_PIN_A4 = 0x00000010U, /*!< Pin 4 selected */ + GPIO_PIN_A5 = 0x00000020U, /*!< Pin 5 selected */ + GPIO_PIN_A6 = 0x00000040U, /*!< Pin 6 selected */ + GPIO_PIN_A7 = 0x00000080U, /*!< Pin 7 selected */ + GPIO_PIN_B0 = 0x00000100U, /*!< Pin 8 selected */ + GPIO_PIN_B1 = 0x00000200U, /*!< Pin 9 selected */ + GPIO_PIN_B2 = 0x00000400U, /*!< Pin 10 selected */ + GPIO_PIN_B3 = 0x00000800U, /*!< Pin 11 selected */ + GPIO_PIN_B4 = 0x00001000U, /*!< Pin 12 selected */ + GPIO_PIN_B5 = 0x00002000U, /*!< Pin 13 selected */ + GPIO_PIN_B6 = 0x00004000U, /*!< Pin 14 selected */ + GPIO_PIN_B7 = 0x00008000U, /*!< Pin 15 selected */ + GPIO_PIN_C0 = 0x00010000U, /*!< Pin 16 selected */ + GPIO_PIN_C1 = 0x00020000U, /*!< Pin 17 selected */ + GPIO_PIN_C2 = 0x00040000U, /*!< Pin 18 selected */ + GPIO_PIN_C3 = 0x00080000U, /*!< Pin 19 selected */ + GPIO_PIN_C4 = 0x00100000U, /*!< Pin 20 selected */ + GPIO_PIN_C5 = 0x00200000U, /*!< Pin 21 selected */ + GPIO_PIN_C6 = 0x00400000U, /*!< Pin 22 selected */ + GPIO_PIN_C7 = 0x00800000U, /*!< Pin 23 selected */ + GPIO_PIN_D0 = 0x01000000U, /*!< Pin 24 selected */ + GPIO_PIN_D1 = 0x02000000U, /*!< Pin 25 selected */ + GPIO_PIN_D2 = 0x04000000U, /*!< Pin 26 selected */ + GPIO_PIN_D3 = 0x08000000U, /*!< Pin 27 selected */ + GPIO_PIN_D4 = 0x10000000U, /*!< Pin 28 selected */ + GPIO_PIN_D5 = 0x20000000U, /*!< Pin 29 selected */ + GPIO_PIN_D6 = 0x40000000U, /*!< Pin 30 selected */ + GPIO_PIN_D7 = 0x80000000U, /*!< Pin 31 selected */ +} ePINCTRL_GPIO_PINS; + +#define GPIO_PIN_ALL (0xFFFFFFFFU) /*!< All pins selected */ + +/** @} */ + +#define ROUTE_VAL(v, s, m) (((v) << (s)) | (m) << ((s) + 16)) + +/***************************** Structure Definition **************************/ + +struct PINCTRL_GRF_INFO { + uint16_t offset; + uint8_t bitsPerPin; + uint8_t pinsPerReg; +}; + +struct PINCTRL_MUX_RECAL_DATA { + uint32_t reg; + uint8_t bank; + uint8_t pin; + uint8_t bit; + uint8_t mask; +}; + +struct PINCTRL_MUX_ROUTE_DATA { + uint32_t routeReg; + uint32_t routeVal; + uint32_t pin; + uint8_t bank; + uint8_t func; +}; + +struct PINCTRL_BANK_INFO { + struct PINCTRL_GRF_INFO GRFInfo[GRF_INFO_NUM]; + uint32_t grfBase; + uint8_t pinCount; + uint8_t channel; +}; + +struct HAL_PINCTRL_DEV { + const struct PINCTRL_BANK_INFO *banks; + const struct PINCTRL_MUX_RECAL_DATA *muxRecalData; + const struct PINCTRL_MUX_ROUTE_DATA *muxRouteData; + uint8_t banksNum; + uint8_t muxRecalDataNum; + uint8_t muxRouteDataNum; +}; + +/** @brief Rockchip pinctrl device struct define + * Define a struct for pinctrl, including banks info, bank number, + * and grf info about iomux offset, iomux bit info, drive/pull/ + * slewrate/schmitt offset and bit info. + */ +extern const struct HAL_PINCTRL_DEV g_pinDev; + +/** @} */ + +/***************************** Function Declare ******************************/ +/** @defgroup PINCTRL_Public_Function_Declare Public Function Declare + * @{ + */ + +HAL_Status HAL_PINCTRL_Suspend(void); +HAL_Status HAL_PINCTRL_Resume(void); + +HAL_Status HAL_PINCTRL_Init(void); +HAL_Status HAL_PINCTRL_DeInit(void); + +HAL_Status HAL_PINCTRL_SetParam(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param); +HAL_Status HAL_PINCTRL_SetIOMUX(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param); +#ifdef RM0_IO +HAL_Status HAL_PINCTRL_SetRMIO(eGPIO_bankId bank, uint32_t rmioPin, eRMIO_Name rmioFunc); +#endif + +HAL_Status HAL_PINCTRL_IOFuncSelForCIF(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForEMMC(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForFLASH(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForFSPI(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForLCDC(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForMIPICSI(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForRGMII(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForGMAC0(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForGMAC1(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForSDIO(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForSDMMC0(eIOFUNC_SEL mode); + +HAL_Status HAL_PINCTRL_IOFuncSelForCAN0(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForCAN1(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForCAN2(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForCAN3(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForCAN4(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForCAN5(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2C0(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2C1(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2C2(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2C3(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2C4(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2C5(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2S0(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2S1(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2S2(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM0(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM1(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM2(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM3(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM4(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM5(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM6(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM7(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM8(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM9(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM10(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM11(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForSPI0(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForSPI1(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForSPI2(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForSPI3(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForSPI4(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForSPI5(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART0(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART1(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART2(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART3(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART4(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART5(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART6(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART7(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART8(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART9(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART10(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART11(eIOFUNC_SEL mode); + +/** @} */ + +#endif /* __HAL_PINCTRL_H__ */ + +/** @} */ + +/** @} */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_pm.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_pm.h new file mode 100644 index 000000000..5ce30c909 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_pm.h @@ -0,0 +1,200 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup PM + * @{ + */ + +#ifndef _HAL_PM_H_ +#define _HAL_PM_H_ + +#include "hal_def.h" + +/***************************** MACRO Definition ******************************/ +/** @defgroup DEMO_Exported_Definition_Group1 Basic Definition + * @{ + */ + +#define PM_RUNTIME_TYPE_MUTI_SFT (3) +#define PM_RUNTIME_PER_TYPE_NUM (8) + +#define PM_RUNTIME_TYPE_TO_FIRST_ID(type) ((type) << PM_RUNTIME_TYPE_MUTI_SFT) +#define PM_RUNTIME_ID_TO_TYPE(id) ((id) >> PM_RUNTIME_TYPE_MUTI_SFT) +#define PM_RUNTIME_ID_TO_TYPE_OFFSET(id) ((id) % PM_RUNTIME_PER_TYPE_NUM) +#define PM_RUNTIME_ID_TYPE_BIT_MSK(id) HAL_BIT(((id) % PM_RUNTIME_PER_TYPE_NUM)) + +#define PM_DISPLAY_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_DISPLAY]) +#define PM_UART_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_UART]) +#define PM_I2C_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_I2C]) +#define PM_INTF_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_INTF]) +#define PM_HS_INTF_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_HS_INTF]) +#define PM_SPI_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_SPI]) +#define PM_CIF_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_CIF]) + +/* suspend config id */ +#define PM_SLEEP_MODE_CONFIG 0x01 +#define PM_SLEEP_WAKEUP_SOURCE 0x02 + +enum { + PM_RUNTIME_TYPE_INTF = 0, /**< normal interface */ + PM_RUNTIME_TYPE_DISPLAY, + PM_RUNTIME_TYPE_AUDIO, + PM_RUNTIME_TYPE_HS_INTF, /**< high speed interface */ + PM_RUNTIME_TYPE_STORAGE, + PM_RUNTIME_TYPE_UART, + PM_RUNTIME_TYPE_I2C, + PM_RUNTIME_TYPE_SPI, + PM_RUNTIME_TYPE_CIF, + PM_RUNTIME_TYPE_DEVICE, + PM_RUNTIME_TYPE_END, +}; + +typedef enum { + PM_RUNTIME_IDLE_ONLY = 0, + PM_RUNTIME_IDLE_NORMAL, + PM_RUNTIME_IDLE_DEEP, + PM_RUNTIME_IDLE_DEEP1, + PM_RUNTIME_IDLE_DEEP2, +} ePM_RUNTIME_idleMode; + +typedef enum { + PM_RUNTIME_ID_INTF_INVLD = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_INTF), /**< the id = 0, is means invalid */ + PM_RUNTIME_ID_SPI_APB, + PM_RUNTIME_ID_VOP = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_DISPLAY), + PM_RUNTIME_ID_MIPI, + + PM_RUNTIME_ID_I2S = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_AUDIO), + PM_RUNTIME_ID_I2S1, + PM_RUNTIME_ID_I2S2, + PM_RUNTIME_ID_ADC, + PM_RUNTIME_ID_DMA, + + PM_RUNTIME_ID_USB = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_HS_INTF), + PM_RUNTIME_ID_SDIO, + + PM_RUNTIME_ID_UART0 = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_UART), + PM_RUNTIME_ID_UART1, + PM_RUNTIME_ID_UART2, + PM_RUNTIME_ID_UART3, + PM_RUNTIME_ID_UART4, + PM_RUNTIME_ID_UART5, + PM_RUNTIME_ID_UART6, + PM_RUNTIME_ID_UART7, + PM_RUNTIME_ID_UART8, + PM_RUNTIME_ID_UART9, + + PM_RUNTIME_ID_I2C0 = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_I2C), + PM_RUNTIME_ID_I2C1, + PM_RUNTIME_ID_I2C2, + PM_RUNTIME_ID_I2C3, + PM_RUNTIME_ID_I2C4, + PM_RUNTIME_ID_I2C5, + + PM_RUNTIME_ID_SPI = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_SPI), + PM_RUNTIME_ID_CIF = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_CIF), + + PM_RUNTIME_ID_END, +} ePM_RUNTIME_ID; + +/***************************** Structure Definition **************************/ +struct PM_RUNTIME_INFO { + uint8_t bits[PM_RUNTIME_TYPE_END]; +}; + +#ifdef HAL_PM_SLEEP_MODULE_ENABLED +struct PM_SUSPEND_INFO { + union { + struct { + uint32_t uartChannel : 4; /*!< bit: 0.. 3 uart debug channel num */ + uint32_t uartValid : 1; /*!< bit: 4 uart channel valid flag */ + uint32_t _reserved : 27; /*!< bit: 5..31 Reserved */ + } flag; + uint32_t suspendFlag; + }; +}; + +struct SLEEP_CONFIG_DATA { + uint32_t suspendMode; + uint32_t suspendWkupSrc; +}; +#endif + +/** @} */ +/***************************** Function Declare ******************************/ +/** @defgroup PM_Public_Function_Declare Public Function Declare + * @{ + */ +#ifdef HAL_PM_SLEEP_MODULE_ENABLED +/** + * @brief it is the enterpoint for suspend invoked by a os's powermanager implement. + * @param suspendInfo: suspend information for controlling + * @return HAL_Status + */ +int HAL_SYS_Suspend(struct PM_SUSPEND_INFO *suspendInfo); +struct SLEEP_CONFIG_DATA *HAL_SYS_GetSuspendConfig(void); +HAL_Status HAL_SYS_SuspendConfig(uint32_t id, uint32_t data); +#endif + +#ifdef HAL_PM_CPU_SLEEP_MODULE_ENABLED +void HAL_CPU_ArchSuspend(uint32_t *ptr); +void HAL_CPU_ArchResume(void); +void HAL_CPU_DoResume(void); + +void HAL_NVIC_SuspendSave(void); +void HAL_NVIC_ResumeRestore(void); + +void HAL_SCB_SuspendSave(void); +void HAL_SCB_ResumeRestore(void); + +int HAL_CPU_SuspendEnter(uint32_t flag, int (*suspend)(uint32_t)); +void HAL_CPU_SuspendSave(uint32_t *ptr, uint32_t ptrsz, uint32_t sp, uint32_t *ptrSave); +#endif + +#ifdef HAL_PM_RUNTIME_MODULE_ENABLED +HAL_Status HAL_PM_RuntimeRequest(ePM_RUNTIME_ID runtimeId); +HAL_Status HAL_PM_RuntimeRelease(ePM_RUNTIME_ID runtimeId); +const struct PM_RUNTIME_INFO *HAL_PM_RuntimeGetData(void); + +/** + * @brief it is for runtime power manager. + * @param idleMode: the soc pm mode will be config + * @return the mask bits indicate request source. + */ +uint32_t HAL_PM_RuntimeEnter(ePM_RUNTIME_idleMode idleMode); +#endif + +/** + * @brief it is for statting a pm timer . + * @param timeoutCount: the next timeout count + * @param needTimeout: if ture, need to start a timer. + * @return HAL_Status. + */ +HAL_Status HAL_PM_TimerStart(uint64_t timeoutCount, bool needTimeout); + +/** + * @brief it is for stopping a pm timer . + * @return HAL_Status. + */ +HAL_Status HAL_PM_TimerStop(void); + +/** + * @brief it is for getting the sleep time. + * @return the sleep time. + */ +uint64_t HAL_PM_GetTimerCount(void); + +/** @} */ + +#endif + +/** @} */ + +/** @} */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_timer.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_timer.h new file mode 100644 index 000000000..0f815b941 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_timer.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +#ifdef HAL_TIMER_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup TIMER + * @{ + */ + +#ifndef _HAL_TIMER_H_ +#define _HAL_TIMER_H_ + +#include "hal_def.h" + +/***************************** MACRO Definition ******************************/ + +/** @defgroup TIMER_Exported_Definition_Group1 Basic Definition + * @{ + */ + +typedef enum { + TIMER_FREE_RUNNING = 0, + TIMER_USER_DEFINED, + TIMER_MODE_MAX +} eTIMER_MODE; + +/***************************** Structure Definition **************************/ + +/** @} */ +/***************************** Function Declare ******************************/ +/** @defgroup TIMER_Public_Function_Declare Public Function Declare + * @{ + */ + +HAL_Status HAL_TIMER_Stop(struct TIMER_REG *pReg); +HAL_Status HAL_TIMER_Start(struct TIMER_REG *pReg); +HAL_Status HAL_TIMER_Stop_IT(struct TIMER_REG *pReg); +HAL_Status HAL_TIMER_Start_IT(struct TIMER_REG *pReg); +HAL_Status HAL_TIMER_SetCount(struct TIMER_REG *pReg, uint64_t usTick); +uint64_t HAL_TIMER_GetCount(struct TIMER_REG *pReg); +HAL_Status HAL_TIMER0_Handler(void); +HAL_Status HAL_TIMER1_Handler(void); +HAL_Status HAL_TIMER_Init(struct TIMER_REG *pReg, eTIMER_MODE mode); +HAL_Status HAL_TIMER_SysTimerInit(struct TIMER_REG *pReg); +HAL_Status HAL_TIMER_DeInit(struct TIMER_REG *pReg); +HAL_Status HAL_TIMER_ClrInt(struct TIMER_REG *pReg); + +/** @} */ + +#endif + +/** @} */ + +/** @} */ + +#endif /* HAL_TIMER_MODULE_ENABLED */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/rk3568.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/rk3568.h new file mode 100644 index 000000000..09e399c20 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/rk3568.h @@ -0,0 +1,16518 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef __RK3568_H +#define __RK3568_H +#ifdef __cplusplus + extern "C" { +#endif +/****************************************************************************************/ +/* */ +/* Module Structure Section */ +/* */ +/****************************************************************************************/ +#ifndef __ASSEMBLY__ +/* GRF Register Structure Define */ +struct GRF_REG { + __IO uint32_t GPIO0A_IOMUX_L; /* Address Offset: 0x0000 */ + __IO uint32_t GPIO0A_IOMUX_H; /* Address Offset: 0x0004 */ + __IO uint32_t GPIO0B_IOMUX_L; /* Address Offset: 0x0008 */ + __IO uint32_t GPIO0B_IOMUX_H; /* Address Offset: 0x000C */ + __IO uint32_t GPIO0C_IOMUX_L; /* Address Offset: 0x0010 */ + __IO uint32_t GPIO0C_IOMUX_H; /* Address Offset: 0x0014 */ + __IO uint32_t GPIO0D_IOMUX_L; /* Address Offset: 0x0018 */ + __IO uint32_t GPIO0D_IOMUX_H; /* Address Offset: 0x001C */ + __IO uint32_t GPIO0A_P; /* Address Offset: 0x0020 */ + __IO uint32_t GPIO0B_P; /* Address Offset: 0x0024 */ + __IO uint32_t GPIO0C_P; /* Address Offset: 0x0028 */ + __IO uint32_t GPIO0D_P; /* Address Offset: 0x002C */ + __IO uint32_t GPIO0A_IE; /* Address Offset: 0x0030 */ + __IO uint32_t GPIO0B_IE; /* Address Offset: 0x0034 */ + __IO uint32_t GPIO0C_IE; /* Address Offset: 0x0038 */ + __IO uint32_t GPIO0D_IE; /* Address Offset: 0x003C */ + __IO uint32_t GPIO0A_OPD; /* Address Offset: 0x0040 */ + __IO uint32_t GPIO0B_OPD; /* Address Offset: 0x0044 */ + __IO uint32_t GPIO0C_OPD; /* Address Offset: 0x0048 */ + __IO uint32_t GPIO0D_OPD; /* Address Offset: 0x004C */ + __IO uint32_t GPIO0A_SUS; /* Address Offset: 0x0050 */ + __IO uint32_t GPIO0B_SUS; /* Address Offset: 0x0054 */ + __IO uint32_t GPIO0C_SUS; /* Address Offset: 0x0058 */ + __IO uint32_t GPIO0D_SUS; /* Address Offset: 0x005C */ + __IO uint32_t GPIO0A_SL; /* Address Offset: 0x0060 */ + __IO uint32_t GPIO0B_SL; /* Address Offset: 0x0064 */ + __IO uint32_t GPIO0C_SL; /* Address Offset: 0x0068 */ + __IO uint32_t GPIO0D_SL; /* Address Offset: 0x006C */ + __IO uint32_t GPIO0A_DS_0; /* Address Offset: 0x0070 */ + __IO uint32_t GPIO0A_DS_1; /* Address Offset: 0x0074 */ + __IO uint32_t GPIO0A_DS_2; /* Address Offset: 0x0078 */ + __IO uint32_t GPIO0A_DS_3; /* Address Offset: 0x007C */ + __IO uint32_t GPIO0B_DS_0; /* Address Offset: 0x0080 */ + __IO uint32_t GPIO0B_DS_1; /* Address Offset: 0x0084 */ + __IO uint32_t GPIO0B_DS_2; /* Address Offset: 0x0088 */ + __IO uint32_t GPIO0B_DS_3; /* Address Offset: 0x008C */ + __IO uint32_t GPIO0C_DS_0; /* Address Offset: 0x0090 */ + __IO uint32_t GPIO0C_DS_1; /* Address Offset: 0x0094 */ + __IO uint32_t GPIO0C_DS_2; /* Address Offset: 0x0098 */ + __IO uint32_t GPIO0C_DS_3; /* Address Offset: 0x009C */ + __IO uint32_t GPIO0D_DS_0; /* Address Offset: 0x00A0 */ + __IO uint32_t GPIO0D_DS_1; /* Address Offset: 0x00A4 */ + __IO uint32_t GPIO0D_DS_2; /* Address Offset: 0x00A8 */ + __IO uint32_t GPIO0D_DS_3; /* Address Offset: 0x00AC */ + uint32_t RESERVED00B0[20]; /* Address Offset: 0x00B0 */ + __IO uint32_t SOC_CON0; /* Address Offset: 0x0100 */ + __IO uint32_t SOC_CON1; /* Address Offset: 0x0104 */ + __IO uint32_t SOC_CON2; /* Address Offset: 0x0108 */ + __IO uint32_t SOC_CON3; /* Address Offset: 0x010C */ + __IO uint32_t SOC_CON4; /* Address Offset: 0x0110 */ + __IO uint32_t SOC_CON5; /* Address Offset: 0x0114 */ + uint32_t RESERVED0118[2]; /* Address Offset: 0x0118 */ + __I uint32_t SOC_STATUS; /* Address Offset: 0x0120 */ + uint32_t RESERVED0124[7]; /* Address Offset: 0x0124 */ + __IO uint32_t IO_VSEL0; /* Address Offset: 0x0140 */ + __IO uint32_t IO_VSEL1; /* Address Offset: 0x0144 */ + __IO uint32_t IO_VSEL2; /* Address Offset: 0x0148 */ + uint32_t RESERVED014C[13]; /* Address Offset: 0x014C */ + __IO uint32_t DLL_CON0; /* Address Offset: 0x0180 */ + uint32_t RESERVED0184[31]; /* Address Offset: 0x0184 */ + __IO uint32_t OS_REG0; /* Address Offset: 0x0200 */ + __IO uint32_t OS_REG1; /* Address Offset: 0x0204 */ + __IO uint32_t OS_REG2; /* Address Offset: 0x0208 */ + __IO uint32_t OS_REG3; /* Address Offset: 0x020C */ + __IO uint32_t OS_REG4; /* Address Offset: 0x0210 */ + __IO uint32_t OS_REG5; /* Address Offset: 0x0214 */ + __IO uint32_t OS_REG6; /* Address Offset: 0x0218 */ + __IO uint32_t OS_REG7; /* Address Offset: 0x021C */ + __IO uint32_t OS_REG8; /* Address Offset: 0x0220 */ + __IO uint32_t OS_REG9; /* Address Offset: 0x0224 */ + __IO uint32_t OS_REG10; /* Address Offset: 0x0228 */ + __IO uint32_t OS_REG11; /* Address Offset: 0x022C */ + __IO uint32_t RESET_FUNCTION_STATUS; /* Address Offset: 0x0230 */ + __IO uint32_t RESET_FUNCTION_CLR; /* Address Offset: 0x0234 */ + uint32_t RESERVED0238[82]; /* Address Offset: 0x0238 */ + __IO uint32_t SIG_DETECT_CON; /* Address Offset: 0x0380 */ + uint32_t RESERVED0384[3]; /* Address Offset: 0x0384 */ + __IO uint32_t SIG_DETECT_STATUS; /* Address Offset: 0x0390 */ + uint32_t RESERVED0394[3]; /* Address Offset: 0x0394 */ + __IO uint32_t SIG_DETECT_STATUS_CLEAR; /* Address Offset: 0x03A0 */ + uint32_t RESERVED03A4[3]; /* Address Offset: 0x03A4 */ + __IO uint32_t SDMMC_DET_COUNTER; /* Address Offset: 0x03B0 */ + uint32_t RESERVED03B4[65299]; /* Address Offset: 0x03B4 */ + __IO uint32_t GPIO1A_IOMUX_L; /* Address Offset: 0x40000 */ + __IO uint32_t GPIO1A_IOMUX_H; /* Address Offset: 0x40004 */ + __IO uint32_t GPIO1B_IOMUX_L; /* Address Offset: 0x40008 */ + __IO uint32_t GPIO1B_IOMUX_H; /* Address Offset: 0x4000C */ + __IO uint32_t GPIO1C_IOMUX_L; /* Address Offset: 0x40010 */ + __IO uint32_t GPIO1C_IOMUX_H; /* Address Offset: 0x40014 */ + __IO uint32_t GPIO1D_IOMUX_L; /* Address Offset: 0x40018 */ + __IO uint32_t GPIO1D_IOMUX_H; /* Address Offset: 0x4001C */ + __IO uint32_t GPIO2A_IOMUX_L; /* Address Offset: 0x40020 */ + __IO uint32_t GPIO2A_IOMUX_H; /* Address Offset: 0x40024 */ + __IO uint32_t GPIO2B_IOMUX_L; /* Address Offset: 0x40028 */ + __IO uint32_t GPIO2B_IOMUX_H; /* Address Offset: 0x4002C */ + __IO uint32_t GPIO2C_IOMUX_L; /* Address Offset: 0x40030 */ + __IO uint32_t GPIO2C_IOMUX_H; /* Address Offset: 0x40034 */ + __IO uint32_t GPIO2D_IOMUX_L; /* Address Offset: 0x40038 */ + __IO uint32_t GPIO2D_IOMUX_H; /* Address Offset: 0x4003C */ + __IO uint32_t GPIO3A_IOMUX_L; /* Address Offset: 0x40040 */ + __IO uint32_t GPIO3A_IOMUX_H; /* Address Offset: 0x40044 */ + __IO uint32_t GPIO3B_IOMUX_L; /* Address Offset: 0x40048 */ + __IO uint32_t GPIO3B_IOMUX_H; /* Address Offset: 0x4004C */ + __IO uint32_t GPIO3C_IOMUX_L; /* Address Offset: 0x40050 */ + __IO uint32_t GPIO3C_IOMUX_H; /* Address Offset: 0x40054 */ + __IO uint32_t GPIO3D_IOMUX_L; /* Address Offset: 0x40058 */ + __IO uint32_t GPIO3D_IOMUX_H; /* Address Offset: 0x4005C */ + __IO uint32_t GPIO4A_IOMUX_L; /* Address Offset: 0x40060 */ + __IO uint32_t GPIO4A_IOMUX_H; /* Address Offset: 0x40064 */ + __IO uint32_t GPIO4B_IOMUX_L; /* Address Offset: 0x40068 */ + __IO uint32_t GPIO4B_IOMUX_H; /* Address Offset: 0x4006C */ + __IO uint32_t GPIO4C_IOMUX_L; /* Address Offset: 0x40070 */ + __IO uint32_t GPIO4C_IOMUX_H; /* Address Offset: 0x40074 */ + __IO uint32_t GPIO4D_IOMUX_L; /* Address Offset: 0x40078 */ + __IO uint32_t GPIO4D_IOMUX_H; /* Address Offset: 0x4007C */ + __IO uint32_t GPIO1A_P; /* Address Offset: 0x40080 */ + __IO uint32_t GPIO1B_P; /* Address Offset: 0x40084 */ + __IO uint32_t GPIO1C_P; /* Address Offset: 0x40088 */ + __IO uint32_t GPIO1D_P; /* Address Offset: 0x4008C */ + __IO uint32_t GPIO2A_P; /* Address Offset: 0x40090 */ + __IO uint32_t GPIO2B_P; /* Address Offset: 0x40094 */ + __IO uint32_t GPIO2C_P; /* Address Offset: 0x40098 */ + __IO uint32_t GPIO2D_P; /* Address Offset: 0x4009C */ + __IO uint32_t GPIO3A_P; /* Address Offset: 0x400A0 */ + __IO uint32_t GPIO3B_P; /* Address Offset: 0x400A4 */ + __IO uint32_t GPIO3C_P; /* Address Offset: 0x400A8 */ + __IO uint32_t GPIO3D_P; /* Address Offset: 0x400AC */ + __IO uint32_t GPIO4A_P; /* Address Offset: 0x400B0 */ + __IO uint32_t GPIO4B_P; /* Address Offset: 0x400B4 */ + __IO uint32_t GPIO4C_P; /* Address Offset: 0x400B8 */ + __IO uint32_t GPIO4D_P; /* Address Offset: 0x400BC */ + __IO uint32_t GPIO1A_IE; /* Address Offset: 0x400C0 */ + __IO uint32_t GPIO1B_IE; /* Address Offset: 0x400C4 */ + __IO uint32_t GPIO1C_IE; /* Address Offset: 0x400C8 */ + __IO uint32_t GPIO1D_IE; /* Address Offset: 0x400CC */ + __IO uint32_t GPIO2A_IE; /* Address Offset: 0x400D0 */ + __IO uint32_t GPIO2B_IE; /* Address Offset: 0x400D4 */ + __IO uint32_t GPIO2C_IE; /* Address Offset: 0x400D8 */ + __IO uint32_t GPIO2D_IE; /* Address Offset: 0x400DC */ + __IO uint32_t GPIO3A_IE; /* Address Offset: 0x400E0 */ + __IO uint32_t GPIO3B_IE; /* Address Offset: 0x400E4 */ + __IO uint32_t GPIO3C_IE; /* Address Offset: 0x400E8 */ + __IO uint32_t GPIO3D_IE; /* Address Offset: 0x400EC */ + __IO uint32_t GPIO4A_IE; /* Address Offset: 0x400F0 */ + __IO uint32_t GPIO4B_IE; /* Address Offset: 0x400F4 */ + __IO uint32_t GPIO4C_IE; /* Address Offset: 0x400F8 */ + __IO uint32_t GPIO4D_IE; /* Address Offset: 0x400FC */ + __IO uint32_t GPIO1A_OPD; /* Address Offset: 0x40100 */ + __IO uint32_t GPIO1B_OPD; /* Address Offset: 0x40104 */ + __IO uint32_t GPIO1C_OPD; /* Address Offset: 0x40108 */ + __IO uint32_t GPIO1D_OPD; /* Address Offset: 0x4010C */ + __IO uint32_t GPIO2A_OPD; /* Address Offset: 0x40110 */ + __IO uint32_t GPIO2B_OPD; /* Address Offset: 0x40114 */ + __IO uint32_t GPIO2C_OPD; /* Address Offset: 0x40118 */ + __IO uint32_t GPIO2D_OPD; /* Address Offset: 0x4011C */ + __IO uint32_t GPIO3A_OPD; /* Address Offset: 0x40120 */ + __IO uint32_t GPIO3B_OPD; /* Address Offset: 0x40124 */ + __IO uint32_t GPIO3C_OPD; /* Address Offset: 0x40128 */ + __IO uint32_t GPIO3D_OPD; /* Address Offset: 0x4012C */ + __IO uint32_t GPIO4A_OPD; /* Address Offset: 0x40130 */ + __IO uint32_t GPIO4B_OPD; /* Address Offset: 0x40134 */ + __IO uint32_t GPIO4C_OPD; /* Address Offset: 0x40138 */ + __IO uint32_t GPIO4D_OPD; /* Address Offset: 0x4013C */ + __IO uint32_t GPIO1A_SUS; /* Address Offset: 0x40140 */ + __IO uint32_t GPIO1B_SUS; /* Address Offset: 0x40144 */ + __IO uint32_t GPIO1C_SUS; /* Address Offset: 0x40148 */ + __IO uint32_t GPIO1D_SUS; /* Address Offset: 0x4014C */ + __IO uint32_t GPIO2A_SUS; /* Address Offset: 0x40150 */ + __IO uint32_t GPIO2B_SUS; /* Address Offset: 0x40154 */ + __IO uint32_t GPIO2C_SUS; /* Address Offset: 0x40158 */ + __IO uint32_t GPIO2D_SUS; /* Address Offset: 0x4015C */ + __IO uint32_t GPIO3A_SUS; /* Address Offset: 0x40160 */ + __IO uint32_t GPIO3B_SUS; /* Address Offset: 0x40164 */ + __IO uint32_t GPIO3C_SUS; /* Address Offset: 0x40168 */ + __IO uint32_t GPIO3D_SUS; /* Address Offset: 0x4016C */ + __IO uint32_t GPIO4A_SUS; /* Address Offset: 0x40170 */ + __IO uint32_t GPIO4B_SUS; /* Address Offset: 0x40174 */ + __IO uint32_t GPIO4C_SUS; /* Address Offset: 0x40178 */ + __IO uint32_t GPIO4D_SUS; /* Address Offset: 0x4017C */ + __IO uint32_t GPIO1A_SL; /* Address Offset: 0x40180 */ + __IO uint32_t GPIO1B_SL; /* Address Offset: 0x40184 */ + __IO uint32_t GPIO1C_SL; /* Address Offset: 0x40188 */ + __IO uint32_t GPIO1D_SL; /* Address Offset: 0x4018C */ + __IO uint32_t GPIO2A_SL; /* Address Offset: 0x40190 */ + __IO uint32_t GPIO2B_SL; /* Address Offset: 0x40194 */ + __IO uint32_t GPIO2C_SL; /* Address Offset: 0x40198 */ + __IO uint32_t GPIO2D_SL; /* Address Offset: 0x4019C */ + __IO uint32_t GPIO3A_SL; /* Address Offset: 0x401A0 */ + __IO uint32_t GPIO3B_SL; /* Address Offset: 0x401A4 */ + __IO uint32_t GPIO3C_SL; /* Address Offset: 0x401A8 */ + __IO uint32_t GPIO3D_SL; /* Address Offset: 0x401AC */ + __IO uint32_t GPIO4A_SL; /* Address Offset: 0x401B0 */ + __IO uint32_t GPIO4B_SL; /* Address Offset: 0x401B4 */ + __IO uint32_t GPIO4C_SL; /* Address Offset: 0x401B8 */ + __IO uint32_t GPIO4D_SL; /* Address Offset: 0x401BC */ + uint32_t RESERVED401C0[16]; /* Address Offset: 0x401C0 */ + __IO uint32_t GPIO1A_DS_0; /* Address Offset: 0x40200 */ + __IO uint32_t GPIO1A_DS_1; /* Address Offset: 0x40204 */ + __IO uint32_t GPIO1A_DS_2; /* Address Offset: 0x40208 */ + __IO uint32_t GPIO1A_DS_3; /* Address Offset: 0x4020C */ + __IO uint32_t GPIO1B_DS_0; /* Address Offset: 0x40210 */ + __IO uint32_t GPIO1B_DS_1; /* Address Offset: 0x40214 */ + __IO uint32_t GPIO1B_DS_2; /* Address Offset: 0x40218 */ + __IO uint32_t GPIO1B_DS_3; /* Address Offset: 0x4021C */ + __IO uint32_t GPIO1C_DS_0; /* Address Offset: 0x40220 */ + __IO uint32_t GPIO1C_DS_1; /* Address Offset: 0x40224 */ + __IO uint32_t GPIO1C_DS_2; /* Address Offset: 0x40228 */ + __IO uint32_t GPIO1C_DS_3; /* Address Offset: 0x4022C */ + __IO uint32_t GPIO1D_DS_0; /* Address Offset: 0x40230 */ + __IO uint32_t GPIO1D_DS_1; /* Address Offset: 0x40234 */ + __IO uint32_t GPIO1D_DS_2; /* Address Offset: 0x40238 */ + __IO uint32_t GPIO1D_DS_3; /* Address Offset: 0x4023C */ + __IO uint32_t GPIO2A_DS_0; /* Address Offset: 0x40240 */ + __IO uint32_t GPIO2A_DS_1; /* Address Offset: 0x40244 */ + __IO uint32_t GPIO2A_DS_2; /* Address Offset: 0x40248 */ + __IO uint32_t GPIO2A_DS_3; /* Address Offset: 0x4024C */ + __IO uint32_t GPIO2B_DS_0; /* Address Offset: 0x40250 */ + __IO uint32_t GPIO2B_DS_1; /* Address Offset: 0x40254 */ + __IO uint32_t GPIO2B_DS_2; /* Address Offset: 0x40258 */ + __IO uint32_t GPIO2B_DS_3; /* Address Offset: 0x4025C */ + __IO uint32_t GPIO2C_DS_0; /* Address Offset: 0x40260 */ + __IO uint32_t GPIO2C_DS_1; /* Address Offset: 0x40264 */ + __IO uint32_t GPIO2C_DS_2; /* Address Offset: 0x40268 */ + __IO uint32_t GPIO2C_DS_3; /* Address Offset: 0x4026C */ + __IO uint32_t GPIO2D_DS_0; /* Address Offset: 0x40270 */ + __IO uint32_t GPIO2D_DS_1; /* Address Offset: 0x40274 */ + __IO uint32_t GPIO2D_DS_2; /* Address Offset: 0x40278 */ + __IO uint32_t GPIO2D_DS_3; /* Address Offset: 0x4027C */ + __IO uint32_t GPIO3A_DS_0; /* Address Offset: 0x40280 */ + __IO uint32_t GPIO3A_DS_1; /* Address Offset: 0x40284 */ + __IO uint32_t GPIO3A_DS_2; /* Address Offset: 0x40288 */ + __IO uint32_t GPIO3A_DS_3; /* Address Offset: 0x4028C */ + __IO uint32_t GPIO3B_DS_0; /* Address Offset: 0x40290 */ + __IO uint32_t GPIO3B_DS_1; /* Address Offset: 0x40294 */ + __IO uint32_t GPIO3B_DS_2; /* Address Offset: 0x40298 */ + __IO uint32_t GPIO3B_DS_3; /* Address Offset: 0x4029C */ + __IO uint32_t GPIO3C_DS_0; /* Address Offset: 0x402A0 */ + __IO uint32_t GPIO3C_DS_1; /* Address Offset: 0x402A4 */ + __IO uint32_t GPIO3C_DS_2; /* Address Offset: 0x402A8 */ + __IO uint32_t GPIO3C_DS_3; /* Address Offset: 0x402AC */ + __IO uint32_t GPIO3D_DS_0; /* Address Offset: 0x402B0 */ + __IO uint32_t GPIO3D_DS_1; /* Address Offset: 0x402B4 */ + __IO uint32_t GPIO3D_DS_2; /* Address Offset: 0x402B8 */ + __IO uint32_t GPIO3D_DS_3; /* Address Offset: 0x402BC */ + __IO uint32_t GPIO4A_DS_0; /* Address Offset: 0x402C0 */ + __IO uint32_t GPIO4A_DS_1; /* Address Offset: 0x402C4 */ + __IO uint32_t GPIO4A_DS_2; /* Address Offset: 0x402C8 */ + __IO uint32_t GPIO4A_DS_3; /* Address Offset: 0x402CC */ + __IO uint32_t GPIO4B_DS_0; /* Address Offset: 0x402D0 */ + __IO uint32_t GPIO4B_DS_1; /* Address Offset: 0x402D4 */ + __IO uint32_t GPIO4B_DS_2; /* Address Offset: 0x402D8 */ + __IO uint32_t GPIO4B_DS_3; /* Address Offset: 0x402DC */ + __IO uint32_t GPIO4C_DS_0; /* Address Offset: 0x402E0 */ + __IO uint32_t GPIO4C_DS_1; /* Address Offset: 0x402E4 */ + __IO uint32_t GPIO4C_DS_2; /* Address Offset: 0x402E8 */ + __IO uint32_t GPIO4C_DS_3; /* Address Offset: 0x402EC */ + __IO uint32_t GPIO4D_DS_0; /* Address Offset: 0x402F0 */ + __IO uint32_t GPIO4D_DS_1; /* Address Offset: 0x402F4 */ + __IO uint32_t GPIO4D_DS_2; /* Address Offset: 0x402F8 */ + __IO uint32_t GPIO4D_DS_3; /* Address Offset: 0x402FC */ + __IO uint32_t IOFUNC_SEL0; /* Address Offset: 0x40300 */ + __IO uint32_t IOFUNC_SEL1; /* Address Offset: 0x40304 */ + __IO uint32_t IOFUNC_SEL2; /* Address Offset: 0x40308 */ + __IO uint32_t IOFUNC_SEL3; /* Address Offset: 0x4030C */ + __IO uint32_t IOFUNC_SEL4; /* Address Offset: 0x40310 */ + __IO uint32_t IOFUNC_SEL5; /* Address Offset: 0x40314 */ + uint32_t RESERVED40318[10]; /* Address Offset: 0x40318 */ + __IO uint32_t VI_CON0; /* Address Offset: 0x40340 */ + __IO uint32_t VI_CON1; /* Address Offset: 0x40344 */ + __IO uint32_t VI_STATUS0; /* Address Offset: 0x40348 */ + uint32_t RESERVED4034C[5]; /* Address Offset: 0x4034C */ + __IO uint32_t VO_CON0; /* Address Offset: 0x40360 */ + __IO uint32_t VO_CON1; /* Address Offset: 0x40364 */ + __IO uint32_t VO_CON2; /* Address Offset: 0x40368 */ + uint32_t RESERVED4036C[5]; /* Address Offset: 0x4036C */ + __IO uint32_t MAC0_CON0; /* Address Offset: 0x40380 */ + __IO uint32_t MAC0_CON1; /* Address Offset: 0x40384 */ + __IO uint32_t MAC1_CON0; /* Address Offset: 0x40388 */ + __IO uint32_t MAC1_CON1; /* Address Offset: 0x4038C */ + uint32_t RESERVED40390[4]; /* Address Offset: 0x40390 */ + __IO uint32_t BIU_CON0; /* Address Offset: 0x403A0 */ + __IO uint32_t BIU_CON1; /* Address Offset: 0x403A4 */ + __IO uint32_t BIU_CON2; /* Address Offset: 0x403A8 */ + uint32_t RESERVED403AC[5]; /* Address Offset: 0x403AC */ + __IO uint32_t GIC_CON0; /* Address Offset: 0x403C0 */ + __IO uint32_t GIC_CON1; /* Address Offset: 0x403C4 */ + __IO uint32_t GIC_CON2; /* Address Offset: 0x403C8 */ + uint32_t RESERVED403CC[9]; /* Address Offset: 0x403CC */ + __IO uint32_t GPU_CON0; /* Address Offset: 0x403F0 */ + __IO uint32_t GPU_CON1; /* Address Offset: 0x403F4 */ + uint32_t RESERVED403F8[2]; /* Address Offset: 0x403F8 */ + __IO uint32_t CPU_CON0; /* Address Offset: 0x40400 */ + uint32_t RESERVED40404[7]; /* Address Offset: 0x40404 */ + __IO uint32_t CPU_STATUS0; /* Address Offset: 0x40420 */ + uint32_t RESERVED40424[55]; /* Address Offset: 0x40424 */ + __IO uint32_t SOC_CON10; /* Address Offset: 0x40500 */ + __IO uint32_t SOC_CON11; /* Address Offset: 0x40504 */ + __IO uint32_t SOC_CON12; /* Address Offset: 0x40508 */ + __IO uint32_t SOC_CON13; /* Address Offset: 0x4050C */ + __IO uint32_t SOC_CON14; /* Address Offset: 0x40510 */ + __IO uint32_t SOC_CON15; /* Address Offset: 0x40514 */ + __IO uint32_t SOC_CON16; /* Address Offset: 0x40518 */ + uint32_t RESERVED4051C[25]; /* Address Offset: 0x4051C */ + __IO uint32_t SOC_STATUS0; /* Address Offset: 0x40580 */ + uint32_t RESERVED40584[15]; /* Address Offset: 0x40584 */ + __IO uint32_t RAM_CON; /* Address Offset: 0x405C0 */ + __IO uint32_t CORE_RAM_CON; /* Address Offset: 0x405C4 */ + uint32_t RESERVED405C8[14]; /* Address Offset: 0x405C8 */ + __IO uint32_t TSADC_CON; /* Address Offset: 0x40600 */ + uint32_t RESERVED40604[3]; /* Address Offset: 0x40604 */ + __IO uint32_t SARADC_CON; /* Address Offset: 0x40610 */ + uint32_t RESERVED40614[59]; /* Address Offset: 0x40614 */ + __IO uint32_t GPUPVTPLL_CON0; /* Address Offset: 0x40700 */ + __IO uint32_t GPUPVTPLL_CON1; /* Address Offset: 0x40704 */ + __IO uint32_t GPUPVTPLL_CON2; /* Address Offset: 0x40708 */ + __IO uint32_t GPUPVTPLL_CON3; /* Address Offset: 0x4070C */ + uint32_t RESERVED40710[12]; /* Address Offset: 0x40710 */ + __IO uint32_t NPUPVTPLL_CON0; /* Address Offset: 0x40740 */ + __IO uint32_t NPUPVTPLL_CON1; /* Address Offset: 0x40744 */ + __IO uint32_t NPUPVTPLL_CON2; /* Address Offset: 0x40748 */ + __IO uint32_t NPUPVTPLL_CON3; /* Address Offset: 0x4074C */ + uint32_t RESERVED40750[44]; /* Address Offset: 0x40750 */ + __IO uint32_t CHIP_ID; /* Address Offset: 0x40800 */ + uint32_t RESERVED40804[15]; /* Address Offset: 0x40804 */ + __IO uint32_t GPIO1C5_DS; /* Address Offset: 0x40840 */ + __IO uint32_t GPIO2A2_DS; /* Address Offset: 0x40844 */ + __IO uint32_t GPIO2B0_DS; /* Address Offset: 0x40848 */ + __IO uint32_t GPIO3A0_DS; /* Address Offset: 0x4084C */ + __IO uint32_t GPIO3A6_DS; /* Address Offset: 0x40850 */ + __IO uint32_t GPIO4A0_DS; /* Address Offset: 0x40854 */ + uint32_t RESERVED40858[42]; /* Address Offset: 0x40858 */ + __IO uint32_t DMAC0_CON0; /* Address Offset: 0x40900 */ + __IO uint32_t DMAC0_CON1; /* Address Offset: 0x40904 */ + __IO uint32_t DMAC0_CON2; /* Address Offset: 0x40908 */ + __IO uint32_t DMAC0_CON3; /* Address Offset: 0x4090C */ + __IO uint32_t DMAC0_CON4; /* Address Offset: 0x40910 */ + __IO uint32_t DMAC0_CON5; /* Address Offset: 0x40914 */ + __IO uint32_t DMAC0_CON6; /* Address Offset: 0x40918 */ + __IO uint32_t DMAC0_CON7; /* Address Offset: 0x4091C */ + __IO uint32_t DMAC0_CON8; /* Address Offset: 0x40920 */ + __IO uint32_t DMAC0_CON9; /* Address Offset: 0x40924 */ + uint32_t RESERVED40928[6]; /* Address Offset: 0x40928 */ + __IO uint32_t DMAC1_CON0; /* Address Offset: 0x40940 */ + __IO uint32_t DMAC1_CON1; /* Address Offset: 0x40944 */ + __IO uint32_t DMAC1_CON2; /* Address Offset: 0x40948 */ + __IO uint32_t DMAC1_CON3; /* Address Offset: 0x4094C */ + __IO uint32_t DMAC1_CON4; /* Address Offset: 0x40950 */ + __IO uint32_t DMAC1_CON5; /* Address Offset: 0x40954 */ + __IO uint32_t DMAC1_CON6; /* Address Offset: 0x40958 */ + __IO uint32_t DMAC1_CON7; /* Address Offset: 0x4095C */ + __IO uint32_t DMAC1_CON8; /* Address Offset: 0x40960 */ + __IO uint32_t DMAC1_CON9; /* Address Offset: 0x40964 */ +}; +/* PMUCRU Register Structure Define */ +struct PMUCRU_REG { + __IO uint32_t PPLL_CON[5]; /* Address Offset: 0x0000 */ + uint32_t RESERVED0014[11]; /* Address Offset: 0x0014 */ + __IO uint32_t HPLL_CON[5]; /* Address Offset: 0x0040 */ + uint32_t RESERVED0054[11]; /* Address Offset: 0x0054 */ + __IO uint32_t MODE_CON00; /* Address Offset: 0x0080 */ + uint32_t RESERVED0084[31]; /* Address Offset: 0x0084 */ + __IO uint32_t CRU_CLKSEL_CON[10]; /* Address Offset: 0x0100 */ + uint32_t RESERVED0128[22]; /* Address Offset: 0x0128 */ + __IO uint32_t CRU_CLKGATE_CON[3]; /* Address Offset: 0x0180 */ + uint32_t RESERVED018C[29]; /* Address Offset: 0x018C */ + __IO uint32_t CRU_SOFTRST_CON[1]; /* Address Offset: 0x0200 */ +}; +/* TIMER Register Structure Define */ +struct TIMER_REG { + __IO uint32_t LOAD_COUNT[2]; /* Address Offset: 0x0000 */ + __I uint32_t CURRENT_VALUE[2]; /* Address Offset: 0x0008 */ + __IO uint32_t CONTROLREG; /* Address Offset: 0x0010 */ + uint32_t RESERVED0014; /* Address Offset: 0x0014 */ + __IO uint32_t INTSTATUS; /* Address Offset: 0x0018 */ +}; +/* CRU Register Structure Define */ +struct CRU_REG { + __IO uint32_t APLL_CON[5]; /* Address Offset: 0x0000 */ + uint32_t RESERVED0014[3]; /* Address Offset: 0x0014 */ + __IO uint32_t DPLL_CON[5]; /* Address Offset: 0x0020 */ + uint32_t RESERVED0034[3]; /* Address Offset: 0x0034 */ + __IO uint32_t GPLL_CON[5]; /* Address Offset: 0x0040 */ + uint32_t RESERVED0054[3]; /* Address Offset: 0x0054 */ + __IO uint32_t CPLL_CON[5]; /* Address Offset: 0x0060 */ + uint32_t RESERVED0074[3]; /* Address Offset: 0x0074 */ + __IO uint32_t NPLL_CON[2]; /* Address Offset: 0x0080 */ + uint32_t RESERVED0088[6]; /* Address Offset: 0x0088 */ + __IO uint32_t VPLL_CON[2]; /* Address Offset: 0x00A0 */ + uint32_t RESERVED00A8[6]; /* Address Offset: 0x00A8 */ + __IO uint32_t MODE_CON00; /* Address Offset: 0x00C0 */ + __IO uint32_t MISC_CON[3]; /* Address Offset: 0x00C4 */ + __IO uint32_t GLB_CNT_TH; /* Address Offset: 0x00D0 */ + __IO uint32_t GLB_SRST_FST; /* Address Offset: 0x00D4 */ + __IO uint32_t GLB_SRST_SND; /* Address Offset: 0x00D8 */ + __IO uint32_t GLB_RST_CON; /* Address Offset: 0x00DC */ + __IO uint32_t GLB_RST_ST; /* Address Offset: 0x00E0 */ + uint32_t RESERVED00E4[7]; /* Address Offset: 0x00E4 */ + __IO uint32_t CRU_CLKSEL_CON[85]; /* Address Offset: 0x0100 */ + uint32_t RESERVED0254[43]; /* Address Offset: 0x0254 */ + __IO uint32_t CRU_CLKGATE_CON[36]; /* Address Offset: 0x0300 */ + uint32_t RESERVED0390[28]; /* Address Offset: 0x0390 */ + __IO uint32_t CRU_SOFTRST_CON[30]; /* Address Offset: 0x0400 */ + uint32_t RESERVED0478[2]; /* Address Offset: 0x0478 */ + __IO uint32_t SSGTBL0_3; /* Address Offset: 0x0480 */ + __IO uint32_t SSGTBL4_7; /* Address Offset: 0x0484 */ + __IO uint32_t SSGTBL8_11; /* Address Offset: 0x0488 */ + __IO uint32_t SSGTBL12_15; /* Address Offset: 0x048C */ + __IO uint32_t SSGTBL16_19; /* Address Offset: 0x0490 */ + __IO uint32_t SSGTBL20_23; /* Address Offset: 0x0494 */ + __IO uint32_t SSGTBL24_27; /* Address Offset: 0x0498 */ + __IO uint32_t SSGTBL28_31; /* Address Offset: 0x049C */ + __IO uint32_t SSGTBL32_35; /* Address Offset: 0x04A0 */ + __IO uint32_t SSGTBL36_39; /* Address Offset: 0x04A4 */ + __IO uint32_t SSGTBL40_43; /* Address Offset: 0x04A8 */ + __IO uint32_t SSGTBL44_47; /* Address Offset: 0x04AC */ + __IO uint32_t SSGTBL48_51; /* Address Offset: 0x04B0 */ + __IO uint32_t SSGTBL52_55; /* Address Offset: 0x04B4 */ + __IO uint32_t SSGTBL56_59; /* Address Offset: 0x04B8 */ + __IO uint32_t SSGTBL60_63; /* Address Offset: 0x04BC */ + __IO uint32_t SSGTBL64_67; /* Address Offset: 0x04C0 */ + __IO uint32_t SSGTBL68_71; /* Address Offset: 0x04C4 */ + __IO uint32_t SSGTBL72_75; /* Address Offset: 0x04C8 */ + __IO uint32_t SSGTBL76_79; /* Address Offset: 0x04CC */ + __IO uint32_t SSGTBL80_83; /* Address Offset: 0x04D0 */ + __IO uint32_t SSGTBL84_87; /* Address Offset: 0x04D4 */ + __IO uint32_t SSGTBL88_91; /* Address Offset: 0x04D8 */ + __IO uint32_t SSGTBL92_95; /* Address Offset: 0x04DC */ + __IO uint32_t SSGTBL96_99; /* Address Offset: 0x04E0 */ + __IO uint32_t SSGTBL100_103; /* Address Offset: 0x04E4 */ + __IO uint32_t SSGTBL104_107; /* Address Offset: 0x04E8 */ + __IO uint32_t SSGTBL108_111; /* Address Offset: 0x04EC */ + __IO uint32_t SSGTBL112_115; /* Address Offset: 0x04F0 */ + __IO uint32_t SSGTBL116_119; /* Address Offset: 0x04F4 */ + __IO uint32_t SSGTBL120_123; /* Address Offset: 0x04F8 */ + __IO uint32_t SSGTBL124_127; /* Address Offset: 0x04FC */ + __IO uint32_t AUTOCS_CORE_CON0; /* Address Offset: 0x0500 */ + __IO uint32_t AUTOCS_CORE_CON1; /* Address Offset: 0x0504 */ + __IO uint32_t AUTOCS_GPU_CON0; /* Address Offset: 0x0508 */ + __IO uint32_t AUTOCS_GPU_CON1; /* Address Offset: 0x050C */ + __IO uint32_t AUTOCS_BUS_CON0; /* Address Offset: 0x0510 */ + __IO uint32_t AUTOCS_BUS_CON1; /* Address Offset: 0x0514 */ + __IO uint32_t AUTOCS_TOP_CON0; /* Address Offset: 0x0518 */ + __IO uint32_t AUTOCS_TOP_CON1; /* Address Offset: 0x051C */ + __IO uint32_t AUTOCS_RKVDEC_CON0; /* Address Offset: 0x0520 */ + __IO uint32_t AUTOCS_RKVDEC_CON1; /* Address Offset: 0x0524 */ + __IO uint32_t AUTOCS_RKVENC_CON0; /* Address Offset: 0x0528 */ + __IO uint32_t AUTOCS_RKVENC_CON1; /* Address Offset: 0x052C */ + __IO uint32_t AUTOCS_VPU_CON0; /* Address Offset: 0x0530 */ + __IO uint32_t AUTOCS_VPU_CON1; /* Address Offset: 0x0534 */ + __IO uint32_t AUTOCS_PERI_CON0; /* Address Offset: 0x0538 */ + __IO uint32_t AUTOCS_PERI_CON1; /* Address Offset: 0x053C */ + __IO uint32_t AUTOCS_GPLL_CON0; /* Address Offset: 0x0540 */ + __IO uint32_t AUTOCS_GPLL_CON1; /* Address Offset: 0x0544 */ + __IO uint32_t AUTOCS_CPLL_CON0; /* Address Offset: 0x0548 */ + __IO uint32_t AUTOCS_CPLL_CON1; /* Address Offset: 0x054C */ + uint32_t RESERVED0550[12]; /* Address Offset: 0x0550 */ + __IO uint32_t SDMMC0_CON[2]; /* Address Offset: 0x0580 */ + __IO uint32_t SDMMC1_CON[2]; /* Address Offset: 0x0588 */ + __IO uint32_t SDMMC2_CON[2]; /* Address Offset: 0x0590 */ + __IO uint32_t EMMC_CON[2]; /* Address Offset: 0x0598 */ +}; +/* I2C Register Structure Define */ +struct I2C_REG { + __IO uint32_t CON; /* Address Offset: 0x0000 */ + __IO uint32_t CLKDIV; /* Address Offset: 0x0004 */ + __IO uint32_t MRXADDR; /* Address Offset: 0x0008 */ + __IO uint32_t MRXRADDR; /* Address Offset: 0x000C */ + __IO uint32_t MTXCNT; /* Address Offset: 0x0010 */ + __IO uint32_t MRXCNT; /* Address Offset: 0x0014 */ + __IO uint32_t IEN; /* Address Offset: 0x0018 */ + __IO uint32_t IPD; /* Address Offset: 0x001C */ + __I uint32_t FCNT; /* Address Offset: 0x0020 */ + __IO uint32_t SCL_OE_DB; /* Address Offset: 0x0024 */ + uint32_t RESERVED0028[54]; /* Address Offset: 0x0028 */ + __IO uint32_t TXDATA[8]; /* Address Offset: 0x0100 */ + uint32_t RESERVED0120[56]; /* Address Offset: 0x0120 */ + __I uint32_t RXDATA[8]; /* Address Offset: 0x0200 */ + __I uint32_t ST; /* Address Offset: 0x0220 */ + __IO uint32_t DBGCTRL; /* Address Offset: 0x0224 */ +}; +/* UART Register Structure Define */ +struct UART_REG { + union { + __I uint32_t RBR; /* Address Offset: 0x0000 */ + __IO uint32_t DLL; /* Address Offset: 0x0000 */ + __O uint32_t THR; /* Address Offset: 0x0000 */ + }; + union { + __IO uint32_t DLH; /* Address Offset: 0x0004 */ + __IO uint32_t IER; /* Address Offset: 0x0004 */ + }; + union { + __O uint32_t FCR; /* Address Offset: 0x0008 */ + __I uint32_t IIR; /* Address Offset: 0x0008 */ + }; + __IO uint32_t LCR; /* Address Offset: 0x000C */ + __IO uint32_t MCR; /* Address Offset: 0x0010 */ + __I uint32_t LSR; /* Address Offset: 0x0014 */ + __I uint32_t MSR; /* Address Offset: 0x0018 */ + __IO uint32_t SCR; /* Address Offset: 0x001C */ + uint32_t RESERVED0020[4]; /* Address Offset: 0x0020 */ + union { + __I uint32_t SRBR; /* Address Offset: 0x0030 */ + __O uint32_t STHR; /* Address Offset: 0x0030 */ + }; + uint32_t RESERVED0034[15]; /* Address Offset: 0x0034 */ + __IO uint32_t FAR; /* Address Offset: 0x0070 */ + __I uint32_t TFR; /* Address Offset: 0x0074 */ + __O uint32_t RFW; /* Address Offset: 0x0078 */ + __I uint32_t USR; /* Address Offset: 0x007C */ + __I uint32_t TFL; /* Address Offset: 0x0080 */ + __I uint32_t RFL; /* Address Offset: 0x0084 */ + __O uint32_t SRR; /* Address Offset: 0x0088 */ + __IO uint32_t SRTS; /* Address Offset: 0x008C */ + __IO uint32_t SBCR; /* Address Offset: 0x0090 */ + __IO uint32_t SDMAM; /* Address Offset: 0x0094 */ + __IO uint32_t SFE; /* Address Offset: 0x0098 */ + __IO uint32_t SRT; /* Address Offset: 0x009C */ + __IO uint32_t STET; /* Address Offset: 0x00A0 */ + __IO uint32_t HTX; /* Address Offset: 0x00A4 */ + __O uint32_t DMASA; /* Address Offset: 0x00A8 */ + uint32_t RESERVED00AC[18]; /* Address Offset: 0x00AC */ + __I uint32_t CPR; /* Address Offset: 0x00F4 */ + __I uint32_t UCV; /* Address Offset: 0x00F8 */ + __I uint32_t CTR; /* Address Offset: 0x00FC */ +}; +/* GPIO Register Structure Define */ +struct GPIO_REG { + __IO uint32_t SWPORT_DR_L; /* Address Offset: 0x0000 */ + __IO uint32_t SWPORT_DR_H; /* Address Offset: 0x0004 */ + __IO uint32_t SWPORT_DDR_L; /* Address Offset: 0x0008 */ + __IO uint32_t SWPORT_DDR_H; /* Address Offset: 0x000C */ + __IO uint32_t INT_EN_L; /* Address Offset: 0x0010 */ + __IO uint32_t INT_EN_H; /* Address Offset: 0x0014 */ + __IO uint32_t INT_MASK_L; /* Address Offset: 0x0018 */ + __IO uint32_t INT_MASK_H; /* Address Offset: 0x001C */ + __IO uint32_t INT_TYPE_L; /* Address Offset: 0x0020 */ + __IO uint32_t INT_TYPE_H; /* Address Offset: 0x0024 */ + __IO uint32_t INT_POLARITY_L; /* Address Offset: 0x0028 */ + __IO uint32_t INT_POLARITY_H; /* Address Offset: 0x002C */ + __IO uint32_t INT_BOTHEDGE_L; /* Address Offset: 0x0030 */ + __IO uint32_t INT_BOTHEDGE_H; /* Address Offset: 0x0034 */ + __IO uint32_t DEBOUNCE_L; /* Address Offset: 0x0038 */ + __IO uint32_t DEBOUNCE_H; /* Address Offset: 0x003C */ + __IO uint32_t DBCLK_DIV_EN_L; /* Address Offset: 0x0040 */ + __IO uint32_t DBCLK_DIV_EN_H; /* Address Offset: 0x0044 */ + __IO uint32_t DBCLK_DIV_CON; /* Address Offset: 0x0048 */ + uint32_t RESERVED004C; /* Address Offset: 0x004C */ + __I uint32_t INT_STATUS; /* Address Offset: 0x0050 */ + uint32_t RESERVED0054; /* Address Offset: 0x0054 */ + __I uint32_t INT_RAWSTATUS; /* Address Offset: 0x0058 */ + uint32_t RESERVED005C; /* Address Offset: 0x005C */ + __IO uint32_t PORT_EOI_L; /* Address Offset: 0x0060 */ + __IO uint32_t PORT_EOI_H; /* Address Offset: 0x0064 */ + uint32_t RESERVED0068[2]; /* Address Offset: 0x0068 */ + __I uint32_t EXT_PORT; /* Address Offset: 0x0070 */ + uint32_t RESERVED0074; /* Address Offset: 0x0074 */ + __I uint32_t VER_ID; /* Address Offset: 0x0078 */ +}; +/* PWM Register Structure Define */ +struct PWM_CHANNEL { + __I uint32_t CNT; + __IO uint32_t PERIOD_HPR; + __IO uint32_t DUTY_LPR; + __IO uint32_t CTRL; +}; +struct PWM_REG { + struct PWM_CHANNEL CHANNELS[4]; /* Address Offset: 0x0000 */ + __IO uint32_t INTSTS; /* Address Offset: 0x0040 */ + __IO uint32_t INT_EN; /* Address Offset: 0x0044 */ + uint32_t RESERVED0048[2]; /* Address Offset: 0x0048 */ + __IO uint32_t FIFO_CTRL; /* Address Offset: 0x0050 */ + __IO uint32_t FIFO_INTSTS; /* Address Offset: 0x0054 */ + __IO uint32_t FIFO_TOUTTHR; /* Address Offset: 0x0058 */ + __IO uint32_t VERSION_ID; /* Address Offset: 0x005C */ + __I uint32_t FIFO; /* Address Offset: 0x0060 */ + uint32_t RESERVED0064[7]; /* Address Offset: 0x0064 */ + __IO uint32_t PWRMATCH_CTRL; /* Address Offset: 0x0080 */ + __IO uint32_t PWRMATCH_LPRE; /* Address Offset: 0x0084 */ + __IO uint32_t PWRMATCH_HPRE; /* Address Offset: 0x0088 */ + __IO uint32_t PWRMATCH_LD; /* Address Offset: 0x008C */ + __IO uint32_t PWRMATCH_HD_ZERO; /* Address Offset: 0x0090 */ + __IO uint32_t PWRMATCH_HD_ONE; /* Address Offset: 0x0094 */ + __IO uint32_t PWRMATCH_VALUE[10]; /* Address Offset: 0x0098 */ + uint32_t RESERVED00C0[3]; /* Address Offset: 0x00C0 */ + __I uint32_t PWM3_PWRCAPTURE_VALUE; /* Address Offset: 0x00CC */ + __IO uint32_t FILTER_CTRL; /* Address Offset: 0x00D0 */ +}; +/* PMU Register Structure Define */ +struct PMU_REG { + __I uint32_t VERSION; /* Address Offset: 0x0000 */ + __IO uint32_t PWR_CON; /* Address Offset: 0x0004 */ + __I uint32_t MAIN_PWR_STATE; /* Address Offset: 0x0008 */ + __IO uint32_t INT_MASK_CON; /* Address Offset: 0x000C */ + __IO uint32_t WAKEUP_INT_CON; /* Address Offset: 0x0010 */ + __I uint32_t WAKEUP_INT_ST; /* Address Offset: 0x0014 */ + __IO uint32_t WAKEUP_EDGE_CON; /* Address Offset: 0x0018 */ + __IO uint32_t WAKEUP_EDGE_ST; /* Address Offset: 0x001C */ + uint32_t RESERVED0020[8]; /* Address Offset: 0x0020 */ + __IO uint32_t BUS_IDLE_CON0; /* Address Offset: 0x0040 */ + __IO uint32_t BUS_IDLE_CON1; /* Address Offset: 0x0044 */ + uint32_t RESERVED0048[2]; /* Address Offset: 0x0048 */ + __IO uint32_t BUS_IDLE_SFTCON0; /* Address Offset: 0x0050 */ + __IO uint32_t BUS_IDLE_SFTCON1; /* Address Offset: 0x0054 */ + uint32_t RESERVED0058[2]; /* Address Offset: 0x0058 */ + __I uint32_t BUS_IDLE_ACK; /* Address Offset: 0x0060 */ + uint32_t RESERVED0064; /* Address Offset: 0x0064 */ + __I uint32_t BUS_IDLE_ST; /* Address Offset: 0x0068 */ + uint32_t RESERVED006C; /* Address Offset: 0x006C */ + __IO uint32_t NOC_AUTO_CON0; /* Address Offset: 0x0070 */ + __IO uint32_t NOC_AUTO_CON1; /* Address Offset: 0x0074 */ + uint32_t RESERVED0078[2]; /* Address Offset: 0x0078 */ + __IO uint32_t DDR_PWR_CON; /* Address Offset: 0x0080 */ + __IO uint32_t DDR_PWR_SFTCON; /* Address Offset: 0x0084 */ + __I uint32_t DDR_PWR_STATE; /* Address Offset: 0x0088 */ + __I uint32_t DDR_PWR_ST; /* Address Offset: 0x008C */ + __IO uint32_t PWR_GATE_CON; /* Address Offset: 0x0090 */ + __I uint32_t PWR_GATE_STATE; /* Address Offset: 0x0094 */ + __I uint32_t PWR_DWN_ST; /* Address Offset: 0x0098 */ + uint32_t RESERVED009C; /* Address Offset: 0x009C */ + __IO uint32_t PWR_GATE_SFTCON; /* Address Offset: 0x00A0 */ + uint32_t RESERVED00A4; /* Address Offset: 0x00A4 */ + __IO uint32_t VOL_GATE_SFTCON; /* Address Offset: 0x00A8 */ + uint32_t RESERVED00AC; /* Address Offset: 0x00AC */ + __IO uint32_t CRU_PWR_CON; /* Address Offset: 0x00B0 */ + __IO uint32_t CRU_PWR_SFTCON; /* Address Offset: 0x00B4 */ + __I uint32_t CRU_PWR_STATE; /* Address Offset: 0x00B8 */ + uint32_t RESERVED00BC; /* Address Offset: 0x00BC */ + __IO uint32_t PLLPD_CON; /* Address Offset: 0x00C0 */ + __IO uint32_t PLLPD_SFTCON; /* Address Offset: 0x00C4 */ + uint32_t RESERVED00C8[2]; /* Address Offset: 0x00C8 */ + __IO uint32_t INFO_TX_CON; /* Address Offset: 0x00D0 */ + uint32_t RESERVED00D4[11]; /* Address Offset: 0x00D4 */ + __IO uint32_t DSU_STABLE_CNT; /* Address Offset: 0x0100 */ + __IO uint32_t PMIC_STABLE_CNT; /* Address Offset: 0x0104 */ + __IO uint32_t OSC_STABLE_CNT; /* Address Offset: 0x0108 */ + __IO uint32_t WAKEUP_RSTCLR_CNT; /* Address Offset: 0x010C */ + __IO uint32_t PLL_LOCK_CNT; /* Address Offset: 0x0110 */ + uint32_t RESERVED0114; /* Address Offset: 0x0114 */ + __IO uint32_t DSU_PWRUP_CNT; /* Address Offset: 0x0118 */ + __IO uint32_t DSU_PWRDN_CNT; /* Address Offset: 0x011C */ + __IO uint32_t GPU_VOLUP_CNT; /* Address Offset: 0x0120 */ + __IO uint32_t GPU_VOLDN_CNT; /* Address Offset: 0x0124 */ + __IO uint32_t WAKEUP_TIMEOUT_CNT; /* Address Offset: 0x0128 */ + __IO uint32_t PWM_SWITCH_CNT; /* Address Offset: 0x012C */ + __IO uint32_t DBG_RST_CNT; /* Address Offset: 0x0130 */ + uint32_t RESERVED0134[19]; /* Address Offset: 0x0134 */ + __IO uint32_t SYS_REG0; /* Address Offset: 0x0180 */ + __IO uint32_t SYS_REG1; /* Address Offset: 0x0184 */ + __IO uint32_t SYS_REG2; /* Address Offset: 0x0188 */ + __IO uint32_t SYS_REG3; /* Address Offset: 0x018C */ + __IO uint32_t SYS_REG4; /* Address Offset: 0x0190 */ + __IO uint32_t SYS_REG5; /* Address Offset: 0x0194 */ + __IO uint32_t SYS_REG6; /* Address Offset: 0x0198 */ + __IO uint32_t SYS_REG7; /* Address Offset: 0x019C */ + uint32_t RESERVED01A0[88]; /* Address Offset: 0x01A0 */ + __IO uint32_t DSU_PWR_CON; /* Address Offset: 0x0300 */ + __IO uint32_t DSU_PWR_SFTCON; /* Address Offset: 0x0304 */ + __IO uint32_t DSU_AUTO_CON; /* Address Offset: 0x0308 */ + __I uint32_t DSU_PWR_STATE; /* Address Offset: 0x030C */ + __IO uint32_t CPU_AUTO_PWR_CON0; /* Address Offset: 0x0310 */ + __IO uint32_t CPU_AUTO_PWR_CON1; /* Address Offset: 0x0314 */ + __IO uint32_t CPU_PWR_SFTCON; /* Address Offset: 0x0318 */ + __I uint32_t CLUSTER_PWR_ST; /* Address Offset: 0x031C */ + __IO uint32_t CLUSTER_IDLE_CON; /* Address Offset: 0x0320 */ + __IO uint32_t CLUSTER_IDLE_SFTCON; /* Address Offset: 0x0324 */ + __I uint32_t CLUSTER_IDLE_ACK; /* Address Offset: 0x0328 */ + __I uint32_t CLUSTER_IDLE_ST; /* Address Offset: 0x032C */ + __IO uint32_t DBG_PWR_CON; /* Address Offset: 0x0330 */ +}; +/* SPINLOCK Register Structure Define */ +struct SPINLOCK_REG { + __IO uint32_t STATUS[64]; /* Address Offset: 0x0000 */ +}; +/* GMAC Register Structure Define */ +struct GMAC_REG { + __IO uint32_t MAC_CONFIGURATION; /* Address Offset: 0x0000 */ + __IO uint32_t MAC_EXT_CONFIGURATION; /* Address Offset: 0x0004 */ + __IO uint32_t MAC_PACKET_FILTER; /* Address Offset: 0x0008 */ + __IO uint32_t MAC_WATCHDOG_TIMEOUT; /* Address Offset: 0x000C */ + __IO uint32_t MAC_HASH_TABLE_REG0; /* Address Offset: 0x0010 */ + __IO uint32_t MAC_HASH_TABLE_REG1; /* Address Offset: 0x0014 */ + uint32_t RESERVED0018[14]; /* Address Offset: 0x0018 */ + __IO uint32_t MAC_VLAN_TAG; /* Address Offset: 0x0050 */ + uint32_t RESERVED0054[7]; /* Address Offset: 0x0054 */ + __IO uint32_t MAC_Q0_TX_FLOW_CTRL; /* Address Offset: 0x0070 */ + uint32_t RESERVED0074[7]; /* Address Offset: 0x0074 */ + __IO uint32_t MAC_RX_FLOW_CTRL; /* Address Offset: 0x0090 */ + uint32_t RESERVED0094[7]; /* Address Offset: 0x0094 */ + __I uint32_t MAC_INTERRUPT_STATUS; /* Address Offset: 0x00B0 */ + __IO uint32_t MAC_INTERRUPT_ENABLE; /* Address Offset: 0x00B4 */ + __I uint32_t MAC_RX_TX_STATUS; /* Address Offset: 0x00B8 */ + uint32_t RESERVED00BC; /* Address Offset: 0x00BC */ + __IO uint32_t MAC_PMT_CONTROL_STATUS; /* Address Offset: 0x00C0 */ + __IO uint32_t RWK_FILTER0_BYTE_MASK; /* Address Offset: 0x00C4 */ + __IO uint32_t RWK_FILTER1_BYTE_MASK; /* Address Offset: 0x00C8 */ + union { + __IO uint32_t RWK_FILTER2_BYTE_MASK; /* Address Offset: 0x00CC */ + __IO uint32_t RWK_FILTER3_BYTE_MASK; /* Address Offset: 0x00CC */ + }; + union { + __IO uint32_t RWK_FILTER01_CRC; /* Address Offset: 0x00D0 */ + __IO uint32_t MAC_LPI_CONTROL_STATUS; /* Address Offset: 0x00D0 */ + }; + union { + __IO uint32_t RWK_FILTER23_CRC; /* Address Offset: 0x00D4 */ + __IO uint32_t MAC_LPI_TIMERS_CONTROL; /* Address Offset: 0x00D4 */ + }; + union { + __IO uint32_t RWK_FILTER_OFFSET; /* Address Offset: 0x00D8 */ + __IO uint32_t MAC_LPI_ENTRY_TIMER; /* Address Offset: 0x00D8 */ + }; + union { + __IO uint32_t RWK_FILTER_COMMAND; /* Address Offset: 0x00DC */ + __IO uint32_t MAC_1US_TIC_COUNTER; /* Address Offset: 0x00DC */ + }; + uint32_t RESERVED00E0[6]; /* Address Offset: 0x00E0 */ + __IO uint32_t MAC_PHYIF_CONTROL_STATUS; /* Address Offset: 0x00F8 */ + uint32_t RESERVED00FC[5]; /* Address Offset: 0x00FC */ + __IO uint32_t MAC_VERSION; /* Address Offset: 0x0110 */ + __I uint32_t MAC_DEBUG; /* Address Offset: 0x0114 */ + uint32_t RESERVED0118; /* Address Offset: 0x0118 */ + __I uint32_t MAC_HW_FEATURE0; /* Address Offset: 0x011C */ + __I uint32_t MAC_HW_FEATURE1; /* Address Offset: 0x0120 */ + __I uint32_t MAC_HW_FEATURE2; /* Address Offset: 0x0124 */ + __IO uint32_t MAC_HW_FEATURE3; /* Address Offset: 0x0128 */ + uint32_t RESERVED012C[53]; /* Address Offset: 0x012C */ + __IO uint32_t MAC_MDIO_ADDRESS; /* Address Offset: 0x0200 */ + __IO uint32_t MAC_MDIO_DATA; /* Address Offset: 0x0204 */ + uint32_t RESERVED0208[10]; /* Address Offset: 0x0208 */ + __IO uint32_t MAC_CSR_SW_CTRL; /* Address Offset: 0x0230 */ + uint32_t RESERVED0234[51]; /* Address Offset: 0x0234 */ + __IO uint32_t MAC_ADDRESS0_HIGH; /* Address Offset: 0x0300 */ + __IO uint32_t MAC_ADDRESS0_LOW; /* Address Offset: 0x0304 */ + uint32_t RESERVED0308[254]; /* Address Offset: 0x0308 */ + __IO uint32_t MMC_CONTROL; /* Address Offset: 0x0700 */ + __I uint32_t MMC_RX_INTERRUPT; /* Address Offset: 0x0704 */ + __I uint32_t MMC_TX_INTERRUPT; /* Address Offset: 0x0708 */ + __IO uint32_t MMC_RX_INTERRUPT_MASK; /* Address Offset: 0x070C */ + __IO uint32_t MMC_TX_INTERRUPT_MASK; /* Address Offset: 0x0710 */ + __I uint32_t TX_OCTET_COUNT_GOOD_BAD; /* Address Offset: 0x0714 */ + __I uint32_t TX_PACKET_COUNT_GOOD_BAD; /* Address Offset: 0x0718 */ + uint32_t RESERVED071C[11]; /* Address Offset: 0x071C */ + __I uint32_t TX_UNDERFLOW_ERROR_PACKETS; /* Address Offset: 0x0748 */ + uint32_t RESERVED074C[5]; /* Address Offset: 0x074C */ + __I uint32_t TX_CARRIER_ERROR_PACKETS; /* Address Offset: 0x0760 */ + __I uint32_t TX_OCTET_COUNT_GOOD; /* Address Offset: 0x0764 */ + __I uint32_t TX_PACKET_COUNT_GOOD; /* Address Offset: 0x0768 */ + uint32_t RESERVED076C[5]; /* Address Offset: 0x076C */ + __I uint32_t RX_PACKETS_COUNT_GOOD_BAD; /* Address Offset: 0x0780 */ + __I uint32_t RX_OCTET_COUNT_GOOD_BAD; /* Address Offset: 0x0784 */ + __I uint32_t RX_OCTET_COUNT_GOOD; /* Address Offset: 0x0788 */ + uint32_t RESERVED078C; /* Address Offset: 0x078C */ + __I uint32_t RX_MULTICAST_PACKETS_GOOD; /* Address Offset: 0x0790 */ + __I uint32_t RX_CRC_ERROR_PACKETS; /* Address Offset: 0x0794 */ + uint32_t RESERVED0798[12]; /* Address Offset: 0x0798 */ + __I uint32_t RX_LENGTH_ERROR_PACKETS; /* Address Offset: 0x07C8 */ + uint32_t RESERVED07CC[2]; /* Address Offset: 0x07CC */ + __I uint32_t RX_FIFO_OVERFLOW_PACKETS; /* Address Offset: 0x07D4 */ + uint32_t RESERVED07D8[10]; /* Address Offset: 0x07D8 */ + __IO uint32_t MMC_IPC_RX_INTERRUPT_MASK; /* Address Offset: 0x0800 */ + uint32_t RESERVED0804; /* Address Offset: 0x0804 */ + __I uint32_t MMC_IPC_RX_INTERRUPT; /* Address Offset: 0x0808 */ + uint32_t RESERVED080C; /* Address Offset: 0x080C */ + __I uint32_t RXIPV4_GOOD_PACKETS; /* Address Offset: 0x0810 */ + __I uint32_t RXIPV4_HEADER_ERROR_PACKETS; /* Address Offset: 0x0814 */ + uint32_t RESERVED0818[3]; /* Address Offset: 0x0818 */ + __I uint32_t RXIPV6_GOOD_PACKETS; /* Address Offset: 0x0824 */ + __I uint32_t RXIPV6_HEADER_ERROR_PACKETS; /* Address Offset: 0x0828 */ + uint32_t RESERVED082C[2]; /* Address Offset: 0x082C */ + __I uint32_t RXUDP_ERROR_PACKETS; /* Address Offset: 0x0834 */ + uint32_t RESERVED0838; /* Address Offset: 0x0838 */ + __I uint32_t RXTCP_ERROR_PACKETS; /* Address Offset: 0x083C */ + uint32_t RESERVED0840; /* Address Offset: 0x0840 */ + __I uint32_t RXICMP_ERROR_PACKETS; /* Address Offset: 0x0844 */ + uint32_t RESERVED0848[3]; /* Address Offset: 0x0848 */ + __I uint32_t RXIPV4_HEADER_ERROR_OCTETS; /* Address Offset: 0x0854 */ + uint32_t RESERVED0858[4]; /* Address Offset: 0x0858 */ + __I uint32_t RXIPV6_HEADER_ERROR_OCTETS; /* Address Offset: 0x0868 */ + uint32_t RESERVED086C[2]; /* Address Offset: 0x086C */ + __I uint32_t RXUDP_ERROR_OCTETS; /* Address Offset: 0x0874 */ + uint32_t RESERVED0878; /* Address Offset: 0x0878 */ + __I uint32_t RXTCP_ERROR_OCTETS; /* Address Offset: 0x087C */ + uint32_t RESERVED0880; /* Address Offset: 0x0880 */ + __I uint32_t RXICMP_ERROR_OCTETS; /* Address Offset: 0x0884 */ + uint32_t RESERVED0888[158]; /* Address Offset: 0x0888 */ + __IO uint32_t MAC_TIMESTAMP_CONTROL; /* Address Offset: 0x0B00 */ + __IO uint32_t MAC_SUB_SECOND_INCREMENT; /* Address Offset: 0x0B04 */ + __IO uint32_t MAC_SYSTEM_TIME_SECS; /* Address Offset: 0x0B08 */ + __IO uint32_t MAC_SYSTEM_TIME_NS; /* Address Offset: 0x0B0C */ + __IO uint32_t MAC_SYS_TIME_SECS_UPDATE; /* Address Offset: 0x0B10 */ + __IO uint32_t MAC_SYS_TIME_NS_UPDATE; /* Address Offset: 0x0B14 */ + __IO uint32_t MAC_TIMESTAMP_ADDEND; /* Address Offset: 0x0B18 */ + uint32_t RESERVED0B1C; /* Address Offset: 0x0B1C */ + __I uint32_t MAC_TIMESTAMP_STATUS; /* Address Offset: 0x0B20 */ + uint32_t RESERVED0B24[3]; /* Address Offset: 0x0B24 */ + __I uint32_t MAC_TX_TS_STATUS_NS; /* Address Offset: 0x0B30 */ + __I uint32_t MAC_TX_TS_STATUS_SECS; /* Address Offset: 0x0B34 */ + uint32_t RESERVED0B38[2]; /* Address Offset: 0x0B38 */ + __IO uint32_t MAC_AUXILIARY_CONTROL; /* Address Offset: 0x0B40 */ + uint32_t RESERVED0B44; /* Address Offset: 0x0B44 */ + __I uint32_t MAC_AUXILIARY_TS_NS; /* Address Offset: 0x0B48 */ + __IO uint32_t MAC_AUXILIARY_TS_SECS; /* Address Offset: 0x0B4C */ + uint32_t RESERVED0B50[2]; /* Address Offset: 0x0B50 */ + __IO uint32_t MAC_TS_INGRESS_CORR_NS; /* Address Offset: 0x0B58 */ + __IO uint32_t MAC_TS_EGRESS_CORR_NS; /* Address Offset: 0x0B5C */ + uint32_t RESERVED0B60[2]; /* Address Offset: 0x0B60 */ + __I uint32_t MAC_TS_INGRESS_LATENCY; /* Address Offset: 0x0B68 */ + __I uint32_t MAC_TS_EGRESS_LATENCY; /* Address Offset: 0x0B6C */ + __IO uint32_t MAC_PPS_CONTROL; /* Address Offset: 0x0B70 */ + uint32_t RESERVED0B74[37]; /* Address Offset: 0x0B74 */ + __IO uint32_t MTL_DBG_CTL; /* Address Offset: 0x0C08 */ + __IO uint32_t MTL_DBG_STS; /* Address Offset: 0x0C0C */ + __IO uint32_t MTL_FIFO_DEBUG_DATA; /* Address Offset: 0x0C10 */ + uint32_t RESERVED0C14[3]; /* Address Offset: 0x0C14 */ + __I uint32_t MTL_INTERRUPT_STATUS; /* Address Offset: 0x0C20 */ + uint32_t RESERVED0C24[55]; /* Address Offset: 0x0C24 */ + __IO uint32_t MTL_TXQ0_OPERATION_MODE; /* Address Offset: 0x0D00 */ + __I uint32_t MTL_TXQ0_UNDERFLOW; /* Address Offset: 0x0D04 */ + __I uint32_t MTL_TXQ0_DEBUG; /* Address Offset: 0x0D08 */ + uint32_t RESERVED0D0C[8]; /* Address Offset: 0x0D0C */ + __IO uint32_t MTL_Q0_INTERRUPT_CTRL_STATUS; /* Address Offset: 0x0D2C */ + __IO uint32_t MTL_RXQ0_OPERATION_MODE; /* Address Offset: 0x0D30 */ + __I uint32_t MTL_RXQ0_MISS_PKT_OVF_CNT; /* Address Offset: 0x0D34 */ + __I uint32_t MTL_RXQ0_DEBUG; /* Address Offset: 0x0D38 */ + uint32_t RESERVED0D3C[177]; /* Address Offset: 0x0D3C */ + __IO uint32_t DMA_MODE; /* Address Offset: 0x1000 */ + __IO uint32_t DMA_SYSBUS_MODE; /* Address Offset: 0x1004 */ + __I uint32_t DMA_INTERRUPT_STATUS; /* Address Offset: 0x1008 */ + __I uint32_t DMA_DEBUG_STATUS0; /* Address Offset: 0x100C */ + uint32_t RESERVED1010[12]; /* Address Offset: 0x1010 */ + __IO uint32_t AXI_LPI_ENTRY_INTERVAL; /* Address Offset: 0x1040 */ + uint32_t RESERVED1044[47]; /* Address Offset: 0x1044 */ + __IO uint32_t DMA_CH0_CONTROL; /* Address Offset: 0x1100 */ + __IO uint32_t DMA_CH0_TX_CONTROL; /* Address Offset: 0x1104 */ + __IO uint32_t DMA_CH0_RX_CONTROL; /* Address Offset: 0x1108 */ + uint32_t RESERVED110C[2]; /* Address Offset: 0x110C */ + __IO uint32_t DMA_CH0_TXDESC_LIST_ADDRESS; /* Address Offset: 0x1114 */ + uint32_t RESERVED1118; /* Address Offset: 0x1118 */ + __IO uint32_t DMA_CH0_RXDESC_LIST_ADDRESS; /* Address Offset: 0x111C */ + __IO uint32_t DMA_CH0_TXDESC_TAIL_POINTER; /* Address Offset: 0x1120 */ + uint32_t RESERVED1124; /* Address Offset: 0x1124 */ + __IO uint32_t DMA_CH0_RXDESC_TAIL_POINTER; /* Address Offset: 0x1128 */ + __IO uint32_t DMA_CH0_TXDESC_RING_LENGTH; /* Address Offset: 0x112C */ + __IO uint32_t DMA_CH0_RXDESC_RING_LENGTH; /* Address Offset: 0x1130 */ + __IO uint32_t DMA_CH0_INTERRUPT_ENABLE; /* Address Offset: 0x1134 */ + __IO uint32_t DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER; /* Address Offset: 0x1138 */ + uint32_t RESERVED113C[2]; /* Address Offset: 0x113C */ + __I uint32_t DMA_CH0_CURRENT_APP_TXDESC; /* Address Offset: 0x1144 */ + uint32_t RESERVED1148; /* Address Offset: 0x1148 */ + __I uint32_t DMA_CH0_CURRENT_APP_RXDESC; /* Address Offset: 0x114C */ + uint32_t RESERVED1150; /* Address Offset: 0x1150 */ + __I uint32_t DMA_CH0_CURRENT_APP_TXBUFFER; /* Address Offset: 0x1154 */ + uint32_t RESERVED1158; /* Address Offset: 0x1158 */ + __I uint32_t DMA_CH0_CURRENT_APP_RXBUFFER; /* Address Offset: 0x115C */ + __IO uint32_t DMA_CH0_STATUS; /* Address Offset: 0x1160 */ + __I uint32_t DMA_CH0_MISS_FRAME_CNT; /* Address Offset: 0x1164 */ + __I uint32_t DMA_CH0_RX_ERI_CNT; /* Address Offset: 0x1168 */ +}; +/* MMC Register Structure Define */ +struct MMC_REG { + __IO uint32_t CTRL; /* Address Offset: 0x0000 */ + __IO uint32_t PWREN; /* Address Offset: 0x0004 */ + __IO uint32_t CLKDIV; /* Address Offset: 0x0008 */ + __IO uint32_t CLKSRC; /* Address Offset: 0x000C */ + __IO uint32_t CLKENA; /* Address Offset: 0x0010 */ + __IO uint32_t TMOUT; /* Address Offset: 0x0014 */ + __IO uint32_t CTYPE; /* Address Offset: 0x0018 */ + __IO uint32_t BLKSIZ; /* Address Offset: 0x001C */ + __IO uint32_t BYTCNT; /* Address Offset: 0x0020 */ + __IO uint32_t INTMASK; /* Address Offset: 0x0024 */ + __IO uint32_t CMDARG; /* Address Offset: 0x0028 */ + __IO uint32_t CMD; /* Address Offset: 0x002C */ + __I uint32_t RESP0; /* Address Offset: 0x0030 */ + __I uint32_t RESP1; /* Address Offset: 0x0034 */ + __I uint32_t RESP2; /* Address Offset: 0x0038 */ + __I uint32_t RESP3; /* Address Offset: 0x003C */ + __IO uint32_t MINTSTS; /* Address Offset: 0x0040 */ + __IO uint32_t RINTSTS; /* Address Offset: 0x0044 */ + __I uint32_t STATUS; /* Address Offset: 0x0048 */ + __IO uint32_t FIFOTH; /* Address Offset: 0x004C */ + __I uint32_t CDETECT; /* Address Offset: 0x0050 */ + __IO uint32_t WRTPRT; /* Address Offset: 0x0054 */ + uint32_t RESERVED0058; /* Address Offset: 0x0058 */ + __I uint32_t TCBCNT; /* Address Offset: 0x005C */ + __I uint32_t TBBCNT; /* Address Offset: 0x0060 */ + __IO uint32_t DEBNCE; /* Address Offset: 0x0064 */ + __IO uint32_t USRID; /* Address Offset: 0x0068 */ + __I uint32_t VERID; /* Address Offset: 0x006C */ + __I uint32_t HCON; /* Address Offset: 0x0070 */ + __IO uint32_t UHSREG; /* Address Offset: 0x0074 */ + __IO uint32_t RSTN; /* Address Offset: 0x0078 */ + uint32_t RESERVED007C; /* Address Offset: 0x007C */ + __IO uint32_t BMOD; /* Address Offset: 0x0080 */ + __O uint32_t PLDMND; /* Address Offset: 0x0084 */ + __IO uint32_t DBADDR; /* Address Offset: 0x0088 */ + __IO uint32_t IDSTS; /* Address Offset: 0x008C */ + __IO uint32_t IDINTEN; /* Address Offset: 0x0090 */ + __IO uint32_t DSCADDR; /* Address Offset: 0x0094 */ + __IO uint32_t BUFADDR; /* Address Offset: 0x0098 */ + uint32_t RESERVED009C[25]; /* Address Offset: 0x009C */ + __IO uint32_t CARDTHRCTL; /* Address Offset: 0x0100 */ + __IO uint32_t BACKEND_POWER; /* Address Offset: 0x0104 */ + uint32_t RESERVED0108; /* Address Offset: 0x0108 */ + __IO uint32_t EMMCDDR_REG; /* Address Offset: 0x010C */ + uint32_t RESERVED0110[4]; /* Address Offset: 0x0110 */ + __IO uint32_t RDYINT_GEN; /* Address Offset: 0x0120 */ + uint32_t RESERVED0124[55]; /* Address Offset: 0x0124 */ + __IO uint32_t FIFO_BASE; /* Address Offset: 0x0200 */ +}; +/* FSPI Register Structure Define */ +struct FSPI_REG { + __IO uint32_t CTRL0; /* Address Offset: 0x0000 */ + __IO uint32_t IMR; /* Address Offset: 0x0004 */ + __IO uint32_t ICLR; /* Address Offset: 0x0008 */ + __IO uint32_t FTLR; /* Address Offset: 0x000C */ + __IO uint32_t RCVR; /* Address Offset: 0x0010 */ + __IO uint32_t AX0; /* Address Offset: 0x0014 */ + __IO uint32_t ABIT0; /* Address Offset: 0x0018 */ + __IO uint32_t ISR; /* Address Offset: 0x001C */ + __IO uint32_t FSR; /* Address Offset: 0x0020 */ + __I uint32_t SR; /* Address Offset: 0x0024 */ + __I uint32_t RISR; /* Address Offset: 0x0028 */ + __I uint32_t VER; /* Address Offset: 0x002C */ + __IO uint32_t QOP; /* Address Offset: 0x0030 */ + __IO uint32_t EXT_CTRL; /* Address Offset: 0x0034 */ + uint32_t RESERVED0038; /* Address Offset: 0x0038 */ + __IO uint32_t DLL_CTRL0; /* Address Offset: 0x003C */ + uint32_t RESERVED0040; /* Address Offset: 0x0040 */ + __IO uint32_t EXT_AX; /* Address Offset: 0x0044 */ + __IO uint32_t SCLK_INATM_CNT; /* Address Offset: 0x0048 */ + uint32_t RESERVED004C; /* Address Offset: 0x004C */ + __O uint32_t XMMC_WCMD0; /* Address Offset: 0x0050 */ + __O uint32_t XMMC_RCMD0; /* Address Offset: 0x0054 */ + __IO uint32_t XMMC_CTRL; /* Address Offset: 0x0058 */ + __IO uint32_t MODE; /* Address Offset: 0x005C */ + __IO uint32_t DEVRGN; /* Address Offset: 0x0060 */ + __IO uint32_t DEVSIZE0; /* Address Offset: 0x0064 */ + __IO uint32_t TME0; /* Address Offset: 0x0068 */ + uint32_t RESERVED006C; /* Address Offset: 0x006C */ + __IO uint32_t XMMC_RX_WTMRK; /* Address Offset: 0x0070 */ + uint32_t RESERVED0074[3]; /* Address Offset: 0x0074 */ + __IO uint32_t DMATR; /* Address Offset: 0x0080 */ + __IO uint32_t DMAADDR; /* Address Offset: 0x0084 */ + __IO uint32_t LEN_CTRL; /* Address Offset: 0x0088 */ + __IO uint32_t LEN_EXT; /* Address Offset: 0x008C */ + uint32_t RESERVED0090; /* Address Offset: 0x0090 */ + __IO uint32_t XMMCSR; /* Address Offset: 0x0094 */ + uint32_t RESERVED0098[26]; /* Address Offset: 0x0098 */ + __O uint32_t CMD; /* Address Offset: 0x0100 */ + __O uint32_t ADDR; /* Address Offset: 0x0104 */ + __IO uint32_t DATA; /* Address Offset: 0x0108 */ + uint32_t RESERVED010C[61]; /* Address Offset: 0x010C */ + __IO uint32_t CTRL1; /* Address Offset: 0x0200 */ + uint32_t RESERVED0204[4]; /* Address Offset: 0x0204 */ + __IO uint32_t AX1; /* Address Offset: 0x0214 */ + __IO uint32_t ABIT1; /* Address Offset: 0x0218 */ + uint32_t RESERVED021C[8]; /* Address Offset: 0x021C */ + __IO uint32_t DLL_CTRL1; /* Address Offset: 0x023C */ + uint32_t RESERVED0240[4]; /* Address Offset: 0x0240 */ + __O uint32_t XMMC_WCMD1; /* Address Offset: 0x0250 */ + __O uint32_t XMMC_RCMD1; /* Address Offset: 0x0254 */ + uint32_t RESERVED0258[3]; /* Address Offset: 0x0258 */ + __IO uint32_t DEVSIZE1; /* Address Offset: 0x0264 */ + __IO uint32_t TME1; /* Address Offset: 0x0268 */ +}; +/* DMA Register Structure Define */ +struct DMA_CHANNEL_STATUS { + __I uint32_t CSR; + __I uint32_t CPC; +}; +struct DMA_CHANNEL_CONFIG { + __I uint32_t SAR; + __I uint32_t DAR; + __I uint32_t CCR; + __I uint32_t LC0; + __I uint32_t LC1; + __I uint32_t PADDING[3]; +}; +struct DMA_REG { + __I uint32_t DSR; /* Address Offset: 0x0000 */ + __I uint32_t DPC; /* Address Offset: 0x0004 */ + uint32_t RESERVED0008[6]; /* Address Offset: 0x0008 */ + __IO uint32_t INTEN; /* Address Offset: 0x0020 */ + __I uint32_t EVENT_RIS; /* Address Offset: 0x0024 */ + __I uint32_t INTMIS; /* Address Offset: 0x0028 */ + __O uint32_t INTCLR; /* Address Offset: 0x002C */ + __I uint32_t FSRD; /* Address Offset: 0x0030 */ + __I uint32_t FSRC; /* Address Offset: 0x0034 */ + __IO uint32_t FTRD; /* Address Offset: 0x0038 */ + uint32_t RESERVED003C; /* Address Offset: 0x003C */ + __I uint32_t FTR[6]; /* Address Offset: 0x0040 */ + uint32_t RESERVED0058[42]; /* Address Offset: 0x0058 */ + struct DMA_CHANNEL_STATUS CHAN_STS[8]; /* Address Offset: 0x0100 */ + uint32_t RESERVED0140[176]; /* Address Offset: 0x0140 */ + struct DMA_CHANNEL_CONFIG CHAN_CFG[8]; /* Address Offset: 0x0400 */ + uint32_t RESERVED0500[512]; /* Address Offset: 0x0500 */ + __I uint32_t DBGSTATUS; /* Address Offset: 0x0D00 */ + __O uint32_t DBGCMD; /* Address Offset: 0x0D04 */ + __O uint32_t DBGINST[2]; /* Address Offset: 0x0D08 */ + uint32_t RESERVED0D10[60]; /* Address Offset: 0x0D10 */ + __I uint32_t CR[5]; /* Address Offset: 0x0E00 */ + __I uint32_t CRDN; /* Address Offset: 0x0E14 */ + uint32_t RESERVED0E18[26]; /* Address Offset: 0x0E18 */ + __IO uint32_t WD; /* Address Offset: 0x0E80 */ +}; +/* CAN Register Structure Define */ +struct CAN_REG { + __IO uint32_t MODE; /* Address Offset: 0x0000 */ + __IO uint32_t CMD; /* Address Offset: 0x0004 */ + __I uint32_t STATE; /* Address Offset: 0x0008 */ + __IO uint32_t INT; /* Address Offset: 0x000C */ + __IO uint32_t INT_MASK; /* Address Offset: 0x0010 */ + __IO uint32_t DMA_CTRL; /* Address Offset: 0x0014 */ + __IO uint32_t BITTIMING; /* Address Offset: 0x0018 */ + uint32_t RESERVED001C[3]; /* Address Offset: 0x001C */ + __I uint32_t ARBITFAIL; /* Address Offset: 0x0028 */ + __IO uint32_t ERROR_CODE; /* Address Offset: 0x002C */ + uint32_t RESERVED0030; /* Address Offset: 0x0030 */ + __I uint32_t RXERRORCNT; /* Address Offset: 0x0034 */ + __I uint32_t TXERRORCNT; /* Address Offset: 0x0038 */ + __IO uint32_t IDCODE; /* Address Offset: 0x003C */ + __IO uint32_t IDMASK; /* Address Offset: 0x0040 */ + uint32_t RESERVED0044[3]; /* Address Offset: 0x0044 */ + __IO uint32_t TXFRAMEINFO; /* Address Offset: 0x0050 */ + __IO uint32_t TXID; /* Address Offset: 0x0054 */ + __IO uint32_t TXDATA0; /* Address Offset: 0x0058 */ + __IO uint32_t TXDATA1; /* Address Offset: 0x005C */ + __I uint32_t RXFRAMEINFO; /* Address Offset: 0x0060 */ + __I uint32_t RXID; /* Address Offset: 0x0064 */ + __I uint32_t RXDATA0; /* Address Offset: 0x0068 */ + __I uint32_t RXDATA1; /* Address Offset: 0x006C */ + __I uint32_t RTL_VERSION; /* Address Offset: 0x0070 */ + uint32_t RESERVED0074[35]; /* Address Offset: 0x0074 */ + __IO uint32_t FD_NOMINAL_BITTIMING; /* Address Offset: 0x0100 */ + __IO uint32_t FD_DATA_BITTIMING; /* Address Offset: 0x0104 */ + __IO uint32_t TRANSMIT_DELAY_COMPENSATION; /* Address Offset: 0x0108 */ + __IO uint32_t TIMESTAMP_CTRL; /* Address Offset: 0x010C */ + __IO uint32_t TIMESTAMP; /* Address Offset: 0x0110 */ + __IO uint32_t TXEVENT_FIFO_CTRL; /* Address Offset: 0x0114 */ + __IO uint32_t RX_FIFO_CTRL; /* Address Offset: 0x0118 */ + __IO uint32_t AFR_CTRL; /* Address Offset: 0x011C */ + __IO uint32_t IDCODE0; /* Address Offset: 0x0120 */ + __IO uint32_t IDMASK0; /* Address Offset: 0x0124 */ + __IO uint32_t IDCODE1; /* Address Offset: 0x0128 */ + __IO uint32_t IDMASK1; /* Address Offset: 0x012C */ + __IO uint32_t IDCODE2; /* Address Offset: 0x0130 */ + __IO uint32_t IDMASK2; /* Address Offset: 0x0134 */ + __IO uint32_t IDCODE3; /* Address Offset: 0x0138 */ + __IO uint32_t IDMASK3; /* Address Offset: 0x013C */ + __IO uint32_t IDCODE4; /* Address Offset: 0x0140 */ + __IO uint32_t IDMASK4; /* Address Offset: 0x0144 */ + uint32_t RESERVED0148[46]; /* Address Offset: 0x0148 */ + __IO uint32_t FD_TXFRAMEINFO; /* Address Offset: 0x0200 */ + __IO uint32_t FD_TXID; /* Address Offset: 0x0204 */ + __IO uint32_t FD_TXDATA[16]; /* Address Offset: 0x0208 */ + uint32_t RESERVED0248[46]; /* Address Offset: 0x0248 */ + __IO uint32_t FD_RXFRAMEINFO; /* Address Offset: 0x0300 */ + __I uint32_t FD_RXID; /* Address Offset: 0x0304 */ + __I uint32_t FD_RXTIMESTAMP; /* Address Offset: 0x0308 */ + __IO uint32_t FD_RXDATA[16]; /* Address Offset: 0x030C */ + uint32_t RESERVED034C[45]; /* Address Offset: 0x034C */ + __I uint32_t RX_FIFO_RDATA; /* Address Offset: 0x0400 */ + uint32_t RESERVED0404[63]; /* Address Offset: 0x0404 */ + __I uint32_t TXE_FIFO_RDATA; /* Address Offset: 0x0500 */ +}; +/* WDT Register Structure Define */ +struct WDT_REG { + __IO uint32_t CR; /* Address Offset: 0x0000 */ + __IO uint32_t TORR; /* Address Offset: 0x0004 */ + __I uint32_t CCVR; /* Address Offset: 0x0008 */ + __O uint32_t CRR; /* Address Offset: 0x000C */ + __I uint32_t STAT; /* Address Offset: 0x0010 */ + __I uint32_t EOI; /* Address Offset: 0x0014 */ +}; +/* SPI Register Structure Define */ +struct SPI_REG { + __IO uint32_t CTRLR[2]; /* Address Offset: 0x0000 */ + __IO uint32_t ENR; /* Address Offset: 0x0008 */ + __IO uint32_t SER; /* Address Offset: 0x000C */ + __IO uint32_t BAUDR; /* Address Offset: 0x0010 */ + __IO uint32_t TXFTLR; /* Address Offset: 0x0014 */ + __IO uint32_t RXFTLR; /* Address Offset: 0x0018 */ + __I uint32_t TXFLR; /* Address Offset: 0x001C */ + __I uint32_t RXFLR; /* Address Offset: 0x0020 */ + __I uint32_t SR; /* Address Offset: 0x0024 */ + __IO uint32_t IPR; /* Address Offset: 0x0028 */ + __IO uint32_t IMR; /* Address Offset: 0x002C */ + __IO uint32_t ISR; /* Address Offset: 0x0030 */ + __IO uint32_t RISR; /* Address Offset: 0x0034 */ + __O uint32_t ICR; /* Address Offset: 0x0038 */ + __IO uint32_t DMACR; /* Address Offset: 0x003C */ + __IO uint32_t DMATDLR; /* Address Offset: 0x0040 */ + __IO uint32_t DMARDLR; /* Address Offset: 0x0044 */ + uint32_t RESERVED0048; /* Address Offset: 0x0048 */ + __IO uint32_t TIMEOUT; /* Address Offset: 0x004C */ + __IO uint32_t BYPASS; /* Address Offset: 0x0050 */ + uint32_t RESERVED0054[235]; /* Address Offset: 0x0054 */ + __O uint32_t TXDR; /* Address Offset: 0x0400 */ + uint32_t RESERVED0404[255]; /* Address Offset: 0x0404 */ + __I uint32_t RXDR; /* Address Offset: 0x0800 */ +}; +/* TSADC Register Structure Define */ +struct TSADC_REG { + __IO uint32_t USER_CON; /* Address Offset: 0x0000 */ + __IO uint32_t AUTO_CON; /* Address Offset: 0x0004 */ + __IO uint32_t INT_EN; /* Address Offset: 0x0008 */ + __IO uint32_t INT_PD; /* Address Offset: 0x000C */ + uint32_t RESERVED0010[4]; /* Address Offset: 0x0010 */ + __I uint32_t DATA[2]; /* Address Offset: 0x0020 */ + uint32_t RESERVED0028[2]; /* Address Offset: 0x0028 */ + __IO uint32_t COMP_INT[2]; /* Address Offset: 0x0030 */ + uint32_t RESERVED0038[2]; /* Address Offset: 0x0038 */ + __IO uint32_t COMP_SHUT[2]; /* Address Offset: 0x0040 */ + uint32_t RESERVED0048[6]; /* Address Offset: 0x0048 */ + __IO uint32_t HIGHT_INT_DEBOUNCE; /* Address Offset: 0x0060 */ + __IO uint32_t HIGHT_TSHUT_DEBOUNCE; /* Address Offset: 0x0064 */ + __IO uint32_t AUTO_PERIOD; /* Address Offset: 0x0068 */ + __IO uint32_t AUTO_PERIOD_HT; /* Address Offset: 0x006C */ + uint32_t RESERVED0070[4]; /* Address Offset: 0x0070 */ + __IO uint32_t COMP_LOW_INT[2]; /* Address Offset: 0x0080 */ +}; +/* SARADC Register Structure Define */ +struct SARADC_REG { + __I uint32_t DATA; /* Address Offset: 0x0000 */ + __I uint32_t STAS; /* Address Offset: 0x0004 */ + __IO uint32_t CTRL; /* Address Offset: 0x0008 */ + __IO uint32_t DLY_PU_SOC; /* Address Offset: 0x000C */ +}; +/* MBOX Register Structure Define */ +struct MBOX_CMD_DAT { + __IO uint32_t CMD; + __IO uint32_t DATA; +}; +struct MBOX_REG { + __IO uint32_t A2B_INTEN; /* Address Offset: 0x0000 */ + __IO uint32_t A2B_STATUS; /* Address Offset: 0x0004 */ + struct MBOX_CMD_DAT A2B[4]; /* Address Offset: 0x0008 */ + __IO uint32_t B2A_INTEN; /* Address Offset: 0x0028 */ + __IO uint32_t B2A_STATUS; /* Address Offset: 0x002C */ + struct MBOX_CMD_DAT B2A[4]; /* Address Offset: 0x0030 */ + uint32_t RESERVED0050[44]; /* Address Offset: 0x0050 */ + __IO uint32_t ATOMIC_LOCK[32]; /* Address Offset: 0x0100 */ +}; +/* INTMUX Register Structure Define */ +struct INTMUX_REG { + __IO uint32_t INT_ENABLE_GROUP[32]; /* Address Offset: 0x0000 */ + __I uint32_t INT_FLAG_GROUP[32]; /* Address Offset: 0x0080 */ +}; +#endif /* __ASSEMBLY__ */ +/****************************************************************************************/ +/* */ +/* Module Address Section */ +/* */ +/****************************************************************************************/ +/* Memory Base */ +#define GRF_BASE 0xFDC20000U /* GRF base address */ +#define PMUCRU_BASE 0xFDD00000U /* PMUCRU base address */ +#define TIMER6_BASE 0xFDD1C000U /* TIMER6 base address */ +#define TIMER7_BASE 0xFDD1C020U /* TIMER7 base address */ +#define CRU_BASE 0xFDD20000U /* CRU base address */ +#define I2C0_BASE 0xFDD40000U /* I2C0 base address */ +#define UART0_BASE 0xFDD50000U /* UART0 base address */ +#define GPIO0_BASE 0xFDD60000U /* GPIO0 base address */ +#define PWM0_BASE 0xFDD70000U /* PWM0 base address */ +#define PMU_BASE 0xFDD90000U /* PMU base address */ +#define SPINLOCK_BASE 0xFDE30000U /* SPINLOCK base address */ +#define GMAC1_BASE 0xFE010000U /* GMAC1 base address */ +#define GMAC0_BASE 0xFE2A0000U /* GMAC0 base address */ +#define MMC_BASE 0xFE2B0000U /* MMC base address */ +#define FSPI_BASE 0xFE300000U /* FSPI base address */ +#define DMA0_BASE 0xFE530000U /* DMA0 base address */ +#define DMA1_BASE 0xFE550000U /* DMA1 base address */ +#define CAN0_BASE 0xFE570000U /* CAN0 base address */ +#define CAN1_BASE 0xFE580000U /* CAN1 base address */ +#define CAN2_BASE 0xFE590000U /* CAN2 base address */ +#define I2C1_BASE 0xFE5A0000U /* I2C1 base address */ +#define I2C2_BASE 0xFE5B0000U /* I2C2 base address */ +#define I2C3_BASE 0xFE5C0000U /* I2C3 base address */ +#define I2C4_BASE 0xFE5D0000U /* I2C4 base address */ +#define I2C5_BASE 0xFE5E0000U /* I2C5 base address */ +#define TIMER0_BASE 0xFE5F0000U /* TIMER0 base address */ +#define TIMER1_BASE 0xFE5F0020U /* TIMER1 base address */ +#define TIMER2_BASE 0xFE5F0040U /* TIMER2 base address */ +#define TIMER3_BASE 0xFE5F0060U /* TIMER3 base address */ +#define TIMER4_BASE 0xFE5F0080U /* TIMER4 base address */ +#define TIMER5_BASE 0xFE5F00A0U /* TIMER5 base address */ +#define WDT_BASE 0xFE600000U /* WDT base address */ +#define SPI0_BASE 0xFE610000U /* SPI0 base address */ +#define SPI1_BASE 0xFE620000U /* SPI1 base address */ +#define SPI2_BASE 0xFE630000U /* SPI2 base address */ +#define SPI3_BASE 0xFE640000U /* SPI3 base address */ +#define UART1_BASE 0xFE650000U /* UART1 base address */ +#define UART2_BASE 0xFE660000U /* UART2 base address */ +#define UART3_BASE 0xFE670000U /* UART3 base address */ +#define UART4_BASE 0xFE680000U /* UART4 base address */ +#define UART5_BASE 0xFE690000U /* UART5 base address */ +#define UART6_BASE 0xFE6A0000U /* UART6 base address */ +#define UART7_BASE 0xFE6B0000U /* UART7 base address */ +#define UART8_BASE 0xFE6C0000U /* UART8 base address */ +#define UART9_BASE 0xFE6D0000U /* UART9 base address */ +#define PWM1_BASE 0xFE6E0000U /* PWM1 base address */ +#define PWM2_BASE 0xFE6F0000U /* PWM2 base address */ +#define PWM3_BASE 0xFE700000U /* PWM3 base address */ +#define TSADC_BASE 0xFE710000U /* TSADC base address */ +#define SARADC_BASE 0xFE720000U /* SARADC base address */ +#define GPIO1_BASE 0xFE740000U /* GPIO1 base address */ +#define GPIO2_BASE 0xFE750000U /* GPIO2 base address */ +#define GPIO3_BASE 0xFE760000U /* GPIO3 base address */ +#define GPIO4_BASE 0xFE770000U /* GPIO4 base address */ +#define MBOX0_BASE 0xFE780000U /* MBOX0 base address */ +#define INTMUX_BASE 0xFE790000U /* INTMUX base address */ +/****************************************************************************************/ +/* */ +/* Module Variable Section */ +/* */ +/****************************************************************************************/ +/* Module Variable Define */ + +#define GRF ((struct GRF_REG *) (GRF_BASE + 0x2000000000ULL)) +#define PMUCRU ((struct PMUCRU_REG *) (PMUCRU_BASE + 0x2000000000ULL)) +#define TIMER6 ((struct TIMER_REG *) TIMER6_BASE) +#define TIMER7 ((struct TIMER_REG *) TIMER7_BASE) +#define CRU ((struct CRU_REG *) (CRU_BASE + 0x2000000000ULL)) +#define I2C0 ((struct I2C_REG *) I2C0_BASE) +#define UART0 ((struct UART_REG *) UART0_BASE) +#define GPIO0 ((struct GPIO_REG *) GPIO0_BASE) +#define PWM0 ((struct PWM_REG *) PWM0_BASE) +#define PMU ((struct PMU_REG *) PMU_BASE) +#define SPINLOCK ((struct SPINLOCK_REG *) SPINLOCK_BASE) +#define GMAC1 ((struct GMAC_REG *) GMAC1_BASE) +#define GMAC0 ((struct GMAC_REG *) (GMAC0_BASE + 0x2000000000ULL)) +#define MMC ((struct MMC_REG *) MMC_BASE) +#define FSPI ((struct FSPI_REG *) FSPI_BASE) +#define DMA0 ((struct DMA_REG *) DMA0_BASE) +#define DMA1 ((struct DMA_REG *) DMA1_BASE) +#define CAN0 ((struct CAN_REG *) CAN0_BASE) +#define CAN1 ((struct CAN_REG *) CAN1_BASE) +#define CAN2 ((struct CAN_REG *) CAN2_BASE) +#define I2C1 ((struct I2C_REG *) I2C1_BASE) +#define I2C2 ((struct I2C_REG *) I2C2_BASE) +#define I2C3 ((struct I2C_REG *) I2C3_BASE) +#define I2C4 ((struct I2C_REG *) I2C4_BASE) +#define I2C5 ((struct I2C_REG *) I2C5_BASE) +#define TIMER0 ((struct TIMER_REG *) TIMER0_BASE) +#define TIMER1 ((struct TIMER_REG *) TIMER1_BASE) +#define TIMER2 ((struct TIMER_REG *) TIMER2_BASE) +#define TIMER3 ((struct TIMER_REG *) TIMER3_BASE) +#define TIMER4 ((struct TIMER_REG *) TIMER4_BASE) +#define TIMER5 ((struct TIMER_REG *) (TIMER5_BASE + 0x2000000000ULL)) +#define WDT ((struct WDT_REG *) WDT_BASE) +#define SPI0 ((struct SPI_REG *) SPI0_BASE) +#define SPI1 ((struct SPI_REG *) SPI1_BASE) +#define SPI2 ((struct SPI_REG *) SPI2_BASE) +#define SPI3 ((struct SPI_REG *) SPI3_BASE) +#define UART1 ((struct UART_REG *) UART1_BASE) +#define UART2 ((struct UART_REG *) UART2_BASE) +#define UART3 ((struct UART_REG *) UART3_BASE) +#define UART4 ((struct UART_REG *) UART4_BASE) +#define UART5 ((struct UART_REG *) UART5_BASE) +#define UART6 ((struct UART_REG *) UART6_BASE) +#define UART7 ((struct UART_REG *) UART7_BASE) +#define UART8 ((struct UART_REG *) UART8_BASE) +#define UART9 ((struct UART_REG *) UART9_BASE) +#define PWM1 ((struct PWM_REG *) PWM1_BASE) +#define PWM2 ((struct PWM_REG *) PWM2_BASE) +#define PWM3 ((struct PWM_REG *) PWM3_BASE) +#define TSADC ((struct TSADC_REG *) TSADC_BASE) +#define SARADC ((struct SARADC_REG *) SARADC_BASE) +#define GPIO1 ((struct GPIO_REG *) GPIO1_BASE) +#define GPIO2 ((struct GPIO_REG *) (GPIO2_BASE + 0x2000000000ULL)) +#define GPIO3 ((struct GPIO_REG *) (GPIO3_BASE + 0x2000000000ULL)) +#define GPIO4 ((struct GPIO_REG *) GPIO4_BASE) +#define MBOX0 ((struct MBOX_REG *) MBOX0_BASE) +#define INTMUX ((struct INTMUX_REG *) INTMUX_BASE) + +#define IS_GRF_INSTANCE(instance) ((instance) == GRF) +#define IS_PMUCRU_INSTANCE(instance) ((instance) == PMUCRU) +#define IS_CRU_INSTANCE(instance) ((instance) == CRU) +#define IS_PMU_INSTANCE(instance) ((instance) == PMU) +#define IS_SPINLOCK_INSTANCE(instance) ((instance) == SPINLOCK) +#define IS_MMC_INSTANCE(instance) ((instance) == MMC) +#define IS_FSPI_INSTANCE(instance) ((instance) == FSPI) +#define IS_WDT_INSTANCE(instance) ((instance) == WDT) +#define IS_TSADC_INSTANCE(instance) ((instance) == TSADC) +#define IS_SARADC_INSTANCE(instance) ((instance) == SARADC) +#define IS_INTMUX_INSTANCE(instance) ((instance) == INTMUX) +#define IS_TIMER_INSTANCE(instance) (((instance) == TIMER6) || ((instance) == TIMER7) || ((instance) == TIMER0) || ((instance) == TIMER1) || ((instance) == TIMER2) || ((instance) == TIMER3) || ((instance) == TIMER4) || ((instance) == TIMER5)) +#define IS_I2C_INSTANCE(instance) (((instance) == I2C0) || ((instance) == I2C1) || ((instance) == I2C2) || ((instance) == I2C3) || ((instance) == I2C4) || ((instance) == I2C5)) +#define IS_UART_INSTANCE(instance) (((instance) == UART0) || ((instance) == UART1) || ((instance) == UART2) || ((instance) == UART3) || ((instance) == UART4) || ((instance) == UART5) || ((instance) == UART6) || ((instance) == UART7) || ((instance) == UART8) || ((instance) == UART9)) +#define IS_GPIO_INSTANCE(instance) (((instance) == GPIO0) || ((instance) == GPIO1) || ((instance) == GPIO2) || ((instance) == GPIO3) || ((instance) == GPIO4)) +#define IS_PWM_INSTANCE(instance) (((instance) == PWM0) || ((instance) == PWM1) || ((instance) == PWM2) || ((instance) == PWM3)) +#define IS_GMAC_INSTANCE(instance) (((instance) == GMAC1) || ((instance) == GMAC0)) +#define IS_DMA_INSTANCE(instance) (((instance) == DMA0) || ((instance) == DMA1)) +#define IS_CAN_INSTANCE(instance) (((instance) == CAN0) || ((instance) == CAN1) || ((instance) == CAN2)) +#define IS_SPI_INSTANCE(instance) (((instance) == SPI0) || ((instance) == SPI1) || ((instance) == SPI2) || ((instance) == SPI3)) +#define IS_MBOX_INSTANCE(instance) ((instance) == MBOX0) +/****************************************************************************************/ +/* */ +/* Register Bitmap Section */ +/* */ +/****************************************************************************************/ +/******************************************GRF*******************************************/ +/* GPIO0A_IOMUX_L */ +#define GRF_GPIO0A_IOMUX_L_OFFSET (0x0U) +#define GRF_GPIO0A_IOMUX_L_GPIO0A0_SEL_SHIFT (0U) +#define GRF_GPIO0A_IOMUX_L_GPIO0A0_SEL_MASK (0x7U << GRF_GPIO0A_IOMUX_L_GPIO0A0_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO0A_IOMUX_L_GPIO0A1_SEL_SHIFT (4U) +#define GRF_GPIO0A_IOMUX_L_GPIO0A1_SEL_MASK (0x7U << GRF_GPIO0A_IOMUX_L_GPIO0A1_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO0A_IOMUX_L_GPIO0A2_SEL_SHIFT (8U) +#define GRF_GPIO0A_IOMUX_L_GPIO0A2_SEL_MASK (0x7U << GRF_GPIO0A_IOMUX_L_GPIO0A2_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO0A_IOMUX_L_GPIO0A3_SEL_SHIFT (12U) +#define GRF_GPIO0A_IOMUX_L_GPIO0A3_SEL_MASK (0x7U << GRF_GPIO0A_IOMUX_L_GPIO0A3_SEL_SHIFT) /* 0x00007000 */ +/* GPIO0A_IOMUX_H */ +#define GRF_GPIO0A_IOMUX_H_OFFSET (0x4U) +#define GRF_GPIO0A_IOMUX_H_GPIO0A4_SEL_SHIFT (0U) +#define GRF_GPIO0A_IOMUX_H_GPIO0A4_SEL_MASK (0x7U << GRF_GPIO0A_IOMUX_H_GPIO0A4_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO0A_IOMUX_H_GPIO0A5_SEL_SHIFT (4U) +#define GRF_GPIO0A_IOMUX_H_GPIO0A5_SEL_MASK (0x7U << GRF_GPIO0A_IOMUX_H_GPIO0A5_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO0A_IOMUX_H_GPIO0A6_SEL_SHIFT (8U) +#define GRF_GPIO0A_IOMUX_H_GPIO0A6_SEL_MASK (0x7U << GRF_GPIO0A_IOMUX_H_GPIO0A6_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO0A_IOMUX_H_GPIO0A7_SEL_SHIFT (12U) +#define GRF_GPIO0A_IOMUX_H_GPIO0A7_SEL_MASK (0x7U << GRF_GPIO0A_IOMUX_H_GPIO0A7_SEL_SHIFT) /* 0x00007000 */ +/* GPIO0B_IOMUX_L */ +#define GRF_GPIO0B_IOMUX_L_OFFSET (0x8U) +#define GRF_GPIO0B_IOMUX_L_GPIO0B0_SEL_SHIFT (0U) +#define GRF_GPIO0B_IOMUX_L_GPIO0B0_SEL_MASK (0x7U << GRF_GPIO0B_IOMUX_L_GPIO0B0_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO0B_IOMUX_L_GPIO0B1_SEL_SHIFT (4U) +#define GRF_GPIO0B_IOMUX_L_GPIO0B1_SEL_MASK (0x7U << GRF_GPIO0B_IOMUX_L_GPIO0B1_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO0B_IOMUX_L_GPIO0B2_SEL_SHIFT (8U) +#define GRF_GPIO0B_IOMUX_L_GPIO0B2_SEL_MASK (0x7U << GRF_GPIO0B_IOMUX_L_GPIO0B2_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO0B_IOMUX_L_GPIO0B3_SEL_SHIFT (12U) +#define GRF_GPIO0B_IOMUX_L_GPIO0B3_SEL_MASK (0x7U << GRF_GPIO0B_IOMUX_L_GPIO0B3_SEL_SHIFT) /* 0x00007000 */ +/* GPIO0B_IOMUX_H */ +#define GRF_GPIO0B_IOMUX_H_OFFSET (0xCU) +#define GRF_GPIO0B_IOMUX_H_GPIO0B4_SEL_SHIFT (0U) +#define GRF_GPIO0B_IOMUX_H_GPIO0B4_SEL_MASK (0x7U << GRF_GPIO0B_IOMUX_H_GPIO0B4_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO0B_IOMUX_H_GPIO0B5_SEL_SHIFT (4U) +#define GRF_GPIO0B_IOMUX_H_GPIO0B5_SEL_MASK (0x7U << GRF_GPIO0B_IOMUX_H_GPIO0B5_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO0B_IOMUX_H_GPIO0B6_SEL_SHIFT (8U) +#define GRF_GPIO0B_IOMUX_H_GPIO0B6_SEL_MASK (0x7U << GRF_GPIO0B_IOMUX_H_GPIO0B6_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO0B_IOMUX_H_GPIO0B7_SEL_SHIFT (12U) +#define GRF_GPIO0B_IOMUX_H_GPIO0B7_SEL_MASK (0x7U << GRF_GPIO0B_IOMUX_H_GPIO0B7_SEL_SHIFT) /* 0x00007000 */ +/* GPIO0C_IOMUX_L */ +#define GRF_GPIO0C_IOMUX_L_OFFSET (0x10U) +#define GRF_GPIO0C_IOMUX_L_GPIO0C0_SEL_SHIFT (0U) +#define GRF_GPIO0C_IOMUX_L_GPIO0C0_SEL_MASK (0x7U << GRF_GPIO0C_IOMUX_L_GPIO0C0_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO0C_IOMUX_L_GPIO0C1_SEL_SHIFT (4U) +#define GRF_GPIO0C_IOMUX_L_GPIO0C1_SEL_MASK (0x7U << GRF_GPIO0C_IOMUX_L_GPIO0C1_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO0C_IOMUX_L_GPIO0C2_SEL_SHIFT (8U) +#define GRF_GPIO0C_IOMUX_L_GPIO0C2_SEL_MASK (0x7U << GRF_GPIO0C_IOMUX_L_GPIO0C2_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO0C_IOMUX_L_GPIO0C3_SEL_SHIFT (12U) +#define GRF_GPIO0C_IOMUX_L_GPIO0C3_SEL_MASK (0x7U << GRF_GPIO0C_IOMUX_L_GPIO0C3_SEL_SHIFT) /* 0x00007000 */ +/* GPIO0C_IOMUX_H */ +#define GRF_GPIO0C_IOMUX_H_OFFSET (0x14U) +#define GRF_GPIO0C_IOMUX_H_GPIO0C4_SEL_SHIFT (0U) +#define GRF_GPIO0C_IOMUX_H_GPIO0C4_SEL_MASK (0x7U << GRF_GPIO0C_IOMUX_H_GPIO0C4_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO0C_IOMUX_H_GPIO0C5_SEL_SHIFT (4U) +#define GRF_GPIO0C_IOMUX_H_GPIO0C5_SEL_MASK (0x7U << GRF_GPIO0C_IOMUX_H_GPIO0C5_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO0C_IOMUX_H_GPIO0C6_SEL_SHIFT (8U) +#define GRF_GPIO0C_IOMUX_H_GPIO0C6_SEL_MASK (0x7U << GRF_GPIO0C_IOMUX_H_GPIO0C6_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO0C_IOMUX_H_GPIO0C7_SEL_SHIFT (12U) +#define GRF_GPIO0C_IOMUX_H_GPIO0C7_SEL_MASK (0x7U << GRF_GPIO0C_IOMUX_H_GPIO0C7_SEL_SHIFT) /* 0x00007000 */ +/* GPIO0D_IOMUX_L */ +#define GRF_GPIO0D_IOMUX_L_OFFSET (0x18U) +#define GRF_GPIO0D_IOMUX_L_GPIO0D0_SEL_SHIFT (0U) +#define GRF_GPIO0D_IOMUX_L_GPIO0D0_SEL_MASK (0x7U << GRF_GPIO0D_IOMUX_L_GPIO0D0_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO0D_IOMUX_L_GPIO0D1_SEL_SHIFT (4U) +#define GRF_GPIO0D_IOMUX_L_GPIO0D1_SEL_MASK (0x7U << GRF_GPIO0D_IOMUX_L_GPIO0D1_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO0D_IOMUX_L_GPIO0D3_SEL_SHIFT (12U) +#define GRF_GPIO0D_IOMUX_L_GPIO0D3_SEL_MASK (0x7U << GRF_GPIO0D_IOMUX_L_GPIO0D3_SEL_SHIFT) /* 0x00007000 */ +/* GPIO0D_IOMUX_H */ +#define GRF_GPIO0D_IOMUX_H_OFFSET (0x1CU) +#define GRF_GPIO0D_IOMUX_H_GPIO0D4_SEL_SHIFT (0U) +#define GRF_GPIO0D_IOMUX_H_GPIO0D4_SEL_MASK (0x7U << GRF_GPIO0D_IOMUX_H_GPIO0D4_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO0D_IOMUX_H_GPIO0D5_SEL_SHIFT (4U) +#define GRF_GPIO0D_IOMUX_H_GPIO0D5_SEL_MASK (0x7U << GRF_GPIO0D_IOMUX_H_GPIO0D5_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO0D_IOMUX_H_GPIO0D6_SEL_SHIFT (8U) +#define GRF_GPIO0D_IOMUX_H_GPIO0D6_SEL_MASK (0x7U << GRF_GPIO0D_IOMUX_H_GPIO0D6_SEL_SHIFT) /* 0x00000700 */ +/* GPIO0A_P */ +#define GRF_GPIO0A_P_OFFSET (0x20U) +#define GRF_GPIO0A_P_GPIO0A0_P_SHIFT (0U) +#define GRF_GPIO0A_P_GPIO0A0_P_MASK (0x3U << GRF_GPIO0A_P_GPIO0A0_P_SHIFT) /* 0x00000003 */ +#define GRF_GPIO0A_P_GPIO0A1_P_SHIFT (2U) +#define GRF_GPIO0A_P_GPIO0A1_P_MASK (0x3U << GRF_GPIO0A_P_GPIO0A1_P_SHIFT) /* 0x0000000C */ +#define GRF_GPIO0A_P_GPIO0A2_P_SHIFT (4U) +#define GRF_GPIO0A_P_GPIO0A2_P_MASK (0x3U << GRF_GPIO0A_P_GPIO0A2_P_SHIFT) /* 0x00000030 */ +#define GRF_GPIO0A_P_GPIO0A3_P_SHIFT (6U) +#define GRF_GPIO0A_P_GPIO0A3_P_MASK (0x3U << GRF_GPIO0A_P_GPIO0A3_P_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO0A_P_GPIO0A4_P_SHIFT (8U) +#define GRF_GPIO0A_P_GPIO0A4_P_MASK (0x3U << GRF_GPIO0A_P_GPIO0A4_P_SHIFT) /* 0x00000300 */ +#define GRF_GPIO0A_P_GPIO0A5_P_SHIFT (10U) +#define GRF_GPIO0A_P_GPIO0A5_P_MASK (0x3U << GRF_GPIO0A_P_GPIO0A5_P_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO0A_P_GPIO0A6_P_SHIFT (12U) +#define GRF_GPIO0A_P_GPIO0A6_P_MASK (0x3U << GRF_GPIO0A_P_GPIO0A6_P_SHIFT) /* 0x00003000 */ +#define GRF_GPIO0A_P_GPIO0A7_P_SHIFT (14U) +#define GRF_GPIO0A_P_GPIO0A7_P_MASK (0x3U << GRF_GPIO0A_P_GPIO0A7_P_SHIFT) /* 0x0000C000 */ +/* GPIO0B_P */ +#define GRF_GPIO0B_P_OFFSET (0x24U) +#define GRF_GPIO0B_P_GPIO0B0_P_SHIFT (0U) +#define GRF_GPIO0B_P_GPIO0B0_P_MASK (0x3U << GRF_GPIO0B_P_GPIO0B0_P_SHIFT) /* 0x00000003 */ +#define GRF_GPIO0B_P_GPIO0B1_P_SHIFT (2U) +#define GRF_GPIO0B_P_GPIO0B1_P_MASK (0x3U << GRF_GPIO0B_P_GPIO0B1_P_SHIFT) /* 0x0000000C */ +#define GRF_GPIO0B_P_GPIO0B2_P_SHIFT (4U) +#define GRF_GPIO0B_P_GPIO0B2_P_MASK (0x3U << GRF_GPIO0B_P_GPIO0B2_P_SHIFT) /* 0x00000030 */ +#define GRF_GPIO0B_P_GPIO0B3_P_SHIFT (6U) +#define GRF_GPIO0B_P_GPIO0B3_P_MASK (0x3U << GRF_GPIO0B_P_GPIO0B3_P_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO0B_P_GPIO0B4_P_SHIFT (8U) +#define GRF_GPIO0B_P_GPIO0B4_P_MASK (0x3U << GRF_GPIO0B_P_GPIO0B4_P_SHIFT) /* 0x00000300 */ +#define GRF_GPIO0B_P_GPIO0B5_P_SHIFT (10U) +#define GRF_GPIO0B_P_GPIO0B5_P_MASK (0x3U << GRF_GPIO0B_P_GPIO0B5_P_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO0B_P_GPIO0B6_P_SHIFT (12U) +#define GRF_GPIO0B_P_GPIO0B6_P_MASK (0x3U << GRF_GPIO0B_P_GPIO0B6_P_SHIFT) /* 0x00003000 */ +#define GRF_GPIO0B_P_GPIO0B7_P_SHIFT (14U) +#define GRF_GPIO0B_P_GPIO0B7_P_MASK (0x3U << GRF_GPIO0B_P_GPIO0B7_P_SHIFT) /* 0x0000C000 */ +/* GPIO0C_P */ +#define GRF_GPIO0C_P_OFFSET (0x28U) +#define GRF_GPIO0C_P_GPIO0C0_P_SHIFT (0U) +#define GRF_GPIO0C_P_GPIO0C0_P_MASK (0x3U << GRF_GPIO0C_P_GPIO0C0_P_SHIFT) /* 0x00000003 */ +#define GRF_GPIO0C_P_GPIO0C1_P_SHIFT (2U) +#define GRF_GPIO0C_P_GPIO0C1_P_MASK (0x3U << GRF_GPIO0C_P_GPIO0C1_P_SHIFT) /* 0x0000000C */ +#define GRF_GPIO0C_P_GPIO0C2_P_SHIFT (4U) +#define GRF_GPIO0C_P_GPIO0C2_P_MASK (0x3U << GRF_GPIO0C_P_GPIO0C2_P_SHIFT) /* 0x00000030 */ +#define GRF_GPIO0C_P_GPIO0C3_P_SHIFT (6U) +#define GRF_GPIO0C_P_GPIO0C3_P_MASK (0x3U << GRF_GPIO0C_P_GPIO0C3_P_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO0C_P_GPIO0C4_P_SHIFT (8U) +#define GRF_GPIO0C_P_GPIO0C4_P_MASK (0x3U << GRF_GPIO0C_P_GPIO0C4_P_SHIFT) /* 0x00000300 */ +#define GRF_GPIO0C_P_GPIO0C5_P_SHIFT (10U) +#define GRF_GPIO0C_P_GPIO0C5_P_MASK (0x3U << GRF_GPIO0C_P_GPIO0C5_P_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO0C_P_GPIO0C6_P_SHIFT (12U) +#define GRF_GPIO0C_P_GPIO0C6_P_MASK (0x3U << GRF_GPIO0C_P_GPIO0C6_P_SHIFT) /* 0x00003000 */ +#define GRF_GPIO0C_P_GPIO0C7_P_SHIFT (14U) +#define GRF_GPIO0C_P_GPIO0C7_P_MASK (0x3U << GRF_GPIO0C_P_GPIO0C7_P_SHIFT) /* 0x0000C000 */ +/* GPIO0D_P */ +#define GRF_GPIO0D_P_OFFSET (0x2CU) +#define GRF_GPIO0D_P_GPIO0D0_P_SHIFT (0U) +#define GRF_GPIO0D_P_GPIO0D0_P_MASK (0x3U << GRF_GPIO0D_P_GPIO0D0_P_SHIFT) /* 0x00000003 */ +#define GRF_GPIO0D_P_GPIO0D1_P_SHIFT (2U) +#define GRF_GPIO0D_P_GPIO0D1_P_MASK (0x3U << GRF_GPIO0D_P_GPIO0D1_P_SHIFT) /* 0x0000000C */ +#define GRF_GPIO0D_P_GPIO0D2_P_SHIFT (4U) +#define GRF_GPIO0D_P_GPIO0D2_P_MASK (0x3U << GRF_GPIO0D_P_GPIO0D2_P_SHIFT) /* 0x00000030 */ +#define GRF_GPIO0D_P_GPIO0D3_P_SHIFT (6U) +#define GRF_GPIO0D_P_GPIO0D3_P_MASK (0x3U << GRF_GPIO0D_P_GPIO0D3_P_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO0D_P_GPIO0D4_P_SHIFT (8U) +#define GRF_GPIO0D_P_GPIO0D4_P_MASK (0x3U << GRF_GPIO0D_P_GPIO0D4_P_SHIFT) /* 0x00000300 */ +#define GRF_GPIO0D_P_GPIO0D5_P_SHIFT (10U) +#define GRF_GPIO0D_P_GPIO0D5_P_MASK (0x3U << GRF_GPIO0D_P_GPIO0D5_P_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO0D_P_GPIO0D6_P_SHIFT (12U) +#define GRF_GPIO0D_P_GPIO0D6_P_MASK (0x3U << GRF_GPIO0D_P_GPIO0D6_P_SHIFT) /* 0x00003000 */ +/* GPIO0A_IE */ +#define GRF_GPIO0A_IE_OFFSET (0x30U) +#define GRF_GPIO0A_IE_GPIO0A0_IE_SHIFT (0U) +#define GRF_GPIO0A_IE_GPIO0A0_IE_MASK (0x3U << GRF_GPIO0A_IE_GPIO0A0_IE_SHIFT) /* 0x00000003 */ +#define GRF_GPIO0A_IE_GPIO0A1_IE_SHIFT (2U) +#define GRF_GPIO0A_IE_GPIO0A1_IE_MASK (0x3U << GRF_GPIO0A_IE_GPIO0A1_IE_SHIFT) /* 0x0000000C */ +#define GRF_GPIO0A_IE_GPIO0A2_IE_SHIFT (4U) +#define GRF_GPIO0A_IE_GPIO0A2_IE_MASK (0x3U << GRF_GPIO0A_IE_GPIO0A2_IE_SHIFT) /* 0x00000030 */ +#define GRF_GPIO0A_IE_GPIO0A3_IE_SHIFT (6U) +#define GRF_GPIO0A_IE_GPIO0A3_IE_MASK (0x3U << GRF_GPIO0A_IE_GPIO0A3_IE_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO0A_IE_GPIO0A4_IE_SHIFT (8U) +#define GRF_GPIO0A_IE_GPIO0A4_IE_MASK (0x3U << GRF_GPIO0A_IE_GPIO0A4_IE_SHIFT) /* 0x00000300 */ +#define GRF_GPIO0A_IE_GPIO0A5_IE_SHIFT (10U) +#define GRF_GPIO0A_IE_GPIO0A5_IE_MASK (0x3U << GRF_GPIO0A_IE_GPIO0A5_IE_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO0A_IE_GPIO0A6_IE_SHIFT (12U) +#define GRF_GPIO0A_IE_GPIO0A6_IE_MASK (0x3U << GRF_GPIO0A_IE_GPIO0A6_IE_SHIFT) /* 0x00003000 */ +#define GRF_GPIO0A_IE_GPIO0A7_IE_SHIFT (14U) +#define GRF_GPIO0A_IE_GPIO0A7_IE_MASK (0x3U << GRF_GPIO0A_IE_GPIO0A7_IE_SHIFT) /* 0x0000C000 */ +/* GPIO0B_IE */ +#define GRF_GPIO0B_IE_OFFSET (0x34U) +#define GRF_GPIO0B_IE_GPIO0B0_IE_SHIFT (0U) +#define GRF_GPIO0B_IE_GPIO0B0_IE_MASK (0x3U << GRF_GPIO0B_IE_GPIO0B0_IE_SHIFT) /* 0x00000003 */ +#define GRF_GPIO0B_IE_GPIO0B1_IE_SHIFT (2U) +#define GRF_GPIO0B_IE_GPIO0B1_IE_MASK (0x3U << GRF_GPIO0B_IE_GPIO0B1_IE_SHIFT) /* 0x0000000C */ +#define GRF_GPIO0B_IE_GPIO0B2_IE_SHIFT (4U) +#define GRF_GPIO0B_IE_GPIO0B2_IE_MASK (0x3U << GRF_GPIO0B_IE_GPIO0B2_IE_SHIFT) /* 0x00000030 */ +#define GRF_GPIO0B_IE_GPIO0B3_IE_SHIFT (6U) +#define GRF_GPIO0B_IE_GPIO0B3_IE_MASK (0x3U << GRF_GPIO0B_IE_GPIO0B3_IE_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO0B_IE_GPIO0B4_IE_SHIFT (8U) +#define GRF_GPIO0B_IE_GPIO0B4_IE_MASK (0x3U << GRF_GPIO0B_IE_GPIO0B4_IE_SHIFT) /* 0x00000300 */ +#define GRF_GPIO0B_IE_GPIO0B5_IE_SHIFT (10U) +#define GRF_GPIO0B_IE_GPIO0B5_IE_MASK (0x3U << GRF_GPIO0B_IE_GPIO0B5_IE_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO0B_IE_GPIO0B6_IE_SHIFT (12U) +#define GRF_GPIO0B_IE_GPIO0B6_IE_MASK (0x3U << GRF_GPIO0B_IE_GPIO0B6_IE_SHIFT) /* 0x00003000 */ +#define GRF_GPIO0B_IE_GPIO0B7_IE_SHIFT (14U) +#define GRF_GPIO0B_IE_GPIO0B7_IE_MASK (0x3U << GRF_GPIO0B_IE_GPIO0B7_IE_SHIFT) /* 0x0000C000 */ +/* GPIO0C_IE */ +#define GRF_GPIO0C_IE_OFFSET (0x38U) +#define GRF_GPIO0C_IE_GPIO0C0_IE_SHIFT (0U) +#define GRF_GPIO0C_IE_GPIO0C0_IE_MASK (0x3U << GRF_GPIO0C_IE_GPIO0C0_IE_SHIFT) /* 0x00000003 */ +#define GRF_GPIO0C_IE_GPIO0C1_IE_SHIFT (2U) +#define GRF_GPIO0C_IE_GPIO0C1_IE_MASK (0x3U << GRF_GPIO0C_IE_GPIO0C1_IE_SHIFT) /* 0x0000000C */ +#define GRF_GPIO0C_IE_GPIO0C2_IE_SHIFT (4U) +#define GRF_GPIO0C_IE_GPIO0C2_IE_MASK (0x3U << GRF_GPIO0C_IE_GPIO0C2_IE_SHIFT) /* 0x00000030 */ +#define GRF_GPIO0C_IE_GPIO0C3_IE_SHIFT (6U) +#define GRF_GPIO0C_IE_GPIO0C3_IE_MASK (0x3U << GRF_GPIO0C_IE_GPIO0C3_IE_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO0C_IE_GPIO0C4_IE_SHIFT (8U) +#define GRF_GPIO0C_IE_GPIO0C4_IE_MASK (0x3U << GRF_GPIO0C_IE_GPIO0C4_IE_SHIFT) /* 0x00000300 */ +#define GRF_GPIO0C_IE_GPIO0C5_IE_SHIFT (10U) +#define GRF_GPIO0C_IE_GPIO0C5_IE_MASK (0x3U << GRF_GPIO0C_IE_GPIO0C5_IE_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO0C_IE_GPIO0C6_IE_SHIFT (12U) +#define GRF_GPIO0C_IE_GPIO0C6_IE_MASK (0x3U << GRF_GPIO0C_IE_GPIO0C6_IE_SHIFT) /* 0x00003000 */ +#define GRF_GPIO0C_IE_GPIO0C7_IE_SHIFT (14U) +#define GRF_GPIO0C_IE_GPIO0C7_IE_MASK (0x3U << GRF_GPIO0C_IE_GPIO0C7_IE_SHIFT) /* 0x0000C000 */ +/* GPIO0D_IE */ +#define GRF_GPIO0D_IE_OFFSET (0x3CU) +#define GRF_GPIO0D_IE_GPIO0D0_IE_SHIFT (0U) +#define GRF_GPIO0D_IE_GPIO0D0_IE_MASK (0x3U << GRF_GPIO0D_IE_GPIO0D0_IE_SHIFT) /* 0x00000003 */ +#define GRF_GPIO0D_IE_GPIO0D1_IE_SHIFT (2U) +#define GRF_GPIO0D_IE_GPIO0D1_IE_MASK (0x3U << GRF_GPIO0D_IE_GPIO0D1_IE_SHIFT) /* 0x0000000C */ +/* GPIO0A_OPD */ +#define GRF_GPIO0A_OPD_OFFSET (0x40U) +#define GRF_GPIO0A_OPD_GPIO0A0_OPD_SHIFT (0U) +#define GRF_GPIO0A_OPD_GPIO0A0_OPD_MASK (0x1U << GRF_GPIO0A_OPD_GPIO0A0_OPD_SHIFT) /* 0x00000001 */ +#define GRF_GPIO0A_OPD_GPIO0A1_OPD_SHIFT (1U) +#define GRF_GPIO0A_OPD_GPIO0A1_OPD_MASK (0x1U << GRF_GPIO0A_OPD_GPIO0A1_OPD_SHIFT) /* 0x00000002 */ +#define GRF_GPIO0A_OPD_GPIO0A2_OPD_SHIFT (2U) +#define GRF_GPIO0A_OPD_GPIO0A2_OPD_MASK (0x1U << GRF_GPIO0A_OPD_GPIO0A2_OPD_SHIFT) /* 0x00000004 */ +#define GRF_GPIO0A_OPD_GPIO0A3_OPD_SHIFT (3U) +#define GRF_GPIO0A_OPD_GPIO0A3_OPD_MASK (0x1U << GRF_GPIO0A_OPD_GPIO0A3_OPD_SHIFT) /* 0x00000008 */ +#define GRF_GPIO0A_OPD_GPIO0A4_OPD_SHIFT (4U) +#define GRF_GPIO0A_OPD_GPIO0A4_OPD_MASK (0x1U << GRF_GPIO0A_OPD_GPIO0A4_OPD_SHIFT) /* 0x00000010 */ +#define GRF_GPIO0A_OPD_GPIO0A5_OPD_SHIFT (5U) +#define GRF_GPIO0A_OPD_GPIO0A5_OPD_MASK (0x1U << GRF_GPIO0A_OPD_GPIO0A5_OPD_SHIFT) /* 0x00000020 */ +#define GRF_GPIO0A_OPD_GPIO0A6_OPD_SHIFT (6U) +#define GRF_GPIO0A_OPD_GPIO0A6_OPD_MASK (0x1U << GRF_GPIO0A_OPD_GPIO0A6_OPD_SHIFT) /* 0x00000040 */ +#define GRF_GPIO0A_OPD_GPIO0A7_OPD_SHIFT (7U) +#define GRF_GPIO0A_OPD_GPIO0A7_OPD_MASK (0x1U << GRF_GPIO0A_OPD_GPIO0A7_OPD_SHIFT) /* 0x00000080 */ +/* GPIO0B_OPD */ +#define GRF_GPIO0B_OPD_OFFSET (0x44U) +#define GRF_GPIO0B_OPD_GPIO0B0_OPD_SHIFT (0U) +#define GRF_GPIO0B_OPD_GPIO0B0_OPD_MASK (0x1U << GRF_GPIO0B_OPD_GPIO0B0_OPD_SHIFT) /* 0x00000001 */ +#define GRF_GPIO0B_OPD_GPIO0B1_OPD_SHIFT (1U) +#define GRF_GPIO0B_OPD_GPIO0B1_OPD_MASK (0x1U << GRF_GPIO0B_OPD_GPIO0B1_OPD_SHIFT) /* 0x00000002 */ +#define GRF_GPIO0B_OPD_GPIO0B2_OPD_SHIFT (2U) +#define GRF_GPIO0B_OPD_GPIO0B2_OPD_MASK (0x1U << GRF_GPIO0B_OPD_GPIO0B2_OPD_SHIFT) /* 0x00000004 */ +#define GRF_GPIO0B_OPD_GPIO0B3_OPD_SHIFT (3U) +#define GRF_GPIO0B_OPD_GPIO0B3_OPD_MASK (0x1U << GRF_GPIO0B_OPD_GPIO0B3_OPD_SHIFT) /* 0x00000008 */ +#define GRF_GPIO0B_OPD_GPIO0B4_OPD_SHIFT (4U) +#define GRF_GPIO0B_OPD_GPIO0B4_OPD_MASK (0x1U << GRF_GPIO0B_OPD_GPIO0B4_OPD_SHIFT) /* 0x00000010 */ +#define GRF_GPIO0B_OPD_GPIO0B5_OPD_SHIFT (5U) +#define GRF_GPIO0B_OPD_GPIO0B5_OPD_MASK (0x1U << GRF_GPIO0B_OPD_GPIO0B5_OPD_SHIFT) /* 0x00000020 */ +#define GRF_GPIO0B_OPD_GPIO0B6_OPD_SHIFT (6U) +#define GRF_GPIO0B_OPD_GPIO0B6_OPD_MASK (0x1U << GRF_GPIO0B_OPD_GPIO0B6_OPD_SHIFT) /* 0x00000040 */ +#define GRF_GPIO0B_OPD_GPIO0B7_OPD_SHIFT (7U) +#define GRF_GPIO0B_OPD_GPIO0B7_OPD_MASK (0x1U << GRF_GPIO0B_OPD_GPIO0B7_OPD_SHIFT) /* 0x00000080 */ +/* GPIO0C_OPD */ +#define GRF_GPIO0C_OPD_OFFSET (0x48U) +#define GRF_GPIO0C_OPD_GPIO0C0_OPD_SHIFT (0U) +#define GRF_GPIO0C_OPD_GPIO0C0_OPD_MASK (0x1U << GRF_GPIO0C_OPD_GPIO0C0_OPD_SHIFT) /* 0x00000001 */ +#define GRF_GPIO0C_OPD_GPIO0C1_OPD_SHIFT (1U) +#define GRF_GPIO0C_OPD_GPIO0C1_OPD_MASK (0x1U << GRF_GPIO0C_OPD_GPIO0C1_OPD_SHIFT) /* 0x00000002 */ +#define GRF_GPIO0C_OPD_GPIO0C2_OPD_SHIFT (2U) +#define GRF_GPIO0C_OPD_GPIO0C2_OPD_MASK (0x1U << GRF_GPIO0C_OPD_GPIO0C2_OPD_SHIFT) /* 0x00000004 */ +#define GRF_GPIO0C_OPD_GPIO0C3_OPD_SHIFT (3U) +#define GRF_GPIO0C_OPD_GPIO0C3_OPD_MASK (0x1U << GRF_GPIO0C_OPD_GPIO0C3_OPD_SHIFT) /* 0x00000008 */ +#define GRF_GPIO0C_OPD_GPIO0C4_OPD_SHIFT (4U) +#define GRF_GPIO0C_OPD_GPIO0C4_OPD_MASK (0x1U << GRF_GPIO0C_OPD_GPIO0C4_OPD_SHIFT) /* 0x00000010 */ +#define GRF_GPIO0C_OPD_GPIO0C5_OPD_SHIFT (5U) +#define GRF_GPIO0C_OPD_GPIO0C5_OPD_MASK (0x1U << GRF_GPIO0C_OPD_GPIO0C5_OPD_SHIFT) /* 0x00000020 */ +#define GRF_GPIO0C_OPD_GPIO0C6_OPD_SHIFT (6U) +#define GRF_GPIO0C_OPD_GPIO0C6_OPD_MASK (0x1U << GRF_GPIO0C_OPD_GPIO0C6_OPD_SHIFT) /* 0x00000040 */ +#define GRF_GPIO0C_OPD_GPIO0C7_OPD_SHIFT (7U) +#define GRF_GPIO0C_OPD_GPIO0C7_OPD_MASK (0x1U << GRF_GPIO0C_OPD_GPIO0C7_OPD_SHIFT) /* 0x00000080 */ +/* GPIO0D_OPD */ +#define GRF_GPIO0D_OPD_OFFSET (0x4CU) +#define GRF_GPIO0D_OPD_GPIO0D0_OPD_SHIFT (0U) +#define GRF_GPIO0D_OPD_GPIO0D0_OPD_MASK (0x1U << GRF_GPIO0D_OPD_GPIO0D0_OPD_SHIFT) /* 0x00000001 */ +#define GRF_GPIO0D_OPD_GPIO0D1_OPD_SHIFT (1U) +#define GRF_GPIO0D_OPD_GPIO0D1_OPD_MASK (0x1U << GRF_GPIO0D_OPD_GPIO0D1_OPD_SHIFT) /* 0x00000002 */ +/* GPIO0A_SUS */ +#define GRF_GPIO0A_SUS_OFFSET (0x50U) +#define GRF_GPIO0A_SUS_GPIO0A0_SUS_SHIFT (0U) +#define GRF_GPIO0A_SUS_GPIO0A0_SUS_MASK (0x1U << GRF_GPIO0A_SUS_GPIO0A0_SUS_SHIFT) /* 0x00000001 */ +#define GRF_GPIO0A_SUS_GPIO0A1_SUS_SHIFT (1U) +#define GRF_GPIO0A_SUS_GPIO0A1_SUS_MASK (0x1U << GRF_GPIO0A_SUS_GPIO0A1_SUS_SHIFT) /* 0x00000002 */ +#define GRF_GPIO0A_SUS_GPIO0A2_SUS_SHIFT (2U) +#define GRF_GPIO0A_SUS_GPIO0A2_SUS_MASK (0x1U << GRF_GPIO0A_SUS_GPIO0A2_SUS_SHIFT) /* 0x00000004 */ +#define GRF_GPIO0A_SUS_GPIO0A3_SUS_SHIFT (3U) +#define GRF_GPIO0A_SUS_GPIO0A3_SUS_MASK (0x1U << GRF_GPIO0A_SUS_GPIO0A3_SUS_SHIFT) /* 0x00000008 */ +#define GRF_GPIO0A_SUS_GPIO0A4_SUS_SHIFT (4U) +#define GRF_GPIO0A_SUS_GPIO0A4_SUS_MASK (0x1U << GRF_GPIO0A_SUS_GPIO0A4_SUS_SHIFT) /* 0x00000010 */ +#define GRF_GPIO0A_SUS_GPIO0A5_SUS_SHIFT (5U) +#define GRF_GPIO0A_SUS_GPIO0A5_SUS_MASK (0x1U << GRF_GPIO0A_SUS_GPIO0A5_SUS_SHIFT) /* 0x00000020 */ +#define GRF_GPIO0A_SUS_GPIO0A6_SUS_SHIFT (6U) +#define GRF_GPIO0A_SUS_GPIO0A6_SUS_MASK (0x1U << GRF_GPIO0A_SUS_GPIO0A6_SUS_SHIFT) /* 0x00000040 */ +#define GRF_GPIO0A_SUS_GPIO0A7_SUS_SHIFT (7U) +#define GRF_GPIO0A_SUS_GPIO0A7_SUS_MASK (0x1U << GRF_GPIO0A_SUS_GPIO0A7_SUS_SHIFT) /* 0x00000080 */ +/* GPIO0B_SUS */ +#define GRF_GPIO0B_SUS_OFFSET (0x54U) +#define GRF_GPIO0B_SUS_GPIO0B0_SUS_SHIFT (0U) +#define GRF_GPIO0B_SUS_GPIO0B0_SUS_MASK (0x1U << GRF_GPIO0B_SUS_GPIO0B0_SUS_SHIFT) /* 0x00000001 */ +#define GRF_GPIO0B_SUS_GPIO0B1_SUS_SHIFT (1U) +#define GRF_GPIO0B_SUS_GPIO0B1_SUS_MASK (0x1U << GRF_GPIO0B_SUS_GPIO0B1_SUS_SHIFT) /* 0x00000002 */ +#define GRF_GPIO0B_SUS_GPIO0B2_SUS_SHIFT (2U) +#define GRF_GPIO0B_SUS_GPIO0B2_SUS_MASK (0x1U << GRF_GPIO0B_SUS_GPIO0B2_SUS_SHIFT) /* 0x00000004 */ +#define GRF_GPIO0B_SUS_GPIO0B3_SUS_SHIFT (3U) +#define GRF_GPIO0B_SUS_GPIO0B3_SUS_MASK (0x1U << GRF_GPIO0B_SUS_GPIO0B3_SUS_SHIFT) /* 0x00000008 */ +#define GRF_GPIO0B_SUS_GPIO0B4_SUS_SHIFT (4U) +#define GRF_GPIO0B_SUS_GPIO0B4_SUS_MASK (0x1U << GRF_GPIO0B_SUS_GPIO0B4_SUS_SHIFT) /* 0x00000010 */ +#define GRF_GPIO0B_SUS_GPIO0B5_SUS_SHIFT (5U) +#define GRF_GPIO0B_SUS_GPIO0B5_SUS_MASK (0x1U << GRF_GPIO0B_SUS_GPIO0B5_SUS_SHIFT) /* 0x00000020 */ +#define GRF_GPIO0B_SUS_GPIO0B6_SUS_SHIFT (6U) +#define GRF_GPIO0B_SUS_GPIO0B6_SUS_MASK (0x1U << GRF_GPIO0B_SUS_GPIO0B6_SUS_SHIFT) /* 0x00000040 */ +#define GRF_GPIO0B_SUS_GPIO0B7_SUS_SHIFT (7U) +#define GRF_GPIO0B_SUS_GPIO0B7_SUS_MASK (0x1U << GRF_GPIO0B_SUS_GPIO0B7_SUS_SHIFT) /* 0x00000080 */ +/* GPIO0C_SUS */ +#define GRF_GPIO0C_SUS_OFFSET (0x58U) +#define GRF_GPIO0C_SUS_GPIO0C0_SUS_SHIFT (0U) +#define GRF_GPIO0C_SUS_GPIO0C0_SUS_MASK (0x1U << GRF_GPIO0C_SUS_GPIO0C0_SUS_SHIFT) /* 0x00000001 */ +#define GRF_GPIO0C_SUS_GPIO0C1_SUS_SHIFT (1U) +#define GRF_GPIO0C_SUS_GPIO0C1_SUS_MASK (0x1U << GRF_GPIO0C_SUS_GPIO0C1_SUS_SHIFT) /* 0x00000002 */ +#define GRF_GPIO0C_SUS_GPIO0C2_SUS_SHIFT (2U) +#define GRF_GPIO0C_SUS_GPIO0C2_SUS_MASK (0x1U << GRF_GPIO0C_SUS_GPIO0C2_SUS_SHIFT) /* 0x00000004 */ +#define GRF_GPIO0C_SUS_GPIO0C3_SUS_SHIFT (3U) +#define GRF_GPIO0C_SUS_GPIO0C3_SUS_MASK (0x1U << GRF_GPIO0C_SUS_GPIO0C3_SUS_SHIFT) /* 0x00000008 */ +#define GRF_GPIO0C_SUS_GPIO0C4_SUS_SHIFT (4U) +#define GRF_GPIO0C_SUS_GPIO0C4_SUS_MASK (0x1U << GRF_GPIO0C_SUS_GPIO0C4_SUS_SHIFT) /* 0x00000010 */ +#define GRF_GPIO0C_SUS_GPIO0C5_SUS_SHIFT (5U) +#define GRF_GPIO0C_SUS_GPIO0C5_SUS_MASK (0x1U << GRF_GPIO0C_SUS_GPIO0C5_SUS_SHIFT) /* 0x00000020 */ +#define GRF_GPIO0C_SUS_GPIO0C6_SUS_SHIFT (6U) +#define GRF_GPIO0C_SUS_GPIO0C6_SUS_MASK (0x1U << GRF_GPIO0C_SUS_GPIO0C6_SUS_SHIFT) /* 0x00000040 */ +#define GRF_GPIO0C_SUS_GPIO0C7_SUS_SHIFT (7U) +#define GRF_GPIO0C_SUS_GPIO0C7_SUS_MASK (0x1U << GRF_GPIO0C_SUS_GPIO0C7_SUS_SHIFT) /* 0x00000080 */ +/* GPIO0D_SUS */ +#define GRF_GPIO0D_SUS_OFFSET (0x5CU) +#define GRF_GPIO0D_SUS_GPIO0D0_SUS_SHIFT (0U) +#define GRF_GPIO0D_SUS_GPIO0D0_SUS_MASK (0x1U << GRF_GPIO0D_SUS_GPIO0D0_SUS_SHIFT) /* 0x00000001 */ +#define GRF_GPIO0D_SUS_GPIO0D1_SUS_SHIFT (1U) +#define GRF_GPIO0D_SUS_GPIO0D1_SUS_MASK (0x1U << GRF_GPIO0D_SUS_GPIO0D1_SUS_SHIFT) /* 0x00000002 */ +/* GPIO0A_SL */ +#define GRF_GPIO0A_SL_OFFSET (0x60U) +#define GRF_GPIO0A_SL_GPIO0A0_SL_SHIFT (0U) +#define GRF_GPIO0A_SL_GPIO0A0_SL_MASK (0x3U << GRF_GPIO0A_SL_GPIO0A0_SL_SHIFT) /* 0x00000003 */ +#define GRF_GPIO0A_SL_GPIO0A1_SL_SHIFT (2U) +#define GRF_GPIO0A_SL_GPIO0A1_SL_MASK (0x3U << GRF_GPIO0A_SL_GPIO0A1_SL_SHIFT) /* 0x0000000C */ +#define GRF_GPIO0A_SL_GPIO0A2_SL_SHIFT (4U) +#define GRF_GPIO0A_SL_GPIO0A2_SL_MASK (0x3U << GRF_GPIO0A_SL_GPIO0A2_SL_SHIFT) /* 0x00000030 */ +#define GRF_GPIO0A_SL_GPIO0A3_SL_SHIFT (6U) +#define GRF_GPIO0A_SL_GPIO0A3_SL_MASK (0x3U << GRF_GPIO0A_SL_GPIO0A3_SL_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO0A_SL_GPIO0A4_SL_SHIFT (8U) +#define GRF_GPIO0A_SL_GPIO0A4_SL_MASK (0x3U << GRF_GPIO0A_SL_GPIO0A4_SL_SHIFT) /* 0x00000300 */ +#define GRF_GPIO0A_SL_GPIO0A5_SL_SHIFT (10U) +#define GRF_GPIO0A_SL_GPIO0A5_SL_MASK (0x3U << GRF_GPIO0A_SL_GPIO0A5_SL_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO0A_SL_GPIO0A6_SL_SHIFT (12U) +#define GRF_GPIO0A_SL_GPIO0A6_SL_MASK (0x3U << GRF_GPIO0A_SL_GPIO0A6_SL_SHIFT) /* 0x00003000 */ +#define GRF_GPIO0A_SL_GPIO0A7_SL_SHIFT (14U) +#define GRF_GPIO0A_SL_GPIO0A7_SL_MASK (0x3U << GRF_GPIO0A_SL_GPIO0A7_SL_SHIFT) /* 0x0000C000 */ +/* GPIO0B_SL */ +#define GRF_GPIO0B_SL_OFFSET (0x64U) +#define GRF_GPIO0B_SL_GPIO0B0_SL_SHIFT (0U) +#define GRF_GPIO0B_SL_GPIO0B0_SL_MASK (0x3U << GRF_GPIO0B_SL_GPIO0B0_SL_SHIFT) /* 0x00000003 */ +#define GRF_GPIO0B_SL_GPIO0B1_SL_SHIFT (2U) +#define GRF_GPIO0B_SL_GPIO0B1_SL_MASK (0x3U << GRF_GPIO0B_SL_GPIO0B1_SL_SHIFT) /* 0x0000000C */ +#define GRF_GPIO0B_SL_GPIO0B2_SL_SHIFT (4U) +#define GRF_GPIO0B_SL_GPIO0B2_SL_MASK (0x3U << GRF_GPIO0B_SL_GPIO0B2_SL_SHIFT) /* 0x00000030 */ +#define GRF_GPIO0B_SL_GPIO0B3_SL_SHIFT (6U) +#define GRF_GPIO0B_SL_GPIO0B3_SL_MASK (0x3U << GRF_GPIO0B_SL_GPIO0B3_SL_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO0B_SL_GPIO0B4_SL_SHIFT (8U) +#define GRF_GPIO0B_SL_GPIO0B4_SL_MASK (0x3U << GRF_GPIO0B_SL_GPIO0B4_SL_SHIFT) /* 0x00000300 */ +#define GRF_GPIO0B_SL_GPIO0B5_SL_SHIFT (10U) +#define GRF_GPIO0B_SL_GPIO0B5_SL_MASK (0x3U << GRF_GPIO0B_SL_GPIO0B5_SL_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO0B_SL_GPIO0B6_SL_SHIFT (12U) +#define GRF_GPIO0B_SL_GPIO0B6_SL_MASK (0x3U << GRF_GPIO0B_SL_GPIO0B6_SL_SHIFT) /* 0x00003000 */ +#define GRF_GPIO0B_SL_GPIO0B7_SL_SHIFT (14U) +#define GRF_GPIO0B_SL_GPIO0B7_SL_MASK (0x3U << GRF_GPIO0B_SL_GPIO0B7_SL_SHIFT) /* 0x0000C000 */ +/* GPIO0C_SL */ +#define GRF_GPIO0C_SL_OFFSET (0x68U) +#define GRF_GPIO0C_SL_GPIO0C0_SL_SHIFT (0U) +#define GRF_GPIO0C_SL_GPIO0C0_SL_MASK (0x3U << GRF_GPIO0C_SL_GPIO0C0_SL_SHIFT) /* 0x00000003 */ +#define GRF_GPIO0C_SL_GPIO0C1_SL_SHIFT (2U) +#define GRF_GPIO0C_SL_GPIO0C1_SL_MASK (0x3U << GRF_GPIO0C_SL_GPIO0C1_SL_SHIFT) /* 0x0000000C */ +#define GRF_GPIO0C_SL_GPIO0C2_SL_SHIFT (4U) +#define GRF_GPIO0C_SL_GPIO0C2_SL_MASK (0x3U << GRF_GPIO0C_SL_GPIO0C2_SL_SHIFT) /* 0x00000030 */ +#define GRF_GPIO0C_SL_GPIO0C3_SL_SHIFT (6U) +#define GRF_GPIO0C_SL_GPIO0C3_SL_MASK (0x3U << GRF_GPIO0C_SL_GPIO0C3_SL_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO0C_SL_GPIO0C4_SL_SHIFT (8U) +#define GRF_GPIO0C_SL_GPIO0C4_SL_MASK (0x3U << GRF_GPIO0C_SL_GPIO0C4_SL_SHIFT) /* 0x00000300 */ +#define GRF_GPIO0C_SL_GPIO0C5_SL_SHIFT (10U) +#define GRF_GPIO0C_SL_GPIO0C5_SL_MASK (0x3U << GRF_GPIO0C_SL_GPIO0C5_SL_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO0C_SL_GPIO0C6_SL_SHIFT (12U) +#define GRF_GPIO0C_SL_GPIO0C6_SL_MASK (0x3U << GRF_GPIO0C_SL_GPIO0C6_SL_SHIFT) /* 0x00003000 */ +#define GRF_GPIO0C_SL_GPIO0C7_SL_SHIFT (14U) +#define GRF_GPIO0C_SL_GPIO0C7_SL_MASK (0x3U << GRF_GPIO0C_SL_GPIO0C7_SL_SHIFT) /* 0x0000C000 */ +/* GPIO0D_SL */ +#define GRF_GPIO0D_SL_OFFSET (0x6CU) +#define GRF_GPIO0D_SL_GPIO0D0_SL_SHIFT (0U) +#define GRF_GPIO0D_SL_GPIO0D0_SL_MASK (0x3U << GRF_GPIO0D_SL_GPIO0D0_SL_SHIFT) /* 0x00000003 */ +#define GRF_GPIO0D_SL_GPIO0D1_SL_SHIFT (2U) +#define GRF_GPIO0D_SL_GPIO0D1_SL_MASK (0x3U << GRF_GPIO0D_SL_GPIO0D1_SL_SHIFT) /* 0x0000000C */ +#define GRF_GPIO0D_SL_GPIO0D2_SL_SHIFT (4U) +#define GRF_GPIO0D_SL_GPIO0D2_SL_MASK (0x3U << GRF_GPIO0D_SL_GPIO0D2_SL_SHIFT) /* 0x00000030 */ +#define GRF_GPIO0D_SL_GPIO0D3_SL_SHIFT (6U) +#define GRF_GPIO0D_SL_GPIO0D3_SL_MASK (0x3U << GRF_GPIO0D_SL_GPIO0D3_SL_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO0D_SL_GPIO0D4_SL_SHIFT (8U) +#define GRF_GPIO0D_SL_GPIO0D4_SL_MASK (0x3U << GRF_GPIO0D_SL_GPIO0D4_SL_SHIFT) /* 0x00000300 */ +#define GRF_GPIO0D_SL_GPIO0D5_SL_SHIFT (10U) +#define GRF_GPIO0D_SL_GPIO0D5_SL_MASK (0x3U << GRF_GPIO0D_SL_GPIO0D5_SL_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO0D_SL_GPIO0D6_SL_SHIFT (12U) +#define GRF_GPIO0D_SL_GPIO0D6_SL_MASK (0x3U << GRF_GPIO0D_SL_GPIO0D6_SL_SHIFT) /* 0x00003000 */ +#define GRF_GPIO0D_SL_GPIO0D7_SL_SHIFT (14U) +#define GRF_GPIO0D_SL_GPIO0D7_SL_MASK (0x3U << GRF_GPIO0D_SL_GPIO0D7_SL_SHIFT) /* 0x0000C000 */ +/* GPIO0A_DS_0 */ +#define GRF_GPIO0A_DS_0_OFFSET (0x70U) +#define GRF_GPIO0A_DS_0_GPIO0A0_DS_SHIFT (0U) +#define GRF_GPIO0A_DS_0_GPIO0A0_DS_MASK (0x3FU << GRF_GPIO0A_DS_0_GPIO0A0_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO0A_DS_0_GPIO0A1_DS_SHIFT (8U) +#define GRF_GPIO0A_DS_0_GPIO0A1_DS_MASK (0x3FU << GRF_GPIO0A_DS_0_GPIO0A1_DS_SHIFT) /* 0x00003F00 */ +/* GPIO0A_DS_1 */ +#define GRF_GPIO0A_DS_1_OFFSET (0x74U) +#define GRF_GPIO0A_DS_1_GPIO0A2_DS_SHIFT (0U) +#define GRF_GPIO0A_DS_1_GPIO0A2_DS_MASK (0x3FU << GRF_GPIO0A_DS_1_GPIO0A2_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO0A_DS_1_GPIO0A3_DS_SHIFT (8U) +#define GRF_GPIO0A_DS_1_GPIO0A3_DS_MASK (0x3FU << GRF_GPIO0A_DS_1_GPIO0A3_DS_SHIFT) /* 0x00003F00 */ +/* GPIO0A_DS_2 */ +#define GRF_GPIO0A_DS_2_OFFSET (0x78U) +#define GRF_GPIO0A_DS_2_GPIO0A4_DS_SHIFT (0U) +#define GRF_GPIO0A_DS_2_GPIO0A4_DS_MASK (0x3FU << GRF_GPIO0A_DS_2_GPIO0A4_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO0A_DS_2_GPIO0A5_DS_SHIFT (8U) +#define GRF_GPIO0A_DS_2_GPIO0A5_DS_MASK (0x3FU << GRF_GPIO0A_DS_2_GPIO0A5_DS_SHIFT) /* 0x00003F00 */ +/* GPIO0A_DS_3 */ +#define GRF_GPIO0A_DS_3_OFFSET (0x7CU) +#define GRF_GPIO0A_DS_3_GPIO0A6_DS_SHIFT (0U) +#define GRF_GPIO0A_DS_3_GPIO0A6_DS_MASK (0x3FU << GRF_GPIO0A_DS_3_GPIO0A6_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO0A_DS_3_GPIO0A7_DS_SHIFT (8U) +#define GRF_GPIO0A_DS_3_GPIO0A7_DS_MASK (0x3FU << GRF_GPIO0A_DS_3_GPIO0A7_DS_SHIFT) /* 0x00003F00 */ +/* GPIO0B_DS_0 */ +#define GRF_GPIO0B_DS_0_OFFSET (0x80U) +#define GRF_GPIO0B_DS_0_GPIO0B0_DS_SHIFT (0U) +#define GRF_GPIO0B_DS_0_GPIO0B0_DS_MASK (0x3FU << GRF_GPIO0B_DS_0_GPIO0B0_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO0B_DS_0_GPIO0B1_DS_SHIFT (8U) +#define GRF_GPIO0B_DS_0_GPIO0B1_DS_MASK (0x3FU << GRF_GPIO0B_DS_0_GPIO0B1_DS_SHIFT) /* 0x00003F00 */ +/* GPIO0B_DS_1 */ +#define GRF_GPIO0B_DS_1_OFFSET (0x84U) +#define GRF_GPIO0B_DS_1_GPIO0B2_DS_SHIFT (0U) +#define GRF_GPIO0B_DS_1_GPIO0B2_DS_MASK (0x3FU << GRF_GPIO0B_DS_1_GPIO0B2_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO0B_DS_1_GPIO0B3_DS_SHIFT (8U) +#define GRF_GPIO0B_DS_1_GPIO0B3_DS_MASK (0x3FU << GRF_GPIO0B_DS_1_GPIO0B3_DS_SHIFT) /* 0x00003F00 */ +/* GPIO0B_DS_2 */ +#define GRF_GPIO0B_DS_2_OFFSET (0x88U) +#define GRF_GPIO0B_DS_2_GPIO0B4_DS_SHIFT (0U) +#define GRF_GPIO0B_DS_2_GPIO0B4_DS_MASK (0x3FU << GRF_GPIO0B_DS_2_GPIO0B4_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO0B_DS_2_GPIO0B5_DS_SHIFT (8U) +#define GRF_GPIO0B_DS_2_GPIO0B5_DS_MASK (0x3FU << GRF_GPIO0B_DS_2_GPIO0B5_DS_SHIFT) /* 0x00003F00 */ +/* GPIO0B_DS_3 */ +#define GRF_GPIO0B_DS_3_OFFSET (0x8CU) +#define GRF_GPIO0B_DS_3_GPIO0B6_DS_SHIFT (0U) +#define GRF_GPIO0B_DS_3_GPIO0B6_DS_MASK (0x3FU << GRF_GPIO0B_DS_3_GPIO0B6_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO0B_DS_3_GPIO0B7_DS_SHIFT (8U) +#define GRF_GPIO0B_DS_3_GPIO0B7_DS_MASK (0x3FU << GRF_GPIO0B_DS_3_GPIO0B7_DS_SHIFT) /* 0x00003F00 */ +/* GPIO0C_DS_0 */ +#define GRF_GPIO0C_DS_0_OFFSET (0x90U) +#define GRF_GPIO0C_DS_0_GPIO0C0_DS_SHIFT (0U) +#define GRF_GPIO0C_DS_0_GPIO0C0_DS_MASK (0x3FU << GRF_GPIO0C_DS_0_GPIO0C0_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO0C_DS_0_GPIO0C1_DS_SHIFT (8U) +#define GRF_GPIO0C_DS_0_GPIO0C1_DS_MASK (0x3FU << GRF_GPIO0C_DS_0_GPIO0C1_DS_SHIFT) /* 0x00003F00 */ +/* GPIO0C_DS_1 */ +#define GRF_GPIO0C_DS_1_OFFSET (0x94U) +#define GRF_GPIO0C_DS_1_GPIO0C2_DS_SHIFT (0U) +#define GRF_GPIO0C_DS_1_GPIO0C2_DS_MASK (0x3FU << GRF_GPIO0C_DS_1_GPIO0C2_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO0C_DS_1_GPIO0C3_DS_SHIFT (8U) +#define GRF_GPIO0C_DS_1_GPIO0C3_DS_MASK (0x3FU << GRF_GPIO0C_DS_1_GPIO0C3_DS_SHIFT) /* 0x00003F00 */ +/* GPIO0C_DS_2 */ +#define GRF_GPIO0C_DS_2_OFFSET (0x98U) +#define GRF_GPIO0C_DS_2_GPIO0C4_DS_SHIFT (0U) +#define GRF_GPIO0C_DS_2_GPIO0C4_DS_MASK (0x3FU << GRF_GPIO0C_DS_2_GPIO0C4_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO0C_DS_2_GPIO0C5_DS_SHIFT (8U) +#define GRF_GPIO0C_DS_2_GPIO0C5_DS_MASK (0x3FU << GRF_GPIO0C_DS_2_GPIO0C5_DS_SHIFT) /* 0x00003F00 */ +/* GPIO0C_DS_3 */ +#define GRF_GPIO0C_DS_3_OFFSET (0x9CU) +#define GRF_GPIO0C_DS_3_GPIO0C6_DS_SHIFT (0U) +#define GRF_GPIO0C_DS_3_GPIO0C6_DS_MASK (0x3FU << GRF_GPIO0C_DS_3_GPIO0C6_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO0C_DS_3_GPIO0C7_DS_SHIFT (8U) +#define GRF_GPIO0C_DS_3_GPIO0C7_DS_MASK (0x3FU << GRF_GPIO0C_DS_3_GPIO0C7_DS_SHIFT) /* 0x00003F00 */ +/* GPIO0D_DS_0 */ +#define GRF_GPIO0D_DS_0_OFFSET (0xA0U) +#define GRF_GPIO0D_DS_0_GPIO0D0_DS_SHIFT (0U) +#define GRF_GPIO0D_DS_0_GPIO0D0_DS_MASK (0x3FU << GRF_GPIO0D_DS_0_GPIO0D0_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO0D_DS_0_GPIO0D1_DS_SHIFT (8U) +#define GRF_GPIO0D_DS_0_GPIO0D1_DS_MASK (0x3FU << GRF_GPIO0D_DS_0_GPIO0D1_DS_SHIFT) /* 0x00003F00 */ +/* SOC_CON0 */ +#define GRF_SOC_CON0_OFFSET (0x100U) +#define GRF_SOC_CON0_CON_32K_IOE_SHIFT (0U) +#define GRF_SOC_CON0_CON_32K_IOE_MASK (0x1U << GRF_SOC_CON0_CON_32K_IOE_SHIFT) /* 0x00000001 */ +#define GRF_SOC_CON0_I2C0_IOMUX_SEL_SHIFT (1U) +#define GRF_SOC_CON0_I2C0_IOMUX_SEL_MASK (0x1U << GRF_SOC_CON0_I2C0_IOMUX_SEL_SHIFT) /* 0x00000002 */ +#define GRF_SOC_CON0_APLL_OSC_SOURCE_SEL_SHIFT (2U) +#define GRF_SOC_CON0_APLL_OSC_SOURCE_SEL_MASK (0x1U << GRF_SOC_CON0_APLL_OSC_SOURCE_SEL_SHIFT) /* 0x00000004 */ +#define GRF_SOC_CON0_DPLL_OSC_SOURCE_SEL_SHIFT (3U) +#define GRF_SOC_CON0_DPLL_OSC_SOURCE_SEL_MASK (0x1U << GRF_SOC_CON0_DPLL_OSC_SOURCE_SEL_SHIFT) /* 0x00000008 */ +#define GRF_SOC_CON0_UART0_RTS_SEL_SHIFT (5U) +#define GRF_SOC_CON0_UART0_RTS_SEL_MASK (0x1U << GRF_SOC_CON0_UART0_RTS_SEL_SHIFT) /* 0x00000020 */ +#define GRF_SOC_CON0_UART0_CTS_SEL_SHIFT (6U) +#define GRF_SOC_CON0_UART0_CTS_SEL_MASK (0x1U << GRF_SOC_CON0_UART0_CTS_SEL_SHIFT) /* 0x00000040 */ +#define GRF_SOC_CON0_GRF_CON_PMIC_SLEEP_SEL_SHIFT (7U) +#define GRF_SOC_CON0_GRF_CON_PMIC_SLEEP_SEL_MASK (0x1U << GRF_SOC_CON0_GRF_CON_PMIC_SLEEP_SEL_SHIFT) /* 0x00000080 */ +#define GRF_SOC_CON0_DDRPHY_BUFFEREN_SEL_SHIFT (12U) +#define GRF_SOC_CON0_DDRPHY_BUFFEREN_SEL_MASK (0x1U << GRF_SOC_CON0_DDRPHY_BUFFEREN_SEL_SHIFT) /* 0x00001000 */ +#define GRF_SOC_CON0_DDRPHY_BUFFEREN_CORE_SHIFT (13U) +#define GRF_SOC_CON0_DDRPHY_BUFFEREN_CORE_MASK (0x1U << GRF_SOC_CON0_DDRPHY_BUFFEREN_CORE_SHIFT) /* 0x00002000 */ +#define GRF_SOC_CON0_PVTM_FRQ_DONE_SHIFT (14U) +#define GRF_SOC_CON0_PVTM_FRQ_DONE_MASK (0x1U << GRF_SOC_CON0_PVTM_FRQ_DONE_SHIFT) /* 0x00004000 */ +/* SOC_CON1 */ +#define GRF_SOC_CON1_OFFSET (0x104U) +#define GRF_SOC_CON1_RESETN_HOLD_SHIFT (0U) +#define GRF_SOC_CON1_RESETN_HOLD_MASK (0xFFFFU << GRF_SOC_CON1_RESETN_HOLD_SHIFT) /* 0x0000FFFF */ +/* SOC_CON2 */ +#define GRF_SOC_CON2_OFFSET (0x108U) +#define GRF_SOC_CON2_RESETN_HOLD_SHIFT (0U) +#define GRF_SOC_CON2_RESETN_HOLD_MASK (0xFFU << GRF_SOC_CON2_RESETN_HOLD_SHIFT) /* 0x000000FF */ +/* SOC_CON3 */ +#define GRF_SOC_CON3_OFFSET (0x10CU) +#define GRF_SOC_CON3_TSADC_SHUT_RESET_TRIGGER_EN_SHIFT (0U) +#define GRF_SOC_CON3_TSADC_SHUT_RESET_TRIGGER_EN_MASK (0x1U << GRF_SOC_CON3_TSADC_SHUT_RESET_TRIGGER_EN_SHIFT) /* 0x00000001 */ +#define GRF_SOC_CON3_WDT_SHUT_RESET_TRIGGER_EN_SHIFT (1U) +#define GRF_SOC_CON3_WDT_SHUT_RESET_TRIGGER_EN_MASK (0x1U << GRF_SOC_CON3_WDT_SHUT_RESET_TRIGGER_EN_SHIFT) /* 0x00000002 */ +#define GRF_SOC_CON3_DDRIO_RET_EN_SHIFT (2U) +#define GRF_SOC_CON3_DDRIO_RET_EN_MASK (0x1U << GRF_SOC_CON3_DDRIO_RET_EN_SHIFT) /* 0x00000004 */ +#define GRF_SOC_CON3_SREF_ENTER_EN_SHIFT (3U) +#define GRF_SOC_CON3_SREF_ENTER_EN_MASK (0x1U << GRF_SOC_CON3_SREF_ENTER_EN_SHIFT) /* 0x00000008 */ +#define GRF_SOC_CON3_DDRC_GATING_EN_SHIFT (4U) +#define GRF_SOC_CON3_DDRC_GATING_EN_MASK (0x1U << GRF_SOC_CON3_DDRC_GATING_EN_SHIFT) /* 0x00000010 */ +#define GRF_SOC_CON3_DDR_IO_RET_DE_REQ_SHIFT (5U) +#define GRF_SOC_CON3_DDR_IO_RET_DE_REQ_MASK (0x1U << GRF_SOC_CON3_DDR_IO_RET_DE_REQ_SHIFT) /* 0x00000020 */ +#define GRF_SOC_CON3_DDR_IO_RET_CFG_SHIFT (6U) +#define GRF_SOC_CON3_DDR_IO_RET_CFG_MASK (0x1U << GRF_SOC_CON3_DDR_IO_RET_CFG_SHIFT) /* 0x00000040 */ +#define GRF_SOC_CON3_DDR_IO_RET_OEN_CFG_SHIFT (7U) +#define GRF_SOC_CON3_DDR_IO_RET_OEN_CFG_MASK (0x1U << GRF_SOC_CON3_DDR_IO_RET_OEN_CFG_SHIFT) /* 0x00000080 */ +#define GRF_SOC_CON3_UPCTL_C_SYSREQ_CFG_SHIFT (8U) +#define GRF_SOC_CON3_UPCTL_C_SYSREQ_CFG_MASK (0x1U << GRF_SOC_CON3_UPCTL_C_SYSREQ_CFG_SHIFT) /* 0x00000100 */ +#define GRF_SOC_CON3_CORE_WFI_EN_SHIFT (9U) +#define GRF_SOC_CON3_CORE_WFI_EN_MASK (0x1U << GRF_SOC_CON3_CORE_WFI_EN_SHIFT) /* 0x00000200 */ +#define GRF_SOC_CON3_CORE_OFF_EN_SHIFT (10U) +#define GRF_SOC_CON3_CORE_OFF_EN_MASK (0x1U << GRF_SOC_CON3_CORE_OFF_EN_SHIFT) /* 0x00000400 */ +#define GRF_SOC_CON3_CORE_RET_EN_SHIFT (11U) +#define GRF_SOC_CON3_CORE_RET_EN_MASK (0x1U << GRF_SOC_CON3_CORE_RET_EN_SHIFT) /* 0x00000800 */ +#define GRF_SOC_CON3_CORE_PACTIVE_EN_SHIFT (12U) +#define GRF_SOC_CON3_CORE_PACTIVE_EN_MASK (0x1U << GRF_SOC_CON3_CORE_PACTIVE_EN_SHIFT) /* 0x00001000 */ +#define GRF_SOC_CON3_DSU_OFF_EN_SHIFT (13U) +#define GRF_SOC_CON3_DSU_OFF_EN_MASK (0x1U << GRF_SOC_CON3_DSU_OFF_EN_SHIFT) /* 0x00002000 */ +#define GRF_SOC_CON3_DSU_RET_EN_SHIFT (14U) +#define GRF_SOC_CON3_DSU_RET_EN_MASK (0x1U << GRF_SOC_CON3_DSU_RET_EN_SHIFT) /* 0x00004000 */ +#define GRF_SOC_CON3_DSU_PACTIVE_EN_SHIFT (15U) +#define GRF_SOC_CON3_DSU_PACTIVE_EN_MASK (0x1U << GRF_SOC_CON3_DSU_PACTIVE_EN_SHIFT) /* 0x00008000 */ +/* SOC_CON4 */ +#define GRF_SOC_CON4_OFFSET (0x110U) +#define GRF_SOC_CON4_PWM0_IOMUX_SEL_SHIFT (0U) +#define GRF_SOC_CON4_PWM0_IOMUX_SEL_MASK (0x3U << GRF_SOC_CON4_PWM0_IOMUX_SEL_SHIFT) /* 0x00000003 */ +#define GRF_SOC_CON4_PWM1_IOMUX_SEL_SHIFT (2U) +#define GRF_SOC_CON4_PWM1_IOMUX_SEL_MASK (0x3U << GRF_SOC_CON4_PWM1_IOMUX_SEL_SHIFT) /* 0x0000000C */ +#define GRF_SOC_CON4_PWM2_IOMUX_SEL_SHIFT (4U) +#define GRF_SOC_CON4_PWM2_IOMUX_SEL_MASK (0x3U << GRF_SOC_CON4_PWM2_IOMUX_SEL_SHIFT) /* 0x00000030 */ +#define GRF_SOC_CON4_GPU_PWREN_POL_SHIFT (10U) +#define GRF_SOC_CON4_GPU_PWREN_POL_MASK (0x3U << GRF_SOC_CON4_GPU_PWREN_POL_SHIFT) /* 0x00000C00 */ +#define GRF_SOC_CON4_SPRA_HD_WTSEL_SHIFT (12U) +#define GRF_SOC_CON4_SPRA_HD_WTSEL_MASK (0x3U << GRF_SOC_CON4_SPRA_HD_WTSEL_SHIFT) /* 0x00003000 */ +#define GRF_SOC_CON4_SPRA_HD_RTSEL_SHIFT (14U) +#define GRF_SOC_CON4_SPRA_HD_RTSEL_MASK (0x3U << GRF_SOC_CON4_SPRA_HD_RTSEL_SHIFT) /* 0x0000C000 */ +/* SOC_CON5 */ +#define GRF_SOC_CON5_OFFSET (0x114U) +#define GRF_SOC_CON5_OUT2CHIP_RST_INIT_SHIFT (0U) +#define GRF_SOC_CON5_OUT2CHIP_RST_INIT_MASK (0x1FFFU << GRF_SOC_CON5_OUT2CHIP_RST_INIT_SHIFT) /* 0x00001FFF */ +/* SOC_STATUS */ +#define GRF_SOC_STATUS_OFFSET (0x120U) +#define GRF_SOC_STATUS (0x0U) +#define GRF_SOC_STATUS_WFI_STATUS_SHIFT (0U) +#define GRF_SOC_STATUS_WFI_STATUS_MASK (0xFU << GRF_SOC_STATUS_WFI_STATUS_SHIFT) /* 0x0000000F */ +/* IO_VSEL0 */ +#define GRF_IO_VSEL0_OFFSET (0x140U) +#define GRF_IO_VSEL0_VCCIO2_VOLTAGE_CONTROL_SELECT_SHIFT (0U) +#define GRF_IO_VSEL0_VCCIO2_VOLTAGE_CONTROL_SELECT_MASK (0x1U << GRF_IO_VSEL0_VCCIO2_VOLTAGE_CONTROL_SELECT_SHIFT) /* 0x00000001 */ +#define GRF_IO_VSEL0_POC_VCCIO1_SEL18_SHIFT (1U) +#define GRF_IO_VSEL0_POC_VCCIO1_SEL18_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO1_SEL18_SHIFT) /* 0x00000002 */ +#define GRF_IO_VSEL0_POC_VCCIO2_SEL18_SHIFT (2U) +#define GRF_IO_VSEL0_POC_VCCIO2_SEL18_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO2_SEL18_SHIFT) /* 0x00000004 */ +#define GRF_IO_VSEL0_POC_VCCIO3_SEL18_SHIFT (3U) +#define GRF_IO_VSEL0_POC_VCCIO3_SEL18_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO3_SEL18_SHIFT) /* 0x00000008 */ +#define GRF_IO_VSEL0_POC_VCCIO4_SEL18_SHIFT (4U) +#define GRF_IO_VSEL0_POC_VCCIO4_SEL18_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO4_SEL18_SHIFT) /* 0x00000010 */ +#define GRF_IO_VSEL0_POC_VCCIO5_SEL18_SHIFT (5U) +#define GRF_IO_VSEL0_POC_VCCIO5_SEL18_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO5_SEL18_SHIFT) /* 0x00000020 */ +#define GRF_IO_VSEL0_POC_VCCIO6_SEL18_SHIFT (6U) +#define GRF_IO_VSEL0_POC_VCCIO6_SEL18_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO6_SEL18_SHIFT) /* 0x00000040 */ +#define GRF_IO_VSEL0_POC_VCCIO7_SEL18_SHIFT (7U) +#define GRF_IO_VSEL0_POC_VCCIO7_SEL18_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO7_SEL18_SHIFT) /* 0x00000080 */ +#define GRF_IO_VSEL0_POC_VCCIO1_SEL25_SHIFT (8U) +#define GRF_IO_VSEL0_POC_VCCIO1_SEL25_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO1_SEL25_SHIFT) /* 0x00000100 */ +#define GRF_IO_VSEL0_POC_VCCIO2_SEL25_SHIFT (9U) +#define GRF_IO_VSEL0_POC_VCCIO2_SEL25_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO2_SEL25_SHIFT) /* 0x00000200 */ +#define GRF_IO_VSEL0_POC_VCCIO3_SEL25_SHIFT (10U) +#define GRF_IO_VSEL0_POC_VCCIO3_SEL25_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO3_SEL25_SHIFT) /* 0x00000400 */ +#define GRF_IO_VSEL0_POC_VCCIO4_SEL25_SHIFT (11U) +#define GRF_IO_VSEL0_POC_VCCIO4_SEL25_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO4_SEL25_SHIFT) /* 0x00000800 */ +#define GRF_IO_VSEL0_POC_VCCIO5_SEL25_SHIFT (12U) +#define GRF_IO_VSEL0_POC_VCCIO5_SEL25_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO5_SEL25_SHIFT) /* 0x00001000 */ +#define GRF_IO_VSEL0_POC_VCCIO6_SEL25_SHIFT (13U) +#define GRF_IO_VSEL0_POC_VCCIO6_SEL25_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO6_SEL25_SHIFT) /* 0x00002000 */ +#define GRF_IO_VSEL0_POC_VCCIO7_SEL25_SHIFT (14U) +#define GRF_IO_VSEL0_POC_VCCIO7_SEL25_MASK (0x1U << GRF_IO_VSEL0_POC_VCCIO7_SEL25_SHIFT) /* 0x00004000 */ +/* IO_VSEL1 */ +#define GRF_IO_VSEL1_OFFSET (0x144U) +#define GRF_IO_VSEL1_POC_VCCIO1_SEL33_SHIFT (1U) +#define GRF_IO_VSEL1_POC_VCCIO1_SEL33_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO1_SEL33_SHIFT) /* 0x00000002 */ +#define GRF_IO_VSEL1_POC_VCCIO2_SEL33_SHIFT (2U) +#define GRF_IO_VSEL1_POC_VCCIO2_SEL33_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO2_SEL33_SHIFT) /* 0x00000004 */ +#define GRF_IO_VSEL1_POC_VCCIO3_SEL33_SHIFT (3U) +#define GRF_IO_VSEL1_POC_VCCIO3_SEL33_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO3_SEL33_SHIFT) /* 0x00000008 */ +#define GRF_IO_VSEL1_POC_VCCIO4_SEL33_SHIFT (4U) +#define GRF_IO_VSEL1_POC_VCCIO4_SEL33_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO4_SEL33_SHIFT) /* 0x00000010 */ +#define GRF_IO_VSEL1_POC_VCCIO5_SEL33_SHIFT (5U) +#define GRF_IO_VSEL1_POC_VCCIO5_SEL33_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO5_SEL33_SHIFT) /* 0x00000020 */ +#define GRF_IO_VSEL1_POC_VCCIO6_SEL33_SHIFT (6U) +#define GRF_IO_VSEL1_POC_VCCIO6_SEL33_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO6_SEL33_SHIFT) /* 0x00000040 */ +#define GRF_IO_VSEL1_POC_VCCIO7_SEL33_SHIFT (7U) +#define GRF_IO_VSEL1_POC_VCCIO7_SEL33_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO7_SEL33_SHIFT) /* 0x00000080 */ +#define GRF_IO_VSEL1_POC_VCCIO1_IDDQ_SHIFT (8U) +#define GRF_IO_VSEL1_POC_VCCIO1_IDDQ_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO1_IDDQ_SHIFT) /* 0x00000100 */ +#define GRF_IO_VSEL1_POC_VCCIO2_IDDQ_SHIFT (9U) +#define GRF_IO_VSEL1_POC_VCCIO2_IDDQ_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO2_IDDQ_SHIFT) /* 0x00000200 */ +#define GRF_IO_VSEL1_POC_VCCIO3_IDDQ_SHIFT (10U) +#define GRF_IO_VSEL1_POC_VCCIO3_IDDQ_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO3_IDDQ_SHIFT) /* 0x00000400 */ +#define GRF_IO_VSEL1_POC_VCCIO4_IDDQ_SHIFT (11U) +#define GRF_IO_VSEL1_POC_VCCIO4_IDDQ_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO4_IDDQ_SHIFT) /* 0x00000800 */ +#define GRF_IO_VSEL1_POC_VCCIO5_IDDQ_SHIFT (12U) +#define GRF_IO_VSEL1_POC_VCCIO5_IDDQ_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO5_IDDQ_SHIFT) /* 0x00001000 */ +#define GRF_IO_VSEL1_POC_VCCIO6_IDDQ_SHIFT (13U) +#define GRF_IO_VSEL1_POC_VCCIO6_IDDQ_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO6_IDDQ_SHIFT) /* 0x00002000 */ +#define GRF_IO_VSEL1_POC_VCCIO7_IDDQ_SHIFT (14U) +#define GRF_IO_VSEL1_POC_VCCIO7_IDDQ_MASK (0x1U << GRF_IO_VSEL1_POC_VCCIO7_IDDQ_SHIFT) /* 0x00004000 */ +/* IO_VSEL2 */ +#define GRF_IO_VSEL2_OFFSET (0x148U) +#define GRF_IO_VSEL2_POC_PMUIO2_SEL18_SHIFT (1U) +#define GRF_IO_VSEL2_POC_PMUIO2_SEL18_MASK (0x1U << GRF_IO_VSEL2_POC_PMUIO2_SEL18_SHIFT) /* 0x00000002 */ +#define GRF_IO_VSEL2_POC_PMUIO2_SEL25_SHIFT (3U) +#define GRF_IO_VSEL2_POC_PMUIO2_SEL25_MASK (0x1U << GRF_IO_VSEL2_POC_PMUIO2_SEL25_SHIFT) /* 0x00000008 */ +#define GRF_IO_VSEL2_POC_PMUIO2_SEL33_SHIFT (5U) +#define GRF_IO_VSEL2_POC_PMUIO2_SEL33_MASK (0x1U << GRF_IO_VSEL2_POC_PMUIO2_SEL33_SHIFT) /* 0x00000020 */ +#define GRF_IO_VSEL2_POC_PMUIO1_IDDQ_SHIFT (6U) +#define GRF_IO_VSEL2_POC_PMUIO1_IDDQ_MASK (0x1U << GRF_IO_VSEL2_POC_PMUIO1_IDDQ_SHIFT) /* 0x00000040 */ +#define GRF_IO_VSEL2_POC_PMUIO2_IDDQ_SHIFT (7U) +#define GRF_IO_VSEL2_POC_PMUIO2_IDDQ_MASK (0x1U << GRF_IO_VSEL2_POC_PMUIO2_IDDQ_SHIFT) /* 0x00000080 */ +/* DLL_CON0 */ +#define GRF_DLL_CON0_OFFSET (0x180U) +#define GRF_DLL_CON0_PVTM_CLKOUT_DIV_SHIFT (0U) +#define GRF_DLL_CON0_PVTM_CLKOUT_DIV_MASK (0xFFFU << GRF_DLL_CON0_PVTM_CLKOUT_DIV_SHIFT) /* 0x00000FFF */ +/* OS_REG0 */ +#define GRF_OS_REG0_OFFSET (0x200U) +#define GRF_OS_REG0_PMU_OS_REG0_SHIFT (0U) +#define GRF_OS_REG0_PMU_OS_REG0_MASK (0xFFFFFFFFU << GRF_OS_REG0_PMU_OS_REG0_SHIFT) /* 0xFFFFFFFF */ +/* OS_REG1 */ +#define GRF_OS_REG1_OFFSET (0x204U) +#define GRF_OS_REG1_PMU_OS_REG1_SHIFT (0U) +#define GRF_OS_REG1_PMU_OS_REG1_MASK (0xFFFFFFFFU << GRF_OS_REG1_PMU_OS_REG1_SHIFT) /* 0xFFFFFFFF */ +/* OS_REG2 */ +#define GRF_OS_REG2_OFFSET (0x208U) +#define GRF_OS_REG2_PMU_OS_REG2_SHIFT (0U) +#define GRF_OS_REG2_PMU_OS_REG2_MASK (0xFFFFFFFFU << GRF_OS_REG2_PMU_OS_REG2_SHIFT) /* 0xFFFFFFFF */ +/* OS_REG3 */ +#define GRF_OS_REG3_OFFSET (0x20CU) +#define GRF_OS_REG3_PMU_OS_REG3_SHIFT (0U) +#define GRF_OS_REG3_PMU_OS_REG3_MASK (0xFFFFFFFFU << GRF_OS_REG3_PMU_OS_REG3_SHIFT) /* 0xFFFFFFFF */ +/* OS_REG4 */ +#define GRF_OS_REG4_OFFSET (0x210U) +#define GRF_OS_REG4_PMU_OS_REG4_SHIFT (0U) +#define GRF_OS_REG4_PMU_OS_REG4_MASK (0xFFFFFFFFU << GRF_OS_REG4_PMU_OS_REG4_SHIFT) /* 0xFFFFFFFF */ +/* OS_REG5 */ +#define GRF_OS_REG5_OFFSET (0x214U) +#define GRF_OS_REG5_PMU_OS_REG5_SHIFT (0U) +#define GRF_OS_REG5_PMU_OS_REG5_MASK (0xFFFFFFFFU << GRF_OS_REG5_PMU_OS_REG5_SHIFT) /* 0xFFFFFFFF */ +/* OS_REG6 */ +#define GRF_OS_REG6_OFFSET (0x218U) +#define GRF_OS_REG6_PMU_OS_REG6_SHIFT (0U) +#define GRF_OS_REG6_PMU_OS_REG6_MASK (0xFFFFFFFFU << GRF_OS_REG6_PMU_OS_REG6_SHIFT) /* 0xFFFFFFFF */ +/* OS_REG7 */ +#define GRF_OS_REG7_OFFSET (0x21CU) +#define GRF_OS_REG7_PMU_OS_REG7_SHIFT (0U) +#define GRF_OS_REG7_PMU_OS_REG7_MASK (0xFFFFFFFFU << GRF_OS_REG7_PMU_OS_REG7_SHIFT) /* 0xFFFFFFFF */ +/* OS_REG8 */ +#define GRF_OS_REG8_OFFSET (0x220U) +#define GRF_OS_REG8_PMU_OS_REG8_SHIFT (0U) +#define GRF_OS_REG8_PMU_OS_REG8_MASK (0xFFFFFFFFU << GRF_OS_REG8_PMU_OS_REG8_SHIFT) /* 0xFFFFFFFF */ +/* OS_REG9 */ +#define GRF_OS_REG9_OFFSET (0x224U) +#define GRF_OS_REG9_PMU_OS_REG9_SHIFT (0U) +#define GRF_OS_REG9_PMU_OS_REG9_MASK (0xFFFFFFFFU << GRF_OS_REG9_PMU_OS_REG9_SHIFT) /* 0xFFFFFFFF */ +/* OS_REG10 */ +#define GRF_OS_REG10_OFFSET (0x228U) +#define GRF_OS_REG10_PMU_OS_REG10_SHIFT (0U) +#define GRF_OS_REG10_PMU_OS_REG10_MASK (0xFFFFFFFFU << GRF_OS_REG10_PMU_OS_REG10_SHIFT) /* 0xFFFFFFFF */ +/* OS_REG11 */ +#define GRF_OS_REG11_OFFSET (0x22CU) +#define GRF_OS_REG11_PMU_OS_REG11_SHIFT (0U) +#define GRF_OS_REG11_PMU_OS_REG11_MASK (0xFFFFFFFFU << GRF_OS_REG11_PMU_OS_REG11_SHIFT) /* 0xFFFFFFFF */ +/* RESET_FUNCTION_STATUS */ +#define GRF_RESET_FUNCTION_STATUS_OFFSET (0x230U) +#define GRF_RESET_FUNCTION_STATUS_FIRST_RESET_SRC_SHIFT (0U) +#define GRF_RESET_FUNCTION_STATUS_FIRST_RESET_SRC_MASK (0x1U << GRF_RESET_FUNCTION_STATUS_FIRST_RESET_SRC_SHIFT) /* 0x00000001 */ +#define GRF_RESET_FUNCTION_STATUS_WDT_RESET_SRC_SHIFT (1U) +#define GRF_RESET_FUNCTION_STATUS_WDT_RESET_SRC_MASK (0x1U << GRF_RESET_FUNCTION_STATUS_WDT_RESET_SRC_SHIFT) /* 0x00000002 */ +#define GRF_RESET_FUNCTION_STATUS_TSADC_SHUT_RESET_SRC_SHIFT (2U) +#define GRF_RESET_FUNCTION_STATUS_TSADC_SHUT_RESET_SRC_MASK (0x1U << GRF_RESET_FUNCTION_STATUS_TSADC_SHUT_RESET_SRC_SHIFT) /* 0x00000004 */ +#define GRF_RESET_FUNCTION_STATUS_DDR_FAIL_SAFE_SRC_SHIFT (3U) +#define GRF_RESET_FUNCTION_STATUS_DDR_FAIL_SAFE_SRC_MASK (0x1U << GRF_RESET_FUNCTION_STATUS_DDR_FAIL_SAFE_SRC_SHIFT) /* 0x00000008 */ +/* RESET_FUNCTION_CLR */ +#define GRF_RESET_FUNCTION_CLR_OFFSET (0x234U) +#define GRF_RESET_FUNCTION_CLR_FIRST_RESET_SRC_CLR_SHIFT (0U) +#define GRF_RESET_FUNCTION_CLR_FIRST_RESET_SRC_CLR_MASK (0x1U << GRF_RESET_FUNCTION_CLR_FIRST_RESET_SRC_CLR_SHIFT) /* 0x00000001 */ +#define GRF_RESET_FUNCTION_CLR_WDT_RESET_SRC_CLR_SHIFT (1U) +#define GRF_RESET_FUNCTION_CLR_WDT_RESET_SRC_CLR_MASK (0x1U << GRF_RESET_FUNCTION_CLR_WDT_RESET_SRC_CLR_SHIFT) /* 0x00000002 */ +#define GRF_RESET_FUNCTION_CLR_TSADC_SHUT_RESET_SRC_CLR_SHIFT (2U) +#define GRF_RESET_FUNCTION_CLR_TSADC_SHUT_RESET_SRC_CLR_MASK (0x1U << GRF_RESET_FUNCTION_CLR_TSADC_SHUT_RESET_SRC_CLR_SHIFT) /* 0x00000004 */ +#define GRF_RESET_FUNCTION_CLR_DDR_FAIL_SAFE_SRC_CLR_SHIFT (3U) +#define GRF_RESET_FUNCTION_CLR_DDR_FAIL_SAFE_SRC_CLR_MASK (0x1U << GRF_RESET_FUNCTION_CLR_DDR_FAIL_SAFE_SRC_CLR_SHIFT) /* 0x00000008 */ +/* SIG_DETECT_CON */ +#define GRF_SIG_DETECT_CON_OFFSET (0x380U) +#define GRF_SIG_DETECT_CON_SDMMC0_DETECTN_POS_IRQ_MSK_SHIFT (0U) +#define GRF_SIG_DETECT_CON_SDMMC0_DETECTN_POS_IRQ_MSK_MASK (0x1U << GRF_SIG_DETECT_CON_SDMMC0_DETECTN_POS_IRQ_MSK_SHIFT) /* 0x00000001 */ +#define GRF_SIG_DETECT_CON_SDMMC0_DETECTN_NEG_IRQ_MSK_SHIFT (1U) +#define GRF_SIG_DETECT_CON_SDMMC0_DETECTN_NEG_IRQ_MSK_MASK (0x1U << GRF_SIG_DETECT_CON_SDMMC0_DETECTN_NEG_IRQ_MSK_SHIFT) /* 0x00000002 */ +#define GRF_SIG_DETECT_CON_SDMMC1_DETECTN_POS_IRQ_MSK_SHIFT (2U) +#define GRF_SIG_DETECT_CON_SDMMC1_DETECTN_POS_IRQ_MSK_MASK (0x1U << GRF_SIG_DETECT_CON_SDMMC1_DETECTN_POS_IRQ_MSK_SHIFT) /* 0x00000004 */ +#define GRF_SIG_DETECT_CON_SDMMC1_DETECTN_NEG_IRQ_MSK_SHIFT (3U) +#define GRF_SIG_DETECT_CON_SDMMC1_DETECTN_NEG_IRQ_MSK_MASK (0x1U << GRF_SIG_DETECT_CON_SDMMC1_DETECTN_NEG_IRQ_MSK_SHIFT) /* 0x00000008 */ +#define GRF_SIG_DETECT_CON_SDMMC2_DETECTN_POS_IRQ_MSK_SHIFT (4U) +#define GRF_SIG_DETECT_CON_SDMMC2_DETECTN_POS_IRQ_MSK_MASK (0x1U << GRF_SIG_DETECT_CON_SDMMC2_DETECTN_POS_IRQ_MSK_SHIFT) /* 0x00000010 */ +#define GRF_SIG_DETECT_CON_SDMMC2_DETECTN_NEG_IRQ_MSK_SHIFT (5U) +#define GRF_SIG_DETECT_CON_SDMMC2_DETECTN_NEG_IRQ_MSK_MASK (0x1U << GRF_SIG_DETECT_CON_SDMMC2_DETECTN_NEG_IRQ_MSK_SHIFT) /* 0x00000020 */ +/* SIG_DETECT_STATUS */ +#define GRF_SIG_DETECT_STATUS_OFFSET (0x390U) +#define GRF_SIG_DETECT_STATUS_SDMMC0_DETECTN_POS_IRQ_SHIFT (0U) +#define GRF_SIG_DETECT_STATUS_SDMMC0_DETECTN_POS_IRQ_MASK (0x1U << GRF_SIG_DETECT_STATUS_SDMMC0_DETECTN_POS_IRQ_SHIFT) /* 0x00000001 */ +#define GRF_SIG_DETECT_STATUS_SDMMC0_DETECTN_NEG_IRQ_SHIFT (1U) +#define GRF_SIG_DETECT_STATUS_SDMMC0_DETECTN_NEG_IRQ_MASK (0x1U << GRF_SIG_DETECT_STATUS_SDMMC0_DETECTN_NEG_IRQ_SHIFT) /* 0x00000002 */ +#define GRF_SIG_DETECT_STATUS_SDMMC1_DETECTN_POS_IRQ_SHIFT (2U) +#define GRF_SIG_DETECT_STATUS_SDMMC1_DETECTN_POS_IRQ_MASK (0x1U << GRF_SIG_DETECT_STATUS_SDMMC1_DETECTN_POS_IRQ_SHIFT) /* 0x00000004 */ +#define GRF_SIG_DETECT_STATUS_SDMMC1_DETECTN_NEG_IRQ_SHIFT (3U) +#define GRF_SIG_DETECT_STATUS_SDMMC1_DETECTN_NEG_IRQ_MASK (0x1U << GRF_SIG_DETECT_STATUS_SDMMC1_DETECTN_NEG_IRQ_SHIFT) /* 0x00000008 */ +#define GRF_SIG_DETECT_STATUS_SDMMC2_DETECTN_POS_IRQ_SHIFT (4U) +#define GRF_SIG_DETECT_STATUS_SDMMC2_DETECTN_POS_IRQ_MASK (0x1U << GRF_SIG_DETECT_STATUS_SDMMC2_DETECTN_POS_IRQ_SHIFT) /* 0x00000010 */ +#define GRF_SIG_DETECT_STATUS_SDMMC2_DETECTN_NEG_IRQ_SHIFT (5U) +#define GRF_SIG_DETECT_STATUS_SDMMC2_DETECTN_NEG_IRQ_MASK (0x1U << GRF_SIG_DETECT_STATUS_SDMMC2_DETECTN_NEG_IRQ_SHIFT) /* 0x00000020 */ +/* SIG_DETECT_STATUS_CLEAR */ +#define GRF_SIG_DETECT_STATUS_CLEAR_OFFSET (0x3A0U) +#define GRF_SIG_DETECT_STATUS_CLEAR_SDMMC0_DETECTN_POS_IRQ_CLR_SHIFT (0U) +#define GRF_SIG_DETECT_STATUS_CLEAR_SDMMC0_DETECTN_POS_IRQ_CLR_MASK (0x1U << GRF_SIG_DETECT_STATUS_CLEAR_SDMMC0_DETECTN_POS_IRQ_CLR_SHIFT) /* 0x00000001 */ +#define GRF_SIG_DETECT_STATUS_CLEAR_SDMMC0_DETECTN_NEG_IRQ_CLR_SHIFT (1U) +#define GRF_SIG_DETECT_STATUS_CLEAR_SDMMC0_DETECTN_NEG_IRQ_CLR_MASK (0x1U << GRF_SIG_DETECT_STATUS_CLEAR_SDMMC0_DETECTN_NEG_IRQ_CLR_SHIFT) /* 0x00000002 */ +#define GRF_SIG_DETECT_STATUS_CLEAR_SDMMC1_DETECTN_POS_IRQ_CLR_SHIFT (2U) +#define GRF_SIG_DETECT_STATUS_CLEAR_SDMMC1_DETECTN_POS_IRQ_CLR_MASK (0x1U << GRF_SIG_DETECT_STATUS_CLEAR_SDMMC1_DETECTN_POS_IRQ_CLR_SHIFT) /* 0x00000004 */ +#define GRF_SIG_DETECT_STATUS_CLEAR_SDMMC1_DETECTN_NEG_IRQ_CLR_SHIFT (3U) +#define GRF_SIG_DETECT_STATUS_CLEAR_SDMMC1_DETECTN_NEG_IRQ_CLR_MASK (0x1U << GRF_SIG_DETECT_STATUS_CLEAR_SDMMC1_DETECTN_NEG_IRQ_CLR_SHIFT) /* 0x00000008 */ +#define GRF_SIG_DETECT_STATUS_CLEAR_SDMMC2_DETECTN_POS_IRQ_CLR_SHIFT (4U) +#define GRF_SIG_DETECT_STATUS_CLEAR_SDMMC2_DETECTN_POS_IRQ_CLR_MASK (0x1U << GRF_SIG_DETECT_STATUS_CLEAR_SDMMC2_DETECTN_POS_IRQ_CLR_SHIFT) /* 0x00000010 */ +#define GRF_SIG_DETECT_STATUS_CLEAR_SDMMC2_DETECTN_NEG_IRQ_CLR_SHIFT (5U) +#define GRF_SIG_DETECT_STATUS_CLEAR_SDMMC2_DETECTN_NEG_IRQ_CLR_MASK (0x1U << GRF_SIG_DETECT_STATUS_CLEAR_SDMMC2_DETECTN_NEG_IRQ_CLR_SHIFT) /* 0x00000020 */ +/* SDMMC_DET_COUNTER */ +#define GRF_SDMMC_DET_COUNTER_OFFSET (0x3B0U) +#define GRF_SDMMC_DET_COUNTER_SDMMC_DETECTN_COUNT_SHIFT (0U) +#define GRF_SDMMC_DET_COUNTER_SDMMC_DETECTN_COUNT_MASK (0xFFFFFU << GRF_SDMMC_DET_COUNTER_SDMMC_DETECTN_COUNT_SHIFT) /* 0x000FFFFF */ +/* GPIO1A_IOMUX_L */ +#define GRF_GPIO1A_IOMUX_L_OFFSET (0x40000U) +#define GRF_GPIO1A_IOMUX_L_GPIO1A0_SEL_SHIFT (0U) +#define GRF_GPIO1A_IOMUX_L_GPIO1A0_SEL_MASK (0x7U << GRF_GPIO1A_IOMUX_L_GPIO1A0_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO1A_IOMUX_L_GPIO1A1_SEL_SHIFT (4U) +#define GRF_GPIO1A_IOMUX_L_GPIO1A1_SEL_MASK (0x7U << GRF_GPIO1A_IOMUX_L_GPIO1A1_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO1A_IOMUX_L_GPIO1A2_SEL_SHIFT (8U) +#define GRF_GPIO1A_IOMUX_L_GPIO1A2_SEL_MASK (0x7U << GRF_GPIO1A_IOMUX_L_GPIO1A2_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO1A_IOMUX_L_GPIO1A3_SEL_SHIFT (12U) +#define GRF_GPIO1A_IOMUX_L_GPIO1A3_SEL_MASK (0x7U << GRF_GPIO1A_IOMUX_L_GPIO1A3_SEL_SHIFT) /* 0x00007000 */ +/* GPIO1A_IOMUX_H */ +#define GRF_GPIO1A_IOMUX_H_OFFSET (0x40004U) +#define GRF_GPIO1A_IOMUX_H_GPIO1A4_SEL_SHIFT (0U) +#define GRF_GPIO1A_IOMUX_H_GPIO1A4_SEL_MASK (0x7U << GRF_GPIO1A_IOMUX_H_GPIO1A4_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO1A_IOMUX_H_GPIO1A5_SEL_SHIFT (4U) +#define GRF_GPIO1A_IOMUX_H_GPIO1A5_SEL_MASK (0x7U << GRF_GPIO1A_IOMUX_H_GPIO1A5_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO1A_IOMUX_H_GPIO1A6_SEL_SHIFT (8U) +#define GRF_GPIO1A_IOMUX_H_GPIO1A6_SEL_MASK (0x7U << GRF_GPIO1A_IOMUX_H_GPIO1A6_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO1A_IOMUX_H_GPIO1A7_SEL_SHIFT (12U) +#define GRF_GPIO1A_IOMUX_H_GPIO1A7_SEL_MASK (0x7U << GRF_GPIO1A_IOMUX_H_GPIO1A7_SEL_SHIFT) /* 0x00007000 */ +/* GPIO1B_IOMUX_L */ +#define GRF_GPIO1B_IOMUX_L_OFFSET (0x40008U) +#define GRF_GPIO1B_IOMUX_L_GPIO1B0_SEL_SHIFT (0U) +#define GRF_GPIO1B_IOMUX_L_GPIO1B0_SEL_MASK (0x7U << GRF_GPIO1B_IOMUX_L_GPIO1B0_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO1B_IOMUX_L_GPIO1B1_SEL_SHIFT (4U) +#define GRF_GPIO1B_IOMUX_L_GPIO1B1_SEL_MASK (0x7U << GRF_GPIO1B_IOMUX_L_GPIO1B1_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO1B_IOMUX_L_GPIO1B2_SEL_SHIFT (8U) +#define GRF_GPIO1B_IOMUX_L_GPIO1B2_SEL_MASK (0x7U << GRF_GPIO1B_IOMUX_L_GPIO1B2_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO1B_IOMUX_L_GPIO1B3_SEL_SHIFT (12U) +#define GRF_GPIO1B_IOMUX_L_GPIO1B3_SEL_MASK (0x7U << GRF_GPIO1B_IOMUX_L_GPIO1B3_SEL_SHIFT) /* 0x00007000 */ +/* GPIO1B_IOMUX_H */ +#define GRF_GPIO1B_IOMUX_H_OFFSET (0x4000CU) +#define GRF_GPIO1B_IOMUX_H_GPIO1B4_SEL_SHIFT (0U) +#define GRF_GPIO1B_IOMUX_H_GPIO1B4_SEL_MASK (0x7U << GRF_GPIO1B_IOMUX_H_GPIO1B4_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO1B_IOMUX_H_GPIO1B5_SEL_SHIFT (4U) +#define GRF_GPIO1B_IOMUX_H_GPIO1B5_SEL_MASK (0x7U << GRF_GPIO1B_IOMUX_H_GPIO1B5_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO1B_IOMUX_H_GPIO1B6_SEL_SHIFT (8U) +#define GRF_GPIO1B_IOMUX_H_GPIO1B6_SEL_MASK (0x7U << GRF_GPIO1B_IOMUX_H_GPIO1B6_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO1B_IOMUX_H_GPIO1B7_SEL_SHIFT (12U) +#define GRF_GPIO1B_IOMUX_H_GPIO1B7_SEL_MASK (0x7U << GRF_GPIO1B_IOMUX_H_GPIO1B7_SEL_SHIFT) /* 0x00007000 */ +/* GPIO1C_IOMUX_L */ +#define GRF_GPIO1C_IOMUX_L_OFFSET (0x40010U) +#define GRF_GPIO1C_IOMUX_L_GPIO1C0_SEL_SHIFT (0U) +#define GRF_GPIO1C_IOMUX_L_GPIO1C0_SEL_MASK (0x7U << GRF_GPIO1C_IOMUX_L_GPIO1C0_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO1C_IOMUX_L_GPIO1C1_SEL_SHIFT (4U) +#define GRF_GPIO1C_IOMUX_L_GPIO1C1_SEL_MASK (0x7U << GRF_GPIO1C_IOMUX_L_GPIO1C1_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO1C_IOMUX_L_GPIO1C2_SEL_SHIFT (8U) +#define GRF_GPIO1C_IOMUX_L_GPIO1C2_SEL_MASK (0x7U << GRF_GPIO1C_IOMUX_L_GPIO1C2_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO1C_IOMUX_L_GPIO1C3_SEL_SHIFT (12U) +#define GRF_GPIO1C_IOMUX_L_GPIO1C3_SEL_MASK (0x7U << GRF_GPIO1C_IOMUX_L_GPIO1C3_SEL_SHIFT) /* 0x00007000 */ +/* GPIO1C_IOMUX_H */ +#define GRF_GPIO1C_IOMUX_H_OFFSET (0x40014U) +#define GRF_GPIO1C_IOMUX_H_GPIO1C4_SEL_SHIFT (0U) +#define GRF_GPIO1C_IOMUX_H_GPIO1C4_SEL_MASK (0x7U << GRF_GPIO1C_IOMUX_H_GPIO1C4_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO1C_IOMUX_H_GPIO1C5_SEL_SHIFT (4U) +#define GRF_GPIO1C_IOMUX_H_GPIO1C5_SEL_MASK (0x7U << GRF_GPIO1C_IOMUX_H_GPIO1C5_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO1C_IOMUX_H_GPIO1C6_SEL_SHIFT (8U) +#define GRF_GPIO1C_IOMUX_H_GPIO1C6_SEL_MASK (0x7U << GRF_GPIO1C_IOMUX_H_GPIO1C6_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO1C_IOMUX_H_GPIO1C7_SEL_SHIFT (12U) +#define GRF_GPIO1C_IOMUX_H_GPIO1C7_SEL_MASK (0x7U << GRF_GPIO1C_IOMUX_H_GPIO1C7_SEL_SHIFT) /* 0x00007000 */ +/* GPIO1D_IOMUX_L */ +#define GRF_GPIO1D_IOMUX_L_OFFSET (0x40018U) +#define GRF_GPIO1D_IOMUX_L_GPIO1D0_SEL_SHIFT (0U) +#define GRF_GPIO1D_IOMUX_L_GPIO1D0_SEL_MASK (0x7U << GRF_GPIO1D_IOMUX_L_GPIO1D0_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO1D_IOMUX_L_GPIO1D1_SEL_SHIFT (4U) +#define GRF_GPIO1D_IOMUX_L_GPIO1D1_SEL_MASK (0x7U << GRF_GPIO1D_IOMUX_L_GPIO1D1_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO1D_IOMUX_L_GPIO1D2_SEL_SHIFT (8U) +#define GRF_GPIO1D_IOMUX_L_GPIO1D2_SEL_MASK (0x7U << GRF_GPIO1D_IOMUX_L_GPIO1D2_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO1D_IOMUX_L_GPIO1D3_SEL_SHIFT (12U) +#define GRF_GPIO1D_IOMUX_L_GPIO1D3_SEL_MASK (0x7U << GRF_GPIO1D_IOMUX_L_GPIO1D3_SEL_SHIFT) /* 0x00007000 */ +/* GPIO1D_IOMUX_H */ +#define GRF_GPIO1D_IOMUX_H_OFFSET (0x4001CU) +#define GRF_GPIO1D_IOMUX_H_GPIO1D4_SEL_SHIFT (0U) +#define GRF_GPIO1D_IOMUX_H_GPIO1D4_SEL_MASK (0x7U << GRF_GPIO1D_IOMUX_H_GPIO1D4_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO1D_IOMUX_H_GPIO1D5_SEL_SHIFT (4U) +#define GRF_GPIO1D_IOMUX_H_GPIO1D5_SEL_MASK (0x7U << GRF_GPIO1D_IOMUX_H_GPIO1D5_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO1D_IOMUX_H_GPIO1D6_SEL_SHIFT (8U) +#define GRF_GPIO1D_IOMUX_H_GPIO1D6_SEL_MASK (0x7U << GRF_GPIO1D_IOMUX_H_GPIO1D6_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO1D_IOMUX_H_GPIO1D7_SEL_SHIFT (12U) +#define GRF_GPIO1D_IOMUX_H_GPIO1D7_SEL_MASK (0x7U << GRF_GPIO1D_IOMUX_H_GPIO1D7_SEL_SHIFT) /* 0x00007000 */ +/* GPIO2A_IOMUX_L */ +#define GRF_GPIO2A_IOMUX_L_OFFSET (0x40020U) +#define GRF_GPIO2A_IOMUX_L_GPIO2A0_SEL_SHIFT (0U) +#define GRF_GPIO2A_IOMUX_L_GPIO2A0_SEL_MASK (0x7U << GRF_GPIO2A_IOMUX_L_GPIO2A0_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO2A_IOMUX_L_GPIO2A1_SEL_SHIFT (4U) +#define GRF_GPIO2A_IOMUX_L_GPIO2A1_SEL_MASK (0x7U << GRF_GPIO2A_IOMUX_L_GPIO2A1_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO2A_IOMUX_L_GPIO2A2_SEL_SHIFT (8U) +#define GRF_GPIO2A_IOMUX_L_GPIO2A2_SEL_MASK (0x7U << GRF_GPIO2A_IOMUX_L_GPIO2A2_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO2A_IOMUX_L_GPIO2A3_SEL_SHIFT (12U) +#define GRF_GPIO2A_IOMUX_L_GPIO2A3_SEL_MASK (0x7U << GRF_GPIO2A_IOMUX_L_GPIO2A3_SEL_SHIFT) /* 0x00007000 */ +/* GPIO2A_IOMUX_H */ +#define GRF_GPIO2A_IOMUX_H_OFFSET (0x40024U) +#define GRF_GPIO2A_IOMUX_H_GPIO2A4_SEL_SHIFT (0U) +#define GRF_GPIO2A_IOMUX_H_GPIO2A4_SEL_MASK (0x7U << GRF_GPIO2A_IOMUX_H_GPIO2A4_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO2A_IOMUX_H_GPIO2A5_SEL_SHIFT (4U) +#define GRF_GPIO2A_IOMUX_H_GPIO2A5_SEL_MASK (0x7U << GRF_GPIO2A_IOMUX_H_GPIO2A5_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO2A_IOMUX_H_GPIO2A6_SEL_SHIFT (8U) +#define GRF_GPIO2A_IOMUX_H_GPIO2A6_SEL_MASK (0x7U << GRF_GPIO2A_IOMUX_H_GPIO2A6_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO2A_IOMUX_H_GPIO2A7_SEL_SHIFT (12U) +#define GRF_GPIO2A_IOMUX_H_GPIO2A7_SEL_MASK (0x7U << GRF_GPIO2A_IOMUX_H_GPIO2A7_SEL_SHIFT) /* 0x00007000 */ +/* GPIO2B_IOMUX_L */ +#define GRF_GPIO2B_IOMUX_L_OFFSET (0x40028U) +#define GRF_GPIO2B_IOMUX_L_GPIO2B0_SEL_SHIFT (0U) +#define GRF_GPIO2B_IOMUX_L_GPIO2B0_SEL_MASK (0x7U << GRF_GPIO2B_IOMUX_L_GPIO2B0_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO2B_IOMUX_L_GPIO2B1_SEL_SHIFT (4U) +#define GRF_GPIO2B_IOMUX_L_GPIO2B1_SEL_MASK (0x7U << GRF_GPIO2B_IOMUX_L_GPIO2B1_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO2B_IOMUX_L_GPIO2B2_SEL_SHIFT (8U) +#define GRF_GPIO2B_IOMUX_L_GPIO2B2_SEL_MASK (0x7U << GRF_GPIO2B_IOMUX_L_GPIO2B2_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO2B_IOMUX_L_GPIO2B3_SEL_SHIFT (12U) +#define GRF_GPIO2B_IOMUX_L_GPIO2B3_SEL_MASK (0x7U << GRF_GPIO2B_IOMUX_L_GPIO2B3_SEL_SHIFT) /* 0x00007000 */ +/* GPIO2B_IOMUX_H */ +#define GRF_GPIO2B_IOMUX_H_OFFSET (0x4002CU) +#define GRF_GPIO2B_IOMUX_H_GPIO2B4_SEL_SHIFT (0U) +#define GRF_GPIO2B_IOMUX_H_GPIO2B4_SEL_MASK (0x7U << GRF_GPIO2B_IOMUX_H_GPIO2B4_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO2B_IOMUX_H_GPIO2B5_SEL_SHIFT (4U) +#define GRF_GPIO2B_IOMUX_H_GPIO2B5_SEL_MASK (0x7U << GRF_GPIO2B_IOMUX_H_GPIO2B5_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO2B_IOMUX_H_GPIO2B6_SEL_SHIFT (8U) +#define GRF_GPIO2B_IOMUX_H_GPIO2B6_SEL_MASK (0x7U << GRF_GPIO2B_IOMUX_H_GPIO2B6_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO2B_IOMUX_H_GPIO2B7_SEL_SHIFT (12U) +#define GRF_GPIO2B_IOMUX_H_GPIO2B7_SEL_MASK (0x7U << GRF_GPIO2B_IOMUX_H_GPIO2B7_SEL_SHIFT) /* 0x00007000 */ +/* GPIO2C_IOMUX_L */ +#define GRF_GPIO2C_IOMUX_L_OFFSET (0x40030U) +#define GRF_GPIO2C_IOMUX_L_GPIO2C0_SEL_SHIFT (0U) +#define GRF_GPIO2C_IOMUX_L_GPIO2C0_SEL_MASK (0x7U << GRF_GPIO2C_IOMUX_L_GPIO2C0_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO2C_IOMUX_L_GPIO2C1_SEL_SHIFT (4U) +#define GRF_GPIO2C_IOMUX_L_GPIO2C1_SEL_MASK (0x7U << GRF_GPIO2C_IOMUX_L_GPIO2C1_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO2C_IOMUX_L_GPIO2C2_SEL_SHIFT (8U) +#define GRF_GPIO2C_IOMUX_L_GPIO2C2_SEL_MASK (0x7U << GRF_GPIO2C_IOMUX_L_GPIO2C2_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO2C_IOMUX_L_GPIO2C3_SEL_SHIFT (12U) +#define GRF_GPIO2C_IOMUX_L_GPIO2C3_SEL_MASK (0x7U << GRF_GPIO2C_IOMUX_L_GPIO2C3_SEL_SHIFT) /* 0x00007000 */ +/* GPIO2C_IOMUX_H */ +#define GRF_GPIO2C_IOMUX_H_OFFSET (0x40034U) +#define GRF_GPIO2C_IOMUX_H_GPIO2C4_SEL_SHIFT (0U) +#define GRF_GPIO2C_IOMUX_H_GPIO2C4_SEL_MASK (0x7U << GRF_GPIO2C_IOMUX_H_GPIO2C4_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO2C_IOMUX_H_GPIO2C5_SEL_SHIFT (4U) +#define GRF_GPIO2C_IOMUX_H_GPIO2C5_SEL_MASK (0x7U << GRF_GPIO2C_IOMUX_H_GPIO2C5_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO2C_IOMUX_H_GPIO2C6_SEL_SHIFT (8U) +#define GRF_GPIO2C_IOMUX_H_GPIO2C6_SEL_MASK (0x7U << GRF_GPIO2C_IOMUX_H_GPIO2C6_SEL_SHIFT) /* 0x00000700 */ +/* GPIO2D_IOMUX_L */ +#define GRF_GPIO2D_IOMUX_L_OFFSET (0x40038U) +#define GRF_GPIO2D_IOMUX_L_GPIO2D0_SEL_SHIFT (0U) +#define GRF_GPIO2D_IOMUX_L_GPIO2D0_SEL_MASK (0x7U << GRF_GPIO2D_IOMUX_L_GPIO2D0_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO2D_IOMUX_L_GPIO2D1_SEL_SHIFT (4U) +#define GRF_GPIO2D_IOMUX_L_GPIO2D1_SEL_MASK (0x7U << GRF_GPIO2D_IOMUX_L_GPIO2D1_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO2D_IOMUX_L_GPIO2D2_SEL_SHIFT (8U) +#define GRF_GPIO2D_IOMUX_L_GPIO2D2_SEL_MASK (0x7U << GRF_GPIO2D_IOMUX_L_GPIO2D2_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO2D_IOMUX_L_GPIO2D3_SEL_SHIFT (12U) +#define GRF_GPIO2D_IOMUX_L_GPIO2D3_SEL_MASK (0x7U << GRF_GPIO2D_IOMUX_L_GPIO2D3_SEL_SHIFT) /* 0x00007000 */ +/* GPIO2D_IOMUX_H */ +#define GRF_GPIO2D_IOMUX_H_OFFSET (0x4003CU) +#define GRF_GPIO2D_IOMUX_H_GPIO2D4_SEL_SHIFT (0U) +#define GRF_GPIO2D_IOMUX_H_GPIO2D4_SEL_MASK (0x7U << GRF_GPIO2D_IOMUX_H_GPIO2D4_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO2D_IOMUX_H_GPIO2D5_SEL_SHIFT (4U) +#define GRF_GPIO2D_IOMUX_H_GPIO2D5_SEL_MASK (0x7U << GRF_GPIO2D_IOMUX_H_GPIO2D5_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO2D_IOMUX_H_GPIO2D6_SEL_SHIFT (8U) +#define GRF_GPIO2D_IOMUX_H_GPIO2D6_SEL_MASK (0x7U << GRF_GPIO2D_IOMUX_H_GPIO2D6_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO2D_IOMUX_H_GPIO2D7_SEL_SHIFT (12U) +#define GRF_GPIO2D_IOMUX_H_GPIO2D7_SEL_MASK (0x7U << GRF_GPIO2D_IOMUX_H_GPIO2D7_SEL_SHIFT) /* 0x00007000 */ +/* GPIO3A_IOMUX_L */ +#define GRF_GPIO3A_IOMUX_L_OFFSET (0x40040U) +#define GRF_GPIO3A_IOMUX_L_GPIO3A0_SEL_SHIFT (0U) +#define GRF_GPIO3A_IOMUX_L_GPIO3A0_SEL_MASK (0x7U << GRF_GPIO3A_IOMUX_L_GPIO3A0_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO3A_IOMUX_L_GPIO3A1_SEL_SHIFT (4U) +#define GRF_GPIO3A_IOMUX_L_GPIO3A1_SEL_MASK (0x7U << GRF_GPIO3A_IOMUX_L_GPIO3A1_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO3A_IOMUX_L_GPIO3A2_SEL_SHIFT (8U) +#define GRF_GPIO3A_IOMUX_L_GPIO3A2_SEL_MASK (0x7U << GRF_GPIO3A_IOMUX_L_GPIO3A2_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO3A_IOMUX_L_GPIO3A3_SEL_SHIFT (12U) +#define GRF_GPIO3A_IOMUX_L_GPIO3A3_SEL_MASK (0x7U << GRF_GPIO3A_IOMUX_L_GPIO3A3_SEL_SHIFT) /* 0x00007000 */ +/* GPIO3A_IOMUX_H */ +#define GRF_GPIO3A_IOMUX_H_OFFSET (0x40044U) +#define GRF_GPIO3A_IOMUX_H_GPIO3A4_SEL_SHIFT (0U) +#define GRF_GPIO3A_IOMUX_H_GPIO3A4_SEL_MASK (0x7U << GRF_GPIO3A_IOMUX_H_GPIO3A4_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO3A_IOMUX_H_GPIO3A5_SEL_SHIFT (4U) +#define GRF_GPIO3A_IOMUX_H_GPIO3A5_SEL_MASK (0x7U << GRF_GPIO3A_IOMUX_H_GPIO3A5_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO3A_IOMUX_H_GPIO3A6_SEL_SHIFT (8U) +#define GRF_GPIO3A_IOMUX_H_GPIO3A6_SEL_MASK (0x7U << GRF_GPIO3A_IOMUX_H_GPIO3A6_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO3A_IOMUX_H_GPIO3A7_SEL_SHIFT (12U) +#define GRF_GPIO3A_IOMUX_H_GPIO3A7_SEL_MASK (0x7U << GRF_GPIO3A_IOMUX_H_GPIO3A7_SEL_SHIFT) /* 0x00007000 */ +/* GPIO3B_IOMUX_L */ +#define GRF_GPIO3B_IOMUX_L_OFFSET (0x40048U) +#define GRF_GPIO3B_IOMUX_L_GPIO3B0_SEL_SHIFT (0U) +#define GRF_GPIO3B_IOMUX_L_GPIO3B0_SEL_MASK (0x7U << GRF_GPIO3B_IOMUX_L_GPIO3B0_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO3B_IOMUX_L_GPIO3B1_SEL_SHIFT (4U) +#define GRF_GPIO3B_IOMUX_L_GPIO3B1_SEL_MASK (0x7U << GRF_GPIO3B_IOMUX_L_GPIO3B1_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO3B_IOMUX_L_GPIO3B2_SEL_SHIFT (8U) +#define GRF_GPIO3B_IOMUX_L_GPIO3B2_SEL_MASK (0x7U << GRF_GPIO3B_IOMUX_L_GPIO3B2_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO3B_IOMUX_L_GPIO3B3_SEL_SHIFT (12U) +#define GRF_GPIO3B_IOMUX_L_GPIO3B3_SEL_MASK (0x7U << GRF_GPIO3B_IOMUX_L_GPIO3B3_SEL_SHIFT) /* 0x00007000 */ +/* GPIO3B_IOMUX_H */ +#define GRF_GPIO3B_IOMUX_H_OFFSET (0x4004CU) +#define GRF_GPIO3B_IOMUX_H_GPIO3B4_SEL_SHIFT (0U) +#define GRF_GPIO3B_IOMUX_H_GPIO3B4_SEL_MASK (0x7U << GRF_GPIO3B_IOMUX_H_GPIO3B4_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO3B_IOMUX_H_GPIO3B5_SEL_SHIFT (4U) +#define GRF_GPIO3B_IOMUX_H_GPIO3B5_SEL_MASK (0x7U << GRF_GPIO3B_IOMUX_H_GPIO3B5_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO3B_IOMUX_H_GPIO3B6_SEL_SHIFT (8U) +#define GRF_GPIO3B_IOMUX_H_GPIO3B6_SEL_MASK (0x7U << GRF_GPIO3B_IOMUX_H_GPIO3B6_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO3B_IOMUX_H_GPIO3B7_SEL_SHIFT (12U) +#define GRF_GPIO3B_IOMUX_H_GPIO3B7_SEL_MASK (0x7U << GRF_GPIO3B_IOMUX_H_GPIO3B7_SEL_SHIFT) /* 0x00007000 */ +/* GPIO3C_IOMUX_L */ +#define GRF_GPIO3C_IOMUX_L_OFFSET (0x40050U) +#define GRF_GPIO3C_IOMUX_L_GPIO3C0_SEL_SHIFT (0U) +#define GRF_GPIO3C_IOMUX_L_GPIO3C0_SEL_MASK (0x7U << GRF_GPIO3C_IOMUX_L_GPIO3C0_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO3C_IOMUX_L_GPIO3C1_SEL_SHIFT (4U) +#define GRF_GPIO3C_IOMUX_L_GPIO3C1_SEL_MASK (0x7U << GRF_GPIO3C_IOMUX_L_GPIO3C1_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO3C_IOMUX_L_GPIO3C2_SEL_SHIFT (8U) +#define GRF_GPIO3C_IOMUX_L_GPIO3C2_SEL_MASK (0x7U << GRF_GPIO3C_IOMUX_L_GPIO3C2_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO3C_IOMUX_L_GPIO3C3_SEL_SHIFT (12U) +#define GRF_GPIO3C_IOMUX_L_GPIO3C3_SEL_MASK (0x7U << GRF_GPIO3C_IOMUX_L_GPIO3C3_SEL_SHIFT) /* 0x00007000 */ +/* GPIO3C_IOMUX_H */ +#define GRF_GPIO3C_IOMUX_H_OFFSET (0x40054U) +#define GRF_GPIO3C_IOMUX_H_GPIO3C4_SEL_SHIFT (0U) +#define GRF_GPIO3C_IOMUX_H_GPIO3C4_SEL_MASK (0x7U << GRF_GPIO3C_IOMUX_H_GPIO3C4_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO3C_IOMUX_H_GPIO3C5_SEL_SHIFT (4U) +#define GRF_GPIO3C_IOMUX_H_GPIO3C5_SEL_MASK (0x7U << GRF_GPIO3C_IOMUX_H_GPIO3C5_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO3C_IOMUX_H_GPIO3C6_SEL_SHIFT (8U) +#define GRF_GPIO3C_IOMUX_H_GPIO3C6_SEL_MASK (0x7U << GRF_GPIO3C_IOMUX_H_GPIO3C6_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO3C_IOMUX_H_GPIO3C7_SEL_SHIFT (12U) +#define GRF_GPIO3C_IOMUX_H_GPIO3C7_SEL_MASK (0x7U << GRF_GPIO3C_IOMUX_H_GPIO3C7_SEL_SHIFT) /* 0x00007000 */ +/* GPIO3D_IOMUX_L */ +#define GRF_GPIO3D_IOMUX_L_OFFSET (0x40058U) +#define GRF_GPIO3D_IOMUX_L_GPIO3D0_SEL_SHIFT (0U) +#define GRF_GPIO3D_IOMUX_L_GPIO3D0_SEL_MASK (0x7U << GRF_GPIO3D_IOMUX_L_GPIO3D0_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO3D_IOMUX_L_GPIO3D1_SEL_SHIFT (4U) +#define GRF_GPIO3D_IOMUX_L_GPIO3D1_SEL_MASK (0x7U << GRF_GPIO3D_IOMUX_L_GPIO3D1_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO3D_IOMUX_L_GPIO3D2_SEL_SHIFT (8U) +#define GRF_GPIO3D_IOMUX_L_GPIO3D2_SEL_MASK (0x7U << GRF_GPIO3D_IOMUX_L_GPIO3D2_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO3D_IOMUX_L_GPIO3D3_SEL_SHIFT (12U) +#define GRF_GPIO3D_IOMUX_L_GPIO3D3_SEL_MASK (0x7U << GRF_GPIO3D_IOMUX_L_GPIO3D3_SEL_SHIFT) /* 0x00007000 */ +/* GPIO3D_IOMUX_H */ +#define GRF_GPIO3D_IOMUX_H_OFFSET (0x4005CU) +#define GRF_GPIO3D_IOMUX_H_GPIO3D4_SEL_SHIFT (0U) +#define GRF_GPIO3D_IOMUX_H_GPIO3D4_SEL_MASK (0x7U << GRF_GPIO3D_IOMUX_H_GPIO3D4_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO3D_IOMUX_H_GPIO3D5_SEL_SHIFT (4U) +#define GRF_GPIO3D_IOMUX_H_GPIO3D5_SEL_MASK (0x7U << GRF_GPIO3D_IOMUX_H_GPIO3D5_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO3D_IOMUX_H_GPIO3D6_SEL_SHIFT (8U) +#define GRF_GPIO3D_IOMUX_H_GPIO3D6_SEL_MASK (0x7U << GRF_GPIO3D_IOMUX_H_GPIO3D6_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO3D_IOMUX_H_GPIO3D7_SEL_SHIFT (12U) +#define GRF_GPIO3D_IOMUX_H_GPIO3D7_SEL_MASK (0x7U << GRF_GPIO3D_IOMUX_H_GPIO3D7_SEL_SHIFT) /* 0x00007000 */ +/* GPIO4A_IOMUX_L */ +#define GRF_GPIO4A_IOMUX_L_OFFSET (0x40060U) +#define GRF_GPIO4A_IOMUX_L_GPIO4A0_SEL_SHIFT (0U) +#define GRF_GPIO4A_IOMUX_L_GPIO4A0_SEL_MASK (0x7U << GRF_GPIO4A_IOMUX_L_GPIO4A0_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO4A_IOMUX_L_GPIO4A1_SEL_SHIFT (4U) +#define GRF_GPIO4A_IOMUX_L_GPIO4A1_SEL_MASK (0x7U << GRF_GPIO4A_IOMUX_L_GPIO4A1_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO4A_IOMUX_L_GPIO4A2_SEL_SHIFT (8U) +#define GRF_GPIO4A_IOMUX_L_GPIO4A2_SEL_MASK (0x7U << GRF_GPIO4A_IOMUX_L_GPIO4A2_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO4A_IOMUX_L_GPIO4A3_SEL_SHIFT (12U) +#define GRF_GPIO4A_IOMUX_L_GPIO4A3_SEL_MASK (0x7U << GRF_GPIO4A_IOMUX_L_GPIO4A3_SEL_SHIFT) /* 0x00007000 */ +/* GPIO4A_IOMUX_H */ +#define GRF_GPIO4A_IOMUX_H_OFFSET (0x40064U) +#define GRF_GPIO4A_IOMUX_H_GPIO4A4_SEL_SHIFT (0U) +#define GRF_GPIO4A_IOMUX_H_GPIO4A4_SEL_MASK (0x7U << GRF_GPIO4A_IOMUX_H_GPIO4A4_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO4A_IOMUX_H_GPIO4A5_SEL_SHIFT (4U) +#define GRF_GPIO4A_IOMUX_H_GPIO4A5_SEL_MASK (0x7U << GRF_GPIO4A_IOMUX_H_GPIO4A5_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO4A_IOMUX_H_GPIO4A6_SEL_SHIFT (8U) +#define GRF_GPIO4A_IOMUX_H_GPIO4A6_SEL_MASK (0x7U << GRF_GPIO4A_IOMUX_H_GPIO4A6_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO4A_IOMUX_H_GPIO4A7_SEL_SHIFT (12U) +#define GRF_GPIO4A_IOMUX_H_GPIO4A7_SEL_MASK (0x7U << GRF_GPIO4A_IOMUX_H_GPIO4A7_SEL_SHIFT) /* 0x00007000 */ +/* GPIO4B_IOMUX_L */ +#define GRF_GPIO4B_IOMUX_L_OFFSET (0x40068U) +#define GRF_GPIO4B_IOMUX_L_GPIO4B0_SEL_SHIFT (0U) +#define GRF_GPIO4B_IOMUX_L_GPIO4B0_SEL_MASK (0x7U << GRF_GPIO4B_IOMUX_L_GPIO4B0_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO4B_IOMUX_L_GPIO4B1_SEL_SHIFT (4U) +#define GRF_GPIO4B_IOMUX_L_GPIO4B1_SEL_MASK (0x7U << GRF_GPIO4B_IOMUX_L_GPIO4B1_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO4B_IOMUX_L_GPIO4B2_SEL_SHIFT (8U) +#define GRF_GPIO4B_IOMUX_L_GPIO4B2_SEL_MASK (0x7U << GRF_GPIO4B_IOMUX_L_GPIO4B2_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO4B_IOMUX_L_GPIO4B3_SEL_SHIFT (12U) +#define GRF_GPIO4B_IOMUX_L_GPIO4B3_SEL_MASK (0x7U << GRF_GPIO4B_IOMUX_L_GPIO4B3_SEL_SHIFT) /* 0x00007000 */ +/* GPIO4B_IOMUX_H */ +#define GRF_GPIO4B_IOMUX_H_OFFSET (0x4006CU) +#define GRF_GPIO4B_IOMUX_H_GPIO4B4_SEL_SHIFT (0U) +#define GRF_GPIO4B_IOMUX_H_GPIO4B4_SEL_MASK (0x7U << GRF_GPIO4B_IOMUX_H_GPIO4B4_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO4B_IOMUX_H_GPIO4B5_SEL_SHIFT (4U) +#define GRF_GPIO4B_IOMUX_H_GPIO4B5_SEL_MASK (0x7U << GRF_GPIO4B_IOMUX_H_GPIO4B5_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO4B_IOMUX_H_GPIO4B6_SEL_SHIFT (8U) +#define GRF_GPIO4B_IOMUX_H_GPIO4B6_SEL_MASK (0x7U << GRF_GPIO4B_IOMUX_H_GPIO4B6_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO4B_IOMUX_H_GPIO4B7_SEL_SHIFT (12U) +#define GRF_GPIO4B_IOMUX_H_GPIO4B7_SEL_MASK (0x7U << GRF_GPIO4B_IOMUX_H_GPIO4B7_SEL_SHIFT) /* 0x00007000 */ +/* GPIO4C_IOMUX_L */ +#define GRF_GPIO4C_IOMUX_L_OFFSET (0x40070U) +#define GRF_GPIO4C_IOMUX_L_GPIO4C0_SEL_SHIFT (0U) +#define GRF_GPIO4C_IOMUX_L_GPIO4C0_SEL_MASK (0x7U << GRF_GPIO4C_IOMUX_L_GPIO4C0_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO4C_IOMUX_L_GPIO4C1_SEL_SHIFT (4U) +#define GRF_GPIO4C_IOMUX_L_GPIO4C1_SEL_MASK (0x7U << GRF_GPIO4C_IOMUX_L_GPIO4C1_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO4C_IOMUX_L_GPIO4C2_SEL_SHIFT (8U) +#define GRF_GPIO4C_IOMUX_L_GPIO4C2_SEL_MASK (0x7U << GRF_GPIO4C_IOMUX_L_GPIO4C2_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO4C_IOMUX_L_GPIO4C3_SEL_SHIFT (12U) +#define GRF_GPIO4C_IOMUX_L_GPIO4C3_SEL_MASK (0x7U << GRF_GPIO4C_IOMUX_L_GPIO4C3_SEL_SHIFT) /* 0x00007000 */ +/* GPIO4C_IOMUX_H */ +#define GRF_GPIO4C_IOMUX_H_OFFSET (0x40074U) +#define GRF_GPIO4C_IOMUX_H_GPIO4C4_SEL_SHIFT (0U) +#define GRF_GPIO4C_IOMUX_H_GPIO4C4_SEL_MASK (0x7U << GRF_GPIO4C_IOMUX_H_GPIO4C4_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO4C_IOMUX_H_GPIO4C5_SEL_SHIFT (4U) +#define GRF_GPIO4C_IOMUX_H_GPIO4C5_SEL_MASK (0x7U << GRF_GPIO4C_IOMUX_H_GPIO4C5_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO4C_IOMUX_H_GPIO4C6_SEL_SHIFT (8U) +#define GRF_GPIO4C_IOMUX_H_GPIO4C6_SEL_MASK (0x7U << GRF_GPIO4C_IOMUX_H_GPIO4C6_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPIO4C_IOMUX_H_GPIO4C7_SEL_SHIFT (12U) +#define GRF_GPIO4C_IOMUX_H_GPIO4C7_SEL_MASK (0x7U << GRF_GPIO4C_IOMUX_H_GPIO4C7_SEL_SHIFT) /* 0x00007000 */ +/* GPIO4D_IOMUX_L */ +#define GRF_GPIO4D_IOMUX_L_OFFSET (0x40078U) +#define GRF_GPIO4D_IOMUX_L_GPIO4D0_SEL_SHIFT (0U) +#define GRF_GPIO4D_IOMUX_L_GPIO4D0_SEL_MASK (0x7U << GRF_GPIO4D_IOMUX_L_GPIO4D0_SEL_SHIFT) /* 0x00000007 */ +#define GRF_GPIO4D_IOMUX_L_GPIO4D1_SEL_SHIFT (4U) +#define GRF_GPIO4D_IOMUX_L_GPIO4D1_SEL_MASK (0x7U << GRF_GPIO4D_IOMUX_L_GPIO4D1_SEL_SHIFT) /* 0x00000070 */ +#define GRF_GPIO4D_IOMUX_L_GPIO4D2_SEL_SHIFT (8U) +#define GRF_GPIO4D_IOMUX_L_GPIO4D2_SEL_MASK (0x7U << GRF_GPIO4D_IOMUX_L_GPIO4D2_SEL_SHIFT) /* 0x00000700 */ +/* GPIO1A_P */ +#define GRF_GPIO1A_P_OFFSET (0x40080U) +#define GRF_GPIO1A_P_GPIO1A0_P_SHIFT (0U) +#define GRF_GPIO1A_P_GPIO1A0_P_MASK (0x3U << GRF_GPIO1A_P_GPIO1A0_P_SHIFT) /* 0x00000003 */ +#define GRF_GPIO1A_P_GPIO1A1_P_SHIFT (2U) +#define GRF_GPIO1A_P_GPIO1A1_P_MASK (0x3U << GRF_GPIO1A_P_GPIO1A1_P_SHIFT) /* 0x0000000C */ +#define GRF_GPIO1A_P_GPIO1A2_P_SHIFT (4U) +#define GRF_GPIO1A_P_GPIO1A2_P_MASK (0x3U << GRF_GPIO1A_P_GPIO1A2_P_SHIFT) /* 0x00000030 */ +#define GRF_GPIO1A_P_GPIO1A3_P_SHIFT (6U) +#define GRF_GPIO1A_P_GPIO1A3_P_MASK (0x3U << GRF_GPIO1A_P_GPIO1A3_P_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO1A_P_GPIO1A4_P_SHIFT (8U) +#define GRF_GPIO1A_P_GPIO1A4_P_MASK (0x3U << GRF_GPIO1A_P_GPIO1A4_P_SHIFT) /* 0x00000300 */ +#define GRF_GPIO1A_P_GPIO1A5_P_SHIFT (10U) +#define GRF_GPIO1A_P_GPIO1A5_P_MASK (0x3U << GRF_GPIO1A_P_GPIO1A5_P_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO1A_P_GPIO1A6_P_SHIFT (12U) +#define GRF_GPIO1A_P_GPIO1A6_P_MASK (0x3U << GRF_GPIO1A_P_GPIO1A6_P_SHIFT) /* 0x00003000 */ +#define GRF_GPIO1A_P_GPIO1A7_P_SHIFT (14U) +#define GRF_GPIO1A_P_GPIO1A7_P_MASK (0x3U << GRF_GPIO1A_P_GPIO1A7_P_SHIFT) /* 0x0000C000 */ +/* GPIO1B_P */ +#define GRF_GPIO1B_P_OFFSET (0x40084U) +#define GRF_GPIO1B_P_GPIO1B0_P_SHIFT (0U) +#define GRF_GPIO1B_P_GPIO1B0_P_MASK (0x3U << GRF_GPIO1B_P_GPIO1B0_P_SHIFT) /* 0x00000003 */ +#define GRF_GPIO1B_P_GPIO1B1_P_SHIFT (2U) +#define GRF_GPIO1B_P_GPIO1B1_P_MASK (0x3U << GRF_GPIO1B_P_GPIO1B1_P_SHIFT) /* 0x0000000C */ +#define GRF_GPIO1B_P_GPIO1B2_P_SHIFT (4U) +#define GRF_GPIO1B_P_GPIO1B2_P_MASK (0x3U << GRF_GPIO1B_P_GPIO1B2_P_SHIFT) /* 0x00000030 */ +#define GRF_GPIO1B_P_GPIO1B3_P_SHIFT (6U) +#define GRF_GPIO1B_P_GPIO1B3_P_MASK (0x3U << GRF_GPIO1B_P_GPIO1B3_P_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO1B_P_GPIO1B4_P_SHIFT (8U) +#define GRF_GPIO1B_P_GPIO1B4_P_MASK (0x3U << GRF_GPIO1B_P_GPIO1B4_P_SHIFT) /* 0x00000300 */ +#define GRF_GPIO1B_P_GPIO1B5_P_SHIFT (10U) +#define GRF_GPIO1B_P_GPIO1B5_P_MASK (0x3U << GRF_GPIO1B_P_GPIO1B5_P_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO1B_P_GPIO1B6_P_SHIFT (12U) +#define GRF_GPIO1B_P_GPIO1B6_P_MASK (0x3U << GRF_GPIO1B_P_GPIO1B6_P_SHIFT) /* 0x00003000 */ +#define GRF_GPIO1B_P_GPIO1B7_P_SHIFT (14U) +#define GRF_GPIO1B_P_GPIO1B7_P_MASK (0x3U << GRF_GPIO1B_P_GPIO1B7_P_SHIFT) /* 0x0000C000 */ +/* GPIO1C_P */ +#define GRF_GPIO1C_P_OFFSET (0x40088U) +#define GRF_GPIO1C_P_GPIO1C0_P_SHIFT (0U) +#define GRF_GPIO1C_P_GPIO1C0_P_MASK (0x3U << GRF_GPIO1C_P_GPIO1C0_P_SHIFT) /* 0x00000003 */ +#define GRF_GPIO1C_P_GPIO1C1_P_SHIFT (2U) +#define GRF_GPIO1C_P_GPIO1C1_P_MASK (0x3U << GRF_GPIO1C_P_GPIO1C1_P_SHIFT) /* 0x0000000C */ +#define GRF_GPIO1C_P_GPIO1C2_P_SHIFT (4U) +#define GRF_GPIO1C_P_GPIO1C2_P_MASK (0x3U << GRF_GPIO1C_P_GPIO1C2_P_SHIFT) /* 0x00000030 */ +#define GRF_GPIO1C_P_GPIO1C3_P_SHIFT (6U) +#define GRF_GPIO1C_P_GPIO1C3_P_MASK (0x3U << GRF_GPIO1C_P_GPIO1C3_P_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO1C_P_GPIO1C4_P_SHIFT (8U) +#define GRF_GPIO1C_P_GPIO1C4_P_MASK (0x3U << GRF_GPIO1C_P_GPIO1C4_P_SHIFT) /* 0x00000300 */ +#define GRF_GPIO1C_P_GPIO1C5_P_SHIFT (10U) +#define GRF_GPIO1C_P_GPIO1C5_P_MASK (0x3U << GRF_GPIO1C_P_GPIO1C5_P_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO1C_P_GPIO1C6_P_SHIFT (12U) +#define GRF_GPIO1C_P_GPIO1C6_P_MASK (0x3U << GRF_GPIO1C_P_GPIO1C6_P_SHIFT) /* 0x00003000 */ +#define GRF_GPIO1C_P_GPIO1C7_P_SHIFT (14U) +#define GRF_GPIO1C_P_GPIO1C7_P_MASK (0x3U << GRF_GPIO1C_P_GPIO1C7_P_SHIFT) /* 0x0000C000 */ +/* GPIO1D_P */ +#define GRF_GPIO1D_P_OFFSET (0x4008CU) +#define GRF_GPIO1D_P_GPIO1D0_P_SHIFT (0U) +#define GRF_GPIO1D_P_GPIO1D0_P_MASK (0x3U << GRF_GPIO1D_P_GPIO1D0_P_SHIFT) /* 0x00000003 */ +#define GRF_GPIO1D_P_GPIO1D1_P_SHIFT (2U) +#define GRF_GPIO1D_P_GPIO1D1_P_MASK (0x3U << GRF_GPIO1D_P_GPIO1D1_P_SHIFT) /* 0x0000000C */ +#define GRF_GPIO1D_P_GPIO1D2_P_SHIFT (4U) +#define GRF_GPIO1D_P_GPIO1D2_P_MASK (0x3U << GRF_GPIO1D_P_GPIO1D2_P_SHIFT) /* 0x00000030 */ +#define GRF_GPIO1D_P_GPIO1D3_P_SHIFT (6U) +#define GRF_GPIO1D_P_GPIO1D3_P_MASK (0x3U << GRF_GPIO1D_P_GPIO1D3_P_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO1D_P_GPIO1D4_P_SHIFT (8U) +#define GRF_GPIO1D_P_GPIO1D4_P_MASK (0x3U << GRF_GPIO1D_P_GPIO1D4_P_SHIFT) /* 0x00000300 */ +#define GRF_GPIO1D_P_GPIO1D5_P_SHIFT (10U) +#define GRF_GPIO1D_P_GPIO1D5_P_MASK (0x3U << GRF_GPIO1D_P_GPIO1D5_P_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO1D_P_GPIO1D6_P_SHIFT (12U) +#define GRF_GPIO1D_P_GPIO1D6_P_MASK (0x3U << GRF_GPIO1D_P_GPIO1D6_P_SHIFT) /* 0x00003000 */ +#define GRF_GPIO1D_P_GPIO1D7_P_SHIFT (14U) +#define GRF_GPIO1D_P_GPIO1D7_P_MASK (0x3U << GRF_GPIO1D_P_GPIO1D7_P_SHIFT) /* 0x0000C000 */ +/* GPIO2A_P */ +#define GRF_GPIO2A_P_OFFSET (0x40090U) +#define GRF_GPIO2A_P_GPIO2A0_P_SHIFT (0U) +#define GRF_GPIO2A_P_GPIO2A0_P_MASK (0x3U << GRF_GPIO2A_P_GPIO2A0_P_SHIFT) /* 0x00000003 */ +#define GRF_GPIO2A_P_GPIO2A1_P_SHIFT (2U) +#define GRF_GPIO2A_P_GPIO2A1_P_MASK (0x3U << GRF_GPIO2A_P_GPIO2A1_P_SHIFT) /* 0x0000000C */ +#define GRF_GPIO2A_P_GPIO2A2_P_SHIFT (4U) +#define GRF_GPIO2A_P_GPIO2A2_P_MASK (0x3U << GRF_GPIO2A_P_GPIO2A2_P_SHIFT) /* 0x00000030 */ +#define GRF_GPIO2A_P_GPIO2A3_P_SHIFT (6U) +#define GRF_GPIO2A_P_GPIO2A3_P_MASK (0x3U << GRF_GPIO2A_P_GPIO2A3_P_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO2A_P_GPIO2A4_P_SHIFT (8U) +#define GRF_GPIO2A_P_GPIO2A4_P_MASK (0x3U << GRF_GPIO2A_P_GPIO2A4_P_SHIFT) /* 0x00000300 */ +#define GRF_GPIO2A_P_GPIO2A5_P_SHIFT (10U) +#define GRF_GPIO2A_P_GPIO2A5_P_MASK (0x3U << GRF_GPIO2A_P_GPIO2A5_P_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO2A_P_GPIO2A6_P_SHIFT (12U) +#define GRF_GPIO2A_P_GPIO2A6_P_MASK (0x3U << GRF_GPIO2A_P_GPIO2A6_P_SHIFT) /* 0x00003000 */ +#define GRF_GPIO2A_P_GPIO2A7_P_SHIFT (14U) +#define GRF_GPIO2A_P_GPIO2A7_P_MASK (0x3U << GRF_GPIO2A_P_GPIO2A7_P_SHIFT) /* 0x0000C000 */ +/* GPIO2B_P */ +#define GRF_GPIO2B_P_OFFSET (0x40094U) +#define GRF_GPIO2B_P_GPIO2B0_P_SHIFT (0U) +#define GRF_GPIO2B_P_GPIO2B0_P_MASK (0x3U << GRF_GPIO2B_P_GPIO2B0_P_SHIFT) /* 0x00000003 */ +#define GRF_GPIO2B_P_GPIO2B1_P_SHIFT (2U) +#define GRF_GPIO2B_P_GPIO2B1_P_MASK (0x3U << GRF_GPIO2B_P_GPIO2B1_P_SHIFT) /* 0x0000000C */ +#define GRF_GPIO2B_P_GPIO2B2_P_SHIFT (4U) +#define GRF_GPIO2B_P_GPIO2B2_P_MASK (0x3U << GRF_GPIO2B_P_GPIO2B2_P_SHIFT) /* 0x00000030 */ +#define GRF_GPIO2B_P_GPIO2B3_P_SHIFT (6U) +#define GRF_GPIO2B_P_GPIO2B3_P_MASK (0x3U << GRF_GPIO2B_P_GPIO2B3_P_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO2B_P_GPIO2B4_P_SHIFT (8U) +#define GRF_GPIO2B_P_GPIO2B4_P_MASK (0x3U << GRF_GPIO2B_P_GPIO2B4_P_SHIFT) /* 0x00000300 */ +#define GRF_GPIO2B_P_GPIO2B5_P_SHIFT (10U) +#define GRF_GPIO2B_P_GPIO2B5_P_MASK (0x3U << GRF_GPIO2B_P_GPIO2B5_P_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO2B_P_GPIO2B6_P_SHIFT (12U) +#define GRF_GPIO2B_P_GPIO2B6_P_MASK (0x3U << GRF_GPIO2B_P_GPIO2B6_P_SHIFT) /* 0x00003000 */ +#define GRF_GPIO2B_P_GPIO2B7_P_SHIFT (14U) +#define GRF_GPIO2B_P_GPIO2B7_P_MASK (0x3U << GRF_GPIO2B_P_GPIO2B7_P_SHIFT) /* 0x0000C000 */ +/* GPIO2C_P */ +#define GRF_GPIO2C_P_OFFSET (0x40098U) +#define GRF_GPIO2C_P_GPIO2C0_P_SHIFT (0U) +#define GRF_GPIO2C_P_GPIO2C0_P_MASK (0x3U << GRF_GPIO2C_P_GPIO2C0_P_SHIFT) /* 0x00000003 */ +#define GRF_GPIO2C_P_GPIO2C1_P_SHIFT (2U) +#define GRF_GPIO2C_P_GPIO2C1_P_MASK (0x3U << GRF_GPIO2C_P_GPIO2C1_P_SHIFT) /* 0x0000000C */ +#define GRF_GPIO2C_P_GPIO2C2_P_SHIFT (4U) +#define GRF_GPIO2C_P_GPIO2C2_P_MASK (0x3U << GRF_GPIO2C_P_GPIO2C2_P_SHIFT) /* 0x00000030 */ +#define GRF_GPIO2C_P_GPIO2C3_P_SHIFT (6U) +#define GRF_GPIO2C_P_GPIO2C3_P_MASK (0x3U << GRF_GPIO2C_P_GPIO2C3_P_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO2C_P_GPIO2C4_P_SHIFT (8U) +#define GRF_GPIO2C_P_GPIO2C4_P_MASK (0x3U << GRF_GPIO2C_P_GPIO2C4_P_SHIFT) /* 0x00000300 */ +#define GRF_GPIO2C_P_GPIO2C5_P_SHIFT (10U) +#define GRF_GPIO2C_P_GPIO2C5_P_MASK (0x3U << GRF_GPIO2C_P_GPIO2C5_P_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO2C_P_GPIO2C6_P_SHIFT (12U) +#define GRF_GPIO2C_P_GPIO2C6_P_MASK (0x3U << GRF_GPIO2C_P_GPIO2C6_P_SHIFT) /* 0x00003000 */ +#define GRF_GPIO2C_P_GPIO2C7_P_SHIFT (14U) +#define GRF_GPIO2C_P_GPIO2C7_P_MASK (0x3U << GRF_GPIO2C_P_GPIO2C7_P_SHIFT) /* 0x0000C000 */ +/* GPIO2D_P */ +#define GRF_GPIO2D_P_OFFSET (0x4009CU) +#define GRF_GPIO2D_P_GPIO2D0_P_SHIFT (0U) +#define GRF_GPIO2D_P_GPIO2D0_P_MASK (0x3U << GRF_GPIO2D_P_GPIO2D0_P_SHIFT) /* 0x00000003 */ +#define GRF_GPIO2D_P_GPIO2D1_P_SHIFT (2U) +#define GRF_GPIO2D_P_GPIO2D1_P_MASK (0x3U << GRF_GPIO2D_P_GPIO2D1_P_SHIFT) /* 0x0000000C */ +#define GRF_GPIO2D_P_GPIO2D2_P_SHIFT (4U) +#define GRF_GPIO2D_P_GPIO2D2_P_MASK (0x3U << GRF_GPIO2D_P_GPIO2D2_P_SHIFT) /* 0x00000030 */ +#define GRF_GPIO2D_P_GPIO2D3_P_SHIFT (6U) +#define GRF_GPIO2D_P_GPIO2D3_P_MASK (0x3U << GRF_GPIO2D_P_GPIO2D3_P_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO2D_P_GPIO2D4_P_SHIFT (8U) +#define GRF_GPIO2D_P_GPIO2D4_P_MASK (0x3U << GRF_GPIO2D_P_GPIO2D4_P_SHIFT) /* 0x00000300 */ +#define GRF_GPIO2D_P_GPIO2D5_P_SHIFT (10U) +#define GRF_GPIO2D_P_GPIO2D5_P_MASK (0x3U << GRF_GPIO2D_P_GPIO2D5_P_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO2D_P_GPIO2D6_P_SHIFT (12U) +#define GRF_GPIO2D_P_GPIO2D6_P_MASK (0x3U << GRF_GPIO2D_P_GPIO2D6_P_SHIFT) /* 0x00003000 */ +#define GRF_GPIO2D_P_GPIO2D7_P_SHIFT (14U) +#define GRF_GPIO2D_P_GPIO2D7_P_MASK (0x3U << GRF_GPIO2D_P_GPIO2D7_P_SHIFT) /* 0x0000C000 */ +/* GPIO3A_P */ +#define GRF_GPIO3A_P_OFFSET (0x400A0U) +#define GRF_GPIO3A_P_GPIO3A0_P_SHIFT (0U) +#define GRF_GPIO3A_P_GPIO3A0_P_MASK (0x3U << GRF_GPIO3A_P_GPIO3A0_P_SHIFT) /* 0x00000003 */ +#define GRF_GPIO3A_P_GPIO3A1_P_SHIFT (2U) +#define GRF_GPIO3A_P_GPIO3A1_P_MASK (0x3U << GRF_GPIO3A_P_GPIO3A1_P_SHIFT) /* 0x0000000C */ +#define GRF_GPIO3A_P_GPIO3A2_P_SHIFT (4U) +#define GRF_GPIO3A_P_GPIO3A2_P_MASK (0x3U << GRF_GPIO3A_P_GPIO3A2_P_SHIFT) /* 0x00000030 */ +#define GRF_GPIO3A_P_GPIO3A3_P_SHIFT (6U) +#define GRF_GPIO3A_P_GPIO3A3_P_MASK (0x3U << GRF_GPIO3A_P_GPIO3A3_P_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO3A_P_GPIO3A4_P_SHIFT (8U) +#define GRF_GPIO3A_P_GPIO3A4_P_MASK (0x3U << GRF_GPIO3A_P_GPIO3A4_P_SHIFT) /* 0x00000300 */ +#define GRF_GPIO3A_P_GPIO3A5_P_SHIFT (10U) +#define GRF_GPIO3A_P_GPIO3A5_P_MASK (0x3U << GRF_GPIO3A_P_GPIO3A5_P_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO3A_P_GPIO3A6_P_SHIFT (12U) +#define GRF_GPIO3A_P_GPIO3A6_P_MASK (0x3U << GRF_GPIO3A_P_GPIO3A6_P_SHIFT) /* 0x00003000 */ +#define GRF_GPIO3A_P_GPIO3A7_P_SHIFT (14U) +#define GRF_GPIO3A_P_GPIO3A7_P_MASK (0x3U << GRF_GPIO3A_P_GPIO3A7_P_SHIFT) /* 0x0000C000 */ +/* GPIO3B_P */ +#define GRF_GPIO3B_P_OFFSET (0x400A4U) +#define GRF_GPIO3B_P_GPIO3B0_P_SHIFT (0U) +#define GRF_GPIO3B_P_GPIO3B0_P_MASK (0x3U << GRF_GPIO3B_P_GPIO3B0_P_SHIFT) /* 0x00000003 */ +#define GRF_GPIO3B_P_GPIO3B1_P_SHIFT (2U) +#define GRF_GPIO3B_P_GPIO3B1_P_MASK (0x3U << GRF_GPIO3B_P_GPIO3B1_P_SHIFT) /* 0x0000000C */ +#define GRF_GPIO3B_P_GPIO3B2_P_SHIFT (4U) +#define GRF_GPIO3B_P_GPIO3B2_P_MASK (0x3U << GRF_GPIO3B_P_GPIO3B2_P_SHIFT) /* 0x00000030 */ +#define GRF_GPIO3B_P_GPIO3B3_P_SHIFT (6U) +#define GRF_GPIO3B_P_GPIO3B3_P_MASK (0x3U << GRF_GPIO3B_P_GPIO3B3_P_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO3B_P_GPIO3B4_P_SHIFT (8U) +#define GRF_GPIO3B_P_GPIO3B4_P_MASK (0x3U << GRF_GPIO3B_P_GPIO3B4_P_SHIFT) /* 0x00000300 */ +#define GRF_GPIO3B_P_GPIO3B5_P_SHIFT (10U) +#define GRF_GPIO3B_P_GPIO3B5_P_MASK (0x3U << GRF_GPIO3B_P_GPIO3B5_P_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO3B_P_GPIO3B6_P_SHIFT (12U) +#define GRF_GPIO3B_P_GPIO3B6_P_MASK (0x3U << GRF_GPIO3B_P_GPIO3B6_P_SHIFT) /* 0x00003000 */ +#define GRF_GPIO3B_P_GPIO3B7_P_SHIFT (14U) +#define GRF_GPIO3B_P_GPIO3B7_P_MASK (0x3U << GRF_GPIO3B_P_GPIO3B7_P_SHIFT) /* 0x0000C000 */ +/* GPIO3C_P */ +#define GRF_GPIO3C_P_OFFSET (0x400A8U) +#define GRF_GPIO3C_P_GPIO3C0_P_SHIFT (0U) +#define GRF_GPIO3C_P_GPIO3C0_P_MASK (0x3U << GRF_GPIO3C_P_GPIO3C0_P_SHIFT) /* 0x00000003 */ +#define GRF_GPIO3C_P_GPIO3C1_P_SHIFT (2U) +#define GRF_GPIO3C_P_GPIO3C1_P_MASK (0x3U << GRF_GPIO3C_P_GPIO3C1_P_SHIFT) /* 0x0000000C */ +#define GRF_GPIO3C_P_GPIO3C2_P_SHIFT (4U) +#define GRF_GPIO3C_P_GPIO3C2_P_MASK (0x3U << GRF_GPIO3C_P_GPIO3C2_P_SHIFT) /* 0x00000030 */ +#define GRF_GPIO3C_P_GPIO3C3_P_SHIFT (6U) +#define GRF_GPIO3C_P_GPIO3C3_P_MASK (0x3U << GRF_GPIO3C_P_GPIO3C3_P_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO3C_P_GPIO3C4_P_SHIFT (8U) +#define GRF_GPIO3C_P_GPIO3C4_P_MASK (0x3U << GRF_GPIO3C_P_GPIO3C4_P_SHIFT) /* 0x00000300 */ +#define GRF_GPIO3C_P_GPIO3C5_P_SHIFT (10U) +#define GRF_GPIO3C_P_GPIO3C5_P_MASK (0x3U << GRF_GPIO3C_P_GPIO3C5_P_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO3C_P_GPIO3C6_P_SHIFT (12U) +#define GRF_GPIO3C_P_GPIO3C6_P_MASK (0x3U << GRF_GPIO3C_P_GPIO3C6_P_SHIFT) /* 0x00003000 */ +#define GRF_GPIO3C_P_GPIO3C7_P_SHIFT (14U) +#define GRF_GPIO3C_P_GPIO3C7_P_MASK (0x3U << GRF_GPIO3C_P_GPIO3C7_P_SHIFT) /* 0x0000C000 */ +/* GPIO3D_P */ +#define GRF_GPIO3D_P_OFFSET (0x400ACU) +#define GRF_GPIO3D_P_GPIO3D0_P_SHIFT (0U) +#define GRF_GPIO3D_P_GPIO3D0_P_MASK (0x3U << GRF_GPIO3D_P_GPIO3D0_P_SHIFT) /* 0x00000003 */ +#define GRF_GPIO3D_P_GPIO3D1_P_SHIFT (2U) +#define GRF_GPIO3D_P_GPIO3D1_P_MASK (0x3U << GRF_GPIO3D_P_GPIO3D1_P_SHIFT) /* 0x0000000C */ +#define GRF_GPIO3D_P_GPIO3D2_P_SHIFT (4U) +#define GRF_GPIO3D_P_GPIO3D2_P_MASK (0x3U << GRF_GPIO3D_P_GPIO3D2_P_SHIFT) /* 0x00000030 */ +#define GRF_GPIO3D_P_GPIO3D3_P_SHIFT (6U) +#define GRF_GPIO3D_P_GPIO3D3_P_MASK (0x3U << GRF_GPIO3D_P_GPIO3D3_P_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO3D_P_GPIO3D4_P_SHIFT (8U) +#define GRF_GPIO3D_P_GPIO3D4_P_MASK (0x3U << GRF_GPIO3D_P_GPIO3D4_P_SHIFT) /* 0x00000300 */ +#define GRF_GPIO3D_P_GPIO3D5_P_SHIFT (10U) +#define GRF_GPIO3D_P_GPIO3D5_P_MASK (0x3U << GRF_GPIO3D_P_GPIO3D5_P_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO3D_P_GPIO3D6_P_SHIFT (12U) +#define GRF_GPIO3D_P_GPIO3D6_P_MASK (0x3U << GRF_GPIO3D_P_GPIO3D6_P_SHIFT) /* 0x00003000 */ +#define GRF_GPIO3D_P_GPIO3D7_P_SHIFT (14U) +#define GRF_GPIO3D_P_GPIO3D7_P_MASK (0x3U << GRF_GPIO3D_P_GPIO3D7_P_SHIFT) /* 0x0000C000 */ +/* GPIO4A_P */ +#define GRF_GPIO4A_P_OFFSET (0x400B0U) +#define GRF_GPIO4A_P_GPIO4A0_P_SHIFT (0U) +#define GRF_GPIO4A_P_GPIO4A0_P_MASK (0x3U << GRF_GPIO4A_P_GPIO4A0_P_SHIFT) /* 0x00000003 */ +#define GRF_GPIO4A_P_GPIO4A1_P_SHIFT (2U) +#define GRF_GPIO4A_P_GPIO4A1_P_MASK (0x3U << GRF_GPIO4A_P_GPIO4A1_P_SHIFT) /* 0x0000000C */ +#define GRF_GPIO4A_P_GPIO4A2_P_SHIFT (4U) +#define GRF_GPIO4A_P_GPIO4A2_P_MASK (0x3U << GRF_GPIO4A_P_GPIO4A2_P_SHIFT) /* 0x00000030 */ +#define GRF_GPIO4A_P_GPIO4A3_P_SHIFT (6U) +#define GRF_GPIO4A_P_GPIO4A3_P_MASK (0x3U << GRF_GPIO4A_P_GPIO4A3_P_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO4A_P_GPIO4A4_P_SHIFT (8U) +#define GRF_GPIO4A_P_GPIO4A4_P_MASK (0x3U << GRF_GPIO4A_P_GPIO4A4_P_SHIFT) /* 0x00000300 */ +#define GRF_GPIO4A_P_GPIO4A5_P_SHIFT (10U) +#define GRF_GPIO4A_P_GPIO4A5_P_MASK (0x3U << GRF_GPIO4A_P_GPIO4A5_P_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO4A_P_GPIO4A6_P_SHIFT (12U) +#define GRF_GPIO4A_P_GPIO4A6_P_MASK (0x3U << GRF_GPIO4A_P_GPIO4A6_P_SHIFT) /* 0x00003000 */ +#define GRF_GPIO4A_P_GPIO4A7_P_SHIFT (14U) +#define GRF_GPIO4A_P_GPIO4A7_P_MASK (0x3U << GRF_GPIO4A_P_GPIO4A7_P_SHIFT) /* 0x0000C000 */ +/* GPIO4B_P */ +#define GRF_GPIO4B_P_OFFSET (0x400B4U) +#define GRF_GPIO4B_P_GPIO4B0_P_SHIFT (0U) +#define GRF_GPIO4B_P_GPIO4B0_P_MASK (0x3U << GRF_GPIO4B_P_GPIO4B0_P_SHIFT) /* 0x00000003 */ +#define GRF_GPIO4B_P_GPIO4B1_P_SHIFT (2U) +#define GRF_GPIO4B_P_GPIO4B1_P_MASK (0x3U << GRF_GPIO4B_P_GPIO4B1_P_SHIFT) /* 0x0000000C */ +#define GRF_GPIO4B_P_GPIO4B2_P_SHIFT (4U) +#define GRF_GPIO4B_P_GPIO4B2_P_MASK (0x3U << GRF_GPIO4B_P_GPIO4B2_P_SHIFT) /* 0x00000030 */ +#define GRF_GPIO4B_P_GPIO4B3_P_SHIFT (6U) +#define GRF_GPIO4B_P_GPIO4B3_P_MASK (0x3U << GRF_GPIO4B_P_GPIO4B3_P_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO4B_P_GPIO4B4_P_SHIFT (8U) +#define GRF_GPIO4B_P_GPIO4B4_P_MASK (0x3U << GRF_GPIO4B_P_GPIO4B4_P_SHIFT) /* 0x00000300 */ +#define GRF_GPIO4B_P_GPIO4B5_P_SHIFT (10U) +#define GRF_GPIO4B_P_GPIO4B5_P_MASK (0x3U << GRF_GPIO4B_P_GPIO4B5_P_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO4B_P_GPIO4B6_P_SHIFT (12U) +#define GRF_GPIO4B_P_GPIO4B6_P_MASK (0x3U << GRF_GPIO4B_P_GPIO4B6_P_SHIFT) /* 0x00003000 */ +#define GRF_GPIO4B_P_GPIO4B7_P_SHIFT (14U) +#define GRF_GPIO4B_P_GPIO4B7_P_MASK (0x3U << GRF_GPIO4B_P_GPIO4B7_P_SHIFT) /* 0x0000C000 */ +/* GPIO4C_P */ +#define GRF_GPIO4C_P_OFFSET (0x400B8U) +#define GRF_GPIO4C_P_GPIO4C0_P_SHIFT (0U) +#define GRF_GPIO4C_P_GPIO4C0_P_MASK (0x3U << GRF_GPIO4C_P_GPIO4C0_P_SHIFT) /* 0x00000003 */ +#define GRF_GPIO4C_P_GPIO4C1_P_SHIFT (2U) +#define GRF_GPIO4C_P_GPIO4C1_P_MASK (0x3U << GRF_GPIO4C_P_GPIO4C1_P_SHIFT) /* 0x0000000C */ +#define GRF_GPIO4C_P_GPIO4C2_P_SHIFT (4U) +#define GRF_GPIO4C_P_GPIO4C2_P_MASK (0x3U << GRF_GPIO4C_P_GPIO4C2_P_SHIFT) /* 0x00000030 */ +#define GRF_GPIO4C_P_GPIO4C3_P_SHIFT (6U) +#define GRF_GPIO4C_P_GPIO4C3_P_MASK (0x3U << GRF_GPIO4C_P_GPIO4C3_P_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO4C_P_GPIO4C4_P_SHIFT (8U) +#define GRF_GPIO4C_P_GPIO4C4_P_MASK (0x3U << GRF_GPIO4C_P_GPIO4C4_P_SHIFT) /* 0x00000300 */ +#define GRF_GPIO4C_P_GPIO4C5_P_SHIFT (10U) +#define GRF_GPIO4C_P_GPIO4C5_P_MASK (0x3U << GRF_GPIO4C_P_GPIO4C5_P_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO4C_P_GPIO4C6_P_SHIFT (12U) +#define GRF_GPIO4C_P_GPIO4C6_P_MASK (0x3U << GRF_GPIO4C_P_GPIO4C6_P_SHIFT) /* 0x00003000 */ +#define GRF_GPIO4C_P_GPIO4C7_P_SHIFT (14U) +#define GRF_GPIO4C_P_GPIO4C7_P_MASK (0x3U << GRF_GPIO4C_P_GPIO4C7_P_SHIFT) /* 0x0000C000 */ +/* GPIO4D_P */ +#define GRF_GPIO4D_P_OFFSET (0x400BCU) +#define GRF_GPIO4D_P_GPIO4D0_P_SHIFT (0U) +#define GRF_GPIO4D_P_GPIO4D0_P_MASK (0x3U << GRF_GPIO4D_P_GPIO4D0_P_SHIFT) /* 0x00000003 */ +#define GRF_GPIO4D_P_GPIO4D1_P_SHIFT (2U) +#define GRF_GPIO4D_P_GPIO4D1_P_MASK (0x3U << GRF_GPIO4D_P_GPIO4D1_P_SHIFT) /* 0x0000000C */ +#define GRF_GPIO4D_P_GPIO4D2_P_SHIFT (4U) +#define GRF_GPIO4D_P_GPIO4D2_P_MASK (0x3U << GRF_GPIO4D_P_GPIO4D2_P_SHIFT) /* 0x00000030 */ +#define GRF_GPIO4D_P_GPIO4D3_P_SHIFT (6U) +#define GRF_GPIO4D_P_GPIO4D3_P_MASK (0x3U << GRF_GPIO4D_P_GPIO4D3_P_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO4D_P_GPIO4D4_P_SHIFT (8U) +#define GRF_GPIO4D_P_GPIO4D4_P_MASK (0x3U << GRF_GPIO4D_P_GPIO4D4_P_SHIFT) /* 0x00000300 */ +#define GRF_GPIO4D_P_GPIO4D5_P_SHIFT (10U) +#define GRF_GPIO4D_P_GPIO4D5_P_MASK (0x3U << GRF_GPIO4D_P_GPIO4D5_P_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO4D_P_GPIO4D6_P_SHIFT (12U) +#define GRF_GPIO4D_P_GPIO4D6_P_MASK (0x3U << GRF_GPIO4D_P_GPIO4D6_P_SHIFT) /* 0x00003000 */ +#define GRF_GPIO4D_P_GPIO4D7_P_SHIFT (14U) +#define GRF_GPIO4D_P_GPIO4D7_P_MASK (0x3U << GRF_GPIO4D_P_GPIO4D7_P_SHIFT) /* 0x0000C000 */ +/* GPIO1A_IE */ +#define GRF_GPIO1A_IE_OFFSET (0x400C0U) +#define GRF_GPIO1A_IE_GPIO1A0_IE_SHIFT (0U) +#define GRF_GPIO1A_IE_GPIO1A0_IE_MASK (0x3U << GRF_GPIO1A_IE_GPIO1A0_IE_SHIFT) /* 0x00000003 */ +#define GRF_GPIO1A_IE_GPIO1A1_IE_SHIFT (2U) +#define GRF_GPIO1A_IE_GPIO1A1_IE_MASK (0x3U << GRF_GPIO1A_IE_GPIO1A1_IE_SHIFT) /* 0x0000000C */ +#define GRF_GPIO1A_IE_GPIO1A2_IE_SHIFT (4U) +#define GRF_GPIO1A_IE_GPIO1A2_IE_MASK (0x3U << GRF_GPIO1A_IE_GPIO1A2_IE_SHIFT) /* 0x00000030 */ +#define GRF_GPIO1A_IE_GPIO1A3_IE_SHIFT (6U) +#define GRF_GPIO1A_IE_GPIO1A3_IE_MASK (0x3U << GRF_GPIO1A_IE_GPIO1A3_IE_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO1A_IE_GPIO1A4_IE_SHIFT (8U) +#define GRF_GPIO1A_IE_GPIO1A4_IE_MASK (0x3U << GRF_GPIO1A_IE_GPIO1A4_IE_SHIFT) /* 0x00000300 */ +#define GRF_GPIO1A_IE_GPIO1A5_IE_SHIFT (10U) +#define GRF_GPIO1A_IE_GPIO1A5_IE_MASK (0x3U << GRF_GPIO1A_IE_GPIO1A5_IE_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO1A_IE_GPIO1A6_IE_SHIFT (12U) +#define GRF_GPIO1A_IE_GPIO1A6_IE_MASK (0x3U << GRF_GPIO1A_IE_GPIO1A6_IE_SHIFT) /* 0x00003000 */ +#define GRF_GPIO1A_IE_GPIO1A7_IE_SHIFT (14U) +#define GRF_GPIO1A_IE_GPIO1A7_IE_MASK (0x3U << GRF_GPIO1A_IE_GPIO1A7_IE_SHIFT) /* 0x0000C000 */ +/* GPIO1B_IE */ +#define GRF_GPIO1B_IE_OFFSET (0x400C4U) +#define GRF_GPIO1B_IE_GPIO1B0_IE_SHIFT (0U) +#define GRF_GPIO1B_IE_GPIO1B0_IE_MASK (0x3U << GRF_GPIO1B_IE_GPIO1B0_IE_SHIFT) /* 0x00000003 */ +#define GRF_GPIO1B_IE_GPIO1B1_IE_SHIFT (2U) +#define GRF_GPIO1B_IE_GPIO1B1_IE_MASK (0x3U << GRF_GPIO1B_IE_GPIO1B1_IE_SHIFT) /* 0x0000000C */ +#define GRF_GPIO1B_IE_GPIO1B2_IE_SHIFT (4U) +#define GRF_GPIO1B_IE_GPIO1B2_IE_MASK (0x3U << GRF_GPIO1B_IE_GPIO1B2_IE_SHIFT) /* 0x00000030 */ +#define GRF_GPIO1B_IE_GPIO1B3_IE_SHIFT (6U) +#define GRF_GPIO1B_IE_GPIO1B3_IE_MASK (0x3U << GRF_GPIO1B_IE_GPIO1B3_IE_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO1B_IE_GPIO1B4_IE_SHIFT (8U) +#define GRF_GPIO1B_IE_GPIO1B4_IE_MASK (0x3U << GRF_GPIO1B_IE_GPIO1B4_IE_SHIFT) /* 0x00000300 */ +#define GRF_GPIO1B_IE_GPIO1B5_IE_SHIFT (10U) +#define GRF_GPIO1B_IE_GPIO1B5_IE_MASK (0x3U << GRF_GPIO1B_IE_GPIO1B5_IE_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO1B_IE_GPIO1B6_IE_SHIFT (12U) +#define GRF_GPIO1B_IE_GPIO1B6_IE_MASK (0x3U << GRF_GPIO1B_IE_GPIO1B6_IE_SHIFT) /* 0x00003000 */ +#define GRF_GPIO1B_IE_GPIO1B7_IE_SHIFT (14U) +#define GRF_GPIO1B_IE_GPIO1B7_IE_MASK (0x3U << GRF_GPIO1B_IE_GPIO1B7_IE_SHIFT) /* 0x0000C000 */ +/* GPIO1C_IE */ +#define GRF_GPIO1C_IE_OFFSET (0x400C8U) +#define GRF_GPIO1C_IE_GPIO1C0_IE_SHIFT (0U) +#define GRF_GPIO1C_IE_GPIO1C0_IE_MASK (0x3U << GRF_GPIO1C_IE_GPIO1C0_IE_SHIFT) /* 0x00000003 */ +#define GRF_GPIO1C_IE_GPIO1C1_IE_SHIFT (2U) +#define GRF_GPIO1C_IE_GPIO1C1_IE_MASK (0x3U << GRF_GPIO1C_IE_GPIO1C1_IE_SHIFT) /* 0x0000000C */ +#define GRF_GPIO1C_IE_GPIO1C2_IE_SHIFT (4U) +#define GRF_GPIO1C_IE_GPIO1C2_IE_MASK (0x3U << GRF_GPIO1C_IE_GPIO1C2_IE_SHIFT) /* 0x00000030 */ +#define GRF_GPIO1C_IE_GPIO1C3_IE_SHIFT (6U) +#define GRF_GPIO1C_IE_GPIO1C3_IE_MASK (0x3U << GRF_GPIO1C_IE_GPIO1C3_IE_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO1C_IE_GPIO1C4_IE_SHIFT (8U) +#define GRF_GPIO1C_IE_GPIO1C4_IE_MASK (0x3U << GRF_GPIO1C_IE_GPIO1C4_IE_SHIFT) /* 0x00000300 */ +#define GRF_GPIO1C_IE_GPIO1C5_IE_SHIFT (10U) +#define GRF_GPIO1C_IE_GPIO1C5_IE_MASK (0x3U << GRF_GPIO1C_IE_GPIO1C5_IE_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO1C_IE_GPIO1C6_IE_SHIFT (12U) +#define GRF_GPIO1C_IE_GPIO1C6_IE_MASK (0x3U << GRF_GPIO1C_IE_GPIO1C6_IE_SHIFT) /* 0x00003000 */ +#define GRF_GPIO1C_IE_GPIO1C7_IE_SHIFT (14U) +#define GRF_GPIO1C_IE_GPIO1C7_IE_MASK (0x3U << GRF_GPIO1C_IE_GPIO1C7_IE_SHIFT) /* 0x0000C000 */ +/* GPIO1D_IE */ +#define GRF_GPIO1D_IE_OFFSET (0x400CCU) +#define GRF_GPIO1D_IE_GPIO1D0_IE_SHIFT (0U) +#define GRF_GPIO1D_IE_GPIO1D0_IE_MASK (0x3U << GRF_GPIO1D_IE_GPIO1D0_IE_SHIFT) /* 0x00000003 */ +#define GRF_GPIO1D_IE_GPIO1D1_IE_SHIFT (2U) +#define GRF_GPIO1D_IE_GPIO1D1_IE_MASK (0x3U << GRF_GPIO1D_IE_GPIO1D1_IE_SHIFT) /* 0x0000000C */ +#define GRF_GPIO1D_IE_GPIO1D2_IE_SHIFT (4U) +#define GRF_GPIO1D_IE_GPIO1D2_IE_MASK (0x3U << GRF_GPIO1D_IE_GPIO1D2_IE_SHIFT) /* 0x00000030 */ +#define GRF_GPIO1D_IE_GPIO1D3_IE_SHIFT (6U) +#define GRF_GPIO1D_IE_GPIO1D3_IE_MASK (0x3U << GRF_GPIO1D_IE_GPIO1D3_IE_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO1D_IE_GPIO1D4_IE_SHIFT (8U) +#define GRF_GPIO1D_IE_GPIO1D4_IE_MASK (0x3U << GRF_GPIO1D_IE_GPIO1D4_IE_SHIFT) /* 0x00000300 */ +#define GRF_GPIO1D_IE_GPIO1D5_IE_SHIFT (10U) +#define GRF_GPIO1D_IE_GPIO1D5_IE_MASK (0x3U << GRF_GPIO1D_IE_GPIO1D5_IE_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO1D_IE_GPIO1D6_IE_SHIFT (12U) +#define GRF_GPIO1D_IE_GPIO1D6_IE_MASK (0x3U << GRF_GPIO1D_IE_GPIO1D6_IE_SHIFT) /* 0x00003000 */ +#define GRF_GPIO1D_IE_GPIO1D7_IE_SHIFT (14U) +#define GRF_GPIO1D_IE_GPIO1D7_IE_MASK (0x3U << GRF_GPIO1D_IE_GPIO1D7_IE_SHIFT) /* 0x0000C000 */ +/* GPIO2A_IE */ +#define GRF_GPIO2A_IE_OFFSET (0x400D0U) +#define GRF_GPIO2A_IE_GPIO2A0_IE_SHIFT (0U) +#define GRF_GPIO2A_IE_GPIO2A0_IE_MASK (0x3U << GRF_GPIO2A_IE_GPIO2A0_IE_SHIFT) /* 0x00000003 */ +#define GRF_GPIO2A_IE_GPIO2A1_IE_SHIFT (2U) +#define GRF_GPIO2A_IE_GPIO2A1_IE_MASK (0x3U << GRF_GPIO2A_IE_GPIO2A1_IE_SHIFT) /* 0x0000000C */ +#define GRF_GPIO2A_IE_GPIO2A2_IE_SHIFT (4U) +#define GRF_GPIO2A_IE_GPIO2A2_IE_MASK (0x3U << GRF_GPIO2A_IE_GPIO2A2_IE_SHIFT) /* 0x00000030 */ +#define GRF_GPIO2A_IE_GPIO2A3_IE_SHIFT (6U) +#define GRF_GPIO2A_IE_GPIO2A3_IE_MASK (0x3U << GRF_GPIO2A_IE_GPIO2A3_IE_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO2A_IE_GPIO2A4_IE_SHIFT (8U) +#define GRF_GPIO2A_IE_GPIO2A4_IE_MASK (0x3U << GRF_GPIO2A_IE_GPIO2A4_IE_SHIFT) /* 0x00000300 */ +#define GRF_GPIO2A_IE_GPIO2A5_IE_SHIFT (10U) +#define GRF_GPIO2A_IE_GPIO2A5_IE_MASK (0x3U << GRF_GPIO2A_IE_GPIO2A5_IE_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO2A_IE_GPIO2A6_IE_SHIFT (12U) +#define GRF_GPIO2A_IE_GPIO2A6_IE_MASK (0x3U << GRF_GPIO2A_IE_GPIO2A6_IE_SHIFT) /* 0x00003000 */ +#define GRF_GPIO2A_IE_GPIO2A7_IE_SHIFT (14U) +#define GRF_GPIO2A_IE_GPIO2A7_IE_MASK (0x3U << GRF_GPIO2A_IE_GPIO2A7_IE_SHIFT) /* 0x0000C000 */ +/* GPIO2B_IE */ +#define GRF_GPIO2B_IE_OFFSET (0x400D4U) +#define GRF_GPIO2B_IE_GPIO2B0_IE_SHIFT (0U) +#define GRF_GPIO2B_IE_GPIO2B0_IE_MASK (0x3U << GRF_GPIO2B_IE_GPIO2B0_IE_SHIFT) /* 0x00000003 */ +#define GRF_GPIO2B_IE_GPIO2B1_IE_SHIFT (2U) +#define GRF_GPIO2B_IE_GPIO2B1_IE_MASK (0x3U << GRF_GPIO2B_IE_GPIO2B1_IE_SHIFT) /* 0x0000000C */ +#define GRF_GPIO2B_IE_GPIO2B2_IE_SHIFT (4U) +#define GRF_GPIO2B_IE_GPIO2B2_IE_MASK (0x3U << GRF_GPIO2B_IE_GPIO2B2_IE_SHIFT) /* 0x00000030 */ +#define GRF_GPIO2B_IE_GPIO2B3_IE_SHIFT (6U) +#define GRF_GPIO2B_IE_GPIO2B3_IE_MASK (0x3U << GRF_GPIO2B_IE_GPIO2B3_IE_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO2B_IE_GPIO2B4_IE_SHIFT (8U) +#define GRF_GPIO2B_IE_GPIO2B4_IE_MASK (0x3U << GRF_GPIO2B_IE_GPIO2B4_IE_SHIFT) /* 0x00000300 */ +#define GRF_GPIO2B_IE_GPIO2B5_IE_SHIFT (10U) +#define GRF_GPIO2B_IE_GPIO2B5_IE_MASK (0x3U << GRF_GPIO2B_IE_GPIO2B5_IE_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO2B_IE_GPIO2B6_IE_SHIFT (12U) +#define GRF_GPIO2B_IE_GPIO2B6_IE_MASK (0x3U << GRF_GPIO2B_IE_GPIO2B6_IE_SHIFT) /* 0x00003000 */ +#define GRF_GPIO2B_IE_GPIO2B7_IE_SHIFT (14U) +#define GRF_GPIO2B_IE_GPIO2B7_IE_MASK (0x3U << GRF_GPIO2B_IE_GPIO2B7_IE_SHIFT) /* 0x0000C000 */ +/* GPIO2C_IE */ +#define GRF_GPIO2C_IE_OFFSET (0x400D8U) +#define GRF_GPIO2C_IE_GPIO2C0_IE_SHIFT (0U) +#define GRF_GPIO2C_IE_GPIO2C0_IE_MASK (0x3U << GRF_GPIO2C_IE_GPIO2C0_IE_SHIFT) /* 0x00000003 */ +#define GRF_GPIO2C_IE_GPIO2C1_IE_SHIFT (2U) +#define GRF_GPIO2C_IE_GPIO2C1_IE_MASK (0x3U << GRF_GPIO2C_IE_GPIO2C1_IE_SHIFT) /* 0x0000000C */ +#define GRF_GPIO2C_IE_GPIO2C2_IE_SHIFT (4U) +#define GRF_GPIO2C_IE_GPIO2C2_IE_MASK (0x3U << GRF_GPIO2C_IE_GPIO2C2_IE_SHIFT) /* 0x00000030 */ +#define GRF_GPIO2C_IE_GPIO2C3_IE_SHIFT (6U) +#define GRF_GPIO2C_IE_GPIO2C3_IE_MASK (0x3U << GRF_GPIO2C_IE_GPIO2C3_IE_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO2C_IE_GPIO2C4_IE_SHIFT (8U) +#define GRF_GPIO2C_IE_GPIO2C4_IE_MASK (0x3U << GRF_GPIO2C_IE_GPIO2C4_IE_SHIFT) /* 0x00000300 */ +#define GRF_GPIO2C_IE_GPIO2C5_IE_SHIFT (10U) +#define GRF_GPIO2C_IE_GPIO2C5_IE_MASK (0x3U << GRF_GPIO2C_IE_GPIO2C5_IE_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO2C_IE_GPIO2C6_IE_SHIFT (12U) +#define GRF_GPIO2C_IE_GPIO2C6_IE_MASK (0x3U << GRF_GPIO2C_IE_GPIO2C6_IE_SHIFT) /* 0x00003000 */ +#define GRF_GPIO2C_IE_GPIO2C7_IE_SHIFT (14U) +#define GRF_GPIO2C_IE_GPIO2C7_IE_MASK (0x3U << GRF_GPIO2C_IE_GPIO2C7_IE_SHIFT) /* 0x0000C000 */ +/* GPIO2D_IE */ +#define GRF_GPIO2D_IE_OFFSET (0x400DCU) +#define GRF_GPIO2D_IE_GPIO2D0_IE_SHIFT (0U) +#define GRF_GPIO2D_IE_GPIO2D0_IE_MASK (0x3U << GRF_GPIO2D_IE_GPIO2D0_IE_SHIFT) /* 0x00000003 */ +#define GRF_GPIO2D_IE_GPIO2D1_IE_SHIFT (2U) +#define GRF_GPIO2D_IE_GPIO2D1_IE_MASK (0x3U << GRF_GPIO2D_IE_GPIO2D1_IE_SHIFT) /* 0x0000000C */ +#define GRF_GPIO2D_IE_GPIO2D2_IE_SHIFT (4U) +#define GRF_GPIO2D_IE_GPIO2D2_IE_MASK (0x3U << GRF_GPIO2D_IE_GPIO2D2_IE_SHIFT) /* 0x00000030 */ +#define GRF_GPIO2D_IE_GPIO2D3_IE_SHIFT (6U) +#define GRF_GPIO2D_IE_GPIO2D3_IE_MASK (0x3U << GRF_GPIO2D_IE_GPIO2D3_IE_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO2D_IE_GPIO2D4_IE_SHIFT (8U) +#define GRF_GPIO2D_IE_GPIO2D4_IE_MASK (0x3U << GRF_GPIO2D_IE_GPIO2D4_IE_SHIFT) /* 0x00000300 */ +#define GRF_GPIO2D_IE_GPIO2A5_IE_SHIFT (10U) +#define GRF_GPIO2D_IE_GPIO2A5_IE_MASK (0x3U << GRF_GPIO2D_IE_GPIO2A5_IE_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO2D_IE_GPIO2A6_IE_SHIFT (12U) +#define GRF_GPIO2D_IE_GPIO2A6_IE_MASK (0x3U << GRF_GPIO2D_IE_GPIO2A6_IE_SHIFT) /* 0x00003000 */ +#define GRF_GPIO2D_IE_GPIO2D7_IE_SHIFT (14U) +#define GRF_GPIO2D_IE_GPIO2D7_IE_MASK (0x3U << GRF_GPIO2D_IE_GPIO2D7_IE_SHIFT) /* 0x0000C000 */ +/* GPIO3A_IE */ +#define GRF_GPIO3A_IE_OFFSET (0x400E0U) +#define GRF_GPIO3A_IE_GPIO3A0_IE_SHIFT (0U) +#define GRF_GPIO3A_IE_GPIO3A0_IE_MASK (0x3U << GRF_GPIO3A_IE_GPIO3A0_IE_SHIFT) /* 0x00000003 */ +#define GRF_GPIO3A_IE_GPIO3A1_IE_SHIFT (2U) +#define GRF_GPIO3A_IE_GPIO3A1_IE_MASK (0x3U << GRF_GPIO3A_IE_GPIO3A1_IE_SHIFT) /* 0x0000000C */ +#define GRF_GPIO3A_IE_GPIO3A2_IE_SHIFT (4U) +#define GRF_GPIO3A_IE_GPIO3A2_IE_MASK (0x3U << GRF_GPIO3A_IE_GPIO3A2_IE_SHIFT) /* 0x00000030 */ +#define GRF_GPIO3A_IE_GPIO3A3_IE_SHIFT (6U) +#define GRF_GPIO3A_IE_GPIO3A3_IE_MASK (0x3U << GRF_GPIO3A_IE_GPIO3A3_IE_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO3A_IE_GPIO3A4_IE_SHIFT (8U) +#define GRF_GPIO3A_IE_GPIO3A4_IE_MASK (0x3U << GRF_GPIO3A_IE_GPIO3A4_IE_SHIFT) /* 0x00000300 */ +#define GRF_GPIO3A_IE_GPIO3A5_IE_SHIFT (10U) +#define GRF_GPIO3A_IE_GPIO3A5_IE_MASK (0x3U << GRF_GPIO3A_IE_GPIO3A5_IE_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO3A_IE_GPIO3A6_IE_SHIFT (12U) +#define GRF_GPIO3A_IE_GPIO3A6_IE_MASK (0x3U << GRF_GPIO3A_IE_GPIO3A6_IE_SHIFT) /* 0x00003000 */ +#define GRF_GPIO3A_IE_GPIO3A7_IE_SHIFT (14U) +#define GRF_GPIO3A_IE_GPIO3A7_IE_MASK (0x3U << GRF_GPIO3A_IE_GPIO3A7_IE_SHIFT) /* 0x0000C000 */ +/* GPIO3B_IE */ +#define GRF_GPIO3B_IE_OFFSET (0x400E4U) +#define GRF_GPIO3B_IE_GPIO3B0_IE_SHIFT (0U) +#define GRF_GPIO3B_IE_GPIO3B0_IE_MASK (0x3U << GRF_GPIO3B_IE_GPIO3B0_IE_SHIFT) /* 0x00000003 */ +#define GRF_GPIO3B_IE_GPIO3B1_IE_SHIFT (2U) +#define GRF_GPIO3B_IE_GPIO3B1_IE_MASK (0x3U << GRF_GPIO3B_IE_GPIO3B1_IE_SHIFT) /* 0x0000000C */ +#define GRF_GPIO3B_IE_GPIO3B2_IE_SHIFT (4U) +#define GRF_GPIO3B_IE_GPIO3B2_IE_MASK (0x3U << GRF_GPIO3B_IE_GPIO3B2_IE_SHIFT) /* 0x00000030 */ +#define GRF_GPIO3B_IE_GPIO3B3_IE_SHIFT (6U) +#define GRF_GPIO3B_IE_GPIO3B3_IE_MASK (0x3U << GRF_GPIO3B_IE_GPIO3B3_IE_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO3B_IE_GPIO3B4_IE_SHIFT (8U) +#define GRF_GPIO3B_IE_GPIO3B4_IE_MASK (0x3U << GRF_GPIO3B_IE_GPIO3B4_IE_SHIFT) /* 0x00000300 */ +#define GRF_GPIO3B_IE_GPIO3B5_IE_SHIFT (10U) +#define GRF_GPIO3B_IE_GPIO3B5_IE_MASK (0x3U << GRF_GPIO3B_IE_GPIO3B5_IE_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO3B_IE_GPIO3B6_IE_SHIFT (12U) +#define GRF_GPIO3B_IE_GPIO3B6_IE_MASK (0x3U << GRF_GPIO3B_IE_GPIO3B6_IE_SHIFT) /* 0x00003000 */ +#define GRF_GPIO3B_IE_GPIO3B7_IE_SHIFT (14U) +#define GRF_GPIO3B_IE_GPIO3B7_IE_MASK (0x3U << GRF_GPIO3B_IE_GPIO3B7_IE_SHIFT) /* 0x0000C000 */ +/* GPIO3C_IE */ +#define GRF_GPIO3C_IE_OFFSET (0x400E8U) +#define GRF_GPIO3C_IE_GPIO3C0_IE_SHIFT (0U) +#define GRF_GPIO3C_IE_GPIO3C0_IE_MASK (0x3U << GRF_GPIO3C_IE_GPIO3C0_IE_SHIFT) /* 0x00000003 */ +#define GRF_GPIO3C_IE_GPIO3C1_IE_SHIFT (2U) +#define GRF_GPIO3C_IE_GPIO3C1_IE_MASK (0x3U << GRF_GPIO3C_IE_GPIO3C1_IE_SHIFT) /* 0x0000000C */ +#define GRF_GPIO3C_IE_GPIO3C2_IE_SHIFT (4U) +#define GRF_GPIO3C_IE_GPIO3C2_IE_MASK (0x3U << GRF_GPIO3C_IE_GPIO3C2_IE_SHIFT) /* 0x00000030 */ +#define GRF_GPIO3C_IE_GPIO3C3_IE_SHIFT (6U) +#define GRF_GPIO3C_IE_GPIO3C3_IE_MASK (0x3U << GRF_GPIO3C_IE_GPIO3C3_IE_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO3C_IE_GPIO3C4_IE_SHIFT (8U) +#define GRF_GPIO3C_IE_GPIO3C4_IE_MASK (0x3U << GRF_GPIO3C_IE_GPIO3C4_IE_SHIFT) /* 0x00000300 */ +#define GRF_GPIO3C_IE_GPIO3C5_IE_SHIFT (10U) +#define GRF_GPIO3C_IE_GPIO3C5_IE_MASK (0x3U << GRF_GPIO3C_IE_GPIO3C5_IE_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO3C_IE_GPIO3C6_IE_SHIFT (12U) +#define GRF_GPIO3C_IE_GPIO3C6_IE_MASK (0x3U << GRF_GPIO3C_IE_GPIO3C6_IE_SHIFT) /* 0x00003000 */ +#define GRF_GPIO3C_IE_GPIO3C7_IE_SHIFT (14U) +#define GRF_GPIO3C_IE_GPIO3C7_IE_MASK (0x3U << GRF_GPIO3C_IE_GPIO3C7_IE_SHIFT) /* 0x0000C000 */ +/* GPIO3D_IE */ +#define GRF_GPIO3D_IE_OFFSET (0x400ECU) +#define GRF_GPIO3D_IE_GPIO3D0_IE_SHIFT (0U) +#define GRF_GPIO3D_IE_GPIO3D0_IE_MASK (0x3U << GRF_GPIO3D_IE_GPIO3D0_IE_SHIFT) /* 0x00000003 */ +#define GRF_GPIO3D_IE_GPIO3D1_IE_SHIFT (2U) +#define GRF_GPIO3D_IE_GPIO3D1_IE_MASK (0x3U << GRF_GPIO3D_IE_GPIO3D1_IE_SHIFT) /* 0x0000000C */ +#define GRF_GPIO3D_IE_GPIO3D2_IE_SHIFT (4U) +#define GRF_GPIO3D_IE_GPIO3D2_IE_MASK (0x3U << GRF_GPIO3D_IE_GPIO3D2_IE_SHIFT) /* 0x00000030 */ +#define GRF_GPIO3D_IE_GPIO3D3_IE_SHIFT (6U) +#define GRF_GPIO3D_IE_GPIO3D3_IE_MASK (0x3U << GRF_GPIO3D_IE_GPIO3D3_IE_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO3D_IE_GPIO3D4_IE_SHIFT (8U) +#define GRF_GPIO3D_IE_GPIO3D4_IE_MASK (0x3U << GRF_GPIO3D_IE_GPIO3D4_IE_SHIFT) /* 0x00000300 */ +#define GRF_GPIO3D_IE_GPIO3D5_IE_SHIFT (10U) +#define GRF_GPIO3D_IE_GPIO3D5_IE_MASK (0x3U << GRF_GPIO3D_IE_GPIO3D5_IE_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO3D_IE_GPIO3D6_IE_SHIFT (12U) +#define GRF_GPIO3D_IE_GPIO3D6_IE_MASK (0x3U << GRF_GPIO3D_IE_GPIO3D6_IE_SHIFT) /* 0x00003000 */ +#define GRF_GPIO3D_IE_GPIO3D7_IE_SHIFT (14U) +#define GRF_GPIO3D_IE_GPIO3D7_IE_MASK (0x3U << GRF_GPIO3D_IE_GPIO3D7_IE_SHIFT) /* 0x0000C000 */ +/* GPIO4A_IE */ +#define GRF_GPIO4A_IE_OFFSET (0x400F0U) +#define GRF_GPIO4A_IE_GPIO4A0_IE_SHIFT (0U) +#define GRF_GPIO4A_IE_GPIO4A0_IE_MASK (0x3U << GRF_GPIO4A_IE_GPIO4A0_IE_SHIFT) /* 0x00000003 */ +#define GRF_GPIO4A_IE_GPIO4A1_IE_SHIFT (2U) +#define GRF_GPIO4A_IE_GPIO4A1_IE_MASK (0x3U << GRF_GPIO4A_IE_GPIO4A1_IE_SHIFT) /* 0x0000000C */ +#define GRF_GPIO4A_IE_GPIO4A2_IE_SHIFT (4U) +#define GRF_GPIO4A_IE_GPIO4A2_IE_MASK (0x3U << GRF_GPIO4A_IE_GPIO4A2_IE_SHIFT) /* 0x00000030 */ +#define GRF_GPIO4A_IE_GPIO4A3_IE_SHIFT (6U) +#define GRF_GPIO4A_IE_GPIO4A3_IE_MASK (0x3U << GRF_GPIO4A_IE_GPIO4A3_IE_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO4A_IE_GPIO4A4_IE_SHIFT (8U) +#define GRF_GPIO4A_IE_GPIO4A4_IE_MASK (0x3U << GRF_GPIO4A_IE_GPIO4A4_IE_SHIFT) /* 0x00000300 */ +#define GRF_GPIO4A_IE_GPIO4A5_IE_SHIFT (10U) +#define GRF_GPIO4A_IE_GPIO4A5_IE_MASK (0x3U << GRF_GPIO4A_IE_GPIO4A5_IE_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO4A_IE_GPIO4A6_IE_SHIFT (12U) +#define GRF_GPIO4A_IE_GPIO4A6_IE_MASK (0x3U << GRF_GPIO4A_IE_GPIO4A6_IE_SHIFT) /* 0x00003000 */ +#define GRF_GPIO4A_IE_GPIO4A7_IE_SHIFT (14U) +#define GRF_GPIO4A_IE_GPIO4A7_IE_MASK (0x3U << GRF_GPIO4A_IE_GPIO4A7_IE_SHIFT) /* 0x0000C000 */ +/* GPIO4B_IE */ +#define GRF_GPIO4B_IE_OFFSET (0x400F4U) +#define GRF_GPIO4B_IE_GPIO4B0_IE_SHIFT (0U) +#define GRF_GPIO4B_IE_GPIO4B0_IE_MASK (0x3U << GRF_GPIO4B_IE_GPIO4B0_IE_SHIFT) /* 0x00000003 */ +#define GRF_GPIO4B_IE_GPIO4B1_IE_SHIFT (2U) +#define GRF_GPIO4B_IE_GPIO4B1_IE_MASK (0x3U << GRF_GPIO4B_IE_GPIO4B1_IE_SHIFT) /* 0x0000000C */ +#define GRF_GPIO4B_IE_GPIO4B2_IE_SHIFT (4U) +#define GRF_GPIO4B_IE_GPIO4B2_IE_MASK (0x3U << GRF_GPIO4B_IE_GPIO4B2_IE_SHIFT) /* 0x00000030 */ +#define GRF_GPIO4B_IE_GPIO4B3_IE_SHIFT (6U) +#define GRF_GPIO4B_IE_GPIO4B3_IE_MASK (0x3U << GRF_GPIO4B_IE_GPIO4B3_IE_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO4B_IE_GPIO4B4_IE_SHIFT (8U) +#define GRF_GPIO4B_IE_GPIO4B4_IE_MASK (0x3U << GRF_GPIO4B_IE_GPIO4B4_IE_SHIFT) /* 0x00000300 */ +#define GRF_GPIO4B_IE_GPIO4B5_IE_SHIFT (10U) +#define GRF_GPIO4B_IE_GPIO4B5_IE_MASK (0x3U << GRF_GPIO4B_IE_GPIO4B5_IE_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO4B_IE_GPIO4B6_IE_SHIFT (12U) +#define GRF_GPIO4B_IE_GPIO4B6_IE_MASK (0x3U << GRF_GPIO4B_IE_GPIO4B6_IE_SHIFT) /* 0x00003000 */ +#define GRF_GPIO4B_IE_GPIO4B7_IE_SHIFT (14U) +#define GRF_GPIO4B_IE_GPIO4B7_IE_MASK (0x3U << GRF_GPIO4B_IE_GPIO4B7_IE_SHIFT) /* 0x0000C000 */ +/* GPIO4C_IE */ +#define GRF_GPIO4C_IE_OFFSET (0x400F8U) +#define GRF_GPIO4C_IE_GPIO4C0_IE_SHIFT (0U) +#define GRF_GPIO4C_IE_GPIO4C0_IE_MASK (0x3U << GRF_GPIO4C_IE_GPIO4C0_IE_SHIFT) /* 0x00000003 */ +#define GRF_GPIO4C_IE_GPIO4C1_IE_SHIFT (2U) +#define GRF_GPIO4C_IE_GPIO4C1_IE_MASK (0x3U << GRF_GPIO4C_IE_GPIO4C1_IE_SHIFT) /* 0x0000000C */ +#define GRF_GPIO4C_IE_GPIO4C2_IE_SHIFT (4U) +#define GRF_GPIO4C_IE_GPIO4C2_IE_MASK (0x3U << GRF_GPIO4C_IE_GPIO4C2_IE_SHIFT) /* 0x00000030 */ +#define GRF_GPIO4C_IE_GPIO4C3_IE_SHIFT (6U) +#define GRF_GPIO4C_IE_GPIO4C3_IE_MASK (0x3U << GRF_GPIO4C_IE_GPIO4C3_IE_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO4C_IE_GPIO4C4_IE_SHIFT (8U) +#define GRF_GPIO4C_IE_GPIO4C4_IE_MASK (0x3U << GRF_GPIO4C_IE_GPIO4C4_IE_SHIFT) /* 0x00000300 */ +#define GRF_GPIO4C_IE_GPIO4C5_IE_SHIFT (10U) +#define GRF_GPIO4C_IE_GPIO4C5_IE_MASK (0x3U << GRF_GPIO4C_IE_GPIO4C5_IE_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO4C_IE_GPIO4C6_IE_SHIFT (12U) +#define GRF_GPIO4C_IE_GPIO4C6_IE_MASK (0x3U << GRF_GPIO4C_IE_GPIO4C6_IE_SHIFT) /* 0x00003000 */ +#define GRF_GPIO4C_IE_GPIO4C7_IE_SHIFT (14U) +#define GRF_GPIO4C_IE_GPIO4C7_IE_MASK (0x3U << GRF_GPIO4C_IE_GPIO4C7_IE_SHIFT) /* 0x0000C000 */ +/* GPIO4D_IE */ +#define GRF_GPIO4D_IE_OFFSET (0x400FCU) +#define GRF_GPIO4D_IE_GPIO4D0_IE_SHIFT (0U) +#define GRF_GPIO4D_IE_GPIO4D0_IE_MASK (0x3U << GRF_GPIO4D_IE_GPIO4D0_IE_SHIFT) /* 0x00000003 */ +#define GRF_GPIO4D_IE_GPIO4D1_IE_SHIFT (2U) +#define GRF_GPIO4D_IE_GPIO4D1_IE_MASK (0x3U << GRF_GPIO4D_IE_GPIO4D1_IE_SHIFT) /* 0x0000000C */ +#define GRF_GPIO4D_IE_GPIO4D2_IE_SHIFT (4U) +#define GRF_GPIO4D_IE_GPIO4D2_IE_MASK (0x3U << GRF_GPIO4D_IE_GPIO4D2_IE_SHIFT) /* 0x00000030 */ +#define GRF_GPIO4D_IE_GPIO4D3_IE_SHIFT (6U) +#define GRF_GPIO4D_IE_GPIO4D3_IE_MASK (0x3U << GRF_GPIO4D_IE_GPIO4D3_IE_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO4D_IE_GPIO4D4_IE_SHIFT (8U) +#define GRF_GPIO4D_IE_GPIO4D4_IE_MASK (0x3U << GRF_GPIO4D_IE_GPIO4D4_IE_SHIFT) /* 0x00000300 */ +#define GRF_GPIO4D_IE_GPIO4D5_IE_SHIFT (10U) +#define GRF_GPIO4D_IE_GPIO4D5_IE_MASK (0x3U << GRF_GPIO4D_IE_GPIO4D5_IE_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO4D_IE_GPIO4D6_IE_SHIFT (12U) +#define GRF_GPIO4D_IE_GPIO4D6_IE_MASK (0x3U << GRF_GPIO4D_IE_GPIO4D6_IE_SHIFT) /* 0x00003000 */ +#define GRF_GPIO4D_IE_GPIO4D7_IE_SHIFT (14U) +#define GRF_GPIO4D_IE_GPIO4D7_IE_MASK (0x3U << GRF_GPIO4D_IE_GPIO4D7_IE_SHIFT) /* 0x0000C000 */ +/* GPIO1A_OPD */ +#define GRF_GPIO1A_OPD_OFFSET (0x40100U) +#define GRF_GPIO1A_OPD_GPIO1A0_OPD_SHIFT (0U) +#define GRF_GPIO1A_OPD_GPIO1A0_OPD_MASK (0x1U << GRF_GPIO1A_OPD_GPIO1A0_OPD_SHIFT) /* 0x00000001 */ +#define GRF_GPIO1A_OPD_GPIO1A1_OPD_SHIFT (1U) +#define GRF_GPIO1A_OPD_GPIO1A1_OPD_MASK (0x1U << GRF_GPIO1A_OPD_GPIO1A1_OPD_SHIFT) /* 0x00000002 */ +#define GRF_GPIO1A_OPD_GPIO1A2_OPD_SHIFT (2U) +#define GRF_GPIO1A_OPD_GPIO1A2_OPD_MASK (0x1U << GRF_GPIO1A_OPD_GPIO1A2_OPD_SHIFT) /* 0x00000004 */ +#define GRF_GPIO1A_OPD_GPIO1A3_OPD_SHIFT (3U) +#define GRF_GPIO1A_OPD_GPIO1A3_OPD_MASK (0x1U << GRF_GPIO1A_OPD_GPIO1A3_OPD_SHIFT) /* 0x00000008 */ +#define GRF_GPIO1A_OPD_GPIO1A4_OPD_SHIFT (4U) +#define GRF_GPIO1A_OPD_GPIO1A4_OPD_MASK (0x1U << GRF_GPIO1A_OPD_GPIO1A4_OPD_SHIFT) /* 0x00000010 */ +#define GRF_GPIO1A_OPD_GPIO1A5_OPD_SHIFT (5U) +#define GRF_GPIO1A_OPD_GPIO1A5_OPD_MASK (0x1U << GRF_GPIO1A_OPD_GPIO1A5_OPD_SHIFT) /* 0x00000020 */ +#define GRF_GPIO1A_OPD_GPIO1A6_OPD_SHIFT (6U) +#define GRF_GPIO1A_OPD_GPIO1A6_OPD_MASK (0x1U << GRF_GPIO1A_OPD_GPIO1A6_OPD_SHIFT) /* 0x00000040 */ +#define GRF_GPIO1A_OPD_GPIO1A7_OPD_SHIFT (7U) +#define GRF_GPIO1A_OPD_GPIO1A7_OPD_MASK (0x1U << GRF_GPIO1A_OPD_GPIO1A7_OPD_SHIFT) /* 0x00000080 */ +/* GPIO1B_OPD */ +#define GRF_GPIO1B_OPD_OFFSET (0x40104U) +#define GRF_GPIO1B_OPD_GPIO1B0_OPD_SHIFT (0U) +#define GRF_GPIO1B_OPD_GPIO1B0_OPD_MASK (0x1U << GRF_GPIO1B_OPD_GPIO1B0_OPD_SHIFT) /* 0x00000001 */ +#define GRF_GPIO1B_OPD_GPIO1B1_OPD_SHIFT (1U) +#define GRF_GPIO1B_OPD_GPIO1B1_OPD_MASK (0x1U << GRF_GPIO1B_OPD_GPIO1B1_OPD_SHIFT) /* 0x00000002 */ +#define GRF_GPIO1B_OPD_GPIO1B2_OPD_SHIFT (2U) +#define GRF_GPIO1B_OPD_GPIO1B2_OPD_MASK (0x1U << GRF_GPIO1B_OPD_GPIO1B2_OPD_SHIFT) /* 0x00000004 */ +#define GRF_GPIO1B_OPD_GPIO1B3_OPD_SHIFT (3U) +#define GRF_GPIO1B_OPD_GPIO1B3_OPD_MASK (0x1U << GRF_GPIO1B_OPD_GPIO1B3_OPD_SHIFT) /* 0x00000008 */ +#define GRF_GPIO1B_OPD_GPIO1B4_OPD_SHIFT (4U) +#define GRF_GPIO1B_OPD_GPIO1B4_OPD_MASK (0x1U << GRF_GPIO1B_OPD_GPIO1B4_OPD_SHIFT) /* 0x00000010 */ +#define GRF_GPIO1B_OPD_GPIO1B5_OPD_SHIFT (5U) +#define GRF_GPIO1B_OPD_GPIO1B5_OPD_MASK (0x1U << GRF_GPIO1B_OPD_GPIO1B5_OPD_SHIFT) /* 0x00000020 */ +#define GRF_GPIO1B_OPD_GPIO1B6_OPD_SHIFT (6U) +#define GRF_GPIO1B_OPD_GPIO1B6_OPD_MASK (0x1U << GRF_GPIO1B_OPD_GPIO1B6_OPD_SHIFT) /* 0x00000040 */ +#define GRF_GPIO1B_OPD_GPIO1B7_OPD_SHIFT (7U) +#define GRF_GPIO1B_OPD_GPIO1B7_OPD_MASK (0x1U << GRF_GPIO1B_OPD_GPIO1B7_OPD_SHIFT) /* 0x00000080 */ +/* GPIO1C_OPD */ +#define GRF_GPIO1C_OPD_OFFSET (0x40108U) +#define GRF_GPIO1C_OPD_GPIO1C0_OPD_SHIFT (0U) +#define GRF_GPIO1C_OPD_GPIO1C0_OPD_MASK (0x1U << GRF_GPIO1C_OPD_GPIO1C0_OPD_SHIFT) /* 0x00000001 */ +#define GRF_GPIO1C_OPD_GPIO1C1_OPD_SHIFT (1U) +#define GRF_GPIO1C_OPD_GPIO1C1_OPD_MASK (0x1U << GRF_GPIO1C_OPD_GPIO1C1_OPD_SHIFT) /* 0x00000002 */ +#define GRF_GPIO1C_OPD_GPIO1C2_OPD_SHIFT (2U) +#define GRF_GPIO1C_OPD_GPIO1C2_OPD_MASK (0x1U << GRF_GPIO1C_OPD_GPIO1C2_OPD_SHIFT) /* 0x00000004 */ +#define GRF_GPIO1C_OPD_GPIO1C3_OPD_SHIFT (3U) +#define GRF_GPIO1C_OPD_GPIO1C3_OPD_MASK (0x1U << GRF_GPIO1C_OPD_GPIO1C3_OPD_SHIFT) /* 0x00000008 */ +#define GRF_GPIO1C_OPD_GPIO1C4_OPD_SHIFT (4U) +#define GRF_GPIO1C_OPD_GPIO1C4_OPD_MASK (0x1U << GRF_GPIO1C_OPD_GPIO1C4_OPD_SHIFT) /* 0x00000010 */ +#define GRF_GPIO1C_OPD_GPIO1C5_OPD_SHIFT (5U) +#define GRF_GPIO1C_OPD_GPIO1C5_OPD_MASK (0x1U << GRF_GPIO1C_OPD_GPIO1C5_OPD_SHIFT) /* 0x00000020 */ +#define GRF_GPIO1C_OPD_GPIO1C6_OPD_SHIFT (6U) +#define GRF_GPIO1C_OPD_GPIO1C6_OPD_MASK (0x1U << GRF_GPIO1C_OPD_GPIO1C6_OPD_SHIFT) /* 0x00000040 */ +#define GRF_GPIO1C_OPD_GPIO1C7_OPD_SHIFT (7U) +#define GRF_GPIO1C_OPD_GPIO1C7_OPD_MASK (0x1U << GRF_GPIO1C_OPD_GPIO1C7_OPD_SHIFT) /* 0x00000080 */ +/* GPIO1D_OPD */ +#define GRF_GPIO1D_OPD_OFFSET (0x4010CU) +#define GRF_GPIO1D_OPD_GPIO1D0_OPD_SHIFT (0U) +#define GRF_GPIO1D_OPD_GPIO1D0_OPD_MASK (0x1U << GRF_GPIO1D_OPD_GPIO1D0_OPD_SHIFT) /* 0x00000001 */ +#define GRF_GPIO1D_OPD_GPIO1D1_OPD_SHIFT (1U) +#define GRF_GPIO1D_OPD_GPIO1D1_OPD_MASK (0x1U << GRF_GPIO1D_OPD_GPIO1D1_OPD_SHIFT) /* 0x00000002 */ +#define GRF_GPIO1D_OPD_GPIO1D2_OPD_SHIFT (2U) +#define GRF_GPIO1D_OPD_GPIO1D2_OPD_MASK (0x1U << GRF_GPIO1D_OPD_GPIO1D2_OPD_SHIFT) /* 0x00000004 */ +#define GRF_GPIO1D_OPD_GPIO1D3_OPD_SHIFT (3U) +#define GRF_GPIO1D_OPD_GPIO1D3_OPD_MASK (0x1U << GRF_GPIO1D_OPD_GPIO1D3_OPD_SHIFT) /* 0x00000008 */ +#define GRF_GPIO1D_OPD_GPIO1D4_OPD_SHIFT (4U) +#define GRF_GPIO1D_OPD_GPIO1D4_OPD_MASK (0x1U << GRF_GPIO1D_OPD_GPIO1D4_OPD_SHIFT) /* 0x00000010 */ +#define GRF_GPIO1D_OPD_GPIO1D5_OPD_SHIFT (5U) +#define GRF_GPIO1D_OPD_GPIO1D5_OPD_MASK (0x1U << GRF_GPIO1D_OPD_GPIO1D5_OPD_SHIFT) /* 0x00000020 */ +#define GRF_GPIO1D_OPD_GPIO1D6_OPD_SHIFT (6U) +#define GRF_GPIO1D_OPD_GPIO1D6_OPD_MASK (0x1U << GRF_GPIO1D_OPD_GPIO1D6_OPD_SHIFT) /* 0x00000040 */ +#define GRF_GPIO1D_OPD_GPIO1D7_OPD_SHIFT (7U) +#define GRF_GPIO1D_OPD_GPIO1D7_OPD_MASK (0x1U << GRF_GPIO1D_OPD_GPIO1D7_OPD_SHIFT) /* 0x00000080 */ +/* GPIO2A_OPD */ +#define GRF_GPIO2A_OPD_OFFSET (0x40110U) +#define GRF_GPIO2A_OPD_GPIO2A0_OPD_SHIFT (0U) +#define GRF_GPIO2A_OPD_GPIO2A0_OPD_MASK (0x1U << GRF_GPIO2A_OPD_GPIO2A0_OPD_SHIFT) /* 0x00000001 */ +#define GRF_GPIO2A_OPD_GPIO2A1_OPD_SHIFT (1U) +#define GRF_GPIO2A_OPD_GPIO2A1_OPD_MASK (0x1U << GRF_GPIO2A_OPD_GPIO2A1_OPD_SHIFT) /* 0x00000002 */ +#define GRF_GPIO2A_OPD_GPIO2A2_OPD_SHIFT (2U) +#define GRF_GPIO2A_OPD_GPIO2A2_OPD_MASK (0x1U << GRF_GPIO2A_OPD_GPIO2A2_OPD_SHIFT) /* 0x00000004 */ +#define GRF_GPIO2A_OPD_GPIO2A3_OPD_SHIFT (3U) +#define GRF_GPIO2A_OPD_GPIO2A3_OPD_MASK (0x1U << GRF_GPIO2A_OPD_GPIO2A3_OPD_SHIFT) /* 0x00000008 */ +#define GRF_GPIO2A_OPD_GPIO2A4_OPD_SHIFT (4U) +#define GRF_GPIO2A_OPD_GPIO2A4_OPD_MASK (0x1U << GRF_GPIO2A_OPD_GPIO2A4_OPD_SHIFT) /* 0x00000010 */ +#define GRF_GPIO2A_OPD_GPIO2A5_OPD_SHIFT (5U) +#define GRF_GPIO2A_OPD_GPIO2A5_OPD_MASK (0x1U << GRF_GPIO2A_OPD_GPIO2A5_OPD_SHIFT) /* 0x00000020 */ +#define GRF_GPIO2A_OPD_GPIO2A6_OPD_SHIFT (6U) +#define GRF_GPIO2A_OPD_GPIO2A6_OPD_MASK (0x1U << GRF_GPIO2A_OPD_GPIO2A6_OPD_SHIFT) /* 0x00000040 */ +#define GRF_GPIO2A_OPD_GPIO2A7_OPD_SHIFT (7U) +#define GRF_GPIO2A_OPD_GPIO2A7_OPD_MASK (0x1U << GRF_GPIO2A_OPD_GPIO2A7_OPD_SHIFT) /* 0x00000080 */ +/* GPIO2B_OPD */ +#define GRF_GPIO2B_OPD_OFFSET (0x40114U) +#define GRF_GPIO2B_OPD_GPIO2B0_OPD_SHIFT (0U) +#define GRF_GPIO2B_OPD_GPIO2B0_OPD_MASK (0x1U << GRF_GPIO2B_OPD_GPIO2B0_OPD_SHIFT) /* 0x00000001 */ +#define GRF_GPIO2B_OPD_GPIO2B1_OPD_SHIFT (1U) +#define GRF_GPIO2B_OPD_GPIO2B1_OPD_MASK (0x1U << GRF_GPIO2B_OPD_GPIO2B1_OPD_SHIFT) /* 0x00000002 */ +#define GRF_GPIO2B_OPD_GPIO2B2_OPD_SHIFT (2U) +#define GRF_GPIO2B_OPD_GPIO2B2_OPD_MASK (0x1U << GRF_GPIO2B_OPD_GPIO2B2_OPD_SHIFT) /* 0x00000004 */ +#define GRF_GPIO2B_OPD_GPIO2B3_OPD_SHIFT (3U) +#define GRF_GPIO2B_OPD_GPIO2B3_OPD_MASK (0x1U << GRF_GPIO2B_OPD_GPIO2B3_OPD_SHIFT) /* 0x00000008 */ +#define GRF_GPIO2B_OPD_GPIO2B4_OPD_SHIFT (4U) +#define GRF_GPIO2B_OPD_GPIO2B4_OPD_MASK (0x1U << GRF_GPIO2B_OPD_GPIO2B4_OPD_SHIFT) /* 0x00000010 */ +#define GRF_GPIO2B_OPD_GPIO2B5_OPD_SHIFT (5U) +#define GRF_GPIO2B_OPD_GPIO2B5_OPD_MASK (0x1U << GRF_GPIO2B_OPD_GPIO2B5_OPD_SHIFT) /* 0x00000020 */ +#define GRF_GPIO2B_OPD_GPIO2B6_OPD_SHIFT (6U) +#define GRF_GPIO2B_OPD_GPIO2B6_OPD_MASK (0x1U << GRF_GPIO2B_OPD_GPIO2B6_OPD_SHIFT) /* 0x00000040 */ +#define GRF_GPIO2B_OPD_GPIO2B7_OPD_SHIFT (7U) +#define GRF_GPIO2B_OPD_GPIO2B7_OPD_MASK (0x1U << GRF_GPIO2B_OPD_GPIO2B7_OPD_SHIFT) /* 0x00000080 */ +/* GPIO2C_OPD */ +#define GRF_GPIO2C_OPD_OFFSET (0x40118U) +#define GRF_GPIO2C_OPD_GPIO2C0_OPD_SHIFT (0U) +#define GRF_GPIO2C_OPD_GPIO2C0_OPD_MASK (0x1U << GRF_GPIO2C_OPD_GPIO2C0_OPD_SHIFT) /* 0x00000001 */ +#define GRF_GPIO2C_OPD_GPIO2C1_OPD_SHIFT (1U) +#define GRF_GPIO2C_OPD_GPIO2C1_OPD_MASK (0x1U << GRF_GPIO2C_OPD_GPIO2C1_OPD_SHIFT) /* 0x00000002 */ +#define GRF_GPIO2C_OPD_GPIO2C2_OPD_SHIFT (2U) +#define GRF_GPIO2C_OPD_GPIO2C2_OPD_MASK (0x1U << GRF_GPIO2C_OPD_GPIO2C2_OPD_SHIFT) /* 0x00000004 */ +#define GRF_GPIO2C_OPD_GPIO2C3_OPD_SHIFT (3U) +#define GRF_GPIO2C_OPD_GPIO2C3_OPD_MASK (0x1U << GRF_GPIO2C_OPD_GPIO2C3_OPD_SHIFT) /* 0x00000008 */ +#define GRF_GPIO2C_OPD_GPIO2C4_OPD_SHIFT (4U) +#define GRF_GPIO2C_OPD_GPIO2C4_OPD_MASK (0x1U << GRF_GPIO2C_OPD_GPIO2C4_OPD_SHIFT) /* 0x00000010 */ +#define GRF_GPIO2C_OPD_GPIO2C5_OPD_SHIFT (5U) +#define GRF_GPIO2C_OPD_GPIO2C5_OPD_MASK (0x1U << GRF_GPIO2C_OPD_GPIO2C5_OPD_SHIFT) /* 0x00000020 */ +#define GRF_GPIO2C_OPD_GPIO2C6_OPD_SHIFT (6U) +#define GRF_GPIO2C_OPD_GPIO2C6_OPD_MASK (0x1U << GRF_GPIO2C_OPD_GPIO2C6_OPD_SHIFT) /* 0x00000040 */ +#define GRF_GPIO2C_OPD_GPIO2C7_OPD_SHIFT (7U) +#define GRF_GPIO2C_OPD_GPIO2C7_OPD_MASK (0x1U << GRF_GPIO2C_OPD_GPIO2C7_OPD_SHIFT) /* 0x00000080 */ +/* GPIO2D_OPD */ +#define GRF_GPIO2D_OPD_OFFSET (0x4011CU) +#define GRF_GPIO2D_OPD_GPIO2D0_OPD_SHIFT (0U) +#define GRF_GPIO2D_OPD_GPIO2D0_OPD_MASK (0x1U << GRF_GPIO2D_OPD_GPIO2D0_OPD_SHIFT) /* 0x00000001 */ +#define GRF_GPIO2D_OPD_GPIO2D1_OPD_SHIFT (1U) +#define GRF_GPIO2D_OPD_GPIO2D1_OPD_MASK (0x1U << GRF_GPIO2D_OPD_GPIO2D1_OPD_SHIFT) /* 0x00000002 */ +#define GRF_GPIO2D_OPD_GPIO2D2_OPD_SHIFT (2U) +#define GRF_GPIO2D_OPD_GPIO2D2_OPD_MASK (0x1U << GRF_GPIO2D_OPD_GPIO2D2_OPD_SHIFT) /* 0x00000004 */ +#define GRF_GPIO2D_OPD_GPIO2D3_OPD_SHIFT (3U) +#define GRF_GPIO2D_OPD_GPIO2D3_OPD_MASK (0x1U << GRF_GPIO2D_OPD_GPIO2D3_OPD_SHIFT) /* 0x00000008 */ +#define GRF_GPIO2D_OPD_GPIO2D4_OPD_SHIFT (4U) +#define GRF_GPIO2D_OPD_GPIO2D4_OPD_MASK (0x1U << GRF_GPIO2D_OPD_GPIO2D4_OPD_SHIFT) /* 0x00000010 */ +#define GRF_GPIO2D_OPD_GPIO2D5_OPD_SHIFT (5U) +#define GRF_GPIO2D_OPD_GPIO2D5_OPD_MASK (0x1U << GRF_GPIO2D_OPD_GPIO2D5_OPD_SHIFT) /* 0x00000020 */ +#define GRF_GPIO2D_OPD_GPIO2D6_OPD_SHIFT (6U) +#define GRF_GPIO2D_OPD_GPIO2D6_OPD_MASK (0x1U << GRF_GPIO2D_OPD_GPIO2D6_OPD_SHIFT) /* 0x00000040 */ +#define GRF_GPIO2D_OPD_GPIO2D7_OPD_SHIFT (7U) +#define GRF_GPIO2D_OPD_GPIO2D7_OPD_MASK (0x1U << GRF_GPIO2D_OPD_GPIO2D7_OPD_SHIFT) /* 0x00000080 */ +/* GPIO3A_OPD */ +#define GRF_GPIO3A_OPD_OFFSET (0x40120U) +#define GRF_GPIO3A_OPD_GPIO3A0_OPD_SHIFT (0U) +#define GRF_GPIO3A_OPD_GPIO3A0_OPD_MASK (0x1U << GRF_GPIO3A_OPD_GPIO3A0_OPD_SHIFT) /* 0x00000001 */ +#define GRF_GPIO3A_OPD_GPIO3A1_OPD_SHIFT (1U) +#define GRF_GPIO3A_OPD_GPIO3A1_OPD_MASK (0x1U << GRF_GPIO3A_OPD_GPIO3A1_OPD_SHIFT) /* 0x00000002 */ +#define GRF_GPIO3A_OPD_GPIO3A2_OPD_SHIFT (2U) +#define GRF_GPIO3A_OPD_GPIO3A2_OPD_MASK (0x1U << GRF_GPIO3A_OPD_GPIO3A2_OPD_SHIFT) /* 0x00000004 */ +#define GRF_GPIO3A_OPD_GPIO3A3_OPD_SHIFT (3U) +#define GRF_GPIO3A_OPD_GPIO3A3_OPD_MASK (0x1U << GRF_GPIO3A_OPD_GPIO3A3_OPD_SHIFT) /* 0x00000008 */ +#define GRF_GPIO3A_OPD_GPIO3A4_OPD_SHIFT (4U) +#define GRF_GPIO3A_OPD_GPIO3A4_OPD_MASK (0x1U << GRF_GPIO3A_OPD_GPIO3A4_OPD_SHIFT) /* 0x00000010 */ +#define GRF_GPIO3A_OPD_GPIO3A5_OPD_SHIFT (5U) +#define GRF_GPIO3A_OPD_GPIO3A5_OPD_MASK (0x1U << GRF_GPIO3A_OPD_GPIO3A5_OPD_SHIFT) /* 0x00000020 */ +#define GRF_GPIO3A_OPD_GPIO3A6_OPD_SHIFT (6U) +#define GRF_GPIO3A_OPD_GPIO3A6_OPD_MASK (0x1U << GRF_GPIO3A_OPD_GPIO3A6_OPD_SHIFT) /* 0x00000040 */ +#define GRF_GPIO3A_OPD_GPIO3A7_OPD_SHIFT (7U) +#define GRF_GPIO3A_OPD_GPIO3A7_OPD_MASK (0x1U << GRF_GPIO3A_OPD_GPIO3A7_OPD_SHIFT) /* 0x00000080 */ +/* GPIO3B_OPD */ +#define GRF_GPIO3B_OPD_OFFSET (0x40124U) +#define GRF_GPIO3B_OPD_GPIO3B0_OPD_SHIFT (0U) +#define GRF_GPIO3B_OPD_GPIO3B0_OPD_MASK (0x1U << GRF_GPIO3B_OPD_GPIO3B0_OPD_SHIFT) /* 0x00000001 */ +#define GRF_GPIO3B_OPD_GPIO3B1_OPD_SHIFT (1U) +#define GRF_GPIO3B_OPD_GPIO3B1_OPD_MASK (0x1U << GRF_GPIO3B_OPD_GPIO3B1_OPD_SHIFT) /* 0x00000002 */ +#define GRF_GPIO3B_OPD_GPIO3B2_OPD_SHIFT (2U) +#define GRF_GPIO3B_OPD_GPIO3B2_OPD_MASK (0x1U << GRF_GPIO3B_OPD_GPIO3B2_OPD_SHIFT) /* 0x00000004 */ +#define GRF_GPIO3B_OPD_GPIO3B3_OPD_SHIFT (3U) +#define GRF_GPIO3B_OPD_GPIO3B3_OPD_MASK (0x1U << GRF_GPIO3B_OPD_GPIO3B3_OPD_SHIFT) /* 0x00000008 */ +#define GRF_GPIO3B_OPD_GPIO3B4_OPD_SHIFT (4U) +#define GRF_GPIO3B_OPD_GPIO3B4_OPD_MASK (0x1U << GRF_GPIO3B_OPD_GPIO3B4_OPD_SHIFT) /* 0x00000010 */ +#define GRF_GPIO3B_OPD_GPIO3B5_OPD_SHIFT (5U) +#define GRF_GPIO3B_OPD_GPIO3B5_OPD_MASK (0x1U << GRF_GPIO3B_OPD_GPIO3B5_OPD_SHIFT) /* 0x00000020 */ +#define GRF_GPIO3B_OPD_GPIO3B6_OPD_SHIFT (6U) +#define GRF_GPIO3B_OPD_GPIO3B6_OPD_MASK (0x1U << GRF_GPIO3B_OPD_GPIO3B6_OPD_SHIFT) /* 0x00000040 */ +#define GRF_GPIO3B_OPD_GPIO3B7_OPD_SHIFT (7U) +#define GRF_GPIO3B_OPD_GPIO3B7_OPD_MASK (0x1U << GRF_GPIO3B_OPD_GPIO3B7_OPD_SHIFT) /* 0x00000080 */ +/* GPIO3C_OPD */ +#define GRF_GPIO3C_OPD_OFFSET (0x40128U) +#define GRF_GPIO3C_OPD_GPIO3C0_OPD_SHIFT (0U) +#define GRF_GPIO3C_OPD_GPIO3C0_OPD_MASK (0x1U << GRF_GPIO3C_OPD_GPIO3C0_OPD_SHIFT) /* 0x00000001 */ +#define GRF_GPIO3C_OPD_GPIO3C1_OPD_SHIFT (1U) +#define GRF_GPIO3C_OPD_GPIO3C1_OPD_MASK (0x1U << GRF_GPIO3C_OPD_GPIO3C1_OPD_SHIFT) /* 0x00000002 */ +#define GRF_GPIO3C_OPD_GPIO3C2_OPD_SHIFT (2U) +#define GRF_GPIO3C_OPD_GPIO3C2_OPD_MASK (0x1U << GRF_GPIO3C_OPD_GPIO3C2_OPD_SHIFT) /* 0x00000004 */ +#define GRF_GPIO3C_OPD_GPIO3C3_OPD_SHIFT (3U) +#define GRF_GPIO3C_OPD_GPIO3C3_OPD_MASK (0x1U << GRF_GPIO3C_OPD_GPIO3C3_OPD_SHIFT) /* 0x00000008 */ +#define GRF_GPIO3C_OPD_GPIO3C4_OPD_SHIFT (4U) +#define GRF_GPIO3C_OPD_GPIO3C4_OPD_MASK (0x1U << GRF_GPIO3C_OPD_GPIO3C4_OPD_SHIFT) /* 0x00000010 */ +#define GRF_GPIO3C_OPD_GPIO3C5_OPD_SHIFT (5U) +#define GRF_GPIO3C_OPD_GPIO3C5_OPD_MASK (0x1U << GRF_GPIO3C_OPD_GPIO3C5_OPD_SHIFT) /* 0x00000020 */ +#define GRF_GPIO3C_OPD_GPIO3C6_OPD_SHIFT (6U) +#define GRF_GPIO3C_OPD_GPIO3C6_OPD_MASK (0x1U << GRF_GPIO3C_OPD_GPIO3C6_OPD_SHIFT) /* 0x00000040 */ +#define GRF_GPIO3C_OPD_GPIO3C7_OPD_SHIFT (7U) +#define GRF_GPIO3C_OPD_GPIO3C7_OPD_MASK (0x1U << GRF_GPIO3C_OPD_GPIO3C7_OPD_SHIFT) /* 0x00000080 */ +/* GPIO3D_OPD */ +#define GRF_GPIO3D_OPD_OFFSET (0x4012CU) +#define GRF_GPIO3D_OPD_GPIO3D0_OPD_SHIFT (0U) +#define GRF_GPIO3D_OPD_GPIO3D0_OPD_MASK (0x1U << GRF_GPIO3D_OPD_GPIO3D0_OPD_SHIFT) /* 0x00000001 */ +#define GRF_GPIO3D_OPD_GPIO3D1_OPD_SHIFT (1U) +#define GRF_GPIO3D_OPD_GPIO3D1_OPD_MASK (0x1U << GRF_GPIO3D_OPD_GPIO3D1_OPD_SHIFT) /* 0x00000002 */ +#define GRF_GPIO3D_OPD_GPIO3D2_OPD_SHIFT (2U) +#define GRF_GPIO3D_OPD_GPIO3D2_OPD_MASK (0x1U << GRF_GPIO3D_OPD_GPIO3D2_OPD_SHIFT) /* 0x00000004 */ +#define GRF_GPIO3D_OPD_GPIO3D3_OPD_SHIFT (3U) +#define GRF_GPIO3D_OPD_GPIO3D3_OPD_MASK (0x1U << GRF_GPIO3D_OPD_GPIO3D3_OPD_SHIFT) /* 0x00000008 */ +#define GRF_GPIO3D_OPD_GPIO3D4_OPD_SHIFT (4U) +#define GRF_GPIO3D_OPD_GPIO3D4_OPD_MASK (0x1U << GRF_GPIO3D_OPD_GPIO3D4_OPD_SHIFT) /* 0x00000010 */ +#define GRF_GPIO3D_OPD_GPIO3D5_OPD_SHIFT (5U) +#define GRF_GPIO3D_OPD_GPIO3D5_OPD_MASK (0x1U << GRF_GPIO3D_OPD_GPIO3D5_OPD_SHIFT) /* 0x00000020 */ +#define GRF_GPIO3D_OPD_GPIO3D6_OPD_SHIFT (6U) +#define GRF_GPIO3D_OPD_GPIO3D6_OPD_MASK (0x1U << GRF_GPIO3D_OPD_GPIO3D6_OPD_SHIFT) /* 0x00000040 */ +#define GRF_GPIO3D_OPD_GPIO3D7_OPD_SHIFT (7U) +#define GRF_GPIO3D_OPD_GPIO3D7_OPD_MASK (0x1U << GRF_GPIO3D_OPD_GPIO3D7_OPD_SHIFT) /* 0x00000080 */ +/* GPIO4A_OPD */ +#define GRF_GPIO4A_OPD_OFFSET (0x40130U) +#define GRF_GPIO4A_OPD_GPIO4A0_OPD_SHIFT (0U) +#define GRF_GPIO4A_OPD_GPIO4A0_OPD_MASK (0x1U << GRF_GPIO4A_OPD_GPIO4A0_OPD_SHIFT) /* 0x00000001 */ +#define GRF_GPIO4A_OPD_GPIO4A1_OPD_SHIFT (1U) +#define GRF_GPIO4A_OPD_GPIO4A1_OPD_MASK (0x1U << GRF_GPIO4A_OPD_GPIO4A1_OPD_SHIFT) /* 0x00000002 */ +#define GRF_GPIO4A_OPD_GPIO4A2_OPD_SHIFT (2U) +#define GRF_GPIO4A_OPD_GPIO4A2_OPD_MASK (0x1U << GRF_GPIO4A_OPD_GPIO4A2_OPD_SHIFT) /* 0x00000004 */ +#define GRF_GPIO4A_OPD_GPIO4A3_OPD_SHIFT (3U) +#define GRF_GPIO4A_OPD_GPIO4A3_OPD_MASK (0x1U << GRF_GPIO4A_OPD_GPIO4A3_OPD_SHIFT) /* 0x00000008 */ +#define GRF_GPIO4A_OPD_GPIO4A4_OPD_SHIFT (4U) +#define GRF_GPIO4A_OPD_GPIO4A4_OPD_MASK (0x1U << GRF_GPIO4A_OPD_GPIO4A4_OPD_SHIFT) /* 0x00000010 */ +#define GRF_GPIO4A_OPD_GPIO4A5_OPD_SHIFT (5U) +#define GRF_GPIO4A_OPD_GPIO4A5_OPD_MASK (0x1U << GRF_GPIO4A_OPD_GPIO4A5_OPD_SHIFT) /* 0x00000020 */ +#define GRF_GPIO4A_OPD_GPIO4A6_OPD_SHIFT (6U) +#define GRF_GPIO4A_OPD_GPIO4A6_OPD_MASK (0x1U << GRF_GPIO4A_OPD_GPIO4A6_OPD_SHIFT) /* 0x00000040 */ +#define GRF_GPIO4A_OPD_GPIO4A7_OPD_SHIFT (7U) +#define GRF_GPIO4A_OPD_GPIO4A7_OPD_MASK (0x1U << GRF_GPIO4A_OPD_GPIO4A7_OPD_SHIFT) /* 0x00000080 */ +/* GPIO4B_OPD */ +#define GRF_GPIO4B_OPD_OFFSET (0x40134U) +#define GRF_GPIO4B_OPD_GPIO4B0_OPD_SHIFT (0U) +#define GRF_GPIO4B_OPD_GPIO4B0_OPD_MASK (0x1U << GRF_GPIO4B_OPD_GPIO4B0_OPD_SHIFT) /* 0x00000001 */ +#define GRF_GPIO4B_OPD_GPIO4B1_OPD_SHIFT (1U) +#define GRF_GPIO4B_OPD_GPIO4B1_OPD_MASK (0x1U << GRF_GPIO4B_OPD_GPIO4B1_OPD_SHIFT) /* 0x00000002 */ +#define GRF_GPIO4B_OPD_GPIO4B2_OPD_SHIFT (2U) +#define GRF_GPIO4B_OPD_GPIO4B2_OPD_MASK (0x1U << GRF_GPIO4B_OPD_GPIO4B2_OPD_SHIFT) /* 0x00000004 */ +#define GRF_GPIO4B_OPD_GPIO4B3_OPD_SHIFT (3U) +#define GRF_GPIO4B_OPD_GPIO4B3_OPD_MASK (0x1U << GRF_GPIO4B_OPD_GPIO4B3_OPD_SHIFT) /* 0x00000008 */ +#define GRF_GPIO4B_OPD_GPIO4B4_OPD_SHIFT (4U) +#define GRF_GPIO4B_OPD_GPIO4B4_OPD_MASK (0x1U << GRF_GPIO4B_OPD_GPIO4B4_OPD_SHIFT) /* 0x00000010 */ +#define GRF_GPIO4B_OPD_GPIO4B5_OPD_SHIFT (5U) +#define GRF_GPIO4B_OPD_GPIO4B5_OPD_MASK (0x1U << GRF_GPIO4B_OPD_GPIO4B5_OPD_SHIFT) /* 0x00000020 */ +#define GRF_GPIO4B_OPD_GPIO4B6_OPD_SHIFT (6U) +#define GRF_GPIO4B_OPD_GPIO4B6_OPD_MASK (0x1U << GRF_GPIO4B_OPD_GPIO4B6_OPD_SHIFT) /* 0x00000040 */ +#define GRF_GPIO4B_OPD_GPIO4B7_OPD_SHIFT (7U) +#define GRF_GPIO4B_OPD_GPIO4B7_OPD_MASK (0x1U << GRF_GPIO4B_OPD_GPIO4B7_OPD_SHIFT) /* 0x00000080 */ +/* GPIO4C_OPD */ +#define GRF_GPIO4C_OPD_OFFSET (0x40138U) +#define GRF_GPIO4C_OPD_GPIO4C0_OPD_SHIFT (0U) +#define GRF_GPIO4C_OPD_GPIO4C0_OPD_MASK (0x1U << GRF_GPIO4C_OPD_GPIO4C0_OPD_SHIFT) /* 0x00000001 */ +#define GRF_GPIO4C_OPD_GPIO4C1_OPD_SHIFT (1U) +#define GRF_GPIO4C_OPD_GPIO4C1_OPD_MASK (0x1U << GRF_GPIO4C_OPD_GPIO4C1_OPD_SHIFT) /* 0x00000002 */ +#define GRF_GPIO4C_OPD_GPIO4C2_OPD_SHIFT (2U) +#define GRF_GPIO4C_OPD_GPIO4C2_OPD_MASK (0x1U << GRF_GPIO4C_OPD_GPIO4C2_OPD_SHIFT) /* 0x00000004 */ +#define GRF_GPIO4C_OPD_GPIO4C3_OPD_SHIFT (3U) +#define GRF_GPIO4C_OPD_GPIO4C3_OPD_MASK (0x1U << GRF_GPIO4C_OPD_GPIO4C3_OPD_SHIFT) /* 0x00000008 */ +#define GRF_GPIO4C_OPD_GPIO4C4_OPD_SHIFT (4U) +#define GRF_GPIO4C_OPD_GPIO4C4_OPD_MASK (0x1U << GRF_GPIO4C_OPD_GPIO4C4_OPD_SHIFT) /* 0x00000010 */ +#define GRF_GPIO4C_OPD_GPIO4C5_OPD_SHIFT (5U) +#define GRF_GPIO4C_OPD_GPIO4C5_OPD_MASK (0x1U << GRF_GPIO4C_OPD_GPIO4C5_OPD_SHIFT) /* 0x00000020 */ +#define GRF_GPIO4C_OPD_GPIO4C6_OPD_SHIFT (6U) +#define GRF_GPIO4C_OPD_GPIO4C6_OPD_MASK (0x1U << GRF_GPIO4C_OPD_GPIO4C6_OPD_SHIFT) /* 0x00000040 */ +#define GRF_GPIO4C_OPD_GPIO4C7_OPD_SHIFT (7U) +#define GRF_GPIO4C_OPD_GPIO4C7_OPD_MASK (0x1U << GRF_GPIO4C_OPD_GPIO4C7_OPD_SHIFT) /* 0x00000080 */ +/* GPIO4D_OPD */ +#define GRF_GPIO4D_OPD_OFFSET (0x4013CU) +#define GRF_GPIO4D_OPD_GPIO4D0_OPD_SHIFT (0U) +#define GRF_GPIO4D_OPD_GPIO4D0_OPD_MASK (0x1U << GRF_GPIO4D_OPD_GPIO4D0_OPD_SHIFT) /* 0x00000001 */ +#define GRF_GPIO4D_OPD_GPIO4D1_OPD_SHIFT (1U) +#define GRF_GPIO4D_OPD_GPIO4D1_OPD_MASK (0x1U << GRF_GPIO4D_OPD_GPIO4D1_OPD_SHIFT) /* 0x00000002 */ +#define GRF_GPIO4D_OPD_GPIO4D2_OPD_SHIFT (2U) +#define GRF_GPIO4D_OPD_GPIO4D2_OPD_MASK (0x1U << GRF_GPIO4D_OPD_GPIO4D2_OPD_SHIFT) /* 0x00000004 */ +#define GRF_GPIO4D_OPD_GPIO4D3_OPD_SHIFT (3U) +#define GRF_GPIO4D_OPD_GPIO4D3_OPD_MASK (0x1U << GRF_GPIO4D_OPD_GPIO4D3_OPD_SHIFT) /* 0x00000008 */ +#define GRF_GPIO4D_OPD_GPIO4D4_OPD_SHIFT (4U) +#define GRF_GPIO4D_OPD_GPIO4D4_OPD_MASK (0x1U << GRF_GPIO4D_OPD_GPIO4D4_OPD_SHIFT) /* 0x00000010 */ +#define GRF_GPIO4D_OPD_GPIO4D5_OPD_SHIFT (5U) +#define GRF_GPIO4D_OPD_GPIO4D5_OPD_MASK (0x1U << GRF_GPIO4D_OPD_GPIO4D5_OPD_SHIFT) /* 0x00000020 */ +#define GRF_GPIO4D_OPD_GPIO4D6_OPD_SHIFT (6U) +#define GRF_GPIO4D_OPD_GPIO4D6_OPD_MASK (0x1U << GRF_GPIO4D_OPD_GPIO4D6_OPD_SHIFT) /* 0x00000040 */ +#define GRF_GPIO4D_OPD_GPIO4D7_OPD_SHIFT (7U) +#define GRF_GPIO4D_OPD_GPIO4D7_OPD_MASK (0x1U << GRF_GPIO4D_OPD_GPIO4D7_OPD_SHIFT) /* 0x00000080 */ +/* GPIO1A_SUS */ +#define GRF_GPIO1A_SUS_OFFSET (0x40140U) +#define GRF_GPIO1A_SUS_GPIO1A0_SUS_SHIFT (0U) +#define GRF_GPIO1A_SUS_GPIO1A0_SUS_MASK (0x1U << GRF_GPIO1A_SUS_GPIO1A0_SUS_SHIFT) /* 0x00000001 */ +#define GRF_GPIO1A_SUS_GPIO1A1_SUS_SHIFT (1U) +#define GRF_GPIO1A_SUS_GPIO1A1_SUS_MASK (0x1U << GRF_GPIO1A_SUS_GPIO1A1_SUS_SHIFT) /* 0x00000002 */ +#define GRF_GPIO1A_SUS_GPIO1A2_SUS_SHIFT (2U) +#define GRF_GPIO1A_SUS_GPIO1A2_SUS_MASK (0x1U << GRF_GPIO1A_SUS_GPIO1A2_SUS_SHIFT) /* 0x00000004 */ +#define GRF_GPIO1A_SUS_GPIO1A3_SUS_SHIFT (3U) +#define GRF_GPIO1A_SUS_GPIO1A3_SUS_MASK (0x1U << GRF_GPIO1A_SUS_GPIO1A3_SUS_SHIFT) /* 0x00000008 */ +#define GRF_GPIO1A_SUS_GPIO1A4_SUS_SHIFT (4U) +#define GRF_GPIO1A_SUS_GPIO1A4_SUS_MASK (0x1U << GRF_GPIO1A_SUS_GPIO1A4_SUS_SHIFT) /* 0x00000010 */ +#define GRF_GPIO1A_SUS_GPIO1A5_SUS_SHIFT (5U) +#define GRF_GPIO1A_SUS_GPIO1A5_SUS_MASK (0x1U << GRF_GPIO1A_SUS_GPIO1A5_SUS_SHIFT) /* 0x00000020 */ +#define GRF_GPIO1A_SUS_GPIO1A6_SUS_SHIFT (6U) +#define GRF_GPIO1A_SUS_GPIO1A6_SUS_MASK (0x1U << GRF_GPIO1A_SUS_GPIO1A6_SUS_SHIFT) /* 0x00000040 */ +#define GRF_GPIO1A_SUS_GPIO1A7_SUS_SHIFT (7U) +#define GRF_GPIO1A_SUS_GPIO1A7_SUS_MASK (0x1U << GRF_GPIO1A_SUS_GPIO1A7_SUS_SHIFT) /* 0x00000080 */ +/* GPIO1B_SUS */ +#define GRF_GPIO1B_SUS_OFFSET (0x40144U) +#define GRF_GPIO1B_SUS_GPIO1B0_SUS_SHIFT (0U) +#define GRF_GPIO1B_SUS_GPIO1B0_SUS_MASK (0x1U << GRF_GPIO1B_SUS_GPIO1B0_SUS_SHIFT) /* 0x00000001 */ +#define GRF_GPIO1B_SUS_GPIO1B1_SUS_SHIFT (1U) +#define GRF_GPIO1B_SUS_GPIO1B1_SUS_MASK (0x1U << GRF_GPIO1B_SUS_GPIO1B1_SUS_SHIFT) /* 0x00000002 */ +#define GRF_GPIO1B_SUS_GPIO1B2_SUS_SHIFT (2U) +#define GRF_GPIO1B_SUS_GPIO1B2_SUS_MASK (0x1U << GRF_GPIO1B_SUS_GPIO1B2_SUS_SHIFT) /* 0x00000004 */ +#define GRF_GPIO1B_SUS_GPIO1B3_SUS_SHIFT (3U) +#define GRF_GPIO1B_SUS_GPIO1B3_SUS_MASK (0x1U << GRF_GPIO1B_SUS_GPIO1B3_SUS_SHIFT) /* 0x00000008 */ +#define GRF_GPIO1B_SUS_GPIO1B4_SUS_SHIFT (4U) +#define GRF_GPIO1B_SUS_GPIO1B4_SUS_MASK (0x1U << GRF_GPIO1B_SUS_GPIO1B4_SUS_SHIFT) /* 0x00000010 */ +#define GRF_GPIO1B_SUS_GPIO1B5_SUS_SHIFT (5U) +#define GRF_GPIO1B_SUS_GPIO1B5_SUS_MASK (0x1U << GRF_GPIO1B_SUS_GPIO1B5_SUS_SHIFT) /* 0x00000020 */ +#define GRF_GPIO1B_SUS_GPIO1B6_SUS_SHIFT (6U) +#define GRF_GPIO1B_SUS_GPIO1B6_SUS_MASK (0x1U << GRF_GPIO1B_SUS_GPIO1B6_SUS_SHIFT) /* 0x00000040 */ +#define GRF_GPIO1B_SUS_GPIO1B7_SUS_SHIFT (7U) +#define GRF_GPIO1B_SUS_GPIO1B7_SUS_MASK (0x1U << GRF_GPIO1B_SUS_GPIO1B7_SUS_SHIFT) /* 0x00000080 */ +/* GPIO1C_SUS */ +#define GRF_GPIO1C_SUS_OFFSET (0x40148U) +#define GRF_GPIO1C_SUS_GPIO1C0_SUS_SHIFT (0U) +#define GRF_GPIO1C_SUS_GPIO1C0_SUS_MASK (0x1U << GRF_GPIO1C_SUS_GPIO1C0_SUS_SHIFT) /* 0x00000001 */ +#define GRF_GPIO1C_SUS_GPIO1C1_SUS_SHIFT (1U) +#define GRF_GPIO1C_SUS_GPIO1C1_SUS_MASK (0x1U << GRF_GPIO1C_SUS_GPIO1C1_SUS_SHIFT) /* 0x00000002 */ +#define GRF_GPIO1C_SUS_GPIO1C2_SUS_SHIFT (2U) +#define GRF_GPIO1C_SUS_GPIO1C2_SUS_MASK (0x1U << GRF_GPIO1C_SUS_GPIO1C2_SUS_SHIFT) /* 0x00000004 */ +#define GRF_GPIO1C_SUS_GPIO1C3_SUS_SHIFT (3U) +#define GRF_GPIO1C_SUS_GPIO1C3_SUS_MASK (0x1U << GRF_GPIO1C_SUS_GPIO1C3_SUS_SHIFT) /* 0x00000008 */ +#define GRF_GPIO1C_SUS_GPIO1C4_SUS_SHIFT (4U) +#define GRF_GPIO1C_SUS_GPIO1C4_SUS_MASK (0x1U << GRF_GPIO1C_SUS_GPIO1C4_SUS_SHIFT) /* 0x00000010 */ +#define GRF_GPIO1C_SUS_GPIO1C5_SUS_SHIFT (5U) +#define GRF_GPIO1C_SUS_GPIO1C5_SUS_MASK (0x1U << GRF_GPIO1C_SUS_GPIO1C5_SUS_SHIFT) /* 0x00000020 */ +#define GRF_GPIO1C_SUS_GPIO1C6_SUS_SHIFT (6U) +#define GRF_GPIO1C_SUS_GPIO1C6_SUS_MASK (0x1U << GRF_GPIO1C_SUS_GPIO1C6_SUS_SHIFT) /* 0x00000040 */ +#define GRF_GPIO1C_SUS_GPIO1C7_SUS_SHIFT (7U) +#define GRF_GPIO1C_SUS_GPIO1C7_SUS_MASK (0x1U << GRF_GPIO1C_SUS_GPIO1C7_SUS_SHIFT) /* 0x00000080 */ +/* GPIO1D_SUS */ +#define GRF_GPIO1D_SUS_OFFSET (0x4014CU) +#define GRF_GPIO1D_SUS_GPIO1D0_SUS_SHIFT (0U) +#define GRF_GPIO1D_SUS_GPIO1D0_SUS_MASK (0x1U << GRF_GPIO1D_SUS_GPIO1D0_SUS_SHIFT) /* 0x00000001 */ +#define GRF_GPIO1D_SUS_GPIO1D1_SUS_SHIFT (1U) +#define GRF_GPIO1D_SUS_GPIO1D1_SUS_MASK (0x1U << GRF_GPIO1D_SUS_GPIO1D1_SUS_SHIFT) /* 0x00000002 */ +#define GRF_GPIO1D_SUS_GPIO1D2_SUS_SHIFT (2U) +#define GRF_GPIO1D_SUS_GPIO1D2_SUS_MASK (0x1U << GRF_GPIO1D_SUS_GPIO1D2_SUS_SHIFT) /* 0x00000004 */ +#define GRF_GPIO1D_SUS_GPIO1D3_SUS_SHIFT (3U) +#define GRF_GPIO1D_SUS_GPIO1D3_SUS_MASK (0x1U << GRF_GPIO1D_SUS_GPIO1D3_SUS_SHIFT) /* 0x00000008 */ +#define GRF_GPIO1D_SUS_GPIO1D4_SUS_SHIFT (4U) +#define GRF_GPIO1D_SUS_GPIO1D4_SUS_MASK (0x1U << GRF_GPIO1D_SUS_GPIO1D4_SUS_SHIFT) /* 0x00000010 */ +#define GRF_GPIO1D_SUS_GPIO1D5_SUS_SHIFT (5U) +#define GRF_GPIO1D_SUS_GPIO1D5_SUS_MASK (0x1U << GRF_GPIO1D_SUS_GPIO1D5_SUS_SHIFT) /* 0x00000020 */ +#define GRF_GPIO1D_SUS_GPIO1D6_SUS_SHIFT (6U) +#define GRF_GPIO1D_SUS_GPIO1D6_SUS_MASK (0x1U << GRF_GPIO1D_SUS_GPIO1D6_SUS_SHIFT) /* 0x00000040 */ +#define GRF_GPIO1D_SUS_GPIO1D7_SUS_SHIFT (7U) +#define GRF_GPIO1D_SUS_GPIO1D7_SUS_MASK (0x1U << GRF_GPIO1D_SUS_GPIO1D7_SUS_SHIFT) /* 0x00000080 */ +/* GPIO2A_SUS */ +#define GRF_GPIO2A_SUS_OFFSET (0x40150U) +#define GRF_GPIO2A_SUS_GPIO2A0_SUS_SHIFT (0U) +#define GRF_GPIO2A_SUS_GPIO2A0_SUS_MASK (0x1U << GRF_GPIO2A_SUS_GPIO2A0_SUS_SHIFT) /* 0x00000001 */ +#define GRF_GPIO2A_SUS_GPIO2A1_SUS_SHIFT (1U) +#define GRF_GPIO2A_SUS_GPIO2A1_SUS_MASK (0x1U << GRF_GPIO2A_SUS_GPIO2A1_SUS_SHIFT) /* 0x00000002 */ +#define GRF_GPIO2A_SUS_GPIO2A2_SUS_SHIFT (2U) +#define GRF_GPIO2A_SUS_GPIO2A2_SUS_MASK (0x1U << GRF_GPIO2A_SUS_GPIO2A2_SUS_SHIFT) /* 0x00000004 */ +#define GRF_GPIO2A_SUS_GPIO2A3_SUS_SHIFT (3U) +#define GRF_GPIO2A_SUS_GPIO2A3_SUS_MASK (0x1U << GRF_GPIO2A_SUS_GPIO2A3_SUS_SHIFT) /* 0x00000008 */ +#define GRF_GPIO2A_SUS_GPIO2A4_SUS_SHIFT (4U) +#define GRF_GPIO2A_SUS_GPIO2A4_SUS_MASK (0x1U << GRF_GPIO2A_SUS_GPIO2A4_SUS_SHIFT) /* 0x00000010 */ +#define GRF_GPIO2A_SUS_GPIO2A5_SUS_SHIFT (5U) +#define GRF_GPIO2A_SUS_GPIO2A5_SUS_MASK (0x1U << GRF_GPIO2A_SUS_GPIO2A5_SUS_SHIFT) /* 0x00000020 */ +#define GRF_GPIO2A_SUS_GPIO2A6_SUS_SHIFT (6U) +#define GRF_GPIO2A_SUS_GPIO2A6_SUS_MASK (0x1U << GRF_GPIO2A_SUS_GPIO2A6_SUS_SHIFT) /* 0x00000040 */ +#define GRF_GPIO2A_SUS_GPIO2A7_SUS_SHIFT (7U) +#define GRF_GPIO2A_SUS_GPIO2A7_SUS_MASK (0x1U << GRF_GPIO2A_SUS_GPIO2A7_SUS_SHIFT) /* 0x00000080 */ +/* GPIO2B_SUS */ +#define GRF_GPIO2B_SUS_OFFSET (0x40154U) +#define GRF_GPIO2B_SUS_GPIO2B0_SUS_SHIFT (0U) +#define GRF_GPIO2B_SUS_GPIO2B0_SUS_MASK (0x1U << GRF_GPIO2B_SUS_GPIO2B0_SUS_SHIFT) /* 0x00000001 */ +#define GRF_GPIO2B_SUS_GPIO2B1_SUS_SHIFT (1U) +#define GRF_GPIO2B_SUS_GPIO2B1_SUS_MASK (0x1U << GRF_GPIO2B_SUS_GPIO2B1_SUS_SHIFT) /* 0x00000002 */ +#define GRF_GPIO2B_SUS_GPIO2B2_SUS_SHIFT (2U) +#define GRF_GPIO2B_SUS_GPIO2B2_SUS_MASK (0x1U << GRF_GPIO2B_SUS_GPIO2B2_SUS_SHIFT) /* 0x00000004 */ +#define GRF_GPIO2B_SUS_GPIO2B3_SUS_SHIFT (3U) +#define GRF_GPIO2B_SUS_GPIO2B3_SUS_MASK (0x1U << GRF_GPIO2B_SUS_GPIO2B3_SUS_SHIFT) /* 0x00000008 */ +#define GRF_GPIO2B_SUS_GPIO2B4_SUS_SHIFT (4U) +#define GRF_GPIO2B_SUS_GPIO2B4_SUS_MASK (0x1U << GRF_GPIO2B_SUS_GPIO2B4_SUS_SHIFT) /* 0x00000010 */ +#define GRF_GPIO2B_SUS_GPIO2B5_SUS_SHIFT (5U) +#define GRF_GPIO2B_SUS_GPIO2B5_SUS_MASK (0x1U << GRF_GPIO2B_SUS_GPIO2B5_SUS_SHIFT) /* 0x00000020 */ +#define GRF_GPIO2B_SUS_GPIO2B6_SUS_SHIFT (6U) +#define GRF_GPIO2B_SUS_GPIO2B6_SUS_MASK (0x1U << GRF_GPIO2B_SUS_GPIO2B6_SUS_SHIFT) /* 0x00000040 */ +#define GRF_GPIO2B_SUS_GPIO2B7_SUS_SHIFT (7U) +#define GRF_GPIO2B_SUS_GPIO2B7_SUS_MASK (0x1U << GRF_GPIO2B_SUS_GPIO2B7_SUS_SHIFT) /* 0x00000080 */ +/* GPIO2C_SUS */ +#define GRF_GPIO2C_SUS_OFFSET (0x40158U) +#define GRF_GPIO2C_SUS_GPIO2C0_SUS_SHIFT (0U) +#define GRF_GPIO2C_SUS_GPIO2C0_SUS_MASK (0x1U << GRF_GPIO2C_SUS_GPIO2C0_SUS_SHIFT) /* 0x00000001 */ +#define GRF_GPIO2C_SUS_GPIO2C1_SUS_SHIFT (1U) +#define GRF_GPIO2C_SUS_GPIO2C1_SUS_MASK (0x1U << GRF_GPIO2C_SUS_GPIO2C1_SUS_SHIFT) /* 0x00000002 */ +#define GRF_GPIO2C_SUS_GPIO2C2_SUS_SHIFT (2U) +#define GRF_GPIO2C_SUS_GPIO2C2_SUS_MASK (0x1U << GRF_GPIO2C_SUS_GPIO2C2_SUS_SHIFT) /* 0x00000004 */ +#define GRF_GPIO2C_SUS_GPIO2C3_SUS_SHIFT (3U) +#define GRF_GPIO2C_SUS_GPIO2C3_SUS_MASK (0x1U << GRF_GPIO2C_SUS_GPIO2C3_SUS_SHIFT) /* 0x00000008 */ +#define GRF_GPIO2C_SUS_GPIO2C4_SUS_SHIFT (4U) +#define GRF_GPIO2C_SUS_GPIO2C4_SUS_MASK (0x1U << GRF_GPIO2C_SUS_GPIO2C4_SUS_SHIFT) /* 0x00000010 */ +#define GRF_GPIO2C_SUS_GPIO2C5_SUS_SHIFT (5U) +#define GRF_GPIO2C_SUS_GPIO2C5_SUS_MASK (0x1U << GRF_GPIO2C_SUS_GPIO2C5_SUS_SHIFT) /* 0x00000020 */ +#define GRF_GPIO2C_SUS_GPIO2C6_SUS_SHIFT (6U) +#define GRF_GPIO2C_SUS_GPIO2C6_SUS_MASK (0x1U << GRF_GPIO2C_SUS_GPIO2C6_SUS_SHIFT) /* 0x00000040 */ +#define GRF_GPIO2C_SUS_GPIO2C7_SUS_SHIFT (7U) +#define GRF_GPIO2C_SUS_GPIO2C7_SUS_MASK (0x1U << GRF_GPIO2C_SUS_GPIO2C7_SUS_SHIFT) /* 0x00000080 */ +/* GPIO2D_SUS */ +#define GRF_GPIO2D_SUS_OFFSET (0x4015CU) +#define GRF_GPIO2D_SUS_GPIO2D0_SUS_SHIFT (0U) +#define GRF_GPIO2D_SUS_GPIO2D0_SUS_MASK (0x1U << GRF_GPIO2D_SUS_GPIO2D0_SUS_SHIFT) /* 0x00000001 */ +#define GRF_GPIO2D_SUS_GPIO2D1_SUS_SHIFT (1U) +#define GRF_GPIO2D_SUS_GPIO2D1_SUS_MASK (0x1U << GRF_GPIO2D_SUS_GPIO2D1_SUS_SHIFT) /* 0x00000002 */ +#define GRF_GPIO2D_SUS_GPIO2D2_SUS_SHIFT (2U) +#define GRF_GPIO2D_SUS_GPIO2D2_SUS_MASK (0x1U << GRF_GPIO2D_SUS_GPIO2D2_SUS_SHIFT) /* 0x00000004 */ +#define GRF_GPIO2D_SUS_GPIO2D3_SUS_SHIFT (3U) +#define GRF_GPIO2D_SUS_GPIO2D3_SUS_MASK (0x1U << GRF_GPIO2D_SUS_GPIO2D3_SUS_SHIFT) /* 0x00000008 */ +#define GRF_GPIO2D_SUS_GPIO2D4_SUS_SHIFT (4U) +#define GRF_GPIO2D_SUS_GPIO2D4_SUS_MASK (0x1U << GRF_GPIO2D_SUS_GPIO2D4_SUS_SHIFT) /* 0x00000010 */ +#define GRF_GPIO2D_SUS_GPIO2D5_SUS_SHIFT (5U) +#define GRF_GPIO2D_SUS_GPIO2D5_SUS_MASK (0x1U << GRF_GPIO2D_SUS_GPIO2D5_SUS_SHIFT) /* 0x00000020 */ +#define GRF_GPIO2D_SUS_GPIO2D6_SUS_SHIFT (6U) +#define GRF_GPIO2D_SUS_GPIO2D6_SUS_MASK (0x1U << GRF_GPIO2D_SUS_GPIO2D6_SUS_SHIFT) /* 0x00000040 */ +#define GRF_GPIO2D_SUS_GPIO2D7_SUS_SHIFT (7U) +#define GRF_GPIO2D_SUS_GPIO2D7_SUS_MASK (0x1U << GRF_GPIO2D_SUS_GPIO2D7_SUS_SHIFT) /* 0x00000080 */ +/* GPIO3A_SUS */ +#define GRF_GPIO3A_SUS_OFFSET (0x40160U) +#define GRF_GPIO3A_SUS_GPIO3A0_SUS_SHIFT (0U) +#define GRF_GPIO3A_SUS_GPIO3A0_SUS_MASK (0x1U << GRF_GPIO3A_SUS_GPIO3A0_SUS_SHIFT) /* 0x00000001 */ +#define GRF_GPIO3A_SUS_GPIO3A1_SUS_SHIFT (1U) +#define GRF_GPIO3A_SUS_GPIO3A1_SUS_MASK (0x1U << GRF_GPIO3A_SUS_GPIO3A1_SUS_SHIFT) /* 0x00000002 */ +#define GRF_GPIO3A_SUS_GPIO3A2_SUS_SHIFT (2U) +#define GRF_GPIO3A_SUS_GPIO3A2_SUS_MASK (0x1U << GRF_GPIO3A_SUS_GPIO3A2_SUS_SHIFT) /* 0x00000004 */ +#define GRF_GPIO3A_SUS_GPIO3A3_SUS_SHIFT (3U) +#define GRF_GPIO3A_SUS_GPIO3A3_SUS_MASK (0x1U << GRF_GPIO3A_SUS_GPIO3A3_SUS_SHIFT) /* 0x00000008 */ +#define GRF_GPIO3A_SUS_GPIO3A4_SUS_SHIFT (4U) +#define GRF_GPIO3A_SUS_GPIO3A4_SUS_MASK (0x1U << GRF_GPIO3A_SUS_GPIO3A4_SUS_SHIFT) /* 0x00000010 */ +#define GRF_GPIO3A_SUS_GPIO3A5_SUS_SHIFT (5U) +#define GRF_GPIO3A_SUS_GPIO3A5_SUS_MASK (0x1U << GRF_GPIO3A_SUS_GPIO3A5_SUS_SHIFT) /* 0x00000020 */ +#define GRF_GPIO3A_SUS_GPIO3A6_SUS_SHIFT (6U) +#define GRF_GPIO3A_SUS_GPIO3A6_SUS_MASK (0x1U << GRF_GPIO3A_SUS_GPIO3A6_SUS_SHIFT) /* 0x00000040 */ +#define GRF_GPIO3A_SUS_GPIO3A7_SUS_SHIFT (7U) +#define GRF_GPIO3A_SUS_GPIO3A7_SUS_MASK (0x1U << GRF_GPIO3A_SUS_GPIO3A7_SUS_SHIFT) /* 0x00000080 */ +/* GPIO3B_SUS */ +#define GRF_GPIO3B_SUS_OFFSET (0x40164U) +#define GRF_GPIO3B_SUS_GPIO3B0_SUS_SHIFT (0U) +#define GRF_GPIO3B_SUS_GPIO3B0_SUS_MASK (0x1U << GRF_GPIO3B_SUS_GPIO3B0_SUS_SHIFT) /* 0x00000001 */ +#define GRF_GPIO3B_SUS_GPIO3B1_SUS_SHIFT (1U) +#define GRF_GPIO3B_SUS_GPIO3B1_SUS_MASK (0x1U << GRF_GPIO3B_SUS_GPIO3B1_SUS_SHIFT) /* 0x00000002 */ +#define GRF_GPIO3B_SUS_GPIO3B2_SUS_SHIFT (2U) +#define GRF_GPIO3B_SUS_GPIO3B2_SUS_MASK (0x1U << GRF_GPIO3B_SUS_GPIO3B2_SUS_SHIFT) /* 0x00000004 */ +#define GRF_GPIO3B_SUS_GPIO3B3_SUS_SHIFT (3U) +#define GRF_GPIO3B_SUS_GPIO3B3_SUS_MASK (0x1U << GRF_GPIO3B_SUS_GPIO3B3_SUS_SHIFT) /* 0x00000008 */ +#define GRF_GPIO3B_SUS_GPIO3B4_SUS_SHIFT (4U) +#define GRF_GPIO3B_SUS_GPIO3B4_SUS_MASK (0x1U << GRF_GPIO3B_SUS_GPIO3B4_SUS_SHIFT) /* 0x00000010 */ +#define GRF_GPIO3B_SUS_GPIO3B5_SUS_SHIFT (5U) +#define GRF_GPIO3B_SUS_GPIO3B5_SUS_MASK (0x1U << GRF_GPIO3B_SUS_GPIO3B5_SUS_SHIFT) /* 0x00000020 */ +#define GRF_GPIO3B_SUS_GPIO3B6_SUS_SHIFT (6U) +#define GRF_GPIO3B_SUS_GPIO3B6_SUS_MASK (0x1U << GRF_GPIO3B_SUS_GPIO3B6_SUS_SHIFT) /* 0x00000040 */ +#define GRF_GPIO3B_SUS_GPIO3B7_SUS_SHIFT (7U) +#define GRF_GPIO3B_SUS_GPIO3B7_SUS_MASK (0x1U << GRF_GPIO3B_SUS_GPIO3B7_SUS_SHIFT) /* 0x00000080 */ +/* GPIO3C_SUS */ +#define GRF_GPIO3C_SUS_OFFSET (0x40168U) +#define GRF_GPIO3C_SUS_GPIO3C0_SUS_SHIFT (0U) +#define GRF_GPIO3C_SUS_GPIO3C0_SUS_MASK (0x1U << GRF_GPIO3C_SUS_GPIO3C0_SUS_SHIFT) /* 0x00000001 */ +#define GRF_GPIO3C_SUS_GPIO3C1_SUS_SHIFT (1U) +#define GRF_GPIO3C_SUS_GPIO3C1_SUS_MASK (0x1U << GRF_GPIO3C_SUS_GPIO3C1_SUS_SHIFT) /* 0x00000002 */ +#define GRF_GPIO3C_SUS_GPIO3C2_SUS_SHIFT (2U) +#define GRF_GPIO3C_SUS_GPIO3C2_SUS_MASK (0x1U << GRF_GPIO3C_SUS_GPIO3C2_SUS_SHIFT) /* 0x00000004 */ +#define GRF_GPIO3C_SUS_GPIO3C3_SUS_SHIFT (3U) +#define GRF_GPIO3C_SUS_GPIO3C3_SUS_MASK (0x1U << GRF_GPIO3C_SUS_GPIO3C3_SUS_SHIFT) /* 0x00000008 */ +#define GRF_GPIO3C_SUS_GPIO3C4_SUS_SHIFT (4U) +#define GRF_GPIO3C_SUS_GPIO3C4_SUS_MASK (0x1U << GRF_GPIO3C_SUS_GPIO3C4_SUS_SHIFT) /* 0x00000010 */ +#define GRF_GPIO3C_SUS_GPIO3C5_SUS_SHIFT (5U) +#define GRF_GPIO3C_SUS_GPIO3C5_SUS_MASK (0x1U << GRF_GPIO3C_SUS_GPIO3C5_SUS_SHIFT) /* 0x00000020 */ +#define GRF_GPIO3C_SUS_GPIO3C6_SUS_SHIFT (6U) +#define GRF_GPIO3C_SUS_GPIO3C6_SUS_MASK (0x1U << GRF_GPIO3C_SUS_GPIO3C6_SUS_SHIFT) /* 0x00000040 */ +#define GRF_GPIO3C_SUS_GPIO3C7_SUS_SHIFT (7U) +#define GRF_GPIO3C_SUS_GPIO3C7_SUS_MASK (0x1U << GRF_GPIO3C_SUS_GPIO3C7_SUS_SHIFT) /* 0x00000080 */ +/* GPIO3D_SUS */ +#define GRF_GPIO3D_SUS_OFFSET (0x4016CU) +#define GRF_GPIO3D_SUS_GPIO3D0_SUS_SHIFT (0U) +#define GRF_GPIO3D_SUS_GPIO3D0_SUS_MASK (0x1U << GRF_GPIO3D_SUS_GPIO3D0_SUS_SHIFT) /* 0x00000001 */ +#define GRF_GPIO3D_SUS_GPIO3D1_SUS_SHIFT (1U) +#define GRF_GPIO3D_SUS_GPIO3D1_SUS_MASK (0x1U << GRF_GPIO3D_SUS_GPIO3D1_SUS_SHIFT) /* 0x00000002 */ +#define GRF_GPIO3D_SUS_GPIO3D2_SUS_SHIFT (2U) +#define GRF_GPIO3D_SUS_GPIO3D2_SUS_MASK (0x1U << GRF_GPIO3D_SUS_GPIO3D2_SUS_SHIFT) /* 0x00000004 */ +#define GRF_GPIO3D_SUS_GPIO3D3_SUS_SHIFT (3U) +#define GRF_GPIO3D_SUS_GPIO3D3_SUS_MASK (0x1U << GRF_GPIO3D_SUS_GPIO3D3_SUS_SHIFT) /* 0x00000008 */ +#define GRF_GPIO3D_SUS_GPIO3D4_SUS_SHIFT (4U) +#define GRF_GPIO3D_SUS_GPIO3D4_SUS_MASK (0x1U << GRF_GPIO3D_SUS_GPIO3D4_SUS_SHIFT) /* 0x00000010 */ +#define GRF_GPIO3D_SUS_GPIO3D5_SUS_SHIFT (5U) +#define GRF_GPIO3D_SUS_GPIO3D5_SUS_MASK (0x1U << GRF_GPIO3D_SUS_GPIO3D5_SUS_SHIFT) /* 0x00000020 */ +#define GRF_GPIO3D_SUS_GPIO3D6_SUS_SHIFT (6U) +#define GRF_GPIO3D_SUS_GPIO3D6_SUS_MASK (0x1U << GRF_GPIO3D_SUS_GPIO3D6_SUS_SHIFT) /* 0x00000040 */ +#define GRF_GPIO3D_SUS_GPIO3D7_SUS_SHIFT (7U) +#define GRF_GPIO3D_SUS_GPIO3D7_SUS_MASK (0x1U << GRF_GPIO3D_SUS_GPIO3D7_SUS_SHIFT) /* 0x00000080 */ +/* GPIO4A_SUS */ +#define GRF_GPIO4A_SUS_OFFSET (0x40170U) +#define GRF_GPIO4A_SUS_GPIO4A0_SUS_SHIFT (0U) +#define GRF_GPIO4A_SUS_GPIO4A0_SUS_MASK (0x1U << GRF_GPIO4A_SUS_GPIO4A0_SUS_SHIFT) /* 0x00000001 */ +#define GRF_GPIO4A_SUS_GPIO4A1_SUS_SHIFT (1U) +#define GRF_GPIO4A_SUS_GPIO4A1_SUS_MASK (0x1U << GRF_GPIO4A_SUS_GPIO4A1_SUS_SHIFT) /* 0x00000002 */ +#define GRF_GPIO4A_SUS_GPIO4A2_SUS_SHIFT (2U) +#define GRF_GPIO4A_SUS_GPIO4A2_SUS_MASK (0x1U << GRF_GPIO4A_SUS_GPIO4A2_SUS_SHIFT) /* 0x00000004 */ +#define GRF_GPIO4A_SUS_GPIO4A3_SUS_SHIFT (3U) +#define GRF_GPIO4A_SUS_GPIO4A3_SUS_MASK (0x1U << GRF_GPIO4A_SUS_GPIO4A3_SUS_SHIFT) /* 0x00000008 */ +#define GRF_GPIO4A_SUS_GPIO4A4_SUS_SHIFT (4U) +#define GRF_GPIO4A_SUS_GPIO4A4_SUS_MASK (0x1U << GRF_GPIO4A_SUS_GPIO4A4_SUS_SHIFT) /* 0x00000010 */ +#define GRF_GPIO4A_SUS_GPIO4A5_SUS_SHIFT (5U) +#define GRF_GPIO4A_SUS_GPIO4A5_SUS_MASK (0x1U << GRF_GPIO4A_SUS_GPIO4A5_SUS_SHIFT) /* 0x00000020 */ +#define GRF_GPIO4A_SUS_GPIO4A6_SUS_SHIFT (6U) +#define GRF_GPIO4A_SUS_GPIO4A6_SUS_MASK (0x1U << GRF_GPIO4A_SUS_GPIO4A6_SUS_SHIFT) /* 0x00000040 */ +#define GRF_GPIO4A_SUS_GPIO4A7_SUS_SHIFT (7U) +#define GRF_GPIO4A_SUS_GPIO4A7_SUS_MASK (0x1U << GRF_GPIO4A_SUS_GPIO4A7_SUS_SHIFT) /* 0x00000080 */ +/* GPIO4B_SUS */ +#define GRF_GPIO4B_SUS_OFFSET (0x40174U) +#define GRF_GPIO4B_SUS_GPIO4B0_SUS_SHIFT (0U) +#define GRF_GPIO4B_SUS_GPIO4B0_SUS_MASK (0x1U << GRF_GPIO4B_SUS_GPIO4B0_SUS_SHIFT) /* 0x00000001 */ +#define GRF_GPIO4B_SUS_GPIO4B1_SUS_SHIFT (1U) +#define GRF_GPIO4B_SUS_GPIO4B1_SUS_MASK (0x1U << GRF_GPIO4B_SUS_GPIO4B1_SUS_SHIFT) /* 0x00000002 */ +#define GRF_GPIO4B_SUS_GPIO4B2_SUS_SHIFT (2U) +#define GRF_GPIO4B_SUS_GPIO4B2_SUS_MASK (0x1U << GRF_GPIO4B_SUS_GPIO4B2_SUS_SHIFT) /* 0x00000004 */ +#define GRF_GPIO4B_SUS_GPIO4B3_SUS_SHIFT (3U) +#define GRF_GPIO4B_SUS_GPIO4B3_SUS_MASK (0x1U << GRF_GPIO4B_SUS_GPIO4B3_SUS_SHIFT) /* 0x00000008 */ +#define GRF_GPIO4B_SUS_GPIO4B4_SUS_SHIFT (4U) +#define GRF_GPIO4B_SUS_GPIO4B4_SUS_MASK (0x1U << GRF_GPIO4B_SUS_GPIO4B4_SUS_SHIFT) /* 0x00000010 */ +#define GRF_GPIO4B_SUS_GPIO4B5_SUS_SHIFT (5U) +#define GRF_GPIO4B_SUS_GPIO4B5_SUS_MASK (0x1U << GRF_GPIO4B_SUS_GPIO4B5_SUS_SHIFT) /* 0x00000020 */ +#define GRF_GPIO4B_SUS_GPIO4B6_SUS_SHIFT (6U) +#define GRF_GPIO4B_SUS_GPIO4B6_SUS_MASK (0x1U << GRF_GPIO4B_SUS_GPIO4B6_SUS_SHIFT) /* 0x00000040 */ +#define GRF_GPIO4B_SUS_GPIO4B7_SUS_SHIFT (7U) +#define GRF_GPIO4B_SUS_GPIO4B7_SUS_MASK (0x1U << GRF_GPIO4B_SUS_GPIO4B7_SUS_SHIFT) /* 0x00000080 */ +/* GPIO4C_SUS */ +#define GRF_GPIO4C_SUS_OFFSET (0x40178U) +#define GRF_GPIO4C_SUS_GPIO4C0_SUS_SHIFT (0U) +#define GRF_GPIO4C_SUS_GPIO4C0_SUS_MASK (0x1U << GRF_GPIO4C_SUS_GPIO4C0_SUS_SHIFT) /* 0x00000001 */ +#define GRF_GPIO4C_SUS_GPIO4C1_SUS_SHIFT (1U) +#define GRF_GPIO4C_SUS_GPIO4C1_SUS_MASK (0x1U << GRF_GPIO4C_SUS_GPIO4C1_SUS_SHIFT) /* 0x00000002 */ +#define GRF_GPIO4C_SUS_GPIO4C2_SUS_SHIFT (2U) +#define GRF_GPIO4C_SUS_GPIO4C2_SUS_MASK (0x1U << GRF_GPIO4C_SUS_GPIO4C2_SUS_SHIFT) /* 0x00000004 */ +#define GRF_GPIO4C_SUS_GPIO4C3_SUS_SHIFT (3U) +#define GRF_GPIO4C_SUS_GPIO4C3_SUS_MASK (0x1U << GRF_GPIO4C_SUS_GPIO4C3_SUS_SHIFT) /* 0x00000008 */ +#define GRF_GPIO4C_SUS_GPIO4C4_SUS_SHIFT (4U) +#define GRF_GPIO4C_SUS_GPIO4C4_SUS_MASK (0x1U << GRF_GPIO4C_SUS_GPIO4C4_SUS_SHIFT) /* 0x00000010 */ +#define GRF_GPIO4C_SUS_GPIO4C5_SUS_SHIFT (5U) +#define GRF_GPIO4C_SUS_GPIO4C5_SUS_MASK (0x1U << GRF_GPIO4C_SUS_GPIO4C5_SUS_SHIFT) /* 0x00000020 */ +#define GRF_GPIO4C_SUS_GPIO4C6_SUS_SHIFT (6U) +#define GRF_GPIO4C_SUS_GPIO4C6_SUS_MASK (0x1U << GRF_GPIO4C_SUS_GPIO4C6_SUS_SHIFT) /* 0x00000040 */ +#define GRF_GPIO4C_SUS_GPIO4C7_SUS_SHIFT (7U) +#define GRF_GPIO4C_SUS_GPIO4C7_SUS_MASK (0x1U << GRF_GPIO4C_SUS_GPIO4C7_SUS_SHIFT) /* 0x00000080 */ +/* GPIO4D_SUS */ +#define GRF_GPIO4D_SUS_OFFSET (0x4017CU) +#define GRF_GPIO4D_SUS_GPIO4D0_SUS_SHIFT (0U) +#define GRF_GPIO4D_SUS_GPIO4D0_SUS_MASK (0x1U << GRF_GPIO4D_SUS_GPIO4D0_SUS_SHIFT) /* 0x00000001 */ +#define GRF_GPIO4D_SUS_GPIO4D1_SUS_SHIFT (1U) +#define GRF_GPIO4D_SUS_GPIO4D1_SUS_MASK (0x1U << GRF_GPIO4D_SUS_GPIO4D1_SUS_SHIFT) /* 0x00000002 */ +#define GRF_GPIO4D_SUS_GPIO4D2_SUS_SHIFT (2U) +#define GRF_GPIO4D_SUS_GPIO4D2_SUS_MASK (0x1U << GRF_GPIO4D_SUS_GPIO4D2_SUS_SHIFT) /* 0x00000004 */ +#define GRF_GPIO4D_SUS_GPIO4D3_SUS_SHIFT (3U) +#define GRF_GPIO4D_SUS_GPIO4D3_SUS_MASK (0x1U << GRF_GPIO4D_SUS_GPIO4D3_SUS_SHIFT) /* 0x00000008 */ +#define GRF_GPIO4D_SUS_GPIO4D4_SUS_SHIFT (4U) +#define GRF_GPIO4D_SUS_GPIO4D4_SUS_MASK (0x1U << GRF_GPIO4D_SUS_GPIO4D4_SUS_SHIFT) /* 0x00000010 */ +#define GRF_GPIO4D_SUS_GPIO4D5_SUS_SHIFT (5U) +#define GRF_GPIO4D_SUS_GPIO4D5_SUS_MASK (0x1U << GRF_GPIO4D_SUS_GPIO4D5_SUS_SHIFT) /* 0x00000020 */ +#define GRF_GPIO4D_SUS_GPIO4D6_SUS_SHIFT (6U) +#define GRF_GPIO4D_SUS_GPIO4D6_SUS_MASK (0x1U << GRF_GPIO4D_SUS_GPIO4D6_SUS_SHIFT) /* 0x00000040 */ +#define GRF_GPIO4D_SUS_GPIO4D7_SUS_SHIFT (7U) +#define GRF_GPIO4D_SUS_GPIO4D7_SUS_MASK (0x1U << GRF_GPIO4D_SUS_GPIO4D7_SUS_SHIFT) /* 0x00000080 */ +/* GPIO1A_SL */ +#define GRF_GPIO1A_SL_OFFSET (0x40180U) +#define GRF_GPIO1A_SL_GPIO1A0_SL_SHIFT (0U) +#define GRF_GPIO1A_SL_GPIO1A0_SL_MASK (0x3U << GRF_GPIO1A_SL_GPIO1A0_SL_SHIFT) /* 0x00000003 */ +#define GRF_GPIO1A_SL_GPIO1A1_SL_SHIFT (2U) +#define GRF_GPIO1A_SL_GPIO1A1_SL_MASK (0x3U << GRF_GPIO1A_SL_GPIO1A1_SL_SHIFT) /* 0x0000000C */ +#define GRF_GPIO1A_SL_GPIO1A2_SL_SHIFT (4U) +#define GRF_GPIO1A_SL_GPIO1A2_SL_MASK (0x3U << GRF_GPIO1A_SL_GPIO1A2_SL_SHIFT) /* 0x00000030 */ +#define GRF_GPIO1A_SL_GPIO1A3_SL_SHIFT (6U) +#define GRF_GPIO1A_SL_GPIO1A3_SL_MASK (0x3U << GRF_GPIO1A_SL_GPIO1A3_SL_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO1A_SL_GPIO1A4_SL_SHIFT (8U) +#define GRF_GPIO1A_SL_GPIO1A4_SL_MASK (0x3U << GRF_GPIO1A_SL_GPIO1A4_SL_SHIFT) /* 0x00000300 */ +#define GRF_GPIO1A_SL_GPIO1A5_SL_SHIFT (10U) +#define GRF_GPIO1A_SL_GPIO1A5_SL_MASK (0x3U << GRF_GPIO1A_SL_GPIO1A5_SL_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO1A_SL_GPIO1A6_SL_SHIFT (12U) +#define GRF_GPIO1A_SL_GPIO1A6_SL_MASK (0x3U << GRF_GPIO1A_SL_GPIO1A6_SL_SHIFT) /* 0x00003000 */ +#define GRF_GPIO1A_SL_GPIO1A7_SL_SHIFT (14U) +#define GRF_GPIO1A_SL_GPIO1A7_SL_MASK (0x3U << GRF_GPIO1A_SL_GPIO1A7_SL_SHIFT) /* 0x0000C000 */ +/* GPIO1B_SL */ +#define GRF_GPIO1B_SL_OFFSET (0x40184U) +#define GRF_GPIO1B_SL_GPIO1B0_SL_SHIFT (0U) +#define GRF_GPIO1B_SL_GPIO1B0_SL_MASK (0x3U << GRF_GPIO1B_SL_GPIO1B0_SL_SHIFT) /* 0x00000003 */ +#define GRF_GPIO1B_SL_GPIO1B1_SL_SHIFT (2U) +#define GRF_GPIO1B_SL_GPIO1B1_SL_MASK (0x3U << GRF_GPIO1B_SL_GPIO1B1_SL_SHIFT) /* 0x0000000C */ +#define GRF_GPIO1B_SL_GPIO1B2_SL_SHIFT (4U) +#define GRF_GPIO1B_SL_GPIO1B2_SL_MASK (0x3U << GRF_GPIO1B_SL_GPIO1B2_SL_SHIFT) /* 0x00000030 */ +#define GRF_GPIO1B_SL_GPIO1B3_SL_SHIFT (6U) +#define GRF_GPIO1B_SL_GPIO1B3_SL_MASK (0x3U << GRF_GPIO1B_SL_GPIO1B3_SL_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO1B_SL_GPIO1B4_SL_SHIFT (8U) +#define GRF_GPIO1B_SL_GPIO1B4_SL_MASK (0x3U << GRF_GPIO1B_SL_GPIO1B4_SL_SHIFT) /* 0x00000300 */ +#define GRF_GPIO1B_SL_GPIO1B5_SL_SHIFT (10U) +#define GRF_GPIO1B_SL_GPIO1B5_SL_MASK (0x3U << GRF_GPIO1B_SL_GPIO1B5_SL_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO1B_SL_GPIO1B6_SL_SHIFT (12U) +#define GRF_GPIO1B_SL_GPIO1B6_SL_MASK (0x3U << GRF_GPIO1B_SL_GPIO1B6_SL_SHIFT) /* 0x00003000 */ +#define GRF_GPIO1B_SL_GPIO1B7_SL_SHIFT (14U) +#define GRF_GPIO1B_SL_GPIO1B7_SL_MASK (0x3U << GRF_GPIO1B_SL_GPIO1B7_SL_SHIFT) /* 0x0000C000 */ +/* GPIO1C_SL */ +#define GRF_GPIO1C_SL_OFFSET (0x40188U) +#define GRF_GPIO1C_SL_GPIO1C0_SL_SHIFT (0U) +#define GRF_GPIO1C_SL_GPIO1C0_SL_MASK (0x3U << GRF_GPIO1C_SL_GPIO1C0_SL_SHIFT) /* 0x00000003 */ +#define GRF_GPIO1C_SL_GPIO1C1_SL_SHIFT (2U) +#define GRF_GPIO1C_SL_GPIO1C1_SL_MASK (0x3U << GRF_GPIO1C_SL_GPIO1C1_SL_SHIFT) /* 0x0000000C */ +#define GRF_GPIO1C_SL_GPIO1C2_SL_SHIFT (4U) +#define GRF_GPIO1C_SL_GPIO1C2_SL_MASK (0x3U << GRF_GPIO1C_SL_GPIO1C2_SL_SHIFT) /* 0x00000030 */ +#define GRF_GPIO1C_SL_GPIO1C3_SL_SHIFT (6U) +#define GRF_GPIO1C_SL_GPIO1C3_SL_MASK (0x3U << GRF_GPIO1C_SL_GPIO1C3_SL_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO1C_SL_GPIO1C4_SL_SHIFT (8U) +#define GRF_GPIO1C_SL_GPIO1C4_SL_MASK (0x3U << GRF_GPIO1C_SL_GPIO1C4_SL_SHIFT) /* 0x00000300 */ +#define GRF_GPIO1C_SL_GPIO1C5_SL_SHIFT (10U) +#define GRF_GPIO1C_SL_GPIO1C5_SL_MASK (0x3U << GRF_GPIO1C_SL_GPIO1C5_SL_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO1C_SL_GPIO1C6_SL_SHIFT (12U) +#define GRF_GPIO1C_SL_GPIO1C6_SL_MASK (0x3U << GRF_GPIO1C_SL_GPIO1C6_SL_SHIFT) /* 0x00003000 */ +#define GRF_GPIO1C_SL_GPIO1C7_SL_SHIFT (14U) +#define GRF_GPIO1C_SL_GPIO1C7_SL_MASK (0x3U << GRF_GPIO1C_SL_GPIO1C7_SL_SHIFT) /* 0x0000C000 */ +/* GPIO1D_SL */ +#define GRF_GPIO1D_SL_OFFSET (0x4018CU) +#define GRF_GPIO1D_SL_GPIO1D0_SL_SHIFT (0U) +#define GRF_GPIO1D_SL_GPIO1D0_SL_MASK (0x3U << GRF_GPIO1D_SL_GPIO1D0_SL_SHIFT) /* 0x00000003 */ +#define GRF_GPIO1D_SL_GPIO1D1_SL_SHIFT (2U) +#define GRF_GPIO1D_SL_GPIO1D1_SL_MASK (0x3U << GRF_GPIO1D_SL_GPIO1D1_SL_SHIFT) /* 0x0000000C */ +#define GRF_GPIO1D_SL_GPIO1D2_SL_SHIFT (4U) +#define GRF_GPIO1D_SL_GPIO1D2_SL_MASK (0x3U << GRF_GPIO1D_SL_GPIO1D2_SL_SHIFT) /* 0x00000030 */ +#define GRF_GPIO1D_SL_GPIO1D3_SL_SHIFT (6U) +#define GRF_GPIO1D_SL_GPIO1D3_SL_MASK (0x3U << GRF_GPIO1D_SL_GPIO1D3_SL_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO1D_SL_GPIO1D4_SL_SHIFT (8U) +#define GRF_GPIO1D_SL_GPIO1D4_SL_MASK (0x3U << GRF_GPIO1D_SL_GPIO1D4_SL_SHIFT) /* 0x00000300 */ +#define GRF_GPIO1D_SL_GPIO1D5_SL_SHIFT (10U) +#define GRF_GPIO1D_SL_GPIO1D5_SL_MASK (0x3U << GRF_GPIO1D_SL_GPIO1D5_SL_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO1D_SL_GPIO1D6_SL_SHIFT (12U) +#define GRF_GPIO1D_SL_GPIO1D6_SL_MASK (0x3U << GRF_GPIO1D_SL_GPIO1D6_SL_SHIFT) /* 0x00003000 */ +#define GRF_GPIO1D_SL_GPIO1D7_SL_SHIFT (14U) +#define GRF_GPIO1D_SL_GPIO1D7_SL_MASK (0x3U << GRF_GPIO1D_SL_GPIO1D7_SL_SHIFT) /* 0x0000C000 */ +/* GPIO2A_SL */ +#define GRF_GPIO2A_SL_OFFSET (0x40190U) +#define GRF_GPIO2A_SL_GPIO2A0_SL_SHIFT (0U) +#define GRF_GPIO2A_SL_GPIO2A0_SL_MASK (0x3U << GRF_GPIO2A_SL_GPIO2A0_SL_SHIFT) /* 0x00000003 */ +#define GRF_GPIO2A_SL_GPIO2A1_SL_SHIFT (2U) +#define GRF_GPIO2A_SL_GPIO2A1_SL_MASK (0x3U << GRF_GPIO2A_SL_GPIO2A1_SL_SHIFT) /* 0x0000000C */ +#define GRF_GPIO2A_SL_GPIO2A2_SL_SHIFT (4U) +#define GRF_GPIO2A_SL_GPIO2A2_SL_MASK (0x3U << GRF_GPIO2A_SL_GPIO2A2_SL_SHIFT) /* 0x00000030 */ +#define GRF_GPIO2A_SL_GPIO2A3_SL_SHIFT (6U) +#define GRF_GPIO2A_SL_GPIO2A3_SL_MASK (0x3U << GRF_GPIO2A_SL_GPIO2A3_SL_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO2A_SL_GPIO2A4_SL_SHIFT (8U) +#define GRF_GPIO2A_SL_GPIO2A4_SL_MASK (0x3U << GRF_GPIO2A_SL_GPIO2A4_SL_SHIFT) /* 0x00000300 */ +#define GRF_GPIO2A_SL_GPIO2A5_SL_SHIFT (10U) +#define GRF_GPIO2A_SL_GPIO2A5_SL_MASK (0x3U << GRF_GPIO2A_SL_GPIO2A5_SL_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO2A_SL_GPIO2A6_SL_SHIFT (12U) +#define GRF_GPIO2A_SL_GPIO2A6_SL_MASK (0x3U << GRF_GPIO2A_SL_GPIO2A6_SL_SHIFT) /* 0x00003000 */ +#define GRF_GPIO2A_SL_GPIO2A7_SL_SHIFT (14U) +#define GRF_GPIO2A_SL_GPIO2A7_SL_MASK (0x3U << GRF_GPIO2A_SL_GPIO2A7_SL_SHIFT) /* 0x0000C000 */ +/* GPIO2B_SL */ +#define GRF_GPIO2B_SL_OFFSET (0x40194U) +#define GRF_GPIO2B_SL_GPIO2B0_SL_SHIFT (0U) +#define GRF_GPIO2B_SL_GPIO2B0_SL_MASK (0x3U << GRF_GPIO2B_SL_GPIO2B0_SL_SHIFT) /* 0x00000003 */ +#define GRF_GPIO2B_SL_GPIO2B1_SL_SHIFT (2U) +#define GRF_GPIO2B_SL_GPIO2B1_SL_MASK (0x3U << GRF_GPIO2B_SL_GPIO2B1_SL_SHIFT) /* 0x0000000C */ +#define GRF_GPIO2B_SL_GPIO2B2_SL_SHIFT (4U) +#define GRF_GPIO2B_SL_GPIO2B2_SL_MASK (0x3U << GRF_GPIO2B_SL_GPIO2B2_SL_SHIFT) /* 0x00000030 */ +#define GRF_GPIO2B_SL_GPIO2B3_SL_SHIFT (6U) +#define GRF_GPIO2B_SL_GPIO2B3_SL_MASK (0x3U << GRF_GPIO2B_SL_GPIO2B3_SL_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO2B_SL_GPIO2B4_SL_SHIFT (8U) +#define GRF_GPIO2B_SL_GPIO2B4_SL_MASK (0x3U << GRF_GPIO2B_SL_GPIO2B4_SL_SHIFT) /* 0x00000300 */ +#define GRF_GPIO2B_SL_GPIO2B5_SL_SHIFT (10U) +#define GRF_GPIO2B_SL_GPIO2B5_SL_MASK (0x3U << GRF_GPIO2B_SL_GPIO2B5_SL_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO2B_SL_GPIO2B6_SL_SHIFT (12U) +#define GRF_GPIO2B_SL_GPIO2B6_SL_MASK (0x3U << GRF_GPIO2B_SL_GPIO2B6_SL_SHIFT) /* 0x00003000 */ +#define GRF_GPIO2B_SL_GPIO2B7_SL_SHIFT (14U) +#define GRF_GPIO2B_SL_GPIO2B7_SL_MASK (0x3U << GRF_GPIO2B_SL_GPIO2B7_SL_SHIFT) /* 0x0000C000 */ +/* GPIO2C_SL */ +#define GRF_GPIO2C_SL_OFFSET (0x40198U) +#define GRF_GPIO2C_SL_GPIO2C0_SL_SHIFT (0U) +#define GRF_GPIO2C_SL_GPIO2C0_SL_MASK (0x3U << GRF_GPIO2C_SL_GPIO2C0_SL_SHIFT) /* 0x00000003 */ +#define GRF_GPIO2C_SL_GPIO2C1_SL_SHIFT (2U) +#define GRF_GPIO2C_SL_GPIO2C1_SL_MASK (0x3U << GRF_GPIO2C_SL_GPIO2C1_SL_SHIFT) /* 0x0000000C */ +#define GRF_GPIO2C_SL_GPIO2C2_SL_SHIFT (4U) +#define GRF_GPIO2C_SL_GPIO2C2_SL_MASK (0x3U << GRF_GPIO2C_SL_GPIO2C2_SL_SHIFT) /* 0x00000030 */ +#define GRF_GPIO2C_SL_GPIO2C3_SL_SHIFT (6U) +#define GRF_GPIO2C_SL_GPIO2C3_SL_MASK (0x3U << GRF_GPIO2C_SL_GPIO2C3_SL_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO2C_SL_GPIO2C4_SL_SHIFT (8U) +#define GRF_GPIO2C_SL_GPIO2C4_SL_MASK (0x3U << GRF_GPIO2C_SL_GPIO2C4_SL_SHIFT) /* 0x00000300 */ +#define GRF_GPIO2C_SL_GPIO2C5_SL_SHIFT (10U) +#define GRF_GPIO2C_SL_GPIO2C5_SL_MASK (0x3U << GRF_GPIO2C_SL_GPIO2C5_SL_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO2C_SL_GPIO2C6_SL_SHIFT (12U) +#define GRF_GPIO2C_SL_GPIO2C6_SL_MASK (0x3U << GRF_GPIO2C_SL_GPIO2C6_SL_SHIFT) /* 0x00003000 */ +#define GRF_GPIO2C_SL_GPIO2C7_SL_SHIFT (14U) +#define GRF_GPIO2C_SL_GPIO2C7_SL_MASK (0x3U << GRF_GPIO2C_SL_GPIO2C7_SL_SHIFT) /* 0x0000C000 */ +/* GPIO2D_SL */ +#define GRF_GPIO2D_SL_OFFSET (0x4019CU) +#define GRF_GPIO2D_SL_GPIO2D0_SL_SHIFT (0U) +#define GRF_GPIO2D_SL_GPIO2D0_SL_MASK (0x3U << GRF_GPIO2D_SL_GPIO2D0_SL_SHIFT) /* 0x00000003 */ +#define GRF_GPIO2D_SL_GPIO2D1_SL_SHIFT (2U) +#define GRF_GPIO2D_SL_GPIO2D1_SL_MASK (0x3U << GRF_GPIO2D_SL_GPIO2D1_SL_SHIFT) /* 0x0000000C */ +#define GRF_GPIO2D_SL_GPIO2D2_SL_SHIFT (4U) +#define GRF_GPIO2D_SL_GPIO2D2_SL_MASK (0x3U << GRF_GPIO2D_SL_GPIO2D2_SL_SHIFT) /* 0x00000030 */ +#define GRF_GPIO2D_SL_GPIO2D3_SL_SHIFT (6U) +#define GRF_GPIO2D_SL_GPIO2D3_SL_MASK (0x3U << GRF_GPIO2D_SL_GPIO2D3_SL_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO2D_SL_GPIO2D4_SL_SHIFT (8U) +#define GRF_GPIO2D_SL_GPIO2D4_SL_MASK (0x3U << GRF_GPIO2D_SL_GPIO2D4_SL_SHIFT) /* 0x00000300 */ +#define GRF_GPIO2D_SL_GPIO2D5_SL_SHIFT (10U) +#define GRF_GPIO2D_SL_GPIO2D5_SL_MASK (0x3U << GRF_GPIO2D_SL_GPIO2D5_SL_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO2D_SL_GPIO2D6_SL_SHIFT (12U) +#define GRF_GPIO2D_SL_GPIO2D6_SL_MASK (0x3U << GRF_GPIO2D_SL_GPIO2D6_SL_SHIFT) /* 0x00003000 */ +#define GRF_GPIO2D_SL_GPIO2D7_SL_SHIFT (14U) +#define GRF_GPIO2D_SL_GPIO2D7_SL_MASK (0x3U << GRF_GPIO2D_SL_GPIO2D7_SL_SHIFT) /* 0x0000C000 */ +/* GPIO3A_SL */ +#define GRF_GPIO3A_SL_OFFSET (0x401A0U) +#define GRF_GPIO3A_SL_GPIO3A0_SL_SHIFT (0U) +#define GRF_GPIO3A_SL_GPIO3A0_SL_MASK (0x3U << GRF_GPIO3A_SL_GPIO3A0_SL_SHIFT) /* 0x00000003 */ +#define GRF_GPIO3A_SL_GPIO3A1_SL_SHIFT (2U) +#define GRF_GPIO3A_SL_GPIO3A1_SL_MASK (0x3U << GRF_GPIO3A_SL_GPIO3A1_SL_SHIFT) /* 0x0000000C */ +#define GRF_GPIO3A_SL_GPIO3A2_SL_SHIFT (4U) +#define GRF_GPIO3A_SL_GPIO3A2_SL_MASK (0x3U << GRF_GPIO3A_SL_GPIO3A2_SL_SHIFT) /* 0x00000030 */ +#define GRF_GPIO3A_SL_GPIO3A3_SL_SHIFT (6U) +#define GRF_GPIO3A_SL_GPIO3A3_SL_MASK (0x3U << GRF_GPIO3A_SL_GPIO3A3_SL_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO3A_SL_GPIO3A4_SL_SHIFT (8U) +#define GRF_GPIO3A_SL_GPIO3A4_SL_MASK (0x3U << GRF_GPIO3A_SL_GPIO3A4_SL_SHIFT) /* 0x00000300 */ +#define GRF_GPIO3A_SL_GPIO3A5_SL_SHIFT (10U) +#define GRF_GPIO3A_SL_GPIO3A5_SL_MASK (0x3U << GRF_GPIO3A_SL_GPIO3A5_SL_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO3A_SL_GPIO3A6_SL_SHIFT (12U) +#define GRF_GPIO3A_SL_GPIO3A6_SL_MASK (0x3U << GRF_GPIO3A_SL_GPIO3A6_SL_SHIFT) /* 0x00003000 */ +#define GRF_GPIO3A_SL_GPIO3A7_SL_SHIFT (14U) +#define GRF_GPIO3A_SL_GPIO3A7_SL_MASK (0x3U << GRF_GPIO3A_SL_GPIO3A7_SL_SHIFT) /* 0x0000C000 */ +/* GPIO3B_SL */ +#define GRF_GPIO3B_SL_OFFSET (0x401A4U) +#define GRF_GPIO3B_SL_GPIO3B0_SL_SHIFT (0U) +#define GRF_GPIO3B_SL_GPIO3B0_SL_MASK (0x3U << GRF_GPIO3B_SL_GPIO3B0_SL_SHIFT) /* 0x00000003 */ +#define GRF_GPIO3B_SL_GPIO3B1_SL_SHIFT (2U) +#define GRF_GPIO3B_SL_GPIO3B1_SL_MASK (0x3U << GRF_GPIO3B_SL_GPIO3B1_SL_SHIFT) /* 0x0000000C */ +#define GRF_GPIO3B_SL_GPIO3B2_SL_SHIFT (4U) +#define GRF_GPIO3B_SL_GPIO3B2_SL_MASK (0x3U << GRF_GPIO3B_SL_GPIO3B2_SL_SHIFT) /* 0x00000030 */ +#define GRF_GPIO3B_SL_GPIO3B3_SL_SHIFT (6U) +#define GRF_GPIO3B_SL_GPIO3B3_SL_MASK (0x3U << GRF_GPIO3B_SL_GPIO3B3_SL_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO3B_SL_GPIO3B4_SL_SHIFT (8U) +#define GRF_GPIO3B_SL_GPIO3B4_SL_MASK (0x3U << GRF_GPIO3B_SL_GPIO3B4_SL_SHIFT) /* 0x00000300 */ +#define GRF_GPIO3B_SL_GPIO3B5_SL_SHIFT (10U) +#define GRF_GPIO3B_SL_GPIO3B5_SL_MASK (0x3U << GRF_GPIO3B_SL_GPIO3B5_SL_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO3B_SL_GPIO3B6_SL_SHIFT (12U) +#define GRF_GPIO3B_SL_GPIO3B6_SL_MASK (0x3U << GRF_GPIO3B_SL_GPIO3B6_SL_SHIFT) /* 0x00003000 */ +#define GRF_GPIO3B_SL_GPIO3B7_SL_SHIFT (14U) +#define GRF_GPIO3B_SL_GPIO3B7_SL_MASK (0x3U << GRF_GPIO3B_SL_GPIO3B7_SL_SHIFT) /* 0x0000C000 */ +/* GPIO3C_SL */ +#define GRF_GPIO3C_SL_OFFSET (0x401A8U) +#define GRF_GPIO3C_SL_GPIO3C0_SL_SHIFT (0U) +#define GRF_GPIO3C_SL_GPIO3C0_SL_MASK (0x3U << GRF_GPIO3C_SL_GPIO3C0_SL_SHIFT) /* 0x00000003 */ +#define GRF_GPIO3C_SL_GPIO3C1_SL_SHIFT (2U) +#define GRF_GPIO3C_SL_GPIO3C1_SL_MASK (0x3U << GRF_GPIO3C_SL_GPIO3C1_SL_SHIFT) /* 0x0000000C */ +#define GRF_GPIO3C_SL_GPIO3C2_SL_SHIFT (4U) +#define GRF_GPIO3C_SL_GPIO3C2_SL_MASK (0x3U << GRF_GPIO3C_SL_GPIO3C2_SL_SHIFT) /* 0x00000030 */ +#define GRF_GPIO3C_SL_GPIO3C3_SL_SHIFT (6U) +#define GRF_GPIO3C_SL_GPIO3C3_SL_MASK (0x3U << GRF_GPIO3C_SL_GPIO3C3_SL_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO3C_SL_GPIO3C4_SL_SHIFT (8U) +#define GRF_GPIO3C_SL_GPIO3C4_SL_MASK (0x3U << GRF_GPIO3C_SL_GPIO3C4_SL_SHIFT) /* 0x00000300 */ +#define GRF_GPIO3C_SL_GPIO3C5_SL_SHIFT (10U) +#define GRF_GPIO3C_SL_GPIO3C5_SL_MASK (0x3U << GRF_GPIO3C_SL_GPIO3C5_SL_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO3C_SL_GPIO3C6_SL_SHIFT (12U) +#define GRF_GPIO3C_SL_GPIO3C6_SL_MASK (0x3U << GRF_GPIO3C_SL_GPIO3C6_SL_SHIFT) /* 0x00003000 */ +#define GRF_GPIO3C_SL_GPIO3C7_SL_SHIFT (14U) +#define GRF_GPIO3C_SL_GPIO3C7_SL_MASK (0x3U << GRF_GPIO3C_SL_GPIO3C7_SL_SHIFT) /* 0x0000C000 */ +/* GPIO3D_SL */ +#define GRF_GPIO3D_SL_OFFSET (0x401ACU) +#define GRF_GPIO3D_SL_GPIO3D0_SL_SHIFT (0U) +#define GRF_GPIO3D_SL_GPIO3D0_SL_MASK (0x3U << GRF_GPIO3D_SL_GPIO3D0_SL_SHIFT) /* 0x00000003 */ +#define GRF_GPIO3D_SL_GPIO3D1_SL_SHIFT (2U) +#define GRF_GPIO3D_SL_GPIO3D1_SL_MASK (0x3U << GRF_GPIO3D_SL_GPIO3D1_SL_SHIFT) /* 0x0000000C */ +#define GRF_GPIO3D_SL_GPIO3D2_SL_SHIFT (4U) +#define GRF_GPIO3D_SL_GPIO3D2_SL_MASK (0x3U << GRF_GPIO3D_SL_GPIO3D2_SL_SHIFT) /* 0x00000030 */ +#define GRF_GPIO3D_SL_GPIO3D3_SL_SHIFT (6U) +#define GRF_GPIO3D_SL_GPIO3D3_SL_MASK (0x3U << GRF_GPIO3D_SL_GPIO3D3_SL_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO3D_SL_GPIO3D4_SL_SHIFT (8U) +#define GRF_GPIO3D_SL_GPIO3D4_SL_MASK (0x3U << GRF_GPIO3D_SL_GPIO3D4_SL_SHIFT) /* 0x00000300 */ +#define GRF_GPIO3D_SL_GPIO3D5_SL_SHIFT (10U) +#define GRF_GPIO3D_SL_GPIO3D5_SL_MASK (0x3U << GRF_GPIO3D_SL_GPIO3D5_SL_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO3D_SL_GPIO3D6_SL_SHIFT (12U) +#define GRF_GPIO3D_SL_GPIO3D6_SL_MASK (0x3U << GRF_GPIO3D_SL_GPIO3D6_SL_SHIFT) /* 0x00003000 */ +#define GRF_GPIO3D_SL_GPIO3D7_SL_SHIFT (14U) +#define GRF_GPIO3D_SL_GPIO3D7_SL_MASK (0x3U << GRF_GPIO3D_SL_GPIO3D7_SL_SHIFT) /* 0x0000C000 */ +/* GPIO4A_SL */ +#define GRF_GPIO4A_SL_OFFSET (0x401B0U) +#define GRF_GPIO4A_SL_GPIO4A0_SL_SHIFT (0U) +#define GRF_GPIO4A_SL_GPIO4A0_SL_MASK (0x3U << GRF_GPIO4A_SL_GPIO4A0_SL_SHIFT) /* 0x00000003 */ +#define GRF_GPIO4A_SL_GPIO4A1_SL_SHIFT (2U) +#define GRF_GPIO4A_SL_GPIO4A1_SL_MASK (0x3U << GRF_GPIO4A_SL_GPIO4A1_SL_SHIFT) /* 0x0000000C */ +#define GRF_GPIO4A_SL_GPIO4A2_SL_SHIFT (4U) +#define GRF_GPIO4A_SL_GPIO4A2_SL_MASK (0x3U << GRF_GPIO4A_SL_GPIO4A2_SL_SHIFT) /* 0x00000030 */ +#define GRF_GPIO4A_SL_GPIO4A3_SL_SHIFT (6U) +#define GRF_GPIO4A_SL_GPIO4A3_SL_MASK (0x3U << GRF_GPIO4A_SL_GPIO4A3_SL_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO4A_SL_GPIO4A4_SL_SHIFT (8U) +#define GRF_GPIO4A_SL_GPIO4A4_SL_MASK (0x3U << GRF_GPIO4A_SL_GPIO4A4_SL_SHIFT) /* 0x00000300 */ +#define GRF_GPIO4A_SL_GPIO4A5_SL_SHIFT (10U) +#define GRF_GPIO4A_SL_GPIO4A5_SL_MASK (0x3U << GRF_GPIO4A_SL_GPIO4A5_SL_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO4A_SL_GPIO4A6_SL_SHIFT (12U) +#define GRF_GPIO4A_SL_GPIO4A6_SL_MASK (0x3U << GRF_GPIO4A_SL_GPIO4A6_SL_SHIFT) /* 0x00003000 */ +#define GRF_GPIO4A_SL_GPIO4A7_SL_SHIFT (14U) +#define GRF_GPIO4A_SL_GPIO4A7_SL_MASK (0x3U << GRF_GPIO4A_SL_GPIO4A7_SL_SHIFT) /* 0x0000C000 */ +/* GPIO4B_SL */ +#define GRF_GPIO4B_SL_OFFSET (0x401B4U) +#define GRF_GPIO4B_SL_GPIO4B0_SL_SHIFT (0U) +#define GRF_GPIO4B_SL_GPIO4B0_SL_MASK (0x3U << GRF_GPIO4B_SL_GPIO4B0_SL_SHIFT) /* 0x00000003 */ +#define GRF_GPIO4B_SL_GPIO4B1_SL_SHIFT (2U) +#define GRF_GPIO4B_SL_GPIO4B1_SL_MASK (0x3U << GRF_GPIO4B_SL_GPIO4B1_SL_SHIFT) /* 0x0000000C */ +#define GRF_GPIO4B_SL_GPIO4B2_SL_SHIFT (4U) +#define GRF_GPIO4B_SL_GPIO4B2_SL_MASK (0x3U << GRF_GPIO4B_SL_GPIO4B2_SL_SHIFT) /* 0x00000030 */ +#define GRF_GPIO4B_SL_GPIO4B3_SL_SHIFT (6U) +#define GRF_GPIO4B_SL_GPIO4B3_SL_MASK (0x3U << GRF_GPIO4B_SL_GPIO4B3_SL_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO4B_SL_GPIO4B4_SL_SHIFT (8U) +#define GRF_GPIO4B_SL_GPIO4B4_SL_MASK (0x3U << GRF_GPIO4B_SL_GPIO4B4_SL_SHIFT) /* 0x00000300 */ +#define GRF_GPIO4B_SL_GPIO4B5_SL_SHIFT (10U) +#define GRF_GPIO4B_SL_GPIO4B5_SL_MASK (0x3U << GRF_GPIO4B_SL_GPIO4B5_SL_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO4B_SL_GPIO4B6_SL_SHIFT (12U) +#define GRF_GPIO4B_SL_GPIO4B6_SL_MASK (0x3U << GRF_GPIO4B_SL_GPIO4B6_SL_SHIFT) /* 0x00003000 */ +#define GRF_GPIO4B_SL_GPIO4B7_SL_SHIFT (14U) +#define GRF_GPIO4B_SL_GPIO4B7_SL_MASK (0x3U << GRF_GPIO4B_SL_GPIO4B7_SL_SHIFT) /* 0x0000C000 */ +/* GPIO4C_SL */ +#define GRF_GPIO4C_SL_OFFSET (0x401B8U) +#define GRF_GPIO4C_SL_GPIO4C0_SL_SHIFT (0U) +#define GRF_GPIO4C_SL_GPIO4C0_SL_MASK (0x3U << GRF_GPIO4C_SL_GPIO4C0_SL_SHIFT) /* 0x00000003 */ +#define GRF_GPIO4C_SL_GPIO4C1_SL_SHIFT (2U) +#define GRF_GPIO4C_SL_GPIO4C1_SL_MASK (0x3U << GRF_GPIO4C_SL_GPIO4C1_SL_SHIFT) /* 0x0000000C */ +#define GRF_GPIO4C_SL_GPIO4C2_SL_SHIFT (4U) +#define GRF_GPIO4C_SL_GPIO4C2_SL_MASK (0x3U << GRF_GPIO4C_SL_GPIO4C2_SL_SHIFT) /* 0x00000030 */ +#define GRF_GPIO4C_SL_GPIO4C3_SL_SHIFT (6U) +#define GRF_GPIO4C_SL_GPIO4C3_SL_MASK (0x3U << GRF_GPIO4C_SL_GPIO4C3_SL_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO4C_SL_GPIO4C4_SL_SHIFT (8U) +#define GRF_GPIO4C_SL_GPIO4C4_SL_MASK (0x3U << GRF_GPIO4C_SL_GPIO4C4_SL_SHIFT) /* 0x00000300 */ +#define GRF_GPIO4C_SL_GPIO4C5_SL_SHIFT (10U) +#define GRF_GPIO4C_SL_GPIO4C5_SL_MASK (0x3U << GRF_GPIO4C_SL_GPIO4C5_SL_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO4C_SL_GPIO4C6_SL_SHIFT (12U) +#define GRF_GPIO4C_SL_GPIO4C6_SL_MASK (0x3U << GRF_GPIO4C_SL_GPIO4C6_SL_SHIFT) /* 0x00003000 */ +#define GRF_GPIO4C_SL_GPIO4C7_SL_SHIFT (14U) +#define GRF_GPIO4C_SL_GPIO4C7_SL_MASK (0x3U << GRF_GPIO4C_SL_GPIO4C7_SL_SHIFT) /* 0x0000C000 */ +/* GPIO4D_SL */ +#define GRF_GPIO4D_SL_OFFSET (0x401BCU) +#define GRF_GPIO4D_SL_GPIO4D0_SL_SHIFT (0U) +#define GRF_GPIO4D_SL_GPIO4D0_SL_MASK (0x3U << GRF_GPIO4D_SL_GPIO4D0_SL_SHIFT) /* 0x00000003 */ +#define GRF_GPIO4D_SL_GPIO4D1_SL_SHIFT (2U) +#define GRF_GPIO4D_SL_GPIO4D1_SL_MASK (0x3U << GRF_GPIO4D_SL_GPIO4D1_SL_SHIFT) /* 0x0000000C */ +#define GRF_GPIO4D_SL_GPIO4D2_SL_SHIFT (4U) +#define GRF_GPIO4D_SL_GPIO4D2_SL_MASK (0x3U << GRF_GPIO4D_SL_GPIO4D2_SL_SHIFT) /* 0x00000030 */ +#define GRF_GPIO4D_SL_GPIO4D3_SL_SHIFT (6U) +#define GRF_GPIO4D_SL_GPIO4D3_SL_MASK (0x3U << GRF_GPIO4D_SL_GPIO4D3_SL_SHIFT) /* 0x000000C0 */ +#define GRF_GPIO4D_SL_GPIO4D4_SL_SHIFT (8U) +#define GRF_GPIO4D_SL_GPIO4D4_SL_MASK (0x3U << GRF_GPIO4D_SL_GPIO4D4_SL_SHIFT) /* 0x00000300 */ +#define GRF_GPIO4D_SL_GPIO4D5_SL_SHIFT (10U) +#define GRF_GPIO4D_SL_GPIO4D5_SL_MASK (0x3U << GRF_GPIO4D_SL_GPIO4D5_SL_SHIFT) /* 0x00000C00 */ +#define GRF_GPIO4D_SL_GPIO4D6_SL_SHIFT (12U) +#define GRF_GPIO4D_SL_GPIO4D6_SL_MASK (0x3U << GRF_GPIO4D_SL_GPIO4D6_SL_SHIFT) /* 0x00003000 */ +#define GRF_GPIO4D_SL_GPIO4D7_SL_SHIFT (14U) +#define GRF_GPIO4D_SL_GPIO4D7_SL_MASK (0x3U << GRF_GPIO4D_SL_GPIO4D7_SL_SHIFT) /* 0x0000C000 */ +/* GPIO1A_DS_0 */ +#define GRF_GPIO1A_DS_0_OFFSET (0x40200U) +#define GRF_GPIO1A_DS_0_GPIO1A0_DS_SHIFT (0U) +#define GRF_GPIO1A_DS_0_GPIO1A0_DS_MASK (0x3FU << GRF_GPIO1A_DS_0_GPIO1A0_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO1A_DS_0_GPIO1A1_DS_SHIFT (8U) +#define GRF_GPIO1A_DS_0_GPIO1A1_DS_MASK (0x3FU << GRF_GPIO1A_DS_0_GPIO1A1_DS_SHIFT) /* 0x00003F00 */ +/* GPIO1A_DS_1 */ +#define GRF_GPIO1A_DS_1_OFFSET (0x40204U) +#define GRF_GPIO1A_DS_1_GPIO1A2_DS_SHIFT (0U) +#define GRF_GPIO1A_DS_1_GPIO1A2_DS_MASK (0x3FU << GRF_GPIO1A_DS_1_GPIO1A2_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO1A_DS_1_GPIO1A3_DS_SHIFT (8U) +#define GRF_GPIO1A_DS_1_GPIO1A3_DS_MASK (0x3FU << GRF_GPIO1A_DS_1_GPIO1A3_DS_SHIFT) /* 0x00003F00 */ +/* GPIO1A_DS_2 */ +#define GRF_GPIO1A_DS_2_OFFSET (0x40208U) +#define GRF_GPIO1A_DS_2_GPIO1A4_DS_SHIFT (0U) +#define GRF_GPIO1A_DS_2_GPIO1A4_DS_MASK (0x3FU << GRF_GPIO1A_DS_2_GPIO1A4_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO1A_DS_2_GPIO1A5_DS_SHIFT (8U) +#define GRF_GPIO1A_DS_2_GPIO1A5_DS_MASK (0x3FU << GRF_GPIO1A_DS_2_GPIO1A5_DS_SHIFT) /* 0x00003F00 */ +/* GPIO1A_DS_3 */ +#define GRF_GPIO1A_DS_3_OFFSET (0x4020CU) +#define GRF_GPIO1A_DS_3_GPIO1A6_DS_SHIFT (0U) +#define GRF_GPIO1A_DS_3_GPIO1A6_DS_MASK (0x3FU << GRF_GPIO1A_DS_3_GPIO1A6_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO1A_DS_3_GPIO1A7_DS_SHIFT (8U) +#define GRF_GPIO1A_DS_3_GPIO1A7_DS_MASK (0x3FU << GRF_GPIO1A_DS_3_GPIO1A7_DS_SHIFT) /* 0x00003F00 */ +/* GPIO1B_DS_0 */ +#define GRF_GPIO1B_DS_0_OFFSET (0x40210U) +#define GRF_GPIO1B_DS_0_GPIO1B0_DS_SHIFT (0U) +#define GRF_GPIO1B_DS_0_GPIO1B0_DS_MASK (0x3FU << GRF_GPIO1B_DS_0_GPIO1B0_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO1B_DS_0_GPIO1B1_DS_SHIFT (8U) +#define GRF_GPIO1B_DS_0_GPIO1B1_DS_MASK (0x3FU << GRF_GPIO1B_DS_0_GPIO1B1_DS_SHIFT) /* 0x00003F00 */ +/* GPIO1B_DS_1 */ +#define GRF_GPIO1B_DS_1_OFFSET (0x40214U) +#define GRF_GPIO1B_DS_1_GPIO1B2_DS_SHIFT (0U) +#define GRF_GPIO1B_DS_1_GPIO1B2_DS_MASK (0x3FU << GRF_GPIO1B_DS_1_GPIO1B2_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO1B_DS_1_GPIO1B3_DS_SHIFT (8U) +#define GRF_GPIO1B_DS_1_GPIO1B3_DS_MASK (0x3FU << GRF_GPIO1B_DS_1_GPIO1B3_DS_SHIFT) /* 0x00003F00 */ +/* GPIO1B_DS_2 */ +#define GRF_GPIO1B_DS_2_OFFSET (0x40218U) +#define GRF_GPIO1B_DS_2_GPIO1B4_DS_SHIFT (0U) +#define GRF_GPIO1B_DS_2_GPIO1B4_DS_MASK (0x3FU << GRF_GPIO1B_DS_2_GPIO1B4_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO1B_DS_2_GPIO1B5_DS_SHIFT (8U) +#define GRF_GPIO1B_DS_2_GPIO1B5_DS_MASK (0x3FU << GRF_GPIO1B_DS_2_GPIO1B5_DS_SHIFT) /* 0x00003F00 */ +/* GPIO1B_DS_3 */ +#define GRF_GPIO1B_DS_3_OFFSET (0x4021CU) +#define GRF_GPIO1B_DS_3_GPIO1B6_DS_SHIFT (0U) +#define GRF_GPIO1B_DS_3_GPIO1B6_DS_MASK (0x3FU << GRF_GPIO1B_DS_3_GPIO1B6_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO1B_DS_3_GPIO1B7_DS_SHIFT (8U) +#define GRF_GPIO1B_DS_3_GPIO1B7_DS_MASK (0x3FU << GRF_GPIO1B_DS_3_GPIO1B7_DS_SHIFT) /* 0x00003F00 */ +/* GPIO1C_DS_0 */ +#define GRF_GPIO1C_DS_0_OFFSET (0x40220U) +#define GRF_GPIO1C_DS_0_GPIO1C0_DS_SHIFT (0U) +#define GRF_GPIO1C_DS_0_GPIO1C0_DS_MASK (0x3FU << GRF_GPIO1C_DS_0_GPIO1C0_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO1C_DS_0_GPIO1C1_DS_SHIFT (8U) +#define GRF_GPIO1C_DS_0_GPIO1C1_DS_MASK (0x3FU << GRF_GPIO1C_DS_0_GPIO1C1_DS_SHIFT) /* 0x00003F00 */ +/* GPIO1C_DS_1 */ +#define GRF_GPIO1C_DS_1_OFFSET (0x40224U) +#define GRF_GPIO1C_DS_1_GPIO1C2_DS_SHIFT (0U) +#define GRF_GPIO1C_DS_1_GPIO1C2_DS_MASK (0x3FU << GRF_GPIO1C_DS_1_GPIO1C2_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO1C_DS_1_GPIO1C3_DS_SHIFT (8U) +#define GRF_GPIO1C_DS_1_GPIO1C3_DS_MASK (0x3FU << GRF_GPIO1C_DS_1_GPIO1C3_DS_SHIFT) /* 0x00003F00 */ +/* GPIO1C_DS_2 */ +#define GRF_GPIO1C_DS_2_OFFSET (0x40228U) +#define GRF_GPIO1C_DS_2_GPIO1C4_DS_SHIFT (0U) +#define GRF_GPIO1C_DS_2_GPIO1C4_DS_MASK (0x3FU << GRF_GPIO1C_DS_2_GPIO1C4_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO1C_DS_2_GPIO1C5_DS_SHIFT (8U) +#define GRF_GPIO1C_DS_2_GPIO1C5_DS_MASK (0x3FU << GRF_GPIO1C_DS_2_GPIO1C5_DS_SHIFT) /* 0x00003F00 */ +/* GPIO1C_DS_3 */ +#define GRF_GPIO1C_DS_3_OFFSET (0x4022CU) +#define GRF_GPIO1C_DS_3_GPIO1C6_DS_SHIFT (0U) +#define GRF_GPIO1C_DS_3_GPIO1C6_DS_MASK (0x3FU << GRF_GPIO1C_DS_3_GPIO1C6_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO1C_DS_3_GPIO1C7_DS_SHIFT (8U) +#define GRF_GPIO1C_DS_3_GPIO1C7_DS_MASK (0x3FU << GRF_GPIO1C_DS_3_GPIO1C7_DS_SHIFT) /* 0x00003F00 */ +/* GPIO1D_DS_0 */ +#define GRF_GPIO1D_DS_0_OFFSET (0x40230U) +#define GRF_GPIO1D_DS_0_GPIO1D0_DS_SHIFT (0U) +#define GRF_GPIO1D_DS_0_GPIO1D0_DS_MASK (0x3FU << GRF_GPIO1D_DS_0_GPIO1D0_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO1D_DS_0_GPIO1D1_DS_SHIFT (8U) +#define GRF_GPIO1D_DS_0_GPIO1D1_DS_MASK (0x3FU << GRF_GPIO1D_DS_0_GPIO1D1_DS_SHIFT) /* 0x00003F00 */ +/* GPIO1D_DS_1 */ +#define GRF_GPIO1D_DS_1_OFFSET (0x40234U) +#define GRF_GPIO1D_DS_1_GPIO1D2_DS_SHIFT (0U) +#define GRF_GPIO1D_DS_1_GPIO1D2_DS_MASK (0x3FU << GRF_GPIO1D_DS_1_GPIO1D2_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO1D_DS_1_GPIO1D3_DS_SHIFT (8U) +#define GRF_GPIO1D_DS_1_GPIO1D3_DS_MASK (0x3FU << GRF_GPIO1D_DS_1_GPIO1D3_DS_SHIFT) /* 0x00003F00 */ +/* GPIO1D_DS_2 */ +#define GRF_GPIO1D_DS_2_OFFSET (0x40238U) +#define GRF_GPIO1D_DS_2_GPIO1D4_DS_SHIFT (0U) +#define GRF_GPIO1D_DS_2_GPIO1D4_DS_MASK (0x3FU << GRF_GPIO1D_DS_2_GPIO1D4_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO1D_DS_2_GPIO1D5_DS_SHIFT (8U) +#define GRF_GPIO1D_DS_2_GPIO1D5_DS_MASK (0x3FU << GRF_GPIO1D_DS_2_GPIO1D5_DS_SHIFT) /* 0x00003F00 */ +/* GPIO1D_DS_3 */ +#define GRF_GPIO1D_DS_3_OFFSET (0x4023CU) +#define GRF_GPIO1D_DS_3_GPIO1D6_DS_SHIFT (0U) +#define GRF_GPIO1D_DS_3_GPIO1D6_DS_MASK (0x3FU << GRF_GPIO1D_DS_3_GPIO1D6_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO1D_DS_3_GPIO1D7_DS_SHIFT (8U) +#define GRF_GPIO1D_DS_3_GPIO1D7_DS_MASK (0x3FU << GRF_GPIO1D_DS_3_GPIO1D7_DS_SHIFT) /* 0x00003F00 */ +/* GPIO2A_DS_0 */ +#define GRF_GPIO2A_DS_0_OFFSET (0x40240U) +#define GRF_GPIO2A_DS_0_GPIO2A0_DS_SHIFT (0U) +#define GRF_GPIO2A_DS_0_GPIO2A0_DS_MASK (0x3FU << GRF_GPIO2A_DS_0_GPIO2A0_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO2A_DS_0_GPIO2A1_DS_SHIFT (8U) +#define GRF_GPIO2A_DS_0_GPIO2A1_DS_MASK (0x3FU << GRF_GPIO2A_DS_0_GPIO2A1_DS_SHIFT) /* 0x00003F00 */ +/* GPIO2A_DS_1 */ +#define GRF_GPIO2A_DS_1_OFFSET (0x40244U) +#define GRF_GPIO2A_DS_1_GPIO2A2_DS_SHIFT (0U) +#define GRF_GPIO2A_DS_1_GPIO2A2_DS_MASK (0x3FU << GRF_GPIO2A_DS_1_GPIO2A2_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO2A_DS_1_GPIO2A3_DS_SHIFT (8U) +#define GRF_GPIO2A_DS_1_GPIO2A3_DS_MASK (0x3FU << GRF_GPIO2A_DS_1_GPIO2A3_DS_SHIFT) /* 0x00003F00 */ +/* GPIO2A_DS_2 */ +#define GRF_GPIO2A_DS_2_OFFSET (0x40248U) +#define GRF_GPIO2A_DS_2_GPIO2A4_DS_SHIFT (0U) +#define GRF_GPIO2A_DS_2_GPIO2A4_DS_MASK (0x3FU << GRF_GPIO2A_DS_2_GPIO2A4_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO2A_DS_2_GPIO2A5_DS_SHIFT (8U) +#define GRF_GPIO2A_DS_2_GPIO2A5_DS_MASK (0x3FU << GRF_GPIO2A_DS_2_GPIO2A5_DS_SHIFT) /* 0x00003F00 */ +/* GPIO2A_DS_3 */ +#define GRF_GPIO2A_DS_3_OFFSET (0x4024CU) +#define GRF_GPIO2A_DS_3_GPIO2A6_DS_SHIFT (0U) +#define GRF_GPIO2A_DS_3_GPIO2A6_DS_MASK (0x3FU << GRF_GPIO2A_DS_3_GPIO2A6_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO2A_DS_3_GPIO2A7_DS_SHIFT (8U) +#define GRF_GPIO2A_DS_3_GPIO2A7_DS_MASK (0x3FU << GRF_GPIO2A_DS_3_GPIO2A7_DS_SHIFT) /* 0x00003F00 */ +/* GPIO2B_DS_0 */ +#define GRF_GPIO2B_DS_0_OFFSET (0x40250U) +#define GRF_GPIO2B_DS_0_GPIO2B0_DS_SHIFT (0U) +#define GRF_GPIO2B_DS_0_GPIO2B0_DS_MASK (0x3FU << GRF_GPIO2B_DS_0_GPIO2B0_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO2B_DS_0_GPIO2B1_DS_SHIFT (8U) +#define GRF_GPIO2B_DS_0_GPIO2B1_DS_MASK (0x3FU << GRF_GPIO2B_DS_0_GPIO2B1_DS_SHIFT) /* 0x00003F00 */ +/* GPIO2B_DS_1 */ +#define GRF_GPIO2B_DS_1_OFFSET (0x40254U) +#define GRF_GPIO2B_DS_1_GPIO2B2_DS_SHIFT (0U) +#define GRF_GPIO2B_DS_1_GPIO2B2_DS_MASK (0x3FU << GRF_GPIO2B_DS_1_GPIO2B2_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO2B_DS_1_GPIO2B3_DS_SHIFT (8U) +#define GRF_GPIO2B_DS_1_GPIO2B3_DS_MASK (0x3FU << GRF_GPIO2B_DS_1_GPIO2B3_DS_SHIFT) /* 0x00003F00 */ +/* GPIO2B_DS_2 */ +#define GRF_GPIO2B_DS_2_OFFSET (0x40258U) +#define GRF_GPIO2B_DS_2_GPIO2B4_DS_SHIFT (0U) +#define GRF_GPIO2B_DS_2_GPIO2B4_DS_MASK (0x3FU << GRF_GPIO2B_DS_2_GPIO2B4_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO2B_DS_2_GPIO2B5_DS_SHIFT (8U) +#define GRF_GPIO2B_DS_2_GPIO2B5_DS_MASK (0x3FU << GRF_GPIO2B_DS_2_GPIO2B5_DS_SHIFT) /* 0x00003F00 */ +/* GPIO2B_DS_3 */ +#define GRF_GPIO2B_DS_3_OFFSET (0x4025CU) +#define GRF_GPIO2B_DS_3_GPIO2B6_DS_SHIFT (0U) +#define GRF_GPIO2B_DS_3_GPIO2B6_DS_MASK (0x3FU << GRF_GPIO2B_DS_3_GPIO2B6_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO2B_DS_3_GPIO2B7_DS_SHIFT (8U) +#define GRF_GPIO2B_DS_3_GPIO2B7_DS_MASK (0x3FU << GRF_GPIO2B_DS_3_GPIO2B7_DS_SHIFT) /* 0x00003F00 */ +/* GPIO2C_DS_0 */ +#define GRF_GPIO2C_DS_0_OFFSET (0x40260U) +#define GRF_GPIO2C_DS_0_GPIO2C0_DS_SHIFT (0U) +#define GRF_GPIO2C_DS_0_GPIO2C0_DS_MASK (0x3FU << GRF_GPIO2C_DS_0_GPIO2C0_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO2C_DS_0_GPIO2C1_DS_SHIFT (8U) +#define GRF_GPIO2C_DS_0_GPIO2C1_DS_MASK (0x3FU << GRF_GPIO2C_DS_0_GPIO2C1_DS_SHIFT) /* 0x00003F00 */ +/* GPIO2C_DS_1 */ +#define GRF_GPIO2C_DS_1_OFFSET (0x40264U) +#define GRF_GPIO2C_DS_1_GPIO2C2_DS_SHIFT (0U) +#define GRF_GPIO2C_DS_1_GPIO2C2_DS_MASK (0x3FU << GRF_GPIO2C_DS_1_GPIO2C2_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO2C_DS_1_GPIO2C3_DS_SHIFT (8U) +#define GRF_GPIO2C_DS_1_GPIO2C3_DS_MASK (0x3FU << GRF_GPIO2C_DS_1_GPIO2C3_DS_SHIFT) /* 0x00003F00 */ +/* GPIO2C_DS_2 */ +#define GRF_GPIO2C_DS_2_OFFSET (0x40268U) +#define GRF_GPIO2C_DS_2_GPIO2C4_DS_SHIFT (0U) +#define GRF_GPIO2C_DS_2_GPIO2C4_DS_MASK (0x3FU << GRF_GPIO2C_DS_2_GPIO2C4_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO2C_DS_2_GPIO2C5_DS_SHIFT (8U) +#define GRF_GPIO2C_DS_2_GPIO2C5_DS_MASK (0x3FU << GRF_GPIO2C_DS_2_GPIO2C5_DS_SHIFT) /* 0x00003F00 */ +/* GPIO2C_DS_3 */ +#define GRF_GPIO2C_DS_3_OFFSET (0x4026CU) +#define GRF_GPIO2C_DS_3_GPIO2C6_DS_SHIFT (0U) +#define GRF_GPIO2C_DS_3_GPIO2C6_DS_MASK (0x3FU << GRF_GPIO2C_DS_3_GPIO2C6_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO2C_DS_3_GPIO2C7_DS_SHIFT (8U) +#define GRF_GPIO2C_DS_3_GPIO2C7_DS_MASK (0x3FU << GRF_GPIO2C_DS_3_GPIO2C7_DS_SHIFT) /* 0x00003F00 */ +/* GPIO2D_DS_0 */ +#define GRF_GPIO2D_DS_0_OFFSET (0x40270U) +#define GRF_GPIO2D_DS_0_GPIO2D0_DS_SHIFT (0U) +#define GRF_GPIO2D_DS_0_GPIO2D0_DS_MASK (0x3FU << GRF_GPIO2D_DS_0_GPIO2D0_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO2D_DS_0_GPIO2D1_DS_SHIFT (8U) +#define GRF_GPIO2D_DS_0_GPIO2D1_DS_MASK (0x3FU << GRF_GPIO2D_DS_0_GPIO2D1_DS_SHIFT) /* 0x00003F00 */ +/* GPIO2D_DS_1 */ +#define GRF_GPIO2D_DS_1_OFFSET (0x40274U) +#define GRF_GPIO2D_DS_1_GPIO2D2_DS_SHIFT (0U) +#define GRF_GPIO2D_DS_1_GPIO2D2_DS_MASK (0x3FU << GRF_GPIO2D_DS_1_GPIO2D2_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO2D_DS_1_GPIO2D3_DS_SHIFT (8U) +#define GRF_GPIO2D_DS_1_GPIO2D3_DS_MASK (0x3FU << GRF_GPIO2D_DS_1_GPIO2D3_DS_SHIFT) /* 0x00003F00 */ +/* GPIO2D_DS_2 */ +#define GRF_GPIO2D_DS_2_OFFSET (0x40278U) +#define GRF_GPIO2D_DS_2_GPIO2D4_DS_SHIFT (0U) +#define GRF_GPIO2D_DS_2_GPIO2D4_DS_MASK (0x3FU << GRF_GPIO2D_DS_2_GPIO2D4_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO2D_DS_2_GPIO2D5_DS_SHIFT (8U) +#define GRF_GPIO2D_DS_2_GPIO2D5_DS_MASK (0x3FU << GRF_GPIO2D_DS_2_GPIO2D5_DS_SHIFT) /* 0x00003F00 */ +/* GPIO2D_DS_3 */ +#define GRF_GPIO2D_DS_3_OFFSET (0x4027CU) +#define GRF_GPIO2D_DS_3_GPIO2D6_DS_SHIFT (0U) +#define GRF_GPIO2D_DS_3_GPIO2D6_DS_MASK (0x3FU << GRF_GPIO2D_DS_3_GPIO2D6_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO2D_DS_3_GPIO2D7_DS_SHIFT (8U) +#define GRF_GPIO2D_DS_3_GPIO2D7_DS_MASK (0x3FU << GRF_GPIO2D_DS_3_GPIO2D7_DS_SHIFT) /* 0x00003F00 */ +/* GPIO3A_DS_0 */ +#define GRF_GPIO3A_DS_0_OFFSET (0x40280U) +#define GRF_GPIO3A_DS_0_GPIO3A0_DS_SHIFT (0U) +#define GRF_GPIO3A_DS_0_GPIO3A0_DS_MASK (0x3FU << GRF_GPIO3A_DS_0_GPIO3A0_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO3A_DS_0_GPIO3A1_DS_SHIFT (8U) +#define GRF_GPIO3A_DS_0_GPIO3A1_DS_MASK (0x3FU << GRF_GPIO3A_DS_0_GPIO3A1_DS_SHIFT) /* 0x00003F00 */ +/* GPIO3A_DS_1 */ +#define GRF_GPIO3A_DS_1_OFFSET (0x40284U) +#define GRF_GPIO3A_DS_1_GPIO3A2_DS_SHIFT (0U) +#define GRF_GPIO3A_DS_1_GPIO3A2_DS_MASK (0x3FU << GRF_GPIO3A_DS_1_GPIO3A2_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO3A_DS_1_GPIO3A3_DS_SHIFT (8U) +#define GRF_GPIO3A_DS_1_GPIO3A3_DS_MASK (0x3FU << GRF_GPIO3A_DS_1_GPIO3A3_DS_SHIFT) /* 0x00003F00 */ +/* GPIO3A_DS_2 */ +#define GRF_GPIO3A_DS_2_OFFSET (0x40288U) +#define GRF_GPIO3A_DS_2_GPIO3A4_DS_SHIFT (0U) +#define GRF_GPIO3A_DS_2_GPIO3A4_DS_MASK (0x3FU << GRF_GPIO3A_DS_2_GPIO3A4_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO3A_DS_2_GPIO3A5_DS_SHIFT (8U) +#define GRF_GPIO3A_DS_2_GPIO3A5_DS_MASK (0x3FU << GRF_GPIO3A_DS_2_GPIO3A5_DS_SHIFT) /* 0x00003F00 */ +/* GPIO3A_DS_3 */ +#define GRF_GPIO3A_DS_3_OFFSET (0x4028CU) +#define GRF_GPIO3A_DS_3_GPIO3A6_DS_SHIFT (0U) +#define GRF_GPIO3A_DS_3_GPIO3A6_DS_MASK (0x3FU << GRF_GPIO3A_DS_3_GPIO3A6_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO3A_DS_3_GPIO3A7_DS_SHIFT (8U) +#define GRF_GPIO3A_DS_3_GPIO3A7_DS_MASK (0x3FU << GRF_GPIO3A_DS_3_GPIO3A7_DS_SHIFT) /* 0x00003F00 */ +/* GPIO3B_DS_0 */ +#define GRF_GPIO3B_DS_0_OFFSET (0x40290U) +#define GRF_GPIO3B_DS_0_GPIO3B0_DS_SHIFT (0U) +#define GRF_GPIO3B_DS_0_GPIO3B0_DS_MASK (0x3FU << GRF_GPIO3B_DS_0_GPIO3B0_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO3B_DS_0_GPIO3B1_DS_SHIFT (8U) +#define GRF_GPIO3B_DS_0_GPIO3B1_DS_MASK (0x3FU << GRF_GPIO3B_DS_0_GPIO3B1_DS_SHIFT) /* 0x00003F00 */ +/* GPIO3B_DS_1 */ +#define GRF_GPIO3B_DS_1_OFFSET (0x40294U) +#define GRF_GPIO3B_DS_1_GPIO3B2_DS_SHIFT (0U) +#define GRF_GPIO3B_DS_1_GPIO3B2_DS_MASK (0x3FU << GRF_GPIO3B_DS_1_GPIO3B2_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO3B_DS_1_GPIO3B3_DS_SHIFT (8U) +#define GRF_GPIO3B_DS_1_GPIO3B3_DS_MASK (0x3FU << GRF_GPIO3B_DS_1_GPIO3B3_DS_SHIFT) /* 0x00003F00 */ +/* GPIO3B_DS_2 */ +#define GRF_GPIO3B_DS_2_OFFSET (0x40298U) +#define GRF_GPIO3B_DS_2_GPIO3B4_DS_SHIFT (0U) +#define GRF_GPIO3B_DS_2_GPIO3B4_DS_MASK (0x3FU << GRF_GPIO3B_DS_2_GPIO3B4_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO3B_DS_2_GPIO3B5_DS_SHIFT (8U) +#define GRF_GPIO3B_DS_2_GPIO3B5_DS_MASK (0x3FU << GRF_GPIO3B_DS_2_GPIO3B5_DS_SHIFT) /* 0x00003F00 */ +/* GPIO3B_DS_3 */ +#define GRF_GPIO3B_DS_3_OFFSET (0x4029CU) +#define GRF_GPIO3B_DS_3_GPIO3B6_DS_SHIFT (0U) +#define GRF_GPIO3B_DS_3_GPIO3B6_DS_MASK (0x3FU << GRF_GPIO3B_DS_3_GPIO3B6_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO3B_DS_3_GPIO3B7_DS_SHIFT (8U) +#define GRF_GPIO3B_DS_3_GPIO3B7_DS_MASK (0x3FU << GRF_GPIO3B_DS_3_GPIO3B7_DS_SHIFT) /* 0x00003F00 */ +/* GPIO3C_DS_0 */ +#define GRF_GPIO3C_DS_0_OFFSET (0x402A0U) +#define GRF_GPIO3C_DS_0_GPIO3C0_DS_SHIFT (0U) +#define GRF_GPIO3C_DS_0_GPIO3C0_DS_MASK (0x3FU << GRF_GPIO3C_DS_0_GPIO3C0_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO3C_DS_0_GPIO3C1_DS_SHIFT (8U) +#define GRF_GPIO3C_DS_0_GPIO3C1_DS_MASK (0x3FU << GRF_GPIO3C_DS_0_GPIO3C1_DS_SHIFT) /* 0x00003F00 */ +/* GPIO3C_DS_1 */ +#define GRF_GPIO3C_DS_1_OFFSET (0x402A4U) +#define GRF_GPIO3C_DS_1_GPIO3C2_DS_SHIFT (0U) +#define GRF_GPIO3C_DS_1_GPIO3C2_DS_MASK (0x3FU << GRF_GPIO3C_DS_1_GPIO3C2_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO3C_DS_1_GPIO3C3_DS_SHIFT (8U) +#define GRF_GPIO3C_DS_1_GPIO3C3_DS_MASK (0x3FU << GRF_GPIO3C_DS_1_GPIO3C3_DS_SHIFT) /* 0x00003F00 */ +/* GPIO3C_DS_2 */ +#define GRF_GPIO3C_DS_2_OFFSET (0x402A8U) +#define GRF_GPIO3C_DS_2_GPIO3C4_DS_SHIFT (0U) +#define GRF_GPIO3C_DS_2_GPIO3C4_DS_MASK (0x3FU << GRF_GPIO3C_DS_2_GPIO3C4_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO3C_DS_2_GPIO3C5_DS_SHIFT (8U) +#define GRF_GPIO3C_DS_2_GPIO3C5_DS_MASK (0x3FU << GRF_GPIO3C_DS_2_GPIO3C5_DS_SHIFT) /* 0x00003F00 */ +/* GPIO3C_DS_3 */ +#define GRF_GPIO3C_DS_3_OFFSET (0x402ACU) +#define GRF_GPIO3C_DS_3_GPIO3C6_DS_SHIFT (0U) +#define GRF_GPIO3C_DS_3_GPIO3C6_DS_MASK (0x3FU << GRF_GPIO3C_DS_3_GPIO3C6_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO3C_DS_3_GPIO3C7_DS_SHIFT (8U) +#define GRF_GPIO3C_DS_3_GPIO3C7_DS_MASK (0x3FU << GRF_GPIO3C_DS_3_GPIO3C7_DS_SHIFT) /* 0x00003F00 */ +/* GPIO3D_DS_0 */ +#define GRF_GPIO3D_DS_0_OFFSET (0x402B0U) +#define GRF_GPIO3D_DS_0_GPIO3D0_DS_SHIFT (0U) +#define GRF_GPIO3D_DS_0_GPIO3D0_DS_MASK (0x3FU << GRF_GPIO3D_DS_0_GPIO3D0_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO3D_DS_0_GPIO3D1_DS_SHIFT (8U) +#define GRF_GPIO3D_DS_0_GPIO3D1_DS_MASK (0x3FU << GRF_GPIO3D_DS_0_GPIO3D1_DS_SHIFT) /* 0x00003F00 */ +/* GPIO3D_DS_1 */ +#define GRF_GPIO3D_DS_1_OFFSET (0x402B4U) +#define GRF_GPIO3D_DS_1_GPIO3D2_DS_SHIFT (0U) +#define GRF_GPIO3D_DS_1_GPIO3D2_DS_MASK (0x3FU << GRF_GPIO3D_DS_1_GPIO3D2_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO3D_DS_1_GPIO3D3_DS_SHIFT (8U) +#define GRF_GPIO3D_DS_1_GPIO3D3_DS_MASK (0x3FU << GRF_GPIO3D_DS_1_GPIO3D3_DS_SHIFT) /* 0x00003F00 */ +/* GPIO3D_DS_2 */ +#define GRF_GPIO3D_DS_2_OFFSET (0x402B8U) +#define GRF_GPIO3D_DS_2_GPIO3D4_DS_SHIFT (0U) +#define GRF_GPIO3D_DS_2_GPIO3D4_DS_MASK (0x3FU << GRF_GPIO3D_DS_2_GPIO3D4_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO3D_DS_2_GPIO3D5_DS_SHIFT (8U) +#define GRF_GPIO3D_DS_2_GPIO3D5_DS_MASK (0x3FU << GRF_GPIO3D_DS_2_GPIO3D5_DS_SHIFT) /* 0x00003F00 */ +/* GPIO3D_DS_3 */ +#define GRF_GPIO3D_DS_3_OFFSET (0x402BCU) +#define GRF_GPIO3D_DS_3_GPIO3D6_DS_SHIFT (0U) +#define GRF_GPIO3D_DS_3_GPIO3D6_DS_MASK (0x3FU << GRF_GPIO3D_DS_3_GPIO3D6_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO3D_DS_3_GPIO3D7_DS_SHIFT (8U) +#define GRF_GPIO3D_DS_3_GPIO3D7_DS_MASK (0x3FU << GRF_GPIO3D_DS_3_GPIO3D7_DS_SHIFT) /* 0x00003F00 */ +/* GPIO4A_DS_0 */ +#define GRF_GPIO4A_DS_0_OFFSET (0x402C0U) +#define GRF_GPIO4A_DS_0_GPIO4A0_DS_SHIFT (0U) +#define GRF_GPIO4A_DS_0_GPIO4A0_DS_MASK (0x3FU << GRF_GPIO4A_DS_0_GPIO4A0_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO4A_DS_0_GPIO4A1_DS_SHIFT (8U) +#define GRF_GPIO4A_DS_0_GPIO4A1_DS_MASK (0x3FU << GRF_GPIO4A_DS_0_GPIO4A1_DS_SHIFT) /* 0x00003F00 */ +/* GPIO4A_DS_1 */ +#define GRF_GPIO4A_DS_1_OFFSET (0x402C4U) +#define GRF_GPIO4A_DS_1_GPIO4A2_DS_SHIFT (0U) +#define GRF_GPIO4A_DS_1_GPIO4A2_DS_MASK (0x3FU << GRF_GPIO4A_DS_1_GPIO4A2_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO4A_DS_1_GPIO4A3_DS_SHIFT (8U) +#define GRF_GPIO4A_DS_1_GPIO4A3_DS_MASK (0x3FU << GRF_GPIO4A_DS_1_GPIO4A3_DS_SHIFT) /* 0x00003F00 */ +/* GPIO4A_DS_2 */ +#define GRF_GPIO4A_DS_2_OFFSET (0x402C8U) +#define GRF_GPIO4A_DS_2_GPIO4A4_DS_SHIFT (0U) +#define GRF_GPIO4A_DS_2_GPIO4A4_DS_MASK (0x3FU << GRF_GPIO4A_DS_2_GPIO4A4_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO4A_DS_2_GPIO4A5_DS_SHIFT (8U) +#define GRF_GPIO4A_DS_2_GPIO4A5_DS_MASK (0x3FU << GRF_GPIO4A_DS_2_GPIO4A5_DS_SHIFT) /* 0x00003F00 */ +/* GPIO4A_DS_3 */ +#define GRF_GPIO4A_DS_3_OFFSET (0x402CCU) +#define GRF_GPIO4A_DS_3_GPIO4A6_DS_SHIFT (0U) +#define GRF_GPIO4A_DS_3_GPIO4A6_DS_MASK (0x3FU << GRF_GPIO4A_DS_3_GPIO4A6_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO4A_DS_3_GPIO4A7_DS_SHIFT (8U) +#define GRF_GPIO4A_DS_3_GPIO4A7_DS_MASK (0x3FU << GRF_GPIO4A_DS_3_GPIO4A7_DS_SHIFT) /* 0x00003F00 */ +/* GPIO4B_DS_0 */ +#define GRF_GPIO4B_DS_0_OFFSET (0x402D0U) +#define GRF_GPIO4B_DS_0_GPIO4B0_DS_SHIFT (0U) +#define GRF_GPIO4B_DS_0_GPIO4B0_DS_MASK (0x3FU << GRF_GPIO4B_DS_0_GPIO4B0_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO4B_DS_0_GPIO4B1_DS_SHIFT (8U) +#define GRF_GPIO4B_DS_0_GPIO4B1_DS_MASK (0x3FU << GRF_GPIO4B_DS_0_GPIO4B1_DS_SHIFT) /* 0x00003F00 */ +/* GPIO4B_DS_1 */ +#define GRF_GPIO4B_DS_1_OFFSET (0x402D4U) +#define GRF_GPIO4B_DS_1_GPIO4B2_DS_SHIFT (0U) +#define GRF_GPIO4B_DS_1_GPIO4B2_DS_MASK (0x3FU << GRF_GPIO4B_DS_1_GPIO4B2_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO4B_DS_1_GPIO4B3_DS_SHIFT (8U) +#define GRF_GPIO4B_DS_1_GPIO4B3_DS_MASK (0x3FU << GRF_GPIO4B_DS_1_GPIO4B3_DS_SHIFT) /* 0x00003F00 */ +/* GPIO4B_DS_2 */ +#define GRF_GPIO4B_DS_2_OFFSET (0x402D8U) +#define GRF_GPIO4B_DS_2_GPIO4B4_DS_SHIFT (0U) +#define GRF_GPIO4B_DS_2_GPIO4B4_DS_MASK (0x3FU << GRF_GPIO4B_DS_2_GPIO4B4_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO4B_DS_2_GPIO4B5_DS_SHIFT (8U) +#define GRF_GPIO4B_DS_2_GPIO4B5_DS_MASK (0x3FU << GRF_GPIO4B_DS_2_GPIO4B5_DS_SHIFT) /* 0x00003F00 */ +/* GPIO4B_DS_3 */ +#define GRF_GPIO4B_DS_3_OFFSET (0x402DCU) +#define GRF_GPIO4B_DS_3_GPIO4B6_DS_SHIFT (0U) +#define GRF_GPIO4B_DS_3_GPIO4B6_DS_MASK (0x3FU << GRF_GPIO4B_DS_3_GPIO4B6_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO4B_DS_3_GPIO4B7_DS_SHIFT (8U) +#define GRF_GPIO4B_DS_3_GPIO4B7_DS_MASK (0x3FU << GRF_GPIO4B_DS_3_GPIO4B7_DS_SHIFT) /* 0x00003F00 */ +/* GPIO4C_DS_0 */ +#define GRF_GPIO4C_DS_0_OFFSET (0x402E0U) +#define GRF_GPIO4C_DS_0_GPIO4C0_DS_SHIFT (0U) +#define GRF_GPIO4C_DS_0_GPIO4C0_DS_MASK (0x3FU << GRF_GPIO4C_DS_0_GPIO4C0_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO4C_DS_0_GPIO4C1_DS_SHIFT (8U) +#define GRF_GPIO4C_DS_0_GPIO4C1_DS_MASK (0x3FU << GRF_GPIO4C_DS_0_GPIO4C1_DS_SHIFT) /* 0x00003F00 */ +/* GPIO4C_DS_1 */ +#define GRF_GPIO4C_DS_1_OFFSET (0x402E4U) +#define GRF_GPIO4C_DS_1_GPIO4C2_DS_SHIFT (0U) +#define GRF_GPIO4C_DS_1_GPIO4C2_DS_MASK (0x3FU << GRF_GPIO4C_DS_1_GPIO4C2_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO4C_DS_1_GPIO4C3_DS_SHIFT (8U) +#define GRF_GPIO4C_DS_1_GPIO4C3_DS_MASK (0x3FU << GRF_GPIO4C_DS_1_GPIO4C3_DS_SHIFT) /* 0x00003F00 */ +/* GPIO4C_DS_2 */ +#define GRF_GPIO4C_DS_2_OFFSET (0x402E8U) +#define GRF_GPIO4C_DS_2_GPIO4C4_DS_SHIFT (0U) +#define GRF_GPIO4C_DS_2_GPIO4C4_DS_MASK (0x3FU << GRF_GPIO4C_DS_2_GPIO4C4_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO4C_DS_2_GPIO4C5_DS_SHIFT (8U) +#define GRF_GPIO4C_DS_2_GPIO4C5_DS_MASK (0x3FU << GRF_GPIO4C_DS_2_GPIO4C5_DS_SHIFT) /* 0x00003F00 */ +/* GPIO4C_DS_3 */ +#define GRF_GPIO4C_DS_3_OFFSET (0x402ECU) +#define GRF_GPIO4C_DS_3_GPIO4C6_DS_SHIFT (0U) +#define GRF_GPIO4C_DS_3_GPIO4C6_DS_MASK (0x3FU << GRF_GPIO4C_DS_3_GPIO4C6_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO4C_DS_3_GPIO4C7_DS_SHIFT (8U) +#define GRF_GPIO4C_DS_3_GPIO4C7_DS_MASK (0x3FU << GRF_GPIO4C_DS_3_GPIO4C7_DS_SHIFT) /* 0x00003F00 */ +/* GPIO4D_DS_0 */ +#define GRF_GPIO4D_DS_0_OFFSET (0x402F0U) +#define GRF_GPIO4D_DS_0_GPIO4D0_DS_SHIFT (0U) +#define GRF_GPIO4D_DS_0_GPIO4D0_DS_MASK (0x3FU << GRF_GPIO4D_DS_0_GPIO4D0_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO4D_DS_0_GPIO4D1_DS_SHIFT (8U) +#define GRF_GPIO4D_DS_0_GPIO4D1_DS_MASK (0x3FU << GRF_GPIO4D_DS_0_GPIO4D1_DS_SHIFT) /* 0x00003F00 */ +/* GPIO4D_DS_1 */ +#define GRF_GPIO4D_DS_1_OFFSET (0x402F4U) +#define GRF_GPIO4D_DS_1_GPIO4D2_DS_SHIFT (0U) +#define GRF_GPIO4D_DS_1_GPIO4D2_DS_MASK (0x3FU << GRF_GPIO4D_DS_1_GPIO4D2_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO4D_DS_1_GPIO4D3_DS_SHIFT (8U) +#define GRF_GPIO4D_DS_1_GPIO4D3_DS_MASK (0x3FU << GRF_GPIO4D_DS_1_GPIO4D3_DS_SHIFT) /* 0x00003F00 */ +/* GPIO4D_DS_2 */ +#define GRF_GPIO4D_DS_2_OFFSET (0x402F8U) +#define GRF_GPIO4D_DS_2_GPIO4D4_DS_SHIFT (0U) +#define GRF_GPIO4D_DS_2_GPIO4D4_DS_MASK (0x3FU << GRF_GPIO4D_DS_2_GPIO4D4_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO4D_DS_2_GPIO4D5_DS_SHIFT (8U) +#define GRF_GPIO4D_DS_2_GPIO4D5_DS_MASK (0x3FU << GRF_GPIO4D_DS_2_GPIO4D5_DS_SHIFT) /* 0x00003F00 */ +/* GPIO4D_DS_3 */ +#define GRF_GPIO4D_DS_3_OFFSET (0x402FCU) +#define GRF_GPIO4D_DS_3_GPIO4D6_DS_SHIFT (0U) +#define GRF_GPIO4D_DS_3_GPIO4D6_DS_MASK (0x3FU << GRF_GPIO4D_DS_3_GPIO4D6_DS_SHIFT) /* 0x0000003F */ +#define GRF_GPIO4D_DS_3_GPIO4D7_DS_SHIFT (8U) +#define GRF_GPIO4D_DS_3_GPIO4D7_DS_MASK (0x3FU << GRF_GPIO4D_DS_3_GPIO4D7_DS_SHIFT) /* 0x00003F00 */ +/* IOFUNC_SEL0 */ +#define GRF_IOFUNC_SEL0_OFFSET (0x40300U) +#define GRF_IOFUNC_SEL0_CAN0_IOMUX_SEL_SHIFT (0U) +#define GRF_IOFUNC_SEL0_CAN0_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL0_CAN0_IOMUX_SEL_SHIFT) /* 0x00000001 */ +#define GRF_IOFUNC_SEL0_CAN1_IOMUX_SEL_SHIFT (2U) +#define GRF_IOFUNC_SEL0_CAN1_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL0_CAN1_IOMUX_SEL_SHIFT) /* 0x00000004 */ +#define GRF_IOFUNC_SEL0_CAN2_IOMUX_SEL_SHIFT (4U) +#define GRF_IOFUNC_SEL0_CAN2_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL0_CAN2_IOMUX_SEL_SHIFT) /* 0x00000010 */ +#define GRF_IOFUNC_SEL0_EDP_HPD_IOMUX_SEL_SHIFT (6U) +#define GRF_IOFUNC_SEL0_EDP_HPD_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL0_EDP_HPD_IOMUX_SEL_SHIFT) /* 0x00000040 */ +#define GRF_IOFUNC_SEL0_GMAC1_IOMUX_SEL_SHIFT (8U) +#define GRF_IOFUNC_SEL0_GMAC1_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL0_GMAC1_IOMUX_SEL_SHIFT) /* 0x00000100 */ +#define GRF_IOFUNC_SEL0_HDMITX_IOMUX_SEL_SHIFT (10U) +#define GRF_IOFUNC_SEL0_HDMITX_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL0_HDMITX_IOMUX_SEL_SHIFT) /* 0x00000400 */ +#define GRF_IOFUNC_SEL0_I2C2_IOMUX_SEL_SHIFT (14U) +#define GRF_IOFUNC_SEL0_I2C2_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL0_I2C2_IOMUX_SEL_SHIFT) /* 0x00004000 */ +/* IOFUNC_SEL1 */ +#define GRF_IOFUNC_SEL1_OFFSET (0x40304U) +#define GRF_IOFUNC_SEL1_I2C3_IOMUX_SEL_SHIFT (0U) +#define GRF_IOFUNC_SEL1_I2C3_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL1_I2C3_IOMUX_SEL_SHIFT) /* 0x00000001 */ +#define GRF_IOFUNC_SEL1_I2C4_IOMUX_SEL_SHIFT (2U) +#define GRF_IOFUNC_SEL1_I2C4_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL1_I2C4_IOMUX_SEL_SHIFT) /* 0x00000004 */ +#define GRF_IOFUNC_SEL1_I2C5_IOMUX_SEL_SHIFT (4U) +#define GRF_IOFUNC_SEL1_I2C5_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL1_I2C5_IOMUX_SEL_SHIFT) /* 0x00000010 */ +#define GRF_IOFUNC_SEL1_PWM8_IOMUX_SEL_SHIFT (14U) +#define GRF_IOFUNC_SEL1_PWM8_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL1_PWM8_IOMUX_SEL_SHIFT) /* 0x00004000 */ +/* IOFUNC_SEL2 */ +#define GRF_IOFUNC_SEL2_OFFSET (0x40308U) +#define GRF_IOFUNC_SEL2_PWM9_IOMUX_SEL_SHIFT (0U) +#define GRF_IOFUNC_SEL2_PWM9_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL2_PWM9_IOMUX_SEL_SHIFT) /* 0x00000001 */ +#define GRF_IOFUNC_SEL2_PWM10_IOMUX_SEL_SHIFT (2U) +#define GRF_IOFUNC_SEL2_PWM10_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL2_PWM10_IOMUX_SEL_SHIFT) /* 0x00000004 */ +#define GRF_IOFUNC_SEL2_PWM11_IOMUX_SEL_SHIFT (4U) +#define GRF_IOFUNC_SEL2_PWM11_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL2_PWM11_IOMUX_SEL_SHIFT) /* 0x00000010 */ +#define GRF_IOFUNC_SEL2_PWM12_IOMUX_SEL_SHIFT (6U) +#define GRF_IOFUNC_SEL2_PWM12_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL2_PWM12_IOMUX_SEL_SHIFT) /* 0x00000040 */ +#define GRF_IOFUNC_SEL2_PWM13_IOMUX_SEL_SHIFT (8U) +#define GRF_IOFUNC_SEL2_PWM13_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL2_PWM13_IOMUX_SEL_SHIFT) /* 0x00000100 */ +#define GRF_IOFUNC_SEL2_PWM14_IOMUX_SEL_SHIFT (10U) +#define GRF_IOFUNC_SEL2_PWM14_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL2_PWM14_IOMUX_SEL_SHIFT) /* 0x00000400 */ +#define GRF_IOFUNC_SEL2_PWM15_IOMUX_SEL_SHIFT (12U) +#define GRF_IOFUNC_SEL2_PWM15_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL2_PWM15_IOMUX_SEL_SHIFT) /* 0x00001000 */ +#define GRF_IOFUNC_SEL2_SDMMC2_IOMUX_SEL_SHIFT (14U) +#define GRF_IOFUNC_SEL2_SDMMC2_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL2_SDMMC2_IOMUX_SEL_SHIFT) /* 0x00004000 */ +/* IOFUNC_SEL3 */ +#define GRF_IOFUNC_SEL3_OFFSET (0x4030CU) +#define GRF_IOFUNC_SEL3_SPI0_IOMUX_SEL_SHIFT (0U) +#define GRF_IOFUNC_SEL3_SPI0_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL3_SPI0_IOMUX_SEL_SHIFT) /* 0x00000001 */ +#define GRF_IOFUNC_SEL3_SPI1_IOMUX_SEL_SHIFT (2U) +#define GRF_IOFUNC_SEL3_SPI1_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL3_SPI1_IOMUX_SEL_SHIFT) /* 0x00000004 */ +#define GRF_IOFUNC_SEL3_SPI2_IOMUX_SEL_SHIFT (4U) +#define GRF_IOFUNC_SEL3_SPI2_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL3_SPI2_IOMUX_SEL_SHIFT) /* 0x00000010 */ +#define GRF_IOFUNC_SEL3_SPI3_IOMUX_SEL_SHIFT (6U) +#define GRF_IOFUNC_SEL3_SPI3_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL3_SPI3_IOMUX_SEL_SHIFT) /* 0x00000040 */ +#define GRF_IOFUNC_SEL3_UART1_IOMUX_SEL_SHIFT (8U) +#define GRF_IOFUNC_SEL3_UART1_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL3_UART1_IOMUX_SEL_SHIFT) /* 0x00000100 */ +#define GRF_IOFUNC_SEL3_UART2_IOMUX_SEL_SHIFT (10U) +#define GRF_IOFUNC_SEL3_UART2_IOMUX_SEL_MASK (0x3U << GRF_IOFUNC_SEL3_UART2_IOMUX_SEL_SHIFT) /* 0x00000C00 */ +#define GRF_IOFUNC_SEL3_UART3_IOMUX_SEL_SHIFT (12U) +#define GRF_IOFUNC_SEL3_UART3_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL3_UART3_IOMUX_SEL_SHIFT) /* 0x00001000 */ +#define GRF_IOFUNC_SEL3_UART4_IOMUX_SEL_SHIFT (14U) +#define GRF_IOFUNC_SEL3_UART4_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL3_UART4_IOMUX_SEL_SHIFT) /* 0x00004000 */ +/* IOFUNC_SEL4 */ +#define GRF_IOFUNC_SEL4_OFFSET (0x40310U) +#define GRF_IOFUNC_SEL4_UART5_IOMUX_SEL_SHIFT (0U) +#define GRF_IOFUNC_SEL4_UART5_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL4_UART5_IOMUX_SEL_SHIFT) /* 0x00000001 */ +#define GRF_IOFUNC_SEL4_UART6_IOMUX_SEL_SHIFT (2U) +#define GRF_IOFUNC_SEL4_UART6_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL4_UART6_IOMUX_SEL_SHIFT) /* 0x00000004 */ +#define GRF_IOFUNC_SEL4_UART7_IOMUX_SEL_SHIFT (4U) +#define GRF_IOFUNC_SEL4_UART7_IOMUX_SEL_MASK (0x3U << GRF_IOFUNC_SEL4_UART7_IOMUX_SEL_SHIFT) /* 0x00000030 */ +#define GRF_IOFUNC_SEL4_UART8_IOMUX_SEL_SHIFT (6U) +#define GRF_IOFUNC_SEL4_UART8_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL4_UART8_IOMUX_SEL_SHIFT) /* 0x00000040 */ +#define GRF_IOFUNC_SEL4_UART9_IOMUX_SEL_SHIFT (8U) +#define GRF_IOFUNC_SEL4_UART9_IOMUX_SEL_MASK (0x3U << GRF_IOFUNC_SEL4_UART9_IOMUX_SEL_SHIFT) /* 0x00000300 */ +#define GRF_IOFUNC_SEL4_I2S1_IOMUX_SEL_SHIFT (10U) +#define GRF_IOFUNC_SEL4_I2S1_IOMUX_SEL_MASK (0x3U << GRF_IOFUNC_SEL4_I2S1_IOMUX_SEL_SHIFT) /* 0x00000C00 */ +#define GRF_IOFUNC_SEL4_I2S2_IOMUX_SEL_SHIFT (12U) +#define GRF_IOFUNC_SEL4_I2S2_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL4_I2S2_IOMUX_SEL_SHIFT) /* 0x00001000 */ +#define GRF_IOFUNC_SEL4_I2S3_IOMUX_SEL_SHIFT (14U) +#define GRF_IOFUNC_SEL4_I2S3_IOMUX_SEL_MASK (0x1U << GRF_IOFUNC_SEL4_I2S3_IOMUX_SEL_SHIFT) /* 0x00004000 */ +/* IOFUNC_SEL5 */ +#define GRF_IOFUNC_SEL5_OFFSET (0x40314U) +#define GRF_IOFUNC_SEL5_PDM_IOMUX_SEL_SHIFT (0U) +#define GRF_IOFUNC_SEL5_PDM_IOMUX_SEL_MASK (0x3U << GRF_IOFUNC_SEL5_PDM_IOMUX_SEL_SHIFT) /* 0x00000003 */ +#define GRF_IOFUNC_SEL5_PCIE20_IOMUX_SEL_SHIFT (2U) +#define GRF_IOFUNC_SEL5_PCIE20_IOMUX_SEL_MASK (0x3U << GRF_IOFUNC_SEL5_PCIE20_IOMUX_SEL_SHIFT) /* 0x0000000C */ +#define GRF_IOFUNC_SEL5_PCIE30X1_IOMUX_SEL_SHIFT (4U) +#define GRF_IOFUNC_SEL5_PCIE30X1_IOMUX_SEL_MASK (0x3U << GRF_IOFUNC_SEL5_PCIE30X1_IOMUX_SEL_SHIFT) /* 0x00000030 */ +#define GRF_IOFUNC_SEL5_PCIE30X2_IOMUX_SEL_SHIFT (6U) +#define GRF_IOFUNC_SEL5_PCIE30X2_IOMUX_SEL_MASK (0x3U << GRF_IOFUNC_SEL5_PCIE30X2_IOMUX_SEL_SHIFT) /* 0x000000C0 */ +#define GRF_IOFUNC_SEL5_SATA_CP_POD_SEL_SHIFT (8U) +#define GRF_IOFUNC_SEL5_SATA_CP_POD_SEL_MASK (0x3U << GRF_IOFUNC_SEL5_SATA_CP_POD_SEL_SHIFT) /* 0x00000300 */ +#define GRF_IOFUNC_SEL5_SATA0_MP_SWITCH_SEL_SHIFT (10U) +#define GRF_IOFUNC_SEL5_SATA0_MP_SWITCH_SEL_MASK (0x1U << GRF_IOFUNC_SEL5_SATA0_MP_SWITCH_SEL_SHIFT) /* 0x00000400 */ +#define GRF_IOFUNC_SEL5_SATA1_MP_SWITCH_SEL_SHIFT (11U) +#define GRF_IOFUNC_SEL5_SATA1_MP_SWITCH_SEL_MASK (0x1U << GRF_IOFUNC_SEL5_SATA1_MP_SWITCH_SEL_SHIFT) /* 0x00000800 */ +#define GRF_IOFUNC_SEL5_SATA2_MP_SWITCH_SEL_SHIFT (12U) +#define GRF_IOFUNC_SEL5_SATA2_MP_SWITCH_SEL_MASK (0x1U << GRF_IOFUNC_SEL5_SATA2_MP_SWITCH_SEL_SHIFT) /* 0x00001000 */ +#define GRF_IOFUNC_SEL5_SATA0_CP_DEL_SEL_SHIFT (13U) +#define GRF_IOFUNC_SEL5_SATA0_CP_DEL_SEL_MASK (0x1U << GRF_IOFUNC_SEL5_SATA0_CP_DEL_SEL_SHIFT) /* 0x00002000 */ +#define GRF_IOFUNC_SEL5_SATA1_CP_DEL_SEL_SHIFT (14U) +#define GRF_IOFUNC_SEL5_SATA1_CP_DEL_SEL_MASK (0x1U << GRF_IOFUNC_SEL5_SATA1_CP_DEL_SEL_SHIFT) /* 0x00004000 */ +#define GRF_IOFUNC_SEL5_SATA2_CP_DEL_SEL_SHIFT (15U) +#define GRF_IOFUNC_SEL5_SATA2_CP_DEL_SEL_MASK (0x1U << GRF_IOFUNC_SEL5_SATA2_CP_DEL_SEL_SHIFT) /* 0x00008000 */ +/* VI_CON0 */ +#define GRF_VI_CON0_OFFSET (0x40340U) +#define GRF_VI_CON0_CSIPHY_FORCERXMODE_0_SHIFT (0U) +#define GRF_VI_CON0_CSIPHY_FORCERXMODE_0_MASK (0x1U << GRF_VI_CON0_CSIPHY_FORCERXMODE_0_SHIFT) /* 0x00000001 */ +#define GRF_VI_CON0_CSIPHY_FORCERXMODE_1_SHIFT (1U) +#define GRF_VI_CON0_CSIPHY_FORCERXMODE_1_MASK (0x1U << GRF_VI_CON0_CSIPHY_FORCERXMODE_1_SHIFT) /* 0x00000002 */ +#define GRF_VI_CON0_CSIPHY_FORCERXMODE_2_SHIFT (2U) +#define GRF_VI_CON0_CSIPHY_FORCERXMODE_2_MASK (0x1U << GRF_VI_CON0_CSIPHY_FORCERXMODE_2_SHIFT) /* 0x00000004 */ +#define GRF_VI_CON0_CSIPHY_FORCERXMODE_3_SHIFT (3U) +#define GRF_VI_CON0_CSIPHY_FORCERXMODE_3_MASK (0x1U << GRF_VI_CON0_CSIPHY_FORCERXMODE_3_SHIFT) /* 0x00000008 */ +#define GRF_VI_CON0_CSIPHY_DATALANE_EN_0_SHIFT (4U) +#define GRF_VI_CON0_CSIPHY_DATALANE_EN_0_MASK (0x1U << GRF_VI_CON0_CSIPHY_DATALANE_EN_0_SHIFT) /* 0x00000010 */ +#define GRF_VI_CON0_CSIPHY_DATALANE_EN_1_SHIFT (5U) +#define GRF_VI_CON0_CSIPHY_DATALANE_EN_1_MASK (0x1U << GRF_VI_CON0_CSIPHY_DATALANE_EN_1_SHIFT) /* 0x00000020 */ +#define GRF_VI_CON0_CSIPHY_DATALANE_EN_2_SHIFT (6U) +#define GRF_VI_CON0_CSIPHY_DATALANE_EN_2_MASK (0x1U << GRF_VI_CON0_CSIPHY_DATALANE_EN_2_SHIFT) /* 0x00000040 */ +#define GRF_VI_CON0_CSIPHY_DATALANE_EN_3_SHIFT (7U) +#define GRF_VI_CON0_CSIPHY_DATALANE_EN_3_MASK (0x1U << GRF_VI_CON0_CSIPHY_DATALANE_EN_3_SHIFT) /* 0x00000080 */ +#define GRF_VI_CON0_CSIPHY_CLKLANE0_EN_SHIFT (8U) +#define GRF_VI_CON0_CSIPHY_CLKLANE0_EN_MASK (0x1U << GRF_VI_CON0_CSIPHY_CLKLANE0_EN_SHIFT) /* 0x00000100 */ +#define GRF_VI_CON0_CSIPHY_CLK0_INV_SELECTION_SHIFT (9U) +#define GRF_VI_CON0_CSIPHY_CLK0_INV_SELECTION_MASK (0x1U << GRF_VI_CON0_CSIPHY_CLK0_INV_SELECTION_SHIFT) /* 0x00000200 */ +#define GRF_VI_CON0_CSIPHY_CLKLANE1_EN_SHIFT (10U) +#define GRF_VI_CON0_CSIPHY_CLKLANE1_EN_MASK (0x1U << GRF_VI_CON0_CSIPHY_CLKLANE1_EN_SHIFT) /* 0x00000400 */ +#define GRF_VI_CON0_CSIPHY_CLK1_INV_SELECTION_SHIFT (11U) +#define GRF_VI_CON0_CSIPHY_CLK1_INV_SELECTION_MASK (0x1U << GRF_VI_CON0_CSIPHY_CLK1_INV_SELECTION_SHIFT) /* 0x00000800 */ +#define GRF_VI_CON0_DVP_CLK_INV_SEL_SHIFT (12U) +#define GRF_VI_CON0_DVP_CLK_INV_SEL_MASK (0x1U << GRF_VI_CON0_DVP_CLK_INV_SEL_SHIFT) /* 0x00001000 */ +/* VI_CON1 */ +#define GRF_VI_CON1_OFFSET (0x40344U) +#define GRF_VI_CON1_CIF_CLK_DELAYNUM_SHIFT (0U) +#define GRF_VI_CON1_CIF_CLK_DELAYNUM_MASK (0x7FU << GRF_VI_CON1_CIF_CLK_DELAYNUM_SHIFT) /* 0x0000007F */ +#define GRF_VI_CON1_CSIPHY_MODE_SEL_SHIFT (7U) +#define GRF_VI_CON1_CSIPHY_MODE_SEL_MASK (0x1U << GRF_VI_CON1_CSIPHY_MODE_SEL_SHIFT) /* 0x00000080 */ +#define GRF_VI_CON1_CIF_DATAPATH_SHIFT (9U) +#define GRF_VI_CON1_CIF_DATAPATH_MASK (0x1U << GRF_VI_CON1_CIF_DATAPATH_SHIFT) /* 0x00000200 */ +#define GRF_VI_CON1_VICAP_CSIPHY_SEL_SHIFT (11U) +#define GRF_VI_CON1_VICAP_CSIPHY_SEL_MASK (0x1U << GRF_VI_CON1_VICAP_CSIPHY_SEL_SHIFT) /* 0x00000800 */ +#define GRF_VI_CON1_ISP_CSIPHY_SEL_SHIFT (12U) +#define GRF_VI_CON1_ISP_CSIPHY_SEL_MASK (0x1U << GRF_VI_CON1_ISP_CSIPHY_SEL_SHIFT) /* 0x00001000 */ +#define GRF_VI_CON1_ISP_SHUTTER_TRIG_SHIFT (13U) +#define GRF_VI_CON1_ISP_SHUTTER_TRIG_MASK (0x1U << GRF_VI_CON1_ISP_SHUTTER_TRIG_SHIFT) /* 0x00002000 */ +#define GRF_VI_CON1_ISP_WIDTH_SHIFT (14U) +#define GRF_VI_CON1_ISP_WIDTH_MASK (0x3U << GRF_VI_CON1_ISP_WIDTH_SHIFT) /* 0x0000C000 */ +/* VI_STATUS0 */ +#define GRF_VI_STATUS0_OFFSET (0x40348U) +#define GRF_VI_STATUS0_CSIPHY_ULPSACTIVENOT_0_SHIFT (0U) +#define GRF_VI_STATUS0_CSIPHY_ULPSACTIVENOT_0_MASK (0x1U << GRF_VI_STATUS0_CSIPHY_ULPSACTIVENOT_0_SHIFT) /* 0x00000001 */ +#define GRF_VI_STATUS0_CSIPHY_ULPSACTIVENOT_1_SHIFT (1U) +#define GRF_VI_STATUS0_CSIPHY_ULPSACTIVENOT_1_MASK (0x1U << GRF_VI_STATUS0_CSIPHY_ULPSACTIVENOT_1_SHIFT) /* 0x00000002 */ +#define GRF_VI_STATUS0_CSIPHY_ULPSACTIVENOT_2_SHIFT (2U) +#define GRF_VI_STATUS0_CSIPHY_ULPSACTIVENOT_2_MASK (0x1U << GRF_VI_STATUS0_CSIPHY_ULPSACTIVENOT_2_SHIFT) /* 0x00000004 */ +#define GRF_VI_STATUS0_CSIPHY_ULPSACTIVENOT_3_SHIFT (3U) +#define GRF_VI_STATUS0_CSIPHY_ULPSACTIVENOT_3_MASK (0x1U << GRF_VI_STATUS0_CSIPHY_ULPSACTIVENOT_3_SHIFT) /* 0x00000008 */ +#define GRF_VI_STATUS0_CSIPHY_DIRECTION_SHIFT (4U) +#define GRF_VI_STATUS0_CSIPHY_DIRECTION_MASK (0x1U << GRF_VI_STATUS0_CSIPHY_DIRECTION_SHIFT) /* 0x00000010 */ +#define GRF_VI_STATUS0_CSIPHY_RXSKEWCALHS_0_SHIFT (5U) +#define GRF_VI_STATUS0_CSIPHY_RXSKEWCALHS_0_MASK (0x1U << GRF_VI_STATUS0_CSIPHY_RXSKEWCALHS_0_SHIFT) /* 0x00000020 */ +#define GRF_VI_STATUS0_CSIPHY_RXSKEWCALHS_1_SHIFT (6U) +#define GRF_VI_STATUS0_CSIPHY_RXSKEWCALHS_1_MASK (0x1U << GRF_VI_STATUS0_CSIPHY_RXSKEWCALHS_1_SHIFT) /* 0x00000040 */ +#define GRF_VI_STATUS0_CSIPHY_RXSKEWCALHS_2_SHIFT (7U) +#define GRF_VI_STATUS0_CSIPHY_RXSKEWCALHS_2_MASK (0x1U << GRF_VI_STATUS0_CSIPHY_RXSKEWCALHS_2_SHIFT) /* 0x00000080 */ +#define GRF_VI_STATUS0_CSIPHY_RXSKEWCALHS_3_SHIFT (8U) +#define GRF_VI_STATUS0_CSIPHY_RXSKEWCALHS_3_MASK (0x1U << GRF_VI_STATUS0_CSIPHY_RXSKEWCALHS_3_SHIFT) /* 0x00000100 */ +#define GRF_VI_STATUS0_CSIPHY_ERRCONTENTIONLP0_0_SHIFT (9U) +#define GRF_VI_STATUS0_CSIPHY_ERRCONTENTIONLP0_0_MASK (0x1U << GRF_VI_STATUS0_CSIPHY_ERRCONTENTIONLP0_0_SHIFT) /* 0x00000200 */ +#define GRF_VI_STATUS0_CSIPHY_ERRCONTENTIONLP1_0_SHIFT (10U) +#define GRF_VI_STATUS0_CSIPHY_ERRCONTENTIONLP1_0_MASK (0x1U << GRF_VI_STATUS0_CSIPHY_ERRCONTENTIONLP1_0_SHIFT) /* 0x00000400 */ +/* VO_CON0 */ +#define GRF_VO_CON0_OFFSET (0x40360U) +#define GRF_VO_CON0_DSI0_DPISHUTDN_SHIFT (0U) +#define GRF_VO_CON0_DSI0_DPISHUTDN_MASK (0x1U << GRF_VO_CON0_DSI0_DPISHUTDN_SHIFT) /* 0x00000001 */ +#define GRF_VO_CON0_DSI0_DPICOLORM_SHIFT (1U) +#define GRF_VO_CON0_DSI0_DPICOLORM_MASK (0x1U << GRF_VO_CON0_DSI0_DPICOLORM_SHIFT) /* 0x00000002 */ +#define GRF_VO_CON0_DSI0_DPIUPDATECFG_SHIFT (2U) +#define GRF_VO_CON0_DSI0_DPIUPDATECFG_MASK (0x1U << GRF_VO_CON0_DSI0_DPIUPDATECFG_SHIFT) /* 0x00000004 */ +#define GRF_VO_CON0_LVDSFORMAT_LVDS0_MSBSEL_SHIFT (3U) +#define GRF_VO_CON0_LVDSFORMAT_LVDS0_MSBSEL_MASK (0x1U << GRF_VO_CON0_LVDSFORMAT_LVDS0_MSBSEL_SHIFT) /* 0x00000008 */ +#define GRF_VO_CON0_LVDSFORMAT_LVDS0_SELECT_SHIFT (4U) +#define GRF_VO_CON0_LVDSFORMAT_LVDS0_SELECT_MASK (0x3U << GRF_VO_CON0_LVDSFORMAT_LVDS0_SELECT_SHIFT) /* 0x00000030 */ +#define GRF_VO_CON0_DSI1_DPISHUTDN_SHIFT (8U) +#define GRF_VO_CON0_DSI1_DPISHUTDN_MASK (0x1U << GRF_VO_CON0_DSI1_DPISHUTDN_SHIFT) /* 0x00000100 */ +#define GRF_VO_CON0_DSI1_DPICOLORM_SHIFT (9U) +#define GRF_VO_CON0_DSI1_DPICOLORM_MASK (0x1U << GRF_VO_CON0_DSI1_DPICOLORM_SHIFT) /* 0x00000200 */ +#define GRF_VO_CON0_DSI1_DPIUPDATECFG_SHIFT (10U) +#define GRF_VO_CON0_DSI1_DPIUPDATECFG_MASK (0x1U << GRF_VO_CON0_DSI1_DPIUPDATECFG_SHIFT) /* 0x00000400 */ +#define GRF_VO_CON0_HDMIPHY_I2C_JTAGZ_SHIFT (15U) +#define GRF_VO_CON0_HDMIPHY_I2C_JTAGZ_MASK (0x1U << GRF_VO_CON0_HDMIPHY_I2C_JTAGZ_SHIFT) /* 0x00008000 */ +/* VO_CON1 */ +#define GRF_VO_CON1_OFFSET (0x40364U) +#define GRF_VO_CON1_EBC_CLK_INV_SEL_SHIFT (0U) +#define GRF_VO_CON1_EBC_CLK_INV_SEL_MASK (0x1U << GRF_VO_CON1_EBC_CLK_INV_SEL_SHIFT) /* 0x00000001 */ +#define GRF_VO_CON1_BT656_CLK_INV_SEL_SHIFT (1U) +#define GRF_VO_CON1_BT656_CLK_INV_SEL_MASK (0x1U << GRF_VO_CON1_BT656_CLK_INV_SEL_SHIFT) /* 0x00000002 */ +#define GRF_VO_CON1_BT1120_CLK_INV_SEL_SHIFT (2U) +#define GRF_VO_CON1_BT1120_CLK_INV_SEL_MASK (0x1U << GRF_VO_CON1_BT1120_CLK_INV_SEL_SHIFT) /* 0x00000004 */ +#define GRF_VO_CON1_RGB_DCLK_INV_SEL_SHIFT (3U) +#define GRF_VO_CON1_RGB_DCLK_INV_SEL_MASK (0x1U << GRF_VO_CON1_RGB_DCLK_INV_SEL_SHIFT) /* 0x00000008 */ +#define GRF_VO_CON1_BT656_BYPASS_SHIFT (4U) +#define GRF_VO_CON1_BT656_BYPASS_MASK (0x1U << GRF_VO_CON1_BT656_BYPASS_SHIFT) /* 0x00000010 */ +#define GRF_VO_CON1_BT1120_BYPASS_SHIFT (5U) +#define GRF_VO_CON1_BT1120_BYPASS_MASK (0x1U << GRF_VO_CON1_BT1120_BYPASS_SHIFT) /* 0x00000020 */ +#define GRF_VO_CON1_RGB_BYPASS_SHIFT (6U) +#define GRF_VO_CON1_RGB_BYPASS_MASK (0x1U << GRF_VO_CON1_RGB_BYPASS_SHIFT) /* 0x00000040 */ +#define GRF_VO_CON1_HDMI_CECIN_MSK_SHIFT (13U) +#define GRF_VO_CON1_HDMI_CECIN_MSK_MASK (0x1U << GRF_VO_CON1_HDMI_CECIN_MSK_SHIFT) /* 0x00002000 */ +#define GRF_VO_CON1_HDMI_SCLIN_MSK_SHIFT (14U) +#define GRF_VO_CON1_HDMI_SCLIN_MSK_MASK (0x1U << GRF_VO_CON1_HDMI_SCLIN_MSK_SHIFT) /* 0x00004000 */ +#define GRF_VO_CON1_HDMI_SDAIN_MSK_SHIFT (15U) +#define GRF_VO_CON1_HDMI_SDAIN_MSK_MASK (0x1U << GRF_VO_CON1_HDMI_SDAIN_MSK_SHIFT) /* 0x00008000 */ +/* VO_CON2 */ +#define GRF_VO_CON2_OFFSET (0x40368U) +#define GRF_VO_CON2_DSIPHY0_FORCERXMODE_SHIFT (0U) +#define GRF_VO_CON2_DSIPHY0_FORCERXMODE_MASK (0x1U << GRF_VO_CON2_DSIPHY0_FORCERXMODE_SHIFT) /* 0x00000001 */ +#define GRF_VO_CON2_DSIPHY0_LVDS_MODE_SHIFT (1U) +#define GRF_VO_CON2_DSIPHY0_LVDS_MODE_MASK (0x1U << GRF_VO_CON2_DSIPHY0_LVDS_MODE_SHIFT) /* 0x00000002 */ +#define GRF_VO_CON2_DSIPHY0_LANE0_TURNDISABLE_SHIFT (2U) +#define GRF_VO_CON2_DSIPHY0_LANE0_TURNDISABLE_MASK (0x1U << GRF_VO_CON2_DSIPHY0_LANE0_TURNDISABLE_SHIFT) /* 0x00000004 */ +#define GRF_VO_CON2_DSIPHY0_LANE0_FRCTXSTPM_SHIFT (4U) +#define GRF_VO_CON2_DSIPHY0_LANE0_FRCTXSTPM_MASK (0x1U << GRF_VO_CON2_DSIPHY0_LANE0_FRCTXSTPM_SHIFT) /* 0x00000010 */ +#define GRF_VO_CON2_DSIPHY0_LANE1_FRCTXSTPM_SHIFT (5U) +#define GRF_VO_CON2_DSIPHY0_LANE1_FRCTXSTPM_MASK (0x1U << GRF_VO_CON2_DSIPHY0_LANE1_FRCTXSTPM_SHIFT) /* 0x00000020 */ +#define GRF_VO_CON2_DSIPHY0_LANE2_FRCTXSTPM_SHIFT (6U) +#define GRF_VO_CON2_DSIPHY0_LANE2_FRCTXSTPM_MASK (0x1U << GRF_VO_CON2_DSIPHY0_LANE2_FRCTXSTPM_SHIFT) /* 0x00000040 */ +#define GRF_VO_CON2_DSIPHY0_LANE3_FRCTXSTPM_SHIFT (7U) +#define GRF_VO_CON2_DSIPHY0_LANE3_FRCTXSTPM_MASK (0x1U << GRF_VO_CON2_DSIPHY0_LANE3_FRCTXSTPM_SHIFT) /* 0x00000080 */ +#define GRF_VO_CON2_LVDS0_DCLK_DIV2_SEL_SHIFT (8U) +#define GRF_VO_CON2_LVDS0_DCLK_DIV2_SEL_MASK (0x1U << GRF_VO_CON2_LVDS0_DCLK_DIV2_SEL_SHIFT) /* 0x00000100 */ +#define GRF_VO_CON2_LVDS0_DCLK_INV_SEL_SHIFT (9U) +#define GRF_VO_CON2_LVDS0_DCLK_INV_SEL_MASK (0x1U << GRF_VO_CON2_LVDS0_DCLK_INV_SEL_SHIFT) /* 0x00000200 */ +#define GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_CK_SHIFT (11U) +#define GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_CK_MASK (0x1U << GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_CK_SHIFT) /* 0x00000800 */ +#define GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_0_SHIFT (12U) +#define GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_0_MASK (0x1U << GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_0_SHIFT) /* 0x00001000 */ +#define GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_1_SHIFT (13U) +#define GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_1_MASK (0x1U << GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_1_SHIFT) /* 0x00002000 */ +#define GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_2_SHIFT (14U) +#define GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_2_MASK (0x1U << GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_2_SHIFT) /* 0x00004000 */ +#define GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_3_SHIFT (15U) +#define GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_3_MASK (0x1U << GRF_VO_CON2_DSIPHY0_TXSKEWCALHS_3_SHIFT) /* 0x00008000 */ +/* MAC0_CON0 */ +#define GRF_MAC0_CON0_OFFSET (0x40380U) +#define GRF_MAC0_CON0_GMAC0_CLK_TX_DL_CFG_SHIFT (0U) +#define GRF_MAC0_CON0_GMAC0_CLK_TX_DL_CFG_MASK (0xFFU << GRF_MAC0_CON0_GMAC0_CLK_TX_DL_CFG_SHIFT) /* 0x000000FF */ +#define GRF_MAC0_CON0_GMAC0_CLK_RX_DL_CFG_SHIFT (8U) +#define GRF_MAC0_CON0_GMAC0_CLK_RX_DL_CFG_MASK (0xFFU << GRF_MAC0_CON0_GMAC0_CLK_RX_DL_CFG_SHIFT) /* 0x0000FF00 */ +/* MAC0_CON1 */ +#define GRF_MAC0_CON1_OFFSET (0x40384U) +#define GRF_MAC0_CON1_GMAC0_TXCLK_DLY_ENA_SHIFT (0U) +#define GRF_MAC0_CON1_GMAC0_TXCLK_DLY_ENA_MASK (0x1U << GRF_MAC0_CON1_GMAC0_TXCLK_DLY_ENA_SHIFT) /* 0x00000001 */ +#define GRF_MAC0_CON1_GMAC0_RXCLK_DLY_ENA_SHIFT (1U) +#define GRF_MAC0_CON1_GMAC0_RXCLK_DLY_ENA_MASK (0x1U << GRF_MAC0_CON1_GMAC0_RXCLK_DLY_ENA_SHIFT) /* 0x00000002 */ +#define GRF_MAC0_CON1_GMAC0_MAC_SPEED_SHIFT (2U) +#define GRF_MAC0_CON1_GMAC0_MAC_SPEED_MASK (0x1U << GRF_MAC0_CON1_GMAC0_MAC_SPEED_SHIFT) /* 0x00000004 */ +#define GRF_MAC0_CON1_GMAC0_FLOWCTRL_SHIFT (3U) +#define GRF_MAC0_CON1_GMAC0_FLOWCTRL_MASK (0x1U << GRF_MAC0_CON1_GMAC0_FLOWCTRL_SHIFT) /* 0x00000008 */ +#define GRF_MAC0_CON1_GMAC0_PHY_INTF_SEL_SHIFT (4U) +#define GRF_MAC0_CON1_GMAC0_PHY_INTF_SEL_MASK (0x7U << GRF_MAC0_CON1_GMAC0_PHY_INTF_SEL_SHIFT) /* 0x00000070 */ +#define GRF_MAC0_CON1_GMAC0_QSGMII_MODE_SHIFT (7U) +#define GRF_MAC0_CON1_GMAC0_QSGMII_MODE_MASK (0x1U << GRF_MAC0_CON1_GMAC0_QSGMII_MODE_SHIFT) /* 0x00000080 */ +/* MAC1_CON0 */ +#define GRF_MAC1_CON0_OFFSET (0x40388U) +#define GRF_MAC1_CON0_GMAC1_CLK_TX_DL_CFG_SHIFT (0U) +#define GRF_MAC1_CON0_GMAC1_CLK_TX_DL_CFG_MASK (0xFFU << GRF_MAC1_CON0_GMAC1_CLK_TX_DL_CFG_SHIFT) /* 0x000000FF */ +#define GRF_MAC1_CON0_GMAC1_CLK_RX_DL_CFG_SHIFT (8U) +#define GRF_MAC1_CON0_GMAC1_CLK_RX_DL_CFG_MASK (0xFFU << GRF_MAC1_CON0_GMAC1_CLK_RX_DL_CFG_SHIFT) /* 0x0000FF00 */ +/* MAC1_CON1 */ +#define GRF_MAC1_CON1_OFFSET (0x4038CU) +#define GRF_MAC1_CON1_GMAC1_TXCLK_DLY_ENA_SHIFT (0U) +#define GRF_MAC1_CON1_GMAC1_TXCLK_DLY_ENA_MASK (0x1U << GRF_MAC1_CON1_GMAC1_TXCLK_DLY_ENA_SHIFT) /* 0x00000001 */ +#define GRF_MAC1_CON1_GMAC1_RXCLK_DLY_ENA_SHIFT (1U) +#define GRF_MAC1_CON1_GMAC1_RXCLK_DLY_ENA_MASK (0x1U << GRF_MAC1_CON1_GMAC1_RXCLK_DLY_ENA_SHIFT) /* 0x00000002 */ +#define GRF_MAC1_CON1_GMAC1_MAC_SPEED_SHIFT (2U) +#define GRF_MAC1_CON1_GMAC1_MAC_SPEED_MASK (0x1U << GRF_MAC1_CON1_GMAC1_MAC_SPEED_SHIFT) /* 0x00000004 */ +#define GRF_MAC1_CON1_GMAC1_FLOWCTRL_SHIFT (3U) +#define GRF_MAC1_CON1_GMAC1_FLOWCTRL_MASK (0x1U << GRF_MAC1_CON1_GMAC1_FLOWCTRL_SHIFT) /* 0x00000008 */ +#define GRF_MAC1_CON1_GMAC1_PHY_INTF_SEL_SHIFT (4U) +#define GRF_MAC1_CON1_GMAC1_PHY_INTF_SEL_MASK (0x7U << GRF_MAC1_CON1_GMAC1_PHY_INTF_SEL_SHIFT) /* 0x00000070 */ +#define GRF_MAC1_CON1_GMAC1_QSGMII_MODE_SHIFT (7U) +#define GRF_MAC1_CON1_GMAC1_QSGMII_MODE_MASK (0x1U << GRF_MAC1_CON1_GMAC1_QSGMII_MODE_SHIFT) /* 0x00000080 */ +/* BIU_CON0 */ +#define GRF_BIU_CON0_OFFSET (0x403A0U) +#define GRF_BIU_CON0_BUS_FWD_TOP_STALL_SHIFT (0U) +#define GRF_BIU_CON0_BUS_FWD_TOP_STALL_MASK (0x1U << GRF_BIU_CON0_BUS_FWD_TOP_STALL_SHIFT) /* 0x00000001 */ +#define GRF_BIU_CON0_CPU_FWD_MSCH_STALL_SHIFT (1U) +#define GRF_BIU_CON0_CPU_FWD_MSCH_STALL_MASK (0x1U << GRF_BIU_CON0_CPU_FWD_MSCH_STALL_SHIFT) /* 0x00000002 */ +#define GRF_BIU_CON0_CPU_FWD_TOP_STALL_SHIFT (2U) +#define GRF_BIU_CON0_CPU_FWD_TOP_STALL_MASK (0x1U << GRF_BIU_CON0_CPU_FWD_TOP_STALL_SHIFT) /* 0x00000004 */ +#define GRF_BIU_CON0_GIC_FWD_PERI_STALL_SHIFT (3U) +#define GRF_BIU_CON0_GIC_FWD_PERI_STALL_MASK (0x1U << GRF_BIU_CON0_GIC_FWD_PERI_STALL_SHIFT) /* 0x00000008 */ +#define GRF_BIU_CON0_GPU_FWD_MSCH_STALL_SHIFT (4U) +#define GRF_BIU_CON0_GPU_FWD_MSCH_STALL_MASK (0x1U << GRF_BIU_CON0_GPU_FWD_MSCH_STALL_SHIFT) /* 0x00000010 */ +#define GRF_BIU_CON0_NPU_FWD_TOP_STALL_SHIFT (5U) +#define GRF_BIU_CON0_NPU_FWD_TOP_STALL_MASK (0x1U << GRF_BIU_CON0_NPU_FWD_TOP_STALL_SHIFT) /* 0x00000020 */ +#define GRF_BIU_CON0_PERI_FWD_TOP_STALL_SHIFT (6U) +#define GRF_BIU_CON0_PERI_FWD_TOP_STALL_MASK (0x1U << GRF_BIU_CON0_PERI_FWD_TOP_STALL_SHIFT) /* 0x00000040 */ +#define GRF_BIU_CON0_PERI_REQ_GA_STALL_SHIFT (7U) +#define GRF_BIU_CON0_PERI_REQ_GA_STALL_MASK (0x1U << GRF_BIU_CON0_PERI_REQ_GA_STALL_SHIFT) /* 0x00000080 */ +#define GRF_BIU_CON0_PERI_FWD_PHP_STALL_SHIFT (8U) +#define GRF_BIU_CON0_PERI_FWD_PHP_STALL_MASK (0x1U << GRF_BIU_CON0_PERI_FWD_PHP_STALL_SHIFT) /* 0x00000100 */ +#define GRF_BIU_CON0_PERI_FWD_SF_STALL_SHIFT (9U) +#define GRF_BIU_CON0_PERI_FWD_SF_STALL_MASK (0x1U << GRF_BIU_CON0_PERI_FWD_SF_STALL_SHIFT) /* 0x00000200 */ +#define GRF_BIU_CON0_PHP_REQ_PERI_STALL_SHIFT (10U) +#define GRF_BIU_CON0_PHP_REQ_PERI_STALL_MASK (0x1U << GRF_BIU_CON0_PHP_REQ_PERI_STALL_SHIFT) /* 0x00000400 */ +#define GRF_BIU_CON0_PIPE_FWD_TOP_STALL_SHIFT (11U) +#define GRF_BIU_CON0_PIPE_FWD_TOP_STALL_MASK (0x1U << GRF_BIU_CON0_PIPE_FWD_TOP_STALL_SHIFT) /* 0x00000800 */ +#define GRF_BIU_CON0_RGA_FWD_MSCH_STALL_SHIFT (12U) +#define GRF_BIU_CON0_RGA_FWD_MSCH_STALL_MASK (0x1U << GRF_BIU_CON0_RGA_FWD_MSCH_STALL_SHIFT) /* 0x00001000 */ +#define GRF_BIU_CON0_SF_REQ_PERI_STALL_SHIFT (13U) +#define GRF_BIU_CON0_SF_REQ_PERI_STALL_MASK (0x1U << GRF_BIU_CON0_SF_REQ_PERI_STALL_SHIFT) /* 0x00002000 */ +#define GRF_BIU_CON0_TOP_FWD_DDRC_STALL_SHIFT (14U) +#define GRF_BIU_CON0_TOP_FWD_DDRC_STALL_MASK (0x1U << GRF_BIU_CON0_TOP_FWD_DDRC_STALL_SHIFT) /* 0x00004000 */ +#define GRF_BIU_CON0_TOP_FWD_MSCH_STALL_SHIFT (15U) +#define GRF_BIU_CON0_TOP_FWD_MSCH_STALL_MASK (0x1U << GRF_BIU_CON0_TOP_FWD_MSCH_STALL_SHIFT) /* 0x00008000 */ +/* BIU_CON1 */ +#define GRF_BIU_CON1_OFFSET (0x403A4U) +#define GRF_BIU_CON1_TOP_FWD_PMU_STALL_SHIFT (0U) +#define GRF_BIU_CON1_TOP_FWD_PMU_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_PMU_STALL_SHIFT) /* 0x00000001 */ +#define GRF_BIU_CON1_TOP_FWD_RGA_STALL_SHIFT (1U) +#define GRF_BIU_CON1_TOP_FWD_RGA_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_RGA_STALL_SHIFT) /* 0x00000002 */ +#define GRF_BIU_CON1_TOP_FWD_VPU_STALL_SHIFT (2U) +#define GRF_BIU_CON1_TOP_FWD_VPU_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_VPU_STALL_SHIFT) /* 0x00000004 */ +#define GRF_BIU_CON1_TOPAHPU_FWD_MSCH_STALL_SHIFT (3U) +#define GRF_BIU_CON1_TOPAHPU_FWD_MSCH_STALL_MASK (0x1U << GRF_BIU_CON1_TOPAHPU_FWD_MSCH_STALL_SHIFT) /* 0x00000008 */ +#define GRF_BIU_CON1_TOPAHVO_FWD_MSCH_STALL_SHIFT (4U) +#define GRF_BIU_CON1_TOPAHVO_FWD_MSCH_STALL_MASK (0x1U << GRF_BIU_CON1_TOPAHVO_FWD_MSCH_STALL_SHIFT) /* 0x00000010 */ +#define GRF_BIU_CON1_TOPAL_FWD_MSCH_STALL_SHIFT (5U) +#define GRF_BIU_CON1_TOPAL_FWD_MSCH_STALL_MASK (0x1U << GRF_BIU_CON1_TOPAL_FWD_MSCH_STALL_SHIFT) /* 0x00000020 */ +#define GRF_BIU_CON1_TOP_FWD_USB_STALL_SHIFT (6U) +#define GRF_BIU_CON1_TOP_FWD_USB_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_USB_STALL_SHIFT) /* 0x00000040 */ +#define GRF_BIU_CON1_TOP_FWD_VI_STALL_SHIFT (7U) +#define GRF_BIU_CON1_TOP_FWD_VI_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_VI_STALL_SHIFT) /* 0x00000080 */ +#define GRF_BIU_CON1_TOP_FWD_VO_STALL_SHIFT (8U) +#define GRF_BIU_CON1_TOP_FWD_VO_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_VO_STALL_SHIFT) /* 0x00000100 */ +#define GRF_BIU_CON1_TOP_FWD_GPU_STALL_SHIFT (9U) +#define GRF_BIU_CON1_TOP_FWD_GPU_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_GPU_STALL_SHIFT) /* 0x00000200 */ +#define GRF_BIU_CON1_TOP_FWD_VDEC_STALL_SHIFT (10U) +#define GRF_BIU_CON1_TOP_FWD_VDEC_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_VDEC_STALL_SHIFT) /* 0x00000400 */ +#define GRF_BIU_CON1_TOP_FWD_VENC_STALL_SHIFT (11U) +#define GRF_BIU_CON1_TOP_FWD_VENC_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_VENC_STALL_SHIFT) /* 0x00000800 */ +#define GRF_BIU_CON1_TOP_FWD_BUS_STALL_SHIFT (12U) +#define GRF_BIU_CON1_TOP_FWD_BUS_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_BUS_STALL_SHIFT) /* 0x00001000 */ +#define GRF_BIU_CON1_TOP_FWD_NPU_STALL_SHIFT (13U) +#define GRF_BIU_CON1_TOP_FWD_NPU_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_NPU_STALL_SHIFT) /* 0x00002000 */ +#define GRF_BIU_CON1_TOP_FWD_PERI_STALL_SHIFT (14U) +#define GRF_BIU_CON1_TOP_FWD_PERI_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_PERI_STALL_SHIFT) /* 0x00004000 */ +#define GRF_BIU_CON1_TOP_FWD_PIPE_STALL_SHIFT (15U) +#define GRF_BIU_CON1_TOP_FWD_PIPE_STALL_MASK (0x1U << GRF_BIU_CON1_TOP_FWD_PIPE_STALL_SHIFT) /* 0x00008000 */ +/* BIU_CON2 */ +#define GRF_BIU_CON2_OFFSET (0x403A8U) +#define GRF_BIU_CON2_USB_FWD_MSCH_STALL_SHIFT (0U) +#define GRF_BIU_CON2_USB_FWD_MSCH_STALL_MASK (0x1U << GRF_BIU_CON2_USB_FWD_MSCH_STALL_SHIFT) /* 0x00000001 */ +#define GRF_BIU_CON2_VDEC_FWD_MSCH_STALL_SHIFT (1U) +#define GRF_BIU_CON2_VDEC_FWD_MSCH_STALL_MASK (0x1U << GRF_BIU_CON2_VDEC_FWD_MSCH_STALL_SHIFT) /* 0x00000002 */ +#define GRF_BIU_CON2_VDEC_FWD_TOP_STALL_SHIFT (2U) +#define GRF_BIU_CON2_VDEC_FWD_TOP_STALL_MASK (0x1U << GRF_BIU_CON2_VDEC_FWD_TOP_STALL_SHIFT) /* 0x00000004 */ +#define GRF_BIU_CON2_VENC_FWD_MSCH_STALL_SHIFT (3U) +#define GRF_BIU_CON2_VENC_FWD_MSCH_STALL_MASK (0x1U << GRF_BIU_CON2_VENC_FWD_MSCH_STALL_SHIFT) /* 0x00000008 */ +#define GRF_BIU_CON2_VI_FWD_TOP_STALL_SHIFT (4U) +#define GRF_BIU_CON2_VI_FWD_TOP_STALL_MASK (0x1U << GRF_BIU_CON2_VI_FWD_TOP_STALL_SHIFT) /* 0x00000010 */ +#define GRF_BIU_CON2_VO_FWD_TOP_STALL_SHIFT (5U) +#define GRF_BIU_CON2_VO_FWD_TOP_STALL_MASK (0x1U << GRF_BIU_CON2_VO_FWD_TOP_STALL_SHIFT) /* 0x00000020 */ +#define GRF_BIU_CON2_VPU_FWD_MSCH_STALL_SHIFT (6U) +#define GRF_BIU_CON2_VPU_FWD_MSCH_STALL_MASK (0x1U << GRF_BIU_CON2_VPU_FWD_MSCH_STALL_SHIFT) /* 0x00000040 */ +/* GIC_CON0 */ +#define GRF_GIC_CON0_OFFSET (0x403C0U) +#define GRF_GIC_CON0_GICD_PAGE_OFFSET_SHIFT (0U) +#define GRF_GIC_CON0_GICD_PAGE_OFFSET_MASK (0xFFFFU << GRF_GIC_CON0_GICD_PAGE_OFFSET_SHIFT) /* 0x0000FFFF */ +/* GIC_CON1 */ +#define GRF_GIC_CON1_OFFSET (0x403C4U) +#define GRF_GIC_CON1_ITS_TRANSR_PAGE_OFFSET_SHIFT (0U) +#define GRF_GIC_CON1_ITS_TRANSR_PAGE_OFFSET_MASK (0xFFFFU << GRF_GIC_CON1_ITS_TRANSR_PAGE_OFFSET_SHIFT) /* 0x0000FFFF */ +/* GIC_CON2 */ +#define GRF_GIC_CON2_OFFSET (0x403C8U) +#define GRF_GIC_CON2_CPU_ACTIVE_SHIFT (0U) +#define GRF_GIC_CON2_CPU_ACTIVE_MASK (0xFU << GRF_GIC_CON2_CPU_ACTIVE_SHIFT) /* 0x0000000F */ +#define GRF_GIC_CON2_SAMPLE_REQ_SHIFT (4U) +#define GRF_GIC_CON2_SAMPLE_REQ_MASK (0x1U << GRF_GIC_CON2_SAMPLE_REQ_SHIFT) /* 0x00000010 */ +#define GRF_GIC_CON2_GIC2CORE_PWRQ_PERMIT_DENY_SAR_SHIFT (5U) +#define GRF_GIC_CON2_GIC2CORE_PWRQ_PERMIT_DENY_SAR_MASK (0x1U << GRF_GIC_CON2_GIC2CORE_PWRQ_PERMIT_DENY_SAR_SHIFT) /* 0x00000020 */ +/* GPU_CON0 */ +#define GRF_GPU_CON0_OFFSET (0x403F0U) +#define GRF_GPU_CON0_DBGEN_SHIFT (0U) +#define GRF_GPU_CON0_DBGEN_MASK (0x1U << GRF_GPU_CON0_DBGEN_SHIFT) /* 0x00000001 */ +#define GRF_GPU_CON0_NIDEN_SHIFT (1U) +#define GRF_GPU_CON0_NIDEN_MASK (0x1U << GRF_GPU_CON0_NIDEN_SHIFT) /* 0x00000002 */ +#define GRF_GPU_CON0_STRIPPING_GRANULE_SHIFT (2U) +#define GRF_GPU_CON0_STRIPPING_GRANULE_MASK (0x7U << GRF_GPU_CON0_STRIPPING_GRANULE_SHIFT) /* 0x0000001C */ +/* GPU_CON1 */ +#define GRF_GPU_CON1_OFFSET (0x403F4U) +#define GRF_GPU_CON1_GPU_TEXFMTENABLE_SHIFT (0U) +#define GRF_GPU_CON1_GPU_TEXFMTENABLE_MASK (0xFFFFFFFFU << GRF_GPU_CON1_GPU_TEXFMTENABLE_SHIFT) /* 0xFFFFFFFF */ +/* CPU_CON0 */ +#define GRF_CPU_CON0_OFFSET (0x40400U) +#define GRF_CPU_CON0_CFGEND_SHIFT (0U) +#define GRF_CPU_CON0_CFGEND_MASK (0xFU << GRF_CPU_CON0_CFGEND_SHIFT) /* 0x0000000F */ +#define GRF_CPU_CON0_CFGTE_SHIFT (4U) +#define GRF_CPU_CON0_CFGTE_MASK (0xFU << GRF_CPU_CON0_CFGTE_SHIFT) /* 0x000000F0 */ +#define GRF_CPU_CON0_PMUSNAPSHOTREQ_SHIFT (8U) +#define GRF_CPU_CON0_PMUSNAPSHOTREQ_MASK (0x1U << GRF_CPU_CON0_PMUSNAPSHOTREQ_SHIFT) /* 0x00000100 */ +#define GRF_CPU_CON0_DBGCONNECTED_SHIFT (9U) +#define GRF_CPU_CON0_DBGCONNECTED_MASK (0x1U << GRF_CPU_CON0_DBGCONNECTED_SHIFT) /* 0x00000200 */ +#define GRF_CPU_CON0_EVENTOACK_SHIFT (10U) +#define GRF_CPU_CON0_EVENTOACK_MASK (0x1U << GRF_CPU_CON0_EVENTOACK_SHIFT) /* 0x00000400 */ +#define GRF_CPU_CON0_EVENCTIREQ_SHIFT (11U) +#define GRF_CPU_CON0_EVENCTIREQ_MASK (0x1U << GRF_CPU_CON0_EVENCTIREQ_SHIFT) /* 0x00000800 */ +#define GRF_CPU_CON0_ADB400_PWRQ_PERMIT_DENY_SHIFT (13U) +#define GRF_CPU_CON0_ADB400_PWRQ_PERMIT_DENY_MASK (0x1U << GRF_CPU_CON0_ADB400_PWRQ_PERMIT_DENY_SHIFT) /* 0x00002000 */ +/* CPU_STATUS0 */ +#define GRF_CPU_STATUS0_OFFSET (0x40420U) +#define GRF_CPU_STATUS0_COREINSTRUN_SHIFT (0U) +#define GRF_CPU_STATUS0_COREINSTRUN_MASK (0xFU << GRF_CPU_STATUS0_COREINSTRUN_SHIFT) /* 0x0000000F */ +#define GRF_CPU_STATUS0_COREINSTRRET_SHIFT (4U) +#define GRF_CPU_STATUS0_COREINSTRRET_MASK (0xFU << GRF_CPU_STATUS0_COREINSTRRET_SHIFT) /* 0x000000F0 */ +#define GRF_CPU_STATUS0_PMUSNAPSHOTACK_SHIFT (8U) +#define GRF_CPU_STATUS0_PMUSNAPSHOTACK_MASK (0x1U << GRF_CPU_STATUS0_PMUSNAPSHOTACK_SHIFT) /* 0x00000100 */ +#define GRF_CPU_STATUS0_EVENTIACK_SHIFT (10U) +#define GRF_CPU_STATUS0_EVENTIACK_MASK (0x1U << GRF_CPU_STATUS0_EVENTIACK_SHIFT) /* 0x00000400 */ +#define GRF_CPU_STATUS0_EVENTOREQ_SHIFT (11U) +#define GRF_CPU_STATUS0_EVENTOREQ_MASK (0x1U << GRF_CPU_STATUS0_EVENTOREQ_SHIFT) /* 0x00000800 */ +#define GRF_CPU_STATUS0_SWACTIVE_SHIFT (12U) +#define GRF_CPU_STATUS0_SWACTIVE_MASK (0x1U << GRF_CPU_STATUS0_SWACTIVE_SHIFT) /* 0x00001000 */ +#define GRF_CPU_STATUS0_JTAGACTIVE_SHIFT (13U) +#define GRF_CPU_STATUS0_JTAGACTIVE_MASK (0x1U << GRF_CPU_STATUS0_JTAGACTIVE_SHIFT) /* 0x00002000 */ +#define GRF_CPU_STATUS0_JTAGIR_SHIFT (14U) +#define GRF_CPU_STATUS0_JTAGIR_MASK (0xFU << GRF_CPU_STATUS0_JTAGIR_SHIFT) /* 0x0003C000 */ +#define GRF_CPU_STATUS0_JTAGSTATE_SHIFT (18U) +#define GRF_CPU_STATUS0_JTAGSTATE_MASK (0xFU << GRF_CPU_STATUS0_JTAGSTATE_SHIFT) /* 0x003C0000 */ +#define GRF_CPU_STATUS0_DORMANTSTATE_SHIFT (22U) +#define GRF_CPU_STATUS0_DORMANTSTATE_MASK (0x1U << GRF_CPU_STATUS0_DORMANTSTATE_SHIFT) /* 0x00400000 */ +/* SOC_CON10 */ +#define GRF_SOC_CON10_OFFSET (0x40500U) +#define GRF_SOC_CON10_UART1_CTS_INV_SHIFT (0U) +#define GRF_SOC_CON10_UART1_CTS_INV_MASK (0x1U << GRF_SOC_CON10_UART1_CTS_INV_SHIFT) /* 0x00000001 */ +#define GRF_SOC_CON10_UART1_RTS_INV_SHIFT (1U) +#define GRF_SOC_CON10_UART1_RTS_INV_MASK (0x1U << GRF_SOC_CON10_UART1_RTS_INV_SHIFT) /* 0x00000002 */ +#define GRF_SOC_CON10_UART2_CTS_INV_SHIFT (2U) +#define GRF_SOC_CON10_UART2_CTS_INV_MASK (0x1U << GRF_SOC_CON10_UART2_CTS_INV_SHIFT) /* 0x00000004 */ +#define GRF_SOC_CON10_UART2_RTS_INV_SHIFT (3U) +#define GRF_SOC_CON10_UART2_RTS_INV_MASK (0x1U << GRF_SOC_CON10_UART2_RTS_INV_SHIFT) /* 0x00000008 */ +#define GRF_SOC_CON10_UART3_CTS_INV_SHIFT (4U) +#define GRF_SOC_CON10_UART3_CTS_INV_MASK (0x1U << GRF_SOC_CON10_UART3_CTS_INV_SHIFT) /* 0x00000010 */ +#define GRF_SOC_CON10_UART3_RTS_INV_SHIFT (5U) +#define GRF_SOC_CON10_UART3_RTS_INV_MASK (0x1U << GRF_SOC_CON10_UART3_RTS_INV_SHIFT) /* 0x00000020 */ +#define GRF_SOC_CON10_UART4_CTS_INV_SHIFT (6U) +#define GRF_SOC_CON10_UART4_CTS_INV_MASK (0x1U << GRF_SOC_CON10_UART4_CTS_INV_SHIFT) /* 0x00000040 */ +#define GRF_SOC_CON10_UART4_RTS_INV_SHIFT (7U) +#define GRF_SOC_CON10_UART4_RTS_INV_MASK (0x1U << GRF_SOC_CON10_UART4_RTS_INV_SHIFT) /* 0x00000080 */ +#define GRF_SOC_CON10_UART5_CTS_INV_SHIFT (8U) +#define GRF_SOC_CON10_UART5_CTS_INV_MASK (0x1U << GRF_SOC_CON10_UART5_CTS_INV_SHIFT) /* 0x00000100 */ +#define GRF_SOC_CON10_UART5_RTS_INV_SHIFT (9U) +#define GRF_SOC_CON10_UART5_RTS_INV_MASK (0x1U << GRF_SOC_CON10_UART5_RTS_INV_SHIFT) /* 0x00000200 */ +#define GRF_SOC_CON10_UART6_CTS_INV_SHIFT (10U) +#define GRF_SOC_CON10_UART6_CTS_INV_MASK (0x1U << GRF_SOC_CON10_UART6_CTS_INV_SHIFT) /* 0x00000400 */ +#define GRF_SOC_CON10_UART6_RTS_INV_SHIFT (11U) +#define GRF_SOC_CON10_UART6_RTS_INV_MASK (0x1U << GRF_SOC_CON10_UART6_RTS_INV_SHIFT) /* 0x00000800 */ +#define GRF_SOC_CON10_UART7_CTS_INV_SHIFT (12U) +#define GRF_SOC_CON10_UART7_CTS_INV_MASK (0x1U << GRF_SOC_CON10_UART7_CTS_INV_SHIFT) /* 0x00001000 */ +#define GRF_SOC_CON10_UART7_RTS_INV_SHIFT (13U) +#define GRF_SOC_CON10_UART7_RTS_INV_MASK (0x1U << GRF_SOC_CON10_UART7_RTS_INV_SHIFT) /* 0x00002000 */ +#define GRF_SOC_CON10_UART8_CTS_INV_SHIFT (14U) +#define GRF_SOC_CON10_UART8_CTS_INV_MASK (0x1U << GRF_SOC_CON10_UART8_CTS_INV_SHIFT) /* 0x00004000 */ +#define GRF_SOC_CON10_UART8_RTS_INV_SHIFT (15U) +#define GRF_SOC_CON10_UART8_RTS_INV_MASK (0x1U << GRF_SOC_CON10_UART8_RTS_INV_SHIFT) /* 0x00008000 */ +/* SOC_CON11 */ +#define GRF_SOC_CON11_OFFSET (0x40504U) +#define GRF_SOC_CON11_UART9_CTS_INV_SHIFT (0U) +#define GRF_SOC_CON11_UART9_CTS_INV_MASK (0x1U << GRF_SOC_CON11_UART9_CTS_INV_SHIFT) /* 0x00000001 */ +#define GRF_SOC_CON11_UART9_RTS_INV_SHIFT (1U) +#define GRF_SOC_CON11_UART9_RTS_INV_MASK (0x1U << GRF_SOC_CON11_UART9_RTS_INV_SHIFT) /* 0x00000002 */ +#define GRF_SOC_CON11_EMMC_CLKBYPASS_SHIFT (2U) +#define GRF_SOC_CON11_EMMC_CLKBYPASS_MASK (0x1U << GRF_SOC_CON11_EMMC_CLKBYPASS_SHIFT) /* 0x00000004 */ +#define GRF_SOC_CON11_EMMC_CLKSTABLE_SHIFT (3U) +#define GRF_SOC_CON11_EMMC_CLKSTABLE_MASK (0x1U << GRF_SOC_CON11_EMMC_CLKSTABLE_SHIFT) /* 0x00000008 */ +#define GRF_SOC_CON11_WDT_NS_PAUSE_EN_SHIFT (4U) +#define GRF_SOC_CON11_WDT_NS_PAUSE_EN_MASK (0x1U << GRF_SOC_CON11_WDT_NS_PAUSE_EN_SHIFT) /* 0x00000010 */ +#define GRF_SOC_CON11_I2S1_MCLK_SEL_SHIFT (5U) +#define GRF_SOC_CON11_I2S1_MCLK_SEL_MASK (0x1U << GRF_SOC_CON11_I2S1_MCLK_SEL_SHIFT) /* 0x00000020 */ +#define GRF_SOC_CON11_I2S3_LRCK_SEL_SHIFT (6U) +#define GRF_SOC_CON11_I2S3_LRCK_SEL_MASK (0x1U << GRF_SOC_CON11_I2S3_LRCK_SEL_SHIFT) /* 0x00000040 */ +#define GRF_SOC_CON11_I2S3_SCLK_SEL_SHIFT (7U) +#define GRF_SOC_CON11_I2S3_SCLK_SEL_MASK (0x1U << GRF_SOC_CON11_I2S3_SCLK_SEL_SHIFT) /* 0x00000080 */ +#define GRF_SOC_CON11_PCIE_ADDR_EXTEND_SHIFT (8U) +#define GRF_SOC_CON11_PCIE_ADDR_EXTEND_MASK (0x1U << GRF_SOC_CON11_PCIE_ADDR_EXTEND_SHIFT) /* 0x00000100 */ +#define GRF_SOC_CON11_SDMMC0_BUFFER_EN_SHIFT (9U) +#define GRF_SOC_CON11_SDMMC0_BUFFER_EN_MASK (0x1U << GRF_SOC_CON11_SDMMC0_BUFFER_EN_SHIFT) /* 0x00000200 */ +#define GRF_SOC_CON11_SDMMC1_BUFFER_EN_SHIFT (10U) +#define GRF_SOC_CON11_SDMMC1_BUFFER_EN_MASK (0x1U << GRF_SOC_CON11_SDMMC1_BUFFER_EN_SHIFT) /* 0x00000400 */ +#define GRF_SOC_CON11_SDMMC2_BUFFER_EN_SHIFT (11U) +#define GRF_SOC_CON11_SDMMC2_BUFFER_EN_MASK (0x1U << GRF_SOC_CON11_SDMMC2_BUFFER_EN_SHIFT) /* 0x00000800 */ +#define GRF_SOC_CON11_OTPCS_LOCK_SHIFT (12U) +#define GRF_SOC_CON11_OTPCS_LOCK_MASK (0x1U << GRF_SOC_CON11_OTPCS_LOCK_SHIFT) /* 0x00001000 */ +#define GRF_SOC_CON11_OPTCNS_LOCK_SHIFT (13U) +#define GRF_SOC_CON11_OPTCNS_LOCK_MASK (0x1U << GRF_SOC_CON11_OPTCNS_LOCK_SHIFT) /* 0x00002000 */ +/* SOC_CON12 */ +#define GRF_SOC_CON12_OFFSET (0x40508U) +#define GRF_SOC_CON12_I2S1_MCLK_RX_OE_SHIFT (0U) +#define GRF_SOC_CON12_I2S1_MCLK_RX_OE_MASK (0x1U << GRF_SOC_CON12_I2S1_MCLK_RX_OE_SHIFT) /* 0x00000001 */ +#define GRF_SOC_CON12_I2S1_MCLK_TX_OE_SHIFT (1U) +#define GRF_SOC_CON12_I2S1_MCLK_TX_OE_MASK (0x1U << GRF_SOC_CON12_I2S1_MCLK_TX_OE_SHIFT) /* 0x00000002 */ +#define GRF_SOC_CON12_I2S2_MCLK_OE_SHIFT (2U) +#define GRF_SOC_CON12_I2S2_MCLK_OE_MASK (0x1U << GRF_SOC_CON12_I2S2_MCLK_OE_SHIFT) /* 0x00000004 */ +#define GRF_SOC_CON12_I2S3_MCLK_OE_SHIFT (3U) +#define GRF_SOC_CON12_I2S3_MCLK_OE_MASK (0x1U << GRF_SOC_CON12_I2S3_MCLK_OE_SHIFT) /* 0x00000008 */ +#define GRF_SOC_CON12_WDTNS_GLB_RESET_EN_SHIFT (4U) +#define GRF_SOC_CON12_WDTNS_GLB_RESET_EN_MASK (0x1U << GRF_SOC_CON12_WDTNS_GLB_RESET_EN_SHIFT) /* 0x00000010 */ +#define GRF_SOC_CON12_SCR_DET_INV_SEL_SHIFT (5U) +#define GRF_SOC_CON12_SCR_DET_INV_SEL_MASK (0x1U << GRF_SOC_CON12_SCR_DET_INV_SEL_SHIFT) /* 0x00000020 */ +#define GRF_SOC_CON12_PMU_PWR_IDLE_REQ_SHIFT (10U) +#define GRF_SOC_CON12_PMU_PWR_IDLE_REQ_MASK (0x1U << GRF_SOC_CON12_PMU_PWR_IDLE_REQ_SHIFT) /* 0x00000400 */ +#define GRF_SOC_CON12_BUS_PWR_IDLE_REQ_SHIFT (11U) +#define GRF_SOC_CON12_BUS_PWR_IDLE_REQ_MASK (0x1U << GRF_SOC_CON12_BUS_PWR_IDLE_REQ_SHIFT) /* 0x00000800 */ +#define GRF_SOC_CON12_ACDCDIG_I2S_ACTIVE_SHIFT (13U) +#define GRF_SOC_CON12_ACDCDIG_I2S_ACTIVE_MASK (0x1U << GRF_SOC_CON12_ACDCDIG_I2S_ACTIVE_SHIFT) /* 0x00002000 */ +#define GRF_SOC_CON12_ACDCDIG_I2C_TRAN_REQ_SHIFT (14U) +#define GRF_SOC_CON12_ACDCDIG_I2C_TRAN_REQ_MASK (0x1U << GRF_SOC_CON12_ACDCDIG_I2C_TRAN_REQ_SHIFT) /* 0x00004000 */ +#define GRF_SOC_CON12_I2S3_MCLK_SEL_SHIFT (15U) +#define GRF_SOC_CON12_I2S3_MCLK_SEL_MASK (0x1U << GRF_SOC_CON12_I2S3_MCLK_SEL_SHIFT) /* 0x00008000 */ +/* SOC_CON13 */ +#define GRF_SOC_CON13_OFFSET (0x4050CU) +#define GRF_SOC_CON13_SDMMC_BUFFER_WR_THRESH_SHIFT (0U) +#define GRF_SOC_CON13_SDMMC_BUFFER_WR_THRESH_MASK (0x1FU << GRF_SOC_CON13_SDMMC_BUFFER_WR_THRESH_SHIFT) /* 0x0000001F */ +#define GRF_SOC_CON13_SDMMC_BUFFER_EN_SHIFT (6U) +#define GRF_SOC_CON13_SDMMC_BUFFER_EN_MASK (0x1U << GRF_SOC_CON13_SDMMC_BUFFER_EN_SHIFT) /* 0x00000040 */ +#define GRF_SOC_CON13_SDMMC_BUF_CLK_INV_SEL_SHIFT (7U) +#define GRF_SOC_CON13_SDMMC_BUF_CLK_INV_SEL_MASK (0x1U << GRF_SOC_CON13_SDMMC_BUF_CLK_INV_SEL_SHIFT) /* 0x00000080 */ +#define GRF_SOC_CON13_HDCP_UART_EN_SHIFT (8U) +#define GRF_SOC_CON13_HDCP_UART_EN_MASK (0x1U << GRF_SOC_CON13_HDCP_UART_EN_SHIFT) /* 0x00000100 */ +#define GRF_SOC_CON13_MCU_SOFT_IRQ_SHIFT (12U) +#define GRF_SOC_CON13_MCU_SOFT_IRQ_MASK (0x1U << GRF_SOC_CON13_MCU_SOFT_IRQ_SHIFT) /* 0x00001000 */ +#define GRF_SOC_CON13_MCU_SEL_AXI_SHIFT (13U) +#define GRF_SOC_CON13_MCU_SEL_AXI_MASK (0x1U << GRF_SOC_CON13_MCU_SEL_AXI_SHIFT) /* 0x00002000 */ +#define GRF_SOC_CON13_MCU_AHB2AXI_I_BUF_FLUSH_SHIFT (14U) +#define GRF_SOC_CON13_MCU_AHB2AXI_I_BUF_FLUSH_MASK (0x1U << GRF_SOC_CON13_MCU_AHB2AXI_I_BUF_FLUSH_SHIFT) /* 0x00004000 */ +#define GRF_SOC_CON13_MCU_AHB2AXI_D_BUF_FLUSH_SHIFT (15U) +#define GRF_SOC_CON13_MCU_AHB2AXI_D_BUF_FLUSH_MASK (0x1U << GRF_SOC_CON13_MCU_AHB2AXI_D_BUF_FLUSH_SHIFT) /* 0x00008000 */ +/* SOC_CON14 */ +#define GRF_SOC_CON14_OFFSET (0x40510U) +#define GRF_SOC_CON14_MCU_BOOT_ADDR_SHIFT (0U) +#define GRF_SOC_CON14_MCU_BOOT_ADDR_MASK (0xFFFFU << GRF_SOC_CON14_MCU_BOOT_ADDR_SHIFT) /* 0x0000FFFF */ +/* SOC_CON15 */ +#define GRF_SOC_CON15_OFFSET (0x40514U) +#define GRF_SOC_CON15_SDCARD_DECTN_DLY_SHIFT (0U) +#define GRF_SOC_CON15_SDCARD_DECTN_DLY_MASK (0xFFFFFFFFU << GRF_SOC_CON15_SDCARD_DECTN_DLY_SHIFT) /* 0xFFFFFFFF */ +/* SOC_CON16 */ +#define GRF_SOC_CON16_OFFSET (0x40518U) +#define GRF_SOC_CON16_AHB2AXI_D_TIMEOUT_SHIFT (0U) +#define GRF_SOC_CON16_AHB2AXI_D_TIMEOUT_MASK (0xFFU << GRF_SOC_CON16_AHB2AXI_D_TIMEOUT_SHIFT) /* 0x000000FF */ +#define GRF_SOC_CON16_AHB2AXI_I_RD_CLEAN_SHIFT (8U) +#define GRF_SOC_CON16_AHB2AXI_I_RD_CLEAN_MASK (0x1U << GRF_SOC_CON16_AHB2AXI_I_RD_CLEAN_SHIFT) /* 0x00000100 */ +#define GRF_SOC_CON16_AHB2AXI_D_RD_CLEAN_SHIFT (9U) +#define GRF_SOC_CON16_AHB2AXI_D_RD_CLEAN_MASK (0x1U << GRF_SOC_CON16_AHB2AXI_D_RD_CLEAN_SHIFT) /* 0x00000200 */ +#define GRF_SOC_CON16_PCIE30PHY_PRB_IO_EN_SHIFT (10U) +#define GRF_SOC_CON16_PCIE30PHY_PRB_IO_EN_MASK (0x1U << GRF_SOC_CON16_PCIE30PHY_PRB_IO_EN_SHIFT) /* 0x00000400 */ +#define GRF_SOC_CON16_HPLL_CLK_SEL_SHIFT (11U) +#define GRF_SOC_CON16_HPLL_CLK_SEL_MASK (0x1U << GRF_SOC_CON16_HPLL_CLK_SEL_SHIFT) /* 0x00000800 */ +#define GRF_SOC_CON16_PPLL_CLK_SEL_SHIFT (12U) +#define GRF_SOC_CON16_PPLL_CLK_SEL_MASK (0x1U << GRF_SOC_CON16_PPLL_CLK_SEL_SHIFT) /* 0x00001000 */ +#define GRF_SOC_CON16_GMAC0_TXCLK_INV_EN_SHIFT (13U) +#define GRF_SOC_CON16_GMAC0_TXCLK_INV_EN_MASK (0x1U << GRF_SOC_CON16_GMAC0_TXCLK_INV_EN_SHIFT) /* 0x00002000 */ +#define GRF_SOC_CON16_GMAC1_TXCLKM0_INV_EN_SHIFT (14U) +#define GRF_SOC_CON16_GMAC1_TXCLKM0_INV_EN_MASK (0x1U << GRF_SOC_CON16_GMAC1_TXCLKM0_INV_EN_SHIFT) /* 0x00004000 */ +#define GRF_SOC_CON16_GMAC1_TXCLKM1_INV_EN_SHIFT (15U) +#define GRF_SOC_CON16_GMAC1_TXCLKM1_INV_EN_MASK (0x1U << GRF_SOC_CON16_GMAC1_TXCLKM1_INV_EN_SHIFT) /* 0x00008000 */ +/* SOC_STATUS0 */ +#define GRF_SOC_STATUS0_OFFSET (0x40580U) +#define GRF_SOC_STATUS0_APLL_LOCK_SHIFT (0U) +#define GRF_SOC_STATUS0_APLL_LOCK_MASK (0x1U << GRF_SOC_STATUS0_APLL_LOCK_SHIFT) /* 0x00000001 */ +#define GRF_SOC_STATUS0_DPLL_LOCK_SHIFT (1U) +#define GRF_SOC_STATUS0_DPLL_LOCK_MASK (0x1U << GRF_SOC_STATUS0_DPLL_LOCK_SHIFT) /* 0x00000002 */ +#define GRF_SOC_STATUS0_CPLL_LOCK_SHIFT (2U) +#define GRF_SOC_STATUS0_CPLL_LOCK_MASK (0x1U << GRF_SOC_STATUS0_CPLL_LOCK_SHIFT) /* 0x00000004 */ +#define GRF_SOC_STATUS0_GPLL_LOCK_SHIFT (3U) +#define GRF_SOC_STATUS0_GPLL_LOCK_MASK (0x1U << GRF_SOC_STATUS0_GPLL_LOCK_SHIFT) /* 0x00000008 */ +#define GRF_SOC_STATUS0_PPLL_LOCK_SHIFT (4U) +#define GRF_SOC_STATUS0_PPLL_LOCK_MASK (0x1U << GRF_SOC_STATUS0_PPLL_LOCK_SHIFT) /* 0x00000010 */ +#define GRF_SOC_STATUS0_NPLL_LOCK_SHIFT (5U) +#define GRF_SOC_STATUS0_NPLL_LOCK_MASK (0x1U << GRF_SOC_STATUS0_NPLL_LOCK_SHIFT) /* 0x00000020 */ +#define GRF_SOC_STATUS0_VPLL_LOCK_SHIFT (6U) +#define GRF_SOC_STATUS0_VPLL_LOCK_MASK (0x1U << GRF_SOC_STATUS0_VPLL_LOCK_SHIFT) /* 0x00000040 */ +#define GRF_SOC_STATUS0_HPLL_LOCK_SHIFT (7U) +#define GRF_SOC_STATUS0_HPLL_LOCK_MASK (0x1U << GRF_SOC_STATUS0_HPLL_LOCK_SHIFT) /* 0x00000080 */ +#define GRF_SOC_STATUS0_MPLL_LOCK_SHIFT (8U) +#define GRF_SOC_STATUS0_MPLL_LOCK_MASK (0x1U << GRF_SOC_STATUS0_MPLL_LOCK_SHIFT) /* 0x00000100 */ +#define GRF_SOC_STATUS0_ACDCDIG_I2C_TRAN_ACK_SHIFT (9U) +#define GRF_SOC_STATUS0_ACDCDIG_I2C_TRAN_ACK_MASK (0x1U << GRF_SOC_STATUS0_ACDCDIG_I2C_TRAN_ACK_SHIFT) /* 0x00000200 */ +#define GRF_SOC_STATUS0_DDR_CMD_PLL_LOCK_SHIFT (10U) +#define GRF_SOC_STATUS0_DDR_CMD_PLL_LOCK_MASK (0x1U << GRF_SOC_STATUS0_DDR_CMD_PLL_LOCK_SHIFT) /* 0x00000400 */ +#define GRF_SOC_STATUS0_TIMER_EN_STATUS0_SHIFT (11U) +#define GRF_SOC_STATUS0_TIMER_EN_STATUS0_MASK (0x1U << GRF_SOC_STATUS0_TIMER_EN_STATUS0_SHIFT) /* 0x00000800 */ +#define GRF_SOC_STATUS0_TIMER_EN_STATUS1_SHIFT (12U) +#define GRF_SOC_STATUS0_TIMER_EN_STATUS1_MASK (0x1U << GRF_SOC_STATUS0_TIMER_EN_STATUS1_SHIFT) /* 0x00001000 */ +#define GRF_SOC_STATUS0_TIMER_EN_STATUS2_SHIFT (13U) +#define GRF_SOC_STATUS0_TIMER_EN_STATUS2_MASK (0x1U << GRF_SOC_STATUS0_TIMER_EN_STATUS2_SHIFT) /* 0x00002000 */ +#define GRF_SOC_STATUS0_TIMER_EN_STATUS3_SHIFT (14U) +#define GRF_SOC_STATUS0_TIMER_EN_STATUS3_MASK (0x1U << GRF_SOC_STATUS0_TIMER_EN_STATUS3_SHIFT) /* 0x00004000 */ +#define GRF_SOC_STATUS0_TIMER_EN_STATUS4_SHIFT (15U) +#define GRF_SOC_STATUS0_TIMER_EN_STATUS4_MASK (0x1U << GRF_SOC_STATUS0_TIMER_EN_STATUS4_SHIFT) /* 0x00008000 */ +#define GRF_SOC_STATUS0_TIMER_EN_STATUS5_SHIFT (16U) +#define GRF_SOC_STATUS0_TIMER_EN_STATUS5_MASK (0x1U << GRF_SOC_STATUS0_TIMER_EN_STATUS5_SHIFT) /* 0x00010000 */ +#define GRF_SOC_STATUS0_VOP_DMA_FINISH_SHIFT (17U) +#define GRF_SOC_STATUS0_VOP_DMA_FINISH_MASK (0x1U << GRF_SOC_STATUS0_VOP_DMA_FINISH_SHIFT) /* 0x00020000 */ +#define GRF_SOC_STATUS0_SCRAMBLE_SHIFT_READY_SHIFT (18U) +#define GRF_SOC_STATUS0_SCRAMBLE_SHIFT_READY_MASK (0x1U << GRF_SOC_STATUS0_SCRAMBLE_SHIFT_READY_SHIFT) /* 0x00040000 */ +#define GRF_SOC_STATUS0_BUF_FLUSH_ACK_I_SHIFT (19U) +#define GRF_SOC_STATUS0_BUF_FLUSH_ACK_I_MASK (0x1U << GRF_SOC_STATUS0_BUF_FLUSH_ACK_I_SHIFT) /* 0x00080000 */ +#define GRF_SOC_STATUS0_BUF_FLUSH_ACK_D_SHIFT (20U) +#define GRF_SOC_STATUS0_BUF_FLUSH_ACK_D_MASK (0x1U << GRF_SOC_STATUS0_BUF_FLUSH_ACK_D_SHIFT) /* 0x00100000 */ +#define GRF_SOC_STATUS0_PMU_PWR_IDLE_SHIFT (21U) +#define GRF_SOC_STATUS0_PMU_PWR_IDLE_MASK (0x1U << GRF_SOC_STATUS0_PMU_PWR_IDLE_SHIFT) /* 0x00200000 */ +#define GRF_SOC_STATUS0_PMU_PWR_IDLE_ACK_SHIFT (22U) +#define GRF_SOC_STATUS0_PMU_PWR_IDLE_ACK_MASK (0x1U << GRF_SOC_STATUS0_PMU_PWR_IDLE_ACK_SHIFT) /* 0x00400000 */ +#define GRF_SOC_STATUS0_OTPCNS_SBPI_BUSY_SHIFT (23U) +#define GRF_SOC_STATUS0_OTPCNS_SBPI_BUSY_MASK (0x1U << GRF_SOC_STATUS0_OTPCNS_SBPI_BUSY_SHIFT) /* 0x00800000 */ +#define GRF_SOC_STATUS0_OTPCNS_USER_BUSY_SHIFT (24U) +#define GRF_SOC_STATUS0_OTPCNS_USER_BUSY_MASK (0x1U << GRF_SOC_STATUS0_OTPCNS_USER_BUSY_SHIFT) /* 0x01000000 */ +#define GRF_SOC_STATUS0_OTP_S_SBPI_BUSY_SHIFT (25U) +#define GRF_SOC_STATUS0_OTP_S_SBPI_BUSY_MASK (0x1U << GRF_SOC_STATUS0_OTP_S_SBPI_BUSY_SHIFT) /* 0x02000000 */ +#define GRF_SOC_STATUS0_OTP_S_USER_BUSY_SHIFT (26U) +#define GRF_SOC_STATUS0_OTP_S_USER_BUSY_MASK (0x1U << GRF_SOC_STATUS0_OTP_S_USER_BUSY_SHIFT) /* 0x04000000 */ +#define GRF_SOC_STATUS0_WFI_HALTED_SHIFT (27U) +#define GRF_SOC_STATUS0_WFI_HALTED_MASK (0x1U << GRF_SOC_STATUS0_WFI_HALTED_SHIFT) /* 0x08000000 */ +/* RAM_CON */ +#define GRF_RAM_CON_OFFSET (0x405C0U) +#define GRF_RAM_CON_SPRA_RTSEL_SHIFT (0U) +#define GRF_RAM_CON_SPRA_RTSEL_MASK (0x3U << GRF_RAM_CON_SPRA_RTSEL_SHIFT) /* 0x00000003 */ +#define GRF_RAM_CON_SPRA_WTSEL_SHIFT (2U) +#define GRF_RAM_CON_SPRA_WTSEL_MASK (0x3U << GRF_RAM_CON_SPRA_WTSEL_SHIFT) /* 0x0000000C */ +#define GRF_RAM_CON_DPRA_PTSEL_SHIFT (4U) +#define GRF_RAM_CON_DPRA_PTSEL_MASK (0x3U << GRF_RAM_CON_DPRA_PTSEL_SHIFT) /* 0x00000030 */ +#define GRF_RAM_CON_DPRA_RTSEL_SHIFT (6U) +#define GRF_RAM_CON_DPRA_RTSEL_MASK (0x3U << GRF_RAM_CON_DPRA_RTSEL_SHIFT) /* 0x000000C0 */ +#define GRF_RAM_CON_DPRA_WTSEL_SHIFT (8U) +#define GRF_RAM_CON_DPRA_WTSEL_MASK (0x3U << GRF_RAM_CON_DPRA_WTSEL_SHIFT) /* 0x00000300 */ +#define GRF_RAM_CON_ROM_PTSEL_SHIFT (10U) +#define GRF_RAM_CON_ROM_PTSEL_MASK (0x3U << GRF_RAM_CON_ROM_PTSEL_SHIFT) /* 0x00000C00 */ +#define GRF_RAM_CON_ROM_RTSEL_SHIFT (12U) +#define GRF_RAM_CON_ROM_RTSEL_MASK (0x3U << GRF_RAM_CON_ROM_RTSEL_SHIFT) /* 0x00003000 */ +#define GRF_RAM_CON_ROM_TRB_SHIFT (14U) +#define GRF_RAM_CON_ROM_TRB_MASK (0x3U << GRF_RAM_CON_ROM_TRB_SHIFT) /* 0x0000C000 */ +/* CORE_RAM_CON */ +#define GRF_CORE_RAM_CON_OFFSET (0x405C4U) +#define GRF_CORE_RAM_CON_WTSEL_CPU_SHIFT (0U) +#define GRF_CORE_RAM_CON_WTSEL_CPU_MASK (0x3U << GRF_CORE_RAM_CON_WTSEL_CPU_SHIFT) /* 0x00000003 */ +#define GRF_CORE_RAM_CON_RTSEL_CPU_SHIFT (2U) +#define GRF_CORE_RAM_CON_RTSEL_CPU_MASK (0x3U << GRF_CORE_RAM_CON_RTSEL_CPU_SHIFT) /* 0x0000000C */ +#define GRF_CORE_RAM_CON_WTSEL_CPU_DSU_SHIFT (4U) +#define GRF_CORE_RAM_CON_WTSEL_CPU_DSU_MASK (0x3U << GRF_CORE_RAM_CON_WTSEL_CPU_DSU_SHIFT) /* 0x00000030 */ +#define GRF_CORE_RAM_CON_RTSEL_CPU_DSU_SHIFT (6U) +#define GRF_CORE_RAM_CON_RTSEL_CPU_DSU_MASK (0x3U << GRF_CORE_RAM_CON_RTSEL_CPU_DSU_SHIFT) /* 0x000000C0 */ +#define GRF_CORE_RAM_CON_SPRA_SLP_SHIFT (15U) +#define GRF_CORE_RAM_CON_SPRA_SLP_MASK (0x1U << GRF_CORE_RAM_CON_SPRA_SLP_SHIFT) /* 0x00008000 */ +/* TSADC_CON */ +#define GRF_TSADC_CON_OFFSET (0x40600U) +#define GRF_TSADC_CON_TSADC_ANA_REG0_SHIFT (0U) +#define GRF_TSADC_CON_TSADC_ANA_REG0_MASK (0x1U << GRF_TSADC_CON_TSADC_ANA_REG0_SHIFT) /* 0x00000001 */ +#define GRF_TSADC_CON_TSADC_ANA_REG1_SHIFT (1U) +#define GRF_TSADC_CON_TSADC_ANA_REG1_MASK (0x1U << GRF_TSADC_CON_TSADC_ANA_REG1_SHIFT) /* 0x00000002 */ +#define GRF_TSADC_CON_TSADC_ANA_REG2_SHIFT (2U) +#define GRF_TSADC_CON_TSADC_ANA_REG2_MASK (0x1U << GRF_TSADC_CON_TSADC_ANA_REG2_SHIFT) /* 0x00000004 */ +#define GRF_TSADC_CON_TSADC_ANA_REG3_SHIFT (3U) +#define GRF_TSADC_CON_TSADC_ANA_REG3_MASK (0x1U << GRF_TSADC_CON_TSADC_ANA_REG3_SHIFT) /* 0x00000008 */ +#define GRF_TSADC_CON_TSADC_ANA_REG4_SHIFT (4U) +#define GRF_TSADC_CON_TSADC_ANA_REG4_MASK (0x1U << GRF_TSADC_CON_TSADC_ANA_REG4_SHIFT) /* 0x00000010 */ +#define GRF_TSADC_CON_TSADC_ANA_REG5_SHIFT (5U) +#define GRF_TSADC_CON_TSADC_ANA_REG5_MASK (0x1U << GRF_TSADC_CON_TSADC_ANA_REG5_SHIFT) /* 0x00000020 */ +#define GRF_TSADC_CON_TSADC_ANA_REG6_SHIFT (6U) +#define GRF_TSADC_CON_TSADC_ANA_REG6_MASK (0x1U << GRF_TSADC_CON_TSADC_ANA_REG6_SHIFT) /* 0x00000040 */ +#define GRF_TSADC_CON_TSADC_TSEN_SHIFT (8U) +#define GRF_TSADC_CON_TSADC_TSEN_MASK (0x1U << GRF_TSADC_CON_TSADC_TSEN_SHIFT) /* 0x00000100 */ +/* SARADC_CON */ +#define GRF_SARADC_CON_OFFSET (0x40610U) +#define GRF_SARADC_CON_SARADC_ANA_REG_SHIFT (0U) +#define GRF_SARADC_CON_SARADC_ANA_REG_MASK (0xFFFFU << GRF_SARADC_CON_SARADC_ANA_REG_SHIFT) /* 0x0000FFFF */ +/* GPUPVTPLL_CON0 */ +#define GRF_GPUPVTPLL_CON0_OFFSET (0x40700U) +#define GRF_GPUPVTPLL_CON0_GPUPVTPLL_START_SHIFT (0U) +#define GRF_GPUPVTPLL_CON0_GPUPVTPLL_START_MASK (0x1U << GRF_GPUPVTPLL_CON0_GPUPVTPLL_START_SHIFT) /* 0x00000001 */ +#define GRF_GPUPVTPLL_CON0_GPUPVTPLL_OSC_EN_SHIFT (1U) +#define GRF_GPUPVTPLL_CON0_GPUPVTPLL_OSC_EN_MASK (0x1U << GRF_GPUPVTPLL_CON0_GPUPVTPLL_OSC_EN_SHIFT) /* 0x00000002 */ +#define GRF_GPUPVTPLL_CON0_GPUPVTPLL_OUT_POLAR_SHIFT (2U) +#define GRF_GPUPVTPLL_CON0_GPUPVTPLL_OUT_POLAR_MASK (0x1U << GRF_GPUPVTPLL_CON0_GPUPVTPLL_OUT_POLAR_SHIFT) /* 0x00000004 */ +#define GRF_GPUPVTPLL_CON0_GPU_PVTPLL_RING_LENGTH_SEL_SHIFT (3U) +#define GRF_GPUPVTPLL_CON0_GPU_PVTPLL_RING_LENGTH_SEL_MASK (0x1FU << GRF_GPUPVTPLL_CON0_GPU_PVTPLL_RING_LENGTH_SEL_SHIFT) /* 0x000000F8 */ +#define GRF_GPUPVTPLL_CON0_GPU_PVTPLL_OSC_SEL_SHIFT (8U) +#define GRF_GPUPVTPLL_CON0_GPU_PVTPLL_OSC_SEL_MASK (0x7U << GRF_GPUPVTPLL_CON0_GPU_PVTPLL_OSC_SEL_SHIFT) /* 0x00000700 */ +#define GRF_GPUPVTPLL_CON0_GPU_PVTPLL_CLK_DIV_CNT_SHIFT (11U) +#define GRF_GPUPVTPLL_CON0_GPU_PVTPLL_CLK_DIV_CNT_MASK (0xFU << GRF_GPUPVTPLL_CON0_GPU_PVTPLL_CLK_DIV_CNT_SHIFT) /* 0x00007800 */ +/* GPUPVTPLL_CON1 */ +#define GRF_GPUPVTPLL_CON1_OFFSET (0x40704U) +#define GRF_GPUPVTPLL_CON1_PVTPLL_CAL_CNT_SHIFT (0U) +#define GRF_GPUPVTPLL_CON1_PVTPLL_CAL_CNT_MASK (0xFFFFFFFFU << GRF_GPUPVTPLL_CON1_PVTPLL_CAL_CNT_SHIFT) /* 0xFFFFFFFF */ +/* GPUPVTPLL_CON2 */ +#define GRF_GPUPVTPLL_CON2_OFFSET (0x40708U) +#define GRF_GPUPVTPLL_CON2_GPU_PVTPLL_THRESHOLD_SHIFT (0U) +#define GRF_GPUPVTPLL_CON2_GPU_PVTPLL_THRESHOLD_MASK (0xFFFFFFFFU << GRF_GPUPVTPLL_CON2_GPU_PVTPLL_THRESHOLD_SHIFT) /* 0xFFFFFFFF */ +/* GPUPVTPLL_CON3 */ +#define GRF_GPUPVTPLL_CON3_OFFSET (0x4070CU) +#define GRF_GPUPVTPLL_CON3_GPU_PVTPLL_REF_CNT_SHIFT (0U) +#define GRF_GPUPVTPLL_CON3_GPU_PVTPLL_REF_CNT_MASK (0xFFFFFFFFU << GRF_GPUPVTPLL_CON3_GPU_PVTPLL_REF_CNT_SHIFT) /* 0xFFFFFFFF */ +/* NPUPVTPLL_CON0 */ +#define GRF_NPUPVTPLL_CON0_OFFSET (0x40740U) +#define GRF_NPUPVTPLL_CON0_GPUPVTPLL_START_SHIFT (0U) +#define GRF_NPUPVTPLL_CON0_GPUPVTPLL_START_MASK (0x1U << GRF_NPUPVTPLL_CON0_GPUPVTPLL_START_SHIFT) /* 0x00000001 */ +#define GRF_NPUPVTPLL_CON0_GPUPVTPLL_OSC_EN_SHIFT (1U) +#define GRF_NPUPVTPLL_CON0_GPUPVTPLL_OSC_EN_MASK (0x1U << GRF_NPUPVTPLL_CON0_GPUPVTPLL_OSC_EN_SHIFT) /* 0x00000002 */ +#define GRF_NPUPVTPLL_CON0_GPUPVTPLL_OUT_POLAR_SHIFT (2U) +#define GRF_NPUPVTPLL_CON0_GPUPVTPLL_OUT_POLAR_MASK (0x1U << GRF_NPUPVTPLL_CON0_GPUPVTPLL_OUT_POLAR_SHIFT) /* 0x00000004 */ +#define GRF_NPUPVTPLL_CON0_GPU_PVTPLL_RING_LENGTH_SEL_SHIFT (3U) +#define GRF_NPUPVTPLL_CON0_GPU_PVTPLL_RING_LENGTH_SEL_MASK (0x1FU << GRF_NPUPVTPLL_CON0_GPU_PVTPLL_RING_LENGTH_SEL_SHIFT) /* 0x000000F8 */ +#define GRF_NPUPVTPLL_CON0_GPU_PVTPLL_OSC_SEL_SHIFT (8U) +#define GRF_NPUPVTPLL_CON0_GPU_PVTPLL_OSC_SEL_MASK (0x7U << GRF_NPUPVTPLL_CON0_GPU_PVTPLL_OSC_SEL_SHIFT) /* 0x00000700 */ +#define GRF_NPUPVTPLL_CON0_GPU_PVTPLL_CLK_DIV_CNT_SHIFT (11U) +#define GRF_NPUPVTPLL_CON0_GPU_PVTPLL_CLK_DIV_CNT_MASK (0xFU << GRF_NPUPVTPLL_CON0_GPU_PVTPLL_CLK_DIV_CNT_SHIFT) /* 0x00007800 */ +/* NPUPVTPLL_CON1 */ +#define GRF_NPUPVTPLL_CON1_OFFSET (0x40744U) +#define GRF_NPUPVTPLL_CON1_PVTPLL_CAL_CNT_SHIFT (0U) +#define GRF_NPUPVTPLL_CON1_PVTPLL_CAL_CNT_MASK (0xFFFFFFFFU << GRF_NPUPVTPLL_CON1_PVTPLL_CAL_CNT_SHIFT) /* 0xFFFFFFFF */ +/* NPUPVTPLL_CON2 */ +#define GRF_NPUPVTPLL_CON2_OFFSET (0x40748U) +#define GRF_NPUPVTPLL_CON2_GPU_PVTPLL_THRESHOLD_SHIFT (0U) +#define GRF_NPUPVTPLL_CON2_GPU_PVTPLL_THRESHOLD_MASK (0xFFFFFFFFU << GRF_NPUPVTPLL_CON2_GPU_PVTPLL_THRESHOLD_SHIFT) /* 0xFFFFFFFF */ +/* NPUPVTPLL_CON3 */ +#define GRF_NPUPVTPLL_CON3_OFFSET (0x4074CU) +#define GRF_NPUPVTPLL_CON3_GPU_PVTPLL_REF_CNT_SHIFT (0U) +#define GRF_NPUPVTPLL_CON3_GPU_PVTPLL_REF_CNT_MASK (0xFFFFFFFFU << GRF_NPUPVTPLL_CON3_GPU_PVTPLL_REF_CNT_SHIFT) /* 0xFFFFFFFF */ +/* CHIP_ID */ +#define GRF_CHIP_ID_OFFSET (0x40800U) +#define GRF_CHIP_ID_CHIP_ID_SHIFT (0U) +#define GRF_CHIP_ID_CHIP_ID_MASK (0xFFFFFFFFU << GRF_CHIP_ID_CHIP_ID_SHIFT) /* 0xFFFFFFFF */ +/* GPIO1C5_DS */ +#define GRF_GPIO1C5_DS_OFFSET (0x40840U) +#define GRF_GPIO1C5_DS_GPIO1C5_DS_SHIFT (0U) +#define GRF_GPIO1C5_DS_GPIO1C5_DS_MASK (0x3FU << GRF_GPIO1C5_DS_GPIO1C5_DS_SHIFT) /* 0x0000003F */ +/* GPIO2A2_DS */ +#define GRF_GPIO2A2_DS_OFFSET (0x40844U) +#define GRF_GPIO2A2_DS_GPIO2A2_DS_SHIFT (0U) +#define GRF_GPIO2A2_DS_GPIO2A2_DS_MASK (0x3FU << GRF_GPIO2A2_DS_GPIO2A2_DS_SHIFT) /* 0x0000003F */ +/* GPIO2B0_DS */ +#define GRF_GPIO2B0_DS_OFFSET (0x40848U) +#define GRF_GPIO2B0_DS_GPIO2B0_DS_SHIFT (0U) +#define GRF_GPIO2B0_DS_GPIO2B0_DS_MASK (0x3FU << GRF_GPIO2B0_DS_GPIO2B0_DS_SHIFT) /* 0x0000003F */ +/* GPIO3A0_DS */ +#define GRF_GPIO3A0_DS_OFFSET (0x4084CU) +#define GRF_GPIO3A0_DS_GPIO3A0_DS_SHIFT (0U) +#define GRF_GPIO3A0_DS_GPIO3A0_DS_MASK (0x3FU << GRF_GPIO3A0_DS_GPIO3A0_DS_SHIFT) /* 0x0000003F */ +/* GPIO3A6_DS */ +#define GRF_GPIO3A6_DS_OFFSET (0x40850U) +#define GRF_GPIO3A6_DS_GPIO3A6_DS_SHIFT (0U) +#define GRF_GPIO3A6_DS_GPIO3A6_DS_MASK (0x3FU << GRF_GPIO3A6_DS_GPIO3A6_DS_SHIFT) /* 0x0000003F */ +/* GPIO4A0_DS */ +#define GRF_GPIO4A0_DS_OFFSET (0x40854U) +#define GRF_GPIO4A0_DS_GPIO4A0_DS_SHIFT (0U) +#define GRF_GPIO4A0_DS_GPIO4A0_DS_MASK (0x3FU << GRF_GPIO4A0_DS_GPIO4A0_DS_SHIFT) /* 0x0000003F */ +/* DMAC0_CON0 */ +#define GRF_DMAC0_CON0_OFFSET (0x40900U) +#define GRF_DMAC0_CON0_DMA0_IRQ_BOOT_NONSEC_SHIFT (0U) +#define GRF_DMAC0_CON0_DMA0_IRQ_BOOT_NONSEC_MASK (0xFFFFU << GRF_DMAC0_CON0_DMA0_IRQ_BOOT_NONSEC_SHIFT) /* 0x0000FFFF */ +/* DMAC0_CON1 */ +#define GRF_DMAC0_CON1_OFFSET (0x40904U) +#define GRF_DMAC0_CON1_DMA0_PERI_CH_NONSEC_15_0_SHIFT (0U) +#define GRF_DMAC0_CON1_DMA0_PERI_CH_NONSEC_15_0_MASK (0xFFFFU << GRF_DMAC0_CON1_DMA0_PERI_CH_NONSEC_15_0_SHIFT) /* 0x0000FFFF */ +/* DMAC0_CON2 */ +#define GRF_DMAC0_CON2_OFFSET (0x40908U) +#define GRF_DMAC0_CON2_DMA0_PERI_CH_NONSEC_31_16_SHIFT (0U) +#define GRF_DMAC0_CON2_DMA0_PERI_CH_NONSEC_31_16_MASK (0xFFFFU << GRF_DMAC0_CON2_DMA0_PERI_CH_NONSEC_31_16_SHIFT) /* 0x0000FFFF */ +/* DMAC0_CON3 */ +#define GRF_DMAC0_CON3_OFFSET (0x4090CU) +#define GRF_DMAC0_CON3_DMA0_MANAGER_BOOT_NONSEC_SHIFT (0U) +#define GRF_DMAC0_CON3_DMA0_MANAGER_BOOT_NONSEC_MASK (0x1U << GRF_DMAC0_CON3_DMA0_MANAGER_BOOT_NONSEC_SHIFT) /* 0x00000001 */ +/* DMAC0_CON4 */ +#define GRF_DMAC0_CON4_OFFSET (0x40910U) +#define GRF_DMAC0_CON4_GRF_TYPE_UART_0_TX_SHIFT (0U) +#define GRF_DMAC0_CON4_GRF_TYPE_UART_0_TX_MASK (0x3U << GRF_DMAC0_CON4_GRF_TYPE_UART_0_TX_SHIFT) /* 0x00000003 */ +#define GRF_DMAC0_CON4_GRF_TYPE_UART_0_RX_SHIFT (2U) +#define GRF_DMAC0_CON4_GRF_TYPE_UART_0_RX_MASK (0x3U << GRF_DMAC0_CON4_GRF_TYPE_UART_0_RX_SHIFT) /* 0x0000000C */ +#define GRF_DMAC0_CON4_GRF_TYPE_UART_1_TX_SHIFT (4U) +#define GRF_DMAC0_CON4_GRF_TYPE_UART_1_TX_MASK (0x3U << GRF_DMAC0_CON4_GRF_TYPE_UART_1_TX_SHIFT) /* 0x00000030 */ +#define GRF_DMAC0_CON4_GRF_TYPE_UART_1_RX_SHIFT (6U) +#define GRF_DMAC0_CON4_GRF_TYPE_UART_1_RX_MASK (0x3U << GRF_DMAC0_CON4_GRF_TYPE_UART_1_RX_SHIFT) /* 0x000000C0 */ +#define GRF_DMAC0_CON4_GRF_TYPE_UART_2_TX_SHIFT (8U) +#define GRF_DMAC0_CON4_GRF_TYPE_UART_2_TX_MASK (0x3U << GRF_DMAC0_CON4_GRF_TYPE_UART_2_TX_SHIFT) /* 0x00000300 */ +#define GRF_DMAC0_CON4_GRF_TYPE_UART_2_RX_SHIFT (10U) +#define GRF_DMAC0_CON4_GRF_TYPE_UART_2_RX_MASK (0x3U << GRF_DMAC0_CON4_GRF_TYPE_UART_2_RX_SHIFT) /* 0x00000C00 */ +#define GRF_DMAC0_CON4_GRF_TYPE_UART_3_TX_SHIFT (12U) +#define GRF_DMAC0_CON4_GRF_TYPE_UART_3_TX_MASK (0x3U << GRF_DMAC0_CON4_GRF_TYPE_UART_3_TX_SHIFT) /* 0x00003000 */ +#define GRF_DMAC0_CON4_GRF_TYPE_UART_3_RX_SHIFT (14U) +#define GRF_DMAC0_CON4_GRF_TYPE_UART_3_RX_MASK (0x3U << GRF_DMAC0_CON4_GRF_TYPE_UART_3_RX_SHIFT) /* 0x0000C000 */ +/* DMAC0_CON5 */ +#define GRF_DMAC0_CON5_OFFSET (0x40914U) +#define GRF_DMAC0_CON5_GRF_TYPE_UART_4_TX_SHIFT (0U) +#define GRF_DMAC0_CON5_GRF_TYPE_UART_4_TX_MASK (0x3U << GRF_DMAC0_CON5_GRF_TYPE_UART_4_TX_SHIFT) /* 0x00000003 */ +#define GRF_DMAC0_CON5_GRF_TYPE_UART_4_RX_SHIFT (2U) +#define GRF_DMAC0_CON5_GRF_TYPE_UART_4_RX_MASK (0x3U << GRF_DMAC0_CON5_GRF_TYPE_UART_4_RX_SHIFT) /* 0x0000000C */ +#define GRF_DMAC0_CON5_GRF_TYPE_UART_5_TX_SHIFT (4U) +#define GRF_DMAC0_CON5_GRF_TYPE_UART_5_TX_MASK (0x3U << GRF_DMAC0_CON5_GRF_TYPE_UART_5_TX_SHIFT) /* 0x00000030 */ +#define GRF_DMAC0_CON5_GRF_TYPE_UART_5_RX_SHIFT (6U) +#define GRF_DMAC0_CON5_GRF_TYPE_UART_5_RX_MASK (0x3U << GRF_DMAC0_CON5_GRF_TYPE_UART_5_RX_SHIFT) /* 0x000000C0 */ +#define GRF_DMAC0_CON5_GRF_TYPE_UART_6_TX_SHIFT (8U) +#define GRF_DMAC0_CON5_GRF_TYPE_UART_6_TX_MASK (0x3U << GRF_DMAC0_CON5_GRF_TYPE_UART_6_TX_SHIFT) /* 0x00000300 */ +#define GRF_DMAC0_CON5_GRF_TYPE_UART_6_RX_SHIFT (10U) +#define GRF_DMAC0_CON5_GRF_TYPE_UART_6_RX_MASK (0x3U << GRF_DMAC0_CON5_GRF_TYPE_UART_6_RX_SHIFT) /* 0x00000C00 */ +#define GRF_DMAC0_CON5_GRF_TYPE_UART_7_TX_SHIFT (12U) +#define GRF_DMAC0_CON5_GRF_TYPE_UART_7_TX_MASK (0x3U << GRF_DMAC0_CON5_GRF_TYPE_UART_7_TX_SHIFT) /* 0x00003000 */ +#define GRF_DMAC0_CON5_GRF_TYPE_UART_7_RX_SHIFT (14U) +#define GRF_DMAC0_CON5_GRF_TYPE_UART_7_RX_MASK (0x3U << GRF_DMAC0_CON5_GRF_TYPE_UART_7_RX_SHIFT) /* 0x0000C000 */ +/* DMAC0_CON6 */ +#define GRF_DMAC0_CON6_OFFSET (0x40918U) +#define GRF_DMAC0_CON6_GRF_TYPE_UART_8_TX_SHIFT (0U) +#define GRF_DMAC0_CON6_GRF_TYPE_UART_8_TX_MASK (0x3U << GRF_DMAC0_CON6_GRF_TYPE_UART_8_TX_SHIFT) /* 0x00000003 */ +#define GRF_DMAC0_CON6_GRF_TYPE_UART_8_RX_SHIFT (2U) +#define GRF_DMAC0_CON6_GRF_TYPE_UART_8_RX_MASK (0x3U << GRF_DMAC0_CON6_GRF_TYPE_UART_8_RX_SHIFT) /* 0x0000000C */ +#define GRF_DMAC0_CON6_GRF_TYPE_UART_9_TX_SHIFT (4U) +#define GRF_DMAC0_CON6_GRF_TYPE_UART_9_TX_MASK (0x3U << GRF_DMAC0_CON6_GRF_TYPE_UART_9_TX_SHIFT) /* 0x00000030 */ +#define GRF_DMAC0_CON6_GRF_TYPE_UART_9_RX_SHIFT (6U) +#define GRF_DMAC0_CON6_GRF_TYPE_UART_9_RX_MASK (0x3U << GRF_DMAC0_CON6_GRF_TYPE_UART_9_RX_SHIFT) /* 0x000000C0 */ +#define GRF_DMAC0_CON6_GRF_TYPE_SPI0_TX_SHIFT (8U) +#define GRF_DMAC0_CON6_GRF_TYPE_SPI0_TX_MASK (0x3U << GRF_DMAC0_CON6_GRF_TYPE_SPI0_TX_SHIFT) /* 0x00000300 */ +#define GRF_DMAC0_CON6_GRF_TYPE_SPI0_RX_SHIFT (10U) +#define GRF_DMAC0_CON6_GRF_TYPE_SPI0_RX_MASK (0x3U << GRF_DMAC0_CON6_GRF_TYPE_SPI0_RX_SHIFT) /* 0x00000C00 */ +#define GRF_DMAC0_CON6_GRF_TYPE_SPI1_TX_SHIFT (12U) +#define GRF_DMAC0_CON6_GRF_TYPE_SPI1_TX_MASK (0x3U << GRF_DMAC0_CON6_GRF_TYPE_SPI1_TX_SHIFT) /* 0x00003000 */ +#define GRF_DMAC0_CON6_GRF_TYPE_SPI1_RX_SHIFT (14U) +#define GRF_DMAC0_CON6_GRF_TYPE_SPI1_RX_MASK (0x3U << GRF_DMAC0_CON6_GRF_TYPE_SPI1_RX_SHIFT) /* 0x0000C000 */ +/* DMAC0_CON7 */ +#define GRF_DMAC0_CON7_OFFSET (0x4091CU) +#define GRF_DMAC0_CON7_GRF_TYPE_SPI2_TX_SHIFT (0U) +#define GRF_DMAC0_CON7_GRF_TYPE_SPI2_TX_MASK (0x3U << GRF_DMAC0_CON7_GRF_TYPE_SPI2_TX_SHIFT) /* 0x00000003 */ +#define GRF_DMAC0_CON7_GRF_TYPE_SPI2_RX_SHIFT (2U) +#define GRF_DMAC0_CON7_GRF_TYPE_SPI2_RX_MASK (0x3U << GRF_DMAC0_CON7_GRF_TYPE_SPI2_RX_SHIFT) /* 0x0000000C */ +#define GRF_DMAC0_CON7_GRF_TYPE_SPI3_TX_SHIFT (4U) +#define GRF_DMAC0_CON7_GRF_TYPE_SPI3_TX_MASK (0x3U << GRF_DMAC0_CON7_GRF_TYPE_SPI3_TX_SHIFT) /* 0x00000030 */ +#define GRF_DMAC0_CON7_GRF_TYPE_SPI3_RX_SHIFT (6U) +#define GRF_DMAC0_CON7_GRF_TYPE_SPI3_RX_MASK (0x3U << GRF_DMAC0_CON7_GRF_TYPE_SPI3_RX_SHIFT) /* 0x000000C0 */ +#define GRF_DMAC0_CON7_GRF_TYPE_PWM0_TX_SHIFT (8U) +#define GRF_DMAC0_CON7_GRF_TYPE_PWM0_TX_MASK (0x3U << GRF_DMAC0_CON7_GRF_TYPE_PWM0_TX_SHIFT) /* 0x00000300 */ +#define GRF_DMAC0_CON7_GRF_TYPE_PWM1_TX_SHIFT (10U) +#define GRF_DMAC0_CON7_GRF_TYPE_PWM1_TX_MASK (0x3U << GRF_DMAC0_CON7_GRF_TYPE_PWM1_TX_SHIFT) /* 0x00000C00 */ +#define GRF_DMAC0_CON7_GRF_TYPE_PWM2_TX_SHIFT (12U) +#define GRF_DMAC0_CON7_GRF_TYPE_PWM2_TX_MASK (0x3U << GRF_DMAC0_CON7_GRF_TYPE_PWM2_TX_SHIFT) /* 0x00003000 */ +#define GRF_DMAC0_CON7_GRF_TYPE_PWM3_TX_SHIFT (14U) +#define GRF_DMAC0_CON7_GRF_TYPE_PWM3_TX_MASK (0x3U << GRF_DMAC0_CON7_GRF_TYPE_PWM3_TX_SHIFT) /* 0x0000C000 */ +/* DMAC0_CON8 */ +#define GRF_DMAC0_CON8_OFFSET (0x40920U) +#define GRF_DMAC0_CON8_GRF_DMA0_REQ_MODIFY_DIS_SHIFT (0U) +#define GRF_DMAC0_CON8_GRF_DMA0_REQ_MODIFY_DIS_MASK (0xFFFFU << GRF_DMAC0_CON8_GRF_DMA0_REQ_MODIFY_DIS_SHIFT) /* 0x0000FFFF */ +/* DMAC0_CON9 */ +#define GRF_DMAC0_CON9_OFFSET (0x40924U) +#define GRF_DMAC0_CON9_GRF_DMA0_REQ_MODIFY_DIS_SHIFT (0U) +#define GRF_DMAC0_CON9_GRF_DMA0_REQ_MODIFY_DIS_MASK (0xFFFFU << GRF_DMAC0_CON9_GRF_DMA0_REQ_MODIFY_DIS_SHIFT) /* 0x0000FFFF */ +/* DMAC1_CON0 */ +#define GRF_DMAC1_CON0_OFFSET (0x40940U) +#define GRF_DMAC1_CON0_DMA1_IRQ_BOOT_NONSEC_SHIFT (0U) +#define GRF_DMAC1_CON0_DMA1_IRQ_BOOT_NONSEC_MASK (0xFFFFU << GRF_DMAC1_CON0_DMA1_IRQ_BOOT_NONSEC_SHIFT) /* 0x0000FFFF */ +/* DMAC1_CON1 */ +#define GRF_DMAC1_CON1_OFFSET (0x40944U) +#define GRF_DMAC1_CON1_DMA1_PERI_CH_NONSEC_15_0_SHIFT (0U) +#define GRF_DMAC1_CON1_DMA1_PERI_CH_NONSEC_15_0_MASK (0xFFFFU << GRF_DMAC1_CON1_DMA1_PERI_CH_NONSEC_15_0_SHIFT) /* 0x0000FFFF */ +/* DMAC1_CON2 */ +#define GRF_DMAC1_CON2_OFFSET (0x40948U) +#define GRF_DMAC1_CON2_DMA1_PERI_CH_NONSEC_31_16_SHIFT (0U) +#define GRF_DMAC1_CON2_DMA1_PERI_CH_NONSEC_31_16_MASK (0xFFFFU << GRF_DMAC1_CON2_DMA1_PERI_CH_NONSEC_31_16_SHIFT) /* 0x0000FFFF */ +/* DMAC1_CON3 */ +#define GRF_DMAC1_CON3_OFFSET (0x4094CU) +#define GRF_DMAC1_CON3_DMA1_MANAGER_BOOT_NONSEC_SHIFT (0U) +#define GRF_DMAC1_CON3_DMA1_MANAGER_BOOT_NONSEC_MASK (0x1U << GRF_DMAC1_CON3_DMA1_MANAGER_BOOT_NONSEC_SHIFT) /* 0x00000001 */ +/* DMAC1_CON4 */ +#define GRF_DMAC1_CON4_OFFSET (0x40950U) +#define GRF_DMAC1_CON4_GRF_TYPE_I2S0_RX_SHIFT (0U) +#define GRF_DMAC1_CON4_GRF_TYPE_I2S0_RX_MASK (0x3U << GRF_DMAC1_CON4_GRF_TYPE_I2S0_RX_SHIFT) /* 0x00000003 */ +#define GRF_DMAC1_CON4_GRF_TYPE_SPDIF_SHIFT (2U) +#define GRF_DMAC1_CON4_GRF_TYPE_SPDIF_MASK (0x3U << GRF_DMAC1_CON4_GRF_TYPE_SPDIF_SHIFT) /* 0x0000000C */ +#define GRF_DMAC1_CON4_GRF_TYPE_I2S1_TX_SHIFT (4U) +#define GRF_DMAC1_CON4_GRF_TYPE_I2S1_TX_MASK (0x3U << GRF_DMAC1_CON4_GRF_TYPE_I2S1_TX_SHIFT) /* 0x00000030 */ +#define GRF_DMAC1_CON4_GRF_TYPE_I2S1_RX_SHIFT (6U) +#define GRF_DMAC1_CON4_GRF_TYPE_I2S1_RX_MASK (0x3U << GRF_DMAC1_CON4_GRF_TYPE_I2S1_RX_SHIFT) /* 0x000000C0 */ +#define GRF_DMAC1_CON4_GRF_TYPE_I2S2_TX_SHIFT (8U) +#define GRF_DMAC1_CON4_GRF_TYPE_I2S2_TX_MASK (0x3U << GRF_DMAC1_CON4_GRF_TYPE_I2S2_TX_SHIFT) /* 0x00000300 */ +#define GRF_DMAC1_CON4_GRF_TYPE_I2S2_RX_SHIFT (10U) +#define GRF_DMAC1_CON4_GRF_TYPE_I2S2_RX_MASK (0x3U << GRF_DMAC1_CON4_GRF_TYPE_I2S2_RX_SHIFT) /* 0x00000C00 */ +#define GRF_DMAC1_CON4_GRF_TYPE_I2S3_TX_SHIFT (12U) +#define GRF_DMAC1_CON4_GRF_TYPE_I2S3_TX_MASK (0x3U << GRF_DMAC1_CON4_GRF_TYPE_I2S3_TX_SHIFT) /* 0x00003000 */ +#define GRF_DMAC1_CON4_GRF_TYPE_I2S3_RX_SHIFT (14U) +#define GRF_DMAC1_CON4_GRF_TYPE_I2S3_RX_MASK (0x3U << GRF_DMAC1_CON4_GRF_TYPE_I2S3_RX_SHIFT) /* 0x0000C000 */ +/* DMAC1_CON5 */ +#define GRF_DMAC1_CON5_OFFSET (0x40954U) +#define GRF_DMAC1_CON5_GRF_TYPE_CAN1_RX_SHIFT (0U) +#define GRF_DMAC1_CON5_GRF_TYPE_CAN1_RX_MASK (0x3U << GRF_DMAC1_CON5_GRF_TYPE_CAN1_RX_SHIFT) /* 0x00000003 */ +/* DMAC1_CON6 */ +#define GRF_DMAC1_CON6_OFFSET (0x40958U) +#define GRF_DMAC1_CON6_GRF_TYPE_AUDPWM_SHIFT (0U) +#define GRF_DMAC1_CON6_GRF_TYPE_AUDPWM_MASK (0x3U << GRF_DMAC1_CON6_GRF_TYPE_AUDPWM_SHIFT) /* 0x00000003 */ +#define GRF_DMAC1_CON6_GRF_TYPE_PDM_SHIFT (2U) +#define GRF_DMAC1_CON6_GRF_TYPE_PDM_MASK (0x3U << GRF_DMAC1_CON6_GRF_TYPE_PDM_SHIFT) /* 0x0000000C */ +#define GRF_DMAC1_CON6_GRF_TYPE_SDMMC_BUFFER_SHIFT (4U) +#define GRF_DMAC1_CON6_GRF_TYPE_SDMMC_BUFFER_MASK (0x3U << GRF_DMAC1_CON6_GRF_TYPE_SDMMC_BUFFER_SHIFT) /* 0x00000030 */ +#define GRF_DMAC1_CON6_GRF_TYPE_CAN0_TX_SHIFT (6U) +#define GRF_DMAC1_CON6_GRF_TYPE_CAN0_TX_MASK (0x3U << GRF_DMAC1_CON6_GRF_TYPE_CAN0_TX_SHIFT) /* 0x000000C0 */ +#define GRF_DMAC1_CON6_GRF_TYPE_CAN0_RX_SHIFT (8U) +#define GRF_DMAC1_CON6_GRF_TYPE_CAN0_RX_MASK (0x3U << GRF_DMAC1_CON6_GRF_TYPE_CAN0_RX_SHIFT) /* 0x00000300 */ +#define GRF_DMAC1_CON6_GRF_TYPE_CAN1_TX_SHIFT (10U) +#define GRF_DMAC1_CON6_GRF_TYPE_CAN1_TX_MASK (0x3U << GRF_DMAC1_CON6_GRF_TYPE_CAN1_TX_SHIFT) /* 0x00000C00 */ +#define GRF_DMAC1_CON6_GRF_TYPE_CAN1_RX_SHIFT (12U) +#define GRF_DMAC1_CON6_GRF_TYPE_CAN1_RX_MASK (0x3U << GRF_DMAC1_CON6_GRF_TYPE_CAN1_RX_SHIFT) /* 0x00003000 */ +#define GRF_DMAC1_CON6_GRF_TYPE_CAN2_TX_SHIFT (14U) +#define GRF_DMAC1_CON6_GRF_TYPE_CAN2_TX_MASK (0x3U << GRF_DMAC1_CON6_GRF_TYPE_CAN2_TX_SHIFT) /* 0x0000C000 */ +/* DMAC1_CON7 */ +#define GRF_DMAC1_CON7_OFFSET (0x4095CU) +#define GRF_DMAC1_CON7_GRF_TYPE_CAN2_RX_SHIFT (0U) +#define GRF_DMAC1_CON7_GRF_TYPE_CAN2_RX_MASK (0x3U << GRF_DMAC1_CON7_GRF_TYPE_CAN2_RX_SHIFT) /* 0x00000003 */ +/* DMAC1_CON8 */ +#define GRF_DMAC1_CON8_OFFSET (0x40960U) +#define GRF_DMAC1_CON8_GRF_DMA1_REQ_MODIFY_DIS_SHIFT (0U) +#define GRF_DMAC1_CON8_GRF_DMA1_REQ_MODIFY_DIS_MASK (0xFFFFU << GRF_DMAC1_CON8_GRF_DMA1_REQ_MODIFY_DIS_SHIFT) /* 0x0000FFFF */ +/* DMAC1_CON9 */ +#define GRF_DMAC1_CON9_OFFSET (0x40964U) +#define GRF_DMAC1_CON9_GRF_DMA1_REQ_MODIFY_DIS_SHIFT (0U) +#define GRF_DMAC1_CON9_GRF_DMA1_REQ_MODIFY_DIS_MASK (0xFFFFU << GRF_DMAC1_CON9_GRF_DMA1_REQ_MODIFY_DIS_SHIFT) /* 0x0000FFFF */ +/*****************************************PMUCRU*****************************************/ +/* PPLL_CON0 */ +#define PMUCRU_PPLL_CON0_OFFSET (0x0U) +#define PMUCRU_PPLL_CON0_FBDIV_SHIFT (0U) +#define PMUCRU_PPLL_CON0_FBDIV_MASK (0xFFFU << PMUCRU_PPLL_CON0_FBDIV_SHIFT) /* 0x00000FFF */ +#define PMUCRU_PPLL_CON0_POSTDIV1_SHIFT (12U) +#define PMUCRU_PPLL_CON0_POSTDIV1_MASK (0x7U << PMUCRU_PPLL_CON0_POSTDIV1_SHIFT) /* 0x00007000 */ +#define PMUCRU_PPLL_CON0_BYPASS_SHIFT (15U) +#define PMUCRU_PPLL_CON0_BYPASS_MASK (0x1U << PMUCRU_PPLL_CON0_BYPASS_SHIFT) /* 0x00008000 */ +/* PPLL_CON1 */ +#define PMUCRU_PPLL_CON1_OFFSET (0x4U) +#define PMUCRU_PPLL_CON1_REFDIV_SHIFT (0U) +#define PMUCRU_PPLL_CON1_REFDIV_MASK (0x3FU << PMUCRU_PPLL_CON1_REFDIV_SHIFT) /* 0x0000003F */ +#define PMUCRU_PPLL_CON1_POSTDIV2_SHIFT (6U) +#define PMUCRU_PPLL_CON1_POSTDIV2_MASK (0x7U << PMUCRU_PPLL_CON1_POSTDIV2_SHIFT) /* 0x000001C0 */ +#define PMUCRU_PPLL_CON1_PLL_LOCK_SHIFT (10U) +#define PMUCRU_PPLL_CON1_PLL_LOCK_MASK (0x1U << PMUCRU_PPLL_CON1_PLL_LOCK_SHIFT) /* 0x00000400 */ +#define PMUCRU_PPLL_CON1_DSMPD_SHIFT (12U) +#define PMUCRU_PPLL_CON1_DSMPD_MASK (0x1U << PMUCRU_PPLL_CON1_DSMPD_SHIFT) /* 0x00001000 */ +#define PMUCRU_PPLL_CON1_PLLPD0_SHIFT (13U) +#define PMUCRU_PPLL_CON1_PLLPD0_MASK (0x1U << PMUCRU_PPLL_CON1_PLLPD0_SHIFT) /* 0x00002000 */ +#define PMUCRU_PPLL_CON1_PLLPD1_SHIFT (14U) +#define PMUCRU_PPLL_CON1_PLLPD1_MASK (0x1U << PMUCRU_PPLL_CON1_PLLPD1_SHIFT) /* 0x00004000 */ +#define PMUCRU_PPLL_CON1_PLLPDSEL_SHIFT (15U) +#define PMUCRU_PPLL_CON1_PLLPDSEL_MASK (0x1U << PMUCRU_PPLL_CON1_PLLPDSEL_SHIFT) /* 0x00008000 */ +/* PPLL_CON2 */ +#define PMUCRU_PPLL_CON2_OFFSET (0x8U) +#define PMUCRU_PPLL_CON2_FRACDIV_SHIFT (0U) +#define PMUCRU_PPLL_CON2_FRACDIV_MASK (0xFFFFFFU << PMUCRU_PPLL_CON2_FRACDIV_SHIFT) /* 0x00FFFFFF */ +#define PMUCRU_PPLL_CON2_DACPD_SHIFT (24U) +#define PMUCRU_PPLL_CON2_DACPD_MASK (0x1U << PMUCRU_PPLL_CON2_DACPD_SHIFT) /* 0x01000000 */ +#define PMUCRU_PPLL_CON2_FOUTPOSTDIVPD_SHIFT (25U) +#define PMUCRU_PPLL_CON2_FOUTPOSTDIVPD_MASK (0x1U << PMUCRU_PPLL_CON2_FOUTPOSTDIVPD_SHIFT) /* 0x02000000 */ +#define PMUCRU_PPLL_CON2_FOUTVCOPD_SHIFT (26U) +#define PMUCRU_PPLL_CON2_FOUTVCOPD_MASK (0x1U << PMUCRU_PPLL_CON2_FOUTVCOPD_SHIFT) /* 0x04000000 */ +#define PMUCRU_PPLL_CON2_FOUT4PHASEPD_SHIFT (27U) +#define PMUCRU_PPLL_CON2_FOUT4PHASEPD_MASK (0x1U << PMUCRU_PPLL_CON2_FOUT4PHASEPD_SHIFT) /* 0x08000000 */ +/* PPLL_CON3 */ +#define PMUCRU_PPLL_CON3_OFFSET (0xCU) +#define PMUCRU_PPLL_CON3_SSMOD_BP_SHIFT (0U) +#define PMUCRU_PPLL_CON3_SSMOD_BP_MASK (0x1U << PMUCRU_PPLL_CON3_SSMOD_BP_SHIFT) /* 0x00000001 */ +#define PMUCRU_PPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT (1U) +#define PMUCRU_PPLL_CON3_SSMOD_DISABLE_SSCG_MASK (0x1U << PMUCRU_PPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT) /* 0x00000002 */ +#define PMUCRU_PPLL_CON3_SSMOD_RESET_SHIFT (2U) +#define PMUCRU_PPLL_CON3_SSMOD_RESET_MASK (0x1U << PMUCRU_PPLL_CON3_SSMOD_RESET_SHIFT) /* 0x00000004 */ +#define PMUCRU_PPLL_CON3_SSMOD_DOWNSPREAD_SHIFT (3U) +#define PMUCRU_PPLL_CON3_SSMOD_DOWNSPREAD_MASK (0x1U << PMUCRU_PPLL_CON3_SSMOD_DOWNSPREAD_SHIFT) /* 0x00000008 */ +#define PMUCRU_PPLL_CON3_SSMOD_DIVVAL_SHIFT (4U) +#define PMUCRU_PPLL_CON3_SSMOD_DIVVAL_MASK (0xFU << PMUCRU_PPLL_CON3_SSMOD_DIVVAL_SHIFT) /* 0x000000F0 */ +#define PMUCRU_PPLL_CON3_SSMOD_SPREAD_SHIFT (8U) +#define PMUCRU_PPLL_CON3_SSMOD_SPREAD_MASK (0x1FU << PMUCRU_PPLL_CON3_SSMOD_SPREAD_SHIFT) /* 0x00001F00 */ +/* PPLL_CON4 */ +#define PMUCRU_PPLL_CON4_OFFSET (0x10U) +#define PMUCRU_PPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT (0U) +#define PMUCRU_PPLL_CON4_SSMOD_SEL_EXT_WAVE_MASK (0x1U << PMUCRU_PPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT) /* 0x00000001 */ +#define PMUCRU_PPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT (8U) +#define PMUCRU_PPLL_CON4_SSMOD_EXT_MAXADDR_MASK (0xFFU << PMUCRU_PPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT) /* 0x0000FF00 */ +/* HPLL_CON0 */ +#define PMUCRU_HPLL_CON0_OFFSET (0x40U) +#define PMUCRU_HPLL_CON0_FBDIV_SHIFT (0U) +#define PMUCRU_HPLL_CON0_FBDIV_MASK (0xFFFU << PMUCRU_HPLL_CON0_FBDIV_SHIFT) /* 0x00000FFF */ +#define PMUCRU_HPLL_CON0_POSTDIV1_SHIFT (12U) +#define PMUCRU_HPLL_CON0_POSTDIV1_MASK (0x7U << PMUCRU_HPLL_CON0_POSTDIV1_SHIFT) /* 0x00007000 */ +#define PMUCRU_HPLL_CON0_BYPASS_SHIFT (15U) +#define PMUCRU_HPLL_CON0_BYPASS_MASK (0x1U << PMUCRU_HPLL_CON0_BYPASS_SHIFT) /* 0x00008000 */ +/* HPLL_CON1 */ +#define PMUCRU_HPLL_CON1_OFFSET (0x44U) +#define PMUCRU_HPLL_CON1_REFDIV_SHIFT (0U) +#define PMUCRU_HPLL_CON1_REFDIV_MASK (0x3FU << PMUCRU_HPLL_CON1_REFDIV_SHIFT) /* 0x0000003F */ +#define PMUCRU_HPLL_CON1_POSTDIV2_SHIFT (6U) +#define PMUCRU_HPLL_CON1_POSTDIV2_MASK (0x7U << PMUCRU_HPLL_CON1_POSTDIV2_SHIFT) /* 0x000001C0 */ +#define PMUCRU_HPLL_CON1_PLL_LOCK_SHIFT (10U) +#define PMUCRU_HPLL_CON1_PLL_LOCK_MASK (0x1U << PMUCRU_HPLL_CON1_PLL_LOCK_SHIFT) /* 0x00000400 */ +#define PMUCRU_HPLL_CON1_DSMPD_SHIFT (12U) +#define PMUCRU_HPLL_CON1_DSMPD_MASK (0x1U << PMUCRU_HPLL_CON1_DSMPD_SHIFT) /* 0x00001000 */ +#define PMUCRU_HPLL_CON1_PLLPD0_SHIFT (13U) +#define PMUCRU_HPLL_CON1_PLLPD0_MASK (0x1U << PMUCRU_HPLL_CON1_PLLPD0_SHIFT) /* 0x00002000 */ +#define PMUCRU_HPLL_CON1_PLLPD1_SHIFT (14U) +#define PMUCRU_HPLL_CON1_PLLPD1_MASK (0x1U << PMUCRU_HPLL_CON1_PLLPD1_SHIFT) /* 0x00004000 */ +#define PMUCRU_HPLL_CON1_PLLPDSEL_SHIFT (15U) +#define PMUCRU_HPLL_CON1_PLLPDSEL_MASK (0x1U << PMUCRU_HPLL_CON1_PLLPDSEL_SHIFT) /* 0x00008000 */ +/* HPLL_CON2 */ +#define PMUCRU_HPLL_CON2_OFFSET (0x48U) +#define PMUCRU_HPLL_CON2_FRACDIV_SHIFT (0U) +#define PMUCRU_HPLL_CON2_FRACDIV_MASK (0xFFFFFFU << PMUCRU_HPLL_CON2_FRACDIV_SHIFT) /* 0x00FFFFFF */ +#define PMUCRU_HPLL_CON2_DACPD_SHIFT (24U) +#define PMUCRU_HPLL_CON2_DACPD_MASK (0x1U << PMUCRU_HPLL_CON2_DACPD_SHIFT) /* 0x01000000 */ +#define PMUCRU_HPLL_CON2_FOUTPOSTDIVPD_SHIFT (25U) +#define PMUCRU_HPLL_CON2_FOUTPOSTDIVPD_MASK (0x1U << PMUCRU_HPLL_CON2_FOUTPOSTDIVPD_SHIFT) /* 0x02000000 */ +#define PMUCRU_HPLL_CON2_FOUTVCOPD_SHIFT (26U) +#define PMUCRU_HPLL_CON2_FOUTVCOPD_MASK (0x1U << PMUCRU_HPLL_CON2_FOUTVCOPD_SHIFT) /* 0x04000000 */ +#define PMUCRU_HPLL_CON2_FOUT4PHASEPD_SHIFT (27U) +#define PMUCRU_HPLL_CON2_FOUT4PHASEPD_MASK (0x1U << PMUCRU_HPLL_CON2_FOUT4PHASEPD_SHIFT) /* 0x08000000 */ +/* HPLL_CON3 */ +#define PMUCRU_HPLL_CON3_OFFSET (0x4CU) +#define PMUCRU_HPLL_CON3_SSMOD_BP_SHIFT (0U) +#define PMUCRU_HPLL_CON3_SSMOD_BP_MASK (0x1U << PMUCRU_HPLL_CON3_SSMOD_BP_SHIFT) /* 0x00000001 */ +#define PMUCRU_HPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT (1U) +#define PMUCRU_HPLL_CON3_SSMOD_DISABLE_SSCG_MASK (0x1U << PMUCRU_HPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT) /* 0x00000002 */ +#define PMUCRU_HPLL_CON3_SSMOD_RESET_SHIFT (2U) +#define PMUCRU_HPLL_CON3_SSMOD_RESET_MASK (0x1U << PMUCRU_HPLL_CON3_SSMOD_RESET_SHIFT) /* 0x00000004 */ +#define PMUCRU_HPLL_CON3_SSMOD_DOWNSPREAD_SHIFT (3U) +#define PMUCRU_HPLL_CON3_SSMOD_DOWNSPREAD_MASK (0x1U << PMUCRU_HPLL_CON3_SSMOD_DOWNSPREAD_SHIFT) /* 0x00000008 */ +#define PMUCRU_HPLL_CON3_SSMOD_DIVVAL_SHIFT (4U) +#define PMUCRU_HPLL_CON3_SSMOD_DIVVAL_MASK (0xFU << PMUCRU_HPLL_CON3_SSMOD_DIVVAL_SHIFT) /* 0x000000F0 */ +#define PMUCRU_HPLL_CON3_SSMOD_SPREAD_SHIFT (8U) +#define PMUCRU_HPLL_CON3_SSMOD_SPREAD_MASK (0x1FU << PMUCRU_HPLL_CON3_SSMOD_SPREAD_SHIFT) /* 0x00001F00 */ +/* HPLL_CON4 */ +#define PMUCRU_HPLL_CON4_OFFSET (0x50U) +#define PMUCRU_HPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT (0U) +#define PMUCRU_HPLL_CON4_SSMOD_SEL_EXT_WAVE_MASK (0x1U << PMUCRU_HPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT) /* 0x00000001 */ +#define PMUCRU_HPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT (8U) +#define PMUCRU_HPLL_CON4_SSMOD_EXT_MAXADDR_MASK (0xFFU << PMUCRU_HPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT) /* 0x0000FF00 */ +/* MODE_CON00 */ +#define PMUCRU_MODE_CON00_OFFSET (0x80U) +#define PMUCRU_MODE_CON00_CLK_PPLL_MODE_SHIFT (0U) +#define PMUCRU_MODE_CON00_CLK_PPLL_MODE_MASK (0x3U << PMUCRU_MODE_CON00_CLK_PPLL_MODE_SHIFT) /* 0x00000003 */ +#define PMUCRU_MODE_CON00_CLK_HPLL_MODE_SHIFT (2U) +#define PMUCRU_MODE_CON00_CLK_HPLL_MODE_MASK (0x3U << PMUCRU_MODE_CON00_CLK_HPLL_MODE_SHIFT) /* 0x0000000C */ +/* PMUCLKSEL_CON00 */ +#define PMUCRU_PMUCLKSEL_CON00_OFFSET (0x100U) +#define PMUCRU_PMUCLKSEL_CON00_XIN_OSC0_DIV_DIV_SHIFT (0U) +#define PMUCRU_PMUCLKSEL_CON00_XIN_OSC0_DIV_DIV_MASK (0x1FU << PMUCRU_PMUCLKSEL_CON00_XIN_OSC0_DIV_DIV_SHIFT) /* 0x0000001F */ +#define PMUCRU_PMUCLKSEL_CON00_CLK_RTC_32K_SEL_SHIFT (6U) +#define PMUCRU_PMUCLKSEL_CON00_CLK_RTC_32K_SEL_MASK (0x3U << PMUCRU_PMUCLKSEL_CON00_CLK_RTC_32K_SEL_SHIFT) /* 0x000000C0 */ +/* PMUCLKSEL_CON01 */ +#define PMUCRU_PMUCLKSEL_CON01_OFFSET (0x104U) +#define PMUCRU_PMUCLKSEL_CON01_CLK_OSC0_DIV32K_DIV_SHIFT (0U) +#define PMUCRU_PMUCLKSEL_CON01_CLK_OSC0_DIV32K_DIV_MASK (0xFFFFFFFFU << PMUCRU_PMUCLKSEL_CON01_CLK_OSC0_DIV32K_DIV_SHIFT) /* 0xFFFFFFFF */ +/* PMUCLKSEL_CON02 */ +#define PMUCRU_PMUCLKSEL_CON02_OFFSET (0x108U) +#define PMUCRU_PMUCLKSEL_CON02_PCLK_PDPMU_PRE_DIV_SHIFT (0U) +#define PMUCRU_PMUCLKSEL_CON02_PCLK_PDPMU_PRE_DIV_MASK (0x1FU << PMUCRU_PMUCLKSEL_CON02_PCLK_PDPMU_PRE_DIV_SHIFT) /* 0x0000001F */ +#define PMUCRU_PMUCLKSEL_CON02_CLK_PDPMU_MUX_SEL_SHIFT (15U) +#define PMUCRU_PMUCLKSEL_CON02_CLK_PDPMU_MUX_SEL_MASK (0x1U << PMUCRU_PMUCLKSEL_CON02_CLK_PDPMU_MUX_SEL_SHIFT) /* 0x00008000 */ +/* PMUCLKSEL_CON03 */ +#define PMUCRU_PMUCLKSEL_CON03_OFFSET (0x10CU) +#define PMUCRU_PMUCLKSEL_CON03_CLK_I2C0_DIV_SHIFT (0U) +#define PMUCRU_PMUCLKSEL_CON03_CLK_I2C0_DIV_MASK (0x7FU << PMUCRU_PMUCLKSEL_CON03_CLK_I2C0_DIV_SHIFT) /* 0x0000007F */ +/* PMUCLKSEL_CON04 */ +#define PMUCRU_PMUCLKSEL_CON04_OFFSET (0x110U) +#define PMUCRU_PMUCLKSEL_CON04_SCLK_UART0_DIV_DIV_SHIFT (0U) +#define PMUCRU_PMUCLKSEL_CON04_SCLK_UART0_DIV_DIV_MASK (0x7FU << PMUCRU_PMUCLKSEL_CON04_SCLK_UART0_DIV_DIV_SHIFT) /* 0x0000007F */ +#define PMUCRU_PMUCLKSEL_CON04_SCLK_UART0_DIV_SEL_SHIFT (8U) +#define PMUCRU_PMUCLKSEL_CON04_SCLK_UART0_DIV_SEL_MASK (0x3U << PMUCRU_PMUCLKSEL_CON04_SCLK_UART0_DIV_SEL_SHIFT) /* 0x00000300 */ +#define PMUCRU_PMUCLKSEL_CON04_SCLK_UART0_SEL_SHIFT (10U) +#define PMUCRU_PMUCLKSEL_CON04_SCLK_UART0_SEL_MASK (0x3U << PMUCRU_PMUCLKSEL_CON04_SCLK_UART0_SEL_SHIFT) /* 0x00000C00 */ +/* PMUCLKSEL_CON05 */ +#define PMUCRU_PMUCLKSEL_CON05_OFFSET (0x114U) +#define PMUCRU_PMUCLKSEL_CON05_SCLK_UART0_FRACDIV_DIV_SHIFT (0U) +#define PMUCRU_PMUCLKSEL_CON05_SCLK_UART0_FRACDIV_DIV_MASK (0xFFFFFFFFU << PMUCRU_PMUCLKSEL_CON05_SCLK_UART0_FRACDIV_DIV_SHIFT) /* 0xFFFFFFFF */ +/* PMUCLKSEL_CON06 */ +#define PMUCRU_PMUCLKSEL_CON06_OFFSET (0x118U) +#define PMUCRU_PMUCLKSEL_CON06_CLK_PWM0_DIV_SHIFT (0U) +#define PMUCRU_PMUCLKSEL_CON06_CLK_PWM0_DIV_MASK (0x7FU << PMUCRU_PMUCLKSEL_CON06_CLK_PWM0_DIV_SHIFT) /* 0x0000007F */ +#define PMUCRU_PMUCLKSEL_CON06_CLK_PWM0_SEL_SHIFT (7U) +#define PMUCRU_PMUCLKSEL_CON06_CLK_PWM0_SEL_MASK (0x1U << PMUCRU_PMUCLKSEL_CON06_CLK_PWM0_SEL_SHIFT) /* 0x00000080 */ +#define PMUCRU_PMUCLKSEL_CON06_DBCLK_GPIO0_SEL_SHIFT (15U) +#define PMUCRU_PMUCLKSEL_CON06_DBCLK_GPIO0_SEL_MASK (0x1U << PMUCRU_PMUCLKSEL_CON06_DBCLK_GPIO0_SEL_SHIFT) /* 0x00008000 */ +/* PMUCLKSEL_CON07 */ +#define PMUCRU_PMUCLKSEL_CON07_OFFSET (0x11CU) +#define PMUCRU_PMUCLKSEL_CON07_CLK_REF24M_DIV_SHIFT (0U) +#define PMUCRU_PMUCLKSEL_CON07_CLK_REF24M_DIV_MASK (0x3FU << PMUCRU_PMUCLKSEL_CON07_CLK_REF24M_DIV_SHIFT) /* 0x0000003F */ +/* PMUCLKSEL_CON08 */ +#define PMUCRU_PMUCLKSEL_CON08_OFFSET (0x120U) +#define PMUCRU_PMUCLKSEL_CON08_CLK_USBPHY0_REF_SEL_SHIFT (0U) +#define PMUCRU_PMUCLKSEL_CON08_CLK_USBPHY0_REF_SEL_MASK (0x1U << PMUCRU_PMUCLKSEL_CON08_CLK_USBPHY0_REF_SEL_SHIFT) /* 0x00000001 */ +#define PMUCRU_PMUCLKSEL_CON08_CLK_USBPHY1_REF_SEL_SHIFT (1U) +#define PMUCRU_PMUCLKSEL_CON08_CLK_USBPHY1_REF_SEL_MASK (0x1U << PMUCRU_PMUCLKSEL_CON08_CLK_USBPHY1_REF_SEL_SHIFT) /* 0x00000002 */ +#define PMUCRU_PMUCLKSEL_CON08_CLK_MIPIDSIPHY0_REF_SEL_SHIFT (2U) +#define PMUCRU_PMUCLKSEL_CON08_CLK_MIPIDSIPHY0_REF_SEL_MASK (0x1U << PMUCRU_PMUCLKSEL_CON08_CLK_MIPIDSIPHY0_REF_SEL_SHIFT) /* 0x00000004 */ +#define PMUCRU_PMUCLKSEL_CON08_CLK_MIPIDSIPHY1_REF_SEL_SHIFT (3U) +#define PMUCRU_PMUCLKSEL_CON08_CLK_MIPIDSIPHY1_REF_SEL_MASK (0x1U << PMUCRU_PMUCLKSEL_CON08_CLK_MIPIDSIPHY1_REF_SEL_SHIFT) /* 0x00000008 */ +#define PMUCRU_PMUCLKSEL_CON08_CLK_HDMIPHY_REF_SEL_SHIFT (7U) +#define PMUCRU_PMUCLKSEL_CON08_CLK_HDMIPHY_REF_SEL_MASK (0x1U << PMUCRU_PMUCLKSEL_CON08_CLK_HDMIPHY_REF_SEL_SHIFT) /* 0x00000080 */ +#define PMUCRU_PMUCLKSEL_CON08_CLK_WIFI_DIV_DIV_SHIFT (8U) +#define PMUCRU_PMUCLKSEL_CON08_CLK_WIFI_DIV_DIV_MASK (0x3FU << PMUCRU_PMUCLKSEL_CON08_CLK_WIFI_DIV_DIV_SHIFT) /* 0x00003F00 */ +#define PMUCRU_PMUCLKSEL_CON08_CLK_WIFI_SEL_SHIFT (15U) +#define PMUCRU_PMUCLKSEL_CON08_CLK_WIFI_SEL_MASK (0x1U << PMUCRU_PMUCLKSEL_CON08_CLK_WIFI_SEL_SHIFT) /* 0x00008000 */ +/* PMUCLKSEL_CON09 */ +#define PMUCRU_PMUCLKSEL_CON09_OFFSET (0x124U) +#define PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY0_DIV_DIV_SHIFT (0U) +#define PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY0_DIV_DIV_MASK (0x7U << PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY0_DIV_DIV_SHIFT) /* 0x00000007 */ +#define PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY0_REF_SEL_SHIFT (3U) +#define PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY0_REF_SEL_MASK (0x1U << PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY0_REF_SEL_SHIFT) /* 0x00000008 */ +#define PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY1_DIV_DIV_SHIFT (4U) +#define PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY1_DIV_DIV_MASK (0x7U << PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY1_DIV_DIV_SHIFT) /* 0x00000070 */ +#define PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY1_REF_SEL_SHIFT (7U) +#define PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY1_REF_SEL_MASK (0x1U << PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY1_REF_SEL_SHIFT) /* 0x00000080 */ +#define PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY2_DIV_DIV_SHIFT (8U) +#define PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY2_DIV_DIV_MASK (0x7U << PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY2_DIV_DIV_SHIFT) /* 0x00000700 */ +#define PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY2_REF_SEL_SHIFT (11U) +#define PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY2_REF_SEL_MASK (0x1U << PMUCRU_PMUCLKSEL_CON09_CLK_PCIEPHY2_REF_SEL_SHIFT) /* 0x00000800 */ +/* PMUGATE_CON00 */ +#define PMUCRU_PMUGATE_CON00_OFFSET (0x180U) +#define PMUCRU_PMUGATE_CON00_XIN_OSC0_DIV_EN_SHIFT (0U) +#define PMUCRU_PMUGATE_CON00_XIN_OSC0_DIV_EN_MASK (0x1U << PMUCRU_PMUGATE_CON00_XIN_OSC0_DIV_EN_SHIFT) /* 0x00000001 */ +#define PMUCRU_PMUGATE_CON00_CLK_OSC0_DIV32K_EN_SHIFT (1U) +#define PMUCRU_PMUGATE_CON00_CLK_OSC0_DIV32K_EN_MASK (0x1U << PMUCRU_PMUGATE_CON00_CLK_OSC0_DIV32K_EN_SHIFT) /* 0x00000002 */ +#define PMUCRU_PMUGATE_CON00_PCLK_PDPMU_EN_SHIFT (2U) +#define PMUCRU_PMUGATE_CON00_PCLK_PDPMU_EN_MASK (0x1U << PMUCRU_PMUGATE_CON00_PCLK_PDPMU_EN_SHIFT) /* 0x00000004 */ +#define PMUCRU_PMUGATE_CON00_PCLK_PDPMU_NIU_EN_SHIFT (3U) +#define PMUCRU_PMUGATE_CON00_PCLK_PDPMU_NIU_EN_MASK (0x1U << PMUCRU_PMUGATE_CON00_PCLK_PDPMU_NIU_EN_SHIFT) /* 0x00000008 */ +#define PMUCRU_PMUGATE_CON00_PCLK_PMUCRU_EN_SHIFT (4U) +#define PMUCRU_PMUGATE_CON00_PCLK_PMUCRU_EN_MASK (0x1U << PMUCRU_PMUGATE_CON00_PCLK_PMUCRU_EN_SHIFT) /* 0x00000010 */ +#define PMUCRU_PMUGATE_CON00_PCLK_PMUGRF_EN_SHIFT (5U) +#define PMUCRU_PMUGATE_CON00_PCLK_PMUGRF_EN_MASK (0x1U << PMUCRU_PMUGATE_CON00_PCLK_PMUGRF_EN_SHIFT) /* 0x00000020 */ +#define PMUCRU_PMUGATE_CON00_PCLK_PMU_EN_SHIFT (6U) +#define PMUCRU_PMUGATE_CON00_PCLK_PMU_EN_MASK (0x1U << PMUCRU_PMUGATE_CON00_PCLK_PMU_EN_SHIFT) /* 0x00000040 */ +#define PMUCRU_PMUGATE_CON00_CLK_PMU_EN_SHIFT (7U) +#define PMUCRU_PMUGATE_CON00_CLK_PMU_EN_MASK (0x1U << PMUCRU_PMUGATE_CON00_CLK_PMU_EN_SHIFT) /* 0x00000080 */ +/* PMUGATE_CON01 */ +#define PMUCRU_PMUGATE_CON01_OFFSET (0x184U) +#define PMUCRU_PMUGATE_CON01_PCLK_I2C0_EN_SHIFT (0U) +#define PMUCRU_PMUGATE_CON01_PCLK_I2C0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_PCLK_I2C0_EN_SHIFT) /* 0x00000001 */ +#define PMUCRU_PMUGATE_CON01_CLK_I2C0_EN_SHIFT (1U) +#define PMUCRU_PMUGATE_CON01_CLK_I2C0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_CLK_I2C0_EN_SHIFT) /* 0x00000002 */ +#define PMUCRU_PMUGATE_CON01_PCLK_UART0_EN_SHIFT (2U) +#define PMUCRU_PMUGATE_CON01_PCLK_UART0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_PCLK_UART0_EN_SHIFT) /* 0x00000004 */ +#define PMUCRU_PMUGATE_CON01_SCLK_UART0_DIV_EN_SHIFT (3U) +#define PMUCRU_PMUGATE_CON01_SCLK_UART0_DIV_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_SCLK_UART0_DIV_EN_SHIFT) /* 0x00000008 */ +#define PMUCRU_PMUGATE_CON01_SCLK_UART0_FRACDIV_EN_SHIFT (4U) +#define PMUCRU_PMUGATE_CON01_SCLK_UART0_FRACDIV_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_SCLK_UART0_FRACDIV_EN_SHIFT) /* 0x00000010 */ +#define PMUCRU_PMUGATE_CON01_SCLK_UART0_EN_SHIFT (5U) +#define PMUCRU_PMUGATE_CON01_SCLK_UART0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_SCLK_UART0_EN_SHIFT) /* 0x00000020 */ +#define PMUCRU_PMUGATE_CON01_PCLK_PWM0_EN_SHIFT (6U) +#define PMUCRU_PMUGATE_CON01_PCLK_PWM0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_PCLK_PWM0_EN_SHIFT) /* 0x00000040 */ +#define PMUCRU_PMUGATE_CON01_CLK_PWM0_EN_SHIFT (7U) +#define PMUCRU_PMUGATE_CON01_CLK_PWM0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_CLK_PWM0_EN_SHIFT) /* 0x00000080 */ +#define PMUCRU_PMUGATE_CON01_CLK_CAPTURE_PWM0_EN_SHIFT (8U) +#define PMUCRU_PMUGATE_CON01_CLK_CAPTURE_PWM0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_CLK_CAPTURE_PWM0_EN_SHIFT) /* 0x00000100 */ +#define PMUCRU_PMUGATE_CON01_PCLK_GPIO0_EN_SHIFT (9U) +#define PMUCRU_PMUGATE_CON01_PCLK_GPIO0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_PCLK_GPIO0_EN_SHIFT) /* 0x00000200 */ +#define PMUCRU_PMUGATE_CON01_DBCLK_GPIO0_EN_SHIFT (10U) +#define PMUCRU_PMUGATE_CON01_DBCLK_GPIO0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_DBCLK_GPIO0_EN_SHIFT) /* 0x00000400 */ +#define PMUCRU_PMUGATE_CON01_PCLK_PMUPVTM_EN_SHIFT (11U) +#define PMUCRU_PMUGATE_CON01_PCLK_PMUPVTM_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_PCLK_PMUPVTM_EN_SHIFT) /* 0x00000800 */ +#define PMUCRU_PMUGATE_CON01_CLK_PMUPVTM_EN_SHIFT (12U) +#define PMUCRU_PMUGATE_CON01_CLK_PMUPVTM_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_CLK_PMUPVTM_EN_SHIFT) /* 0x00001000 */ +#define PMUCRU_PMUGATE_CON01_CLK_CORE_PMUPVTM_EN_SHIFT (13U) +#define PMUCRU_PMUGATE_CON01_CLK_CORE_PMUPVTM_EN_MASK (0x1U << PMUCRU_PMUGATE_CON01_CLK_CORE_PMUPVTM_EN_SHIFT) /* 0x00002000 */ +/* PMUGATE_CON02 */ +#define PMUCRU_PMUGATE_CON02_OFFSET (0x188U) +#define PMUCRU_PMUGATE_CON02_CLK_REF24M_EN_SHIFT (0U) +#define PMUCRU_PMUGATE_CON02_CLK_REF24M_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_CLK_REF24M_EN_SHIFT) /* 0x00000001 */ +#define PMUCRU_PMUGATE_CON02_XIN_OSC0_USBPHY0_EN_SHIFT (1U) +#define PMUCRU_PMUGATE_CON02_XIN_OSC0_USBPHY0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_XIN_OSC0_USBPHY0_EN_SHIFT) /* 0x00000002 */ +#define PMUCRU_PMUGATE_CON02_XIN_OSC0_USBPHY1_EN_SHIFT (2U) +#define PMUCRU_PMUGATE_CON02_XIN_OSC0_USBPHY1_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_XIN_OSC0_USBPHY1_EN_SHIFT) /* 0x00000004 */ +#define PMUCRU_PMUGATE_CON02_XIN_OSC0_MIPIDSIPHY0_EN_SHIFT (3U) +#define PMUCRU_PMUGATE_CON02_XIN_OSC0_MIPIDSIPHY0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_XIN_OSC0_MIPIDSIPHY0_EN_SHIFT) /* 0x00000008 */ +#define PMUCRU_PMUGATE_CON02_XIN_OSC0_MIPIDSIPHY1_EN_SHIFT (4U) +#define PMUCRU_PMUGATE_CON02_XIN_OSC0_MIPIDSIPHY1_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_XIN_OSC0_MIPIDSIPHY1_EN_SHIFT) /* 0x00000010 */ +#define PMUCRU_PMUGATE_CON02_CLK_WIFI_DIV_EN_SHIFT (5U) +#define PMUCRU_PMUGATE_CON02_CLK_WIFI_DIV_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_CLK_WIFI_DIV_EN_SHIFT) /* 0x00000020 */ +#define PMUCRU_PMUGATE_CON02_CLK_WIFI_OSC0_EN_SHIFT (6U) +#define PMUCRU_PMUGATE_CON02_CLK_WIFI_OSC0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_CLK_WIFI_OSC0_EN_SHIFT) /* 0x00000040 */ +#define PMUCRU_PMUGATE_CON02_CLK_PCIEPHY0_DIV_EN_SHIFT (7U) +#define PMUCRU_PMUGATE_CON02_CLK_PCIEPHY0_DIV_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_CLK_PCIEPHY0_DIV_EN_SHIFT) /* 0x00000080 */ +#define PMUCRU_PMUGATE_CON02_CLK_PCIEPHY0_OSC0_EN_SHIFT (8U) +#define PMUCRU_PMUGATE_CON02_CLK_PCIEPHY0_OSC0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_CLK_PCIEPHY0_OSC0_EN_SHIFT) /* 0x00000100 */ +#define PMUCRU_PMUGATE_CON02_CLK_PCIEPHY1_DIV_EN_SHIFT (9U) +#define PMUCRU_PMUGATE_CON02_CLK_PCIEPHY1_DIV_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_CLK_PCIEPHY1_DIV_EN_SHIFT) /* 0x00000200 */ +#define PMUCRU_PMUGATE_CON02_CLK_PCIEPHY1_OSC0_EN_SHIFT (10U) +#define PMUCRU_PMUGATE_CON02_CLK_PCIEPHY1_OSC0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_CLK_PCIEPHY1_OSC0_EN_SHIFT) /* 0x00000400 */ +#define PMUCRU_PMUGATE_CON02_CLK_PCIEPHY2_DIV_EN_SHIFT (11U) +#define PMUCRU_PMUGATE_CON02_CLK_PCIEPHY2_DIV_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_CLK_PCIEPHY2_DIV_EN_SHIFT) /* 0x00000800 */ +#define PMUCRU_PMUGATE_CON02_CLK_PCIEPHY2_OSC0_EN_SHIFT (12U) +#define PMUCRU_PMUGATE_CON02_CLK_PCIEPHY2_OSC0_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_CLK_PCIEPHY2_OSC0_EN_SHIFT) /* 0x00001000 */ +#define PMUCRU_PMUGATE_CON02_CLK_PCIE30PHY_REF_M_EN_SHIFT (13U) +#define PMUCRU_PMUGATE_CON02_CLK_PCIE30PHY_REF_M_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_CLK_PCIE30PHY_REF_M_EN_SHIFT) /* 0x00002000 */ +#define PMUCRU_PMUGATE_CON02_CLK_PCIE30PHY_REF_N_EN_SHIFT (14U) +#define PMUCRU_PMUGATE_CON02_CLK_PCIE30PHY_REF_N_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_CLK_PCIE30PHY_REF_N_EN_SHIFT) /* 0x00004000 */ +#define PMUCRU_PMUGATE_CON02_XIN_OSC0_EDPPHY_EN_SHIFT (15U) +#define PMUCRU_PMUGATE_CON02_XIN_OSC0_EDPPHY_EN_MASK (0x1U << PMUCRU_PMUGATE_CON02_XIN_OSC0_EDPPHY_EN_SHIFT) /* 0x00008000 */ +/* PMUSOFTRST_CON00 */ +#define PMUCRU_PMUSOFTRST_CON00_OFFSET (0x200U) +#define PMUCRU_PMUSOFTRST_CON00_PRESETN_PDPMU_NIU_SHIFT (0U) +#define PMUCRU_PMUSOFTRST_CON00_PRESETN_PDPMU_NIU_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_PRESETN_PDPMU_NIU_SHIFT) /* 0x00000001 */ +#define PMUCRU_PMUSOFTRST_CON00_PRESETN_PMUCRU_SHIFT (1U) +#define PMUCRU_PMUSOFTRST_CON00_PRESETN_PMUCRU_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_PRESETN_PMUCRU_SHIFT) /* 0x00000002 */ +#define PMUCRU_PMUSOFTRST_CON00_PRESETN_PMUGRF_SHIFT (2U) +#define PMUCRU_PMUSOFTRST_CON00_PRESETN_PMUGRF_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_PRESETN_PMUGRF_SHIFT) /* 0x00000004 */ +#define PMUCRU_PMUSOFTRST_CON00_PRESETN_I2C0_SHIFT (3U) +#define PMUCRU_PMUSOFTRST_CON00_PRESETN_I2C0_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_PRESETN_I2C0_SHIFT) /* 0x00000008 */ +#define PMUCRU_PMUSOFTRST_CON00_RESETN_I2C0_SHIFT (4U) +#define PMUCRU_PMUSOFTRST_CON00_RESETN_I2C0_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_RESETN_I2C0_SHIFT) /* 0x00000010 */ +#define PMUCRU_PMUSOFTRST_CON00_PRESETN_UART0_SHIFT (5U) +#define PMUCRU_PMUSOFTRST_CON00_PRESETN_UART0_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_PRESETN_UART0_SHIFT) /* 0x00000020 */ +#define PMUCRU_PMUSOFTRST_CON00_SRESETN_UART0_SHIFT (6U) +#define PMUCRU_PMUSOFTRST_CON00_SRESETN_UART0_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_SRESETN_UART0_SHIFT) /* 0x00000040 */ +#define PMUCRU_PMUSOFTRST_CON00_PRESETN_PWM0_SHIFT (7U) +#define PMUCRU_PMUSOFTRST_CON00_PRESETN_PWM0_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_PRESETN_PWM0_SHIFT) /* 0x00000080 */ +#define PMUCRU_PMUSOFTRST_CON00_RESETN_PWM0_SHIFT (8U) +#define PMUCRU_PMUSOFTRST_CON00_RESETN_PWM0_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_RESETN_PWM0_SHIFT) /* 0x00000100 */ +#define PMUCRU_PMUSOFTRST_CON00_PRESETN_GPIO0_SHIFT (9U) +#define PMUCRU_PMUSOFTRST_CON00_PRESETN_GPIO0_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_PRESETN_GPIO0_SHIFT) /* 0x00000200 */ +#define PMUCRU_PMUSOFTRST_CON00_DBRESETN_GPIO0_SHIFT (10U) +#define PMUCRU_PMUSOFTRST_CON00_DBRESETN_GPIO0_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_DBRESETN_GPIO0_SHIFT) /* 0x00000400 */ +#define PMUCRU_PMUSOFTRST_CON00_PRESETN_PMUPVTM_SHIFT (11U) +#define PMUCRU_PMUSOFTRST_CON00_PRESETN_PMUPVTM_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_PRESETN_PMUPVTM_SHIFT) /* 0x00000800 */ +#define PMUCRU_PMUSOFTRST_CON00_RESETN_PMUPVTM_SHIFT (12U) +#define PMUCRU_PMUSOFTRST_CON00_RESETN_PMUPVTM_MASK (0x1U << PMUCRU_PMUSOFTRST_CON00_RESETN_PMUPVTM_SHIFT) /* 0x00001000 */ +/*****************************************TIMER******************************************/ +/* LOAD_COUNT0 */ +#define TIMER_LOAD_COUNT0_OFFSET (0x0U) +#define TIMER_LOAD_COUNT0_COUNT0_SHIFT (0U) +#define TIMER_LOAD_COUNT0_COUNT0_MASK (0xFFFFFFFFU << TIMER_LOAD_COUNT0_COUNT0_SHIFT) /* 0xFFFFFFFF */ +/* LOAD_COUNT1 */ +#define TIMER_LOAD_COUNT1_OFFSET (0x4U) +#define TIMER_LOAD_COUNT1_COUNT1_SHIFT (0U) +#define TIMER_LOAD_COUNT1_COUNT1_MASK (0xFFFFFFFFU << TIMER_LOAD_COUNT1_COUNT1_SHIFT) /* 0xFFFFFFFF */ +/* CURRENT_VALUE0 */ +#define TIMER_CURRENT_VALUE0_OFFSET (0x8U) +#define TIMER_CURRENT_VALUE0 (0x0U) +#define TIMER_CURRENT_VALUE0_CURRENT_VALUE0_SHIFT (0U) +#define TIMER_CURRENT_VALUE0_CURRENT_VALUE0_MASK (0xFFFFFFFFU << TIMER_CURRENT_VALUE0_CURRENT_VALUE0_SHIFT) /* 0xFFFFFFFF */ +/* CURRENT_VALUE1 */ +#define TIMER_CURRENT_VALUE1_OFFSET (0xCU) +#define TIMER_CURRENT_VALUE1 (0x0U) +#define TIMER_CURRENT_VALUE1_CURRENT_VALUE1_SHIFT (0U) +#define TIMER_CURRENT_VALUE1_CURRENT_VALUE1_MASK (0xFFFFFFFFU << TIMER_CURRENT_VALUE1_CURRENT_VALUE1_SHIFT) /* 0xFFFFFFFF */ +/* CONTROLREG */ +#define TIMER_CONTROLREG_OFFSET (0x10U) +#define TIMER_CONTROLREG_TIMER_ENABLE_SHIFT (0U) +#define TIMER_CONTROLREG_TIMER_ENABLE_MASK (0x1U << TIMER_CONTROLREG_TIMER_ENABLE_SHIFT) /* 0x00000001 */ +#define TIMER_CONTROLREG_TIMER_MODE_SHIFT (1U) +#define TIMER_CONTROLREG_TIMER_MODE_MASK (0x1U << TIMER_CONTROLREG_TIMER_MODE_SHIFT) /* 0x00000002 */ +#define TIMER_CONTROLREG_TIMER_INT_MASK_SHIFT (2U) +#define TIMER_CONTROLREG_TIMER_INT_MASK_MASK (0x1U << TIMER_CONTROLREG_TIMER_INT_MASK_SHIFT) /* 0x00000004 */ +/* INTSTATUS */ +#define TIMER_INTSTATUS_OFFSET (0x18U) +#define TIMER_INTSTATUS_INT_PD_SHIFT (0U) +#define TIMER_INTSTATUS_INT_PD_MASK (0x1U << TIMER_INTSTATUS_INT_PD_SHIFT) /* 0x00000001 */ +/******************************************CRU*******************************************/ +/* APLL_CON0 */ +#define CRU_APLL_CON0_OFFSET (0x0U) +#define CRU_APLL_CON0_FBDIV_SHIFT (0U) +#define CRU_APLL_CON0_FBDIV_MASK (0xFFFU << CRU_APLL_CON0_FBDIV_SHIFT) /* 0x00000FFF */ +#define CRU_APLL_CON0_POSTDIV1_SHIFT (12U) +#define CRU_APLL_CON0_POSTDIV1_MASK (0x7U << CRU_APLL_CON0_POSTDIV1_SHIFT) /* 0x00007000 */ +#define CRU_APLL_CON0_BYPASS_SHIFT (15U) +#define CRU_APLL_CON0_BYPASS_MASK (0x1U << CRU_APLL_CON0_BYPASS_SHIFT) /* 0x00008000 */ +/* APLL_CON1 */ +#define CRU_APLL_CON1_OFFSET (0x4U) +#define CRU_APLL_CON1_REFDIV_SHIFT (0U) +#define CRU_APLL_CON1_REFDIV_MASK (0x3FU << CRU_APLL_CON1_REFDIV_SHIFT) /* 0x0000003F */ +#define CRU_APLL_CON1_POSTDIV2_SHIFT (6U) +#define CRU_APLL_CON1_POSTDIV2_MASK (0x7U << CRU_APLL_CON1_POSTDIV2_SHIFT) /* 0x000001C0 */ +#define CRU_APLL_CON1_PLL_LOCK_SHIFT (10U) +#define CRU_APLL_CON1_PLL_LOCK_MASK (0x1U << CRU_APLL_CON1_PLL_LOCK_SHIFT) /* 0x00000400 */ +#define CRU_APLL_CON1_DSMPD_SHIFT (12U) +#define CRU_APLL_CON1_DSMPD_MASK (0x1U << CRU_APLL_CON1_DSMPD_SHIFT) /* 0x00001000 */ +#define CRU_APLL_CON1_PLLPD0_SHIFT (13U) +#define CRU_APLL_CON1_PLLPD0_MASK (0x1U << CRU_APLL_CON1_PLLPD0_SHIFT) /* 0x00002000 */ +#define CRU_APLL_CON1_PLLPD1_SHIFT (14U) +#define CRU_APLL_CON1_PLLPD1_MASK (0x1U << CRU_APLL_CON1_PLLPD1_SHIFT) /* 0x00004000 */ +#define CRU_APLL_CON1_PLLPDSEL_SHIFT (15U) +#define CRU_APLL_CON1_PLLPDSEL_MASK (0x1U << CRU_APLL_CON1_PLLPDSEL_SHIFT) /* 0x00008000 */ +/* APLL_CON2 */ +#define CRU_APLL_CON2_OFFSET (0x8U) +#define CRU_APLL_CON2_FRACDIV_SHIFT (0U) +#define CRU_APLL_CON2_FRACDIV_MASK (0xFFFFFFU << CRU_APLL_CON2_FRACDIV_SHIFT) /* 0x00FFFFFF */ +#define CRU_APLL_CON2_DACPD_SHIFT (24U) +#define CRU_APLL_CON2_DACPD_MASK (0x1U << CRU_APLL_CON2_DACPD_SHIFT) /* 0x01000000 */ +#define CRU_APLL_CON2_FOUTPOSTDIVPD_SHIFT (25U) +#define CRU_APLL_CON2_FOUTPOSTDIVPD_MASK (0x1U << CRU_APLL_CON2_FOUTPOSTDIVPD_SHIFT) /* 0x02000000 */ +#define CRU_APLL_CON2_FOUTVCOPD_SHIFT (26U) +#define CRU_APLL_CON2_FOUTVCOPD_MASK (0x1U << CRU_APLL_CON2_FOUTVCOPD_SHIFT) /* 0x04000000 */ +#define CRU_APLL_CON2_FOUT4PHASEPD_SHIFT (27U) +#define CRU_APLL_CON2_FOUT4PHASEPD_MASK (0x1U << CRU_APLL_CON2_FOUT4PHASEPD_SHIFT) /* 0x08000000 */ +/* APLL_CON3 */ +#define CRU_APLL_CON3_OFFSET (0xCU) +#define CRU_APLL_CON3_SSMOD_BP_SHIFT (0U) +#define CRU_APLL_CON3_SSMOD_BP_MASK (0x1U << CRU_APLL_CON3_SSMOD_BP_SHIFT) /* 0x00000001 */ +#define CRU_APLL_CON3_SSMOD_DISABLE_SSCG_SHIFT (1U) +#define CRU_APLL_CON3_SSMOD_DISABLE_SSCG_MASK (0x1U << CRU_APLL_CON3_SSMOD_DISABLE_SSCG_SHIFT) /* 0x00000002 */ +#define CRU_APLL_CON3_SSMOD_RESET_SHIFT (2U) +#define CRU_APLL_CON3_SSMOD_RESET_MASK (0x1U << CRU_APLL_CON3_SSMOD_RESET_SHIFT) /* 0x00000004 */ +#define CRU_APLL_CON3_SSMOD_DOWNSPREAD_SHIFT (3U) +#define CRU_APLL_CON3_SSMOD_DOWNSPREAD_MASK (0x1U << CRU_APLL_CON3_SSMOD_DOWNSPREAD_SHIFT) /* 0x00000008 */ +#define CRU_APLL_CON3_SSMOD_DIVVAL_SHIFT (4U) +#define CRU_APLL_CON3_SSMOD_DIVVAL_MASK (0xFU << CRU_APLL_CON3_SSMOD_DIVVAL_SHIFT) /* 0x000000F0 */ +#define CRU_APLL_CON3_SSMOD_SPREAD_SHIFT (8U) +#define CRU_APLL_CON3_SSMOD_SPREAD_MASK (0x1FU << CRU_APLL_CON3_SSMOD_SPREAD_SHIFT) /* 0x00001F00 */ +/* APLL_CON4 */ +#define CRU_APLL_CON4_OFFSET (0x10U) +#define CRU_APLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT (0U) +#define CRU_APLL_CON4_SSMOD_SEL_EXT_WAVE_MASK (0x1U << CRU_APLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT) /* 0x00000001 */ +#define CRU_APLL_CON4_SSMOD_EXT_MAXADDR_SHIFT (8U) +#define CRU_APLL_CON4_SSMOD_EXT_MAXADDR_MASK (0xFFU << CRU_APLL_CON4_SSMOD_EXT_MAXADDR_SHIFT) /* 0x0000FF00 */ +/* DPLL_CON0 */ +#define CRU_DPLL_CON0_OFFSET (0x20U) +#define CRU_DPLL_CON0_FBDIV_SHIFT (0U) +#define CRU_DPLL_CON0_FBDIV_MASK (0xFFFU << CRU_DPLL_CON0_FBDIV_SHIFT) /* 0x00000FFF */ +#define CRU_DPLL_CON0_POSTDIV1_SHIFT (12U) +#define CRU_DPLL_CON0_POSTDIV1_MASK (0x7U << CRU_DPLL_CON0_POSTDIV1_SHIFT) /* 0x00007000 */ +#define CRU_DPLL_CON0_BYPASS_SHIFT (15U) +#define CRU_DPLL_CON0_BYPASS_MASK (0x1U << CRU_DPLL_CON0_BYPASS_SHIFT) /* 0x00008000 */ +/* DPLL_CON1 */ +#define CRU_DPLL_CON1_OFFSET (0x24U) +#define CRU_DPLL_CON1_REFDIV_SHIFT (0U) +#define CRU_DPLL_CON1_REFDIV_MASK (0x3FU << CRU_DPLL_CON1_REFDIV_SHIFT) /* 0x0000003F */ +#define CRU_DPLL_CON1_POSTDIV2_SHIFT (6U) +#define CRU_DPLL_CON1_POSTDIV2_MASK (0x7U << CRU_DPLL_CON1_POSTDIV2_SHIFT) /* 0x000001C0 */ +#define CRU_DPLL_CON1_PLL_LOCK_SHIFT (10U) +#define CRU_DPLL_CON1_PLL_LOCK_MASK (0x1U << CRU_DPLL_CON1_PLL_LOCK_SHIFT) /* 0x00000400 */ +#define CRU_DPLL_CON1_DSMPD_SHIFT (12U) +#define CRU_DPLL_CON1_DSMPD_MASK (0x1U << CRU_DPLL_CON1_DSMPD_SHIFT) /* 0x00001000 */ +#define CRU_DPLL_CON1_PLLPD0_SHIFT (13U) +#define CRU_DPLL_CON1_PLLPD0_MASK (0x1U << CRU_DPLL_CON1_PLLPD0_SHIFT) /* 0x00002000 */ +#define CRU_DPLL_CON1_PLLPD1_SHIFT (14U) +#define CRU_DPLL_CON1_PLLPD1_MASK (0x1U << CRU_DPLL_CON1_PLLPD1_SHIFT) /* 0x00004000 */ +#define CRU_DPLL_CON1_PLLPDSEL_SHIFT (15U) +#define CRU_DPLL_CON1_PLLPDSEL_MASK (0x1U << CRU_DPLL_CON1_PLLPDSEL_SHIFT) /* 0x00008000 */ +/* DPLL_CON2 */ +#define CRU_DPLL_CON2_OFFSET (0x28U) +#define CRU_DPLL_CON2_FRACDIV_SHIFT (0U) +#define CRU_DPLL_CON2_FRACDIV_MASK (0xFFFFFFU << CRU_DPLL_CON2_FRACDIV_SHIFT) /* 0x00FFFFFF */ +#define CRU_DPLL_CON2_DACPD_SHIFT (24U) +#define CRU_DPLL_CON2_DACPD_MASK (0x1U << CRU_DPLL_CON2_DACPD_SHIFT) /* 0x01000000 */ +#define CRU_DPLL_CON2_FOUTPOSTDIVPD_SHIFT (25U) +#define CRU_DPLL_CON2_FOUTPOSTDIVPD_MASK (0x1U << CRU_DPLL_CON2_FOUTPOSTDIVPD_SHIFT) /* 0x02000000 */ +#define CRU_DPLL_CON2_FOUTVCOPD_SHIFT (26U) +#define CRU_DPLL_CON2_FOUTVCOPD_MASK (0x1U << CRU_DPLL_CON2_FOUTVCOPD_SHIFT) /* 0x04000000 */ +#define CRU_DPLL_CON2_FOUT4PHASEPD_SHIFT (27U) +#define CRU_DPLL_CON2_FOUT4PHASEPD_MASK (0x1U << CRU_DPLL_CON2_FOUT4PHASEPD_SHIFT) /* 0x08000000 */ +/* DPLL_CON3 */ +#define CRU_DPLL_CON3_OFFSET (0x2CU) +#define CRU_DPLL_CON3_SSMOD_BP_SHIFT (0U) +#define CRU_DPLL_CON3_SSMOD_BP_MASK (0x1U << CRU_DPLL_CON3_SSMOD_BP_SHIFT) /* 0x00000001 */ +#define CRU_DPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT (1U) +#define CRU_DPLL_CON3_SSMOD_DISABLE_SSCG_MASK (0x1U << CRU_DPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT) /* 0x00000002 */ +#define CRU_DPLL_CON3_SSMOD_RESET_SHIFT (2U) +#define CRU_DPLL_CON3_SSMOD_RESET_MASK (0x1U << CRU_DPLL_CON3_SSMOD_RESET_SHIFT) /* 0x00000004 */ +#define CRU_DPLL_CON3_SSMOD_DOWNSPREAD_SHIFT (3U) +#define CRU_DPLL_CON3_SSMOD_DOWNSPREAD_MASK (0x1U << CRU_DPLL_CON3_SSMOD_DOWNSPREAD_SHIFT) /* 0x00000008 */ +#define CRU_DPLL_CON3_SSMOD_DIVVAL_SHIFT (4U) +#define CRU_DPLL_CON3_SSMOD_DIVVAL_MASK (0xFU << CRU_DPLL_CON3_SSMOD_DIVVAL_SHIFT) /* 0x000000F0 */ +#define CRU_DPLL_CON3_SSMOD_SPREAD_SHIFT (8U) +#define CRU_DPLL_CON3_SSMOD_SPREAD_MASK (0x1FU << CRU_DPLL_CON3_SSMOD_SPREAD_SHIFT) /* 0x00001F00 */ +/* DPLL_CON4 */ +#define CRU_DPLL_CON4_OFFSET (0x30U) +#define CRU_DPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT (0U) +#define CRU_DPLL_CON4_SSMOD_SEL_EXT_WAVE_MASK (0x1U << CRU_DPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT) /* 0x00000001 */ +#define CRU_DPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT (8U) +#define CRU_DPLL_CON4_SSMOD_EXT_MAXADDR_MASK (0xFFU << CRU_DPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT) /* 0x0000FF00 */ +/* GPLL_CON0 */ +#define CRU_GPLL_CON0_OFFSET (0x40U) +#define CRU_GPLL_CON0_FBDIV_SHIFT (0U) +#define CRU_GPLL_CON0_FBDIV_MASK (0xFFFU << CRU_GPLL_CON0_FBDIV_SHIFT) /* 0x00000FFF */ +#define CRU_GPLL_CON0_POSTDIV1_SHIFT (12U) +#define CRU_GPLL_CON0_POSTDIV1_MASK (0x7U << CRU_GPLL_CON0_POSTDIV1_SHIFT) /* 0x00007000 */ +#define CRU_GPLL_CON0_BYPASS_SHIFT (15U) +#define CRU_GPLL_CON0_BYPASS_MASK (0x1U << CRU_GPLL_CON0_BYPASS_SHIFT) /* 0x00008000 */ +/* GPLL_CON1 */ +#define CRU_GPLL_CON1_OFFSET (0x44U) +#define CRU_GPLL_CON1_REFDIV_SHIFT (0U) +#define CRU_GPLL_CON1_REFDIV_MASK (0x3FU << CRU_GPLL_CON1_REFDIV_SHIFT) /* 0x0000003F */ +#define CRU_GPLL_CON1_POSTDIV2_SHIFT (6U) +#define CRU_GPLL_CON1_POSTDIV2_MASK (0x7U << CRU_GPLL_CON1_POSTDIV2_SHIFT) /* 0x000001C0 */ +#define CRU_GPLL_CON1_PLL_LOCK_SHIFT (10U) +#define CRU_GPLL_CON1_PLL_LOCK_MASK (0x1U << CRU_GPLL_CON1_PLL_LOCK_SHIFT) /* 0x00000400 */ +#define CRU_GPLL_CON1_DSMPD_SHIFT (12U) +#define CRU_GPLL_CON1_DSMPD_MASK (0x1U << CRU_GPLL_CON1_DSMPD_SHIFT) /* 0x00001000 */ +#define CRU_GPLL_CON1_PLLPD0_SHIFT (13U) +#define CRU_GPLL_CON1_PLLPD0_MASK (0x1U << CRU_GPLL_CON1_PLLPD0_SHIFT) /* 0x00002000 */ +#define CRU_GPLL_CON1_PLLPD1_SHIFT (14U) +#define CRU_GPLL_CON1_PLLPD1_MASK (0x1U << CRU_GPLL_CON1_PLLPD1_SHIFT) /* 0x00004000 */ +#define CRU_GPLL_CON1_PLLPDSEL_SHIFT (15U) +#define CRU_GPLL_CON1_PLLPDSEL_MASK (0x1U << CRU_GPLL_CON1_PLLPDSEL_SHIFT) /* 0x00008000 */ +/* GPLL_CON2 */ +#define CRU_GPLL_CON2_OFFSET (0x48U) +#define CRU_GPLL_CON2_FRACDIV_SHIFT (0U) +#define CRU_GPLL_CON2_FRACDIV_MASK (0xFFFFFFU << CRU_GPLL_CON2_FRACDIV_SHIFT) /* 0x00FFFFFF */ +#define CRU_GPLL_CON2_DACPD_SHIFT (24U) +#define CRU_GPLL_CON2_DACPD_MASK (0x1U << CRU_GPLL_CON2_DACPD_SHIFT) /* 0x01000000 */ +#define CRU_GPLL_CON2_FOUTPOSTDIVPD_SHIFT (25U) +#define CRU_GPLL_CON2_FOUTPOSTDIVPD_MASK (0x1U << CRU_GPLL_CON2_FOUTPOSTDIVPD_SHIFT) /* 0x02000000 */ +#define CRU_GPLL_CON2_FOUTVCOPD_SHIFT (26U) +#define CRU_GPLL_CON2_FOUTVCOPD_MASK (0x1U << CRU_GPLL_CON2_FOUTVCOPD_SHIFT) /* 0x04000000 */ +#define CRU_GPLL_CON2_FOUT4PHASEPD_SHIFT (27U) +#define CRU_GPLL_CON2_FOUT4PHASEPD_MASK (0x1U << CRU_GPLL_CON2_FOUT4PHASEPD_SHIFT) /* 0x08000000 */ +/* GPLL_CON3 */ +#define CRU_GPLL_CON3_OFFSET (0x4CU) +#define CRU_GPLL_CON3_SSMOD_BP_SHIFT (0U) +#define CRU_GPLL_CON3_SSMOD_BP_MASK (0x1U << CRU_GPLL_CON3_SSMOD_BP_SHIFT) /* 0x00000001 */ +#define CRU_GPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT (1U) +#define CRU_GPLL_CON3_SSMOD_DISABLE_SSCG_MASK (0x1U << CRU_GPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT) /* 0x00000002 */ +#define CRU_GPLL_CON3_SSMOD_RESET_SHIFT (2U) +#define CRU_GPLL_CON3_SSMOD_RESET_MASK (0x1U << CRU_GPLL_CON3_SSMOD_RESET_SHIFT) /* 0x00000004 */ +#define CRU_GPLL_CON3_SSMOD_DOWNSPREAD_SHIFT (3U) +#define CRU_GPLL_CON3_SSMOD_DOWNSPREAD_MASK (0x1U << CRU_GPLL_CON3_SSMOD_DOWNSPREAD_SHIFT) /* 0x00000008 */ +#define CRU_GPLL_CON3_SSMOD_DIVVAL_SHIFT (4U) +#define CRU_GPLL_CON3_SSMOD_DIVVAL_MASK (0xFU << CRU_GPLL_CON3_SSMOD_DIVVAL_SHIFT) /* 0x000000F0 */ +#define CRU_GPLL_CON3_SSMOD_SPREAD_SHIFT (8U) +#define CRU_GPLL_CON3_SSMOD_SPREAD_MASK (0x1FU << CRU_GPLL_CON3_SSMOD_SPREAD_SHIFT) /* 0x00001F00 */ +/* GPLL_CON4 */ +#define CRU_GPLL_CON4_OFFSET (0x50U) +#define CRU_GPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT (0U) +#define CRU_GPLL_CON4_SSMOD_SEL_EXT_WAVE_MASK (0x1U << CRU_GPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT) /* 0x00000001 */ +#define CRU_GPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT (8U) +#define CRU_GPLL_CON4_SSMOD_EXT_MAXADDR_MASK (0xFFU << CRU_GPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT) /* 0x0000FF00 */ +/* CPLL_CON0 */ +#define CRU_CPLL_CON0_OFFSET (0x60U) +#define CRU_CPLL_CON0_FBDIV_SHIFT (0U) +#define CRU_CPLL_CON0_FBDIV_MASK (0xFFFU << CRU_CPLL_CON0_FBDIV_SHIFT) /* 0x00000FFF */ +#define CRU_CPLL_CON0_POSTDIV1_SHIFT (12U) +#define CRU_CPLL_CON0_POSTDIV1_MASK (0x7U << CRU_CPLL_CON0_POSTDIV1_SHIFT) /* 0x00007000 */ +#define CRU_CPLL_CON0_BYPASS_SHIFT (15U) +#define CRU_CPLL_CON0_BYPASS_MASK (0x1U << CRU_CPLL_CON0_BYPASS_SHIFT) /* 0x00008000 */ +/* CPLL_CON1 */ +#define CRU_CPLL_CON1_OFFSET (0x64U) +#define CRU_CPLL_CON1_REFDIV_SHIFT (0U) +#define CRU_CPLL_CON1_REFDIV_MASK (0x3FU << CRU_CPLL_CON1_REFDIV_SHIFT) /* 0x0000003F */ +#define CRU_CPLL_CON1_POSTDIV2_SHIFT (6U) +#define CRU_CPLL_CON1_POSTDIV2_MASK (0x7U << CRU_CPLL_CON1_POSTDIV2_SHIFT) /* 0x000001C0 */ +#define CRU_CPLL_CON1_PLL_LOCK_SHIFT (10U) +#define CRU_CPLL_CON1_PLL_LOCK_MASK (0x1U << CRU_CPLL_CON1_PLL_LOCK_SHIFT) /* 0x00000400 */ +#define CRU_CPLL_CON1_DSMPD_SHIFT (12U) +#define CRU_CPLL_CON1_DSMPD_MASK (0x1U << CRU_CPLL_CON1_DSMPD_SHIFT) /* 0x00001000 */ +#define CRU_CPLL_CON1_PLLPD0_SHIFT (13U) +#define CRU_CPLL_CON1_PLLPD0_MASK (0x1U << CRU_CPLL_CON1_PLLPD0_SHIFT) /* 0x00002000 */ +#define CRU_CPLL_CON1_PLLPD1_SHIFT (14U) +#define CRU_CPLL_CON1_PLLPD1_MASK (0x1U << CRU_CPLL_CON1_PLLPD1_SHIFT) /* 0x00004000 */ +#define CRU_CPLL_CON1_PLLPDSEL_SHIFT (15U) +#define CRU_CPLL_CON1_PLLPDSEL_MASK (0x1U << CRU_CPLL_CON1_PLLPDSEL_SHIFT) /* 0x00008000 */ +/* CPLL_CON2 */ +#define CRU_CPLL_CON2_OFFSET (0x68U) +#define CRU_CPLL_CON2_FRACDIV_SHIFT (0U) +#define CRU_CPLL_CON2_FRACDIV_MASK (0xFFFFFFU << CRU_CPLL_CON2_FRACDIV_SHIFT) /* 0x00FFFFFF */ +#define CRU_CPLL_CON2_DACPD_SHIFT (24U) +#define CRU_CPLL_CON2_DACPD_MASK (0x1U << CRU_CPLL_CON2_DACPD_SHIFT) /* 0x01000000 */ +#define CRU_CPLL_CON2_FOUTPOSTDIVPD_SHIFT (25U) +#define CRU_CPLL_CON2_FOUTPOSTDIVPD_MASK (0x1U << CRU_CPLL_CON2_FOUTPOSTDIVPD_SHIFT) /* 0x02000000 */ +#define CRU_CPLL_CON2_FOUTVCOPD_SHIFT (26U) +#define CRU_CPLL_CON2_FOUTVCOPD_MASK (0x1U << CRU_CPLL_CON2_FOUTVCOPD_SHIFT) /* 0x04000000 */ +#define CRU_CPLL_CON2_FOUT4PHASEPD_SHIFT (27U) +#define CRU_CPLL_CON2_FOUT4PHASEPD_MASK (0x1U << CRU_CPLL_CON2_FOUT4PHASEPD_SHIFT) /* 0x08000000 */ +/* CPLL_CON3 */ +#define CRU_CPLL_CON3_OFFSET (0x6CU) +#define CRU_CPLL_CON3_SSMOD_BP_SHIFT (0U) +#define CRU_CPLL_CON3_SSMOD_BP_MASK (0x1U << CRU_CPLL_CON3_SSMOD_BP_SHIFT) /* 0x00000001 */ +#define CRU_CPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT (1U) +#define CRU_CPLL_CON3_SSMOD_DISABLE_SSCG_MASK (0x1U << CRU_CPLL_CON3_SSMOD_DISABLE_SSCG_SHIFT) /* 0x00000002 */ +#define CRU_CPLL_CON3_SSMOD_RESET_SHIFT (2U) +#define CRU_CPLL_CON3_SSMOD_RESET_MASK (0x1U << CRU_CPLL_CON3_SSMOD_RESET_SHIFT) /* 0x00000004 */ +#define CRU_CPLL_CON3_SSMOD_DOWNSPREAD_SHIFT (3U) +#define CRU_CPLL_CON3_SSMOD_DOWNSPREAD_MASK (0x1U << CRU_CPLL_CON3_SSMOD_DOWNSPREAD_SHIFT) /* 0x00000008 */ +#define CRU_CPLL_CON3_SSMOD_DIVVAL_SHIFT (4U) +#define CRU_CPLL_CON3_SSMOD_DIVVAL_MASK (0xFU << CRU_CPLL_CON3_SSMOD_DIVVAL_SHIFT) /* 0x000000F0 */ +#define CRU_CPLL_CON3_SSMOD_SPREAD_SHIFT (8U) +#define CRU_CPLL_CON3_SSMOD_SPREAD_MASK (0x1FU << CRU_CPLL_CON3_SSMOD_SPREAD_SHIFT) /* 0x00001F00 */ +/* CPLL_CON4 */ +#define CRU_CPLL_CON4_OFFSET (0x70U) +#define CRU_CPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT (0U) +#define CRU_CPLL_CON4_SSMOD_SEL_EXT_WAVE_MASK (0x1U << CRU_CPLL_CON4_SSMOD_SEL_EXT_WAVE_SHIFT) /* 0x00000001 */ +#define CRU_CPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT (8U) +#define CRU_CPLL_CON4_SSMOD_EXT_MAXADDR_MASK (0xFFU << CRU_CPLL_CON4_SSMOD_EXT_MAXADDR_SHIFT) /* 0x0000FF00 */ +/* NPLL_CON0 */ +#define CRU_NPLL_CON0_OFFSET (0x80U) +#define CRU_NPLL_CON0_FBDIV_SHIFT (0U) +#define CRU_NPLL_CON0_FBDIV_MASK (0xFFFU << CRU_NPLL_CON0_FBDIV_SHIFT) /* 0x00000FFF */ +#define CRU_NPLL_CON0_POSTDIV1_SHIFT (12U) +#define CRU_NPLL_CON0_POSTDIV1_MASK (0x7U << CRU_NPLL_CON0_POSTDIV1_SHIFT) /* 0x00007000 */ +#define CRU_NPLL_CON0_BYPASS_SHIFT (15U) +#define CRU_NPLL_CON0_BYPASS_MASK (0x1U << CRU_NPLL_CON0_BYPASS_SHIFT) /* 0x00008000 */ +/* NPLL_CON1 */ +#define CRU_NPLL_CON1_OFFSET (0x84U) +#define CRU_NPLL_CON1_REFDIV_SHIFT (0U) +#define CRU_NPLL_CON1_REFDIV_MASK (0x3FU << CRU_NPLL_CON1_REFDIV_SHIFT) /* 0x0000003F */ +#define CRU_NPLL_CON1_POSTDIV2_SHIFT (6U) +#define CRU_NPLL_CON1_POSTDIV2_MASK (0x7U << CRU_NPLL_CON1_POSTDIV2_SHIFT) /* 0x000001C0 */ +#define CRU_NPLL_CON1_FOUTPOSTDIVPD_SHIFT (9U) +#define CRU_NPLL_CON1_FOUTPOSTDIVPD_MASK (0x1U << CRU_NPLL_CON1_FOUTPOSTDIVPD_SHIFT) /* 0x00000200 */ +#define CRU_NPLL_CON1_PLL_LOCK_SHIFT (10U) +#define CRU_NPLL_CON1_PLL_LOCK_MASK (0x1U << CRU_NPLL_CON1_PLL_LOCK_SHIFT) /* 0x00000400 */ +#define CRU_NPLL_CON1_FOUTVCOPD_SHIFT (11U) +#define CRU_NPLL_CON1_FOUTVCOPD_MASK (0x1U << CRU_NPLL_CON1_FOUTVCOPD_SHIFT) /* 0x00000800 */ +#define CRU_NPLL_CON1_DSMPD_SHIFT (12U) +#define CRU_NPLL_CON1_DSMPD_MASK (0x1U << CRU_NPLL_CON1_DSMPD_SHIFT) /* 0x00001000 */ +#define CRU_NPLL_CON1_PLLPD0_SHIFT (13U) +#define CRU_NPLL_CON1_PLLPD0_MASK (0x1U << CRU_NPLL_CON1_PLLPD0_SHIFT) /* 0x00002000 */ +#define CRU_NPLL_CON1_PLLPD1_SHIFT (14U) +#define CRU_NPLL_CON1_PLLPD1_MASK (0x1U << CRU_NPLL_CON1_PLLPD1_SHIFT) /* 0x00004000 */ +#define CRU_NPLL_CON1_PLLPDSEL_SHIFT (15U) +#define CRU_NPLL_CON1_PLLPDSEL_MASK (0x1U << CRU_NPLL_CON1_PLLPDSEL_SHIFT) /* 0x00008000 */ +/* VPLL_CON0 */ +#define CRU_VPLL_CON0_OFFSET (0xA0U) +#define CRU_VPLL_CON0_FBDIV_SHIFT (0U) +#define CRU_VPLL_CON0_FBDIV_MASK (0xFFFU << CRU_VPLL_CON0_FBDIV_SHIFT) /* 0x00000FFF */ +#define CRU_VPLL_CON0_POSTDIV1_SHIFT (12U) +#define CRU_VPLL_CON0_POSTDIV1_MASK (0x7U << CRU_VPLL_CON0_POSTDIV1_SHIFT) /* 0x00007000 */ +#define CRU_VPLL_CON0_BYPASS_SHIFT (15U) +#define CRU_VPLL_CON0_BYPASS_MASK (0x1U << CRU_VPLL_CON0_BYPASS_SHIFT) /* 0x00008000 */ +/* VPLL_CON1 */ +#define CRU_VPLL_CON1_OFFSET (0xA4U) +#define CRU_VPLL_CON1_REFDIV_SHIFT (0U) +#define CRU_VPLL_CON1_REFDIV_MASK (0x3FU << CRU_VPLL_CON1_REFDIV_SHIFT) /* 0x0000003F */ +#define CRU_VPLL_CON1_POSTDIV2_SHIFT (6U) +#define CRU_VPLL_CON1_POSTDIV2_MASK (0x7U << CRU_VPLL_CON1_POSTDIV2_SHIFT) /* 0x000001C0 */ +#define CRU_VPLL_CON1_FOUTPOSTDIVPD_SHIFT (9U) +#define CRU_VPLL_CON1_FOUTPOSTDIVPD_MASK (0x1U << CRU_VPLL_CON1_FOUTPOSTDIVPD_SHIFT) /* 0x00000200 */ +#define CRU_VPLL_CON1_PLL_LOCK_SHIFT (10U) +#define CRU_VPLL_CON1_PLL_LOCK_MASK (0x1U << CRU_VPLL_CON1_PLL_LOCK_SHIFT) /* 0x00000400 */ +#define CRU_VPLL_CON1_FOUTVCOPD_SHIFT (11U) +#define CRU_VPLL_CON1_FOUTVCOPD_MASK (0x1U << CRU_VPLL_CON1_FOUTVCOPD_SHIFT) /* 0x00000800 */ +#define CRU_VPLL_CON1_DSMPD_SHIFT (12U) +#define CRU_VPLL_CON1_DSMPD_MASK (0x1U << CRU_VPLL_CON1_DSMPD_SHIFT) /* 0x00001000 */ +#define CRU_VPLL_CON1_PLLPD0_SHIFT (13U) +#define CRU_VPLL_CON1_PLLPD0_MASK (0x1U << CRU_VPLL_CON1_PLLPD0_SHIFT) /* 0x00002000 */ +#define CRU_VPLL_CON1_PLLPD1_SHIFT (14U) +#define CRU_VPLL_CON1_PLLPD1_MASK (0x1U << CRU_VPLL_CON1_PLLPD1_SHIFT) /* 0x00004000 */ +#define CRU_VPLL_CON1_PLLPDSEL_SHIFT (15U) +#define CRU_VPLL_CON1_PLLPDSEL_MASK (0x1U << CRU_VPLL_CON1_PLLPDSEL_SHIFT) /* 0x00008000 */ +/* MODE_CON00 */ +#define CRU_MODE_CON00_OFFSET (0xC0U) +#define CRU_MODE_CON00_CLK_APLL_MODE_SHIFT (0U) +#define CRU_MODE_CON00_CLK_APLL_MODE_MASK (0x3U << CRU_MODE_CON00_CLK_APLL_MODE_SHIFT) /* 0x00000003 */ +#define CRU_MODE_CON00_CLK_DPLL_MODE_SHIFT (2U) +#define CRU_MODE_CON00_CLK_DPLL_MODE_MASK (0x3U << CRU_MODE_CON00_CLK_DPLL_MODE_SHIFT) /* 0x0000000C */ +#define CRU_MODE_CON00_CLK_CPLL_MODE_SHIFT (4U) +#define CRU_MODE_CON00_CLK_CPLL_MODE_MASK (0x3U << CRU_MODE_CON00_CLK_CPLL_MODE_SHIFT) /* 0x00000030 */ +#define CRU_MODE_CON00_CLK_GPLL_MODE_SHIFT (6U) +#define CRU_MODE_CON00_CLK_GPLL_MODE_MASK (0x3U << CRU_MODE_CON00_CLK_GPLL_MODE_SHIFT) /* 0x000000C0 */ +#define CRU_MODE_CON00_CLK_NPLL_MODE_SHIFT (10U) +#define CRU_MODE_CON00_CLK_NPLL_MODE_MASK (0x3U << CRU_MODE_CON00_CLK_NPLL_MODE_SHIFT) /* 0x00000C00 */ +#define CRU_MODE_CON00_CLK_VPLL_MODE_SHIFT (12U) +#define CRU_MODE_CON00_CLK_VPLL_MODE_MASK (0x3U << CRU_MODE_CON00_CLK_VPLL_MODE_SHIFT) /* 0x00003000 */ +#define CRU_MODE_CON00_USBPHY480M_PLL_MODE_SHIFT (14U) +#define CRU_MODE_CON00_USBPHY480M_PLL_MODE_MASK (0x3U << CRU_MODE_CON00_USBPHY480M_PLL_MODE_SHIFT) /* 0x0000C000 */ +/* MISC_CON0 */ +#define CRU_MISC_CON0_OFFSET (0xC4U) +#define CRU_MISC_CON0_QCHANNEL_ENA_SCLK_CORE_SHIFT (0U) +#define CRU_MISC_CON0_QCHANNEL_ENA_SCLK_CORE_MASK (0x1U << CRU_MISC_CON0_QCHANNEL_ENA_SCLK_CORE_SHIFT) /* 0x00000001 */ +#define CRU_MISC_CON0_QCHANNEL_ENA_PCLK_CORE_SHIFT (1U) +#define CRU_MISC_CON0_QCHANNEL_ENA_PCLK_CORE_MASK (0x1U << CRU_MISC_CON0_QCHANNEL_ENA_PCLK_CORE_SHIFT) /* 0x00000002 */ +#define CRU_MISC_CON0_QCHANNEL_ENA_ATCLK_CORE_SHIFT (2U) +#define CRU_MISC_CON0_QCHANNEL_ENA_ATCLK_CORE_MASK (0x1U << CRU_MISC_CON0_QCHANNEL_ENA_ATCLK_CORE_SHIFT) /* 0x00000004 */ +#define CRU_MISC_CON0_QCHANNEL_ENA_GICCLK_CORE_SHIFT (3U) +#define CRU_MISC_CON0_QCHANNEL_ENA_GICCLK_CORE_MASK (0x1U << CRU_MISC_CON0_QCHANNEL_ENA_GICCLK_CORE_SHIFT) /* 0x00000008 */ +#define CRU_MISC_CON0_QCHANNEL_ENA_PDBGCLK_CORE_SHIFT (4U) +#define CRU_MISC_CON0_QCHANNEL_ENA_PDBGCLK_CORE_MASK (0x1U << CRU_MISC_CON0_QCHANNEL_ENA_PDBGCLK_CORE_SHIFT) /* 0x00000010 */ +#define CRU_MISC_CON0_QCHANNEL_ENA_CLK_GPU_SHIFT (5U) +#define CRU_MISC_CON0_QCHANNEL_ENA_CLK_GPU_MASK (0x1U << CRU_MISC_CON0_QCHANNEL_ENA_CLK_GPU_SHIFT) /* 0x00000020 */ +#define CRU_MISC_CON0_QCHANNEL_ENA_CLK_PDCORE_CORE2GIC_SHIFT (6U) +#define CRU_MISC_CON0_QCHANNEL_ENA_CLK_PDCORE_CORE2GIC_MASK (0x1U << CRU_MISC_CON0_QCHANNEL_ENA_CLK_PDCORE_CORE2GIC_SHIFT) /* 0x00000040 */ +#define CRU_MISC_CON0_QCHANNEL_ENA_CLK_PDCORE_GIC2CORE_SHIFT (7U) +#define CRU_MISC_CON0_QCHANNEL_ENA_CLK_PDCORE_GIC2CORE_MASK (0x1U << CRU_MISC_CON0_QCHANNEL_ENA_CLK_PDCORE_GIC2CORE_SHIFT) /* 0x00000080 */ +#define CRU_MISC_CON0_QCHANNEL_ENA_CLK_PDGIC_CORE2GIC_SHIFT (8U) +#define CRU_MISC_CON0_QCHANNEL_ENA_CLK_PDGIC_CORE2GIC_MASK (0x1U << CRU_MISC_CON0_QCHANNEL_ENA_CLK_PDGIC_CORE2GIC_SHIFT) /* 0x00000100 */ +#define CRU_MISC_CON0_QCHANNEL_ENA_CLK_PDGIC_GIC2CORE_SHIFT (9U) +#define CRU_MISC_CON0_QCHANNEL_ENA_CLK_PDGIC_GIC2CORE_MASK (0x1U << CRU_MISC_CON0_QCHANNEL_ENA_CLK_PDGIC_GIC2CORE_SHIFT) /* 0x00000200 */ +#define CRU_MISC_CON0_QCHANNEL_ENA_CLK_GIC600_SHIFT (10U) +#define CRU_MISC_CON0_QCHANNEL_ENA_CLK_GIC600_MASK (0x1U << CRU_MISC_CON0_QCHANNEL_ENA_CLK_GIC600_SHIFT) /* 0x00000400 */ +#define CRU_MISC_CON0_QCHANNEL_GATING_ENABLE_SHIFT (11U) +#define CRU_MISC_CON0_QCHANNEL_GATING_ENABLE_MASK (0x1U << CRU_MISC_CON0_QCHANNEL_GATING_ENABLE_SHIFT) /* 0x00000800 */ +#define CRU_MISC_CON0_DBGRST_EN_SHIFT (12U) +#define CRU_MISC_CON0_DBGRST_EN_MASK (0x1U << CRU_MISC_CON0_DBGRST_EN_SHIFT) /* 0x00001000 */ +#define CRU_MISC_CON0_HWFFC_CLK_SWITCH2CRU_ENA_SHIFT (13U) +#define CRU_MISC_CON0_HWFFC_CLK_SWITCH2CRU_ENA_MASK (0x1U << CRU_MISC_CON0_HWFFC_CLK_SWITCH2CRU_ENA_SHIFT) /* 0x00002000 */ +#define CRU_MISC_CON0_CPU_CLK_GATE_EMA_ENA_SHIFT (14U) +#define CRU_MISC_CON0_CPU_CLK_GATE_EMA_ENA_MASK (0x1U << CRU_MISC_CON0_CPU_CLK_GATE_EMA_ENA_SHIFT) /* 0x00004000 */ +#define CRU_MISC_CON0_GPU_CLK_GATE_EMA_ENA_SHIFT (15U) +#define CRU_MISC_CON0_GPU_CLK_GATE_EMA_ENA_MASK (0x1U << CRU_MISC_CON0_GPU_CLK_GATE_EMA_ENA_SHIFT) /* 0x00008000 */ +/* MISC_CON1 */ +#define CRU_MISC_CON1_OFFSET (0xC8U) +#define CRU_MISC_CON1_PD_CORE_DWN_CLK_EN_MASK_SHIFT (0U) +#define CRU_MISC_CON1_PD_CORE_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_CORE_DWN_CLK_EN_MASK_SHIFT) /* 0x00000001 */ +#define CRU_MISC_CON1_PD_GPU_DWN_CLK_EN_MASK_SHIFT (1U) +#define CRU_MISC_CON1_PD_GPU_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_GPU_DWN_CLK_EN_MASK_SHIFT) /* 0x00000002 */ +#define CRU_MISC_CON1_PD_NPU_DWN_CLK_EN_MASK_SHIFT (2U) +#define CRU_MISC_CON1_PD_NPU_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_NPU_DWN_CLK_EN_MASK_SHIFT) /* 0x00000004 */ +#define CRU_MISC_CON1_PD_DDR_DWN_CLK_EN_MASK_SHIFT (3U) +#define CRU_MISC_CON1_PD_DDR_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_DDR_DWN_CLK_EN_MASK_SHIFT) /* 0x00000008 */ +#define CRU_MISC_CON1_PD_PERI_DWN_CLK_EN_MASK_SHIFT (4U) +#define CRU_MISC_CON1_PD_PERI_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_PERI_DWN_CLK_EN_MASK_SHIFT) /* 0x00000010 */ +#define CRU_MISC_CON1_PD_PIPE_DWN_CLK_EN_MASK_SHIFT (5U) +#define CRU_MISC_CON1_PD_PIPE_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_PIPE_DWN_CLK_EN_MASK_SHIFT) /* 0x00000020 */ +#define CRU_MISC_CON1_PD_USB_DWN_CLK_EN_MASK_SHIFT (8U) +#define CRU_MISC_CON1_PD_USB_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_USB_DWN_CLK_EN_MASK_SHIFT) /* 0x00000100 */ +#define CRU_MISC_CON1_PD_VI_DWN_CLK_EN_MASK_SHIFT (9U) +#define CRU_MISC_CON1_PD_VI_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_VI_DWN_CLK_EN_MASK_SHIFT) /* 0x00000200 */ +#define CRU_MISC_CON1_PD_VO_DWN_CLK_EN_MASK_SHIFT (10U) +#define CRU_MISC_CON1_PD_VO_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_VO_DWN_CLK_EN_MASK_SHIFT) /* 0x00000400 */ +#define CRU_MISC_CON1_PD_RGA_DWN_CLK_EN_MASK_SHIFT (11U) +#define CRU_MISC_CON1_PD_RGA_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_RGA_DWN_CLK_EN_MASK_SHIFT) /* 0x00000800 */ +#define CRU_MISC_CON1_PD_VPU_DWN_CLK_EN_MASK_SHIFT (12U) +#define CRU_MISC_CON1_PD_VPU_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_VPU_DWN_CLK_EN_MASK_SHIFT) /* 0x00001000 */ +#define CRU_MISC_CON1_PD_RKVENC_DWN_CLK_EN_MASK_SHIFT (13U) +#define CRU_MISC_CON1_PD_RKVENC_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_RKVENC_DWN_CLK_EN_MASK_SHIFT) /* 0x00002000 */ +#define CRU_MISC_CON1_PD_RKVDEC_DWN_CLK_EN_MASK_SHIFT (14U) +#define CRU_MISC_CON1_PD_RKVDEC_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_RKVDEC_DWN_CLK_EN_MASK_SHIFT) /* 0x00004000 */ +#define CRU_MISC_CON1_PD_BUS_DWN_CLK_EN_MASK_SHIFT (15U) +#define CRU_MISC_CON1_PD_BUS_DWN_CLK_EN_MASK_MASK (0x1U << CRU_MISC_CON1_PD_BUS_DWN_CLK_EN_MASK_SHIFT) /* 0x00008000 */ +/* MISC_CON2 */ +#define CRU_MISC_CON2_OFFSET (0xCCU) +#define CRU_MISC_CON2_CLK_RGA_CORE_IDLE_ENABLE_SHIFT (0U) +#define CRU_MISC_CON2_CLK_RGA_CORE_IDLE_ENABLE_MASK (0x1U << CRU_MISC_CON2_CLK_RGA_CORE_IDLE_ENABLE_SHIFT) /* 0x00000001 */ +#define CRU_MISC_CON2_CLK_IEP_CORE_IDLE_ENABLE_SHIFT (1U) +#define CRU_MISC_CON2_CLK_IEP_CORE_IDLE_ENABLE_MASK (0x1U << CRU_MISC_CON2_CLK_IEP_CORE_IDLE_ENABLE_SHIFT) /* 0x00000002 */ +#define CRU_MISC_CON2_ACLK_VPU_IDLE_ENABLE_SHIFT (2U) +#define CRU_MISC_CON2_ACLK_VPU_IDLE_ENABLE_MASK (0x1U << CRU_MISC_CON2_ACLK_VPU_IDLE_ENABLE_SHIFT) /* 0x00000004 */ +#define CRU_MISC_CON2_ACLK_RKVENC_IDLE_ENABLE_SHIFT (3U) +#define CRU_MISC_CON2_ACLK_RKVENC_IDLE_ENABLE_MASK (0x1U << CRU_MISC_CON2_ACLK_RKVENC_IDLE_ENABLE_SHIFT) /* 0x00000008 */ +#define CRU_MISC_CON2_HCLK_RKVENC_IDLE_ENABLE_SHIFT (4U) +#define CRU_MISC_CON2_HCLK_RKVENC_IDLE_ENABLE_MASK (0x1U << CRU_MISC_CON2_HCLK_RKVENC_IDLE_ENABLE_SHIFT) /* 0x00000010 */ +#define CRU_MISC_CON2_CLK_RKVENC_CORE_IDLE_ENABLE_SHIFT (5U) +#define CRU_MISC_CON2_CLK_RKVENC_CORE_IDLE_ENABLE_MASK (0x1U << CRU_MISC_CON2_CLK_RKVENC_CORE_IDLE_ENABLE_SHIFT) /* 0x00000020 */ +#define CRU_MISC_CON2_ACLK_RKVDEC_IDLE_ENABLE_SHIFT (6U) +#define CRU_MISC_CON2_ACLK_RKVDEC_IDLE_ENABLE_MASK (0x1U << CRU_MISC_CON2_ACLK_RKVDEC_IDLE_ENABLE_SHIFT) /* 0x00000040 */ +#define CRU_MISC_CON2_CLK_RKVDEC_CORE_IDLE_ENABLE_SHIFT (7U) +#define CRU_MISC_CON2_CLK_RKVDEC_CORE_IDLE_ENABLE_MASK (0x1U << CRU_MISC_CON2_CLK_RKVDEC_CORE_IDLE_ENABLE_SHIFT) /* 0x00000080 */ +#define CRU_MISC_CON2_CLK_RKVDEC_CA_IDLE_ENABLE_SHIFT (8U) +#define CRU_MISC_CON2_CLK_RKVDEC_CA_IDLE_ENABLE_MASK (0x1U << CRU_MISC_CON2_CLK_RKVDEC_CA_IDLE_ENABLE_SHIFT) /* 0x00000100 */ +#define CRU_MISC_CON2_CLK_RKVDEC_HEVC_CA_IDLE_ENABLE_SHIFT (9U) +#define CRU_MISC_CON2_CLK_RKVDEC_HEVC_CA_IDLE_ENABLE_MASK (0x1U << CRU_MISC_CON2_CLK_RKVDEC_HEVC_CA_IDLE_ENABLE_SHIFT) /* 0x00000200 */ +#define CRU_MISC_CON2_USBPHY480M_SRC_SEL_SHIFT (15U) +#define CRU_MISC_CON2_USBPHY480M_SRC_SEL_MASK (0x1U << CRU_MISC_CON2_USBPHY480M_SRC_SEL_SHIFT) /* 0x00008000 */ +/* GLB_CNT_TH */ +#define CRU_GLB_CNT_TH_OFFSET (0xD0U) +#define CRU_GLB_CNT_TH_GLOBAL_RESET_COUNTER_THRESHOLD_SHIFT (0U) +#define CRU_GLB_CNT_TH_GLOBAL_RESET_COUNTER_THRESHOLD_MASK (0xFFFFU << CRU_GLB_CNT_TH_GLOBAL_RESET_COUNTER_THRESHOLD_SHIFT) /* 0x0000FFFF */ +#define CRU_GLB_CNT_TH_RESERVED_SHIFT (16U) +#define CRU_GLB_CNT_TH_RESERVED_MASK (0xFFFFU << CRU_GLB_CNT_TH_RESERVED_SHIFT) /* 0xFFFF0000 */ +/* GLB_SRST_FST */ +#define CRU_GLB_SRST_FST_OFFSET (0xD4U) +#define CRU_GLB_SRST_FST_GLB_SRST_FST_SHIFT (0U) +#define CRU_GLB_SRST_FST_GLB_SRST_FST_MASK (0xFFFFU << CRU_GLB_SRST_FST_GLB_SRST_FST_SHIFT) /* 0x0000FFFF */ +/* GLB_SRST_SND */ +#define CRU_GLB_SRST_SND_OFFSET (0xD8U) +#define CRU_GLB_SRST_SND_GLB_SRST_SND_SHIFT (0U) +#define CRU_GLB_SRST_SND_GLB_SRST_SND_MASK (0xFFFFU << CRU_GLB_SRST_SND_GLB_SRST_SND_SHIFT) /* 0x0000FFFF */ +/* GLB_RST_CON */ +#define CRU_GLB_RST_CON_OFFSET (0xDCU) +#define CRU_GLB_RST_CON_TSADC_GLB_SRST_CTRL_SHIFT (0U) +#define CRU_GLB_RST_CON_TSADC_GLB_SRST_CTRL_MASK (0x1U << CRU_GLB_RST_CON_TSADC_GLB_SRST_CTRL_SHIFT) /* 0x00000001 */ +#define CRU_GLB_RST_CON_WDT_GLB_SRST_CTRL_SHIFT (1U) +#define CRU_GLB_RST_CON_WDT_GLB_SRST_CTRL_MASK (0x1U << CRU_GLB_RST_CON_WDT_GLB_SRST_CTRL_SHIFT) /* 0x00000002 */ +#define CRU_GLB_RST_CON_PMU_SRST_GLB_CTRL_SHIFT (2U) +#define CRU_GLB_RST_CON_PMU_SRST_GLB_CTRL_MASK (0x1U << CRU_GLB_RST_CON_PMU_SRST_GLB_CTRL_SHIFT) /* 0x00000004 */ +#define CRU_GLB_RST_CON_PMU_SRST_GLB_EN_SHIFT (3U) +#define CRU_GLB_RST_CON_PMU_SRST_GLB_EN_MASK (0x1U << CRU_GLB_RST_CON_PMU_SRST_GLB_EN_SHIFT) /* 0x00000008 */ +#define CRU_GLB_RST_CON_PMU_SRST_WDT_EN_SHIFT (4U) +#define CRU_GLB_RST_CON_PMU_SRST_WDT_EN_MASK (0x1U << CRU_GLB_RST_CON_PMU_SRST_WDT_EN_SHIFT) /* 0x00000010 */ +#define CRU_GLB_RST_CON_TSADC_SHUT_RESET_EXT_EN_SHIFT (6U) +#define CRU_GLB_RST_CON_TSADC_SHUT_RESET_EXT_EN_MASK (0x1U << CRU_GLB_RST_CON_TSADC_SHUT_RESET_EXT_EN_SHIFT) /* 0x00000040 */ +#define CRU_GLB_RST_CON_WDT_RESET_EXT_EN_SHIFT (7U) +#define CRU_GLB_RST_CON_WDT_RESET_EXT_EN_MASK (0x1U << CRU_GLB_RST_CON_WDT_RESET_EXT_EN_SHIFT) /* 0x00000080 */ +#define CRU_GLB_RST_CON_JDB_GLB_SRST_CTRL_ENABLE_SHIFT (8U) +#define CRU_GLB_RST_CON_JDB_GLB_SRST_CTRL_ENABLE_MASK (0x1U << CRU_GLB_RST_CON_JDB_GLB_SRST_CTRL_ENABLE_SHIFT) /* 0x00000100 */ +#define CRU_GLB_RST_CON_OSC_CHK_GLB_SRST_CTRL_ENABLE_SHIFT (9U) +#define CRU_GLB_RST_CON_OSC_CHK_GLB_SRST_CTRL_ENABLE_MASK (0x1U << CRU_GLB_RST_CON_OSC_CHK_GLB_SRST_CTRL_ENABLE_SHIFT) /* 0x00000200 */ +#define CRU_GLB_RST_CON_SGRF_CRC_CHK_GLB_SRST_CTRL_ENABLE_SHIFT (10U) +#define CRU_GLB_RST_CON_SGRF_CRC_CHK_GLB_SRST_CTRL_ENABLE_MASK (0x1U << CRU_GLB_RST_CON_SGRF_CRC_CHK_GLB_SRST_CTRL_ENABLE_SHIFT) /* 0x00000400 */ +#define CRU_GLB_RST_CON_PMUSGRF_CRC_CHK_GLB_SRST_CTRL_ENABLE_SHIFT (11U) +#define CRU_GLB_RST_CON_PMUSGRF_CRC_CHK_GLB_SRST_CTRL_ENABLE_MASK (0x1U << CRU_GLB_RST_CON_PMUSGRF_CRC_CHK_GLB_SRST_CTRL_ENABLE_SHIFT) /* 0x00000800 */ +#define CRU_GLB_RST_CON_JDB_GLB_SRST_CTRL_SHIFT (12U) +#define CRU_GLB_RST_CON_JDB_GLB_SRST_CTRL_MASK (0x1U << CRU_GLB_RST_CON_JDB_GLB_SRST_CTRL_SHIFT) /* 0x00001000 */ +#define CRU_GLB_RST_CON_OSC_CHK_GLB_SRST_CTRL_SHIFT (13U) +#define CRU_GLB_RST_CON_OSC_CHK_GLB_SRST_CTRL_MASK (0x1U << CRU_GLB_RST_CON_OSC_CHK_GLB_SRST_CTRL_SHIFT) /* 0x00002000 */ +#define CRU_GLB_RST_CON_SGRF_CRC_CHK_GLB_SRST_CTRL_SHIFT (14U) +#define CRU_GLB_RST_CON_SGRF_CRC_CHK_GLB_SRST_CTRL_MASK (0x1U << CRU_GLB_RST_CON_SGRF_CRC_CHK_GLB_SRST_CTRL_SHIFT) /* 0x00004000 */ +#define CRU_GLB_RST_CON_PMUSGRF_CRC_CHK_GLB_SRST_CTRL_SHIFT (15U) +#define CRU_GLB_RST_CON_PMUSGRF_CRC_CHK_GLB_SRST_CTRL_MASK (0x1U << CRU_GLB_RST_CON_PMUSGRF_CRC_CHK_GLB_SRST_CTRL_SHIFT) /* 0x00008000 */ +/* GLB_RST_ST */ +#define CRU_GLB_RST_ST_OFFSET (0xE0U) +#define CRU_GLB_RST_ST_FST_GLB_RST_ST_SHIFT (0U) +#define CRU_GLB_RST_ST_FST_GLB_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_FST_GLB_RST_ST_SHIFT) /* 0x00000001 */ +#define CRU_GLB_RST_ST_SND_GLB_RST_ST_SHIFT (1U) +#define CRU_GLB_RST_ST_SND_GLB_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_SND_GLB_RST_ST_SHIFT) /* 0x00000002 */ +#define CRU_GLB_RST_ST_FST_GLB_TSADC_RST_ST_SHIFT (2U) +#define CRU_GLB_RST_ST_FST_GLB_TSADC_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_FST_GLB_TSADC_RST_ST_SHIFT) /* 0x00000004 */ +#define CRU_GLB_RST_ST_SND_GLB_TSADC_RST_ST_SHIFT (3U) +#define CRU_GLB_RST_ST_SND_GLB_TSADC_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_SND_GLB_TSADC_RST_ST_SHIFT) /* 0x00000008 */ +#define CRU_GLB_RST_ST_FST_GLB_WDT_RST_ST_SHIFT (4U) +#define CRU_GLB_RST_ST_FST_GLB_WDT_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_FST_GLB_WDT_RST_ST_SHIFT) /* 0x00000010 */ +#define CRU_GLB_RST_ST_SND_GLB_WDT_RST_ST_SHIFT (5U) +#define CRU_GLB_RST_ST_SND_GLB_WDT_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_SND_GLB_WDT_RST_ST_SHIFT) /* 0x00000020 */ +#define CRU_GLB_RST_ST_GLB_JDB_RST_ST_SHIFT (6U) +#define CRU_GLB_RST_ST_GLB_JDB_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_GLB_JDB_RST_ST_SHIFT) /* 0x00000040 */ +#define CRU_GLB_RST_ST_GLB_OSC_CHK_RST_ST_SHIFT (7U) +#define CRU_GLB_RST_ST_GLB_OSC_CHK_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_GLB_OSC_CHK_RST_ST_SHIFT) /* 0x00000080 */ +#define CRU_GLB_RST_ST_GLB_SGRF_CRC_RST_ST_SHIFT (8U) +#define CRU_GLB_RST_ST_GLB_SGRF_CRC_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_GLB_SGRF_CRC_RST_ST_SHIFT) /* 0x00000100 */ +#define CRU_GLB_RST_ST_GLB_PMUSGRF_CRC_RST_ST_SHIFT (9U) +#define CRU_GLB_RST_ST_GLB_PMUSGRF_CRC_RST_ST_MASK (0x1U << CRU_GLB_RST_ST_GLB_PMUSGRF_CRC_RST_ST_SHIFT) /* 0x00000200 */ +/* CLKSEL_CON00 */ +#define CRU_CLKSEL_CON00_OFFSET (0x100U) +#define CRU_CLKSEL_CON00_CLK_CORE0_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON00_CLK_CORE0_DIV_MASK (0x1FU << CRU_CLKSEL_CON00_CLK_CORE0_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON00_CLK_CORE_I_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON00_CLK_CORE_I_SEL_MASK (0x1U << CRU_CLKSEL_CON00_CLK_CORE_I_SEL_SHIFT) /* 0x00000040 */ +#define CRU_CLKSEL_CON00_CLK_CORE_NDFT_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON00_CLK_CORE_NDFT_SEL_MASK (0x1U << CRU_CLKSEL_CON00_CLK_CORE_NDFT_SEL_SHIFT) /* 0x00000080 */ +#define CRU_CLKSEL_CON00_CLK_CORE1_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON00_CLK_CORE1_DIV_MASK (0x1FU << CRU_CLKSEL_CON00_CLK_CORE1_DIV_SHIFT) /* 0x00001F00 */ +#define CRU_CLKSEL_CON00_CLK_CORE_NDFT_MUX_SEL_SHIFT (15U) +#define CRU_CLKSEL_CON00_CLK_CORE_NDFT_MUX_SEL_MASK (0x1U << CRU_CLKSEL_CON00_CLK_CORE_NDFT_MUX_SEL_SHIFT) /* 0x00008000 */ +/* CLKSEL_CON01 */ +#define CRU_CLKSEL_CON01_OFFSET (0x104U) +#define CRU_CLKSEL_CON01_CLK_CORE2_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON01_CLK_CORE2_DIV_MASK (0x1FU << CRU_CLKSEL_CON01_CLK_CORE2_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON01_CLK_CORE3_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON01_CLK_CORE3_DIV_MASK (0x1FU << CRU_CLKSEL_CON01_CLK_CORE3_DIV_SHIFT) /* 0x00001F00 */ +/* CLKSEL_CON02 */ +#define CRU_CLKSEL_CON02_OFFSET (0x108U) +#define CRU_CLKSEL_CON02_SCLK_CORE_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON02_SCLK_CORE_SRC_DIV_MASK (0xFU << CRU_CLKSEL_CON02_SCLK_CORE_SRC_DIV_SHIFT) /* 0x0000000F */ +#define CRU_CLKSEL_CON02_SCLK_CORE_SRC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON02_SCLK_CORE_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON02_SCLK_CORE_SRC_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON02_SCLK_CORE_PRE_SEL_SHIFT (15U) +#define CRU_CLKSEL_CON02_SCLK_CORE_PRE_SEL_MASK (0x1U << CRU_CLKSEL_CON02_SCLK_CORE_PRE_SEL_SHIFT) /* 0x00008000 */ +/* CLKSEL_CON03 */ +#define CRU_CLKSEL_CON03_OFFSET (0x10CU) +#define CRU_CLKSEL_CON03_ATCLK_CORE_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON03_ATCLK_CORE_DIV_MASK (0x1FU << CRU_CLKSEL_CON03_ATCLK_CORE_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON03_GICCLK_CORE_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON03_GICCLK_CORE_DIV_MASK (0x1FU << CRU_CLKSEL_CON03_GICCLK_CORE_DIV_SHIFT) /* 0x00001F00 */ +/* CLKSEL_CON04 */ +#define CRU_CLKSEL_CON04_OFFSET (0x110U) +#define CRU_CLKSEL_CON04_PCLK_CORE_PRE_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON04_PCLK_CORE_PRE_DIV_MASK (0x1FU << CRU_CLKSEL_CON04_PCLK_CORE_PRE_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON04_PERIPHCLK_CORE_PRE_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON04_PERIPHCLK_CORE_PRE_DIV_MASK (0x1FU << CRU_CLKSEL_CON04_PERIPHCLK_CORE_PRE_DIV_SHIFT) /* 0x00001F00 */ +/* CLKSEL_CON05 */ +#define CRU_CLKSEL_CON05_OFFSET (0x114U) +#define CRU_CLKSEL_CON05_RESERVED_SHIFT (0U) +#define CRU_CLKSEL_CON05_RESERVED_MASK (0xFFU << CRU_CLKSEL_CON05_RESERVED_SHIFT) /* 0x000000FF */ +#define CRU_CLKSEL_CON05_ACLK_CORE_NDFT_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON05_ACLK_CORE_NDFT_DIV_MASK (0x1FU << CRU_CLKSEL_CON05_ACLK_CORE_NDFT_DIV_SHIFT) /* 0x00001F00 */ +#define CRU_CLKSEL_CON05_ACLK_CORE_NIU2BUS_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON05_ACLK_CORE_NIU2BUS_SEL_MASK (0x3U << CRU_CLKSEL_CON05_ACLK_CORE_NIU2BUS_SEL_SHIFT) /* 0x0000C000 */ +/* CLKSEL_CON06 */ +#define CRU_CLKSEL_CON06_OFFSET (0x118U) +#define CRU_CLKSEL_CON06_CLK_GPU_PRE_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON06_CLK_GPU_PRE_DIV_MASK (0xFU << CRU_CLKSEL_CON06_CLK_GPU_PRE_DIV_SHIFT) /* 0x0000000F */ +#define CRU_CLKSEL_CON06_CLK_GPU_PRE_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON06_CLK_GPU_PRE_SEL_MASK (0x3U << CRU_CLKSEL_CON06_CLK_GPU_PRE_SEL_SHIFT) /* 0x000000C0 */ +#define CRU_CLKSEL_CON06_ACLK_GPU_PRE_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON06_ACLK_GPU_PRE_DIV_MASK (0x3U << CRU_CLKSEL_CON06_ACLK_GPU_PRE_DIV_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON06_CLK_GPU_PRE_MUX_SEL_SHIFT (11U) +#define CRU_CLKSEL_CON06_CLK_GPU_PRE_MUX_SEL_MASK (0x1U << CRU_CLKSEL_CON06_CLK_GPU_PRE_MUX_SEL_SHIFT) /* 0x00000800 */ +#define CRU_CLKSEL_CON06_PCLK_GPU_PRE_DIV_SHIFT (12U) +#define CRU_CLKSEL_CON06_PCLK_GPU_PRE_DIV_MASK (0xFU << CRU_CLKSEL_CON06_PCLK_GPU_PRE_DIV_SHIFT) /* 0x0000F000 */ +/* CLKSEL_CON07 */ +#define CRU_CLKSEL_CON07_OFFSET (0x11CU) +#define CRU_CLKSEL_CON07_CLK_NPU_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON07_CLK_NPU_SRC_DIV_MASK (0xFU << CRU_CLKSEL_CON07_CLK_NPU_SRC_DIV_SHIFT) /* 0x0000000F */ +#define CRU_CLKSEL_CON07_CLK_NPU_NP5_DIV_SHIFT (4U) +#define CRU_CLKSEL_CON07_CLK_NPU_NP5_DIV_MASK (0x3U << CRU_CLKSEL_CON07_CLK_NPU_NP5_DIV_SHIFT) /* 0x00000030 */ +#define CRU_CLKSEL_CON07_CLK_NPU_SRC_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON07_CLK_NPU_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON07_CLK_NPU_SRC_SEL_SHIFT) /* 0x00000040 */ +#define CRU_CLKSEL_CON07_CLK_NPU_NP5_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON07_CLK_NPU_NP5_SEL_MASK (0x1U << CRU_CLKSEL_CON07_CLK_NPU_NP5_SEL_SHIFT) /* 0x00000080 */ +#define CRU_CLKSEL_CON07_CLK_NPU_PRE_NDFT_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON07_CLK_NPU_PRE_NDFT_SEL_MASK (0x1U << CRU_CLKSEL_CON07_CLK_NPU_PRE_NDFT_SEL_SHIFT) /* 0x00000100 */ +#define CRU_CLKSEL_CON07_CLK_NPU_PRE_MUX_SEL_SHIFT (15U) +#define CRU_CLKSEL_CON07_CLK_NPU_PRE_MUX_SEL_MASK (0x1U << CRU_CLKSEL_CON07_CLK_NPU_PRE_MUX_SEL_SHIFT) /* 0x00008000 */ +/* CLKSEL_CON08 */ +#define CRU_CLKSEL_CON08_OFFSET (0x120U) +#define CRU_CLKSEL_CON08_HCLK_NPU_PRE_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON08_HCLK_NPU_PRE_DIV_MASK (0xFU << CRU_CLKSEL_CON08_HCLK_NPU_PRE_DIV_SHIFT) /* 0x0000000F */ +#define CRU_CLKSEL_CON08_PCLK_NPU_PRE_DIV_SHIFT (4U) +#define CRU_CLKSEL_CON08_PCLK_NPU_PRE_DIV_MASK (0xFU << CRU_CLKSEL_CON08_PCLK_NPU_PRE_DIV_SHIFT) /* 0x000000F0 */ +/* CLKSEL_CON09 */ +#define CRU_CLKSEL_CON09_OFFSET (0x124U) +#define CRU_CLKSEL_CON09_CLK_DDRPHY1X_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON09_CLK_DDRPHY1X_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON09_CLK_DDRPHY1X_SRC_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON09_CLK_DDRPHY1X_SRC_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON09_CLK_DDRPHY1X_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON09_CLK_DDRPHY1X_SRC_SEL_SHIFT) /* 0x000000C0 */ +#define CRU_CLKSEL_CON09_CLK_DDRPHY1X_SEL_SHIFT (15U) +#define CRU_CLKSEL_CON09_CLK_DDRPHY1X_SEL_MASK (0x1U << CRU_CLKSEL_CON09_CLK_DDRPHY1X_SEL_SHIFT) /* 0x00008000 */ +/* CLKSEL_CON10 */ +#define CRU_CLKSEL_CON10_OFFSET (0x128U) +#define CRU_CLKSEL_CON10_CLK_MSCH_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON10_CLK_MSCH_DIV_MASK (0x3U << CRU_CLKSEL_CON10_CLK_MSCH_DIV_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON10_ACLK_PERIMID_SEL_SHIFT (4U) +#define CRU_CLKSEL_CON10_ACLK_PERIMID_SEL_MASK (0x3U << CRU_CLKSEL_CON10_ACLK_PERIMID_SEL_SHIFT) /* 0x00000030 */ +#define CRU_CLKSEL_CON10_HCLK_PERIMID_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON10_HCLK_PERIMID_SEL_MASK (0x3U << CRU_CLKSEL_CON10_HCLK_PERIMID_SEL_SHIFT) /* 0x000000C0 */ +#define CRU_CLKSEL_CON10_ACLK_GIC_AUDIO_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON10_ACLK_GIC_AUDIO_SEL_MASK (0x3U << CRU_CLKSEL_CON10_ACLK_GIC_AUDIO_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON10_HCLK_GIC_AUDIO_SEL_SHIFT (10U) +#define CRU_CLKSEL_CON10_HCLK_GIC_AUDIO_SEL_MASK (0x3U << CRU_CLKSEL_CON10_HCLK_GIC_AUDIO_SEL_SHIFT) /* 0x00000C00 */ +#define CRU_CLKSEL_CON10_DCLK_SDMMC_BUFFER_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON10_DCLK_SDMMC_BUFFER_SEL_MASK (0x3U << CRU_CLKSEL_CON10_DCLK_SDMMC_BUFFER_SEL_SHIFT) /* 0x00003000 */ +/* CLKSEL_CON11 */ +#define CRU_CLKSEL_CON11_OFFSET (0x12CU) +#define CRU_CLKSEL_CON11_CLK_I2S0_8CH_TX_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON11_CLK_I2S0_8CH_TX_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON11_CLK_I2S0_8CH_TX_SRC_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON11_CLK_I2S0_8CH_TX_SRC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON11_CLK_I2S0_8CH_TX_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON11_CLK_I2S0_8CH_TX_SRC_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON11_MCLK_I2S0_8CH_TX_SEL_SHIFT (10U) +#define CRU_CLKSEL_CON11_MCLK_I2S0_8CH_TX_SEL_MASK (0x3U << CRU_CLKSEL_CON11_MCLK_I2S0_8CH_TX_SEL_SHIFT) /* 0x00000C00 */ +#define CRU_CLKSEL_CON11_I2S0_MCLKOUT_TX_SEL_SHIFT (15U) +#define CRU_CLKSEL_CON11_I2S0_MCLKOUT_TX_SEL_MASK (0x1U << CRU_CLKSEL_CON11_I2S0_MCLKOUT_TX_SEL_SHIFT) /* 0x00008000 */ +/* CLKSEL_CON12 */ +#define CRU_CLKSEL_CON12_OFFSET (0x130U) +#define CRU_CLKSEL_CON12_CLK_I2S0_8CH_TX_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON12_CLK_I2S0_8CH_TX_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON12_CLK_I2S0_8CH_TX_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON13 */ +#define CRU_CLKSEL_CON13_OFFSET (0x134U) +#define CRU_CLKSEL_CON13_CLK_I2S0_8CH_RX_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON13_CLK_I2S0_8CH_RX_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON13_CLK_I2S0_8CH_RX_SRC_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON13_CLK_I2S0_8CH_RX_SRC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON13_CLK_I2S0_8CH_RX_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON13_CLK_I2S0_8CH_RX_SRC_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON13_MCLK_I2S0_8CH_RX_SEL_SHIFT (10U) +#define CRU_CLKSEL_CON13_MCLK_I2S0_8CH_RX_SEL_MASK (0x3U << CRU_CLKSEL_CON13_MCLK_I2S0_8CH_RX_SEL_SHIFT) /* 0x00000C00 */ +#define CRU_CLKSEL_CON13_I2S0_MCLKOUT_RX_SEL_SHIFT (15U) +#define CRU_CLKSEL_CON13_I2S0_MCLKOUT_RX_SEL_MASK (0x1U << CRU_CLKSEL_CON13_I2S0_MCLKOUT_RX_SEL_SHIFT) /* 0x00008000 */ +/* CLKSEL_CON14 */ +#define CRU_CLKSEL_CON14_OFFSET (0x138U) +#define CRU_CLKSEL_CON14_CLK_I2S0_8CH_RX_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON14_CLK_I2S0_8CH_RX_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON14_CLK_I2S0_8CH_RX_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON15 */ +#define CRU_CLKSEL_CON15_OFFSET (0x13CU) +#define CRU_CLKSEL_CON15_CLK_I2S1_8CH_TX_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON15_CLK_I2S1_8CH_TX_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON15_CLK_I2S1_8CH_TX_SRC_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON15_CLK_I2S1_8CH_TX_SRC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON15_CLK_I2S1_8CH_TX_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON15_CLK_I2S1_8CH_TX_SRC_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON15_MCLK_I2S1_8CH_TX_SEL_SHIFT (10U) +#define CRU_CLKSEL_CON15_MCLK_I2S1_8CH_TX_SEL_MASK (0x3U << CRU_CLKSEL_CON15_MCLK_I2S1_8CH_TX_SEL_SHIFT) /* 0x00000C00 */ +#define CRU_CLKSEL_CON15_I2S1_MCLKOUT_TX_SEL_SHIFT (15U) +#define CRU_CLKSEL_CON15_I2S1_MCLKOUT_TX_SEL_MASK (0x1U << CRU_CLKSEL_CON15_I2S1_MCLKOUT_TX_SEL_SHIFT) /* 0x00008000 */ +/* CLKSEL_CON16 */ +#define CRU_CLKSEL_CON16_OFFSET (0x140U) +#define CRU_CLKSEL_CON16_CLK_I2S1_8CH_TX_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON16_CLK_I2S1_8CH_TX_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON16_CLK_I2S1_8CH_TX_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON17 */ +#define CRU_CLKSEL_CON17_OFFSET (0x144U) +#define CRU_CLKSEL_CON17_CLK_I2S1_8CH_RX_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON17_CLK_I2S1_8CH_RX_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON17_CLK_I2S1_8CH_RX_SRC_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON17_CLK_I2S1_8CH_RX_SRC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON17_CLK_I2S1_8CH_RX_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON17_CLK_I2S1_8CH_RX_SRC_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON17_MCLK_I2S1_8CH_RX_SEL_SHIFT (10U) +#define CRU_CLKSEL_CON17_MCLK_I2S1_8CH_RX_SEL_MASK (0x3U << CRU_CLKSEL_CON17_MCLK_I2S1_8CH_RX_SEL_SHIFT) /* 0x00000C00 */ +#define CRU_CLKSEL_CON17_I2S1_MCLKOUT_RX_SEL_SHIFT (15U) +#define CRU_CLKSEL_CON17_I2S1_MCLKOUT_RX_SEL_MASK (0x1U << CRU_CLKSEL_CON17_I2S1_MCLKOUT_RX_SEL_SHIFT) /* 0x00008000 */ +/* CLKSEL_CON18 */ +#define CRU_CLKSEL_CON18_OFFSET (0x148U) +#define CRU_CLKSEL_CON18_CLK_I2S1_8CH_RX_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON18_CLK_I2S1_8CH_RX_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON18_CLK_I2S1_8CH_RX_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON19 */ +#define CRU_CLKSEL_CON19_OFFSET (0x14CU) +#define CRU_CLKSEL_CON19_CLK_I2S2_2CH_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON19_CLK_I2S2_2CH_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON19_CLK_I2S2_2CH_SRC_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON19_CLK_I2S2_2CH_SRC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON19_CLK_I2S2_2CH_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON19_CLK_I2S2_2CH_SRC_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON19_MCLK_I2S2_2CH_SEL_SHIFT (10U) +#define CRU_CLKSEL_CON19_MCLK_I2S2_2CH_SEL_MASK (0x3U << CRU_CLKSEL_CON19_MCLK_I2S2_2CH_SEL_SHIFT) /* 0x00000C00 */ +#define CRU_CLKSEL_CON19_I2S2_MCLKOUT_SEL_SHIFT (15U) +#define CRU_CLKSEL_CON19_I2S2_MCLKOUT_SEL_MASK (0x1U << CRU_CLKSEL_CON19_I2S2_MCLKOUT_SEL_SHIFT) /* 0x00008000 */ +/* CLKSEL_CON20 */ +#define CRU_CLKSEL_CON20_OFFSET (0x150U) +#define CRU_CLKSEL_CON20_CLK_I2S2_2CH_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON20_CLK_I2S2_2CH_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON20_CLK_I2S2_2CH_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON21 */ +#define CRU_CLKSEL_CON21_OFFSET (0x154U) +#define CRU_CLKSEL_CON21_CLK_I2S3_2CH_TX_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON21_CLK_I2S3_2CH_TX_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON21_CLK_I2S3_2CH_TX_SRC_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON21_CLK_I2S3_2CH_TX_SRC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON21_CLK_I2S3_2CH_TX_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON21_CLK_I2S3_2CH_TX_SRC_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON21_MCLK_I2S3_2CH_TX_SEL_SHIFT (10U) +#define CRU_CLKSEL_CON21_MCLK_I2S3_2CH_TX_SEL_MASK (0x3U << CRU_CLKSEL_CON21_MCLK_I2S3_2CH_TX_SEL_SHIFT) /* 0x00000C00 */ +#define CRU_CLKSEL_CON21_I2S3_MCLKOUT_TX_SEL_SHIFT (15U) +#define CRU_CLKSEL_CON21_I2S3_MCLKOUT_TX_SEL_MASK (0x1U << CRU_CLKSEL_CON21_I2S3_MCLKOUT_TX_SEL_SHIFT) /* 0x00008000 */ +/* CLKSEL_CON22 */ +#define CRU_CLKSEL_CON22_OFFSET (0x158U) +#define CRU_CLKSEL_CON22_CLK_I2S3_2CH_TX_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON22_CLK_I2S3_2CH_TX_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON22_CLK_I2S3_2CH_TX_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON23 */ +#define CRU_CLKSEL_CON23_OFFSET (0x15CU) +#define CRU_CLKSEL_CON23_MCLK_SPDIF_8CH_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON23_MCLK_SPDIF_8CH_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON23_MCLK_SPDIF_8CH_SRC_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON23_MCLK_PDM_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON23_MCLK_PDM_SEL_MASK (0x3U << CRU_CLKSEL_CON23_MCLK_PDM_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON23_CLK_ACDCDIG_I2C_SEL_SHIFT (10U) +#define CRU_CLKSEL_CON23_CLK_ACDCDIG_I2C_SEL_MASK (0x3U << CRU_CLKSEL_CON23_CLK_ACDCDIG_I2C_SEL_SHIFT) /* 0x00000C00 */ +#define CRU_CLKSEL_CON23_MCLK_SPDIF_8CH_SRC_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON23_MCLK_SPDIF_8CH_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON23_MCLK_SPDIF_8CH_SRC_SEL_SHIFT) /* 0x00004000 */ +#define CRU_CLKSEL_CON23_MCLK_SPDIF_8CH_SEL_SHIFT (15U) +#define CRU_CLKSEL_CON23_MCLK_SPDIF_8CH_SEL_MASK (0x1U << CRU_CLKSEL_CON23_MCLK_SPDIF_8CH_SEL_SHIFT) /* 0x00008000 */ +/* CLKSEL_CON24 */ +#define CRU_CLKSEL_CON24_OFFSET (0x160U) +#define CRU_CLKSEL_CON24_MCLK_SPDIF_8CH_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON24_MCLK_SPDIF_8CH_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON24_MCLK_SPDIF_8CH_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON25 */ +#define CRU_CLKSEL_CON25_OFFSET (0x164U) +#define CRU_CLKSEL_CON25_SCLK_AUDPWM_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON25_SCLK_AUDPWM_SRC_DIV_MASK (0x3FU << CRU_CLKSEL_CON25_SCLK_AUDPWM_SRC_DIV_SHIFT) /* 0x0000003F */ +#define CRU_CLKSEL_CON25_SCLK_AUDPWM_SRC_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON25_SCLK_AUDPWM_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON25_SCLK_AUDPWM_SRC_SEL_SHIFT) /* 0x00004000 */ +#define CRU_CLKSEL_CON25_SCLK_AUDPWM_SEL_SHIFT (15U) +#define CRU_CLKSEL_CON25_SCLK_AUDPWM_SEL_MASK (0x1U << CRU_CLKSEL_CON25_SCLK_AUDPWM_SEL_SHIFT) /* 0x00008000 */ +/* CLKSEL_CON26 */ +#define CRU_CLKSEL_CON26_OFFSET (0x168U) +#define CRU_CLKSEL_CON26_SCLK_AUDPWM_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON26_SCLK_AUDPWM_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON26_SCLK_AUDPWM_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON27 */ +#define CRU_CLKSEL_CON27_OFFSET (0x16CU) +#define CRU_CLKSEL_CON27_ACLK_SECURE_FLASH_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON27_ACLK_SECURE_FLASH_SEL_MASK (0x3U << CRU_CLKSEL_CON27_ACLK_SECURE_FLASH_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON27_HCLK_SECURE_FLASH_SEL_SHIFT (2U) +#define CRU_CLKSEL_CON27_HCLK_SECURE_FLASH_SEL_MASK (0x3U << CRU_CLKSEL_CON27_HCLK_SECURE_FLASH_SEL_SHIFT) /* 0x0000000C */ +#define CRU_CLKSEL_CON27_CLK_CRYPTO_NS_CORE_SEL_SHIFT (4U) +#define CRU_CLKSEL_CON27_CLK_CRYPTO_NS_CORE_SEL_MASK (0x3U << CRU_CLKSEL_CON27_CLK_CRYPTO_NS_CORE_SEL_SHIFT) /* 0x00000030 */ +#define CRU_CLKSEL_CON27_CLK_CRYPTO_NS_PKA_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON27_CLK_CRYPTO_NS_PKA_SEL_MASK (0x3U << CRU_CLKSEL_CON27_CLK_CRYPTO_NS_PKA_SEL_SHIFT) /* 0x000000C0 */ +/* CLKSEL_CON28 */ +#define CRU_CLKSEL_CON28_OFFSET (0x170U) +#define CRU_CLKSEL_CON28_NCLK_NANDC_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON28_NCLK_NANDC_SEL_MASK (0x3U << CRU_CLKSEL_CON28_NCLK_NANDC_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON28_SCLK_SFC_SEL_SHIFT (4U) +#define CRU_CLKSEL_CON28_SCLK_SFC_SEL_MASK (0x7U << CRU_CLKSEL_CON28_SCLK_SFC_SEL_SHIFT) /* 0x00000070 */ +#define CRU_CLKSEL_CON28_BCLK_EMMC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON28_BCLK_EMMC_SEL_MASK (0x3U << CRU_CLKSEL_CON28_BCLK_EMMC_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON28_CCLK_EMMC_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON28_CCLK_EMMC_SEL_MASK (0x7U << CRU_CLKSEL_CON28_CCLK_EMMC_SEL_SHIFT) /* 0x00007000 */ +/* CLKSEL_CON29 */ +#define CRU_CLKSEL_CON29_OFFSET (0x174U) +#define CRU_CLKSEL_CON29_ACLK_PIPE_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON29_ACLK_PIPE_SEL_MASK (0x3U << CRU_CLKSEL_CON29_ACLK_PIPE_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON29_PCLK_PIPE_DIV_SHIFT (4U) +#define CRU_CLKSEL_CON29_PCLK_PIPE_DIV_MASK (0xFU << CRU_CLKSEL_CON29_PCLK_PIPE_DIV_SHIFT) /* 0x000000F0 */ +#define CRU_CLKSEL_CON29_CLK_USB3OTG0_SUSPEND_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON29_CLK_USB3OTG0_SUSPEND_SEL_MASK (0x1U << CRU_CLKSEL_CON29_CLK_USB3OTG0_SUSPEND_SEL_SHIFT) /* 0x00000100 */ +#define CRU_CLKSEL_CON29_CLK_USB3OTG1_SUSPEND_SEL_SHIFT (9U) +#define CRU_CLKSEL_CON29_CLK_USB3OTG1_SUSPEND_SEL_MASK (0x1U << CRU_CLKSEL_CON29_CLK_USB3OTG1_SUSPEND_SEL_SHIFT) /* 0x00000200 */ +#define CRU_CLKSEL_CON29_CLK_XPCS_EEE_SEL_SHIFT (13U) +#define CRU_CLKSEL_CON29_CLK_XPCS_EEE_SEL_MASK (0x1U << CRU_CLKSEL_CON29_CLK_XPCS_EEE_SEL_SHIFT) /* 0x00002000 */ +/* CLKSEL_CON30 */ +#define CRU_CLKSEL_CON30_OFFSET (0x178U) +#define CRU_CLKSEL_CON30_ACLK_PHP_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON30_ACLK_PHP_SEL_MASK (0x3U << CRU_CLKSEL_CON30_ACLK_PHP_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON30_HCLK_PHP_SEL_SHIFT (2U) +#define CRU_CLKSEL_CON30_HCLK_PHP_SEL_MASK (0x3U << CRU_CLKSEL_CON30_HCLK_PHP_SEL_SHIFT) /* 0x0000000C */ +#define CRU_CLKSEL_CON30_PCLK_PHP_DIV_SHIFT (4U) +#define CRU_CLKSEL_CON30_PCLK_PHP_DIV_MASK (0xFU << CRU_CLKSEL_CON30_PCLK_PHP_DIV_SHIFT) /* 0x000000F0 */ +#define CRU_CLKSEL_CON30_CLK_SDMMC0_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON30_CLK_SDMMC0_SEL_MASK (0x7U << CRU_CLKSEL_CON30_CLK_SDMMC0_SEL_SHIFT) /* 0x00000700 */ +#define CRU_CLKSEL_CON30_CLK_SDMMC1_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON30_CLK_SDMMC1_SEL_MASK (0x7U << CRU_CLKSEL_CON30_CLK_SDMMC1_SEL_SHIFT) /* 0x00007000 */ +/* CLKSEL_CON31 */ +#define CRU_CLKSEL_CON31_OFFSET (0x17CU) +#define CRU_CLKSEL_CON31_RMII0_MODE_SHIFT (0U) +#define CRU_CLKSEL_CON31_RMII0_MODE_MASK (0x3U << CRU_CLKSEL_CON31_RMII0_MODE_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON31_RMII0_EXTCLK_SEL_SHIFT (2U) +#define CRU_CLKSEL_CON31_RMII0_EXTCLK_SEL_MASK (0x1U << CRU_CLKSEL_CON31_RMII0_EXTCLK_SEL_SHIFT) /* 0x00000004 */ +#define CRU_CLKSEL_CON31_RMII0_CLK_SEL_SHIFT (3U) +#define CRU_CLKSEL_CON31_RMII0_CLK_SEL_MASK (0x1U << CRU_CLKSEL_CON31_RMII0_CLK_SEL_SHIFT) /* 0x00000008 */ +#define CRU_CLKSEL_CON31_RGMII0_CLK_SEL_SHIFT (4U) +#define CRU_CLKSEL_CON31_RGMII0_CLK_SEL_MASK (0x3U << CRU_CLKSEL_CON31_RGMII0_CLK_SEL_SHIFT) /* 0x00000030 */ +#define CRU_CLKSEL_CON31_CLK_MAC0_2TOP_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON31_CLK_MAC0_2TOP_SEL_MASK (0x3U << CRU_CLKSEL_CON31_CLK_MAC0_2TOP_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON31_CLK_GMAC0_PTP_REF_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON31_CLK_GMAC0_PTP_REF_SEL_MASK (0x3U << CRU_CLKSEL_CON31_CLK_GMAC0_PTP_REF_SEL_SHIFT) /* 0x00003000 */ +#define CRU_CLKSEL_CON31_CLK_MAC0_OUT_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON31_CLK_MAC0_OUT_SEL_MASK (0x3U << CRU_CLKSEL_CON31_CLK_MAC0_OUT_SEL_SHIFT) /* 0x0000C000 */ +/* CLKSEL_CON32 */ +#define CRU_CLKSEL_CON32_OFFSET (0x180U) +#define CRU_CLKSEL_CON32_ACLK_USB_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON32_ACLK_USB_SEL_MASK (0x3U << CRU_CLKSEL_CON32_ACLK_USB_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON32_HCLK_USB_SEL_SHIFT (2U) +#define CRU_CLKSEL_CON32_HCLK_USB_SEL_MASK (0x3U << CRU_CLKSEL_CON32_HCLK_USB_SEL_SHIFT) /* 0x0000000C */ +#define CRU_CLKSEL_CON32_PCLK_USB_DIV_SHIFT (4U) +#define CRU_CLKSEL_CON32_PCLK_USB_DIV_MASK (0xFU << CRU_CLKSEL_CON32_PCLK_USB_DIV_SHIFT) /* 0x000000F0 */ +#define CRU_CLKSEL_CON32_CLK_SDMMC2_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON32_CLK_SDMMC2_SEL_MASK (0x7U << CRU_CLKSEL_CON32_CLK_SDMMC2_SEL_SHIFT) /* 0x00000700 */ +/* CLKSEL_CON33 */ +#define CRU_CLKSEL_CON33_OFFSET (0x184U) +#define CRU_CLKSEL_CON33_RMII1_MODE_SHIFT (0U) +#define CRU_CLKSEL_CON33_RMII1_MODE_MASK (0x3U << CRU_CLKSEL_CON33_RMII1_MODE_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON33_RMII1_EXTCLK_SEL_SHIFT (2U) +#define CRU_CLKSEL_CON33_RMII1_EXTCLK_SEL_MASK (0x1U << CRU_CLKSEL_CON33_RMII1_EXTCLK_SEL_SHIFT) /* 0x00000004 */ +#define CRU_CLKSEL_CON33_RMII1_CLK_SEL_SHIFT (3U) +#define CRU_CLKSEL_CON33_RMII1_CLK_SEL_MASK (0x1U << CRU_CLKSEL_CON33_RMII1_CLK_SEL_SHIFT) /* 0x00000008 */ +#define CRU_CLKSEL_CON33_RGMII1_CLK_SEL_SHIFT (4U) +#define CRU_CLKSEL_CON33_RGMII1_CLK_SEL_MASK (0x3U << CRU_CLKSEL_CON33_RGMII1_CLK_SEL_SHIFT) /* 0x00000030 */ +#define CRU_CLKSEL_CON33_CLK_MAC1_2TOP_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON33_CLK_MAC1_2TOP_SEL_MASK (0x3U << CRU_CLKSEL_CON33_CLK_MAC1_2TOP_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON33_CLK_GMAC1_PTP_REF_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON33_CLK_GMAC1_PTP_REF_SEL_MASK (0x3U << CRU_CLKSEL_CON33_CLK_GMAC1_PTP_REF_SEL_SHIFT) /* 0x00003000 */ +#define CRU_CLKSEL_CON33_CLK_MAC1_OUT_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON33_CLK_MAC1_OUT_SEL_MASK (0x3U << CRU_CLKSEL_CON33_CLK_MAC1_OUT_SEL_SHIFT) /* 0x0000C000 */ +/* CLKSEL_CON34 */ +#define CRU_CLKSEL_CON34_OFFSET (0x188U) +#define CRU_CLKSEL_CON34_ACLK_VI_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON34_ACLK_VI_SEL_MASK (0x3U << CRU_CLKSEL_CON34_ACLK_VI_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON34_HCLK_VI_DIV_SHIFT (4U) +#define CRU_CLKSEL_CON34_HCLK_VI_DIV_MASK (0xFU << CRU_CLKSEL_CON34_HCLK_VI_DIV_SHIFT) /* 0x000000F0 */ +#define CRU_CLKSEL_CON34_PCLK_VI_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON34_PCLK_VI_DIV_MASK (0xFU << CRU_CLKSEL_CON34_PCLK_VI_DIV_SHIFT) /* 0x00000F00 */ +#define CRU_CLKSEL_CON34_DCLK_VICAP1_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON34_DCLK_VICAP1_SEL_MASK (0x3U << CRU_CLKSEL_CON34_DCLK_VICAP1_SEL_SHIFT) /* 0x0000C000 */ +/* CLKSEL_CON35 */ +#define CRU_CLKSEL_CON35_OFFSET (0x18CU) +#define CRU_CLKSEL_CON35_CLK_ISP_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON35_CLK_ISP_DIV_MASK (0x1FU << CRU_CLKSEL_CON35_CLK_ISP_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON35_CLK_ISP_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON35_CLK_ISP_SEL_MASK (0x3U << CRU_CLKSEL_CON35_CLK_ISP_SEL_SHIFT) /* 0x000000C0 */ +#define CRU_CLKSEL_CON35_CLK_CIF_OUT_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON35_CLK_CIF_OUT_DIV_MASK (0x3FU << CRU_CLKSEL_CON35_CLK_CIF_OUT_DIV_SHIFT) /* 0x00003F00 */ +#define CRU_CLKSEL_CON35_CLK_CIF_OUT_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON35_CLK_CIF_OUT_SEL_MASK (0x3U << CRU_CLKSEL_CON35_CLK_CIF_OUT_SEL_SHIFT) /* 0x0000C000 */ +/* CLKSEL_CON36 */ +#define CRU_CLKSEL_CON36_OFFSET (0x190U) +#define CRU_CLKSEL_CON36_CLK_CAM0_OUT_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON36_CLK_CAM0_OUT_DIV_MASK (0x3FU << CRU_CLKSEL_CON36_CLK_CAM0_OUT_DIV_SHIFT) /* 0x0000003F */ +#define CRU_CLKSEL_CON36_CLK_CAM0_OUT_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON36_CLK_CAM0_OUT_SEL_MASK (0x3U << CRU_CLKSEL_CON36_CLK_CAM0_OUT_SEL_SHIFT) /* 0x000000C0 */ +#define CRU_CLKSEL_CON36_CLK_CAM1_OUT_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON36_CLK_CAM1_OUT_DIV_MASK (0x3FU << CRU_CLKSEL_CON36_CLK_CAM1_OUT_DIV_SHIFT) /* 0x00003F00 */ +#define CRU_CLKSEL_CON36_CLK_CAM1_OUT_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON36_CLK_CAM1_OUT_SEL_MASK (0x3U << CRU_CLKSEL_CON36_CLK_CAM1_OUT_SEL_SHIFT) /* 0x0000C000 */ +/* CLKSEL_CON37 */ +#define CRU_CLKSEL_CON37_OFFSET (0x194U) +#define CRU_CLKSEL_CON37_ACLK_VO_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON37_ACLK_VO_SEL_MASK (0x3U << CRU_CLKSEL_CON37_ACLK_VO_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON37_HCLK_VO_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON37_HCLK_VO_DIV_MASK (0xFU << CRU_CLKSEL_CON37_HCLK_VO_DIV_SHIFT) /* 0x00000F00 */ +#define CRU_CLKSEL_CON37_PCLK_VO_DIV_SHIFT (12U) +#define CRU_CLKSEL_CON37_PCLK_VO_DIV_MASK (0xFU << CRU_CLKSEL_CON37_PCLK_VO_DIV_SHIFT) /* 0x0000F000 */ +/* CLKSEL_CON38 */ +#define CRU_CLKSEL_CON38_OFFSET (0x198U) +#define CRU_CLKSEL_CON38_ACLK_VOP_PRE_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON38_ACLK_VOP_PRE_DIV_MASK (0x1FU << CRU_CLKSEL_CON38_ACLK_VOP_PRE_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON38_ACLK_VOP_PRE_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON38_ACLK_VOP_PRE_SEL_MASK (0x3U << CRU_CLKSEL_CON38_ACLK_VOP_PRE_SEL_SHIFT) /* 0x000000C0 */ +#define CRU_CLKSEL_CON38_CLK_EDP_200M_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON38_CLK_EDP_200M_SEL_MASK (0x3U << CRU_CLKSEL_CON38_CLK_EDP_200M_SEL_SHIFT) /* 0x00000300 */ +/* CLKSEL_CON39 */ +#define CRU_CLKSEL_CON39_OFFSET (0x19CU) +#define CRU_CLKSEL_CON39_DCLK0_VOP_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON39_DCLK0_VOP_DIV_MASK (0xFFU << CRU_CLKSEL_CON39_DCLK0_VOP_DIV_SHIFT) /* 0x000000FF */ +#define CRU_CLKSEL_CON39_DCLK0_VOP_SEL_SHIFT (10U) +#define CRU_CLKSEL_CON39_DCLK0_VOP_SEL_MASK (0x3U << CRU_CLKSEL_CON39_DCLK0_VOP_SEL_SHIFT) /* 0x00000C00 */ +/* CLKSEL_CON40 */ +#define CRU_CLKSEL_CON40_OFFSET (0x1A0U) +#define CRU_CLKSEL_CON40_DCLK1_VOP_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON40_DCLK1_VOP_DIV_MASK (0xFFU << CRU_CLKSEL_CON40_DCLK1_VOP_DIV_SHIFT) /* 0x000000FF */ +#define CRU_CLKSEL_CON40_DCLK1_VOP_SEL_SHIFT (10U) +#define CRU_CLKSEL_CON40_DCLK1_VOP_SEL_MASK (0x3U << CRU_CLKSEL_CON40_DCLK1_VOP_SEL_SHIFT) /* 0x00000C00 */ +/* CLKSEL_CON41 */ +#define CRU_CLKSEL_CON41_OFFSET (0x1A4U) +#define CRU_CLKSEL_CON41_DCLK2_VOP_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON41_DCLK2_VOP_DIV_MASK (0xFFU << CRU_CLKSEL_CON41_DCLK2_VOP_DIV_SHIFT) /* 0x000000FF */ +#define CRU_CLKSEL_CON41_DCLK2_VOP_SEL_SHIFT (10U) +#define CRU_CLKSEL_CON41_DCLK2_VOP_SEL_MASK (0x3U << CRU_CLKSEL_CON41_DCLK2_VOP_SEL_SHIFT) /* 0x00000C00 */ +/* CLKSEL_CON42 */ +#define CRU_CLKSEL_CON42_OFFSET (0x1A8U) +#define CRU_CLKSEL_CON42_ACLK_VPU_PRE_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON42_ACLK_VPU_PRE_DIV_MASK (0x1FU << CRU_CLKSEL_CON42_ACLK_VPU_PRE_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON42_ACLK_VPU_PRE_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON42_ACLK_VPU_PRE_SEL_MASK (0x1U << CRU_CLKSEL_CON42_ACLK_VPU_PRE_SEL_SHIFT) /* 0x00000080 */ +#define CRU_CLKSEL_CON42_HCLK_VPU_PRE_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON42_HCLK_VPU_PRE_DIV_MASK (0xFU << CRU_CLKSEL_CON42_HCLK_VPU_PRE_DIV_SHIFT) /* 0x00000F00 */ +/* CLKSEL_CON43 */ +#define CRU_CLKSEL_CON43_OFFSET (0x1ACU) +#define CRU_CLKSEL_CON43_ACLK_RGA_PRE_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON43_ACLK_RGA_PRE_SEL_MASK (0x3U << CRU_CLKSEL_CON43_ACLK_RGA_PRE_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON43_CLK_RGA_CORE_SEL_SHIFT (2U) +#define CRU_CLKSEL_CON43_CLK_RGA_CORE_SEL_MASK (0x3U << CRU_CLKSEL_CON43_CLK_RGA_CORE_SEL_SHIFT) /* 0x0000000C */ +#define CRU_CLKSEL_CON43_CLK_IEP_CORE_SEL_SHIFT (4U) +#define CRU_CLKSEL_CON43_CLK_IEP_CORE_SEL_MASK (0x3U << CRU_CLKSEL_CON43_CLK_IEP_CORE_SEL_SHIFT) /* 0x00000030 */ +#define CRU_CLKSEL_CON43_DCLK_EBC_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON43_DCLK_EBC_SEL_MASK (0x3U << CRU_CLKSEL_CON43_DCLK_EBC_SEL_SHIFT) /* 0x000000C0 */ +#define CRU_CLKSEL_CON43_HCLK_RGA_PRE_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON43_HCLK_RGA_PRE_DIV_MASK (0xFU << CRU_CLKSEL_CON43_HCLK_RGA_PRE_DIV_SHIFT) /* 0x00000F00 */ +#define CRU_CLKSEL_CON43_PCLK_RGA_PRE_DIV_SHIFT (12U) +#define CRU_CLKSEL_CON43_PCLK_RGA_PRE_DIV_MASK (0xFU << CRU_CLKSEL_CON43_PCLK_RGA_PRE_DIV_SHIFT) /* 0x0000F000 */ +/* CLKSEL_CON44 */ +#define CRU_CLKSEL_CON44_OFFSET (0x1B0U) +#define CRU_CLKSEL_CON44_ACLK_RKVENC_PRE_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON44_ACLK_RKVENC_PRE_DIV_MASK (0x1FU << CRU_CLKSEL_CON44_ACLK_RKVENC_PRE_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON44_ACLK_RKVENC_PRE_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON44_ACLK_RKVENC_PRE_SEL_MASK (0x3U << CRU_CLKSEL_CON44_ACLK_RKVENC_PRE_SEL_SHIFT) /* 0x000000C0 */ +#define CRU_CLKSEL_CON44_HCLK_RKVENC_PRE_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON44_HCLK_RKVENC_PRE_DIV_MASK (0xFU << CRU_CLKSEL_CON44_HCLK_RKVENC_PRE_DIV_SHIFT) /* 0x00000F00 */ +/* CLKSEL_CON45 */ +#define CRU_CLKSEL_CON45_OFFSET (0x1B4U) +#define CRU_CLKSEL_CON45_CLK_RKVENC_CORE_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON45_CLK_RKVENC_CORE_DIV_MASK (0x1FU << CRU_CLKSEL_CON45_CLK_RKVENC_CORE_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON45_CLK_RKVENC_CORE_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON45_CLK_RKVENC_CORE_SEL_MASK (0x3U << CRU_CLKSEL_CON45_CLK_RKVENC_CORE_SEL_SHIFT) /* 0x0000C000 */ +/* CLKSEL_CON47 */ +#define CRU_CLKSEL_CON47_OFFSET (0x1BCU) +#define CRU_CLKSEL_CON47_ACLK_RKVDEC_PRE_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON47_ACLK_RKVDEC_PRE_DIV_MASK (0x1FU << CRU_CLKSEL_CON47_ACLK_RKVDEC_PRE_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON47_ACLK_RKVDEC_PRE_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON47_ACLK_RKVDEC_PRE_SEL_MASK (0x1U << CRU_CLKSEL_CON47_ACLK_RKVDEC_PRE_SEL_SHIFT) /* 0x00000080 */ +#define CRU_CLKSEL_CON47_HCLK_RKVDEC_PRE_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON47_HCLK_RKVDEC_PRE_DIV_MASK (0xFU << CRU_CLKSEL_CON47_HCLK_RKVDEC_PRE_DIV_SHIFT) /* 0x00000F00 */ +/* CLKSEL_CON48 */ +#define CRU_CLKSEL_CON48_OFFSET (0x1C0U) +#define CRU_CLKSEL_CON48_CLK_RKVDEC_CA_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON48_CLK_RKVDEC_CA_DIV_MASK (0x1FU << CRU_CLKSEL_CON48_CLK_RKVDEC_CA_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON48_CLK_RKVDEC_CA_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON48_CLK_RKVDEC_CA_SEL_MASK (0x3U << CRU_CLKSEL_CON48_CLK_RKVDEC_CA_SEL_SHIFT) /* 0x000000C0 */ +/* CLKSEL_CON49 */ +#define CRU_CLKSEL_CON49_OFFSET (0x1C4U) +#define CRU_CLKSEL_CON49_CLK_RKVDEC_HEVC_CA_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON49_CLK_RKVDEC_HEVC_CA_DIV_MASK (0x1FU << CRU_CLKSEL_CON49_CLK_RKVDEC_HEVC_CA_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON49_CLK_RKVDEC_HEVC_CA_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON49_CLK_RKVDEC_HEVC_CA_SEL_MASK (0x3U << CRU_CLKSEL_CON49_CLK_RKVDEC_HEVC_CA_SEL_SHIFT) /* 0x000000C0 */ +#define CRU_CLKSEL_CON49_CLK_RKVDEC_CORE_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON49_CLK_RKVDEC_CORE_DIV_MASK (0x1FU << CRU_CLKSEL_CON49_CLK_RKVDEC_CORE_DIV_SHIFT) /* 0x00001F00 */ +#define CRU_CLKSEL_CON49_CLK_RKVDEC_CORE_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON49_CLK_RKVDEC_CORE_SEL_MASK (0x3U << CRU_CLKSEL_CON49_CLK_RKVDEC_CORE_SEL_SHIFT) /* 0x0000C000 */ +/* CLKSEL_CON50 */ +#define CRU_CLKSEL_CON50_OFFSET (0x1C8U) +#define CRU_CLKSEL_CON50_ACLK_BUS_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON50_ACLK_BUS_SEL_MASK (0x3U << CRU_CLKSEL_CON50_ACLK_BUS_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON50_PCLK_BUS_SEL_SHIFT (4U) +#define CRU_CLKSEL_CON50_PCLK_BUS_SEL_MASK (0x3U << CRU_CLKSEL_CON50_PCLK_BUS_SEL_SHIFT) /* 0x00000030 */ +/* CLKSEL_CON51 */ +#define CRU_CLKSEL_CON51_OFFSET (0x1CCU) +#define CRU_CLKSEL_CON51_CLK_TSADC_TSEN_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON51_CLK_TSADC_TSEN_DIV_MASK (0x7U << CRU_CLKSEL_CON51_CLK_TSADC_TSEN_DIV_SHIFT) /* 0x00000007 */ +#define CRU_CLKSEL_CON51_CLK_TSADC_TSEN_SEL_SHIFT (4U) +#define CRU_CLKSEL_CON51_CLK_TSADC_TSEN_SEL_MASK (0x3U << CRU_CLKSEL_CON51_CLK_TSADC_TSEN_SEL_SHIFT) /* 0x00000030 */ +#define CRU_CLKSEL_CON51_CLK_TSADC_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON51_CLK_TSADC_DIV_MASK (0x7FU << CRU_CLKSEL_CON51_CLK_TSADC_DIV_SHIFT) /* 0x00007F00 */ +/* CLKSEL_CON52 */ +#define CRU_CLKSEL_CON52_OFFSET (0x1D0U) +#define CRU_CLKSEL_CON52_CLK_UART1_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON52_CLK_UART1_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON52_CLK_UART1_SRC_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON52_CLK_UART1_SRC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON52_CLK_UART1_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON52_CLK_UART1_SRC_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON52_SCLK_UART1_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON52_SCLK_UART1_SEL_MASK (0x3U << CRU_CLKSEL_CON52_SCLK_UART1_SEL_SHIFT) /* 0x00003000 */ +/* CLKSEL_CON53 */ +#define CRU_CLKSEL_CON53_OFFSET (0x1D4U) +#define CRU_CLKSEL_CON53_CLK_UART1_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON53_CLK_UART1_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON53_CLK_UART1_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON54 */ +#define CRU_CLKSEL_CON54_OFFSET (0x1D8U) +#define CRU_CLKSEL_CON54_CLK_UART2_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON54_CLK_UART2_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON54_CLK_UART2_SRC_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON54_CLK_UART2_SRC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON54_CLK_UART2_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON54_CLK_UART2_SRC_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON54_SCLK_UART2_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON54_SCLK_UART2_SEL_MASK (0x3U << CRU_CLKSEL_CON54_SCLK_UART2_SEL_SHIFT) /* 0x00003000 */ +/* CLKSEL_CON55 */ +#define CRU_CLKSEL_CON55_OFFSET (0x1DCU) +#define CRU_CLKSEL_CON55_CLK_UART2_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON55_CLK_UART2_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON55_CLK_UART2_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON56 */ +#define CRU_CLKSEL_CON56_OFFSET (0x1E0U) +#define CRU_CLKSEL_CON56_CLK_UART3_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON56_CLK_UART3_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON56_CLK_UART3_SRC_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON56_CLK_UART3_SRC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON56_CLK_UART3_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON56_CLK_UART3_SRC_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON56_SCLK_UART3_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON56_SCLK_UART3_SEL_MASK (0x3U << CRU_CLKSEL_CON56_SCLK_UART3_SEL_SHIFT) /* 0x00003000 */ +/* CLKSEL_CON57 */ +#define CRU_CLKSEL_CON57_OFFSET (0x1E4U) +#define CRU_CLKSEL_CON57_CLK_UART3_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON57_CLK_UART3_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON57_CLK_UART3_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON58 */ +#define CRU_CLKSEL_CON58_OFFSET (0x1E8U) +#define CRU_CLKSEL_CON58_CLK_UART4_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON58_CLK_UART4_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON58_CLK_UART4_SRC_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON58_CLK_UART4_SRC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON58_CLK_UART4_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON58_CLK_UART4_SRC_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON58_SCLK_UART4_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON58_SCLK_UART4_SEL_MASK (0x3U << CRU_CLKSEL_CON58_SCLK_UART4_SEL_SHIFT) /* 0x00003000 */ +/* CLKSEL_CON59 */ +#define CRU_CLKSEL_CON59_OFFSET (0x1ECU) +#define CRU_CLKSEL_CON59_CLK_UART4_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON59_CLK_UART4_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON59_CLK_UART4_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON60 */ +#define CRU_CLKSEL_CON60_OFFSET (0x1F0U) +#define CRU_CLKSEL_CON60_CLK_UART5_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON60_CLK_UART5_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON60_CLK_UART5_SRC_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON60_CLK_UART5_SRC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON60_CLK_UART5_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON60_CLK_UART5_SRC_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON60_SCLK_UART5_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON60_SCLK_UART5_SEL_MASK (0x3U << CRU_CLKSEL_CON60_SCLK_UART5_SEL_SHIFT) /* 0x00003000 */ +/* CLKSEL_CON61 */ +#define CRU_CLKSEL_CON61_OFFSET (0x1F4U) +#define CRU_CLKSEL_CON61_CLK_UART5_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON61_CLK_UART5_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON61_CLK_UART5_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON62 */ +#define CRU_CLKSEL_CON62_OFFSET (0x1F8U) +#define CRU_CLKSEL_CON62_CLK_UART6_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON62_CLK_UART6_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON62_CLK_UART6_SRC_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON62_CLK_UART6_SRC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON62_CLK_UART6_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON62_CLK_UART6_SRC_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON62_SCLK_UART6_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON62_SCLK_UART6_SEL_MASK (0x3U << CRU_CLKSEL_CON62_SCLK_UART6_SEL_SHIFT) /* 0x00003000 */ +/* CLKSEL_CON63 */ +#define CRU_CLKSEL_CON63_OFFSET (0x1FCU) +#define CRU_CLKSEL_CON63_CLK_UART6_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON63_CLK_UART6_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON63_CLK_UART6_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON64 */ +#define CRU_CLKSEL_CON64_OFFSET (0x200U) +#define CRU_CLKSEL_CON64_CLK_UART7_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON64_CLK_UART7_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON64_CLK_UART7_SRC_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON64_CLK_UART7_SRC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON64_CLK_UART7_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON64_CLK_UART7_SRC_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON64_SCLK_UART7_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON64_SCLK_UART7_SEL_MASK (0x3U << CRU_CLKSEL_CON64_SCLK_UART7_SEL_SHIFT) /* 0x00003000 */ +/* CLKSEL_CON65 */ +#define CRU_CLKSEL_CON65_OFFSET (0x204U) +#define CRU_CLKSEL_CON65_CLK_UART7_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON65_CLK_UART7_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON65_CLK_UART7_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON66 */ +#define CRU_CLKSEL_CON66_OFFSET (0x208U) +#define CRU_CLKSEL_CON66_CLK_UART8_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON66_CLK_UART8_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON66_CLK_UART8_SRC_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON66_CLK_UART8_SRC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON66_CLK_UART8_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON66_CLK_UART8_SRC_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON66_SCLK_UART8_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON66_SCLK_UART8_SEL_MASK (0x3U << CRU_CLKSEL_CON66_SCLK_UART8_SEL_SHIFT) /* 0x00003000 */ +/* CLKSEL_CON67 */ +#define CRU_CLKSEL_CON67_OFFSET (0x20CU) +#define CRU_CLKSEL_CON67_CLK_UART8_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON67_CLK_UART8_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON67_CLK_UART8_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON68 */ +#define CRU_CLKSEL_CON68_OFFSET (0x210U) +#define CRU_CLKSEL_CON68_CLK_UART9_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON68_CLK_UART9_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON68_CLK_UART9_SRC_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON68_CLK_UART9_SRC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON68_CLK_UART9_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON68_CLK_UART9_SRC_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON68_SCLK_UART9_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON68_SCLK_UART9_SEL_MASK (0x3U << CRU_CLKSEL_CON68_SCLK_UART9_SEL_SHIFT) /* 0x00003000 */ +/* CLKSEL_CON69 */ +#define CRU_CLKSEL_CON69_OFFSET (0x214U) +#define CRU_CLKSEL_CON69_CLK_UART9_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON69_CLK_UART9_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON69_CLK_UART9_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON70 */ +#define CRU_CLKSEL_CON70_OFFSET (0x218U) +#define CRU_CLKSEL_CON70_CLK_CAN0_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON70_CLK_CAN0_DIV_MASK (0x1FU << CRU_CLKSEL_CON70_CLK_CAN0_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON70_CLK_CAN0_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON70_CLK_CAN0_SEL_MASK (0x1U << CRU_CLKSEL_CON70_CLK_CAN0_SEL_SHIFT) /* 0x00000080 */ +#define CRU_CLKSEL_CON70_CLK_CAN1_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON70_CLK_CAN1_DIV_MASK (0x1FU << CRU_CLKSEL_CON70_CLK_CAN1_DIV_SHIFT) /* 0x00001F00 */ +#define CRU_CLKSEL_CON70_CLK_CAN1_SEL_SHIFT (15U) +#define CRU_CLKSEL_CON70_CLK_CAN1_SEL_MASK (0x1U << CRU_CLKSEL_CON70_CLK_CAN1_SEL_SHIFT) /* 0x00008000 */ +/* CLKSEL_CON71 */ +#define CRU_CLKSEL_CON71_OFFSET (0x21CU) +#define CRU_CLKSEL_CON71_CLK_CAN2_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON71_CLK_CAN2_DIV_MASK (0x1FU << CRU_CLKSEL_CON71_CLK_CAN2_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON71_CLK_CAN2_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON71_CLK_CAN2_SEL_MASK (0x1U << CRU_CLKSEL_CON71_CLK_CAN2_SEL_SHIFT) /* 0x00000080 */ +#define CRU_CLKSEL_CON71_CLK_I2C_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON71_CLK_I2C_SEL_MASK (0x3U << CRU_CLKSEL_CON71_CLK_I2C_SEL_SHIFT) /* 0x00000300 */ +/* CLKSEL_CON72 */ +#define CRU_CLKSEL_CON72_OFFSET (0x220U) +#define CRU_CLKSEL_CON72_CLK_SPI0_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON72_CLK_SPI0_SEL_MASK (0x3U << CRU_CLKSEL_CON72_CLK_SPI0_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON72_CLK_SPI1_SEL_SHIFT (2U) +#define CRU_CLKSEL_CON72_CLK_SPI1_SEL_MASK (0x3U << CRU_CLKSEL_CON72_CLK_SPI1_SEL_SHIFT) /* 0x0000000C */ +#define CRU_CLKSEL_CON72_CLK_SPI2_SEL_SHIFT (4U) +#define CRU_CLKSEL_CON72_CLK_SPI2_SEL_MASK (0x3U << CRU_CLKSEL_CON72_CLK_SPI2_SEL_SHIFT) /* 0x00000030 */ +#define CRU_CLKSEL_CON72_CLK_SPI3_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON72_CLK_SPI3_SEL_MASK (0x3U << CRU_CLKSEL_CON72_CLK_SPI3_SEL_SHIFT) /* 0x000000C0 */ +#define CRU_CLKSEL_CON72_CLK_PWM1_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON72_CLK_PWM1_SEL_MASK (0x3U << CRU_CLKSEL_CON72_CLK_PWM1_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON72_CLK_PWM2_SEL_SHIFT (10U) +#define CRU_CLKSEL_CON72_CLK_PWM2_SEL_MASK (0x3U << CRU_CLKSEL_CON72_CLK_PWM2_SEL_SHIFT) /* 0x00000C00 */ +#define CRU_CLKSEL_CON72_CLK_PWM3_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON72_CLK_PWM3_SEL_MASK (0x3U << CRU_CLKSEL_CON72_CLK_PWM3_SEL_SHIFT) /* 0x00003000 */ +#define CRU_CLKSEL_CON72_DBCLK_GPIO_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON72_DBCLK_GPIO_SEL_MASK (0x1U << CRU_CLKSEL_CON72_DBCLK_GPIO_SEL_SHIFT) /* 0x00004000 */ +/* CLKSEL_CON73 */ +#define CRU_CLKSEL_CON73_OFFSET (0x224U) +#define CRU_CLKSEL_CON73_ACLK_TOP_HIGH_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON73_ACLK_TOP_HIGH_SEL_MASK (0x3U << CRU_CLKSEL_CON73_ACLK_TOP_HIGH_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON73_ACLK_TOP_LOW_SEL_SHIFT (4U) +#define CRU_CLKSEL_CON73_ACLK_TOP_LOW_SEL_MASK (0x3U << CRU_CLKSEL_CON73_ACLK_TOP_LOW_SEL_SHIFT) /* 0x00000030 */ +#define CRU_CLKSEL_CON73_HCLK_TOP_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON73_HCLK_TOP_SEL_MASK (0x3U << CRU_CLKSEL_CON73_HCLK_TOP_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON73_PCLK_TOP_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON73_PCLK_TOP_SEL_MASK (0x3U << CRU_CLKSEL_CON73_PCLK_TOP_SEL_SHIFT) /* 0x00003000 */ +#define CRU_CLKSEL_CON73_CLK_OTPC_ARB_SEL_SHIFT (15U) +#define CRU_CLKSEL_CON73_CLK_OTPC_ARB_SEL_MASK (0x1U << CRU_CLKSEL_CON73_CLK_OTPC_ARB_SEL_SHIFT) /* 0x00008000 */ +/* CLKSEL_CON74 */ +#define CRU_CLKSEL_CON74_OFFSET (0x228U) +#define CRU_CLKSEL_CON74_CLK_TESTOUT_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON74_CLK_TESTOUT_DIV_MASK (0xFFU << CRU_CLKSEL_CON74_CLK_TESTOUT_DIV_SHIFT) /* 0x000000FF */ +#define CRU_CLKSEL_CON74_CLK_TESTOUT_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON74_CLK_TESTOUT_SEL_MASK (0x1FU << CRU_CLKSEL_CON74_CLK_TESTOUT_SEL_SHIFT) /* 0x00001F00 */ +/* CLKSEL_CON75 */ +#define CRU_CLKSEL_CON75_OFFSET (0x22CU) +#define CRU_CLKSEL_CON75_CLK_GPLL_DIV_400M_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON75_CLK_GPLL_DIV_400M_DIV_MASK (0x1FU << CRU_CLKSEL_CON75_CLK_GPLL_DIV_400M_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON75_CLK_GPLL_DIV_300M_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON75_CLK_GPLL_DIV_300M_DIV_MASK (0x1FU << CRU_CLKSEL_CON75_CLK_GPLL_DIV_300M_DIV_SHIFT) /* 0x00001F00 */ +/* CLKSEL_CON76 */ +#define CRU_CLKSEL_CON76_OFFSET (0x230U) +#define CRU_CLKSEL_CON76_CLK_GPLL_DIV_200M_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON76_CLK_GPLL_DIV_200M_DIV_MASK (0x1FU << CRU_CLKSEL_CON76_CLK_GPLL_DIV_200M_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON76_CLK_GPLL_DIV_150M_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON76_CLK_GPLL_DIV_150M_DIV_MASK (0x1FU << CRU_CLKSEL_CON76_CLK_GPLL_DIV_150M_DIV_SHIFT) /* 0x00001F00 */ +/* CLKSEL_CON77 */ +#define CRU_CLKSEL_CON77_OFFSET (0x234U) +#define CRU_CLKSEL_CON77_CLK_GPLL_DIV_100M_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON77_CLK_GPLL_DIV_100M_DIV_MASK (0x1FU << CRU_CLKSEL_CON77_CLK_GPLL_DIV_100M_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON77_CLK_GPLL_DIV_75M_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON77_CLK_GPLL_DIV_75M_DIV_MASK (0x1FU << CRU_CLKSEL_CON77_CLK_GPLL_DIV_75M_DIV_SHIFT) /* 0x00001F00 */ +/* CLKSEL_CON78 */ +#define CRU_CLKSEL_CON78_OFFSET (0x238U) +#define CRU_CLKSEL_CON78_CLK_GPLL_DIV_20M_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON78_CLK_GPLL_DIV_20M_DIV_MASK (0x3FU << CRU_CLKSEL_CON78_CLK_GPLL_DIV_20M_DIV_SHIFT) /* 0x0000003F */ +#define CRU_CLKSEL_CON78_CLK_CPLL_DIV_500M_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON78_CLK_CPLL_DIV_500M_DIV_MASK (0x1FU << CRU_CLKSEL_CON78_CLK_CPLL_DIV_500M_DIV_SHIFT) /* 0x00001F00 */ +/* CLKSEL_CON79 */ +#define CRU_CLKSEL_CON79_OFFSET (0x23CU) +#define CRU_CLKSEL_CON79_CLK_CPLL_DIV_333M_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON79_CLK_CPLL_DIV_333M_DIV_MASK (0x1FU << CRU_CLKSEL_CON79_CLK_CPLL_DIV_333M_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON79_CLK_CPLL_DIV_250M_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON79_CLK_CPLL_DIV_250M_DIV_MASK (0x1FU << CRU_CLKSEL_CON79_CLK_CPLL_DIV_250M_DIV_SHIFT) /* 0x00001F00 */ +/* CLKSEL_CON80 */ +#define CRU_CLKSEL_CON80_OFFSET (0x240U) +#define CRU_CLKSEL_CON80_CLK_CPLL_DIV_125M_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON80_CLK_CPLL_DIV_125M_DIV_MASK (0x1FU << CRU_CLKSEL_CON80_CLK_CPLL_DIV_125M_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON80_CLK_CPLL_DIV_62P5_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON80_CLK_CPLL_DIV_62P5_DIV_MASK (0x1FU << CRU_CLKSEL_CON80_CLK_CPLL_DIV_62P5_DIV_SHIFT) /* 0x00001F00 */ +/* CLKSEL_CON81 */ +#define CRU_CLKSEL_CON81_OFFSET (0x244U) +#define CRU_CLKSEL_CON81_CLK_CPLL_DIV_50M_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON81_CLK_CPLL_DIV_50M_DIV_MASK (0x1FU << CRU_CLKSEL_CON81_CLK_CPLL_DIV_50M_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON81_CLK_CPLL_DIV_25M_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON81_CLK_CPLL_DIV_25M_DIV_MASK (0x3FU << CRU_CLKSEL_CON81_CLK_CPLL_DIV_25M_DIV_SHIFT) /* 0x00003F00 */ +/* CLKSEL_CON82 */ +#define CRU_CLKSEL_CON82_OFFSET (0x248U) +#define CRU_CLKSEL_CON82_CLK_CPLL_DIV_100M_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON82_CLK_CPLL_DIV_100M_DIV_MASK (0x1FU << CRU_CLKSEL_CON82_CLK_CPLL_DIV_100M_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON82_CLK_OSC0_DIV_750K_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON82_CLK_OSC0_DIV_750K_DIV_MASK (0x3FU << CRU_CLKSEL_CON82_CLK_OSC0_DIV_750K_DIV_SHIFT) /* 0x00003F00 */ +/* CLKSEL_CON83 */ +#define CRU_CLKSEL_CON83_OFFSET (0x24CU) +#define CRU_CLKSEL_CON83_CLK_I2S3_2CH_RX_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON83_CLK_I2S3_2CH_RX_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON83_CLK_I2S3_2CH_RX_SRC_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON83_CLK_I2S3_2CH_RX_SRC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON83_CLK_I2S3_2CH_RX_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON83_CLK_I2S3_2CH_RX_SRC_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON83_MCLK_I2S3_2CH_RX_SEL_SHIFT (10U) +#define CRU_CLKSEL_CON83_MCLK_I2S3_2CH_RX_SEL_MASK (0x3U << CRU_CLKSEL_CON83_MCLK_I2S3_2CH_RX_SEL_SHIFT) /* 0x00000C00 */ +#define CRU_CLKSEL_CON83_I2S3_MCLKOUT_RX_SEL_SHIFT (15U) +#define CRU_CLKSEL_CON83_I2S3_MCLKOUT_RX_SEL_MASK (0x1U << CRU_CLKSEL_CON83_I2S3_MCLKOUT_RX_SEL_SHIFT) /* 0x00008000 */ +/* CLKSEL_CON84 */ +#define CRU_CLKSEL_CON84_OFFSET (0x250U) +#define CRU_CLKSEL_CON84_CLK_I2S3_2CH_RX_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON84_CLK_I2S3_2CH_RX_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON84_CLK_I2S3_2CH_RX_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* GATE_CON00 */ +#define CRU_GATE_CON00_OFFSET (0x300U) +#define CRU_GATE_CON00_CLK_CORE_EN_SHIFT (0U) +#define CRU_GATE_CON00_CLK_CORE_EN_MASK (0x1U << CRU_GATE_CON00_CLK_CORE_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON00_CLK_CORE0_EN_SHIFT (1U) +#define CRU_GATE_CON00_CLK_CORE0_EN_MASK (0x1U << CRU_GATE_CON00_CLK_CORE0_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON00_CLK_CORE1_EN_SHIFT (2U) +#define CRU_GATE_CON00_CLK_CORE1_EN_MASK (0x1U << CRU_GATE_CON00_CLK_CORE1_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON00_CLK_CORE2_EN_SHIFT (3U) +#define CRU_GATE_CON00_CLK_CORE2_EN_MASK (0x1U << CRU_GATE_CON00_CLK_CORE2_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON00_CLK_CORE3_EN_SHIFT (4U) +#define CRU_GATE_CON00_CLK_CORE3_EN_MASK (0x1U << CRU_GATE_CON00_CLK_CORE3_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON00_SCLK_CORE_SRC_EN_SHIFT (5U) +#define CRU_GATE_CON00_SCLK_CORE_SRC_EN_MASK (0x1U << CRU_GATE_CON00_SCLK_CORE_SRC_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON00_CLK_NPLL_CORE_EN_SHIFT (6U) +#define CRU_GATE_CON00_CLK_NPLL_CORE_EN_MASK (0x1U << CRU_GATE_CON00_CLK_NPLL_CORE_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON00_SCLK_CORE_EN_SHIFT (7U) +#define CRU_GATE_CON00_SCLK_CORE_EN_MASK (0x1U << CRU_GATE_CON00_SCLK_CORE_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON00_ATCLK_CORE_EN_SHIFT (8U) +#define CRU_GATE_CON00_ATCLK_CORE_EN_MASK (0x1U << CRU_GATE_CON00_ATCLK_CORE_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON00_GICCLK_CORE_EN_SHIFT (9U) +#define CRU_GATE_CON00_GICCLK_CORE_EN_MASK (0x1U << CRU_GATE_CON00_GICCLK_CORE_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON00_PCLK_CORE_PRE_EN_SHIFT (10U) +#define CRU_GATE_CON00_PCLK_CORE_PRE_EN_MASK (0x1U << CRU_GATE_CON00_PCLK_CORE_PRE_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON00_PERIPHCLK_CORE_PRE_EN_SHIFT (11U) +#define CRU_GATE_CON00_PERIPHCLK_CORE_PRE_EN_MASK (0x1U << CRU_GATE_CON00_PERIPHCLK_CORE_PRE_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON00_PCLK_CORE_EN_SHIFT (12U) +#define CRU_GATE_CON00_PCLK_CORE_EN_MASK (0x1U << CRU_GATE_CON00_PCLK_CORE_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON00_PERIPHCLK_CORE_EN_SHIFT (13U) +#define CRU_GATE_CON00_PERIPHCLK_CORE_EN_MASK (0x1U << CRU_GATE_CON00_PERIPHCLK_CORE_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON00_TSCLK_CORE_EN_SHIFT (14U) +#define CRU_GATE_CON00_TSCLK_CORE_EN_MASK (0x1U << CRU_GATE_CON00_TSCLK_CORE_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON00_CNTCLK_CORE_EN_SHIFT (15U) +#define CRU_GATE_CON00_CNTCLK_CORE_EN_MASK (0x1U << CRU_GATE_CON00_CNTCLK_CORE_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON01 */ +#define CRU_GATE_CON01_OFFSET (0x304U) +#define CRU_GATE_CON01_ACLK_CORE_EN_SHIFT (0U) +#define CRU_GATE_CON01_ACLK_CORE_EN_MASK (0x1U << CRU_GATE_CON01_ACLK_CORE_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON01_ACLK_CORE_NIU2DDR_EN_SHIFT (1U) +#define CRU_GATE_CON01_ACLK_CORE_NIU2DDR_EN_MASK (0x1U << CRU_GATE_CON01_ACLK_CORE_NIU2DDR_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON01_ACLK_CORE_NIU2BUS_EN_SHIFT (2U) +#define CRU_GATE_CON01_ACLK_CORE_NIU2BUS_EN_MASK (0x1U << CRU_GATE_CON01_ACLK_CORE_NIU2BUS_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON01_PCLK_DBG_NIU_EN_SHIFT (3U) +#define CRU_GATE_CON01_PCLK_DBG_NIU_EN_MASK (0x1U << CRU_GATE_CON01_PCLK_DBG_NIU_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON01_PCLK_DBG_EN_SHIFT (4U) +#define CRU_GATE_CON01_PCLK_DBG_EN_MASK (0x1U << CRU_GATE_CON01_PCLK_DBG_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON01_PCLK_DBG_DAPLITE_EN_SHIFT (5U) +#define CRU_GATE_CON01_PCLK_DBG_DAPLITE_EN_MASK (0x1U << CRU_GATE_CON01_PCLK_DBG_DAPLITE_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON01_ACLK_ADB400_CORE2GIC_EN_SHIFT (6U) +#define CRU_GATE_CON01_ACLK_ADB400_CORE2GIC_EN_MASK (0x1U << CRU_GATE_CON01_ACLK_ADB400_CORE2GIC_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON01_ACLK_ADB400_GIC2CORE_EN_SHIFT (7U) +#define CRU_GATE_CON01_ACLK_ADB400_GIC2CORE_EN_MASK (0x1U << CRU_GATE_CON01_ACLK_ADB400_GIC2CORE_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON01_PCLK_CORE_GRF_EN_SHIFT (8U) +#define CRU_GATE_CON01_PCLK_CORE_GRF_EN_MASK (0x1U << CRU_GATE_CON01_PCLK_CORE_GRF_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON01_PCLK_CORE_PVTM_EN_SHIFT (9U) +#define CRU_GATE_CON01_PCLK_CORE_PVTM_EN_MASK (0x1U << CRU_GATE_CON01_PCLK_CORE_PVTM_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON01_CLK_CORE_PVTM_EN_SHIFT (10U) +#define CRU_GATE_CON01_CLK_CORE_PVTM_EN_MASK (0x1U << CRU_GATE_CON01_CLK_CORE_PVTM_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON01_CLK_CORE_PVTM_CORE_EN_SHIFT (11U) +#define CRU_GATE_CON01_CLK_CORE_PVTM_CORE_EN_MASK (0x1U << CRU_GATE_CON01_CLK_CORE_PVTM_CORE_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON01_CLK_CORE_PVTPLL_EN_SHIFT (12U) +#define CRU_GATE_CON01_CLK_CORE_PVTPLL_EN_MASK (0x1U << CRU_GATE_CON01_CLK_CORE_PVTPLL_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON01_CLK_CORE_DIV2_EN_SHIFT (13U) +#define CRU_GATE_CON01_CLK_CORE_DIV2_EN_MASK (0x1U << CRU_GATE_CON01_CLK_CORE_DIV2_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON01_CLK_APLL_CORE_EN_SHIFT (14U) +#define CRU_GATE_CON01_CLK_APLL_CORE_EN_MASK (0x1U << CRU_GATE_CON01_CLK_APLL_CORE_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON01_CLK_JTAG_EN_SHIFT (15U) +#define CRU_GATE_CON01_CLK_JTAG_EN_MASK (0x1U << CRU_GATE_CON01_CLK_JTAG_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON02 */ +#define CRU_GATE_CON02_OFFSET (0x308U) +#define CRU_GATE_CON02_CLK_GPU_SRC_EN_SHIFT (0U) +#define CRU_GATE_CON02_CLK_GPU_SRC_EN_MASK (0x1U << CRU_GATE_CON02_CLK_GPU_SRC_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON02_PCLK_GPU_PRE_EN_SHIFT (2U) +#define CRU_GATE_CON02_PCLK_GPU_PRE_EN_MASK (0x1U << CRU_GATE_CON02_PCLK_GPU_PRE_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON02_ACLK_GPU_EN_SHIFT (3U) +#define CRU_GATE_CON02_ACLK_GPU_EN_MASK (0x1U << CRU_GATE_CON02_ACLK_GPU_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON02_ACLK_GPU_NIU_EN_SHIFT (4U) +#define CRU_GATE_CON02_ACLK_GPU_NIU_EN_MASK (0x1U << CRU_GATE_CON02_ACLK_GPU_NIU_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON02_PCLK_GPU_NIU_EN_SHIFT (5U) +#define CRU_GATE_CON02_PCLK_GPU_NIU_EN_MASK (0x1U << CRU_GATE_CON02_PCLK_GPU_NIU_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON02_PCLK_GPU_PVTM_EN_SHIFT (6U) +#define CRU_GATE_CON02_PCLK_GPU_PVTM_EN_MASK (0x1U << CRU_GATE_CON02_PCLK_GPU_PVTM_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON02_CLK_GPU_PVTM_EN_SHIFT (7U) +#define CRU_GATE_CON02_CLK_GPU_PVTM_EN_MASK (0x1U << CRU_GATE_CON02_CLK_GPU_PVTM_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON02_CLK_GPU_PVTM_CORE_EN_SHIFT (8U) +#define CRU_GATE_CON02_CLK_GPU_PVTM_CORE_EN_MASK (0x1U << CRU_GATE_CON02_CLK_GPU_PVTM_CORE_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON02_CLK_GPU_PVTPLL_EN_SHIFT (9U) +#define CRU_GATE_CON02_CLK_GPU_PVTPLL_EN_MASK (0x1U << CRU_GATE_CON02_CLK_GPU_PVTPLL_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON02_CLK_GPU_DIV2_EN_SHIFT (10U) +#define CRU_GATE_CON02_CLK_GPU_DIV2_EN_MASK (0x1U << CRU_GATE_CON02_CLK_GPU_DIV2_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON02_ACLK_GPU_PRE_EN_SHIFT (11U) +#define CRU_GATE_CON02_ACLK_GPU_PRE_EN_MASK (0x1U << CRU_GATE_CON02_ACLK_GPU_PRE_EN_SHIFT) /* 0x00000800 */ +/* GATE_CON03 */ +#define CRU_GATE_CON03_OFFSET (0x30CU) +#define CRU_GATE_CON03_CLK_NPU_SRC_EN_SHIFT (0U) +#define CRU_GATE_CON03_CLK_NPU_SRC_EN_MASK (0x1U << CRU_GATE_CON03_CLK_NPU_SRC_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON03_CLK_NPU_NP5_EN_SHIFT (1U) +#define CRU_GATE_CON03_CLK_NPU_NP5_EN_MASK (0x1U << CRU_GATE_CON03_CLK_NPU_NP5_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON03_HCLK_NPU_PRE_EN_SHIFT (2U) +#define CRU_GATE_CON03_HCLK_NPU_PRE_EN_MASK (0x1U << CRU_GATE_CON03_HCLK_NPU_PRE_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON03_PCLK_NPU_PRE_EN_SHIFT (3U) +#define CRU_GATE_CON03_PCLK_NPU_PRE_EN_MASK (0x1U << CRU_GATE_CON03_PCLK_NPU_PRE_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON03_ACLK_NPU_NIU_EN_SHIFT (4U) +#define CRU_GATE_CON03_ACLK_NPU_NIU_EN_MASK (0x1U << CRU_GATE_CON03_ACLK_NPU_NIU_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON03_HCLK_NPU_NIU_EN_SHIFT (5U) +#define CRU_GATE_CON03_HCLK_NPU_NIU_EN_MASK (0x1U << CRU_GATE_CON03_HCLK_NPU_NIU_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON03_PCLK_NPU_NIU_EN_SHIFT (6U) +#define CRU_GATE_CON03_PCLK_NPU_NIU_EN_MASK (0x1U << CRU_GATE_CON03_PCLK_NPU_NIU_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON03_ACLK_RKNN_EN_SHIFT (7U) +#define CRU_GATE_CON03_ACLK_RKNN_EN_MASK (0x1U << CRU_GATE_CON03_ACLK_RKNN_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON03_HCLK_RKNN_EN_SHIFT (8U) +#define CRU_GATE_CON03_HCLK_RKNN_EN_MASK (0x1U << CRU_GATE_CON03_HCLK_RKNN_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON03_PCLK_NPU_PVTM_EN_SHIFT (9U) +#define CRU_GATE_CON03_PCLK_NPU_PVTM_EN_MASK (0x1U << CRU_GATE_CON03_PCLK_NPU_PVTM_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON03_CLK_NPU_PVTM_EN_SHIFT (10U) +#define CRU_GATE_CON03_CLK_NPU_PVTM_EN_MASK (0x1U << CRU_GATE_CON03_CLK_NPU_PVTM_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON03_CLK_NPU_PVTM_CORE_EN_SHIFT (11U) +#define CRU_GATE_CON03_CLK_NPU_PVTM_CORE_EN_MASK (0x1U << CRU_GATE_CON03_CLK_NPU_PVTM_CORE_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON03_CLK_NPU_PVTPLL_EN_SHIFT (12U) +#define CRU_GATE_CON03_CLK_NPU_PVTPLL_EN_MASK (0x1U << CRU_GATE_CON03_CLK_NPU_PVTPLL_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON03_CLK_NPU_DIV2_EN_SHIFT (13U) +#define CRU_GATE_CON03_CLK_NPU_DIV2_EN_MASK (0x1U << CRU_GATE_CON03_CLK_NPU_DIV2_EN_SHIFT) /* 0x00002000 */ +/* GATE_CON04 */ +#define CRU_GATE_CON04_OFFSET (0x310U) +#define CRU_GATE_CON04_CLK_DDRPHY1X_EN_SHIFT (0U) +#define CRU_GATE_CON04_CLK_DDRPHY1X_EN_MASK (0x1U << CRU_GATE_CON04_CLK_DDRPHY1X_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON04_CLK_DPLL_DDR_EN_SHIFT (1U) +#define CRU_GATE_CON04_CLK_DPLL_DDR_EN_MASK (0x1U << CRU_GATE_CON04_CLK_DPLL_DDR_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON04_ACLK_MSCH_DIV2_EN_SHIFT (2U) +#define CRU_GATE_CON04_ACLK_MSCH_DIV2_EN_MASK (0x1U << CRU_GATE_CON04_ACLK_MSCH_DIV2_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON04_CLK_HWFFC_CTRL_EN_SHIFT (3U) +#define CRU_GATE_CON04_CLK_HWFFC_CTRL_EN_MASK (0x1U << CRU_GATE_CON04_CLK_HWFFC_CTRL_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON04_ACLK_DDRSCRAMBLE_EN_SHIFT (4U) +#define CRU_GATE_CON04_ACLK_DDRSCRAMBLE_EN_MASK (0x1U << CRU_GATE_CON04_ACLK_DDRSCRAMBLE_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON04_ACLK_MSCH_EN_SHIFT (5U) +#define CRU_GATE_CON04_ACLK_MSCH_EN_MASK (0x1U << CRU_GATE_CON04_ACLK_MSCH_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON04_CLK_DDR_ALWAYSON_EN_SHIFT (6U) +#define CRU_GATE_CON04_CLK_DDR_ALWAYSON_EN_MASK (0x1U << CRU_GATE_CON04_CLK_DDR_ALWAYSON_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON04_ACLK_DDRSPLIT_EN_SHIFT (8U) +#define CRU_GATE_CON04_ACLK_DDRSPLIT_EN_MASK (0x1U << CRU_GATE_CON04_ACLK_DDRSPLIT_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON04_CLK_DDRDFI_CTL_EN_SHIFT (9U) +#define CRU_GATE_CON04_CLK_DDRDFI_CTL_EN_MASK (0x1U << CRU_GATE_CON04_CLK_DDRDFI_CTL_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON04_ACLK_DMA2DDR_EN_SHIFT (11U) +#define CRU_GATE_CON04_ACLK_DMA2DDR_EN_MASK (0x1U << CRU_GATE_CON04_ACLK_DMA2DDR_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON04_CLK_DDRMON_EN_SHIFT (13U) +#define CRU_GATE_CON04_CLK_DDRMON_EN_MASK (0x1U << CRU_GATE_CON04_CLK_DDRMON_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON04_CLK24_DDRMON_EN_SHIFT (15U) +#define CRU_GATE_CON04_CLK24_DDRMON_EN_MASK (0x1U << CRU_GATE_CON04_CLK24_DDRMON_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON05 */ +#define CRU_GATE_CON05_OFFSET (0x314U) +#define CRU_GATE_CON05_ACLK_GIC_AUDIO_EN_SHIFT (0U) +#define CRU_GATE_CON05_ACLK_GIC_AUDIO_EN_MASK (0x1U << CRU_GATE_CON05_ACLK_GIC_AUDIO_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON05_HCLK_GIC_AUDIO_EN_SHIFT (1U) +#define CRU_GATE_CON05_HCLK_GIC_AUDIO_EN_MASK (0x1U << CRU_GATE_CON05_HCLK_GIC_AUDIO_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON05_ACLK_GIC_AUDIO_NIU_EN_SHIFT (2U) +#define CRU_GATE_CON05_ACLK_GIC_AUDIO_NIU_EN_MASK (0x1U << CRU_GATE_CON05_ACLK_GIC_AUDIO_NIU_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON05_HCLK_GIC_AUDIO_NIU_EN_SHIFT (3U) +#define CRU_GATE_CON05_HCLK_GIC_AUDIO_NIU_EN_MASK (0x1U << CRU_GATE_CON05_HCLK_GIC_AUDIO_NIU_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON05_ACLK_GIC600_EN_SHIFT (4U) +#define CRU_GATE_CON05_ACLK_GIC600_EN_MASK (0x1U << CRU_GATE_CON05_ACLK_GIC600_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON05_ACLK_GICADB_CORE2GIC_EN_SHIFT (5U) +#define CRU_GATE_CON05_ACLK_GICADB_CORE2GIC_EN_MASK (0x1U << CRU_GATE_CON05_ACLK_GICADB_CORE2GIC_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON05_ACLK_GICADB_GIC2CORE_EN_SHIFT (6U) +#define CRU_GATE_CON05_ACLK_GICADB_GIC2CORE_EN_MASK (0x1U << CRU_GATE_CON05_ACLK_GICADB_GIC2CORE_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON05_ACLK_SPINLOCK_EN_SHIFT (7U) +#define CRU_GATE_CON05_ACLK_SPINLOCK_EN_MASK (0x1U << CRU_GATE_CON05_ACLK_SPINLOCK_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON05_HCLK_SDMMC_BUFFER_EN_SHIFT (8U) +#define CRU_GATE_CON05_HCLK_SDMMC_BUFFER_EN_MASK (0x1U << CRU_GATE_CON05_HCLK_SDMMC_BUFFER_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON05_DCLK_SDMMC_BUFFER_EN_SHIFT (9U) +#define CRU_GATE_CON05_DCLK_SDMMC_BUFFER_EN_MASK (0x1U << CRU_GATE_CON05_DCLK_SDMMC_BUFFER_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON05_HCLK_I2S0_8CH_EN_SHIFT (10U) +#define CRU_GATE_CON05_HCLK_I2S0_8CH_EN_MASK (0x1U << CRU_GATE_CON05_HCLK_I2S0_8CH_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON05_HCLK_I2S1_8CH_EN_SHIFT (11U) +#define CRU_GATE_CON05_HCLK_I2S1_8CH_EN_MASK (0x1U << CRU_GATE_CON05_HCLK_I2S1_8CH_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON05_HCLK_I2S2_2CH_EN_SHIFT (12U) +#define CRU_GATE_CON05_HCLK_I2S2_2CH_EN_MASK (0x1U << CRU_GATE_CON05_HCLK_I2S2_2CH_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON05_HCLK_I2S3_2CH_EN_SHIFT (13U) +#define CRU_GATE_CON05_HCLK_I2S3_2CH_EN_MASK (0x1U << CRU_GATE_CON05_HCLK_I2S3_2CH_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON05_HCLK_PDM_EN_SHIFT (14U) +#define CRU_GATE_CON05_HCLK_PDM_EN_MASK (0x1U << CRU_GATE_CON05_HCLK_PDM_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON05_MCLK_PDM_EN_SHIFT (15U) +#define CRU_GATE_CON05_MCLK_PDM_EN_MASK (0x1U << CRU_GATE_CON05_MCLK_PDM_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON06 */ +#define CRU_GATE_CON06_OFFSET (0x318U) +#define CRU_GATE_CON06_CLK_I2S0_8CH_TX_SRC_EN_SHIFT (0U) +#define CRU_GATE_CON06_CLK_I2S0_8CH_TX_SRC_EN_MASK (0x1U << CRU_GATE_CON06_CLK_I2S0_8CH_TX_SRC_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON06_CLK_I2S0_8CH_TX_FRAC_EN_SHIFT (1U) +#define CRU_GATE_CON06_CLK_I2S0_8CH_TX_FRAC_EN_MASK (0x1U << CRU_GATE_CON06_CLK_I2S0_8CH_TX_FRAC_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON06_MCLK_I2S0_8CH_TX_EN_SHIFT (2U) +#define CRU_GATE_CON06_MCLK_I2S0_8CH_TX_EN_MASK (0x1U << CRU_GATE_CON06_MCLK_I2S0_8CH_TX_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON06_I2S0_MCLKOUT_TX_EN_SHIFT (3U) +#define CRU_GATE_CON06_I2S0_MCLKOUT_TX_EN_MASK (0x1U << CRU_GATE_CON06_I2S0_MCLKOUT_TX_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON06_CLK_I2S0_8CH_RX_SRC_EN_SHIFT (4U) +#define CRU_GATE_CON06_CLK_I2S0_8CH_RX_SRC_EN_MASK (0x1U << CRU_GATE_CON06_CLK_I2S0_8CH_RX_SRC_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON06_CLK_I2S0_8CH_RX_FRAC_EN_SHIFT (5U) +#define CRU_GATE_CON06_CLK_I2S0_8CH_RX_FRAC_EN_MASK (0x1U << CRU_GATE_CON06_CLK_I2S0_8CH_RX_FRAC_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON06_MCLK_I2S0_8CH_RX_EN_SHIFT (6U) +#define CRU_GATE_CON06_MCLK_I2S0_8CH_RX_EN_MASK (0x1U << CRU_GATE_CON06_MCLK_I2S0_8CH_RX_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON06_I2S0_MCLKOUT_RX_EN_SHIFT (7U) +#define CRU_GATE_CON06_I2S0_MCLKOUT_RX_EN_MASK (0x1U << CRU_GATE_CON06_I2S0_MCLKOUT_RX_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON06_CLK_I2S1_8CH_TX_SRC_EN_SHIFT (8U) +#define CRU_GATE_CON06_CLK_I2S1_8CH_TX_SRC_EN_MASK (0x1U << CRU_GATE_CON06_CLK_I2S1_8CH_TX_SRC_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON06_CLK_I2S1_8CH_TX_FRAC_EN_SHIFT (9U) +#define CRU_GATE_CON06_CLK_I2S1_8CH_TX_FRAC_EN_MASK (0x1U << CRU_GATE_CON06_CLK_I2S1_8CH_TX_FRAC_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON06_MCLK_I2S1_8CH_TX_EN_SHIFT (10U) +#define CRU_GATE_CON06_MCLK_I2S1_8CH_TX_EN_MASK (0x1U << CRU_GATE_CON06_MCLK_I2S1_8CH_TX_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON06_I2S1_MCLKOUT_TX_EN_SHIFT (11U) +#define CRU_GATE_CON06_I2S1_MCLKOUT_TX_EN_MASK (0x1U << CRU_GATE_CON06_I2S1_MCLKOUT_TX_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON06_CLK_I2S1_8CH_RX_SRC_EN_SHIFT (12U) +#define CRU_GATE_CON06_CLK_I2S1_8CH_RX_SRC_EN_MASK (0x1U << CRU_GATE_CON06_CLK_I2S1_8CH_RX_SRC_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON06_CLK_I2S1_8CH_RX_FRAC_EN_SHIFT (13U) +#define CRU_GATE_CON06_CLK_I2S1_8CH_RX_FRAC_EN_MASK (0x1U << CRU_GATE_CON06_CLK_I2S1_8CH_RX_FRAC_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON06_MCLK_I2S1_8CH_RX_EN_SHIFT (14U) +#define CRU_GATE_CON06_MCLK_I2S1_8CH_RX_EN_MASK (0x1U << CRU_GATE_CON06_MCLK_I2S1_8CH_RX_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON06_I2S1_MCLKOUT_RX_EN_SHIFT (15U) +#define CRU_GATE_CON06_I2S1_MCLKOUT_RX_EN_MASK (0x1U << CRU_GATE_CON06_I2S1_MCLKOUT_RX_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON07 */ +#define CRU_GATE_CON07_OFFSET (0x31CU) +#define CRU_GATE_CON07_CLK_I2S2_2CH_SRC_EN_SHIFT (0U) +#define CRU_GATE_CON07_CLK_I2S2_2CH_SRC_EN_MASK (0x1U << CRU_GATE_CON07_CLK_I2S2_2CH_SRC_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON07_CLK_I2S2_2CH_FRAC_EN_SHIFT (1U) +#define CRU_GATE_CON07_CLK_I2S2_2CH_FRAC_EN_MASK (0x1U << CRU_GATE_CON07_CLK_I2S2_2CH_FRAC_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON07_MCLK_I2S2_2CH_EN_SHIFT (2U) +#define CRU_GATE_CON07_MCLK_I2S2_2CH_EN_MASK (0x1U << CRU_GATE_CON07_MCLK_I2S2_2CH_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON07_I2S2_MCLKOUT_EN_SHIFT (3U) +#define CRU_GATE_CON07_I2S2_MCLKOUT_EN_MASK (0x1U << CRU_GATE_CON07_I2S2_MCLKOUT_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON07_CLK_I2S3_2CH_TX_SRC_EN_SHIFT (4U) +#define CRU_GATE_CON07_CLK_I2S3_2CH_TX_SRC_EN_MASK (0x1U << CRU_GATE_CON07_CLK_I2S3_2CH_TX_SRC_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON07_CLK_I2S3_2CH_TX_FRAC_EN_SHIFT (5U) +#define CRU_GATE_CON07_CLK_I2S3_2CH_TX_FRAC_EN_MASK (0x1U << CRU_GATE_CON07_CLK_I2S3_2CH_TX_FRAC_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON07_MCLK_I2S3_2CH_TX_EN_SHIFT (6U) +#define CRU_GATE_CON07_MCLK_I2S3_2CH_TX_EN_MASK (0x1U << CRU_GATE_CON07_MCLK_I2S3_2CH_TX_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON07_I2S3_MCLKOUT_TX_EN_SHIFT (7U) +#define CRU_GATE_CON07_I2S3_MCLKOUT_TX_EN_MASK (0x1U << CRU_GATE_CON07_I2S3_MCLKOUT_TX_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON07_CLK_I2S3_2CH_RX_SRC_EN_SHIFT (8U) +#define CRU_GATE_CON07_CLK_I2S3_2CH_RX_SRC_EN_MASK (0x1U << CRU_GATE_CON07_CLK_I2S3_2CH_RX_SRC_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON07_CLK_I2S3_2CH_RX_FRAC_EN_SHIFT (9U) +#define CRU_GATE_CON07_CLK_I2S3_2CH_RX_FRAC_EN_MASK (0x1U << CRU_GATE_CON07_CLK_I2S3_2CH_RX_FRAC_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON07_MCLK_I2S3_2CH_RX_EN_SHIFT (10U) +#define CRU_GATE_CON07_MCLK_I2S3_2CH_RX_EN_MASK (0x1U << CRU_GATE_CON07_MCLK_I2S3_2CH_RX_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON07_I2S3_MCLKOUT_RX_EN_SHIFT (11U) +#define CRU_GATE_CON07_I2S3_MCLKOUT_RX_EN_MASK (0x1U << CRU_GATE_CON07_I2S3_MCLKOUT_RX_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON07_HCLK_VAD_EN_SHIFT (12U) +#define CRU_GATE_CON07_HCLK_VAD_EN_MASK (0x1U << CRU_GATE_CON07_HCLK_VAD_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON07_HCLK_SPDIF_8CH_EN_SHIFT (13U) +#define CRU_GATE_CON07_HCLK_SPDIF_8CH_EN_MASK (0x1U << CRU_GATE_CON07_HCLK_SPDIF_8CH_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON07_MCLK_SPDIF_8CH_SRC_EN_SHIFT (14U) +#define CRU_GATE_CON07_MCLK_SPDIF_8CH_SRC_EN_MASK (0x1U << CRU_GATE_CON07_MCLK_SPDIF_8CH_SRC_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON07_MCLK_SPDIF_8CH_FRAC_EN_SHIFT (15U) +#define CRU_GATE_CON07_MCLK_SPDIF_8CH_FRAC_EN_MASK (0x1U << CRU_GATE_CON07_MCLK_SPDIF_8CH_FRAC_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON08 */ +#define CRU_GATE_CON08_OFFSET (0x320U) +#define CRU_GATE_CON08_HCLK_AUDPWM_EN_SHIFT (0U) +#define CRU_GATE_CON08_HCLK_AUDPWM_EN_MASK (0x1U << CRU_GATE_CON08_HCLK_AUDPWM_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON08_SCLK_AUDPWM_SRC_EN_SHIFT (1U) +#define CRU_GATE_CON08_SCLK_AUDPWM_SRC_EN_MASK (0x1U << CRU_GATE_CON08_SCLK_AUDPWM_SRC_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON08_SCLK_AUDPWM_FRAC_EN_SHIFT (2U) +#define CRU_GATE_CON08_SCLK_AUDPWM_FRAC_EN_MASK (0x1U << CRU_GATE_CON08_SCLK_AUDPWM_FRAC_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON08_HCLK_ACDCDIG_EN_SHIFT (3U) +#define CRU_GATE_CON08_HCLK_ACDCDIG_EN_MASK (0x1U << CRU_GATE_CON08_HCLK_ACDCDIG_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON08_CLK_ACDCDIG_I2C_EN_SHIFT (4U) +#define CRU_GATE_CON08_CLK_ACDCDIG_I2C_EN_MASK (0x1U << CRU_GATE_CON08_CLK_ACDCDIG_I2C_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON08_CLK_ACDCDIG_DAC_EN_SHIFT (5U) +#define CRU_GATE_CON08_CLK_ACDCDIG_DAC_EN_MASK (0x1U << CRU_GATE_CON08_CLK_ACDCDIG_DAC_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON08_CLK_ACDCDIG_ADC_EN_SHIFT (6U) +#define CRU_GATE_CON08_CLK_ACDCDIG_ADC_EN_MASK (0x1U << CRU_GATE_CON08_CLK_ACDCDIG_ADC_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON08_ACLK_SECURE_FLASH_EN_SHIFT (7U) +#define CRU_GATE_CON08_ACLK_SECURE_FLASH_EN_MASK (0x1U << CRU_GATE_CON08_ACLK_SECURE_FLASH_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON08_HCLK_SECURE_FLASH_EN_SHIFT (8U) +#define CRU_GATE_CON08_HCLK_SECURE_FLASH_EN_MASK (0x1U << CRU_GATE_CON08_HCLK_SECURE_FLASH_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON08_ACLK_SECURE_FLASH_NIU_EN_SHIFT (9U) +#define CRU_GATE_CON08_ACLK_SECURE_FLASH_NIU_EN_MASK (0x1U << CRU_GATE_CON08_ACLK_SECURE_FLASH_NIU_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON08_HCLK_SECURE_FLASH_NIU_EN_SHIFT (10U) +#define CRU_GATE_CON08_HCLK_SECURE_FLASH_NIU_EN_MASK (0x1U << CRU_GATE_CON08_HCLK_SECURE_FLASH_NIU_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON08_ACLK_CRYPTO_NS_EN_SHIFT (11U) +#define CRU_GATE_CON08_ACLK_CRYPTO_NS_EN_MASK (0x1U << CRU_GATE_CON08_ACLK_CRYPTO_NS_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON08_HCLK_CRYPTO_NS_EN_SHIFT (12U) +#define CRU_GATE_CON08_HCLK_CRYPTO_NS_EN_MASK (0x1U << CRU_GATE_CON08_HCLK_CRYPTO_NS_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON08_CLK_CRYPTO_NS_CORE_EN_SHIFT (13U) +#define CRU_GATE_CON08_CLK_CRYPTO_NS_CORE_EN_MASK (0x1U << CRU_GATE_CON08_CLK_CRYPTO_NS_CORE_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON08_CLK_CRYPTO_NS_PKA_EN_SHIFT (14U) +#define CRU_GATE_CON08_CLK_CRYPTO_NS_PKA_EN_MASK (0x1U << CRU_GATE_CON08_CLK_CRYPTO_NS_PKA_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON08_CLK_CRYPTO_NS_RNG_EN_SHIFT (15U) +#define CRU_GATE_CON08_CLK_CRYPTO_NS_RNG_EN_MASK (0x1U << CRU_GATE_CON08_CLK_CRYPTO_NS_RNG_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON09 */ +#define CRU_GATE_CON09_OFFSET (0x324U) +#define CRU_GATE_CON09_HCLK_NANDC_EN_SHIFT (0U) +#define CRU_GATE_CON09_HCLK_NANDC_EN_MASK (0x1U << CRU_GATE_CON09_HCLK_NANDC_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON09_NCLK_NANDC_EN_SHIFT (1U) +#define CRU_GATE_CON09_NCLK_NANDC_EN_MASK (0x1U << CRU_GATE_CON09_NCLK_NANDC_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON09_HCLK_SFC_EN_SHIFT (2U) +#define CRU_GATE_CON09_HCLK_SFC_EN_MASK (0x1U << CRU_GATE_CON09_HCLK_SFC_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON09_HCLK_SFC_XIP_EN_SHIFT (3U) +#define CRU_GATE_CON09_HCLK_SFC_XIP_EN_MASK (0x1U << CRU_GATE_CON09_HCLK_SFC_XIP_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON09_SCLK_SFC_EN_SHIFT (4U) +#define CRU_GATE_CON09_SCLK_SFC_EN_MASK (0x1U << CRU_GATE_CON09_SCLK_SFC_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON09_ACLK_EMMC_EN_SHIFT (5U) +#define CRU_GATE_CON09_ACLK_EMMC_EN_MASK (0x1U << CRU_GATE_CON09_ACLK_EMMC_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON09_HCLK_EMMC_EN_SHIFT (6U) +#define CRU_GATE_CON09_HCLK_EMMC_EN_MASK (0x1U << CRU_GATE_CON09_HCLK_EMMC_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON09_BCLK_EMMC_EN_SHIFT (7U) +#define CRU_GATE_CON09_BCLK_EMMC_EN_MASK (0x1U << CRU_GATE_CON09_BCLK_EMMC_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON09_CCLK_EMMC_EN_SHIFT (8U) +#define CRU_GATE_CON09_CCLK_EMMC_EN_MASK (0x1U << CRU_GATE_CON09_CCLK_EMMC_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON09_TCLK_EMMC_EN_SHIFT (9U) +#define CRU_GATE_CON09_TCLK_EMMC_EN_MASK (0x1U << CRU_GATE_CON09_TCLK_EMMC_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON09_HCLK_TRNG_NS_EN_SHIFT (10U) +#define CRU_GATE_CON09_HCLK_TRNG_NS_EN_MASK (0x1U << CRU_GATE_CON09_HCLK_TRNG_NS_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON09_CLK_TRNG_NS_EN_SHIFT (11U) +#define CRU_GATE_CON09_CLK_TRNG_NS_EN_MASK (0x1U << CRU_GATE_CON09_CLK_TRNG_NS_EN_SHIFT) /* 0x00000800 */ +/* GATE_CON10 */ +#define CRU_GATE_CON10_OFFSET (0x328U) +#define CRU_GATE_CON10_ACLK_PIPE_EN_SHIFT (0U) +#define CRU_GATE_CON10_ACLK_PIPE_EN_MASK (0x1U << CRU_GATE_CON10_ACLK_PIPE_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON10_PCLK_PIPE_EN_SHIFT (1U) +#define CRU_GATE_CON10_PCLK_PIPE_EN_MASK (0x1U << CRU_GATE_CON10_PCLK_PIPE_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON10_ACLK_PIPE_NIU_EN_SHIFT (2U) +#define CRU_GATE_CON10_ACLK_PIPE_NIU_EN_MASK (0x1U << CRU_GATE_CON10_ACLK_PIPE_NIU_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON10_PCLK_PIPE_NIU_EN_SHIFT (3U) +#define CRU_GATE_CON10_PCLK_PIPE_NIU_EN_MASK (0x1U << CRU_GATE_CON10_PCLK_PIPE_NIU_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON10_CLK_XPCS_EEE_EN_SHIFT (4U) +#define CRU_GATE_CON10_CLK_XPCS_EEE_EN_MASK (0x1U << CRU_GATE_CON10_CLK_XPCS_EEE_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON10_CLK_XPCS_RX_DIV10_EN_SHIFT (5U) +#define CRU_GATE_CON10_CLK_XPCS_RX_DIV10_EN_MASK (0x1U << CRU_GATE_CON10_CLK_XPCS_RX_DIV10_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON10_CLK_XPCS_TX_DIV10_EN_SHIFT (6U) +#define CRU_GATE_CON10_CLK_XPCS_TX_DIV10_EN_MASK (0x1U << CRU_GATE_CON10_CLK_XPCS_TX_DIV10_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON10_PCLK_PIPE_GRF_EN_SHIFT (7U) +#define CRU_GATE_CON10_PCLK_PIPE_GRF_EN_MASK (0x1U << CRU_GATE_CON10_PCLK_PIPE_GRF_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON10_ACLK_USB3OTG0_EN_SHIFT (8U) +#define CRU_GATE_CON10_ACLK_USB3OTG0_EN_MASK (0x1U << CRU_GATE_CON10_ACLK_USB3OTG0_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON10_CLK_USB3OTG0_REF_EN_SHIFT (9U) +#define CRU_GATE_CON10_CLK_USB3OTG0_REF_EN_MASK (0x1U << CRU_GATE_CON10_CLK_USB3OTG0_REF_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON10_CLK_USB3OTG0_SUSPEND_EN_SHIFT (10U) +#define CRU_GATE_CON10_CLK_USB3OTG0_SUSPEND_EN_MASK (0x1U << CRU_GATE_CON10_CLK_USB3OTG0_SUSPEND_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON10_CLK_USB3OTG0_PIPE_EN_SHIFT (11U) +#define CRU_GATE_CON10_CLK_USB3OTG0_PIPE_EN_MASK (0x1U << CRU_GATE_CON10_CLK_USB3OTG0_PIPE_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON10_ACLK_USB3OTG1_EN_SHIFT (12U) +#define CRU_GATE_CON10_ACLK_USB3OTG1_EN_MASK (0x1U << CRU_GATE_CON10_ACLK_USB3OTG1_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON10_CLK_USB3OTG1_REF_EN_SHIFT (13U) +#define CRU_GATE_CON10_CLK_USB3OTG1_REF_EN_MASK (0x1U << CRU_GATE_CON10_CLK_USB3OTG1_REF_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON10_CLK_USB3OTG1_SUSPEND_EN_SHIFT (14U) +#define CRU_GATE_CON10_CLK_USB3OTG1_SUSPEND_EN_MASK (0x1U << CRU_GATE_CON10_CLK_USB3OTG1_SUSPEND_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON10_CLK_USB3OTG1_PIPE_EN_SHIFT (15U) +#define CRU_GATE_CON10_CLK_USB3OTG1_PIPE_EN_MASK (0x1U << CRU_GATE_CON10_CLK_USB3OTG1_PIPE_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON11 */ +#define CRU_GATE_CON11_OFFSET (0x32CU) +#define CRU_GATE_CON11_ACLK_SATA0_EN_SHIFT (0U) +#define CRU_GATE_CON11_ACLK_SATA0_EN_MASK (0x1U << CRU_GATE_CON11_ACLK_SATA0_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON11_CLK_SATA0_PMALIVE_EN_SHIFT (1U) +#define CRU_GATE_CON11_CLK_SATA0_PMALIVE_EN_MASK (0x1U << CRU_GATE_CON11_CLK_SATA0_PMALIVE_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON11_CLK_SATA0_RXOOB_EN_SHIFT (2U) +#define CRU_GATE_CON11_CLK_SATA0_RXOOB_EN_MASK (0x1U << CRU_GATE_CON11_CLK_SATA0_RXOOB_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON11_CLK_SATA0_PIPE_EN_SHIFT (3U) +#define CRU_GATE_CON11_CLK_SATA0_PIPE_EN_MASK (0x1U << CRU_GATE_CON11_CLK_SATA0_PIPE_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON11_ACLK_SATA1_EN_SHIFT (4U) +#define CRU_GATE_CON11_ACLK_SATA1_EN_MASK (0x1U << CRU_GATE_CON11_ACLK_SATA1_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON11_CLK_SATA1_PMALIVE_EN_SHIFT (5U) +#define CRU_GATE_CON11_CLK_SATA1_PMALIVE_EN_MASK (0x1U << CRU_GATE_CON11_CLK_SATA1_PMALIVE_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON11_CLK_SATA1_RXOOB_EN_SHIFT (6U) +#define CRU_GATE_CON11_CLK_SATA1_RXOOB_EN_MASK (0x1U << CRU_GATE_CON11_CLK_SATA1_RXOOB_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON11_CLK_SATA1_PIPE_EN_SHIFT (7U) +#define CRU_GATE_CON11_CLK_SATA1_PIPE_EN_MASK (0x1U << CRU_GATE_CON11_CLK_SATA1_PIPE_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON11_ACLK_SATA2_EN_SHIFT (8U) +#define CRU_GATE_CON11_ACLK_SATA2_EN_MASK (0x1U << CRU_GATE_CON11_ACLK_SATA2_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON11_CLK_SATA2_PMALIVE_EN_SHIFT (9U) +#define CRU_GATE_CON11_CLK_SATA2_PMALIVE_EN_MASK (0x1U << CRU_GATE_CON11_CLK_SATA2_PMALIVE_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON11_CLK_SATA2_RXOOB_EN_SHIFT (10U) +#define CRU_GATE_CON11_CLK_SATA2_RXOOB_EN_MASK (0x1U << CRU_GATE_CON11_CLK_SATA2_RXOOB_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON11_CLK_SATA2_PIPE_EN_SHIFT (11U) +#define CRU_GATE_CON11_CLK_SATA2_PIPE_EN_MASK (0x1U << CRU_GATE_CON11_CLK_SATA2_PIPE_EN_SHIFT) /* 0x00000800 */ +/* GATE_CON12 */ +#define CRU_GATE_CON12_OFFSET (0x330U) +#define CRU_GATE_CON12_ACLK_PCIE20_MST_EN_SHIFT (0U) +#define CRU_GATE_CON12_ACLK_PCIE20_MST_EN_MASK (0x1U << CRU_GATE_CON12_ACLK_PCIE20_MST_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON12_ACLK_PCIE20_SLV_EN_SHIFT (1U) +#define CRU_GATE_CON12_ACLK_PCIE20_SLV_EN_MASK (0x1U << CRU_GATE_CON12_ACLK_PCIE20_SLV_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON12_ACLK_PCIE20_DBI_EN_SHIFT (2U) +#define CRU_GATE_CON12_ACLK_PCIE20_DBI_EN_MASK (0x1U << CRU_GATE_CON12_ACLK_PCIE20_DBI_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON12_PCLK_PCIE20_EN_SHIFT (3U) +#define CRU_GATE_CON12_PCLK_PCIE20_EN_MASK (0x1U << CRU_GATE_CON12_PCLK_PCIE20_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON12_CLK_PCIE20_AUX_EN_SHIFT (4U) +#define CRU_GATE_CON12_CLK_PCIE20_AUX_EN_MASK (0x1U << CRU_GATE_CON12_CLK_PCIE20_AUX_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON12_CLK_PCIE20_PIPE_EN_SHIFT (5U) +#define CRU_GATE_CON12_CLK_PCIE20_PIPE_EN_MASK (0x1U << CRU_GATE_CON12_CLK_PCIE20_PIPE_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON12_ACLK_PCIE30X1_MST_EN_SHIFT (8U) +#define CRU_GATE_CON12_ACLK_PCIE30X1_MST_EN_MASK (0x1U << CRU_GATE_CON12_ACLK_PCIE30X1_MST_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON12_ACLK_PCIE30X1_SLV_EN_SHIFT (9U) +#define CRU_GATE_CON12_ACLK_PCIE30X1_SLV_EN_MASK (0x1U << CRU_GATE_CON12_ACLK_PCIE30X1_SLV_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON12_ACLK_PCIE30X1_DBI_EN_SHIFT (10U) +#define CRU_GATE_CON12_ACLK_PCIE30X1_DBI_EN_MASK (0x1U << CRU_GATE_CON12_ACLK_PCIE30X1_DBI_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON12_PCLK_PCIE30X1_EN_SHIFT (11U) +#define CRU_GATE_CON12_PCLK_PCIE30X1_EN_MASK (0x1U << CRU_GATE_CON12_PCLK_PCIE30X1_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON12_CLK_PCIE30X1_AUX_EN_SHIFT (12U) +#define CRU_GATE_CON12_CLK_PCIE30X1_AUX_EN_MASK (0x1U << CRU_GATE_CON12_CLK_PCIE30X1_AUX_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON12_CLK_PCIE30X1_PIPE_EN_SHIFT (13U) +#define CRU_GATE_CON12_CLK_PCIE30X1_PIPE_EN_MASK (0x1U << CRU_GATE_CON12_CLK_PCIE30X1_PIPE_EN_SHIFT) /* 0x00002000 */ +/* GATE_CON13 */ +#define CRU_GATE_CON13_OFFSET (0x334U) +#define CRU_GATE_CON13_ACLK_PCIE30X2_MST_EN_SHIFT (0U) +#define CRU_GATE_CON13_ACLK_PCIE30X2_MST_EN_MASK (0x1U << CRU_GATE_CON13_ACLK_PCIE30X2_MST_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON13_ACLK_PCIE30X2_SLV_EN_SHIFT (1U) +#define CRU_GATE_CON13_ACLK_PCIE30X2_SLV_EN_MASK (0x1U << CRU_GATE_CON13_ACLK_PCIE30X2_SLV_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON13_ACLK_PCIE30X2_DBI_EN_SHIFT (2U) +#define CRU_GATE_CON13_ACLK_PCIE30X2_DBI_EN_MASK (0x1U << CRU_GATE_CON13_ACLK_PCIE30X2_DBI_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON13_PCLK_PCIE30X2_EN_SHIFT (3U) +#define CRU_GATE_CON13_PCLK_PCIE30X2_EN_MASK (0x1U << CRU_GATE_CON13_PCLK_PCIE30X2_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON13_CLK_PCIE30X2_AUX_EN_SHIFT (4U) +#define CRU_GATE_CON13_CLK_PCIE30X2_AUX_EN_MASK (0x1U << CRU_GATE_CON13_CLK_PCIE30X2_AUX_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON13_CLK_PCIE30X2_PIPE_EN_SHIFT (5U) +#define CRU_GATE_CON13_CLK_PCIE30X2_PIPE_EN_MASK (0x1U << CRU_GATE_CON13_CLK_PCIE30X2_PIPE_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON13_PCLK_XPCS_EN_SHIFT (6U) +#define CRU_GATE_CON13_PCLK_XPCS_EN_MASK (0x1U << CRU_GATE_CON13_PCLK_XPCS_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON13_CLK_XPCS_QSGMII_TX_EN_SHIFT (7U) +#define CRU_GATE_CON13_CLK_XPCS_QSGMII_TX_EN_MASK (0x1U << CRU_GATE_CON13_CLK_XPCS_QSGMII_TX_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON13_CLK_XPCS_QSGMII_RX_EN_SHIFT (8U) +#define CRU_GATE_CON13_CLK_XPCS_QSGMII_RX_EN_MASK (0x1U << CRU_GATE_CON13_CLK_XPCS_QSGMII_RX_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON13_CLK_XPCS_XGXS_TX_EN_SHIFT (9U) +#define CRU_GATE_CON13_CLK_XPCS_XGXS_TX_EN_MASK (0x1U << CRU_GATE_CON13_CLK_XPCS_XGXS_TX_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON13_CLK_XPCS_XGXS_RX_EN_SHIFT (11U) +#define CRU_GATE_CON13_CLK_XPCS_XGXS_RX_EN_MASK (0x1U << CRU_GATE_CON13_CLK_XPCS_XGXS_RX_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON13_CLK_XPCS_MII0_TX_EN_SHIFT (12U) +#define CRU_GATE_CON13_CLK_XPCS_MII0_TX_EN_MASK (0x1U << CRU_GATE_CON13_CLK_XPCS_MII0_TX_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON13_CLK_XPCS_MII0_RX_EN_SHIFT (13U) +#define CRU_GATE_CON13_CLK_XPCS_MII0_RX_EN_MASK (0x1U << CRU_GATE_CON13_CLK_XPCS_MII0_RX_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON13_CLK_XPCS_MII1_TX_EN_SHIFT (14U) +#define CRU_GATE_CON13_CLK_XPCS_MII1_TX_EN_MASK (0x1U << CRU_GATE_CON13_CLK_XPCS_MII1_TX_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON13_CLK_XPCS_MII1_RX_EN_SHIFT (15U) +#define CRU_GATE_CON13_CLK_XPCS_MII1_RX_EN_MASK (0x1U << CRU_GATE_CON13_CLK_XPCS_MII1_RX_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON14 */ +#define CRU_GATE_CON14_OFFSET (0x338U) +#define CRU_GATE_CON14_ACLK_PERIMID_EN_SHIFT (0U) +#define CRU_GATE_CON14_ACLK_PERIMID_EN_MASK (0x1U << CRU_GATE_CON14_ACLK_PERIMID_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON14_HCLK_PERIMID_EN_SHIFT (1U) +#define CRU_GATE_CON14_HCLK_PERIMID_EN_MASK (0x1U << CRU_GATE_CON14_HCLK_PERIMID_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON14_ACLK_PERIMID_NIU_EN_SHIFT (2U) +#define CRU_GATE_CON14_ACLK_PERIMID_NIU_EN_MASK (0x1U << CRU_GATE_CON14_ACLK_PERIMID_NIU_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON14_HCLK_PERIMID_NIU_EN_SHIFT (3U) +#define CRU_GATE_CON14_HCLK_PERIMID_NIU_EN_MASK (0x1U << CRU_GATE_CON14_HCLK_PERIMID_NIU_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON14_ACLK_PHP_EN_SHIFT (8U) +#define CRU_GATE_CON14_ACLK_PHP_EN_MASK (0x1U << CRU_GATE_CON14_ACLK_PHP_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON14_HCLK_PHP_EN_SHIFT (9U) +#define CRU_GATE_CON14_HCLK_PHP_EN_MASK (0x1U << CRU_GATE_CON14_HCLK_PHP_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON14_PCLK_PHP_EN_SHIFT (10U) +#define CRU_GATE_CON14_PCLK_PHP_EN_MASK (0x1U << CRU_GATE_CON14_PCLK_PHP_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON14_ACLK_PHP_NIU_EN_SHIFT (11U) +#define CRU_GATE_CON14_ACLK_PHP_NIU_EN_MASK (0x1U << CRU_GATE_CON14_ACLK_PHP_NIU_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON14_HCLK_PHP_NIU_EN_SHIFT (12U) +#define CRU_GATE_CON14_HCLK_PHP_NIU_EN_MASK (0x1U << CRU_GATE_CON14_HCLK_PHP_NIU_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON14_PCLK_PHP_NIU_EN_SHIFT (13U) +#define CRU_GATE_CON14_PCLK_PHP_NIU_EN_MASK (0x1U << CRU_GATE_CON14_PCLK_PHP_NIU_EN_SHIFT) /* 0x00002000 */ +/* GATE_CON15 */ +#define CRU_GATE_CON15_OFFSET (0x33CU) +#define CRU_GATE_CON15_HCLK_SDMMC0_EN_SHIFT (0U) +#define CRU_GATE_CON15_HCLK_SDMMC0_EN_MASK (0x1U << CRU_GATE_CON15_HCLK_SDMMC0_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON15_CLK_SDMMC0_EN_SHIFT (1U) +#define CRU_GATE_CON15_CLK_SDMMC0_EN_MASK (0x1U << CRU_GATE_CON15_CLK_SDMMC0_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON15_HCLK_SDMMC1_EN_SHIFT (2U) +#define CRU_GATE_CON15_HCLK_SDMMC1_EN_MASK (0x1U << CRU_GATE_CON15_HCLK_SDMMC1_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON15_CLK_SDMMC1_EN_SHIFT (3U) +#define CRU_GATE_CON15_CLK_SDMMC1_EN_MASK (0x1U << CRU_GATE_CON15_CLK_SDMMC1_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON15_CLK_GMAC0_PTP_REF_EN_SHIFT (4U) +#define CRU_GATE_CON15_CLK_GMAC0_PTP_REF_EN_MASK (0x1U << CRU_GATE_CON15_CLK_GMAC0_PTP_REF_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON15_ACLK_GMAC0_EN_SHIFT (5U) +#define CRU_GATE_CON15_ACLK_GMAC0_EN_MASK (0x1U << CRU_GATE_CON15_ACLK_GMAC0_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON15_PCLK_GMAC0_EN_SHIFT (6U) +#define CRU_GATE_CON15_PCLK_GMAC0_EN_MASK (0x1U << CRU_GATE_CON15_PCLK_GMAC0_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON15_CLK_MAC0_2TOP_EN_SHIFT (7U) +#define CRU_GATE_CON15_CLK_MAC0_2TOP_EN_MASK (0x1U << CRU_GATE_CON15_CLK_MAC0_2TOP_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON15_CLK_MAC0_OUT_EN_SHIFT (8U) +#define CRU_GATE_CON15_CLK_MAC0_OUT_EN_MASK (0x1U << CRU_GATE_CON15_CLK_MAC0_OUT_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON15_CLK_MAC0_REFOUT_EN_SHIFT (12U) +#define CRU_GATE_CON15_CLK_MAC0_REFOUT_EN_MASK (0x1U << CRU_GATE_CON15_CLK_MAC0_REFOUT_EN_SHIFT) /* 0x00001000 */ +/* GATE_CON16 */ +#define CRU_GATE_CON16_OFFSET (0x340U) +#define CRU_GATE_CON16_ACLK_USB_EN_SHIFT (0U) +#define CRU_GATE_CON16_ACLK_USB_EN_MASK (0x1U << CRU_GATE_CON16_ACLK_USB_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON16_HCLK_USB_EN_SHIFT (1U) +#define CRU_GATE_CON16_HCLK_USB_EN_MASK (0x1U << CRU_GATE_CON16_HCLK_USB_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON16_PCLK_USB_EN_SHIFT (2U) +#define CRU_GATE_CON16_PCLK_USB_EN_MASK (0x1U << CRU_GATE_CON16_PCLK_USB_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON16_ACLK_USB_NIU_EN_SHIFT (3U) +#define CRU_GATE_CON16_ACLK_USB_NIU_EN_MASK (0x1U << CRU_GATE_CON16_ACLK_USB_NIU_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON16_HCLK_USB_NIU_EN_SHIFT (4U) +#define CRU_GATE_CON16_HCLK_USB_NIU_EN_MASK (0x1U << CRU_GATE_CON16_HCLK_USB_NIU_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON16_PCLK_USB_NIU_EN_SHIFT (5U) +#define CRU_GATE_CON16_PCLK_USB_NIU_EN_MASK (0x1U << CRU_GATE_CON16_PCLK_USB_NIU_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON16_PCLK_USB_GRF_EN_SHIFT (6U) +#define CRU_GATE_CON16_PCLK_USB_GRF_EN_MASK (0x1U << CRU_GATE_CON16_PCLK_USB_GRF_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON16_HCLK_USB2HOST0_EN_SHIFT (12U) +#define CRU_GATE_CON16_HCLK_USB2HOST0_EN_MASK (0x1U << CRU_GATE_CON16_HCLK_USB2HOST0_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON16_HCLK_USB2HOST0_ARB_EN_SHIFT (13U) +#define CRU_GATE_CON16_HCLK_USB2HOST0_ARB_EN_MASK (0x1U << CRU_GATE_CON16_HCLK_USB2HOST0_ARB_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON16_HCLK_USB2HOST1_EN_SHIFT (14U) +#define CRU_GATE_CON16_HCLK_USB2HOST1_EN_MASK (0x1U << CRU_GATE_CON16_HCLK_USB2HOST1_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON16_HCLK_USB2HOST1_ARB_EN_SHIFT (15U) +#define CRU_GATE_CON16_HCLK_USB2HOST1_ARB_EN_MASK (0x1U << CRU_GATE_CON16_HCLK_USB2HOST1_ARB_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON17 */ +#define CRU_GATE_CON17_OFFSET (0x344U) +#define CRU_GATE_CON17_HCLK_SDMMC2_EN_SHIFT (0U) +#define CRU_GATE_CON17_HCLK_SDMMC2_EN_MASK (0x1U << CRU_GATE_CON17_HCLK_SDMMC2_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON17_CLK_SDMMC2_EN_SHIFT (1U) +#define CRU_GATE_CON17_CLK_SDMMC2_EN_MASK (0x1U << CRU_GATE_CON17_CLK_SDMMC2_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON17_CLK_GMAC1_PTP_REF_EN_SHIFT (2U) +#define CRU_GATE_CON17_CLK_GMAC1_PTP_REF_EN_MASK (0x1U << CRU_GATE_CON17_CLK_GMAC1_PTP_REF_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON17_ACLK_GMAC1_EN_SHIFT (3U) +#define CRU_GATE_CON17_ACLK_GMAC1_EN_MASK (0x1U << CRU_GATE_CON17_ACLK_GMAC1_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON17_PCLK_GMAC1_EN_SHIFT (4U) +#define CRU_GATE_CON17_PCLK_GMAC1_EN_MASK (0x1U << CRU_GATE_CON17_PCLK_GMAC1_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON17_CLK_MAC1_2TOP_EN_SHIFT (5U) +#define CRU_GATE_CON17_CLK_MAC1_2TOP_EN_MASK (0x1U << CRU_GATE_CON17_CLK_MAC1_2TOP_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON17_CLK_MAC1_OUT_EN_SHIFT (6U) +#define CRU_GATE_CON17_CLK_MAC1_OUT_EN_MASK (0x1U << CRU_GATE_CON17_CLK_MAC1_OUT_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON17_CLK_MAC1_REFOUT_EN_SHIFT (10U) +#define CRU_GATE_CON17_CLK_MAC1_REFOUT_EN_MASK (0x1U << CRU_GATE_CON17_CLK_MAC1_REFOUT_EN_SHIFT) /* 0x00000400 */ +/* GATE_CON18 */ +#define CRU_GATE_CON18_OFFSET (0x348U) +#define CRU_GATE_CON18_ACLK_VI_EN_SHIFT (0U) +#define CRU_GATE_CON18_ACLK_VI_EN_MASK (0x1U << CRU_GATE_CON18_ACLK_VI_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON18_HCLK_VI_EN_SHIFT (1U) +#define CRU_GATE_CON18_HCLK_VI_EN_MASK (0x1U << CRU_GATE_CON18_HCLK_VI_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON18_PCLK_VI_EN_SHIFT (2U) +#define CRU_GATE_CON18_PCLK_VI_EN_MASK (0x1U << CRU_GATE_CON18_PCLK_VI_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON18_ACLK_VI_NIU_EN_SHIFT (3U) +#define CRU_GATE_CON18_ACLK_VI_NIU_EN_MASK (0x1U << CRU_GATE_CON18_ACLK_VI_NIU_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON18_HCLK_VI_NIU_EN_SHIFT (4U) +#define CRU_GATE_CON18_HCLK_VI_NIU_EN_MASK (0x1U << CRU_GATE_CON18_HCLK_VI_NIU_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON18_PCLK_VI_NIU_EN_SHIFT (5U) +#define CRU_GATE_CON18_PCLK_VI_NIU_EN_MASK (0x1U << CRU_GATE_CON18_PCLK_VI_NIU_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON18_ACLK_VICAP1_EN_SHIFT (9U) +#define CRU_GATE_CON18_ACLK_VICAP1_EN_MASK (0x1U << CRU_GATE_CON18_ACLK_VICAP1_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON18_HCLK_VICAP1_EN_SHIFT (10U) +#define CRU_GATE_CON18_HCLK_VICAP1_EN_MASK (0x1U << CRU_GATE_CON18_HCLK_VICAP1_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON18_DCLK_VICAP1_EN_SHIFT (11U) +#define CRU_GATE_CON18_DCLK_VICAP1_EN_MASK (0x1U << CRU_GATE_CON18_DCLK_VICAP1_EN_SHIFT) /* 0x00000800 */ +/* GATE_CON19 */ +#define CRU_GATE_CON19_OFFSET (0x34CU) +#define CRU_GATE_CON19_ACLK_ISP_EN_SHIFT (0U) +#define CRU_GATE_CON19_ACLK_ISP_EN_MASK (0x1U << CRU_GATE_CON19_ACLK_ISP_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON19_HCLK_ISP_EN_SHIFT (1U) +#define CRU_GATE_CON19_HCLK_ISP_EN_MASK (0x1U << CRU_GATE_CON19_HCLK_ISP_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON19_CLK_ISP_EN_SHIFT (2U) +#define CRU_GATE_CON19_CLK_ISP_EN_MASK (0x1U << CRU_GATE_CON19_CLK_ISP_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON19_PCLK_CSI2HOST1_EN_SHIFT (4U) +#define CRU_GATE_CON19_PCLK_CSI2HOST1_EN_MASK (0x1U << CRU_GATE_CON19_PCLK_CSI2HOST1_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON19_CLK_CIF_OUT_EN_SHIFT (8U) +#define CRU_GATE_CON19_CLK_CIF_OUT_EN_MASK (0x1U << CRU_GATE_CON19_CLK_CIF_OUT_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON19_CLK_CAM0_OUT_EN_SHIFT (9U) +#define CRU_GATE_CON19_CLK_CAM0_OUT_EN_MASK (0x1U << CRU_GATE_CON19_CLK_CAM0_OUT_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON19_CLK_CAM1_OUT_EN_SHIFT (10U) +#define CRU_GATE_CON19_CLK_CAM1_OUT_EN_MASK (0x1U << CRU_GATE_CON19_CLK_CAM1_OUT_EN_SHIFT) /* 0x00000400 */ +/* GATE_CON20 */ +#define CRU_GATE_CON20_OFFSET (0x350U) +#define CRU_GATE_CON20_HCLK_VO_EN_SHIFT (1U) +#define CRU_GATE_CON20_HCLK_VO_EN_MASK (0x1U << CRU_GATE_CON20_HCLK_VO_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON20_PCLK_VO_EN_SHIFT (2U) +#define CRU_GATE_CON20_PCLK_VO_EN_MASK (0x1U << CRU_GATE_CON20_PCLK_VO_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON20_ACLK_VO_NIU_EN_SHIFT (3U) +#define CRU_GATE_CON20_ACLK_VO_NIU_EN_MASK (0x1U << CRU_GATE_CON20_ACLK_VO_NIU_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON20_HCLK_VO_NIU_EN_SHIFT (4U) +#define CRU_GATE_CON20_HCLK_VO_NIU_EN_MASK (0x1U << CRU_GATE_CON20_HCLK_VO_NIU_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON20_PCLK_VO_NIU_EN_SHIFT (5U) +#define CRU_GATE_CON20_PCLK_VO_NIU_EN_MASK (0x1U << CRU_GATE_CON20_PCLK_VO_NIU_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON20_ACLK_VOP_PRE_EN_SHIFT (6U) +#define CRU_GATE_CON20_ACLK_VOP_PRE_EN_MASK (0x1U << CRU_GATE_CON20_ACLK_VOP_PRE_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON20_ACLK_VOP_NIU_EN_SHIFT (7U) +#define CRU_GATE_CON20_ACLK_VOP_NIU_EN_MASK (0x1U << CRU_GATE_CON20_ACLK_VOP_NIU_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON20_ACLK_VOP_EN_SHIFT (8U) +#define CRU_GATE_CON20_ACLK_VOP_EN_MASK (0x1U << CRU_GATE_CON20_ACLK_VOP_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON20_HCLK_VOP_EN_SHIFT (9U) +#define CRU_GATE_CON20_HCLK_VOP_EN_MASK (0x1U << CRU_GATE_CON20_HCLK_VOP_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON20_DCLK0_VOP_EN_SHIFT (10U) +#define CRU_GATE_CON20_DCLK0_VOP_EN_MASK (0x1U << CRU_GATE_CON20_DCLK0_VOP_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON20_DCLK1_VOP_EN_SHIFT (11U) +#define CRU_GATE_CON20_DCLK1_VOP_EN_MASK (0x1U << CRU_GATE_CON20_DCLK1_VOP_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON20_DCLK2_VOP_EN_SHIFT (12U) +#define CRU_GATE_CON20_DCLK2_VOP_EN_MASK (0x1U << CRU_GATE_CON20_DCLK2_VOP_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON20_CLK_VOP_PWM_EN_SHIFT (13U) +#define CRU_GATE_CON20_CLK_VOP_PWM_EN_MASK (0x1U << CRU_GATE_CON20_CLK_VOP_PWM_EN_SHIFT) /* 0x00002000 */ +/* GATE_CON21 */ +#define CRU_GATE_CON21_OFFSET (0x354U) +#define CRU_GATE_CON21_ACLK_HDCP_EN_SHIFT (0U) +#define CRU_GATE_CON21_ACLK_HDCP_EN_MASK (0x1U << CRU_GATE_CON21_ACLK_HDCP_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON21_HCLK_HDCP_EN_SHIFT (1U) +#define CRU_GATE_CON21_HCLK_HDCP_EN_MASK (0x1U << CRU_GATE_CON21_HCLK_HDCP_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON21_PCLK_HDCP_EN_SHIFT (2U) +#define CRU_GATE_CON21_PCLK_HDCP_EN_MASK (0x1U << CRU_GATE_CON21_PCLK_HDCP_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON21_PCLK_HDMI_HOST_EN_SHIFT (3U) +#define CRU_GATE_CON21_PCLK_HDMI_HOST_EN_MASK (0x1U << CRU_GATE_CON21_PCLK_HDMI_HOST_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON21_CLK_HDMI_SFR_EN_SHIFT (4U) +#define CRU_GATE_CON21_CLK_HDMI_SFR_EN_MASK (0x1U << CRU_GATE_CON21_CLK_HDMI_SFR_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON21_CLK_HDMI_CEC_EN_SHIFT (5U) +#define CRU_GATE_CON21_CLK_HDMI_CEC_EN_MASK (0x1U << CRU_GATE_CON21_CLK_HDMI_CEC_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON21_PCLK_DSITX_0_EN_SHIFT (6U) +#define CRU_GATE_CON21_PCLK_DSITX_0_EN_MASK (0x1U << CRU_GATE_CON21_PCLK_DSITX_0_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON21_PCLK_DSITX_1_EN_SHIFT (7U) +#define CRU_GATE_CON21_PCLK_DSITX_1_EN_MASK (0x1U << CRU_GATE_CON21_PCLK_DSITX_1_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON21_PCLK_EDP_CTRL_EN_SHIFT (8U) +#define CRU_GATE_CON21_PCLK_EDP_CTRL_EN_MASK (0x1U << CRU_GATE_CON21_PCLK_EDP_CTRL_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON21_CLK_EDP_200M_EN_SHIFT (9U) +#define CRU_GATE_CON21_CLK_EDP_200M_EN_MASK (0x1U << CRU_GATE_CON21_CLK_EDP_200M_EN_SHIFT) /* 0x00000200 */ +/* GATE_CON22 */ +#define CRU_GATE_CON22_OFFSET (0x358U) +#define CRU_GATE_CON22_ACLK_VPU_PRE_EN_SHIFT (0U) +#define CRU_GATE_CON22_ACLK_VPU_PRE_EN_MASK (0x1U << CRU_GATE_CON22_ACLK_VPU_PRE_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON22_HCLK_VPU_PRE_EN_SHIFT (1U) +#define CRU_GATE_CON22_HCLK_VPU_PRE_EN_MASK (0x1U << CRU_GATE_CON22_HCLK_VPU_PRE_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON22_ACLK_VPU_NIU_EN_SHIFT (2U) +#define CRU_GATE_CON22_ACLK_VPU_NIU_EN_MASK (0x1U << CRU_GATE_CON22_ACLK_VPU_NIU_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON22_HCLK_VPU_NIU_EN_SHIFT (3U) +#define CRU_GATE_CON22_HCLK_VPU_NIU_EN_MASK (0x1U << CRU_GATE_CON22_HCLK_VPU_NIU_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON22_ACLK_VPU_EN_SHIFT (4U) +#define CRU_GATE_CON22_ACLK_VPU_EN_MASK (0x1U << CRU_GATE_CON22_ACLK_VPU_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON22_HCLK_VPU_EN_SHIFT (5U) +#define CRU_GATE_CON22_HCLK_VPU_EN_MASK (0x1U << CRU_GATE_CON22_HCLK_VPU_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON22_PCLK_RGA_PRE_EN_SHIFT (12U) +#define CRU_GATE_CON22_PCLK_RGA_PRE_EN_MASK (0x1U << CRU_GATE_CON22_PCLK_RGA_PRE_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON22_PCLK_RGA_NIU_EN_SHIFT (13U) +#define CRU_GATE_CON22_PCLK_RGA_NIU_EN_MASK (0x1U << CRU_GATE_CON22_PCLK_RGA_NIU_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON22_PCLK_EINK_EN_SHIFT (14U) +#define CRU_GATE_CON22_PCLK_EINK_EN_MASK (0x1U << CRU_GATE_CON22_PCLK_EINK_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON22_HCLK_EINK_EN_SHIFT (15U) +#define CRU_GATE_CON22_HCLK_EINK_EN_MASK (0x1U << CRU_GATE_CON22_HCLK_EINK_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON23 */ +#define CRU_GATE_CON23_OFFSET (0x35CU) +#define CRU_GATE_CON23_ACLK_RGA_PRE_EN_SHIFT (0U) +#define CRU_GATE_CON23_ACLK_RGA_PRE_EN_MASK (0x1U << CRU_GATE_CON23_ACLK_RGA_PRE_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON23_HCLK_RGA_PRE_EN_SHIFT (1U) +#define CRU_GATE_CON23_HCLK_RGA_PRE_EN_MASK (0x1U << CRU_GATE_CON23_HCLK_RGA_PRE_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON23_ACLK_RGA_NIU_EN_SHIFT (2U) +#define CRU_GATE_CON23_ACLK_RGA_NIU_EN_MASK (0x1U << CRU_GATE_CON23_ACLK_RGA_NIU_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON23_HCLK_RGA_NIU_EN_SHIFT (3U) +#define CRU_GATE_CON23_HCLK_RGA_NIU_EN_MASK (0x1U << CRU_GATE_CON23_HCLK_RGA_NIU_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON23_ACLK_RGA_EN_SHIFT (4U) +#define CRU_GATE_CON23_ACLK_RGA_EN_MASK (0x1U << CRU_GATE_CON23_ACLK_RGA_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON23_HCLK_RGA_EN_SHIFT (5U) +#define CRU_GATE_CON23_HCLK_RGA_EN_MASK (0x1U << CRU_GATE_CON23_HCLK_RGA_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON23_CLK_RGA_CORE_EN_SHIFT (6U) +#define CRU_GATE_CON23_CLK_RGA_CORE_EN_MASK (0x1U << CRU_GATE_CON23_CLK_RGA_CORE_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON23_ACLK_IEP_EN_SHIFT (7U) +#define CRU_GATE_CON23_ACLK_IEP_EN_MASK (0x1U << CRU_GATE_CON23_ACLK_IEP_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON23_HCLK_IEP_EN_SHIFT (8U) +#define CRU_GATE_CON23_HCLK_IEP_EN_MASK (0x1U << CRU_GATE_CON23_HCLK_IEP_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON23_CLK_IEP_CORE_EN_SHIFT (9U) +#define CRU_GATE_CON23_CLK_IEP_CORE_EN_MASK (0x1U << CRU_GATE_CON23_CLK_IEP_CORE_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON23_HCLK_EBC_EN_SHIFT (10U) +#define CRU_GATE_CON23_HCLK_EBC_EN_MASK (0x1U << CRU_GATE_CON23_HCLK_EBC_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON23_DCLK_EBC_EN_SHIFT (11U) +#define CRU_GATE_CON23_DCLK_EBC_EN_MASK (0x1U << CRU_GATE_CON23_DCLK_EBC_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON23_ACLK_JDEC_EN_SHIFT (12U) +#define CRU_GATE_CON23_ACLK_JDEC_EN_MASK (0x1U << CRU_GATE_CON23_ACLK_JDEC_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON23_HCLK_JDEC_EN_SHIFT (13U) +#define CRU_GATE_CON23_HCLK_JDEC_EN_MASK (0x1U << CRU_GATE_CON23_HCLK_JDEC_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON23_ACLK_JENC_EN_SHIFT (14U) +#define CRU_GATE_CON23_ACLK_JENC_EN_MASK (0x1U << CRU_GATE_CON23_ACLK_JENC_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON23_HCLK_JENC_EN_SHIFT (15U) +#define CRU_GATE_CON23_HCLK_JENC_EN_MASK (0x1U << CRU_GATE_CON23_HCLK_JENC_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON24 */ +#define CRU_GATE_CON24_OFFSET (0x360U) +#define CRU_GATE_CON24_ACLK_RKVENC_PRE_EN_SHIFT (0U) +#define CRU_GATE_CON24_ACLK_RKVENC_PRE_EN_MASK (0x1U << CRU_GATE_CON24_ACLK_RKVENC_PRE_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON24_HCLK_RKVENC_PRE_EN_SHIFT (1U) +#define CRU_GATE_CON24_HCLK_RKVENC_PRE_EN_MASK (0x1U << CRU_GATE_CON24_HCLK_RKVENC_PRE_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON24_ACLK_RKVENC_NIU_EN_SHIFT (3U) +#define CRU_GATE_CON24_ACLK_RKVENC_NIU_EN_MASK (0x1U << CRU_GATE_CON24_ACLK_RKVENC_NIU_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON24_HCLK_RKVENC_NIU_EN_SHIFT (4U) +#define CRU_GATE_CON24_HCLK_RKVENC_NIU_EN_MASK (0x1U << CRU_GATE_CON24_HCLK_RKVENC_NIU_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON24_ACLK_RKVENC_EN_SHIFT (6U) +#define CRU_GATE_CON24_ACLK_RKVENC_EN_MASK (0x1U << CRU_GATE_CON24_ACLK_RKVENC_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON24_HCLK_RKVENC_EN_SHIFT (7U) +#define CRU_GATE_CON24_HCLK_RKVENC_EN_MASK (0x1U << CRU_GATE_CON24_HCLK_RKVENC_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON24_CLK_RKVENC_CORE_EN_SHIFT (8U) +#define CRU_GATE_CON24_CLK_RKVENC_CORE_EN_MASK (0x1U << CRU_GATE_CON24_CLK_RKVENC_CORE_EN_SHIFT) /* 0x00000100 */ +/* GATE_CON25 */ +#define CRU_GATE_CON25_OFFSET (0x364U) +#define CRU_GATE_CON25_ACLK_RKVDEC_PRE_EN_SHIFT (0U) +#define CRU_GATE_CON25_ACLK_RKVDEC_PRE_EN_MASK (0x1U << CRU_GATE_CON25_ACLK_RKVDEC_PRE_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON25_HCLK_RKVDEC_PRE_EN_SHIFT (1U) +#define CRU_GATE_CON25_HCLK_RKVDEC_PRE_EN_MASK (0x1U << CRU_GATE_CON25_HCLK_RKVDEC_PRE_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON25_ACLK_RKVDEC_NIU_EN_SHIFT (2U) +#define CRU_GATE_CON25_ACLK_RKVDEC_NIU_EN_MASK (0x1U << CRU_GATE_CON25_ACLK_RKVDEC_NIU_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON25_HCLK_RKVDEC_NIU_EN_SHIFT (3U) +#define CRU_GATE_CON25_HCLK_RKVDEC_NIU_EN_MASK (0x1U << CRU_GATE_CON25_HCLK_RKVDEC_NIU_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON25_ACLK_RKVDEC_EN_SHIFT (4U) +#define CRU_GATE_CON25_ACLK_RKVDEC_EN_MASK (0x1U << CRU_GATE_CON25_ACLK_RKVDEC_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON25_HCLK_RKVDEC_EN_SHIFT (5U) +#define CRU_GATE_CON25_HCLK_RKVDEC_EN_MASK (0x1U << CRU_GATE_CON25_HCLK_RKVDEC_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON25_CLK_RKVDEC_CA_EN_SHIFT (6U) +#define CRU_GATE_CON25_CLK_RKVDEC_CA_EN_MASK (0x1U << CRU_GATE_CON25_CLK_RKVDEC_CA_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON25_CLK_RKVDEC_CORE_EN_SHIFT (7U) +#define CRU_GATE_CON25_CLK_RKVDEC_CORE_EN_MASK (0x1U << CRU_GATE_CON25_CLK_RKVDEC_CORE_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON25_CLK_RKVDEC_HEVC_CA_EN_SHIFT (8U) +#define CRU_GATE_CON25_CLK_RKVDEC_HEVC_CA_EN_MASK (0x1U << CRU_GATE_CON25_CLK_RKVDEC_HEVC_CA_EN_SHIFT) /* 0x00000100 */ +/* GATE_CON26 */ +#define CRU_GATE_CON26_OFFSET (0x368U) +#define CRU_GATE_CON26_ACLK_BUS_EN_SHIFT (0U) +#define CRU_GATE_CON26_ACLK_BUS_EN_MASK (0x1U << CRU_GATE_CON26_ACLK_BUS_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON26_PCLK_BUS_EN_SHIFT (1U) +#define CRU_GATE_CON26_PCLK_BUS_EN_MASK (0x1U << CRU_GATE_CON26_PCLK_BUS_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON26_ACLK_BUS_NIU_EN_SHIFT (2U) +#define CRU_GATE_CON26_ACLK_BUS_NIU_EN_MASK (0x1U << CRU_GATE_CON26_ACLK_BUS_NIU_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON26_PCLK_BUS_NIU_EN_SHIFT (3U) +#define CRU_GATE_CON26_PCLK_BUS_NIU_EN_MASK (0x1U << CRU_GATE_CON26_PCLK_BUS_NIU_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON26_PCLK_TSADC_EN_SHIFT (4U) +#define CRU_GATE_CON26_PCLK_TSADC_EN_MASK (0x1U << CRU_GATE_CON26_PCLK_TSADC_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON26_CLK_TSADC_TSEN_EN_SHIFT (5U) +#define CRU_GATE_CON26_CLK_TSADC_TSEN_EN_MASK (0x1U << CRU_GATE_CON26_CLK_TSADC_TSEN_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON26_CLK_TSADC_EN_SHIFT (6U) +#define CRU_GATE_CON26_CLK_TSADC_EN_MASK (0x1U << CRU_GATE_CON26_CLK_TSADC_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON26_PCLK_SARADC_EN_SHIFT (7U) +#define CRU_GATE_CON26_PCLK_SARADC_EN_MASK (0x1U << CRU_GATE_CON26_PCLK_SARADC_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON26_CLK_SARADC_EN_SHIFT (8U) +#define CRU_GATE_CON26_CLK_SARADC_EN_MASK (0x1U << CRU_GATE_CON26_CLK_SARADC_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON26_PCLK_OTPC_NS_EN_SHIFT (9U) +#define CRU_GATE_CON26_PCLK_OTPC_NS_EN_MASK (0x1U << CRU_GATE_CON26_PCLK_OTPC_NS_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON26_CLK_OTPC_NS_SBPI_EN_SHIFT (10U) +#define CRU_GATE_CON26_CLK_OTPC_NS_SBPI_EN_MASK (0x1U << CRU_GATE_CON26_CLK_OTPC_NS_SBPI_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON26_CLK_OTPC_NS_USR_EN_SHIFT (11U) +#define CRU_GATE_CON26_CLK_OTPC_NS_USR_EN_MASK (0x1U << CRU_GATE_CON26_CLK_OTPC_NS_USR_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON26_PCLK_SCR_EN_SHIFT (12U) +#define CRU_GATE_CON26_PCLK_SCR_EN_MASK (0x1U << CRU_GATE_CON26_PCLK_SCR_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON26_PCLK_WDT_NS_EN_SHIFT (13U) +#define CRU_GATE_CON26_PCLK_WDT_NS_EN_MASK (0x1U << CRU_GATE_CON26_PCLK_WDT_NS_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON26_TCLK_WDT_NS_EN_SHIFT (14U) +#define CRU_GATE_CON26_TCLK_WDT_NS_EN_MASK (0x1U << CRU_GATE_CON26_TCLK_WDT_NS_EN_SHIFT) /* 0x00004000 */ +/* GATE_CON27 */ +#define CRU_GATE_CON27_OFFSET (0x36CU) +#define CRU_GATE_CON27_PCLK_GRF_EN_SHIFT (0U) +#define CRU_GATE_CON27_PCLK_GRF_EN_MASK (0x1U << CRU_GATE_CON27_PCLK_GRF_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON27_PCLK_GRF_VCCIO12_EN_SHIFT (1U) +#define CRU_GATE_CON27_PCLK_GRF_VCCIO12_EN_MASK (0x1U << CRU_GATE_CON27_PCLK_GRF_VCCIO12_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON27_PCLK_GRF_VCCIO34_EN_SHIFT (2U) +#define CRU_GATE_CON27_PCLK_GRF_VCCIO34_EN_MASK (0x1U << CRU_GATE_CON27_PCLK_GRF_VCCIO34_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON27_PCLK_GRF_VCCIO567_EN_SHIFT (3U) +#define CRU_GATE_CON27_PCLK_GRF_VCCIO567_EN_MASK (0x1U << CRU_GATE_CON27_PCLK_GRF_VCCIO567_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON27_PCLK_DFT2APB_EN_SHIFT (4U) +#define CRU_GATE_CON27_PCLK_DFT2APB_EN_MASK (0x1U << CRU_GATE_CON27_PCLK_DFT2APB_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON27_PCLK_CAN0_EN_SHIFT (5U) +#define CRU_GATE_CON27_PCLK_CAN0_EN_MASK (0x1U << CRU_GATE_CON27_PCLK_CAN0_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON27_CLK_CAN0_EN_SHIFT (6U) +#define CRU_GATE_CON27_CLK_CAN0_EN_MASK (0x1U << CRU_GATE_CON27_CLK_CAN0_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON27_PCLK_CAN1_EN_SHIFT (7U) +#define CRU_GATE_CON27_PCLK_CAN1_EN_MASK (0x1U << CRU_GATE_CON27_PCLK_CAN1_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON27_CLK_CAN1_EN_SHIFT (8U) +#define CRU_GATE_CON27_CLK_CAN1_EN_MASK (0x1U << CRU_GATE_CON27_CLK_CAN1_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON27_PCLK_CAN2_EN_SHIFT (9U) +#define CRU_GATE_CON27_PCLK_CAN2_EN_MASK (0x1U << CRU_GATE_CON27_PCLK_CAN2_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON27_CLK_CAN2_EN_SHIFT (10U) +#define CRU_GATE_CON27_CLK_CAN2_EN_MASK (0x1U << CRU_GATE_CON27_CLK_CAN2_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON27_PCLK_UART1_EN_SHIFT (12U) +#define CRU_GATE_CON27_PCLK_UART1_EN_MASK (0x1U << CRU_GATE_CON27_PCLK_UART1_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON27_CLK_UART1_EN_SHIFT (13U) +#define CRU_GATE_CON27_CLK_UART1_EN_MASK (0x1U << CRU_GATE_CON27_CLK_UART1_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON27_CLK_UART1_FRAC_EN_SHIFT (14U) +#define CRU_GATE_CON27_CLK_UART1_FRAC_EN_MASK (0x1U << CRU_GATE_CON27_CLK_UART1_FRAC_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON27_SCLK_UART1_EN_SHIFT (15U) +#define CRU_GATE_CON27_SCLK_UART1_EN_MASK (0x1U << CRU_GATE_CON27_SCLK_UART1_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON28 */ +#define CRU_GATE_CON28_OFFSET (0x370U) +#define CRU_GATE_CON28_PCLK_UART2_EN_SHIFT (0U) +#define CRU_GATE_CON28_PCLK_UART2_EN_MASK (0x1U << CRU_GATE_CON28_PCLK_UART2_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON28_CLK_UART2_EN_SHIFT (1U) +#define CRU_GATE_CON28_CLK_UART2_EN_MASK (0x1U << CRU_GATE_CON28_CLK_UART2_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON28_CLK_UART2_FRAC_EN_SHIFT (2U) +#define CRU_GATE_CON28_CLK_UART2_FRAC_EN_MASK (0x1U << CRU_GATE_CON28_CLK_UART2_FRAC_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON28_SCLK_UART2_EN_SHIFT (3U) +#define CRU_GATE_CON28_SCLK_UART2_EN_MASK (0x1U << CRU_GATE_CON28_SCLK_UART2_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON28_PCLK_UART3_EN_SHIFT (4U) +#define CRU_GATE_CON28_PCLK_UART3_EN_MASK (0x1U << CRU_GATE_CON28_PCLK_UART3_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON28_CLK_UART3_EN_SHIFT (5U) +#define CRU_GATE_CON28_CLK_UART3_EN_MASK (0x1U << CRU_GATE_CON28_CLK_UART3_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON28_CLK_UART3_FRAC_EN_SHIFT (6U) +#define CRU_GATE_CON28_CLK_UART3_FRAC_EN_MASK (0x1U << CRU_GATE_CON28_CLK_UART3_FRAC_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON28_SCLK_UART3_EN_SHIFT (7U) +#define CRU_GATE_CON28_SCLK_UART3_EN_MASK (0x1U << CRU_GATE_CON28_SCLK_UART3_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON28_PCLK_UART4_EN_SHIFT (8U) +#define CRU_GATE_CON28_PCLK_UART4_EN_MASK (0x1U << CRU_GATE_CON28_PCLK_UART4_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON28_CLK_UART4_EN_SHIFT (9U) +#define CRU_GATE_CON28_CLK_UART4_EN_MASK (0x1U << CRU_GATE_CON28_CLK_UART4_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON28_CLK_UART4_FRAC_EN_SHIFT (10U) +#define CRU_GATE_CON28_CLK_UART4_FRAC_EN_MASK (0x1U << CRU_GATE_CON28_CLK_UART4_FRAC_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON28_SCLK_UART4_EN_SHIFT (11U) +#define CRU_GATE_CON28_SCLK_UART4_EN_MASK (0x1U << CRU_GATE_CON28_SCLK_UART4_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON28_PCLK_UART5_EN_SHIFT (12U) +#define CRU_GATE_CON28_PCLK_UART5_EN_MASK (0x1U << CRU_GATE_CON28_PCLK_UART5_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON28_CLK_UART5_EN_SHIFT (13U) +#define CRU_GATE_CON28_CLK_UART5_EN_MASK (0x1U << CRU_GATE_CON28_CLK_UART5_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON28_CLK_UART5_FRAC_EN_SHIFT (14U) +#define CRU_GATE_CON28_CLK_UART5_FRAC_EN_MASK (0x1U << CRU_GATE_CON28_CLK_UART5_FRAC_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON28_SCLK_UART5_EN_SHIFT (15U) +#define CRU_GATE_CON28_SCLK_UART5_EN_MASK (0x1U << CRU_GATE_CON28_SCLK_UART5_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON29 */ +#define CRU_GATE_CON29_OFFSET (0x374U) +#define CRU_GATE_CON29_PCLK_UART6_EN_SHIFT (0U) +#define CRU_GATE_CON29_PCLK_UART6_EN_MASK (0x1U << CRU_GATE_CON29_PCLK_UART6_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON29_CLK_UART6_EN_SHIFT (1U) +#define CRU_GATE_CON29_CLK_UART6_EN_MASK (0x1U << CRU_GATE_CON29_CLK_UART6_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON29_CLK_UART6_FRAC_EN_SHIFT (2U) +#define CRU_GATE_CON29_CLK_UART6_FRAC_EN_MASK (0x1U << CRU_GATE_CON29_CLK_UART6_FRAC_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON29_SCLK_UART6_EN_SHIFT (3U) +#define CRU_GATE_CON29_SCLK_UART6_EN_MASK (0x1U << CRU_GATE_CON29_SCLK_UART6_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON29_PCLK_UART7_EN_SHIFT (4U) +#define CRU_GATE_CON29_PCLK_UART7_EN_MASK (0x1U << CRU_GATE_CON29_PCLK_UART7_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON29_CLK_UART7_EN_SHIFT (5U) +#define CRU_GATE_CON29_CLK_UART7_EN_MASK (0x1U << CRU_GATE_CON29_CLK_UART7_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON29_CLK_UART7_FRAC_EN_SHIFT (6U) +#define CRU_GATE_CON29_CLK_UART7_FRAC_EN_MASK (0x1U << CRU_GATE_CON29_CLK_UART7_FRAC_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON29_SCLK_UART7_EN_SHIFT (7U) +#define CRU_GATE_CON29_SCLK_UART7_EN_MASK (0x1U << CRU_GATE_CON29_SCLK_UART7_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON29_PCLK_UART8_EN_SHIFT (8U) +#define CRU_GATE_CON29_PCLK_UART8_EN_MASK (0x1U << CRU_GATE_CON29_PCLK_UART8_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON29_CLK_UART8_EN_SHIFT (9U) +#define CRU_GATE_CON29_CLK_UART8_EN_MASK (0x1U << CRU_GATE_CON29_CLK_UART8_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON29_CLK_UART8_FRAC_EN_SHIFT (10U) +#define CRU_GATE_CON29_CLK_UART8_FRAC_EN_MASK (0x1U << CRU_GATE_CON29_CLK_UART8_FRAC_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON29_SCLK_UART8_EN_SHIFT (11U) +#define CRU_GATE_CON29_SCLK_UART8_EN_MASK (0x1U << CRU_GATE_CON29_SCLK_UART8_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON29_PCLK_UART9_EN_SHIFT (12U) +#define CRU_GATE_CON29_PCLK_UART9_EN_MASK (0x1U << CRU_GATE_CON29_PCLK_UART9_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON29_CLK_UART9_EN_SHIFT (13U) +#define CRU_GATE_CON29_CLK_UART9_EN_MASK (0x1U << CRU_GATE_CON29_CLK_UART9_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON29_CLK_UART9_FRAC_EN_SHIFT (14U) +#define CRU_GATE_CON29_CLK_UART9_FRAC_EN_MASK (0x1U << CRU_GATE_CON29_CLK_UART9_FRAC_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON29_SCLK_UART9_EN_SHIFT (15U) +#define CRU_GATE_CON29_SCLK_UART9_EN_MASK (0x1U << CRU_GATE_CON29_SCLK_UART9_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON30 */ +#define CRU_GATE_CON30_OFFSET (0x378U) +#define CRU_GATE_CON30_PCLK_I2C1_EN_SHIFT (0U) +#define CRU_GATE_CON30_PCLK_I2C1_EN_MASK (0x1U << CRU_GATE_CON30_PCLK_I2C1_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON30_CLK_I2C1_EN_SHIFT (1U) +#define CRU_GATE_CON30_CLK_I2C1_EN_MASK (0x1U << CRU_GATE_CON30_CLK_I2C1_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON30_PCLK_I2C2_EN_SHIFT (2U) +#define CRU_GATE_CON30_PCLK_I2C2_EN_MASK (0x1U << CRU_GATE_CON30_PCLK_I2C2_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON30_CLK_I2C2_EN_SHIFT (3U) +#define CRU_GATE_CON30_CLK_I2C2_EN_MASK (0x1U << CRU_GATE_CON30_CLK_I2C2_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON30_PCLK_I2C3_EN_SHIFT (4U) +#define CRU_GATE_CON30_PCLK_I2C3_EN_MASK (0x1U << CRU_GATE_CON30_PCLK_I2C3_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON30_CLK_I2C3_EN_SHIFT (5U) +#define CRU_GATE_CON30_CLK_I2C3_EN_MASK (0x1U << CRU_GATE_CON30_CLK_I2C3_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON30_PCLK_I2C4_EN_SHIFT (6U) +#define CRU_GATE_CON30_PCLK_I2C4_EN_MASK (0x1U << CRU_GATE_CON30_PCLK_I2C4_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON30_CLK_I2C4_EN_SHIFT (7U) +#define CRU_GATE_CON30_CLK_I2C4_EN_MASK (0x1U << CRU_GATE_CON30_CLK_I2C4_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON30_PCLK_I2C5_EN_SHIFT (8U) +#define CRU_GATE_CON30_PCLK_I2C5_EN_MASK (0x1U << CRU_GATE_CON30_PCLK_I2C5_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON30_CLK_I2C5_EN_SHIFT (9U) +#define CRU_GATE_CON30_CLK_I2C5_EN_MASK (0x1U << CRU_GATE_CON30_CLK_I2C5_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON30_PCLK_SPI0_EN_SHIFT (10U) +#define CRU_GATE_CON30_PCLK_SPI0_EN_MASK (0x1U << CRU_GATE_CON30_PCLK_SPI0_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON30_CLK_SPI0_EN_SHIFT (11U) +#define CRU_GATE_CON30_CLK_SPI0_EN_MASK (0x1U << CRU_GATE_CON30_CLK_SPI0_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON30_PCLK_SPI1_EN_SHIFT (12U) +#define CRU_GATE_CON30_PCLK_SPI1_EN_MASK (0x1U << CRU_GATE_CON30_PCLK_SPI1_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON30_CLK_SPI1_EN_SHIFT (13U) +#define CRU_GATE_CON30_CLK_SPI1_EN_MASK (0x1U << CRU_GATE_CON30_CLK_SPI1_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON30_PCLK_SPI2_EN_SHIFT (14U) +#define CRU_GATE_CON30_PCLK_SPI2_EN_MASK (0x1U << CRU_GATE_CON30_PCLK_SPI2_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON30_CLK_SPI2_EN_SHIFT (15U) +#define CRU_GATE_CON30_CLK_SPI2_EN_MASK (0x1U << CRU_GATE_CON30_CLK_SPI2_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON31 */ +#define CRU_GATE_CON31_OFFSET (0x37CU) +#define CRU_GATE_CON31_PCLK_SPI3_EN_SHIFT (0U) +#define CRU_GATE_CON31_PCLK_SPI3_EN_MASK (0x1U << CRU_GATE_CON31_PCLK_SPI3_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON31_CLK_SPI3_EN_SHIFT (1U) +#define CRU_GATE_CON31_CLK_SPI3_EN_MASK (0x1U << CRU_GATE_CON31_CLK_SPI3_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON31_PCLK_GPIO1_EN_SHIFT (2U) +#define CRU_GATE_CON31_PCLK_GPIO1_EN_MASK (0x1U << CRU_GATE_CON31_PCLK_GPIO1_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON31_DBCLK_GPIO1_EN_SHIFT (3U) +#define CRU_GATE_CON31_DBCLK_GPIO1_EN_MASK (0x1U << CRU_GATE_CON31_DBCLK_GPIO1_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON31_PCLK_GPIO2_EN_SHIFT (4U) +#define CRU_GATE_CON31_PCLK_GPIO2_EN_MASK (0x1U << CRU_GATE_CON31_PCLK_GPIO2_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON31_DBCLK_GPIO2_EN_SHIFT (5U) +#define CRU_GATE_CON31_DBCLK_GPIO2_EN_MASK (0x1U << CRU_GATE_CON31_DBCLK_GPIO2_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON31_PCLK_GPIO3_EN_SHIFT (6U) +#define CRU_GATE_CON31_PCLK_GPIO3_EN_MASK (0x1U << CRU_GATE_CON31_PCLK_GPIO3_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON31_DBCLK_GPIO3_EN_SHIFT (7U) +#define CRU_GATE_CON31_DBCLK_GPIO3_EN_MASK (0x1U << CRU_GATE_CON31_DBCLK_GPIO3_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON31_PCLK_GPIO4_EN_SHIFT (8U) +#define CRU_GATE_CON31_PCLK_GPIO4_EN_MASK (0x1U << CRU_GATE_CON31_PCLK_GPIO4_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON31_DBCLK_GPIO4_EN_SHIFT (9U) +#define CRU_GATE_CON31_DBCLK_GPIO4_EN_MASK (0x1U << CRU_GATE_CON31_DBCLK_GPIO4_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON31_PCLK_PWM1_EN_SHIFT (10U) +#define CRU_GATE_CON31_PCLK_PWM1_EN_MASK (0x1U << CRU_GATE_CON31_PCLK_PWM1_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON31_CLK_PWM1_EN_SHIFT (11U) +#define CRU_GATE_CON31_CLK_PWM1_EN_MASK (0x1U << CRU_GATE_CON31_CLK_PWM1_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON31_CLK_PWM1_CAPTURE_EN_SHIFT (12U) +#define CRU_GATE_CON31_CLK_PWM1_CAPTURE_EN_MASK (0x1U << CRU_GATE_CON31_CLK_PWM1_CAPTURE_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON31_PCLK_PWM2_EN_SHIFT (13U) +#define CRU_GATE_CON31_PCLK_PWM2_EN_MASK (0x1U << CRU_GATE_CON31_PCLK_PWM2_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON31_CLK_PWM2_EN_SHIFT (14U) +#define CRU_GATE_CON31_CLK_PWM2_EN_MASK (0x1U << CRU_GATE_CON31_CLK_PWM2_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON31_CLK_PWM2_CAPTURE_EN_SHIFT (15U) +#define CRU_GATE_CON31_CLK_PWM2_CAPTURE_EN_MASK (0x1U << CRU_GATE_CON31_CLK_PWM2_CAPTURE_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON32 */ +#define CRU_GATE_CON32_OFFSET (0x380U) +#define CRU_GATE_CON32_PCLK_PWM3_EN_SHIFT (0U) +#define CRU_GATE_CON32_PCLK_PWM3_EN_MASK (0x1U << CRU_GATE_CON32_PCLK_PWM3_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON32_CLK_PWM3_EN_SHIFT (1U) +#define CRU_GATE_CON32_CLK_PWM3_EN_MASK (0x1U << CRU_GATE_CON32_CLK_PWM3_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON32_CLK_PWM3_CAPTURE_EN_SHIFT (2U) +#define CRU_GATE_CON32_CLK_PWM3_CAPTURE_EN_MASK (0x1U << CRU_GATE_CON32_CLK_PWM3_CAPTURE_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON32_PCLK_TIMER_EN_SHIFT (3U) +#define CRU_GATE_CON32_PCLK_TIMER_EN_MASK (0x1U << CRU_GATE_CON32_PCLK_TIMER_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON32_CLK_TIMER0_EN_SHIFT (4U) +#define CRU_GATE_CON32_CLK_TIMER0_EN_MASK (0x1U << CRU_GATE_CON32_CLK_TIMER0_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON32_CLK_TIMER1_EN_SHIFT (5U) +#define CRU_GATE_CON32_CLK_TIMER1_EN_MASK (0x1U << CRU_GATE_CON32_CLK_TIMER1_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON32_CLK_TIMER2_EN_SHIFT (6U) +#define CRU_GATE_CON32_CLK_TIMER2_EN_MASK (0x1U << CRU_GATE_CON32_CLK_TIMER2_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON32_CLK_TIMER3_EN_SHIFT (7U) +#define CRU_GATE_CON32_CLK_TIMER3_EN_MASK (0x1U << CRU_GATE_CON32_CLK_TIMER3_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON32_CLK_TIMER4_EN_SHIFT (8U) +#define CRU_GATE_CON32_CLK_TIMER4_EN_MASK (0x1U << CRU_GATE_CON32_CLK_TIMER4_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON32_CLK_TIMER5_EN_SHIFT (9U) +#define CRU_GATE_CON32_CLK_TIMER5_EN_MASK (0x1U << CRU_GATE_CON32_CLK_TIMER5_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON32_CLK_I2C_EN_SHIFT (10U) +#define CRU_GATE_CON32_CLK_I2C_EN_MASK (0x1U << CRU_GATE_CON32_CLK_I2C_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON32_DBCLK_GPIO_EN_SHIFT (11U) +#define CRU_GATE_CON32_DBCLK_GPIO_EN_MASK (0x1U << CRU_GATE_CON32_DBCLK_GPIO_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON32_CLK_TIMER_EN_SHIFT (12U) +#define CRU_GATE_CON32_CLK_TIMER_EN_MASK (0x1U << CRU_GATE_CON32_CLK_TIMER_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON32_ACLK_MCU_EN_SHIFT (13U) +#define CRU_GATE_CON32_ACLK_MCU_EN_MASK (0x1U << CRU_GATE_CON32_ACLK_MCU_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON32_PCLK_INTMUX_EN_SHIFT (14U) +#define CRU_GATE_CON32_PCLK_INTMUX_EN_MASK (0x1U << CRU_GATE_CON32_PCLK_INTMUX_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON32_PCLK_MAILBOX_EN_SHIFT (15U) +#define CRU_GATE_CON32_PCLK_MAILBOX_EN_MASK (0x1U << CRU_GATE_CON32_PCLK_MAILBOX_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON33 */ +#define CRU_GATE_CON33_OFFSET (0x384U) +#define CRU_GATE_CON33_ACLK_TOP_HIGH_EN_SHIFT (0U) +#define CRU_GATE_CON33_ACLK_TOP_HIGH_EN_MASK (0x1U << CRU_GATE_CON33_ACLK_TOP_HIGH_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON33_ACLK_TOP_LOW_EN_SHIFT (1U) +#define CRU_GATE_CON33_ACLK_TOP_LOW_EN_MASK (0x1U << CRU_GATE_CON33_ACLK_TOP_LOW_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON33_HCLK_TOP_EN_SHIFT (2U) +#define CRU_GATE_CON33_HCLK_TOP_EN_MASK (0x1U << CRU_GATE_CON33_HCLK_TOP_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON33_PCLK_TOP_EN_SHIFT (3U) +#define CRU_GATE_CON33_PCLK_TOP_EN_MASK (0x1U << CRU_GATE_CON33_PCLK_TOP_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON33_ACLK_TOP_HIGH_NIU_EN_SHIFT (4U) +#define CRU_GATE_CON33_ACLK_TOP_HIGH_NIU_EN_MASK (0x1U << CRU_GATE_CON33_ACLK_TOP_HIGH_NIU_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON33_ACLK_TOP_LOW_NIU_EN_SHIFT (5U) +#define CRU_GATE_CON33_ACLK_TOP_LOW_NIU_EN_MASK (0x1U << CRU_GATE_CON33_ACLK_TOP_LOW_NIU_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON33_HCLK_TOP_NIU_EN_SHIFT (6U) +#define CRU_GATE_CON33_HCLK_TOP_NIU_EN_MASK (0x1U << CRU_GATE_CON33_HCLK_TOP_NIU_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON33_PCLK_TOP_NIU_EN_SHIFT (7U) +#define CRU_GATE_CON33_PCLK_TOP_NIU_EN_MASK (0x1U << CRU_GATE_CON33_PCLK_TOP_NIU_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON33_PCLK_PCIE30PHY_EN_SHIFT (8U) +#define CRU_GATE_CON33_PCLK_PCIE30PHY_EN_MASK (0x1U << CRU_GATE_CON33_PCLK_PCIE30PHY_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON33_CLK_OTPC_ARB_EN_SHIFT (9U) +#define CRU_GATE_CON33_CLK_OTPC_ARB_EN_MASK (0x1U << CRU_GATE_CON33_CLK_OTPC_ARB_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON33_PCLK_TOP_CRU_EN_SHIFT (12U) +#define CRU_GATE_CON33_PCLK_TOP_CRU_EN_MASK (0x1U << CRU_GATE_CON33_PCLK_TOP_CRU_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON33_PCLK_MIPICSIPHY_EN_SHIFT (13U) +#define CRU_GATE_CON33_PCLK_MIPICSIPHY_EN_MASK (0x1U << CRU_GATE_CON33_PCLK_MIPICSIPHY_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON33_PCLK_MIPIDSIPHY0_EN_SHIFT (14U) +#define CRU_GATE_CON33_PCLK_MIPIDSIPHY0_EN_MASK (0x1U << CRU_GATE_CON33_PCLK_MIPIDSIPHY0_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON33_PCLK_MIPIDSIPHY1_EN_SHIFT (15U) +#define CRU_GATE_CON33_PCLK_MIPIDSIPHY1_EN_MASK (0x1U << CRU_GATE_CON33_PCLK_MIPIDSIPHY1_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON34 */ +#define CRU_GATE_CON34_OFFSET (0x388U) +#define CRU_GATE_CON34_PCLK_APB2ASB_CHIP_LEFT_EN_SHIFT (0U) +#define CRU_GATE_CON34_PCLK_APB2ASB_CHIP_LEFT_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_APB2ASB_CHIP_LEFT_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON34_PCLK_APB2ASB_CHIP_BOTTOM_EN_SHIFT (1U) +#define CRU_GATE_CON34_PCLK_APB2ASB_CHIP_BOTTOM_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_APB2ASB_CHIP_BOTTOM_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON34_PCLK_ASB2APB_CHIP_LEFT_EN_SHIFT (2U) +#define CRU_GATE_CON34_PCLK_ASB2APB_CHIP_LEFT_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_ASB2APB_CHIP_LEFT_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON34_PCLK_ASB2APB_CHIP_BOTTOM_EN_SHIFT (3U) +#define CRU_GATE_CON34_PCLK_ASB2APB_CHIP_BOTTOM_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_ASB2APB_CHIP_BOTTOM_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON34_PCLK_PIPEPHY0_EN_SHIFT (4U) +#define CRU_GATE_CON34_PCLK_PIPEPHY0_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_PIPEPHY0_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON34_PCLK_PIPEPHY1_EN_SHIFT (5U) +#define CRU_GATE_CON34_PCLK_PIPEPHY1_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_PIPEPHY1_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON34_PCLK_PIPEPHY2_EN_SHIFT (6U) +#define CRU_GATE_CON34_PCLK_PIPEPHY2_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_PIPEPHY2_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON34_PCLK_USB2PHY0_GRF_EN_SHIFT (7U) +#define CRU_GATE_CON34_PCLK_USB2PHY0_GRF_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_USB2PHY0_GRF_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON34_PCLK_USB2PHY1_GRF_EN_SHIFT (8U) +#define CRU_GATE_CON34_PCLK_USB2PHY1_GRF_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_USB2PHY1_GRF_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON34_PCLK_DDRPHY_EN_SHIFT (9U) +#define CRU_GATE_CON34_PCLK_DDRPHY_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_DDRPHY_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON34_CLK_DDRPHY_EN_SHIFT (10U) +#define CRU_GATE_CON34_CLK_DDRPHY_EN_MASK (0x1U << CRU_GATE_CON34_CLK_DDRPHY_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON34_PCLK_CPU_BOOST_EN_SHIFT (11U) +#define CRU_GATE_CON34_PCLK_CPU_BOOST_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_CPU_BOOST_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON34_CLK_CPU_BOOST_EN_SHIFT (12U) +#define CRU_GATE_CON34_CLK_CPU_BOOST_EN_MASK (0x1U << CRU_GATE_CON34_CLK_CPU_BOOST_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON34_PCLK_OTPPHY_EN_SHIFT (13U) +#define CRU_GATE_CON34_PCLK_OTPPHY_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_OTPPHY_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON34_PCLK_EDPPHY_GRF_EN_SHIFT (14U) +#define CRU_GATE_CON34_PCLK_EDPPHY_GRF_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_EDPPHY_GRF_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON34_CLK_TESTOUT_EN_SHIFT (15U) +#define CRU_GATE_CON34_CLK_TESTOUT_EN_MASK (0x1U << CRU_GATE_CON34_CLK_TESTOUT_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON35 */ +#define CRU_GATE_CON35_OFFSET (0x38CU) +#define CRU_GATE_CON35_CLK_GPLL_DIV_400M_EN_SHIFT (0U) +#define CRU_GATE_CON35_CLK_GPLL_DIV_400M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_GPLL_DIV_400M_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON35_CLK_GPLL_DIV_300M_EN_SHIFT (1U) +#define CRU_GATE_CON35_CLK_GPLL_DIV_300M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_GPLL_DIV_300M_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON35_CLK_GPLL_DIV_200M_EN_SHIFT (2U) +#define CRU_GATE_CON35_CLK_GPLL_DIV_200M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_GPLL_DIV_200M_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON35_CLK_GPLL_DIV_150M_EN_SHIFT (3U) +#define CRU_GATE_CON35_CLK_GPLL_DIV_150M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_GPLL_DIV_150M_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON35_CLK_GPLL_DIV_100M_EN_SHIFT (4U) +#define CRU_GATE_CON35_CLK_GPLL_DIV_100M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_GPLL_DIV_100M_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON35_CLK_GPLL_DIV_75M_EN_SHIFT (5U) +#define CRU_GATE_CON35_CLK_GPLL_DIV_75M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_GPLL_DIV_75M_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON35_CLK_GPLL_DIV_20M_EN_SHIFT (6U) +#define CRU_GATE_CON35_CLK_GPLL_DIV_20M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_GPLL_DIV_20M_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON35_CLK_CPLL_DIV_500M_EN_SHIFT (7U) +#define CRU_GATE_CON35_CLK_CPLL_DIV_500M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_CPLL_DIV_500M_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON35_CLK_CPLL_DIV_333M_EN_SHIFT (8U) +#define CRU_GATE_CON35_CLK_CPLL_DIV_333M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_CPLL_DIV_333M_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON35_CLK_CPLL_DIV_250M_EN_SHIFT (9U) +#define CRU_GATE_CON35_CLK_CPLL_DIV_250M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_CPLL_DIV_250M_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON35_CLK_CPLL_DIV_125M_EN_SHIFT (10U) +#define CRU_GATE_CON35_CLK_CPLL_DIV_125M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_CPLL_DIV_125M_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON35_CLK_CPLL_DIV_100M_EN_SHIFT (11U) +#define CRU_GATE_CON35_CLK_CPLL_DIV_100M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_CPLL_DIV_100M_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON35_CLK_CPLL_DIV_62P5_EN_SHIFT (12U) +#define CRU_GATE_CON35_CLK_CPLL_DIV_62P5_EN_MASK (0x1U << CRU_GATE_CON35_CLK_CPLL_DIV_62P5_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON35_CLK_CPLL_DIV_50M_EN_SHIFT (13U) +#define CRU_GATE_CON35_CLK_CPLL_DIV_50M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_CPLL_DIV_50M_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON35_CLK_CPLL_DIV_25M_EN_SHIFT (14U) +#define CRU_GATE_CON35_CLK_CPLL_DIV_25M_EN_MASK (0x1U << CRU_GATE_CON35_CLK_CPLL_DIV_25M_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON35_CLK_OSC0_DIV_750K_EN_SHIFT (15U) +#define CRU_GATE_CON35_CLK_OSC0_DIV_750K_EN_MASK (0x1U << CRU_GATE_CON35_CLK_OSC0_DIV_750K_EN_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON00 */ +#define CRU_SOFTRST_CON00_OFFSET (0x400U) +#define CRU_SOFTRST_CON00_NCORERESET0_SHIFT (0U) +#define CRU_SOFTRST_CON00_NCORERESET0_MASK (0x1U << CRU_SOFTRST_CON00_NCORERESET0_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON00_NCORERESET1_SHIFT (1U) +#define CRU_SOFTRST_CON00_NCORERESET1_MASK (0x1U << CRU_SOFTRST_CON00_NCORERESET1_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON00_NCORERESET2_SHIFT (2U) +#define CRU_SOFTRST_CON00_NCORERESET2_MASK (0x1U << CRU_SOFTRST_CON00_NCORERESET2_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON00_NCORERESET3_SHIFT (3U) +#define CRU_SOFTRST_CON00_NCORERESET3_MASK (0x1U << CRU_SOFTRST_CON00_NCORERESET3_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON00_NCPUPORESET0_SHIFT (4U) +#define CRU_SOFTRST_CON00_NCPUPORESET0_MASK (0x1U << CRU_SOFTRST_CON00_NCPUPORESET0_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON00_NCPUPORESET1_SHIFT (5U) +#define CRU_SOFTRST_CON00_NCPUPORESET1_MASK (0x1U << CRU_SOFTRST_CON00_NCPUPORESET1_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON00_NCPUPORESET2_SHIFT (6U) +#define CRU_SOFTRST_CON00_NCPUPORESET2_MASK (0x1U << CRU_SOFTRST_CON00_NCPUPORESET2_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON00_NCPUPORESET3_SHIFT (7U) +#define CRU_SOFTRST_CON00_NCPUPORESET3_MASK (0x1U << CRU_SOFTRST_CON00_NCPUPORESET3_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON00_NSRESET_SHIFT (8U) +#define CRU_SOFTRST_CON00_NSRESET_MASK (0x1U << CRU_SOFTRST_CON00_NSRESET_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON00_NSPORESET_SHIFT (9U) +#define CRU_SOFTRST_CON00_NSPORESET_MASK (0x1U << CRU_SOFTRST_CON00_NSPORESET_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON00_NATRESET_SHIFT (10U) +#define CRU_SOFTRST_CON00_NATRESET_MASK (0x1U << CRU_SOFTRST_CON00_NATRESET_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON00_NGICRESET_SHIFT (11U) +#define CRU_SOFTRST_CON00_NGICRESET_MASK (0x1U << CRU_SOFTRST_CON00_NGICRESET_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON00_NPRESET_SHIFT (12U) +#define CRU_SOFTRST_CON00_NPRESET_MASK (0x1U << CRU_SOFTRST_CON00_NPRESET_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON00_NPERIPHRESET_SHIFT (13U) +#define CRU_SOFTRST_CON00_NPERIPHRESET_MASK (0x1U << CRU_SOFTRST_CON00_NPERIPHRESET_SHIFT) /* 0x00002000 */ +/* SOFTRST_CON01 */ +#define CRU_SOFTRST_CON01_OFFSET (0x404U) +#define CRU_SOFTRST_CON01_ARESETN_CORE_NIU2DDR_SHIFT (0U) +#define CRU_SOFTRST_CON01_ARESETN_CORE_NIU2DDR_MASK (0x1U << CRU_SOFTRST_CON01_ARESETN_CORE_NIU2DDR_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON01_ARESETN_CORE_NIU2BUS_SHIFT (1U) +#define CRU_SOFTRST_CON01_ARESETN_CORE_NIU2BUS_MASK (0x1U << CRU_SOFTRST_CON01_ARESETN_CORE_NIU2BUS_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON01_PRESETN_DBG_NIU_SHIFT (2U) +#define CRU_SOFTRST_CON01_PRESETN_DBG_NIU_MASK (0x1U << CRU_SOFTRST_CON01_PRESETN_DBG_NIU_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON01_PRESETN_DBG_SHIFT (3U) +#define CRU_SOFTRST_CON01_PRESETN_DBG_MASK (0x1U << CRU_SOFTRST_CON01_PRESETN_DBG_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON01_PRESETN_DBG_DAPLITE_SHIFT (4U) +#define CRU_SOFTRST_CON01_PRESETN_DBG_DAPLITE_MASK (0x1U << CRU_SOFTRST_CON01_PRESETN_DBG_DAPLITE_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON01_RESETN_DAP_SHIFT (5U) +#define CRU_SOFTRST_CON01_RESETN_DAP_MASK (0x1U << CRU_SOFTRST_CON01_RESETN_DAP_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON01_ARESETN_ADB400_CORE2GIC_SHIFT (6U) +#define CRU_SOFTRST_CON01_ARESETN_ADB400_CORE2GIC_MASK (0x1U << CRU_SOFTRST_CON01_ARESETN_ADB400_CORE2GIC_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON01_ARESETN_ADB400_GIC2CORE_SHIFT (7U) +#define CRU_SOFTRST_CON01_ARESETN_ADB400_GIC2CORE_MASK (0x1U << CRU_SOFTRST_CON01_ARESETN_ADB400_GIC2CORE_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON01_PRESETN_CORE_GRF_SHIFT (8U) +#define CRU_SOFTRST_CON01_PRESETN_CORE_GRF_MASK (0x1U << CRU_SOFTRST_CON01_PRESETN_CORE_GRF_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON01_PRESETN_CORE_PVTM_SHIFT (9U) +#define CRU_SOFTRST_CON01_PRESETN_CORE_PVTM_MASK (0x1U << CRU_SOFTRST_CON01_PRESETN_CORE_PVTM_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON01_RESETN_CORE_PVTM_SHIFT (10U) +#define CRU_SOFTRST_CON01_RESETN_CORE_PVTM_MASK (0x1U << CRU_SOFTRST_CON01_RESETN_CORE_PVTM_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON01_RESETN_CORE_PVTPLL_SHIFT (11U) +#define CRU_SOFTRST_CON01_RESETN_CORE_PVTPLL_MASK (0x1U << CRU_SOFTRST_CON01_RESETN_CORE_PVTPLL_SHIFT) /* 0x00000800 */ +/* SOFTRST_CON02 */ +#define CRU_SOFTRST_CON02_OFFSET (0x408U) +#define CRU_SOFTRST_CON02_RESETN_GPU_SHIFT (0U) +#define CRU_SOFTRST_CON02_RESETN_GPU_MASK (0x1U << CRU_SOFTRST_CON02_RESETN_GPU_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON02_ARESETN_GPU_NIU_SHIFT (1U) +#define CRU_SOFTRST_CON02_ARESETN_GPU_NIU_MASK (0x1U << CRU_SOFTRST_CON02_ARESETN_GPU_NIU_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON02_PRESETN_GPU_NIU_SHIFT (2U) +#define CRU_SOFTRST_CON02_PRESETN_GPU_NIU_MASK (0x1U << CRU_SOFTRST_CON02_PRESETN_GPU_NIU_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON02_PRESETN_GPU_PVTM_SHIFT (3U) +#define CRU_SOFTRST_CON02_PRESETN_GPU_PVTM_MASK (0x1U << CRU_SOFTRST_CON02_PRESETN_GPU_PVTM_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON02_RESETN_GPU_PVTM_SHIFT (4U) +#define CRU_SOFTRST_CON02_RESETN_GPU_PVTM_MASK (0x1U << CRU_SOFTRST_CON02_RESETN_GPU_PVTM_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON02_RESETN_GPU_PVTPLL_SHIFT (5U) +#define CRU_SOFTRST_CON02_RESETN_GPU_PVTPLL_MASK (0x1U << CRU_SOFTRST_CON02_RESETN_GPU_PVTPLL_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON02_ARESETN_NPU_NIU_SHIFT (8U) +#define CRU_SOFTRST_CON02_ARESETN_NPU_NIU_MASK (0x1U << CRU_SOFTRST_CON02_ARESETN_NPU_NIU_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON02_HRESETN_NPU_NIU_SHIFT (9U) +#define CRU_SOFTRST_CON02_HRESETN_NPU_NIU_MASK (0x1U << CRU_SOFTRST_CON02_HRESETN_NPU_NIU_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON02_PRESETN_NPU_NIU_SHIFT (10U) +#define CRU_SOFTRST_CON02_PRESETN_NPU_NIU_MASK (0x1U << CRU_SOFTRST_CON02_PRESETN_NPU_NIU_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON02_ARESETN_RKNN_SHIFT (11U) +#define CRU_SOFTRST_CON02_ARESETN_RKNN_MASK (0x1U << CRU_SOFTRST_CON02_ARESETN_RKNN_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON02_HRESETN_RKNN_SHIFT (12U) +#define CRU_SOFTRST_CON02_HRESETN_RKNN_MASK (0x1U << CRU_SOFTRST_CON02_HRESETN_RKNN_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON02_PRESETN_NPU_PVTM_SHIFT (13U) +#define CRU_SOFTRST_CON02_PRESETN_NPU_PVTM_MASK (0x1U << CRU_SOFTRST_CON02_PRESETN_NPU_PVTM_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON02_RESETN_NPU_PVTM_SHIFT (14U) +#define CRU_SOFTRST_CON02_RESETN_NPU_PVTM_MASK (0x1U << CRU_SOFTRST_CON02_RESETN_NPU_PVTM_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON02_RESETN_NPU_PVTPLL_SHIFT (15U) +#define CRU_SOFTRST_CON02_RESETN_NPU_PVTPLL_MASK (0x1U << CRU_SOFTRST_CON02_RESETN_NPU_PVTPLL_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON03 */ +#define CRU_SOFTRST_CON03_OFFSET (0x40CU) +#define CRU_SOFTRST_CON03_ARESETN_MSCH_SHIFT (3U) +#define CRU_SOFTRST_CON03_ARESETN_MSCH_MASK (0x1U << CRU_SOFTRST_CON03_ARESETN_MSCH_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON03_RESETN_HWFFC_CTRL_SHIFT (4U) +#define CRU_SOFTRST_CON03_RESETN_HWFFC_CTRL_MASK (0x1U << CRU_SOFTRST_CON03_RESETN_HWFFC_CTRL_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON03_RESETN_DDR_ALWAYSON_SHIFT (5U) +#define CRU_SOFTRST_CON03_RESETN_DDR_ALWAYSON_MASK (0x1U << CRU_SOFTRST_CON03_RESETN_DDR_ALWAYSON_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON03_ARESETN_DDRSPLIT_SHIFT (6U) +#define CRU_SOFTRST_CON03_ARESETN_DDRSPLIT_MASK (0x1U << CRU_SOFTRST_CON03_ARESETN_DDRSPLIT_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON03_RESETN_DDRDFI_CTL_SHIFT (7U) +#define CRU_SOFTRST_CON03_RESETN_DDRDFI_CTL_MASK (0x1U << CRU_SOFTRST_CON03_RESETN_DDRDFI_CTL_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON03_ARESETN_DMA2DDR_SHIFT (9U) +#define CRU_SOFTRST_CON03_ARESETN_DMA2DDR_MASK (0x1U << CRU_SOFTRST_CON03_ARESETN_DMA2DDR_SHIFT) /* 0x00000200 */ +/* SOFTRST_CON04 */ +#define CRU_SOFTRST_CON04_OFFSET (0x410U) +#define CRU_SOFTRST_CON04_ARESETN_PERIMID_NIU_SHIFT (0U) +#define CRU_SOFTRST_CON04_ARESETN_PERIMID_NIU_MASK (0x1U << CRU_SOFTRST_CON04_ARESETN_PERIMID_NIU_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON04_HRESETN_PERIMID_NIU_SHIFT (1U) +#define CRU_SOFTRST_CON04_HRESETN_PERIMID_NIU_MASK (0x1U << CRU_SOFTRST_CON04_HRESETN_PERIMID_NIU_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON04_ARESETN_GIC_AUDIO_NIU_SHIFT (2U) +#define CRU_SOFTRST_CON04_ARESETN_GIC_AUDIO_NIU_MASK (0x1U << CRU_SOFTRST_CON04_ARESETN_GIC_AUDIO_NIU_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON04_HRESETN_GIC_AUDIO_NIU_SHIFT (3U) +#define CRU_SOFTRST_CON04_HRESETN_GIC_AUDIO_NIU_MASK (0x1U << CRU_SOFTRST_CON04_HRESETN_GIC_AUDIO_NIU_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON04_ARESETN_GIC600_SHIFT (4U) +#define CRU_SOFTRST_CON04_ARESETN_GIC600_MASK (0x1U << CRU_SOFTRST_CON04_ARESETN_GIC600_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON04_ARESETN_GIC600_DEBUG_SHIFT (5U) +#define CRU_SOFTRST_CON04_ARESETN_GIC600_DEBUG_MASK (0x1U << CRU_SOFTRST_CON04_ARESETN_GIC600_DEBUG_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON04_ARESETN_GICADB_CORE2GIC_SHIFT (6U) +#define CRU_SOFTRST_CON04_ARESETN_GICADB_CORE2GIC_MASK (0x1U << CRU_SOFTRST_CON04_ARESETN_GICADB_CORE2GIC_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON04_ARESETN_GICADB_GIC2CORE_SHIFT (7U) +#define CRU_SOFTRST_CON04_ARESETN_GICADB_GIC2CORE_MASK (0x1U << CRU_SOFTRST_CON04_ARESETN_GICADB_GIC2CORE_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON04_ARESETN_SPINLOCK_SHIFT (8U) +#define CRU_SOFTRST_CON04_ARESETN_SPINLOCK_MASK (0x1U << CRU_SOFTRST_CON04_ARESETN_SPINLOCK_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON04_HRESETN_SDMMC_BUFFER_SHIFT (9U) +#define CRU_SOFTRST_CON04_HRESETN_SDMMC_BUFFER_MASK (0x1U << CRU_SOFTRST_CON04_HRESETN_SDMMC_BUFFER_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON04_DRESETN_SDMMC_BUFFER_SHIFT (10U) +#define CRU_SOFTRST_CON04_DRESETN_SDMMC_BUFFER_MASK (0x1U << CRU_SOFTRST_CON04_DRESETN_SDMMC_BUFFER_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON04_HRESETN_I2S0_8CH_SHIFT (11U) +#define CRU_SOFTRST_CON04_HRESETN_I2S0_8CH_MASK (0x1U << CRU_SOFTRST_CON04_HRESETN_I2S0_8CH_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON04_HRESETN_I2S1_8CH_SHIFT (12U) +#define CRU_SOFTRST_CON04_HRESETN_I2S1_8CH_MASK (0x1U << CRU_SOFTRST_CON04_HRESETN_I2S1_8CH_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON04_HRESETN_I2S2_2CH_SHIFT (13U) +#define CRU_SOFTRST_CON04_HRESETN_I2S2_2CH_MASK (0x1U << CRU_SOFTRST_CON04_HRESETN_I2S2_2CH_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON04_HRESETN_I2S3_2CH_SHIFT (14U) +#define CRU_SOFTRST_CON04_HRESETN_I2S3_2CH_MASK (0x1U << CRU_SOFTRST_CON04_HRESETN_I2S3_2CH_SHIFT) /* 0x00004000 */ +/* SOFTRST_CON05 */ +#define CRU_SOFTRST_CON05_OFFSET (0x414U) +#define CRU_SOFTRST_CON05_MRESETN_I2S0_8CH_TX_SHIFT (0U) +#define CRU_SOFTRST_CON05_MRESETN_I2S0_8CH_TX_MASK (0x1U << CRU_SOFTRST_CON05_MRESETN_I2S0_8CH_TX_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON05_MRESETN_I2S0_8CH_RX_SHIFT (1U) +#define CRU_SOFTRST_CON05_MRESETN_I2S0_8CH_RX_MASK (0x1U << CRU_SOFTRST_CON05_MRESETN_I2S0_8CH_RX_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON05_MRESETN_I2S1_8CH_TX_SHIFT (2U) +#define CRU_SOFTRST_CON05_MRESETN_I2S1_8CH_TX_MASK (0x1U << CRU_SOFTRST_CON05_MRESETN_I2S1_8CH_TX_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON05_MRESETN_I2S1_8CH_RX_SHIFT (3U) +#define CRU_SOFTRST_CON05_MRESETN_I2S1_8CH_RX_MASK (0x1U << CRU_SOFTRST_CON05_MRESETN_I2S1_8CH_RX_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON05_MRESETN_I2S2_2CH_SHIFT (4U) +#define CRU_SOFTRST_CON05_MRESETN_I2S2_2CH_MASK (0x1U << CRU_SOFTRST_CON05_MRESETN_I2S2_2CH_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON05_MRESETN_I2S3_2CH_TX_SHIFT (5U) +#define CRU_SOFTRST_CON05_MRESETN_I2S3_2CH_TX_MASK (0x1U << CRU_SOFTRST_CON05_MRESETN_I2S3_2CH_TX_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON05_MRESETN_I2S3_2CH_RX_SHIFT (6U) +#define CRU_SOFTRST_CON05_MRESETN_I2S3_2CH_RX_MASK (0x1U << CRU_SOFTRST_CON05_MRESETN_I2S3_2CH_RX_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON05_HRESETN_PDM_SHIFT (7U) +#define CRU_SOFTRST_CON05_HRESETN_PDM_MASK (0x1U << CRU_SOFTRST_CON05_HRESETN_PDM_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON05_MRESETN_PDM_SHIFT (8U) +#define CRU_SOFTRST_CON05_MRESETN_PDM_MASK (0x1U << CRU_SOFTRST_CON05_MRESETN_PDM_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON05_HRESETN_VAD_SHIFT (9U) +#define CRU_SOFTRST_CON05_HRESETN_VAD_MASK (0x1U << CRU_SOFTRST_CON05_HRESETN_VAD_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON05_HRESETN_SPDIF_8CH_SHIFT (10U) +#define CRU_SOFTRST_CON05_HRESETN_SPDIF_8CH_MASK (0x1U << CRU_SOFTRST_CON05_HRESETN_SPDIF_8CH_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON05_MRESETN_SPDIF_8CH_SHIFT (11U) +#define CRU_SOFTRST_CON05_MRESETN_SPDIF_8CH_MASK (0x1U << CRU_SOFTRST_CON05_MRESETN_SPDIF_8CH_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON05_HRESETN_AUDPWM_SHIFT (12U) +#define CRU_SOFTRST_CON05_HRESETN_AUDPWM_MASK (0x1U << CRU_SOFTRST_CON05_HRESETN_AUDPWM_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON05_SRESETN_AUDPWM_SHIFT (13U) +#define CRU_SOFTRST_CON05_SRESETN_AUDPWM_MASK (0x1U << CRU_SOFTRST_CON05_SRESETN_AUDPWM_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON05_HRESETN_ACDCDIG_SHIFT (14U) +#define CRU_SOFTRST_CON05_HRESETN_ACDCDIG_MASK (0x1U << CRU_SOFTRST_CON05_HRESETN_ACDCDIG_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON05_RESETN_ACDCDIG_SHIFT (15U) +#define CRU_SOFTRST_CON05_RESETN_ACDCDIG_MASK (0x1U << CRU_SOFTRST_CON05_RESETN_ACDCDIG_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON06 */ +#define CRU_SOFTRST_CON06_OFFSET (0x418U) +#define CRU_SOFTRST_CON06_ARESETN_SECURE_FLASH_NIU_SHIFT (0U) +#define CRU_SOFTRST_CON06_ARESETN_SECURE_FLASH_NIU_MASK (0x1U << CRU_SOFTRST_CON06_ARESETN_SECURE_FLASH_NIU_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON06_HRESETN_SECURE_FLASH_NIU_SHIFT (1U) +#define CRU_SOFTRST_CON06_HRESETN_SECURE_FLASH_NIU_MASK (0x1U << CRU_SOFTRST_CON06_HRESETN_SECURE_FLASH_NIU_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON06_ARESETN_CRYPTO_NS_SHIFT (7U) +#define CRU_SOFTRST_CON06_ARESETN_CRYPTO_NS_MASK (0x1U << CRU_SOFTRST_CON06_ARESETN_CRYPTO_NS_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON06_HRESETN_CRYPTO_NS_SHIFT (8U) +#define CRU_SOFTRST_CON06_HRESETN_CRYPTO_NS_MASK (0x1U << CRU_SOFTRST_CON06_HRESETN_CRYPTO_NS_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON06_RESETN_CRYPTO_NS_CORE_SHIFT (9U) +#define CRU_SOFTRST_CON06_RESETN_CRYPTO_NS_CORE_MASK (0x1U << CRU_SOFTRST_CON06_RESETN_CRYPTO_NS_CORE_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON06_RESETN_CRYPTO_NS_PKA_SHIFT (10U) +#define CRU_SOFTRST_CON06_RESETN_CRYPTO_NS_PKA_MASK (0x1U << CRU_SOFTRST_CON06_RESETN_CRYPTO_NS_PKA_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON06_RESETN_CRYPTO_NS_RNG_SHIFT (11U) +#define CRU_SOFTRST_CON06_RESETN_CRYPTO_NS_RNG_MASK (0x1U << CRU_SOFTRST_CON06_RESETN_CRYPTO_NS_RNG_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON06_HRESETN_TRNG_NS_SHIFT (12U) +#define CRU_SOFTRST_CON06_HRESETN_TRNG_NS_MASK (0x1U << CRU_SOFTRST_CON06_HRESETN_TRNG_NS_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON06_RESETN_TRNG_NS_SHIFT (13U) +#define CRU_SOFTRST_CON06_RESETN_TRNG_NS_MASK (0x1U << CRU_SOFTRST_CON06_RESETN_TRNG_NS_SHIFT) /* 0x00002000 */ +/* SOFTRST_CON07 */ +#define CRU_SOFTRST_CON07_OFFSET (0x41CU) +#define CRU_SOFTRST_CON07_HRESETN_NANDC_SHIFT (0U) +#define CRU_SOFTRST_CON07_HRESETN_NANDC_MASK (0x1U << CRU_SOFTRST_CON07_HRESETN_NANDC_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON07_NRESETN_NANDC_SHIFT (1U) +#define CRU_SOFTRST_CON07_NRESETN_NANDC_MASK (0x1U << CRU_SOFTRST_CON07_NRESETN_NANDC_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON07_HRESETN_SFC_SHIFT (2U) +#define CRU_SOFTRST_CON07_HRESETN_SFC_MASK (0x1U << CRU_SOFTRST_CON07_HRESETN_SFC_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON07_HRESETN_SFC_XIP_SHIFT (3U) +#define CRU_SOFTRST_CON07_HRESETN_SFC_XIP_MASK (0x1U << CRU_SOFTRST_CON07_HRESETN_SFC_XIP_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON07_SRESETN_SFC_SHIFT (4U) +#define CRU_SOFTRST_CON07_SRESETN_SFC_MASK (0x1U << CRU_SOFTRST_CON07_SRESETN_SFC_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON07_ARESETN_EMMC_SHIFT (5U) +#define CRU_SOFTRST_CON07_ARESETN_EMMC_MASK (0x1U << CRU_SOFTRST_CON07_ARESETN_EMMC_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON07_HRESETN_EMMC_SHIFT (6U) +#define CRU_SOFTRST_CON07_HRESETN_EMMC_MASK (0x1U << CRU_SOFTRST_CON07_HRESETN_EMMC_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON07_BRESETN_EMMC_SHIFT (7U) +#define CRU_SOFTRST_CON07_BRESETN_EMMC_MASK (0x1U << CRU_SOFTRST_CON07_BRESETN_EMMC_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON07_CRESETN_EMMC_SHIFT (8U) +#define CRU_SOFTRST_CON07_CRESETN_EMMC_MASK (0x1U << CRU_SOFTRST_CON07_CRESETN_EMMC_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON07_TRESETN_EMMC_SHIFT (9U) +#define CRU_SOFTRST_CON07_TRESETN_EMMC_MASK (0x1U << CRU_SOFTRST_CON07_TRESETN_EMMC_SHIFT) /* 0x00000200 */ +/* SOFTRST_CON08 */ +#define CRU_SOFTRST_CON08_OFFSET (0x420U) +#define CRU_SOFTRST_CON08_ARESETN_PIPE_NIU_SHIFT (0U) +#define CRU_SOFTRST_CON08_ARESETN_PIPE_NIU_MASK (0x1U << CRU_SOFTRST_CON08_ARESETN_PIPE_NIU_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON08_PRESETN_PIPE_NIU_SHIFT (2U) +#define CRU_SOFTRST_CON08_PRESETN_PIPE_NIU_MASK (0x1U << CRU_SOFTRST_CON08_PRESETN_PIPE_NIU_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON08_PRESETN_PIPE_GRF_SHIFT (5U) +#define CRU_SOFTRST_CON08_PRESETN_PIPE_GRF_MASK (0x1U << CRU_SOFTRST_CON08_PRESETN_PIPE_GRF_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON08_ARESETN_SATA0_SHIFT (6U) +#define CRU_SOFTRST_CON08_ARESETN_SATA0_MASK (0x1U << CRU_SOFTRST_CON08_ARESETN_SATA0_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON08_RESETN_SATA0_PIPE_SHIFT (7U) +#define CRU_SOFTRST_CON08_RESETN_SATA0_PIPE_MASK (0x1U << CRU_SOFTRST_CON08_RESETN_SATA0_PIPE_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON08_RESETN_SATA0_PMALIVE_SHIFT (8U) +#define CRU_SOFTRST_CON08_RESETN_SATA0_PMALIVE_MASK (0x1U << CRU_SOFTRST_CON08_RESETN_SATA0_PMALIVE_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON08_RESETN_SATA0_RXOOB_SHIFT (9U) +#define CRU_SOFTRST_CON08_RESETN_SATA0_RXOOB_MASK (0x1U << CRU_SOFTRST_CON08_RESETN_SATA0_RXOOB_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON08_ARESETN_SATA1_SHIFT (10U) +#define CRU_SOFTRST_CON08_ARESETN_SATA1_MASK (0x1U << CRU_SOFTRST_CON08_ARESETN_SATA1_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON08_RESETN_SATA1_PIPE_SHIFT (11U) +#define CRU_SOFTRST_CON08_RESETN_SATA1_PIPE_MASK (0x1U << CRU_SOFTRST_CON08_RESETN_SATA1_PIPE_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON08_RESETN_SATA1_PMALIVE_SHIFT (12U) +#define CRU_SOFTRST_CON08_RESETN_SATA1_PMALIVE_MASK (0x1U << CRU_SOFTRST_CON08_RESETN_SATA1_PMALIVE_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON08_RESETN_SATA1_RXOOB_SHIFT (13U) +#define CRU_SOFTRST_CON08_RESETN_SATA1_RXOOB_MASK (0x1U << CRU_SOFTRST_CON08_RESETN_SATA1_RXOOB_SHIFT) /* 0x00002000 */ +/* SOFTRST_CON09 */ +#define CRU_SOFTRST_CON09_OFFSET (0x424U) +#define CRU_SOFTRST_CON09_ARESETN_SATA2_SHIFT (0U) +#define CRU_SOFTRST_CON09_ARESETN_SATA2_MASK (0x1U << CRU_SOFTRST_CON09_ARESETN_SATA2_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON09_RESETN_SATA2_PIPE_SHIFT (1U) +#define CRU_SOFTRST_CON09_RESETN_SATA2_PIPE_MASK (0x1U << CRU_SOFTRST_CON09_RESETN_SATA2_PIPE_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON09_RESETN_SATA2_PMALIVE_SHIFT (2U) +#define CRU_SOFTRST_CON09_RESETN_SATA2_PMALIVE_MASK (0x1U << CRU_SOFTRST_CON09_RESETN_SATA2_PMALIVE_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON09_RESETN_SATA2_RXOOB_SHIFT (3U) +#define CRU_SOFTRST_CON09_RESETN_SATA2_RXOOB_MASK (0x1U << CRU_SOFTRST_CON09_RESETN_SATA2_RXOOB_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON09_RESETN_USB3OTG0_SHIFT (4U) +#define CRU_SOFTRST_CON09_RESETN_USB3OTG0_MASK (0x1U << CRU_SOFTRST_CON09_RESETN_USB3OTG0_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON09_RESETN_USB3OTG1_SHIFT (5U) +#define CRU_SOFTRST_CON09_RESETN_USB3OTG1_MASK (0x1U << CRU_SOFTRST_CON09_RESETN_USB3OTG1_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON09_RESETN_XPCS_SHIFT (6U) +#define CRU_SOFTRST_CON09_RESETN_XPCS_MASK (0x1U << CRU_SOFTRST_CON09_RESETN_XPCS_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON09_RESETN_XPCS_TX_DIV10_SHIFT (7U) +#define CRU_SOFTRST_CON09_RESETN_XPCS_TX_DIV10_MASK (0x1U << CRU_SOFTRST_CON09_RESETN_XPCS_TX_DIV10_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON09_RESETN_XPCS_RX_DIV10_SHIFT (8U) +#define CRU_SOFTRST_CON09_RESETN_XPCS_RX_DIV10_MASK (0x1U << CRU_SOFTRST_CON09_RESETN_XPCS_RX_DIV10_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON09_RESETN_XPCS_XGXS_RX_SHIFT (9U) +#define CRU_SOFTRST_CON09_RESETN_XPCS_XGXS_RX_MASK (0x1U << CRU_SOFTRST_CON09_RESETN_XPCS_XGXS_RX_SHIFT) /* 0x00000200 */ +/* SOFTRST_CON10 */ +#define CRU_SOFTRST_CON10_OFFSET (0x428U) +#define CRU_SOFTRST_CON10_PRESETN_PCIE20_SHIFT (0U) +#define CRU_SOFTRST_CON10_PRESETN_PCIE20_MASK (0x1U << CRU_SOFTRST_CON10_PRESETN_PCIE20_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON10_RESETN_PCIE20_POWERUP_REQ_SHIFT (1U) +#define CRU_SOFTRST_CON10_RESETN_PCIE20_POWERUP_REQ_MASK (0x1U << CRU_SOFTRST_CON10_RESETN_PCIE20_POWERUP_REQ_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON10_MSTR_ARESET_PCIE20_REQ_SHIFT (2U) +#define CRU_SOFTRST_CON10_MSTR_ARESET_PCIE20_REQ_MASK (0x1U << CRU_SOFTRST_CON10_MSTR_ARESET_PCIE20_REQ_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON10_SLV_ARESET_PCIE20_REQ_SHIFT (3U) +#define CRU_SOFTRST_CON10_SLV_ARESET_PCIE20_REQ_MASK (0x1U << CRU_SOFTRST_CON10_SLV_ARESET_PCIE20_REQ_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON10_DBI_ARESET_PCIE20_REQ_SHIFT (4U) +#define CRU_SOFTRST_CON10_DBI_ARESET_PCIE20_REQ_MASK (0x1U << CRU_SOFTRST_CON10_DBI_ARESET_PCIE20_REQ_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON10_BRESET_PCIE20_REQ_SHIFT (5U) +#define CRU_SOFTRST_CON10_BRESET_PCIE20_REQ_MASK (0x1U << CRU_SOFTRST_CON10_BRESET_PCIE20_REQ_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON10_PERST_PCIE20_REQ_SHIFT (6U) +#define CRU_SOFTRST_CON10_PERST_PCIE20_REQ_MASK (0x1U << CRU_SOFTRST_CON10_PERST_PCIE20_REQ_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON10_CORE_RST_PCIE20_REQ_SHIFT (7U) +#define CRU_SOFTRST_CON10_CORE_RST_PCIE20_REQ_MASK (0x1U << CRU_SOFTRST_CON10_CORE_RST_PCIE20_REQ_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON10_NSTICKY_RST_PCIE20_REQ_SHIFT (8U) +#define CRU_SOFTRST_CON10_NSTICKY_RST_PCIE20_REQ_MASK (0x1U << CRU_SOFTRST_CON10_NSTICKY_RST_PCIE20_REQ_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON10_STICKY_RST_PCIE20_REQ_SHIFT (9U) +#define CRU_SOFTRST_CON10_STICKY_RST_PCIE20_REQ_MASK (0x1U << CRU_SOFTRST_CON10_STICKY_RST_PCIE20_REQ_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON10_PWR_RST_PCIE20_REQ_SHIFT (10U) +#define CRU_SOFTRST_CON10_PWR_RST_PCIE20_REQ_MASK (0x1U << CRU_SOFTRST_CON10_PWR_RST_PCIE20_REQ_SHIFT) /* 0x00000400 */ +/* SOFTRST_CON11 */ +#define CRU_SOFTRST_CON11_OFFSET (0x42CU) +#define CRU_SOFTRST_CON11_PRESETN_PCIE30X1_SHIFT (0U) +#define CRU_SOFTRST_CON11_PRESETN_PCIE30X1_MASK (0x1U << CRU_SOFTRST_CON11_PRESETN_PCIE30X1_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON11_RESETN_PCIE30X1_POWERUP_REQ_SHIFT (1U) +#define CRU_SOFTRST_CON11_RESETN_PCIE30X1_POWERUP_REQ_MASK (0x1U << CRU_SOFTRST_CON11_RESETN_PCIE30X1_POWERUP_REQ_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON11_MSTR_ARESET_PCIE30X1_REQ_SHIFT (2U) +#define CRU_SOFTRST_CON11_MSTR_ARESET_PCIE30X1_REQ_MASK (0x1U << CRU_SOFTRST_CON11_MSTR_ARESET_PCIE30X1_REQ_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON11_SLV_ARESET_PCIE30X1_REQ_SHIFT (3U) +#define CRU_SOFTRST_CON11_SLV_ARESET_PCIE30X1_REQ_MASK (0x1U << CRU_SOFTRST_CON11_SLV_ARESET_PCIE30X1_REQ_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON11_DBI_ARESET_PCIE30X1_REQ_SHIFT (4U) +#define CRU_SOFTRST_CON11_DBI_ARESET_PCIE30X1_REQ_MASK (0x1U << CRU_SOFTRST_CON11_DBI_ARESET_PCIE30X1_REQ_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON11_BRESET_PCIE30X1_REQ_SHIFT (5U) +#define CRU_SOFTRST_CON11_BRESET_PCIE30X1_REQ_MASK (0x1U << CRU_SOFTRST_CON11_BRESET_PCIE30X1_REQ_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON11_PERST_PCIE30X1_REQ_SHIFT (6U) +#define CRU_SOFTRST_CON11_PERST_PCIE30X1_REQ_MASK (0x1U << CRU_SOFTRST_CON11_PERST_PCIE30X1_REQ_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON11_CORE_RST_PCIE30X1_REQ_SHIFT (7U) +#define CRU_SOFTRST_CON11_CORE_RST_PCIE30X1_REQ_MASK (0x1U << CRU_SOFTRST_CON11_CORE_RST_PCIE30X1_REQ_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON11_NSTICKY_RST_PCIE30X1_REQ_SHIFT (8U) +#define CRU_SOFTRST_CON11_NSTICKY_RST_PCIE30X1_REQ_MASK (0x1U << CRU_SOFTRST_CON11_NSTICKY_RST_PCIE30X1_REQ_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON11_STICKY_RST_PCIE30X1_REQ_SHIFT (9U) +#define CRU_SOFTRST_CON11_STICKY_RST_PCIE30X1_REQ_MASK (0x1U << CRU_SOFTRST_CON11_STICKY_RST_PCIE30X1_REQ_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON11_PWR_RST_PCIE30X1_REQ_SHIFT (10U) +#define CRU_SOFTRST_CON11_PWR_RST_PCIE30X1_REQ_MASK (0x1U << CRU_SOFTRST_CON11_PWR_RST_PCIE30X1_REQ_SHIFT) /* 0x00000400 */ +/* SOFTRST_CON12 */ +#define CRU_SOFTRST_CON12_OFFSET (0x430U) +#define CRU_SOFTRST_CON12_PRESETN_PCIE30X2_SHIFT (0U) +#define CRU_SOFTRST_CON12_PRESETN_PCIE30X2_MASK (0x1U << CRU_SOFTRST_CON12_PRESETN_PCIE30X2_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON12_RESETN_PCIE30X2_POWERUP_REQ_SHIFT (1U) +#define CRU_SOFTRST_CON12_RESETN_PCIE30X2_POWERUP_REQ_MASK (0x1U << CRU_SOFTRST_CON12_RESETN_PCIE30X2_POWERUP_REQ_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON12_MSTR_ARESET_PCIE30X2_REQ_SHIFT (2U) +#define CRU_SOFTRST_CON12_MSTR_ARESET_PCIE30X2_REQ_MASK (0x1U << CRU_SOFTRST_CON12_MSTR_ARESET_PCIE30X2_REQ_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON12_SLV_ARESET_PCIE30X2_REQ_SHIFT (3U) +#define CRU_SOFTRST_CON12_SLV_ARESET_PCIE30X2_REQ_MASK (0x1U << CRU_SOFTRST_CON12_SLV_ARESET_PCIE30X2_REQ_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON12_DBI_ARESET_PCIE30X2_REQ_SHIFT (4U) +#define CRU_SOFTRST_CON12_DBI_ARESET_PCIE30X2_REQ_MASK (0x1U << CRU_SOFTRST_CON12_DBI_ARESET_PCIE30X2_REQ_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON12_BRESET_PCIE30X2_REQ_SHIFT (5U) +#define CRU_SOFTRST_CON12_BRESET_PCIE30X2_REQ_MASK (0x1U << CRU_SOFTRST_CON12_BRESET_PCIE30X2_REQ_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON12_PERST_PCIE30X2_REQ_SHIFT (6U) +#define CRU_SOFTRST_CON12_PERST_PCIE30X2_REQ_MASK (0x1U << CRU_SOFTRST_CON12_PERST_PCIE30X2_REQ_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON12_CORE_RST_PCIE30X2_REQ_SHIFT (7U) +#define CRU_SOFTRST_CON12_CORE_RST_PCIE30X2_REQ_MASK (0x1U << CRU_SOFTRST_CON12_CORE_RST_PCIE30X2_REQ_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON12_NSTICKY_RST_PCIE30X2_REQ_SHIFT (8U) +#define CRU_SOFTRST_CON12_NSTICKY_RST_PCIE30X2_REQ_MASK (0x1U << CRU_SOFTRST_CON12_NSTICKY_RST_PCIE30X2_REQ_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON12_STICKY_RST_PCIE30X2_REQ_SHIFT (9U) +#define CRU_SOFTRST_CON12_STICKY_RST_PCIE30X2_REQ_MASK (0x1U << CRU_SOFTRST_CON12_STICKY_RST_PCIE30X2_REQ_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON12_PWR_RST_PCIE30X2_REQ_SHIFT (10U) +#define CRU_SOFTRST_CON12_PWR_RST_PCIE30X2_REQ_MASK (0x1U << CRU_SOFTRST_CON12_PWR_RST_PCIE30X2_REQ_SHIFT) /* 0x00000400 */ +/* SOFTRST_CON13 */ +#define CRU_SOFTRST_CON13_OFFSET (0x434U) +#define CRU_SOFTRST_CON13_ARESETN_PHP_NIU_SHIFT (0U) +#define CRU_SOFTRST_CON13_ARESETN_PHP_NIU_MASK (0x1U << CRU_SOFTRST_CON13_ARESETN_PHP_NIU_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON13_HRESETN_PHP_NIU_SHIFT (1U) +#define CRU_SOFTRST_CON13_HRESETN_PHP_NIU_MASK (0x1U << CRU_SOFTRST_CON13_HRESETN_PHP_NIU_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON13_PRESETN_PHP_NIU_SHIFT (2U) +#define CRU_SOFTRST_CON13_PRESETN_PHP_NIU_MASK (0x1U << CRU_SOFTRST_CON13_PRESETN_PHP_NIU_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON13_HRESETN_SDMMC0_SHIFT (3U) +#define CRU_SOFTRST_CON13_HRESETN_SDMMC0_MASK (0x1U << CRU_SOFTRST_CON13_HRESETN_SDMMC0_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON13_RESETN_SDMMC0_SHIFT (4U) +#define CRU_SOFTRST_CON13_RESETN_SDMMC0_MASK (0x1U << CRU_SOFTRST_CON13_RESETN_SDMMC0_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON13_HRESETN_SDMMC1_SHIFT (5U) +#define CRU_SOFTRST_CON13_HRESETN_SDMMC1_MASK (0x1U << CRU_SOFTRST_CON13_HRESETN_SDMMC1_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON13_RESETN_SDMMC1_SHIFT (6U) +#define CRU_SOFTRST_CON13_RESETN_SDMMC1_MASK (0x1U << CRU_SOFTRST_CON13_RESETN_SDMMC1_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON13_ARESETN_GMAC0_SHIFT (7U) +#define CRU_SOFTRST_CON13_ARESETN_GMAC0_MASK (0x1U << CRU_SOFTRST_CON13_ARESETN_GMAC0_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON13_RESETN_GMAC0_TIMESTAMP_SHIFT (8U) +#define CRU_SOFTRST_CON13_RESETN_GMAC0_TIMESTAMP_MASK (0x1U << CRU_SOFTRST_CON13_RESETN_GMAC0_TIMESTAMP_SHIFT) /* 0x00000100 */ +/* SOFTRST_CON14 */ +#define CRU_SOFTRST_CON14_OFFSET (0x438U) +#define CRU_SOFTRST_CON14_ARESETN_USB_NIU_SHIFT (0U) +#define CRU_SOFTRST_CON14_ARESETN_USB_NIU_MASK (0x1U << CRU_SOFTRST_CON14_ARESETN_USB_NIU_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON14_HRESETN_USB_NIU_SHIFT (1U) +#define CRU_SOFTRST_CON14_HRESETN_USB_NIU_MASK (0x1U << CRU_SOFTRST_CON14_HRESETN_USB_NIU_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON14_PRESETN_USB_NIU_SHIFT (2U) +#define CRU_SOFTRST_CON14_PRESETN_USB_NIU_MASK (0x1U << CRU_SOFTRST_CON14_PRESETN_USB_NIU_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON14_PRESETN_USB_GRF_SHIFT (3U) +#define CRU_SOFTRST_CON14_PRESETN_USB_GRF_MASK (0x1U << CRU_SOFTRST_CON14_PRESETN_USB_GRF_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON14_HRESETN_USB2HOST0_SHIFT (4U) +#define CRU_SOFTRST_CON14_HRESETN_USB2HOST0_MASK (0x1U << CRU_SOFTRST_CON14_HRESETN_USB2HOST0_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON14_HRESETN_USB2HOST0_ARB_SHIFT (5U) +#define CRU_SOFTRST_CON14_HRESETN_USB2HOST0_ARB_MASK (0x1U << CRU_SOFTRST_CON14_HRESETN_USB2HOST0_ARB_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON14_RESETN_USB2HOST0_UTMI_SHIFT (6U) +#define CRU_SOFTRST_CON14_RESETN_USB2HOST0_UTMI_MASK (0x1U << CRU_SOFTRST_CON14_RESETN_USB2HOST0_UTMI_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON14_HRESETN_USB2HOST1_SHIFT (7U) +#define CRU_SOFTRST_CON14_HRESETN_USB2HOST1_MASK (0x1U << CRU_SOFTRST_CON14_HRESETN_USB2HOST1_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON14_HRESETN_USB2HOST1_ARB_SHIFT (8U) +#define CRU_SOFTRST_CON14_HRESETN_USB2HOST1_ARB_MASK (0x1U << CRU_SOFTRST_CON14_HRESETN_USB2HOST1_ARB_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON14_RESETN_USB2HOST1_UTMI_SHIFT (9U) +#define CRU_SOFTRST_CON14_RESETN_USB2HOST1_UTMI_MASK (0x1U << CRU_SOFTRST_CON14_RESETN_USB2HOST1_UTMI_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON14_HRESETN_SDMMC2_SHIFT (10U) +#define CRU_SOFTRST_CON14_HRESETN_SDMMC2_MASK (0x1U << CRU_SOFTRST_CON14_HRESETN_SDMMC2_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON14_RESETN_SDMMC2_SHIFT (11U) +#define CRU_SOFTRST_CON14_RESETN_SDMMC2_MASK (0x1U << CRU_SOFTRST_CON14_RESETN_SDMMC2_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON14_ARESETN_GMAC1_SHIFT (12U) +#define CRU_SOFTRST_CON14_ARESETN_GMAC1_MASK (0x1U << CRU_SOFTRST_CON14_ARESETN_GMAC1_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON14_RESETN_GMAC1_TIMESTAMP_SHIFT (13U) +#define CRU_SOFTRST_CON14_RESETN_GMAC1_TIMESTAMP_MASK (0x1U << CRU_SOFTRST_CON14_RESETN_GMAC1_TIMESTAMP_SHIFT) /* 0x00002000 */ +/* SOFTRST_CON15 */ +#define CRU_SOFTRST_CON15_OFFSET (0x43CU) +#define CRU_SOFTRST_CON15_ARESETN_VI_NIU_SHIFT (0U) +#define CRU_SOFTRST_CON15_ARESETN_VI_NIU_MASK (0x1U << CRU_SOFTRST_CON15_ARESETN_VI_NIU_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON15_HRESETN_VI_NIU_SHIFT (1U) +#define CRU_SOFTRST_CON15_HRESETN_VI_NIU_MASK (0x1U << CRU_SOFTRST_CON15_HRESETN_VI_NIU_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON15_PRESETN_VI_NIU_SHIFT (2U) +#define CRU_SOFTRST_CON15_PRESETN_VI_NIU_MASK (0x1U << CRU_SOFTRST_CON15_PRESETN_VI_NIU_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON15_ARESETN_VICAP1_SHIFT (7U) +#define CRU_SOFTRST_CON15_ARESETN_VICAP1_MASK (0x1U << CRU_SOFTRST_CON15_ARESETN_VICAP1_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON15_HRESETN_VICAP1_SHIFT (8U) +#define CRU_SOFTRST_CON15_HRESETN_VICAP1_MASK (0x1U << CRU_SOFTRST_CON15_HRESETN_VICAP1_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON15_DRESETN_VICAP1_SHIFT (9U) +#define CRU_SOFTRST_CON15_DRESETN_VICAP1_MASK (0x1U << CRU_SOFTRST_CON15_DRESETN_VICAP1_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON15_IRESETN_VICAP1_SHIFT (10U) +#define CRU_SOFTRST_CON15_IRESETN_VICAP1_MASK (0x1U << CRU_SOFTRST_CON15_IRESETN_VICAP1_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON15_PRESETN_VICAP1_SHIFT (11U) +#define CRU_SOFTRST_CON15_PRESETN_VICAP1_MASK (0x1U << CRU_SOFTRST_CON15_PRESETN_VICAP1_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON15_HRESETN_ISP_SHIFT (12U) +#define CRU_SOFTRST_CON15_HRESETN_ISP_MASK (0x1U << CRU_SOFTRST_CON15_HRESETN_ISP_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON15_RESETN_ISP_SHIFT (13U) +#define CRU_SOFTRST_CON15_RESETN_ISP_MASK (0x1U << CRU_SOFTRST_CON15_RESETN_ISP_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON15_PRESETN_CSI2HOST1_SHIFT (15U) +#define CRU_SOFTRST_CON15_PRESETN_CSI2HOST1_MASK (0x1U << CRU_SOFTRST_CON15_PRESETN_CSI2HOST1_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON16 */ +#define CRU_SOFTRST_CON16_OFFSET (0x440U) +#define CRU_SOFTRST_CON16_ARESETN_VO_NIU_SHIFT (0U) +#define CRU_SOFTRST_CON16_ARESETN_VO_NIU_MASK (0x1U << CRU_SOFTRST_CON16_ARESETN_VO_NIU_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON16_HRESETN_VO_NIU_SHIFT (1U) +#define CRU_SOFTRST_CON16_HRESETN_VO_NIU_MASK (0x1U << CRU_SOFTRST_CON16_HRESETN_VO_NIU_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON16_PRESETN_VO_NIU_SHIFT (2U) +#define CRU_SOFTRST_CON16_PRESETN_VO_NIU_MASK (0x1U << CRU_SOFTRST_CON16_PRESETN_VO_NIU_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON16_ARESETN_VOP_NIU_SHIFT (3U) +#define CRU_SOFTRST_CON16_ARESETN_VOP_NIU_MASK (0x1U << CRU_SOFTRST_CON16_ARESETN_VOP_NIU_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON16_ARESETN_VOP_SHIFT (4U) +#define CRU_SOFTRST_CON16_ARESETN_VOP_MASK (0x1U << CRU_SOFTRST_CON16_ARESETN_VOP_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON16_HRESETN_VOP_SHIFT (5U) +#define CRU_SOFTRST_CON16_HRESETN_VOP_MASK (0x1U << CRU_SOFTRST_CON16_HRESETN_VOP_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON16_DRESETN0_VOP_SHIFT (6U) +#define CRU_SOFTRST_CON16_DRESETN0_VOP_MASK (0x1U << CRU_SOFTRST_CON16_DRESETN0_VOP_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON16_DRESETN1_VOP_SHIFT (7U) +#define CRU_SOFTRST_CON16_DRESETN1_VOP_MASK (0x1U << CRU_SOFTRST_CON16_DRESETN1_VOP_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON16_DRESETN2_VOP_SHIFT (8U) +#define CRU_SOFTRST_CON16_DRESETN2_VOP_MASK (0x1U << CRU_SOFTRST_CON16_DRESETN2_VOP_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON16_RESETN_VOP_PWM_SHIFT (9U) +#define CRU_SOFTRST_CON16_RESETN_VOP_PWM_MASK (0x1U << CRU_SOFTRST_CON16_RESETN_VOP_PWM_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON16_ARESETN_HDCP_SHIFT (10U) +#define CRU_SOFTRST_CON16_ARESETN_HDCP_MASK (0x1U << CRU_SOFTRST_CON16_ARESETN_HDCP_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON16_HRESETN_HDCP_SHIFT (11U) +#define CRU_SOFTRST_CON16_HRESETN_HDCP_MASK (0x1U << CRU_SOFTRST_CON16_HRESETN_HDCP_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON16_PRESETN_HDCP_SHIFT (12U) +#define CRU_SOFTRST_CON16_PRESETN_HDCP_MASK (0x1U << CRU_SOFTRST_CON16_PRESETN_HDCP_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON16_PRESETN_HDMI_HOST_SHIFT (14U) +#define CRU_SOFTRST_CON16_PRESETN_HDMI_HOST_MASK (0x1U << CRU_SOFTRST_CON16_PRESETN_HDMI_HOST_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON16_RESETN_HDMI_HOST_SHIFT (15U) +#define CRU_SOFTRST_CON16_RESETN_HDMI_HOST_MASK (0x1U << CRU_SOFTRST_CON16_RESETN_HDMI_HOST_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON17 */ +#define CRU_SOFTRST_CON17_OFFSET (0x444U) +#define CRU_SOFTRST_CON17_PRESETN_DSITX_0_SHIFT (0U) +#define CRU_SOFTRST_CON17_PRESETN_DSITX_0_MASK (0x1U << CRU_SOFTRST_CON17_PRESETN_DSITX_0_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON17_PRESETN_DSITX_1_SHIFT (1U) +#define CRU_SOFTRST_CON17_PRESETN_DSITX_1_MASK (0x1U << CRU_SOFTRST_CON17_PRESETN_DSITX_1_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON17_PRESETN_EDP_CTRL_SHIFT (2U) +#define CRU_SOFTRST_CON17_PRESETN_EDP_CTRL_MASK (0x1U << CRU_SOFTRST_CON17_PRESETN_EDP_CTRL_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON17_RESETN_EDP_24M_SHIFT (3U) +#define CRU_SOFTRST_CON17_RESETN_EDP_24M_MASK (0x1U << CRU_SOFTRST_CON17_RESETN_EDP_24M_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON17_ARESETN_VPU_NIU_SHIFT (8U) +#define CRU_SOFTRST_CON17_ARESETN_VPU_NIU_MASK (0x1U << CRU_SOFTRST_CON17_ARESETN_VPU_NIU_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON17_HRESETN_VPU_NIU_SHIFT (9U) +#define CRU_SOFTRST_CON17_HRESETN_VPU_NIU_MASK (0x1U << CRU_SOFTRST_CON17_HRESETN_VPU_NIU_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON17_ARESETN_VPU_SHIFT (10U) +#define CRU_SOFTRST_CON17_ARESETN_VPU_MASK (0x1U << CRU_SOFTRST_CON17_ARESETN_VPU_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON17_HRESETN_VPU_SHIFT (11U) +#define CRU_SOFTRST_CON17_HRESETN_VPU_MASK (0x1U << CRU_SOFTRST_CON17_HRESETN_VPU_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON17_HRESETN_EINK_SHIFT (14U) +#define CRU_SOFTRST_CON17_HRESETN_EINK_MASK (0x1U << CRU_SOFTRST_CON17_HRESETN_EINK_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON17_PRESETN_EINK_SHIFT (15U) +#define CRU_SOFTRST_CON17_PRESETN_EINK_MASK (0x1U << CRU_SOFTRST_CON17_PRESETN_EINK_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON18 */ +#define CRU_SOFTRST_CON18_OFFSET (0x448U) +#define CRU_SOFTRST_CON18_ARESETN_RGA_NIU_SHIFT (0U) +#define CRU_SOFTRST_CON18_ARESETN_RGA_NIU_MASK (0x1U << CRU_SOFTRST_CON18_ARESETN_RGA_NIU_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON18_HRESETN_RGA_NIU_SHIFT (1U) +#define CRU_SOFTRST_CON18_HRESETN_RGA_NIU_MASK (0x1U << CRU_SOFTRST_CON18_HRESETN_RGA_NIU_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON18_PRESETN_RGA_NIU_SHIFT (2U) +#define CRU_SOFTRST_CON18_PRESETN_RGA_NIU_MASK (0x1U << CRU_SOFTRST_CON18_PRESETN_RGA_NIU_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON18_ARESETN_RGA_SHIFT (4U) +#define CRU_SOFTRST_CON18_ARESETN_RGA_MASK (0x1U << CRU_SOFTRST_CON18_ARESETN_RGA_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON18_HRESETN_RGA_SHIFT (5U) +#define CRU_SOFTRST_CON18_HRESETN_RGA_MASK (0x1U << CRU_SOFTRST_CON18_HRESETN_RGA_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON18_RESETN_RGA_CORE_SHIFT (6U) +#define CRU_SOFTRST_CON18_RESETN_RGA_CORE_MASK (0x1U << CRU_SOFTRST_CON18_RESETN_RGA_CORE_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON18_ARESETN_IEP_SHIFT (7U) +#define CRU_SOFTRST_CON18_ARESETN_IEP_MASK (0x1U << CRU_SOFTRST_CON18_ARESETN_IEP_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON18_HRESETN_IEP_SHIFT (8U) +#define CRU_SOFTRST_CON18_HRESETN_IEP_MASK (0x1U << CRU_SOFTRST_CON18_HRESETN_IEP_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON18_RESETN_IEP_CORE_SHIFT (9U) +#define CRU_SOFTRST_CON18_RESETN_IEP_CORE_MASK (0x1U << CRU_SOFTRST_CON18_RESETN_IEP_CORE_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON18_HRESETN_EBC_SHIFT (10U) +#define CRU_SOFTRST_CON18_HRESETN_EBC_MASK (0x1U << CRU_SOFTRST_CON18_HRESETN_EBC_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON18_DRESETN_EBC_SHIFT (11U) +#define CRU_SOFTRST_CON18_DRESETN_EBC_MASK (0x1U << CRU_SOFTRST_CON18_DRESETN_EBC_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON18_ARESETN_JDEC_SHIFT (12U) +#define CRU_SOFTRST_CON18_ARESETN_JDEC_MASK (0x1U << CRU_SOFTRST_CON18_ARESETN_JDEC_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON18_HRESETN_JDEC_SHIFT (13U) +#define CRU_SOFTRST_CON18_HRESETN_JDEC_MASK (0x1U << CRU_SOFTRST_CON18_HRESETN_JDEC_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON18_ARESETN_JENC_SHIFT (14U) +#define CRU_SOFTRST_CON18_ARESETN_JENC_MASK (0x1U << CRU_SOFTRST_CON18_ARESETN_JENC_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON18_HRESETN_JENC_SHIFT (15U) +#define CRU_SOFTRST_CON18_HRESETN_JENC_MASK (0x1U << CRU_SOFTRST_CON18_HRESETN_JENC_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON19 */ +#define CRU_SOFTRST_CON19_OFFSET (0x44CU) +#define CRU_SOFTRST_CON19_ARESETN_VENC_NIU_SHIFT (0U) +#define CRU_SOFTRST_CON19_ARESETN_VENC_NIU_MASK (0x1U << CRU_SOFTRST_CON19_ARESETN_VENC_NIU_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON19_HRESETN_VENC_NIU_SHIFT (1U) +#define CRU_SOFTRST_CON19_HRESETN_VENC_NIU_MASK (0x1U << CRU_SOFTRST_CON19_HRESETN_VENC_NIU_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON19_ARESETN_RKVENC_SHIFT (3U) +#define CRU_SOFTRST_CON19_ARESETN_RKVENC_MASK (0x1U << CRU_SOFTRST_CON19_ARESETN_RKVENC_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON19_HRESETN_RKVENC_SHIFT (4U) +#define CRU_SOFTRST_CON19_HRESETN_RKVENC_MASK (0x1U << CRU_SOFTRST_CON19_HRESETN_RKVENC_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON19_RESETN_RKVENC_CORE_SHIFT (5U) +#define CRU_SOFTRST_CON19_RESETN_RKVENC_CORE_MASK (0x1U << CRU_SOFTRST_CON19_RESETN_RKVENC_CORE_SHIFT) /* 0x00000020 */ +/* SOFTRST_CON20 */ +#define CRU_SOFTRST_CON20_OFFSET (0x450U) +#define CRU_SOFTRST_CON20_ARESETN_RKVDEC_NIU_SHIFT (0U) +#define CRU_SOFTRST_CON20_ARESETN_RKVDEC_NIU_MASK (0x1U << CRU_SOFTRST_CON20_ARESETN_RKVDEC_NIU_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON20_HRESETN_RKVDEC_NIU_SHIFT (1U) +#define CRU_SOFTRST_CON20_HRESETN_RKVDEC_NIU_MASK (0x1U << CRU_SOFTRST_CON20_HRESETN_RKVDEC_NIU_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON20_ARESETN_RKVDEC_SHIFT (2U) +#define CRU_SOFTRST_CON20_ARESETN_RKVDEC_MASK (0x1U << CRU_SOFTRST_CON20_ARESETN_RKVDEC_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON20_HRESETN_RKVDEC_SHIFT (3U) +#define CRU_SOFTRST_CON20_HRESETN_RKVDEC_MASK (0x1U << CRU_SOFTRST_CON20_HRESETN_RKVDEC_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON20_RESETN_RKVDEC_CA_SHIFT (4U) +#define CRU_SOFTRST_CON20_RESETN_RKVDEC_CA_MASK (0x1U << CRU_SOFTRST_CON20_RESETN_RKVDEC_CA_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON20_RESETN_RKVDEC_CORE_SHIFT (5U) +#define CRU_SOFTRST_CON20_RESETN_RKVDEC_CORE_MASK (0x1U << CRU_SOFTRST_CON20_RESETN_RKVDEC_CORE_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON20_RESETN_RKVDEC_HEVC_CA_SHIFT (6U) +#define CRU_SOFTRST_CON20_RESETN_RKVDEC_HEVC_CA_MASK (0x1U << CRU_SOFTRST_CON20_RESETN_RKVDEC_HEVC_CA_SHIFT) /* 0x00000040 */ +/* SOFTRST_CON21 */ +#define CRU_SOFTRST_CON21_OFFSET (0x454U) +#define CRU_SOFTRST_CON21_ARESETN_BUS_NIU_SHIFT (0U) +#define CRU_SOFTRST_CON21_ARESETN_BUS_NIU_MASK (0x1U << CRU_SOFTRST_CON21_ARESETN_BUS_NIU_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON21_PRESETN_BUS_NIU_SHIFT (2U) +#define CRU_SOFTRST_CON21_PRESETN_BUS_NIU_MASK (0x1U << CRU_SOFTRST_CON21_PRESETN_BUS_NIU_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON21_PRESETN_CAN0_SHIFT (4U) +#define CRU_SOFTRST_CON21_PRESETN_CAN0_MASK (0x1U << CRU_SOFTRST_CON21_PRESETN_CAN0_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON21_RESETN_CAN0_SHIFT (5U) +#define CRU_SOFTRST_CON21_RESETN_CAN0_MASK (0x1U << CRU_SOFTRST_CON21_RESETN_CAN0_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON21_PRESETN_CAN1_SHIFT (6U) +#define CRU_SOFTRST_CON21_PRESETN_CAN1_MASK (0x1U << CRU_SOFTRST_CON21_PRESETN_CAN1_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON21_RESETN_CAN1_SHIFT (7U) +#define CRU_SOFTRST_CON21_RESETN_CAN1_MASK (0x1U << CRU_SOFTRST_CON21_RESETN_CAN1_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON21_PRESETN_CAN2_SHIFT (8U) +#define CRU_SOFTRST_CON21_PRESETN_CAN2_MASK (0x1U << CRU_SOFTRST_CON21_PRESETN_CAN2_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON21_RESETN_CAN2_SHIFT (9U) +#define CRU_SOFTRST_CON21_RESETN_CAN2_MASK (0x1U << CRU_SOFTRST_CON21_RESETN_CAN2_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON21_PRESETN_GPIO1_SHIFT (10U) +#define CRU_SOFTRST_CON21_PRESETN_GPIO1_MASK (0x1U << CRU_SOFTRST_CON21_PRESETN_GPIO1_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON21_DBRESETN_GPIO1_SHIFT (11U) +#define CRU_SOFTRST_CON21_DBRESETN_GPIO1_MASK (0x1U << CRU_SOFTRST_CON21_DBRESETN_GPIO1_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON21_PRESETN_GPIO2_SHIFT (12U) +#define CRU_SOFTRST_CON21_PRESETN_GPIO2_MASK (0x1U << CRU_SOFTRST_CON21_PRESETN_GPIO2_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON21_DBRESETN_GPIO2_SHIFT (13U) +#define CRU_SOFTRST_CON21_DBRESETN_GPIO2_MASK (0x1U << CRU_SOFTRST_CON21_DBRESETN_GPIO2_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON21_PRESETN_GPIO3_SHIFT (14U) +#define CRU_SOFTRST_CON21_PRESETN_GPIO3_MASK (0x1U << CRU_SOFTRST_CON21_PRESETN_GPIO3_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON21_DBRESETN_GPIO3_SHIFT (15U) +#define CRU_SOFTRST_CON21_DBRESETN_GPIO3_MASK (0x1U << CRU_SOFTRST_CON21_DBRESETN_GPIO3_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON22 */ +#define CRU_SOFTRST_CON22_OFFSET (0x458U) +#define CRU_SOFTRST_CON22_PRESETN_GPIO4_SHIFT (0U) +#define CRU_SOFTRST_CON22_PRESETN_GPIO4_MASK (0x1U << CRU_SOFTRST_CON22_PRESETN_GPIO4_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON22_DBRESETN_GPIO4_SHIFT (1U) +#define CRU_SOFTRST_CON22_DBRESETN_GPIO4_MASK (0x1U << CRU_SOFTRST_CON22_DBRESETN_GPIO4_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON22_PRESETN_I2C1_SHIFT (2U) +#define CRU_SOFTRST_CON22_PRESETN_I2C1_MASK (0x1U << CRU_SOFTRST_CON22_PRESETN_I2C1_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON22_RESETN_I2C1_SHIFT (3U) +#define CRU_SOFTRST_CON22_RESETN_I2C1_MASK (0x1U << CRU_SOFTRST_CON22_RESETN_I2C1_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON22_PRESETN_I2C2_SHIFT (4U) +#define CRU_SOFTRST_CON22_PRESETN_I2C2_MASK (0x1U << CRU_SOFTRST_CON22_PRESETN_I2C2_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON22_RESETN_I2C2_SHIFT (5U) +#define CRU_SOFTRST_CON22_RESETN_I2C2_MASK (0x1U << CRU_SOFTRST_CON22_RESETN_I2C2_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON22_PRESETN_I2C3_SHIFT (6U) +#define CRU_SOFTRST_CON22_PRESETN_I2C3_MASK (0x1U << CRU_SOFTRST_CON22_PRESETN_I2C3_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON22_RESETN_I2C3_SHIFT (7U) +#define CRU_SOFTRST_CON22_RESETN_I2C3_MASK (0x1U << CRU_SOFTRST_CON22_RESETN_I2C3_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON22_PRESETN_I2C4_SHIFT (8U) +#define CRU_SOFTRST_CON22_PRESETN_I2C4_MASK (0x1U << CRU_SOFTRST_CON22_PRESETN_I2C4_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON22_RESETN_I2C4_SHIFT (9U) +#define CRU_SOFTRST_CON22_RESETN_I2C4_MASK (0x1U << CRU_SOFTRST_CON22_RESETN_I2C4_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON22_PRESETN_I2C5_SHIFT (10U) +#define CRU_SOFTRST_CON22_PRESETN_I2C5_MASK (0x1U << CRU_SOFTRST_CON22_PRESETN_I2C5_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON22_RESETN_I2C5_SHIFT (11U) +#define CRU_SOFTRST_CON22_RESETN_I2C5_MASK (0x1U << CRU_SOFTRST_CON22_RESETN_I2C5_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON22_PRESETN_OTPC_NS_SHIFT (12U) +#define CRU_SOFTRST_CON22_PRESETN_OTPC_NS_MASK (0x1U << CRU_SOFTRST_CON22_PRESETN_OTPC_NS_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON22_RESETN_OTPC_NS_SBPI_SHIFT (13U) +#define CRU_SOFTRST_CON22_RESETN_OTPC_NS_SBPI_MASK (0x1U << CRU_SOFTRST_CON22_RESETN_OTPC_NS_SBPI_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON22_RESETN_OTPC_NS_USR_SHIFT (14U) +#define CRU_SOFTRST_CON22_RESETN_OTPC_NS_USR_MASK (0x1U << CRU_SOFTRST_CON22_RESETN_OTPC_NS_USR_SHIFT) /* 0x00004000 */ +/* SOFTRST_CON23 */ +#define CRU_SOFTRST_CON23_OFFSET (0x45CU) +#define CRU_SOFTRST_CON23_PRESETN_PWM1_SHIFT (0U) +#define CRU_SOFTRST_CON23_PRESETN_PWM1_MASK (0x1U << CRU_SOFTRST_CON23_PRESETN_PWM1_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON23_RESETN_PWM1_SHIFT (1U) +#define CRU_SOFTRST_CON23_RESETN_PWM1_MASK (0x1U << CRU_SOFTRST_CON23_RESETN_PWM1_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON23_PRESETN_PWM2_SHIFT (2U) +#define CRU_SOFTRST_CON23_PRESETN_PWM2_MASK (0x1U << CRU_SOFTRST_CON23_PRESETN_PWM2_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON23_RESETN_PWM2_SHIFT (3U) +#define CRU_SOFTRST_CON23_RESETN_PWM2_MASK (0x1U << CRU_SOFTRST_CON23_RESETN_PWM2_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON23_PRESETN_PWM3_SHIFT (4U) +#define CRU_SOFTRST_CON23_PRESETN_PWM3_MASK (0x1U << CRU_SOFTRST_CON23_PRESETN_PWM3_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON23_RESETN_PWM3_SHIFT (5U) +#define CRU_SOFTRST_CON23_RESETN_PWM3_MASK (0x1U << CRU_SOFTRST_CON23_RESETN_PWM3_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON23_PRESETN_SPI0_SHIFT (6U) +#define CRU_SOFTRST_CON23_PRESETN_SPI0_MASK (0x1U << CRU_SOFTRST_CON23_PRESETN_SPI0_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON23_RESETN_SPI0_SHIFT (7U) +#define CRU_SOFTRST_CON23_RESETN_SPI0_MASK (0x1U << CRU_SOFTRST_CON23_RESETN_SPI0_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON23_PRESETN_SPI1_SHIFT (8U) +#define CRU_SOFTRST_CON23_PRESETN_SPI1_MASK (0x1U << CRU_SOFTRST_CON23_PRESETN_SPI1_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON23_RESETN_SPI1_SHIFT (9U) +#define CRU_SOFTRST_CON23_RESETN_SPI1_MASK (0x1U << CRU_SOFTRST_CON23_RESETN_SPI1_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON23_PRESETN_SPI2_SHIFT (10U) +#define CRU_SOFTRST_CON23_PRESETN_SPI2_MASK (0x1U << CRU_SOFTRST_CON23_PRESETN_SPI2_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON23_RESETN_SPI2_SHIFT (11U) +#define CRU_SOFTRST_CON23_RESETN_SPI2_MASK (0x1U << CRU_SOFTRST_CON23_RESETN_SPI2_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON23_PRESETN_SPI3_SHIFT (12U) +#define CRU_SOFTRST_CON23_PRESETN_SPI3_MASK (0x1U << CRU_SOFTRST_CON23_PRESETN_SPI3_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON23_RESETN_SPI3_SHIFT (13U) +#define CRU_SOFTRST_CON23_RESETN_SPI3_MASK (0x1U << CRU_SOFTRST_CON23_RESETN_SPI3_SHIFT) /* 0x00002000 */ +/* SOFTRST_CON24 */ +#define CRU_SOFTRST_CON24_OFFSET (0x460U) +#define CRU_SOFTRST_CON24_PRESETN_SARADC_SHIFT (0U) +#define CRU_SOFTRST_CON24_PRESETN_SARADC_MASK (0x1U << CRU_SOFTRST_CON24_PRESETN_SARADC_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON24_PRESETN_TSADC_SHIFT (1U) +#define CRU_SOFTRST_CON24_PRESETN_TSADC_MASK (0x1U << CRU_SOFTRST_CON24_PRESETN_TSADC_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON24_RESETN_TSADC_SHIFT (2U) +#define CRU_SOFTRST_CON24_RESETN_TSADC_MASK (0x1U << CRU_SOFTRST_CON24_RESETN_TSADC_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON24_PRESETN_TIMER_SHIFT (3U) +#define CRU_SOFTRST_CON24_PRESETN_TIMER_MASK (0x1U << CRU_SOFTRST_CON24_PRESETN_TIMER_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON24_RESETN_TIMER0_SHIFT (4U) +#define CRU_SOFTRST_CON24_RESETN_TIMER0_MASK (0x1U << CRU_SOFTRST_CON24_RESETN_TIMER0_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON24_RESETN_TIMER1_SHIFT (5U) +#define CRU_SOFTRST_CON24_RESETN_TIMER1_MASK (0x1U << CRU_SOFTRST_CON24_RESETN_TIMER1_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON24_RESETN_TIMER2_SHIFT (6U) +#define CRU_SOFTRST_CON24_RESETN_TIMER2_MASK (0x1U << CRU_SOFTRST_CON24_RESETN_TIMER2_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON24_RESETN_TIMER3_SHIFT (7U) +#define CRU_SOFTRST_CON24_RESETN_TIMER3_MASK (0x1U << CRU_SOFTRST_CON24_RESETN_TIMER3_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON24_RESETN_TIMER4_SHIFT (8U) +#define CRU_SOFTRST_CON24_RESETN_TIMER4_MASK (0x1U << CRU_SOFTRST_CON24_RESETN_TIMER4_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON24_RESETN_TIMER5_SHIFT (9U) +#define CRU_SOFTRST_CON24_RESETN_TIMER5_MASK (0x1U << CRU_SOFTRST_CON24_RESETN_TIMER5_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON24_PRESETN_UART1_SHIFT (10U) +#define CRU_SOFTRST_CON24_PRESETN_UART1_MASK (0x1U << CRU_SOFTRST_CON24_PRESETN_UART1_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON24_SRESETN_UART1_SHIFT (11U) +#define CRU_SOFTRST_CON24_SRESETN_UART1_MASK (0x1U << CRU_SOFTRST_CON24_SRESETN_UART1_SHIFT) /* 0x00000800 */ +/* SOFTRST_CON25 */ +#define CRU_SOFTRST_CON25_OFFSET (0x464U) +#define CRU_SOFTRST_CON25_PRESETN_UART2_SHIFT (0U) +#define CRU_SOFTRST_CON25_PRESETN_UART2_MASK (0x1U << CRU_SOFTRST_CON25_PRESETN_UART2_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON25_SRESETN_UART2_SHIFT (1U) +#define CRU_SOFTRST_CON25_SRESETN_UART2_MASK (0x1U << CRU_SOFTRST_CON25_SRESETN_UART2_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON25_PRESETN_UART3_SHIFT (2U) +#define CRU_SOFTRST_CON25_PRESETN_UART3_MASK (0x1U << CRU_SOFTRST_CON25_PRESETN_UART3_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON25_SRESETN_UART3_SHIFT (3U) +#define CRU_SOFTRST_CON25_SRESETN_UART3_MASK (0x1U << CRU_SOFTRST_CON25_SRESETN_UART3_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON25_PRESETN_UART4_SHIFT (4U) +#define CRU_SOFTRST_CON25_PRESETN_UART4_MASK (0x1U << CRU_SOFTRST_CON25_PRESETN_UART4_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON25_SRESETN_UART4_SHIFT (5U) +#define CRU_SOFTRST_CON25_SRESETN_UART4_MASK (0x1U << CRU_SOFTRST_CON25_SRESETN_UART4_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON25_PRESETN_UART5_SHIFT (6U) +#define CRU_SOFTRST_CON25_PRESETN_UART5_MASK (0x1U << CRU_SOFTRST_CON25_PRESETN_UART5_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON25_SRESETN_UART5_SHIFT (7U) +#define CRU_SOFTRST_CON25_SRESETN_UART5_MASK (0x1U << CRU_SOFTRST_CON25_SRESETN_UART5_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON25_PRESETN_UART6_SHIFT (8U) +#define CRU_SOFTRST_CON25_PRESETN_UART6_MASK (0x1U << CRU_SOFTRST_CON25_PRESETN_UART6_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON25_SRESETN_UART6_SHIFT (9U) +#define CRU_SOFTRST_CON25_SRESETN_UART6_MASK (0x1U << CRU_SOFTRST_CON25_SRESETN_UART6_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON25_PRESETN_UART7_SHIFT (10U) +#define CRU_SOFTRST_CON25_PRESETN_UART7_MASK (0x1U << CRU_SOFTRST_CON25_PRESETN_UART7_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON25_SRESETN_UART7_SHIFT (11U) +#define CRU_SOFTRST_CON25_SRESETN_UART7_MASK (0x1U << CRU_SOFTRST_CON25_SRESETN_UART7_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON25_PRESETN_UART8_SHIFT (12U) +#define CRU_SOFTRST_CON25_PRESETN_UART8_MASK (0x1U << CRU_SOFTRST_CON25_PRESETN_UART8_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON25_SRESETN_UART8_SHIFT (13U) +#define CRU_SOFTRST_CON25_SRESETN_UART8_MASK (0x1U << CRU_SOFTRST_CON25_SRESETN_UART8_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON25_PRESETN_UART9_SHIFT (14U) +#define CRU_SOFTRST_CON25_PRESETN_UART9_MASK (0x1U << CRU_SOFTRST_CON25_PRESETN_UART9_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON25_SRESETN_UART9_SHIFT (15U) +#define CRU_SOFTRST_CON25_SRESETN_UART9_MASK (0x1U << CRU_SOFTRST_CON25_SRESETN_UART9_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON26 */ +#define CRU_SOFTRST_CON26_OFFSET (0x468U) +#define CRU_SOFTRST_CON26_PRESETN_GRF_SHIFT (0U) +#define CRU_SOFTRST_CON26_PRESETN_GRF_MASK (0x1U << CRU_SOFTRST_CON26_PRESETN_GRF_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON26_PRESETN_GRF_VCCIO12_SHIFT (1U) +#define CRU_SOFTRST_CON26_PRESETN_GRF_VCCIO12_MASK (0x1U << CRU_SOFTRST_CON26_PRESETN_GRF_VCCIO12_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON26_PRESETN_GRF_VCCIO34_SHIFT (2U) +#define CRU_SOFTRST_CON26_PRESETN_GRF_VCCIO34_MASK (0x1U << CRU_SOFTRST_CON26_PRESETN_GRF_VCCIO34_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON26_PRESETN_GRF_VCCIO567_SHIFT (3U) +#define CRU_SOFTRST_CON26_PRESETN_GRF_VCCIO567_MASK (0x1U << CRU_SOFTRST_CON26_PRESETN_GRF_VCCIO567_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON26_PRESETN_SCR_SHIFT (4U) +#define CRU_SOFTRST_CON26_PRESETN_SCR_MASK (0x1U << CRU_SOFTRST_CON26_PRESETN_SCR_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON26_PRESETN_WDT_NS_SHIFT (5U) +#define CRU_SOFTRST_CON26_PRESETN_WDT_NS_MASK (0x1U << CRU_SOFTRST_CON26_PRESETN_WDT_NS_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON26_TRESETN_WDT_NS_SHIFT (6U) +#define CRU_SOFTRST_CON26_TRESETN_WDT_NS_MASK (0x1U << CRU_SOFTRST_CON26_TRESETN_WDT_NS_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON26_PRESETN_DFT2APB_SHIFT (7U) +#define CRU_SOFTRST_CON26_PRESETN_DFT2APB_MASK (0x1U << CRU_SOFTRST_CON26_PRESETN_DFT2APB_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON26_ARESETN_MCU_SHIFT (10U) +#define CRU_SOFTRST_CON26_ARESETN_MCU_MASK (0x1U << CRU_SOFTRST_CON26_ARESETN_MCU_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON26_PRESETN_INTMUX_SHIFT (11U) +#define CRU_SOFTRST_CON26_PRESETN_INTMUX_MASK (0x1U << CRU_SOFTRST_CON26_PRESETN_INTMUX_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON26_PRESETN_MAILBOX_SHIFT (12U) +#define CRU_SOFTRST_CON26_PRESETN_MAILBOX_MASK (0x1U << CRU_SOFTRST_CON26_PRESETN_MAILBOX_SHIFT) /* 0x00001000 */ +/* SOFTRST_CON27 */ +#define CRU_SOFTRST_CON27_OFFSET (0x46CU) +#define CRU_SOFTRST_CON27_ARESETN_TOP_HIGH_NIU_SHIFT (0U) +#define CRU_SOFTRST_CON27_ARESETN_TOP_HIGH_NIU_MASK (0x1U << CRU_SOFTRST_CON27_ARESETN_TOP_HIGH_NIU_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON27_ARESETN_TOP_LOW_NIU_SHIFT (1U) +#define CRU_SOFTRST_CON27_ARESETN_TOP_LOW_NIU_MASK (0x1U << CRU_SOFTRST_CON27_ARESETN_TOP_LOW_NIU_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON27_HRESETN_TOP_NIU_SHIFT (2U) +#define CRU_SOFTRST_CON27_HRESETN_TOP_NIU_MASK (0x1U << CRU_SOFTRST_CON27_HRESETN_TOP_NIU_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON27_PRESETN_TOP_NIU_SHIFT (3U) +#define CRU_SOFTRST_CON27_PRESETN_TOP_NIU_MASK (0x1U << CRU_SOFTRST_CON27_PRESETN_TOP_NIU_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON27_PRESETN_TOP_CRU_SHIFT (6U) +#define CRU_SOFTRST_CON27_PRESETN_TOP_CRU_MASK (0x1U << CRU_SOFTRST_CON27_PRESETN_TOP_CRU_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON27_PRESETN_DDRPHY_SHIFT (7U) +#define CRU_SOFTRST_CON27_PRESETN_DDRPHY_MASK (0x1U << CRU_SOFTRST_CON27_PRESETN_DDRPHY_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON27_RESETN_DDRPHY_SHIFT (8U) +#define CRU_SOFTRST_CON27_RESETN_DDRPHY_MASK (0x1U << CRU_SOFTRST_CON27_RESETN_DDRPHY_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON27_PRESETN_MIPICSIPHY_SHIFT (10U) +#define CRU_SOFTRST_CON27_PRESETN_MIPICSIPHY_MASK (0x1U << CRU_SOFTRST_CON27_PRESETN_MIPICSIPHY_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON27_PRESETN_MIPIDSIPHY0_SHIFT (11U) +#define CRU_SOFTRST_CON27_PRESETN_MIPIDSIPHY0_MASK (0x1U << CRU_SOFTRST_CON27_PRESETN_MIPIDSIPHY0_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON27_PRESETN_MIPIDSIPHY1_SHIFT (12U) +#define CRU_SOFTRST_CON27_PRESETN_MIPIDSIPHY1_MASK (0x1U << CRU_SOFTRST_CON27_PRESETN_MIPIDSIPHY1_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON27_PRESETN_PCIE30PHY_SHIFT (13U) +#define CRU_SOFTRST_CON27_PRESETN_PCIE30PHY_MASK (0x1U << CRU_SOFTRST_CON27_PRESETN_PCIE30PHY_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON27_RESETN_PCIE30PHY_SHIFT (14U) +#define CRU_SOFTRST_CON27_RESETN_PCIE30PHY_MASK (0x1U << CRU_SOFTRST_CON27_RESETN_PCIE30PHY_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON27_PRESETN_PCIE30PHY_GRF_SHIFT (15U) +#define CRU_SOFTRST_CON27_PRESETN_PCIE30PHY_GRF_MASK (0x1U << CRU_SOFTRST_CON27_PRESETN_PCIE30PHY_GRF_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON28 */ +#define CRU_SOFTRST_CON28_OFFSET (0x470U) +#define CRU_SOFTRST_CON28_PRESETN_APB2ASB_CHIP_LEFT_SHIFT (0U) +#define CRU_SOFTRST_CON28_PRESETN_APB2ASB_CHIP_LEFT_MASK (0x1U << CRU_SOFTRST_CON28_PRESETN_APB2ASB_CHIP_LEFT_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON28_PRESETN_APB2ASB_CHIP_BOTTOM_SHIFT (1U) +#define CRU_SOFTRST_CON28_PRESETN_APB2ASB_CHIP_BOTTOM_MASK (0x1U << CRU_SOFTRST_CON28_PRESETN_APB2ASB_CHIP_BOTTOM_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON28_PRESETN_ASB2APB_CHIP_LEFT_SHIFT (2U) +#define CRU_SOFTRST_CON28_PRESETN_ASB2APB_CHIP_LEFT_MASK (0x1U << CRU_SOFTRST_CON28_PRESETN_ASB2APB_CHIP_LEFT_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON28_PRESETN_ASB2APB_CHIP_BOTTOM_SHIFT (3U) +#define CRU_SOFTRST_CON28_PRESETN_ASB2APB_CHIP_BOTTOM_MASK (0x1U << CRU_SOFTRST_CON28_PRESETN_ASB2APB_CHIP_BOTTOM_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON28_PRESETN_PIPEPHY0_SHIFT (4U) +#define CRU_SOFTRST_CON28_PRESETN_PIPEPHY0_MASK (0x1U << CRU_SOFTRST_CON28_PRESETN_PIPEPHY0_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON28_RESETN_PIPEPHY0_SHIFT (5U) +#define CRU_SOFTRST_CON28_RESETN_PIPEPHY0_MASK (0x1U << CRU_SOFTRST_CON28_RESETN_PIPEPHY0_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON28_PRESETN_PIPEPHY1_SHIFT (6U) +#define CRU_SOFTRST_CON28_PRESETN_PIPEPHY1_MASK (0x1U << CRU_SOFTRST_CON28_PRESETN_PIPEPHY1_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON28_RESETN_PIPEPHY1_SHIFT (7U) +#define CRU_SOFTRST_CON28_RESETN_PIPEPHY1_MASK (0x1U << CRU_SOFTRST_CON28_RESETN_PIPEPHY1_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON28_PRESETN_PIPEPHY2_SHIFT (8U) +#define CRU_SOFTRST_CON28_PRESETN_PIPEPHY2_MASK (0x1U << CRU_SOFTRST_CON28_PRESETN_PIPEPHY2_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON28_RESETN_PIPEPHY2_SHIFT (9U) +#define CRU_SOFTRST_CON28_RESETN_PIPEPHY2_MASK (0x1U << CRU_SOFTRST_CON28_RESETN_PIPEPHY2_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON28_PRESETN_USB2PHY0_GRF_SHIFT (10U) +#define CRU_SOFTRST_CON28_PRESETN_USB2PHY0_GRF_MASK (0x1U << CRU_SOFTRST_CON28_PRESETN_USB2PHY0_GRF_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON28_PRESETN_USB2PHY1_GRF_SHIFT (11U) +#define CRU_SOFTRST_CON28_PRESETN_USB2PHY1_GRF_MASK (0x1U << CRU_SOFTRST_CON28_PRESETN_USB2PHY1_GRF_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON28_PRESETN_CPU_BOOST_SHIFT (12U) +#define CRU_SOFTRST_CON28_PRESETN_CPU_BOOST_MASK (0x1U << CRU_SOFTRST_CON28_PRESETN_CPU_BOOST_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON28_RESETN_CPU_BOOST_SHIFT (13U) +#define CRU_SOFTRST_CON28_RESETN_CPU_BOOST_MASK (0x1U << CRU_SOFTRST_CON28_RESETN_CPU_BOOST_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON28_PRESETN_OTPPHY_SHIFT (14U) +#define CRU_SOFTRST_CON28_PRESETN_OTPPHY_MASK (0x1U << CRU_SOFTRST_CON28_PRESETN_OTPPHY_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON28_RESETN_OTPPHY_SHIFT (15U) +#define CRU_SOFTRST_CON28_RESETN_OTPPHY_MASK (0x1U << CRU_SOFTRST_CON28_RESETN_OTPPHY_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON29 */ +#define CRU_SOFTRST_CON29_OFFSET (0x474U) +#define CRU_SOFTRST_CON29_RESETN_USB2PHY0_POR_SHIFT (0U) +#define CRU_SOFTRST_CON29_RESETN_USB2PHY0_POR_MASK (0x1U << CRU_SOFTRST_CON29_RESETN_USB2PHY0_POR_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON29_RESETN_USB2PHY0_USB3OTG0_SHIFT (1U) +#define CRU_SOFTRST_CON29_RESETN_USB2PHY0_USB3OTG0_MASK (0x1U << CRU_SOFTRST_CON29_RESETN_USB2PHY0_USB3OTG0_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON29_RESETN_USB2PHY0_USB3OTG1_SHIFT (2U) +#define CRU_SOFTRST_CON29_RESETN_USB2PHY0_USB3OTG1_MASK (0x1U << CRU_SOFTRST_CON29_RESETN_USB2PHY0_USB3OTG1_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON29_RESETN_USB2PHY1_POR_SHIFT (3U) +#define CRU_SOFTRST_CON29_RESETN_USB2PHY1_POR_MASK (0x1U << CRU_SOFTRST_CON29_RESETN_USB2PHY1_POR_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON29_RESETN_USB2PHY1_USB2HOST0_SHIFT (4U) +#define CRU_SOFTRST_CON29_RESETN_USB2PHY1_USB2HOST0_MASK (0x1U << CRU_SOFTRST_CON29_RESETN_USB2PHY1_USB2HOST0_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON29_RESETN_USB2PHY1_USB2HOST1_SHIFT (5U) +#define CRU_SOFTRST_CON29_RESETN_USB2PHY1_USB2HOST1_MASK (0x1U << CRU_SOFTRST_CON29_RESETN_USB2PHY1_USB2HOST1_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON29_PRESETN_EDPPHY_GRF_SHIFT (6U) +#define CRU_SOFTRST_CON29_PRESETN_EDPPHY_GRF_MASK (0x1U << CRU_SOFTRST_CON29_PRESETN_EDPPHY_GRF_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON29_RESETN_TSADCPHY_SHIFT (7U) +#define CRU_SOFTRST_CON29_RESETN_TSADCPHY_MASK (0x1U << CRU_SOFTRST_CON29_RESETN_TSADCPHY_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON29_RESETN_GMAC0_DELAYLINE_SHIFT (8U) +#define CRU_SOFTRST_CON29_RESETN_GMAC0_DELAYLINE_MASK (0x1U << CRU_SOFTRST_CON29_RESETN_GMAC0_DELAYLINE_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON29_RESETN_GMAC1_DELAYLINE_SHIFT (9U) +#define CRU_SOFTRST_CON29_RESETN_GMAC1_DELAYLINE_MASK (0x1U << CRU_SOFTRST_CON29_RESETN_GMAC1_DELAYLINE_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON29_RESETN_OTPC_ARB_SHIFT (10U) +#define CRU_SOFTRST_CON29_RESETN_OTPC_ARB_MASK (0x1U << CRU_SOFTRST_CON29_RESETN_OTPC_ARB_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON29_PRESETN_PIPEPHY0_GRF_SHIFT (11U) +#define CRU_SOFTRST_CON29_PRESETN_PIPEPHY0_GRF_MASK (0x1U << CRU_SOFTRST_CON29_PRESETN_PIPEPHY0_GRF_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON29_PRESETN_PIPEPHY1_GRF_SHIFT (12U) +#define CRU_SOFTRST_CON29_PRESETN_PIPEPHY1_GRF_MASK (0x1U << CRU_SOFTRST_CON29_PRESETN_PIPEPHY1_GRF_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON29_PRESETN_PIPEPHY2_GRF_SHIFT (13U) +#define CRU_SOFTRST_CON29_PRESETN_PIPEPHY2_GRF_MASK (0x1U << CRU_SOFTRST_CON29_PRESETN_PIPEPHY2_GRF_SHIFT) /* 0x00002000 */ +/* SSGTBL0_3 */ +#define CRU_SSGTBL0_3_OFFSET (0x480U) +#define CRU_SSGTBL0_3_SSGTBL0_3_SHIFT (0U) +#define CRU_SSGTBL0_3_SSGTBL0_3_MASK (0xFFFFFFFFU << CRU_SSGTBL0_3_SSGTBL0_3_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL4_7 */ +#define CRU_SSGTBL4_7_OFFSET (0x484U) +#define CRU_SSGTBL4_7_SSGTBL4_7_SHIFT (0U) +#define CRU_SSGTBL4_7_SSGTBL4_7_MASK (0xFFFFFFFFU << CRU_SSGTBL4_7_SSGTBL4_7_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL8_11 */ +#define CRU_SSGTBL8_11_OFFSET (0x488U) +#define CRU_SSGTBL8_11_SSGTBL8_11_SHIFT (0U) +#define CRU_SSGTBL8_11_SSGTBL8_11_MASK (0xFFFFFFFFU << CRU_SSGTBL8_11_SSGTBL8_11_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL12_15 */ +#define CRU_SSGTBL12_15_OFFSET (0x48CU) +#define CRU_SSGTBL12_15_SSGTBL12_15_SHIFT (0U) +#define CRU_SSGTBL12_15_SSGTBL12_15_MASK (0xFFFFFFFFU << CRU_SSGTBL12_15_SSGTBL12_15_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL16_19 */ +#define CRU_SSGTBL16_19_OFFSET (0x490U) +#define CRU_SSGTBL16_19_SSGTBL16_19_SHIFT (0U) +#define CRU_SSGTBL16_19_SSGTBL16_19_MASK (0xFFFFFFFFU << CRU_SSGTBL16_19_SSGTBL16_19_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL20_23 */ +#define CRU_SSGTBL20_23_OFFSET (0x494U) +#define CRU_SSGTBL20_23_SSGTBL20_23_SHIFT (0U) +#define CRU_SSGTBL20_23_SSGTBL20_23_MASK (0xFFFFFFFFU << CRU_SSGTBL20_23_SSGTBL20_23_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL24_27 */ +#define CRU_SSGTBL24_27_OFFSET (0x498U) +#define CRU_SSGTBL24_27_SSGTBL24_27_SHIFT (0U) +#define CRU_SSGTBL24_27_SSGTBL24_27_MASK (0xFFFFFFFFU << CRU_SSGTBL24_27_SSGTBL24_27_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL28_31 */ +#define CRU_SSGTBL28_31_OFFSET (0x49CU) +#define CRU_SSGTBL28_31_SSGTBL28_31_SHIFT (0U) +#define CRU_SSGTBL28_31_SSGTBL28_31_MASK (0xFFFFFFFFU << CRU_SSGTBL28_31_SSGTBL28_31_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL32_35 */ +#define CRU_SSGTBL32_35_OFFSET (0x4A0U) +#define CRU_SSGTBL32_35_SSGTBL32_35_SHIFT (0U) +#define CRU_SSGTBL32_35_SSGTBL32_35_MASK (0xFFFFFFFFU << CRU_SSGTBL32_35_SSGTBL32_35_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL36_39 */ +#define CRU_SSGTBL36_39_OFFSET (0x4A4U) +#define CRU_SSGTBL36_39_SSGTBL36_39_SHIFT (0U) +#define CRU_SSGTBL36_39_SSGTBL36_39_MASK (0xFFFFFFFFU << CRU_SSGTBL36_39_SSGTBL36_39_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL40_43 */ +#define CRU_SSGTBL40_43_OFFSET (0x4A8U) +#define CRU_SSGTBL40_43_SSGTBL40_43_SHIFT (0U) +#define CRU_SSGTBL40_43_SSGTBL40_43_MASK (0xFFFFFFFFU << CRU_SSGTBL40_43_SSGTBL40_43_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL44_47 */ +#define CRU_SSGTBL44_47_OFFSET (0x4ACU) +#define CRU_SSGTBL44_47_SSGTBL44_47_SHIFT (0U) +#define CRU_SSGTBL44_47_SSGTBL44_47_MASK (0xFFFFFFFFU << CRU_SSGTBL44_47_SSGTBL44_47_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL48_51 */ +#define CRU_SSGTBL48_51_OFFSET (0x4B0U) +#define CRU_SSGTBL48_51_SSGTBL48_51_SHIFT (0U) +#define CRU_SSGTBL48_51_SSGTBL48_51_MASK (0xFFFFFFFFU << CRU_SSGTBL48_51_SSGTBL48_51_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL52_55 */ +#define CRU_SSGTBL52_55_OFFSET (0x4B4U) +#define CRU_SSGTBL52_55_SSGTBL52_55_SHIFT (0U) +#define CRU_SSGTBL52_55_SSGTBL52_55_MASK (0xFFFFFFFFU << CRU_SSGTBL52_55_SSGTBL52_55_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL56_59 */ +#define CRU_SSGTBL56_59_OFFSET (0x4B8U) +#define CRU_SSGTBL56_59_SSGTBL56_59_SHIFT (0U) +#define CRU_SSGTBL56_59_SSGTBL56_59_MASK (0xFFFFFFFFU << CRU_SSGTBL56_59_SSGTBL56_59_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL60_63 */ +#define CRU_SSGTBL60_63_OFFSET (0x4BCU) +#define CRU_SSGTBL60_63_SSGTBL60_63_SHIFT (0U) +#define CRU_SSGTBL60_63_SSGTBL60_63_MASK (0xFFFFFFFFU << CRU_SSGTBL60_63_SSGTBL60_63_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL64_67 */ +#define CRU_SSGTBL64_67_OFFSET (0x4C0U) +#define CRU_SSGTBL64_67_SSGTBL64_67_SHIFT (0U) +#define CRU_SSGTBL64_67_SSGTBL64_67_MASK (0xFFFFFFFFU << CRU_SSGTBL64_67_SSGTBL64_67_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL68_71 */ +#define CRU_SSGTBL68_71_OFFSET (0x4C4U) +#define CRU_SSGTBL68_71_SSGTBL68_71_SHIFT (0U) +#define CRU_SSGTBL68_71_SSGTBL68_71_MASK (0xFFFFFFFFU << CRU_SSGTBL68_71_SSGTBL68_71_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL72_75 */ +#define CRU_SSGTBL72_75_OFFSET (0x4C8U) +#define CRU_SSGTBL72_75_SSGTBL72_75_SHIFT (0U) +#define CRU_SSGTBL72_75_SSGTBL72_75_MASK (0xFFFFFFFFU << CRU_SSGTBL72_75_SSGTBL72_75_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL76_79 */ +#define CRU_SSGTBL76_79_OFFSET (0x4CCU) +#define CRU_SSGTBL76_79_SSGTBL76_79_SHIFT (0U) +#define CRU_SSGTBL76_79_SSGTBL76_79_MASK (0xFFFFFFFFU << CRU_SSGTBL76_79_SSGTBL76_79_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL80_83 */ +#define CRU_SSGTBL80_83_OFFSET (0x4D0U) +#define CRU_SSGTBL80_83_SSGTBL80_83_SHIFT (0U) +#define CRU_SSGTBL80_83_SSGTBL80_83_MASK (0xFFFFFFFFU << CRU_SSGTBL80_83_SSGTBL80_83_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL84_87 */ +#define CRU_SSGTBL84_87_OFFSET (0x4D4U) +#define CRU_SSGTBL84_87_SSGTBL84_87_SHIFT (0U) +#define CRU_SSGTBL84_87_SSGTBL84_87_MASK (0xFFFFFFFFU << CRU_SSGTBL84_87_SSGTBL84_87_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL88_91 */ +#define CRU_SSGTBL88_91_OFFSET (0x4D8U) +#define CRU_SSGTBL88_91_SSGTBL88_91_SHIFT (0U) +#define CRU_SSGTBL88_91_SSGTBL88_91_MASK (0xFFFFFFFFU << CRU_SSGTBL88_91_SSGTBL88_91_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL92_95 */ +#define CRU_SSGTBL92_95_OFFSET (0x4DCU) +#define CRU_SSGTBL92_95_SSGTBL92_95_SHIFT (0U) +#define CRU_SSGTBL92_95_SSGTBL92_95_MASK (0xFFFFFFFFU << CRU_SSGTBL92_95_SSGTBL92_95_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL96_99 */ +#define CRU_SSGTBL96_99_OFFSET (0x4E0U) +#define CRU_SSGTBL96_99_SSGTBL96_99_SHIFT (0U) +#define CRU_SSGTBL96_99_SSGTBL96_99_MASK (0xFFFFFFFFU << CRU_SSGTBL96_99_SSGTBL96_99_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL100_103 */ +#define CRU_SSGTBL100_103_OFFSET (0x4E4U) +#define CRU_SSGTBL100_103_SSGTBL100_103_SHIFT (0U) +#define CRU_SSGTBL100_103_SSGTBL100_103_MASK (0xFFFFFFFFU << CRU_SSGTBL100_103_SSGTBL100_103_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL104_107 */ +#define CRU_SSGTBL104_107_OFFSET (0x4E8U) +#define CRU_SSGTBL104_107_SSGTBL104_107_SHIFT (0U) +#define CRU_SSGTBL104_107_SSGTBL104_107_MASK (0xFFFFFFFFU << CRU_SSGTBL104_107_SSGTBL104_107_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL108_111 */ +#define CRU_SSGTBL108_111_OFFSET (0x4ECU) +#define CRU_SSGTBL108_111_SSGTBL108_111_SHIFT (0U) +#define CRU_SSGTBL108_111_SSGTBL108_111_MASK (0xFFFFFFFFU << CRU_SSGTBL108_111_SSGTBL108_111_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL112_115 */ +#define CRU_SSGTBL112_115_OFFSET (0x4F0U) +#define CRU_SSGTBL112_115_SSGTBL112_115_SHIFT (0U) +#define CRU_SSGTBL112_115_SSGTBL112_115_MASK (0xFFFFFFFFU << CRU_SSGTBL112_115_SSGTBL112_115_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL116_119 */ +#define CRU_SSGTBL116_119_OFFSET (0x4F4U) +#define CRU_SSGTBL116_119_SSGTBL116_119_SHIFT (0U) +#define CRU_SSGTBL116_119_SSGTBL116_119_MASK (0xFFFFFFFFU << CRU_SSGTBL116_119_SSGTBL116_119_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL120_123 */ +#define CRU_SSGTBL120_123_OFFSET (0x4F8U) +#define CRU_SSGTBL120_123_SSGTBL120_123_SHIFT (0U) +#define CRU_SSGTBL120_123_SSGTBL120_123_MASK (0xFFFFFFFFU << CRU_SSGTBL120_123_SSGTBL120_123_SHIFT) /* 0xFFFFFFFF */ +/* SSGTBL124_127 */ +#define CRU_SSGTBL124_127_OFFSET (0x4FCU) +#define CRU_SSGTBL124_127_SSGTBL124_127_SHIFT (0U) +#define CRU_SSGTBL124_127_SSGTBL124_127_MASK (0xFFFFFFFFU << CRU_SSGTBL124_127_SSGTBL124_127_SHIFT) /* 0xFFFFFFFF */ +/* AUTOCS_CORE_CON0 */ +#define CRU_AUTOCS_CORE_CON0_OFFSET (0x500U) +#define CRU_AUTOCS_CORE_CON0_PDCORE_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_CORE_CON0_PDCORE_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_CORE_CON0_PDCORE_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_CORE_CON0_PDCORE_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_CORE_CON0_PDCORE_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_CORE_CON0_PDCORE_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_CORE_CON1 */ +#define CRU_AUTOCS_CORE_CON1_OFFSET (0x504U) +#define CRU_AUTOCS_CORE_CON1_CPU_SWITCH_EN_SHIFT (0U) +#define CRU_AUTOCS_CORE_CON1_CPU_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_CORE_CON1_CPU_SWITCH_EN_SHIFT) /* 0x00000001 */ +#define CRU_AUTOCS_CORE_CON1_DSU_SWITCH_EN_SHIFT (1U) +#define CRU_AUTOCS_CORE_CON1_DSU_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_CORE_CON1_DSU_SWITCH_EN_SHIFT) /* 0x00000002 */ +#define CRU_AUTOCS_CORE_CON1_WFI_EN_SHIFT (2U) +#define CRU_AUTOCS_CORE_CON1_WFI_EN_MASK (0x1U << CRU_AUTOCS_CORE_CON1_WFI_EN_SHIFT) /* 0x00000004 */ +#define CRU_AUTOCS_CORE_CON1_WFIL3_EN_SHIFT (3U) +#define CRU_AUTOCS_CORE_CON1_WFIL3_EN_MASK (0x1U << CRU_AUTOCS_CORE_CON1_WFIL3_EN_SHIFT) /* 0x00000008 */ +#define CRU_AUTOCS_CORE_CON1_FIQIRQ_EN_SHIFT (4U) +#define CRU_AUTOCS_CORE_CON1_FIQIRQ_EN_MASK (0x1U << CRU_AUTOCS_CORE_CON1_FIQIRQ_EN_SHIFT) /* 0x00000010 */ +#define CRU_AUTOCS_CORE_CON1_VFIQIRQ_EN_SHIFT (5U) +#define CRU_AUTOCS_CORE_CON1_VFIQIRQ_EN_MASK (0x1U << CRU_AUTOCS_CORE_CON1_VFIQIRQ_EN_SHIFT) /* 0x00000020 */ +#define CRU_AUTOCS_CORE_CON1_NIU_ACTIVE_EN_SHIFT (6U) +#define CRU_AUTOCS_CORE_CON1_NIU_ACTIVE_EN_MASK (0x1U << CRU_AUTOCS_CORE_CON1_NIU_ACTIVE_EN_SHIFT) /* 0x00000040 */ +#define CRU_AUTOCS_CORE_CON1_STEP_SHIFT (8U) +#define CRU_AUTOCS_CORE_CON1_STEP_MASK (0x7U << CRU_AUTOCS_CORE_CON1_STEP_SHIFT) /* 0x00000700 */ +#define CRU_AUTOCS_CORE_CON1_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_CORE_CON1_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_CORE_CON1_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_GPU_CON0 */ +#define CRU_AUTOCS_GPU_CON0_OFFSET (0x508U) +#define CRU_AUTOCS_GPU_CON0_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_GPU_CON0_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_GPU_CON0_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_GPU_CON0_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_GPU_CON0_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_GPU_CON0_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_GPU_CON1 */ +#define CRU_AUTOCS_GPU_CON1_OFFSET (0x50CU) +#define CRU_AUTOCS_GPU_CON1_SWITCH_EN_SHIFT (0U) +#define CRU_AUTOCS_GPU_CON1_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_GPU_CON1_SWITCH_EN_SHIFT) /* 0x00000001 */ +#define CRU_AUTOCS_GPU_CON1_CLK_EN_SHIFT (1U) +#define CRU_AUTOCS_GPU_CON1_CLK_EN_MASK (0x1U << CRU_AUTOCS_GPU_CON1_CLK_EN_SHIFT) /* 0x00000002 */ +#define CRU_AUTOCS_GPU_CON1_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_GPU_CON1_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_GPU_CON1_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_BUS_CON0 */ +#define CRU_AUTOCS_BUS_CON0_OFFSET (0x510U) +#define CRU_AUTOCS_BUS_CON0_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_BUS_CON0_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_BUS_CON0_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_BUS_CON0_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_BUS_CON0_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_BUS_CON0_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_BUS_CON1 */ +#define CRU_AUTOCS_BUS_CON1_OFFSET (0x514U) +#define CRU_AUTOCS_BUS_CON1_SWITCH_EN_SHIFT (0U) +#define CRU_AUTOCS_BUS_CON1_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_BUS_CON1_SWITCH_EN_SHIFT) /* 0x00000001 */ +#define CRU_AUTOCS_BUS_CON1_ACLK_EN_SHIFT (1U) +#define CRU_AUTOCS_BUS_CON1_ACLK_EN_MASK (0x1U << CRU_AUTOCS_BUS_CON1_ACLK_EN_SHIFT) /* 0x00000002 */ +#define CRU_AUTOCS_BUS_CON1_PCLK_EN_SHIFT (3U) +#define CRU_AUTOCS_BUS_CON1_PCLK_EN_MASK (0x1U << CRU_AUTOCS_BUS_CON1_PCLK_EN_SHIFT) /* 0x00000008 */ +#define CRU_AUTOCS_BUS_CON1_MASTER_EN_SHIFT (4U) +#define CRU_AUTOCS_BUS_CON1_MASTER_EN_MASK (0x1U << CRU_AUTOCS_BUS_CON1_MASTER_EN_SHIFT) /* 0x00000010 */ +#define CRU_AUTOCS_BUS_CON1_SLAVE_EN_SHIFT (5U) +#define CRU_AUTOCS_BUS_CON1_SLAVE_EN_MASK (0x1U << CRU_AUTOCS_BUS_CON1_SLAVE_EN_SHIFT) /* 0x00000020 */ +#define CRU_AUTOCS_BUS_CON1_DMAC_M_EN_SHIFT (7U) +#define CRU_AUTOCS_BUS_CON1_DMAC_M_EN_MASK (0x1U << CRU_AUTOCS_BUS_CON1_DMAC_M_EN_SHIFT) /* 0x00000080 */ +#define CRU_AUTOCS_BUS_CON1_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_BUS_CON1_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_BUS_CON1_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_TOP_CON0 */ +#define CRU_AUTOCS_TOP_CON0_OFFSET (0x518U) +#define CRU_AUTOCS_TOP_CON0_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_TOP_CON0_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_TOP_CON0_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_TOP_CON0_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_TOP_CON0_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_TOP_CON0_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_TOP_CON1 */ +#define CRU_AUTOCS_TOP_CON1_OFFSET (0x51CU) +#define CRU_AUTOCS_TOP_CON1_SWITCH_EN_SHIFT (0U) +#define CRU_AUTOCS_TOP_CON1_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_TOP_CON1_SWITCH_EN_SHIFT) /* 0x00000001 */ +#define CRU_AUTOCS_TOP_CON1_ACLK_EN_SHIFT (1U) +#define CRU_AUTOCS_TOP_CON1_ACLK_EN_MASK (0x1U << CRU_AUTOCS_TOP_CON1_ACLK_EN_SHIFT) /* 0x00000002 */ +#define CRU_AUTOCS_TOP_CON1_HCLK_EN_SHIFT (2U) +#define CRU_AUTOCS_TOP_CON1_HCLK_EN_MASK (0x1U << CRU_AUTOCS_TOP_CON1_HCLK_EN_SHIFT) /* 0x00000004 */ +#define CRU_AUTOCS_TOP_CON1_PCLK_EN_SHIFT (3U) +#define CRU_AUTOCS_TOP_CON1_PCLK_EN_MASK (0x1U << CRU_AUTOCS_TOP_CON1_PCLK_EN_SHIFT) /* 0x00000008 */ +#define CRU_AUTOCS_TOP_CON1_MASTER_EN_SHIFT (4U) +#define CRU_AUTOCS_TOP_CON1_MASTER_EN_MASK (0x1U << CRU_AUTOCS_TOP_CON1_MASTER_EN_SHIFT) /* 0x00000010 */ +#define CRU_AUTOCS_TOP_CON1_SLAVE_EN_SHIFT (5U) +#define CRU_AUTOCS_TOP_CON1_SLAVE_EN_MASK (0x1U << CRU_AUTOCS_TOP_CON1_SLAVE_EN_SHIFT) /* 0x00000020 */ +#define CRU_AUTOCS_TOP_CON1_DMAC_M_EN_SHIFT (7U) +#define CRU_AUTOCS_TOP_CON1_DMAC_M_EN_MASK (0x1U << CRU_AUTOCS_TOP_CON1_DMAC_M_EN_SHIFT) /* 0x00000080 */ +#define CRU_AUTOCS_TOP_CON1_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_TOP_CON1_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_TOP_CON1_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_RKVDEC_CON0 */ +#define CRU_AUTOCS_RKVDEC_CON0_OFFSET (0x520U) +#define CRU_AUTOCS_RKVDEC_CON0_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_RKVDEC_CON0_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_RKVDEC_CON0_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_RKVDEC_CON0_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_RKVDEC_CON0_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_RKVDEC_CON0_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_RKVDEC_CON1 */ +#define CRU_AUTOCS_RKVDEC_CON1_OFFSET (0x524U) +#define CRU_AUTOCS_RKVDEC_CON1_SWITCH_EN_SHIFT (0U) +#define CRU_AUTOCS_RKVDEC_CON1_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_RKVDEC_CON1_SWITCH_EN_SHIFT) /* 0x00000001 */ +#define CRU_AUTOCS_RKVDEC_CON1_RKVDEC_ACLK_EN_SHIFT (1U) +#define CRU_AUTOCS_RKVDEC_CON1_RKVDEC_ACLK_EN_MASK (0x1U << CRU_AUTOCS_RKVDEC_CON1_RKVDEC_ACLK_EN_SHIFT) /* 0x00000002 */ +#define CRU_AUTOCS_RKVDEC_CON1_RKVDEC_CLK_CA_EN_SHIFT (2U) +#define CRU_AUTOCS_RKVDEC_CON1_RKVDEC_CLK_CA_EN_MASK (0x1U << CRU_AUTOCS_RKVDEC_CON1_RKVDEC_CLK_CA_EN_SHIFT) /* 0x00000004 */ +#define CRU_AUTOCS_RKVDEC_CON1_RKVDEC_CLK_CORE_EN_SHIFT (3U) +#define CRU_AUTOCS_RKVDEC_CON1_RKVDEC_CLK_CORE_EN_MASK (0x1U << CRU_AUTOCS_RKVDEC_CON1_RKVDEC_CLK_CORE_EN_SHIFT) /* 0x00000008 */ +#define CRU_AUTOCS_RKVDEC_CON1_RKVDEC_CLK_HEVC_EN_SHIFT (4U) +#define CRU_AUTOCS_RKVDEC_CON1_RKVDEC_CLK_HEVC_EN_MASK (0x1U << CRU_AUTOCS_RKVDEC_CON1_RKVDEC_CLK_HEVC_EN_SHIFT) /* 0x00000010 */ +#define CRU_AUTOCS_RKVDEC_CON1_CLK_CA_SEL_CFG_SHIFT (8U) +#define CRU_AUTOCS_RKVDEC_CON1_CLK_CA_SEL_CFG_MASK (0x3U << CRU_AUTOCS_RKVDEC_CON1_CLK_CA_SEL_CFG_SHIFT) /* 0x00000300 */ +#define CRU_AUTOCS_RKVDEC_CON1_CLK_CORE_SEL_CFG_SHIFT (10U) +#define CRU_AUTOCS_RKVDEC_CON1_CLK_CORE_SEL_CFG_MASK (0x3U << CRU_AUTOCS_RKVDEC_CON1_CLK_CORE_SEL_CFG_SHIFT) /* 0x00000C00 */ +#define CRU_AUTOCS_RKVDEC_CON1_CLK_HEVC_SEL_CFG_SHIFT (12U) +#define CRU_AUTOCS_RKVDEC_CON1_CLK_HEVC_SEL_CFG_MASK (0x3U << CRU_AUTOCS_RKVDEC_CON1_CLK_HEVC_SEL_CFG_SHIFT) /* 0x00003000 */ +#define CRU_AUTOCS_RKVDEC_CON1_ACLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_RKVDEC_CON1_ACLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_RKVDEC_CON1_ACLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_RKVENC_CON0 */ +#define CRU_AUTOCS_RKVENC_CON0_OFFSET (0x528U) +#define CRU_AUTOCS_RKVENC_CON0_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_RKVENC_CON0_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_RKVENC_CON0_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_RKVENC_CON0_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_RKVENC_CON0_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_RKVENC_CON0_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_RKVENC_CON1 */ +#define CRU_AUTOCS_RKVENC_CON1_OFFSET (0x52CU) +#define CRU_AUTOCS_RKVENC_CON1_SWITCH_EN_SHIFT (0U) +#define CRU_AUTOCS_RKVENC_CON1_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_RKVENC_CON1_SWITCH_EN_SHIFT) /* 0x00000001 */ +#define CRU_AUTOCS_RKVENC_CON1_CLK_EN_SHIFT (1U) +#define CRU_AUTOCS_RKVENC_CON1_CLK_EN_MASK (0x1U << CRU_AUTOCS_RKVENC_CON1_CLK_EN_SHIFT) /* 0x00000002 */ +#define CRU_AUTOCS_RKVENC_CON1_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_RKVENC_CON1_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_RKVENC_CON1_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_VPU_CON0 */ +#define CRU_AUTOCS_VPU_CON0_OFFSET (0x530U) +#define CRU_AUTOCS_VPU_CON0_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_VPU_CON0_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_VPU_CON0_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_VPU_CON0_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_VPU_CON0_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_VPU_CON0_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_VPU_CON1 */ +#define CRU_AUTOCS_VPU_CON1_OFFSET (0x534U) +#define CRU_AUTOCS_VPU_CON1_SWITCH_EN_SHIFT (0U) +#define CRU_AUTOCS_VPU_CON1_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_VPU_CON1_SWITCH_EN_SHIFT) /* 0x00000001 */ +#define CRU_AUTOCS_VPU_CON1_CLK_EN_SHIFT (1U) +#define CRU_AUTOCS_VPU_CON1_CLK_EN_MASK (0x1U << CRU_AUTOCS_VPU_CON1_CLK_EN_SHIFT) /* 0x00000002 */ +#define CRU_AUTOCS_VPU_CON1_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_VPU_CON1_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_VPU_CON1_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_PERI_CON0 */ +#define CRU_AUTOCS_PERI_CON0_OFFSET (0x538U) +#define CRU_AUTOCS_PERI_CON0_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_PERI_CON0_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_PERI_CON0_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_PERI_CON0_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_PERI_CON0_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_PERI_CON0_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_PERI_CON1 */ +#define CRU_AUTOCS_PERI_CON1_OFFSET (0x53CU) +#define CRU_AUTOCS_PERI_CON1_PERI_SWITCH_EN_SHIFT (0U) +#define CRU_AUTOCS_PERI_CON1_PERI_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_PERI_SWITCH_EN_SHIFT) /* 0x00000001 */ +#define CRU_AUTOCS_PERI_CON1_PERI_ACLK_EN_SHIFT (1U) +#define CRU_AUTOCS_PERI_CON1_PERI_ACLK_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_PERI_ACLK_EN_SHIFT) /* 0x00000002 */ +#define CRU_AUTOCS_PERI_CON1_PERI_HCLK_EN_SHIFT (2U) +#define CRU_AUTOCS_PERI_CON1_PERI_HCLK_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_PERI_HCLK_EN_SHIFT) /* 0x00000004 */ +#define CRU_AUTOCS_PERI_CON1_PHP_SWITCH_EN_SHIFT (3U) +#define CRU_AUTOCS_PERI_CON1_PHP_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_PHP_SWITCH_EN_SHIFT) /* 0x00000008 */ +#define CRU_AUTOCS_PERI_CON1_PHP_ACLK_EN_SHIFT (4U) +#define CRU_AUTOCS_PERI_CON1_PHP_ACLK_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_PHP_ACLK_EN_SHIFT) /* 0x00000010 */ +#define CRU_AUTOCS_PERI_CON1_PHP_HCLK_EN_SHIFT (5U) +#define CRU_AUTOCS_PERI_CON1_PHP_HCLK_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_PHP_HCLK_EN_SHIFT) /* 0x00000020 */ +#define CRU_AUTOCS_PERI_CON1_GA_SWITCH_EN_SHIFT (6U) +#define CRU_AUTOCS_PERI_CON1_GA_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_GA_SWITCH_EN_SHIFT) /* 0x00000040 */ +#define CRU_AUTOCS_PERI_CON1_GA_ACLK_EN_SHIFT (7U) +#define CRU_AUTOCS_PERI_CON1_GA_ACLK_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_GA_ACLK_EN_SHIFT) /* 0x00000080 */ +#define CRU_AUTOCS_PERI_CON1_GA_HCLK_EN_SHIFT (8U) +#define CRU_AUTOCS_PERI_CON1_GA_HCLK_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_GA_HCLK_EN_SHIFT) /* 0x00000100 */ +#define CRU_AUTOCS_PERI_CON1_SF_SWITCH_EN_SHIFT (9U) +#define CRU_AUTOCS_PERI_CON1_SF_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_SF_SWITCH_EN_SHIFT) /* 0x00000200 */ +#define CRU_AUTOCS_PERI_CON1_SF_ACLK_EN_SHIFT (10U) +#define CRU_AUTOCS_PERI_CON1_SF_ACLK_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_SF_ACLK_EN_SHIFT) /* 0x00000400 */ +#define CRU_AUTOCS_PERI_CON1_SF_HCLK_EN_SHIFT (11U) +#define CRU_AUTOCS_PERI_CON1_SF_HCLK_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_SF_HCLK_EN_SHIFT) /* 0x00000800 */ +#define CRU_AUTOCS_PERI_CON1_DCF_M_EN_SHIFT (12U) +#define CRU_AUTOCS_PERI_CON1_DCF_M_EN_MASK (0x1U << CRU_AUTOCS_PERI_CON1_DCF_M_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_PERI_CON1_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_PERI_CON1_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_PERI_CON1_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_GPLL_CON0 */ +#define CRU_AUTOCS_GPLL_CON0_OFFSET (0x540U) +#define CRU_AUTOCS_GPLL_CON0_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_GPLL_CON0_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_GPLL_CON0_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_GPLL_CON0_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_GPLL_CON0_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_GPLL_CON0_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_GPLL_CON1 */ +#define CRU_AUTOCS_GPLL_CON1_OFFSET (0x544U) +#define CRU_AUTOCS_GPLL_CON1_SWITCH_EN_SHIFT (0U) +#define CRU_AUTOCS_GPLL_CON1_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_GPLL_CON1_SWITCH_EN_SHIFT) /* 0x00000001 */ +#define CRU_AUTOCS_GPLL_CON1_WFI_EN_SHIFT (2U) +#define CRU_AUTOCS_GPLL_CON1_WFI_EN_MASK (0x1U << CRU_AUTOCS_GPLL_CON1_WFI_EN_SHIFT) /* 0x00000004 */ +#define CRU_AUTOCS_GPLL_CON1_WFIL3_EN_SHIFT (3U) +#define CRU_AUTOCS_GPLL_CON1_WFIL3_EN_MASK (0x1U << CRU_AUTOCS_GPLL_CON1_WFIL3_EN_SHIFT) /* 0x00000008 */ +#define CRU_AUTOCS_GPLL_CON1_FIQIRQ_EN_SHIFT (4U) +#define CRU_AUTOCS_GPLL_CON1_FIQIRQ_EN_MASK (0x1U << CRU_AUTOCS_GPLL_CON1_FIQIRQ_EN_SHIFT) /* 0x00000010 */ +#define CRU_AUTOCS_GPLL_CON1_VFIQIRQ_EN_SHIFT (5U) +#define CRU_AUTOCS_GPLL_CON1_VFIQIRQ_EN_MASK (0x1U << CRU_AUTOCS_GPLL_CON1_VFIQIRQ_EN_SHIFT) /* 0x00000020 */ +/* AUTOCS_CPLL_CON0 */ +#define CRU_AUTOCS_CPLL_CON0_OFFSET (0x548U) +#define CRU_AUTOCS_CPLL_CON0_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_CPLL_CON0_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_CPLL_CON0_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_CPLL_CON0_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_CPLL_CON0_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_CPLL_CON0_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_CPLL_CON1 */ +#define CRU_AUTOCS_CPLL_CON1_OFFSET (0x54CU) +#define CRU_AUTOCS_CPLL_CON1_SWITCH_EN_SHIFT (0U) +#define CRU_AUTOCS_CPLL_CON1_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_CPLL_CON1_SWITCH_EN_SHIFT) /* 0x00000001 */ +#define CRU_AUTOCS_CPLL_CON1_WFI_EN_SHIFT (2U) +#define CRU_AUTOCS_CPLL_CON1_WFI_EN_MASK (0x1U << CRU_AUTOCS_CPLL_CON1_WFI_EN_SHIFT) /* 0x00000004 */ +#define CRU_AUTOCS_CPLL_CON1_WFIL3_EN_SHIFT (3U) +#define CRU_AUTOCS_CPLL_CON1_WFIL3_EN_MASK (0x1U << CRU_AUTOCS_CPLL_CON1_WFIL3_EN_SHIFT) /* 0x00000008 */ +#define CRU_AUTOCS_CPLL_CON1_FIQIRQ_EN_SHIFT (4U) +#define CRU_AUTOCS_CPLL_CON1_FIQIRQ_EN_MASK (0x1U << CRU_AUTOCS_CPLL_CON1_FIQIRQ_EN_SHIFT) /* 0x00000010 */ +#define CRU_AUTOCS_CPLL_CON1_VFIQIRQ_EN_SHIFT (5U) +#define CRU_AUTOCS_CPLL_CON1_VFIQIRQ_EN_MASK (0x1U << CRU_AUTOCS_CPLL_CON1_VFIQIRQ_EN_SHIFT) /* 0x00000020 */ +/* SDMMC0_CON0 */ +#define CRU_SDMMC0_CON0_OFFSET (0x580U) +#define CRU_SDMMC0_CON0_INIT_STATE_SHIFT (0U) +#define CRU_SDMMC0_CON0_INIT_STATE_MASK (0x1U << CRU_SDMMC0_CON0_INIT_STATE_SHIFT) /* 0x00000001 */ +#define CRU_SDMMC0_CON0_DRV_DEGREE_SHIFT (1U) +#define CRU_SDMMC0_CON0_DRV_DEGREE_MASK (0x3U << CRU_SDMMC0_CON0_DRV_DEGREE_SHIFT) /* 0x00000006 */ +#define CRU_SDMMC0_CON0_DRV_DELAYNUM_SHIFT (3U) +#define CRU_SDMMC0_CON0_DRV_DELAYNUM_MASK (0xFFU << CRU_SDMMC0_CON0_DRV_DELAYNUM_SHIFT) /* 0x000007F8 */ +#define CRU_SDMMC0_CON0_DRV_SEL_SHIFT (11U) +#define CRU_SDMMC0_CON0_DRV_SEL_MASK (0x1U << CRU_SDMMC0_CON0_DRV_SEL_SHIFT) /* 0x00000800 */ +/* SDMMC0_CON1 */ +#define CRU_SDMMC0_CON1_OFFSET (0x584U) +#define CRU_SDMMC0_CON1_SAMPLE_DEGREE_SHIFT (0U) +#define CRU_SDMMC0_CON1_SAMPLE_DEGREE_MASK (0x3U << CRU_SDMMC0_CON1_SAMPLE_DEGREE_SHIFT) /* 0x00000003 */ +#define CRU_SDMMC0_CON1_SAMPLE_DELAYNUM_SHIFT (2U) +#define CRU_SDMMC0_CON1_SAMPLE_DELAYNUM_MASK (0xFFU << CRU_SDMMC0_CON1_SAMPLE_DELAYNUM_SHIFT) /* 0x000003FC */ +#define CRU_SDMMC0_CON1_SAMPLE_SEL_SHIFT (10U) +#define CRU_SDMMC0_CON1_SAMPLE_SEL_MASK (0x1U << CRU_SDMMC0_CON1_SAMPLE_SEL_SHIFT) /* 0x00000400 */ +/* SDMMC1_CON0 */ +#define CRU_SDMMC1_CON0_OFFSET (0x588U) +#define CRU_SDMMC1_CON0_INIT_STATE_SHIFT (0U) +#define CRU_SDMMC1_CON0_INIT_STATE_MASK (0x1U << CRU_SDMMC1_CON0_INIT_STATE_SHIFT) /* 0x00000001 */ +#define CRU_SDMMC1_CON0_DRV_DEGREE_SHIFT (1U) +#define CRU_SDMMC1_CON0_DRV_DEGREE_MASK (0x3U << CRU_SDMMC1_CON0_DRV_DEGREE_SHIFT) /* 0x00000006 */ +#define CRU_SDMMC1_CON0_DRV_DELAYNUM_SHIFT (3U) +#define CRU_SDMMC1_CON0_DRV_DELAYNUM_MASK (0xFFU << CRU_SDMMC1_CON0_DRV_DELAYNUM_SHIFT) /* 0x000007F8 */ +#define CRU_SDMMC1_CON0_DRV_SEL_SHIFT (11U) +#define CRU_SDMMC1_CON0_DRV_SEL_MASK (0x1U << CRU_SDMMC1_CON0_DRV_SEL_SHIFT) /* 0x00000800 */ +/* SDMMC1_CON1 */ +#define CRU_SDMMC1_CON1_OFFSET (0x58CU) +#define CRU_SDMMC1_CON1_SAMPLE_DEGREE_SHIFT (0U) +#define CRU_SDMMC1_CON1_SAMPLE_DEGREE_MASK (0x3U << CRU_SDMMC1_CON1_SAMPLE_DEGREE_SHIFT) /* 0x00000003 */ +#define CRU_SDMMC1_CON1_SAMPLE_DELAYNUM_SHIFT (2U) +#define CRU_SDMMC1_CON1_SAMPLE_DELAYNUM_MASK (0xFFU << CRU_SDMMC1_CON1_SAMPLE_DELAYNUM_SHIFT) /* 0x000003FC */ +#define CRU_SDMMC1_CON1_SAMPLE_SEL_SHIFT (10U) +#define CRU_SDMMC1_CON1_SAMPLE_SEL_MASK (0x1U << CRU_SDMMC1_CON1_SAMPLE_SEL_SHIFT) /* 0x00000400 */ +/* SDMMC2_CON0 */ +#define CRU_SDMMC2_CON0_OFFSET (0x590U) +#define CRU_SDMMC2_CON0_INIT_STATE_SHIFT (0U) +#define CRU_SDMMC2_CON0_INIT_STATE_MASK (0x1U << CRU_SDMMC2_CON0_INIT_STATE_SHIFT) /* 0x00000001 */ +#define CRU_SDMMC2_CON0_DRV_DEGREE_SHIFT (1U) +#define CRU_SDMMC2_CON0_DRV_DEGREE_MASK (0x3U << CRU_SDMMC2_CON0_DRV_DEGREE_SHIFT) /* 0x00000006 */ +#define CRU_SDMMC2_CON0_DRV_DELAYNUM_SHIFT (3U) +#define CRU_SDMMC2_CON0_DRV_DELAYNUM_MASK (0xFFU << CRU_SDMMC2_CON0_DRV_DELAYNUM_SHIFT) /* 0x000007F8 */ +#define CRU_SDMMC2_CON0_DRV_SEL_SHIFT (11U) +#define CRU_SDMMC2_CON0_DRV_SEL_MASK (0x1U << CRU_SDMMC2_CON0_DRV_SEL_SHIFT) /* 0x00000800 */ +/* SDMMC2_CON1 */ +#define CRU_SDMMC2_CON1_OFFSET (0x594U) +#define CRU_SDMMC2_CON1_SAMPLE_DEGREE_SHIFT (0U) +#define CRU_SDMMC2_CON1_SAMPLE_DEGREE_MASK (0x3U << CRU_SDMMC2_CON1_SAMPLE_DEGREE_SHIFT) /* 0x00000003 */ +#define CRU_SDMMC2_CON1_SAMPLE_DELAYNUM_SHIFT (2U) +#define CRU_SDMMC2_CON1_SAMPLE_DELAYNUM_MASK (0xFFU << CRU_SDMMC2_CON1_SAMPLE_DELAYNUM_SHIFT) /* 0x000003FC */ +#define CRU_SDMMC2_CON1_SAMPLE_SEL_SHIFT (10U) +#define CRU_SDMMC2_CON1_SAMPLE_SEL_MASK (0x1U << CRU_SDMMC2_CON1_SAMPLE_SEL_SHIFT) /* 0x00000400 */ +/* EMMC_CON0 */ +#define CRU_EMMC_CON0_OFFSET (0x598U) +#define CRU_EMMC_CON0_INIT_STATE_SHIFT (0U) +#define CRU_EMMC_CON0_INIT_STATE_MASK (0x1U << CRU_EMMC_CON0_INIT_STATE_SHIFT) /* 0x00000001 */ +#define CRU_EMMC_CON0_DRV_DEGREE_SHIFT (1U) +#define CRU_EMMC_CON0_DRV_DEGREE_MASK (0x3U << CRU_EMMC_CON0_DRV_DEGREE_SHIFT) /* 0x00000006 */ +#define CRU_EMMC_CON0_DRV_DELAYNUM_SHIFT (3U) +#define CRU_EMMC_CON0_DRV_DELAYNUM_MASK (0xFFU << CRU_EMMC_CON0_DRV_DELAYNUM_SHIFT) /* 0x000007F8 */ +#define CRU_EMMC_CON0_DRV_SEL_SHIFT (11U) +#define CRU_EMMC_CON0_DRV_SEL_MASK (0x1U << CRU_EMMC_CON0_DRV_SEL_SHIFT) /* 0x00000800 */ +/* EMMC_CON1 */ +#define CRU_EMMC_CON1_OFFSET (0x59CU) +#define CRU_EMMC_CON1_SAMPLE_DEGREE_SHIFT (0U) +#define CRU_EMMC_CON1_SAMPLE_DEGREE_MASK (0x3U << CRU_EMMC_CON1_SAMPLE_DEGREE_SHIFT) /* 0x00000003 */ +#define CRU_EMMC_CON1_SAMPLE_DELAYNUM_SHIFT (2U) +#define CRU_EMMC_CON1_SAMPLE_DELAYNUM_MASK (0xFFU << CRU_EMMC_CON1_SAMPLE_DELAYNUM_SHIFT) /* 0x000003FC */ +#define CRU_EMMC_CON1_SAMPLE_SEL_SHIFT (10U) +#define CRU_EMMC_CON1_SAMPLE_SEL_MASK (0x1U << CRU_EMMC_CON1_SAMPLE_SEL_SHIFT) /* 0x00000400 */ +/******************************************I2C*******************************************/ +/* CON */ +#define I2C_CON_OFFSET (0x0U) +#define I2C_CON_I2C_EN_SHIFT (0U) +#define I2C_CON_I2C_EN_MASK (0x1U << I2C_CON_I2C_EN_SHIFT) /* 0x00000001 */ +#define I2C_CON_I2C_MODE_SHIFT (1U) +#define I2C_CON_I2C_MODE_MASK (0x3U << I2C_CON_I2C_MODE_SHIFT) /* 0x00000006 */ +#define I2C_CON_START_SHIFT (3U) +#define I2C_CON_START_MASK (0x1U << I2C_CON_START_SHIFT) /* 0x00000008 */ +#define I2C_CON_STOP_SHIFT (4U) +#define I2C_CON_STOP_MASK (0x1U << I2C_CON_STOP_SHIFT) /* 0x00000010 */ +#define I2C_CON_ACK_SHIFT (5U) +#define I2C_CON_ACK_MASK (0x1U << I2C_CON_ACK_SHIFT) /* 0x00000020 */ +#define I2C_CON_ACT2NAK_SHIFT (6U) +#define I2C_CON_ACT2NAK_MASK (0x1U << I2C_CON_ACT2NAK_SHIFT) /* 0x00000040 */ +#define I2C_CON_DATA_UPD_ST_SHIFT (8U) +#define I2C_CON_DATA_UPD_ST_MASK (0x7U << I2C_CON_DATA_UPD_ST_SHIFT) /* 0x00000700 */ +#define I2C_CON_START_SETUP_SHIFT (12U) +#define I2C_CON_START_SETUP_MASK (0x3U << I2C_CON_START_SETUP_SHIFT) /* 0x00003000 */ +#define I2C_CON_STOP_SETUP_SHIFT (14U) +#define I2C_CON_STOP_SETUP_MASK (0x3U << I2C_CON_STOP_SETUP_SHIFT) /* 0x0000C000 */ +#define I2C_CON_VERSION_SHIFT (16U) +#define I2C_CON_VERSION_MASK (0xFFFFU << I2C_CON_VERSION_SHIFT) /* 0xFFFF0000 */ +/* CLKDIV */ +#define I2C_CLKDIV_OFFSET (0x4U) +#define I2C_CLKDIV_CLKDIVL_SHIFT (0U) +#define I2C_CLKDIV_CLKDIVL_MASK (0xFFFFU << I2C_CLKDIV_CLKDIVL_SHIFT) /* 0x0000FFFF */ +#define I2C_CLKDIV_CLKDIVH_SHIFT (16U) +#define I2C_CLKDIV_CLKDIVH_MASK (0xFFFFU << I2C_CLKDIV_CLKDIVH_SHIFT) /* 0xFFFF0000 */ +/* MRXADDR */ +#define I2C_MRXADDR_OFFSET (0x8U) +#define I2C_MRXADDR_SADDR_SHIFT (0U) +#define I2C_MRXADDR_SADDR_MASK (0xFFFFFFU << I2C_MRXADDR_SADDR_SHIFT) /* 0x00FFFFFF */ +#define I2C_MRXADDR_ADDLVLD_SHIFT (24U) +#define I2C_MRXADDR_ADDLVLD_MASK (0x1U << I2C_MRXADDR_ADDLVLD_SHIFT) /* 0x01000000 */ +#define I2C_MRXADDR_ADDMVLD_SHIFT (25U) +#define I2C_MRXADDR_ADDMVLD_MASK (0x1U << I2C_MRXADDR_ADDMVLD_SHIFT) /* 0x02000000 */ +#define I2C_MRXADDR_ADDHVLD_SHIFT (26U) +#define I2C_MRXADDR_ADDHVLD_MASK (0x1U << I2C_MRXADDR_ADDHVLD_SHIFT) /* 0x04000000 */ +/* MRXRADDR */ +#define I2C_MRXRADDR_OFFSET (0xCU) +#define I2C_MRXRADDR_SRADDR_SHIFT (0U) +#define I2C_MRXRADDR_SRADDR_MASK (0xFFFFFFU << I2C_MRXRADDR_SRADDR_SHIFT) /* 0x00FFFFFF */ +#define I2C_MRXRADDR_SRADDLVLD_SHIFT (24U) +#define I2C_MRXRADDR_SRADDLVLD_MASK (0x1U << I2C_MRXRADDR_SRADDLVLD_SHIFT) /* 0x01000000 */ +#define I2C_MRXRADDR_SRADDMVLD_SHIFT (25U) +#define I2C_MRXRADDR_SRADDMVLD_MASK (0x1U << I2C_MRXRADDR_SRADDMVLD_SHIFT) /* 0x02000000 */ +#define I2C_MRXRADDR_SRADDHVLD_SHIFT (26U) +#define I2C_MRXRADDR_SRADDHVLD_MASK (0x1U << I2C_MRXRADDR_SRADDHVLD_SHIFT) /* 0x04000000 */ +/* MTXCNT */ +#define I2C_MTXCNT_OFFSET (0x10U) +#define I2C_MTXCNT_MTXCNT_SHIFT (0U) +#define I2C_MTXCNT_MTXCNT_MASK (0x3FU << I2C_MTXCNT_MTXCNT_SHIFT) /* 0x0000003F */ +/* MRXCNT */ +#define I2C_MRXCNT_OFFSET (0x14U) +#define I2C_MRXCNT_MRXCNT_SHIFT (0U) +#define I2C_MRXCNT_MRXCNT_MASK (0x3FU << I2C_MRXCNT_MRXCNT_SHIFT) /* 0x0000003F */ +/* IEN */ +#define I2C_IEN_OFFSET (0x18U) +#define I2C_IEN_BTFIEN_SHIFT (0U) +#define I2C_IEN_BTFIEN_MASK (0x1U << I2C_IEN_BTFIEN_SHIFT) /* 0x00000001 */ +#define I2C_IEN_BRFIEN_SHIFT (1U) +#define I2C_IEN_BRFIEN_MASK (0x1U << I2C_IEN_BRFIEN_SHIFT) /* 0x00000002 */ +#define I2C_IEN_MBTFIEN_SHIFT (2U) +#define I2C_IEN_MBTFIEN_MASK (0x1U << I2C_IEN_MBTFIEN_SHIFT) /* 0x00000004 */ +#define I2C_IEN_MBRFIEN_SHIFT (3U) +#define I2C_IEN_MBRFIEN_MASK (0x1U << I2C_IEN_MBRFIEN_SHIFT) /* 0x00000008 */ +#define I2C_IEN_STARTIEN_SHIFT (4U) +#define I2C_IEN_STARTIEN_MASK (0x1U << I2C_IEN_STARTIEN_SHIFT) /* 0x00000010 */ +#define I2C_IEN_STOPIEN_SHIFT (5U) +#define I2C_IEN_STOPIEN_MASK (0x1U << I2C_IEN_STOPIEN_SHIFT) /* 0x00000020 */ +#define I2C_IEN_NAKRCVIEN_SHIFT (6U) +#define I2C_IEN_NAKRCVIEN_MASK (0x1U << I2C_IEN_NAKRCVIEN_SHIFT) /* 0x00000040 */ +#define I2C_IEN_SLAVEHDSCLEN_SHIFT (7U) +#define I2C_IEN_SLAVEHDSCLEN_MASK (0x1U << I2C_IEN_SLAVEHDSCLEN_SHIFT) /* 0x00000080 */ +/* IPD */ +#define I2C_IPD_OFFSET (0x1CU) +#define I2C_IPD_BTFIPD_SHIFT (0U) +#define I2C_IPD_BTFIPD_MASK (0x1U << I2C_IPD_BTFIPD_SHIFT) /* 0x00000001 */ +#define I2C_IPD_BRFIPD_SHIFT (1U) +#define I2C_IPD_BRFIPD_MASK (0x1U << I2C_IPD_BRFIPD_SHIFT) /* 0x00000002 */ +#define I2C_IPD_MBTFIPD_SHIFT (2U) +#define I2C_IPD_MBTFIPD_MASK (0x1U << I2C_IPD_MBTFIPD_SHIFT) /* 0x00000004 */ +#define I2C_IPD_MBRFIPD_SHIFT (3U) +#define I2C_IPD_MBRFIPD_MASK (0x1U << I2C_IPD_MBRFIPD_SHIFT) /* 0x00000008 */ +#define I2C_IPD_STARTIPD_SHIFT (4U) +#define I2C_IPD_STARTIPD_MASK (0x1U << I2C_IPD_STARTIPD_SHIFT) /* 0x00000010 */ +#define I2C_IPD_STOPIPD_SHIFT (5U) +#define I2C_IPD_STOPIPD_MASK (0x1U << I2C_IPD_STOPIPD_SHIFT) /* 0x00000020 */ +#define I2C_IPD_NAKRCVIPD_SHIFT (6U) +#define I2C_IPD_NAKRCVIPD_MASK (0x1U << I2C_IPD_NAKRCVIPD_SHIFT) /* 0x00000040 */ +#define I2C_IPD_SLAVEHDSCLIPD_SHIFT (7U) +#define I2C_IPD_SLAVEHDSCLIPD_MASK (0x1U << I2C_IPD_SLAVEHDSCLIPD_SHIFT) /* 0x00000080 */ +/* FCNT */ +#define I2C_FCNT_OFFSET (0x20U) +#define I2C_FCNT (0x0U) +#define I2C_FCNT_FCNT_SHIFT (0U) +#define I2C_FCNT_FCNT_MASK (0x3FU << I2C_FCNT_FCNT_SHIFT) /* 0x0000003F */ +/* SCL_OE_DB */ +#define I2C_SCL_OE_DB_OFFSET (0x24U) +#define I2C_SCL_OE_DB_SCL_OE_DB_SHIFT (0U) +#define I2C_SCL_OE_DB_SCL_OE_DB_MASK (0xFFU << I2C_SCL_OE_DB_SCL_OE_DB_SHIFT) /* 0x000000FF */ +/* TXDATA0 */ +#define I2C_TXDATA0_OFFSET (0x100U) +#define I2C_TXDATA0_TXDATA0_SHIFT (0U) +#define I2C_TXDATA0_TXDATA0_MASK (0xFFFFFFFFU << I2C_TXDATA0_TXDATA0_SHIFT) /* 0xFFFFFFFF */ +/* TXDATA1 */ +#define I2C_TXDATA1_OFFSET (0x104U) +#define I2C_TXDATA1_TXDATA1_SHIFT (0U) +#define I2C_TXDATA1_TXDATA1_MASK (0xFFFFFFFFU << I2C_TXDATA1_TXDATA1_SHIFT) /* 0xFFFFFFFF */ +/* TXDATA2 */ +#define I2C_TXDATA2_OFFSET (0x108U) +#define I2C_TXDATA2_TXDATA2_SHIFT (0U) +#define I2C_TXDATA2_TXDATA2_MASK (0xFFFFFFFFU << I2C_TXDATA2_TXDATA2_SHIFT) /* 0xFFFFFFFF */ +/* TXDATA3 */ +#define I2C_TXDATA3_OFFSET (0x10CU) +#define I2C_TXDATA3_TXDATA3_SHIFT (0U) +#define I2C_TXDATA3_TXDATA3_MASK (0xFFFFFFFFU << I2C_TXDATA3_TXDATA3_SHIFT) /* 0xFFFFFFFF */ +/* TXDATA4 */ +#define I2C_TXDATA4_OFFSET (0x110U) +#define I2C_TXDATA4_TXDATA4_SHIFT (0U) +#define I2C_TXDATA4_TXDATA4_MASK (0xFFFFFFFFU << I2C_TXDATA4_TXDATA4_SHIFT) /* 0xFFFFFFFF */ +/* TXDATA5 */ +#define I2C_TXDATA5_OFFSET (0x114U) +#define I2C_TXDATA5_TXDATA5_SHIFT (0U) +#define I2C_TXDATA5_TXDATA5_MASK (0xFFFFFFFFU << I2C_TXDATA5_TXDATA5_SHIFT) /* 0xFFFFFFFF */ +/* TXDATA6 */ +#define I2C_TXDATA6_OFFSET (0x118U) +#define I2C_TXDATA6_TXDATA6_SHIFT (0U) +#define I2C_TXDATA6_TXDATA6_MASK (0xFFFFFFFFU << I2C_TXDATA6_TXDATA6_SHIFT) /* 0xFFFFFFFF */ +/* TXDATA7 */ +#define I2C_TXDATA7_OFFSET (0x11CU) +#define I2C_TXDATA7_TXDATA7_SHIFT (0U) +#define I2C_TXDATA7_TXDATA7_MASK (0xFFFFFFFFU << I2C_TXDATA7_TXDATA7_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA0 */ +#define I2C_RXDATA0_OFFSET (0x200U) +#define I2C_RXDATA0 (0x0U) +#define I2C_RXDATA0_RXDATA0_SHIFT (0U) +#define I2C_RXDATA0_RXDATA0_MASK (0xFFFFFFFFU << I2C_RXDATA0_RXDATA0_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA1 */ +#define I2C_RXDATA1_OFFSET (0x204U) +#define I2C_RXDATA1 (0x0U) +#define I2C_RXDATA1_RXDATA1_SHIFT (0U) +#define I2C_RXDATA1_RXDATA1_MASK (0xFFFFFFFFU << I2C_RXDATA1_RXDATA1_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA2 */ +#define I2C_RXDATA2_OFFSET (0x208U) +#define I2C_RXDATA2 (0x0U) +#define I2C_RXDATA2_RXDATA2_SHIFT (0U) +#define I2C_RXDATA2_RXDATA2_MASK (0xFFFFFFFFU << I2C_RXDATA2_RXDATA2_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA3 */ +#define I2C_RXDATA3_OFFSET (0x20CU) +#define I2C_RXDATA3 (0x0U) +#define I2C_RXDATA3_RXDATA3_SHIFT (0U) +#define I2C_RXDATA3_RXDATA3_MASK (0xFFFFFFFFU << I2C_RXDATA3_RXDATA3_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA4 */ +#define I2C_RXDATA4_OFFSET (0x210U) +#define I2C_RXDATA4 (0x0U) +#define I2C_RXDATA4_RXDATA4_SHIFT (0U) +#define I2C_RXDATA4_RXDATA4_MASK (0xFFFFFFFFU << I2C_RXDATA4_RXDATA4_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA5 */ +#define I2C_RXDATA5_OFFSET (0x214U) +#define I2C_RXDATA5 (0x0U) +#define I2C_RXDATA5_RXDATA5_SHIFT (0U) +#define I2C_RXDATA5_RXDATA5_MASK (0xFFFFFFFFU << I2C_RXDATA5_RXDATA5_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA6 */ +#define I2C_RXDATA6_OFFSET (0x218U) +#define I2C_RXDATA6 (0x0U) +#define I2C_RXDATA6_RXDATA6_SHIFT (0U) +#define I2C_RXDATA6_RXDATA6_MASK (0xFFFFFFFFU << I2C_RXDATA6_RXDATA6_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA7 */ +#define I2C_RXDATA7_OFFSET (0x21CU) +#define I2C_RXDATA7 (0x0U) +#define I2C_RXDATA7_RXDATA7_SHIFT (0U) +#define I2C_RXDATA7_RXDATA7_MASK (0xFFFFFFFFU << I2C_RXDATA7_RXDATA7_SHIFT) /* 0xFFFFFFFF */ +/* ST */ +#define I2C_ST_OFFSET (0x220U) +#define I2C_ST (0x0U) +#define I2C_ST_SDA_ST_SHIFT (0U) +#define I2C_ST_SDA_ST_MASK (0x1U << I2C_ST_SDA_ST_SHIFT) /* 0x00000001 */ +#define I2C_ST_SCL_ST_SHIFT (1U) +#define I2C_ST_SCL_ST_MASK (0x1U << I2C_ST_SCL_ST_SHIFT) /* 0x00000002 */ +/* DBGCTRL */ +#define I2C_DBGCTRL_OFFSET (0x224U) +#define I2C_DBGCTRL_FLT_F_SHIFT (0U) +#define I2C_DBGCTRL_FLT_F_MASK (0xFU << I2C_DBGCTRL_FLT_F_SHIFT) /* 0x0000000F */ +#define I2C_DBGCTRL_FLT_R_SHIFT (4U) +#define I2C_DBGCTRL_FLT_R_MASK (0xFU << I2C_DBGCTRL_FLT_R_SHIFT) /* 0x000000F0 */ +#define I2C_DBGCTRL_SLV_HOLD_SCL_TH_SHIFT (8U) +#define I2C_DBGCTRL_SLV_HOLD_SCL_TH_MASK (0xFU << I2C_DBGCTRL_SLV_HOLD_SCL_TH_SHIFT) /* 0x00000F00 */ +#define I2C_DBGCTRL_FLT_EN_SHIFT (12U) +#define I2C_DBGCTRL_FLT_EN_MASK (0x1U << I2C_DBGCTRL_FLT_EN_SHIFT) /* 0x00001000 */ +#define I2C_DBGCTRL_NAK_RELEASE_SCL_SHIFT (13U) +#define I2C_DBGCTRL_NAK_RELEASE_SCL_MASK (0x1U << I2C_DBGCTRL_NAK_RELEASE_SCL_SHIFT) /* 0x00002000 */ +#define I2C_DBGCTRL_H0_CHECK_SCL_SHIFT (14U) +#define I2C_DBGCTRL_H0_CHECK_SCL_MASK (0x1U << I2C_DBGCTRL_H0_CHECK_SCL_SHIFT) /* 0x00004000 */ +/******************************************UART******************************************/ +/* RBR */ +#define UART_RBR_OFFSET (0x0U) +#define UART_RBR (0x0U) +#define UART_RBR_DATA_INPUT_SHIFT (0U) +#define UART_RBR_DATA_INPUT_MASK (0xFFU << UART_RBR_DATA_INPUT_SHIFT) /* 0x000000FF */ +/* DLL */ +#define UART_DLL_OFFSET (0x0U) +#define UART_DLL_BAUD_RATE_DIVISOR_L_SHIFT (0U) +#define UART_DLL_BAUD_RATE_DIVISOR_L_MASK (0xFFU << UART_DLL_BAUD_RATE_DIVISOR_L_SHIFT) /* 0x000000FF */ +/* THR */ +#define UART_THR_OFFSET (0x0U) +#define UART_THR_DATA_OUTPUT_SHIFT (0U) +#define UART_THR_DATA_OUTPUT_MASK (0xFFU << UART_THR_DATA_OUTPUT_SHIFT) /* 0x000000FF */ +/* DLH */ +#define UART_DLH_OFFSET (0x4U) +#define UART_DLH_BAUD_RATE_DIVISOR_H_SHIFT (0U) +#define UART_DLH_BAUD_RATE_DIVISOR_H_MASK (0xFFU << UART_DLH_BAUD_RATE_DIVISOR_H_SHIFT) /* 0x000000FF */ +/* IER */ +#define UART_IER_OFFSET (0x4U) +#define UART_IER_RECEIVE_DATA_AVAILABLE_INT_EN_SHIFT (0U) +#define UART_IER_RECEIVE_DATA_AVAILABLE_INT_EN_MASK (0x1U << UART_IER_RECEIVE_DATA_AVAILABLE_INT_EN_SHIFT) /* 0x00000001 */ +#define UART_IER_TRANS_HOLD_EMPTY_INT_EN_SHIFT (1U) +#define UART_IER_TRANS_HOLD_EMPTY_INT_EN_MASK (0x1U << UART_IER_TRANS_HOLD_EMPTY_INT_EN_SHIFT) /* 0x00000002 */ +#define UART_IER_RECEIVE_LINE_STATUS_INT_EN_SHIFT (2U) +#define UART_IER_RECEIVE_LINE_STATUS_INT_EN_MASK (0x1U << UART_IER_RECEIVE_LINE_STATUS_INT_EN_SHIFT) /* 0x00000004 */ +#define UART_IER_MODEM_STATUS_INT_EN_SHIFT (3U) +#define UART_IER_MODEM_STATUS_INT_EN_MASK (0x1U << UART_IER_MODEM_STATUS_INT_EN_SHIFT) /* 0x00000008 */ +#define UART_IER_PROG_THRE_INT_EN_SHIFT (7U) +#define UART_IER_PROG_THRE_INT_EN_MASK (0x1U << UART_IER_PROG_THRE_INT_EN_SHIFT) /* 0x00000080 */ +/* FCR */ +#define UART_FCR_OFFSET (0x8U) +#define UART_FCR_FIFO_EN_SHIFT (0U) +#define UART_FCR_FIFO_EN_MASK (0x1U << UART_FCR_FIFO_EN_SHIFT) /* 0x00000001 */ +#define UART_FCR_RCVR_FIFO_RESET_SHIFT (1U) +#define UART_FCR_RCVR_FIFO_RESET_MASK (0x1U << UART_FCR_RCVR_FIFO_RESET_SHIFT) /* 0x00000002 */ +#define UART_FCR_XMIT_FIFO_RESET_SHIFT (2U) +#define UART_FCR_XMIT_FIFO_RESET_MASK (0x1U << UART_FCR_XMIT_FIFO_RESET_SHIFT) /* 0x00000004 */ +#define UART_FCR_DMA_MODE_SHIFT (3U) +#define UART_FCR_DMA_MODE_MASK (0x1U << UART_FCR_DMA_MODE_SHIFT) /* 0x00000008 */ +#define UART_FCR_TX_EMPTY_TRIGGER_SHIFT (4U) +#define UART_FCR_TX_EMPTY_TRIGGER_MASK (0x3U << UART_FCR_TX_EMPTY_TRIGGER_SHIFT) /* 0x00000030 */ +#define UART_FCR_RCVR_TRIGGER_SHIFT (6U) +#define UART_FCR_RCVR_TRIGGER_MASK (0x3U << UART_FCR_RCVR_TRIGGER_SHIFT) /* 0x000000C0 */ +/* IIR */ +#define UART_IIR_OFFSET (0x8U) +#define UART_IIR (0x1U) +#define UART_IIR_INT_ID_SHIFT (0U) +#define UART_IIR_INT_ID_MASK (0xFU << UART_IIR_INT_ID_SHIFT) /* 0x0000000F */ +#define UART_IIR_FIFOS_EN_SHIFT (6U) +#define UART_IIR_FIFOS_EN_MASK (0x3U << UART_IIR_FIFOS_EN_SHIFT) /* 0x000000C0 */ +/* LCR */ +#define UART_LCR_OFFSET (0xCU) +#define UART_LCR_DATA_LENGTH_SEL_SHIFT (0U) +#define UART_LCR_DATA_LENGTH_SEL_MASK (0x3U << UART_LCR_DATA_LENGTH_SEL_SHIFT) /* 0x00000003 */ +#define UART_LCR_STOP_BITS_NUM_SHIFT (2U) +#define UART_LCR_STOP_BITS_NUM_MASK (0x1U << UART_LCR_STOP_BITS_NUM_SHIFT) /* 0x00000004 */ +#define UART_LCR_PARITY_EN_SHIFT (3U) +#define UART_LCR_PARITY_EN_MASK (0x1U << UART_LCR_PARITY_EN_SHIFT) /* 0x00000008 */ +#define UART_LCR_EVEN_PARITY_SEL_SHIFT (4U) +#define UART_LCR_EVEN_PARITY_SEL_MASK (0x1U << UART_LCR_EVEN_PARITY_SEL_SHIFT) /* 0x00000010 */ +#define UART_LCR_BREAK_CTRL_SHIFT (6U) +#define UART_LCR_BREAK_CTRL_MASK (0x1U << UART_LCR_BREAK_CTRL_SHIFT) /* 0x00000040 */ +#define UART_LCR_DIV_LAT_ACCESS_SHIFT (7U) +#define UART_LCR_DIV_LAT_ACCESS_MASK (0x1U << UART_LCR_DIV_LAT_ACCESS_SHIFT) /* 0x00000080 */ +/* MCR */ +#define UART_MCR_OFFSET (0x10U) +#define UART_MCR_DATA_TERMINAL_READY_SHIFT (0U) +#define UART_MCR_DATA_TERMINAL_READY_MASK (0x1U << UART_MCR_DATA_TERMINAL_READY_SHIFT) /* 0x00000001 */ +#define UART_MCR_REQ_TO_SEND_SHIFT (1U) +#define UART_MCR_REQ_TO_SEND_MASK (0x1U << UART_MCR_REQ_TO_SEND_SHIFT) /* 0x00000002 */ +#define UART_MCR_OUT1_SHIFT (2U) +#define UART_MCR_OUT1_MASK (0x1U << UART_MCR_OUT1_SHIFT) /* 0x00000004 */ +#define UART_MCR_OUT2_SHIFT (3U) +#define UART_MCR_OUT2_MASK (0x1U << UART_MCR_OUT2_SHIFT) /* 0x00000008 */ +#define UART_MCR_LOOPBACK_SHIFT (4U) +#define UART_MCR_LOOPBACK_MASK (0x1U << UART_MCR_LOOPBACK_SHIFT) /* 0x00000010 */ +#define UART_MCR_AUTO_FLOW_CTRL_EN_SHIFT (5U) +#define UART_MCR_AUTO_FLOW_CTRL_EN_MASK (0x1U << UART_MCR_AUTO_FLOW_CTRL_EN_SHIFT) /* 0x00000020 */ +#define UART_MCR_SIR_MODE_EN_SHIFT (6U) +#define UART_MCR_SIR_MODE_EN_MASK (0x1U << UART_MCR_SIR_MODE_EN_SHIFT) /* 0x00000040 */ +/* LSR */ +#define UART_LSR_OFFSET (0x14U) +#define UART_LSR (0x60U) +#define UART_LSR_DATA_READY_SHIFT (0U) +#define UART_LSR_DATA_READY_MASK (0x1U << UART_LSR_DATA_READY_SHIFT) /* 0x00000001 */ +#define UART_LSR_OVERRUN_ERROR_SHIFT (1U) +#define UART_LSR_OVERRUN_ERROR_MASK (0x1U << UART_LSR_OVERRUN_ERROR_SHIFT) /* 0x00000002 */ +#define UART_LSR_PARITY_EROR_SHIFT (2U) +#define UART_LSR_PARITY_EROR_MASK (0x1U << UART_LSR_PARITY_EROR_SHIFT) /* 0x00000004 */ +#define UART_LSR_FRAMING_ERROR_SHIFT (3U) +#define UART_LSR_FRAMING_ERROR_MASK (0x1U << UART_LSR_FRAMING_ERROR_SHIFT) /* 0x00000008 */ +#define UART_LSR_BREAK_INT_SHIFT (4U) +#define UART_LSR_BREAK_INT_MASK (0x1U << UART_LSR_BREAK_INT_SHIFT) /* 0x00000010 */ +#define UART_LSR_TRANS_HOLD_REG_EMPTY_SHIFT (5U) +#define UART_LSR_TRANS_HOLD_REG_EMPTY_MASK (0x1U << UART_LSR_TRANS_HOLD_REG_EMPTY_SHIFT) /* 0x00000020 */ +#define UART_LSR_TRANS_EMPTY_SHIFT (6U) +#define UART_LSR_TRANS_EMPTY_MASK (0x1U << UART_LSR_TRANS_EMPTY_SHIFT) /* 0x00000040 */ +#define UART_LSR_RECEIVER_FIFO_ERROR_SHIFT (7U) +#define UART_LSR_RECEIVER_FIFO_ERROR_MASK (0x1U << UART_LSR_RECEIVER_FIFO_ERROR_SHIFT) /* 0x00000080 */ +/* MSR */ +#define UART_MSR_OFFSET (0x18U) +#define UART_MSR (0x0U) +#define UART_MSR_DELTA_CLEAR_TO_SEND_SHIFT (0U) +#define UART_MSR_DELTA_CLEAR_TO_SEND_MASK (0x1U << UART_MSR_DELTA_CLEAR_TO_SEND_SHIFT) /* 0x00000001 */ +#define UART_MSR_DELTA_DATA_SET_READY_SHIFT (1U) +#define UART_MSR_DELTA_DATA_SET_READY_MASK (0x1U << UART_MSR_DELTA_DATA_SET_READY_SHIFT) /* 0x00000002 */ +#define UART_MSR_TRAILING_EDGE_RING_INDICATOR_SHIFT (2U) +#define UART_MSR_TRAILING_EDGE_RING_INDICATOR_MASK (0x1U << UART_MSR_TRAILING_EDGE_RING_INDICATOR_SHIFT) /* 0x00000004 */ +#define UART_MSR_DELTA_DATA_CARRIER_DETECT_SHIFT (3U) +#define UART_MSR_DELTA_DATA_CARRIER_DETECT_MASK (0x1U << UART_MSR_DELTA_DATA_CARRIER_DETECT_SHIFT) /* 0x00000008 */ +#define UART_MSR_CLEAR_TO_SEND_SHIFT (4U) +#define UART_MSR_CLEAR_TO_SEND_MASK (0x1U << UART_MSR_CLEAR_TO_SEND_SHIFT) /* 0x00000010 */ +#define UART_MSR_DATA_SET_READY_SHIFT (5U) +#define UART_MSR_DATA_SET_READY_MASK (0x1U << UART_MSR_DATA_SET_READY_SHIFT) /* 0x00000020 */ +#define UART_MSR_RING_INDICATOR_SHIFT (6U) +#define UART_MSR_RING_INDICATOR_MASK (0x1U << UART_MSR_RING_INDICATOR_SHIFT) /* 0x00000040 */ +#define UART_MSR_DATA_CARRIOR_DETECT_SHIFT (7U) +#define UART_MSR_DATA_CARRIOR_DETECT_MASK (0x1U << UART_MSR_DATA_CARRIOR_DETECT_SHIFT) /* 0x00000080 */ +/* SCR */ +#define UART_SCR_OFFSET (0x1CU) +#define UART_SCR_TEMP_STORE_SPACE_SHIFT (0U) +#define UART_SCR_TEMP_STORE_SPACE_MASK (0xFFU << UART_SCR_TEMP_STORE_SPACE_SHIFT) /* 0x000000FF */ +/* SRBR */ +#define UART_SRBR_OFFSET (0x30U) +#define UART_SRBR (0x0U) +#define UART_SRBR_SHADOW_RBR_SHIFT (0U) +#define UART_SRBR_SHADOW_RBR_MASK (0xFFU << UART_SRBR_SHADOW_RBR_SHIFT) /* 0x000000FF */ +/* STHR */ +#define UART_STHR_OFFSET (0x30U) +#define UART_STHR_SHADOW_THR_SHIFT (0U) +#define UART_STHR_SHADOW_THR_MASK (0xFFU << UART_STHR_SHADOW_THR_SHIFT) /* 0x000000FF */ +/* FAR */ +#define UART_FAR_OFFSET (0x70U) +#define UART_FAR_FIFO_ACCESS_TEST_EN_SHIFT (0U) +#define UART_FAR_FIFO_ACCESS_TEST_EN_MASK (0x1U << UART_FAR_FIFO_ACCESS_TEST_EN_SHIFT) /* 0x00000001 */ +/* TFR */ +#define UART_TFR_OFFSET (0x74U) +#define UART_TFR (0x0U) +#define UART_TFR_TRANS_FIFO_READ_SHIFT (0U) +#define UART_TFR_TRANS_FIFO_READ_MASK (0xFFU << UART_TFR_TRANS_FIFO_READ_SHIFT) /* 0x000000FF */ +/* RFW */ +#define UART_RFW_OFFSET (0x78U) +#define UART_RFW_RECEIVE_FIFO_WRITE_SHIFT (0U) +#define UART_RFW_RECEIVE_FIFO_WRITE_MASK (0xFFU << UART_RFW_RECEIVE_FIFO_WRITE_SHIFT) /* 0x000000FF */ +#define UART_RFW_RECEIVE_FIFO_PARITY_ERROR_SHIFT (8U) +#define UART_RFW_RECEIVE_FIFO_PARITY_ERROR_MASK (0x1U << UART_RFW_RECEIVE_FIFO_PARITY_ERROR_SHIFT) /* 0x00000100 */ +#define UART_RFW_RECEIVE_FIFO_FRAMING_ERROR_SHIFT (9U) +#define UART_RFW_RECEIVE_FIFO_FRAMING_ERROR_MASK (0x1U << UART_RFW_RECEIVE_FIFO_FRAMING_ERROR_SHIFT) /* 0x00000200 */ +/* USR */ +#define UART_USR_OFFSET (0x7CU) +#define UART_USR (0x6U) +#define UART_USR_UART_BUSY_SHIFT (0U) +#define UART_USR_UART_BUSY_MASK (0x1U << UART_USR_UART_BUSY_SHIFT) /* 0x00000001 */ +#define UART_USR_TRANS_FIFO_NOT_FULL_SHIFT (1U) +#define UART_USR_TRANS_FIFO_NOT_FULL_MASK (0x1U << UART_USR_TRANS_FIFO_NOT_FULL_SHIFT) /* 0x00000002 */ +#define UART_USR_TRASN_FIFO_EMPTY_SHIFT (2U) +#define UART_USR_TRASN_FIFO_EMPTY_MASK (0x1U << UART_USR_TRASN_FIFO_EMPTY_SHIFT) /* 0x00000004 */ +#define UART_USR_RECEIVE_FIFO_NOT_EMPTY_SHIFT (3U) +#define UART_USR_RECEIVE_FIFO_NOT_EMPTY_MASK (0x1U << UART_USR_RECEIVE_FIFO_NOT_EMPTY_SHIFT) /* 0x00000008 */ +#define UART_USR_RECEIVE_FIFO_FULL_SHIFT (4U) +#define UART_USR_RECEIVE_FIFO_FULL_MASK (0x1U << UART_USR_RECEIVE_FIFO_FULL_SHIFT) /* 0x00000010 */ +/* TFL */ +#define UART_TFL_OFFSET (0x80U) +#define UART_TFL (0x0U) +#define UART_TFL_TRANS_FIFO_LEVEL_SHIFT (0U) +#define UART_TFL_TRANS_FIFO_LEVEL_MASK (0x3FU << UART_TFL_TRANS_FIFO_LEVEL_SHIFT) /* 0x0000003F */ +/* RFL */ +#define UART_RFL_OFFSET (0x84U) +#define UART_RFL (0x0U) +#define UART_RFL_RECEIVE_FIFO_LEVEL_SHIFT (0U) +#define UART_RFL_RECEIVE_FIFO_LEVEL_MASK (0x3FU << UART_RFL_RECEIVE_FIFO_LEVEL_SHIFT) /* 0x0000003F */ +/* SRR */ +#define UART_SRR_OFFSET (0x88U) +#define UART_SRR_UART_RESET_SHIFT (0U) +#define UART_SRR_UART_RESET_MASK (0x1U << UART_SRR_UART_RESET_SHIFT) /* 0x00000001 */ +#define UART_SRR_RCVR_FIFO_RESET_SHIFT (1U) +#define UART_SRR_RCVR_FIFO_RESET_MASK (0x1U << UART_SRR_RCVR_FIFO_RESET_SHIFT) /* 0x00000002 */ +#define UART_SRR_XMIT_FIFO_RESET_SHIFT (2U) +#define UART_SRR_XMIT_FIFO_RESET_MASK (0x1U << UART_SRR_XMIT_FIFO_RESET_SHIFT) /* 0x00000004 */ +/* SRTS */ +#define UART_SRTS_OFFSET (0x8CU) +#define UART_SRTS_SHADOW_REQ_TO_SEND_SHIFT (0U) +#define UART_SRTS_SHADOW_REQ_TO_SEND_MASK (0x1U << UART_SRTS_SHADOW_REQ_TO_SEND_SHIFT) /* 0x00000001 */ +/* SBCR */ +#define UART_SBCR_OFFSET (0x90U) +#define UART_SBCR_SHADOW_BREAK_CTRL_SHIFT (0U) +#define UART_SBCR_SHADOW_BREAK_CTRL_MASK (0x1U << UART_SBCR_SHADOW_BREAK_CTRL_SHIFT) /* 0x00000001 */ +/* SDMAM */ +#define UART_SDMAM_OFFSET (0x94U) +#define UART_SDMAM_SHADOW_DMA_MODE_SHIFT (0U) +#define UART_SDMAM_SHADOW_DMA_MODE_MASK (0x1U << UART_SDMAM_SHADOW_DMA_MODE_SHIFT) /* 0x00000001 */ +/* SFE */ +#define UART_SFE_OFFSET (0x98U) +#define UART_SFE_SHADOW_FIFO_EN_SHIFT (0U) +#define UART_SFE_SHADOW_FIFO_EN_MASK (0x1U << UART_SFE_SHADOW_FIFO_EN_SHIFT) /* 0x00000001 */ +/* SRT */ +#define UART_SRT_OFFSET (0x9CU) +#define UART_SRT_SHADOW_RCVR_TRIGGER_SHIFT (0U) +#define UART_SRT_SHADOW_RCVR_TRIGGER_MASK (0x3U << UART_SRT_SHADOW_RCVR_TRIGGER_SHIFT) /* 0x00000003 */ +/* STET */ +#define UART_STET_OFFSET (0xA0U) +#define UART_STET_SHADOW_TX_EMPTY_TRIGGER_SHIFT (0U) +#define UART_STET_SHADOW_TX_EMPTY_TRIGGER_MASK (0x3U << UART_STET_SHADOW_TX_EMPTY_TRIGGER_SHIFT) /* 0x00000003 */ +/* HTX */ +#define UART_HTX_OFFSET (0xA4U) +#define UART_HTX_HALT_TX_EN_SHIFT (0U) +#define UART_HTX_HALT_TX_EN_MASK (0x1U << UART_HTX_HALT_TX_EN_SHIFT) /* 0x00000001 */ +/* DMASA */ +#define UART_DMASA_OFFSET (0xA8U) +#define UART_DMASA_DMA_SOFTWARE_ACK_SHIFT (0U) +#define UART_DMASA_DMA_SOFTWARE_ACK_MASK (0x1U << UART_DMASA_DMA_SOFTWARE_ACK_SHIFT) /* 0x00000001 */ +/* CPR */ +#define UART_CPR_OFFSET (0xF4U) +#define UART_CPR (0x0U) +#define UART_CPR_APB_DATA_WIDTH_SHIFT (0U) +#define UART_CPR_APB_DATA_WIDTH_MASK (0x3U << UART_CPR_APB_DATA_WIDTH_SHIFT) /* 0x00000003 */ +#define UART_CPR_AFCE_MODE_SHIFT (4U) +#define UART_CPR_AFCE_MODE_MASK (0x1U << UART_CPR_AFCE_MODE_SHIFT) /* 0x00000010 */ +#define UART_CPR_THRE_MODE_SHIFT (5U) +#define UART_CPR_THRE_MODE_MASK (0x1U << UART_CPR_THRE_MODE_SHIFT) /* 0x00000020 */ +#define UART_CPR_SIR_MODE_SHIFT (6U) +#define UART_CPR_SIR_MODE_MASK (0x1U << UART_CPR_SIR_MODE_SHIFT) /* 0x00000040 */ +#define UART_CPR_SIR_LP_MODE_SHIFT (7U) +#define UART_CPR_SIR_LP_MODE_MASK (0x1U << UART_CPR_SIR_LP_MODE_SHIFT) /* 0x00000080 */ +#define UART_CPR_NEW_FEAT_SHIFT (8U) +#define UART_CPR_NEW_FEAT_MASK (0x1U << UART_CPR_NEW_FEAT_SHIFT) /* 0x00000100 */ +#define UART_CPR_FIFO_ACCESS_SHIFT (9U) +#define UART_CPR_FIFO_ACCESS_MASK (0x1U << UART_CPR_FIFO_ACCESS_SHIFT) /* 0x00000200 */ +#define UART_CPR_FIFO_STAT_SHIFT (10U) +#define UART_CPR_FIFO_STAT_MASK (0x1U << UART_CPR_FIFO_STAT_SHIFT) /* 0x00000400 */ +#define UART_CPR_SHADOW_SHIFT (11U) +#define UART_CPR_SHADOW_MASK (0x1U << UART_CPR_SHADOW_SHIFT) /* 0x00000800 */ +#define UART_CPR_UART_ADD_ENCODED_PARAMS_SHIFT (12U) +#define UART_CPR_UART_ADD_ENCODED_PARAMS_MASK (0x1U << UART_CPR_UART_ADD_ENCODED_PARAMS_SHIFT) /* 0x00001000 */ +#define UART_CPR_DMA_EXTRA_SHIFT (13U) +#define UART_CPR_DMA_EXTRA_MASK (0x1U << UART_CPR_DMA_EXTRA_SHIFT) /* 0x00002000 */ +#define UART_CPR_FIFO_MODE_SHIFT (16U) +#define UART_CPR_FIFO_MODE_MASK (0xFFU << UART_CPR_FIFO_MODE_SHIFT) /* 0x00FF0000 */ +/* UCV */ +#define UART_UCV_OFFSET (0xF8U) +#define UART_UCV (0x330372AU) +#define UART_UCV_VER_SHIFT (0U) +#define UART_UCV_VER_MASK (0xFFFFFFFFU << UART_UCV_VER_SHIFT) /* 0xFFFFFFFF */ +/* CTR */ +#define UART_CTR_OFFSET (0xFCU) +#define UART_CTR (0x44570110U) +#define UART_CTR_PERIPHERAL_ID_SHIFT (0U) +#define UART_CTR_PERIPHERAL_ID_MASK (0xFFFFFFFFU << UART_CTR_PERIPHERAL_ID_SHIFT) /* 0xFFFFFFFF */ +/******************************************GPIO******************************************/ +/* SWPORT_DR_L */ +#define GPIO_SWPORT_DR_L_OFFSET (0x0U) +#define GPIO_SWPORT_DR_L_SWPORT_DR_LOW_SHIFT (0U) +#define GPIO_SWPORT_DR_L_SWPORT_DR_LOW_MASK (0xFFFFU << GPIO_SWPORT_DR_L_SWPORT_DR_LOW_SHIFT) /* 0x0000FFFF */ +/* SWPORT_DR_H */ +#define GPIO_SWPORT_DR_H_OFFSET (0x4U) +#define GPIO_SWPORT_DR_H_SWPORT_DR_HIGH_SHIFT (0U) +#define GPIO_SWPORT_DR_H_SWPORT_DR_HIGH_MASK (0xFFFFU << GPIO_SWPORT_DR_H_SWPORT_DR_HIGH_SHIFT) /* 0x0000FFFF */ +/* SWPORT_DDR_L */ +#define GPIO_SWPORT_DDR_L_OFFSET (0x8U) +#define GPIO_SWPORT_DDR_L_SWPORT_DDR_LOW_SHIFT (0U) +#define GPIO_SWPORT_DDR_L_SWPORT_DDR_LOW_MASK (0xFFFFU << GPIO_SWPORT_DDR_L_SWPORT_DDR_LOW_SHIFT) /* 0x0000FFFF */ +/* SWPORT_DDR_H */ +#define GPIO_SWPORT_DDR_H_OFFSET (0xCU) +#define GPIO_SWPORT_DDR_H_SWPORT_DDR_HIGH_SHIFT (0U) +#define GPIO_SWPORT_DDR_H_SWPORT_DDR_HIGH_MASK (0xFFFFU << GPIO_SWPORT_DDR_H_SWPORT_DDR_HIGH_SHIFT) /* 0x0000FFFF */ +/* INT_EN_L */ +#define GPIO_INT_EN_L_OFFSET (0x10U) +#define GPIO_INT_EN_L_INT_EN_LOW_SHIFT (0U) +#define GPIO_INT_EN_L_INT_EN_LOW_MASK (0xFFFFU << GPIO_INT_EN_L_INT_EN_LOW_SHIFT) /* 0x0000FFFF */ +/* INT_EN_H */ +#define GPIO_INT_EN_H_OFFSET (0x14U) +#define GPIO_INT_EN_H_INT_EN_HIGH_SHIFT (0U) +#define GPIO_INT_EN_H_INT_EN_HIGH_MASK (0xFFFFU << GPIO_INT_EN_H_INT_EN_HIGH_SHIFT) /* 0x0000FFFF */ +/* INT_MASK_L */ +#define GPIO_INT_MASK_L_OFFSET (0x18U) +#define GPIO_INT_MASK_L_INT_MASK_LOW_SHIFT (0U) +#define GPIO_INT_MASK_L_INT_MASK_LOW_MASK (0xFFFFU << GPIO_INT_MASK_L_INT_MASK_LOW_SHIFT) /* 0x0000FFFF */ +/* INT_MASK_H */ +#define GPIO_INT_MASK_H_OFFSET (0x1CU) +#define GPIO_INT_MASK_H_INT_MASK_HIGH_SHIFT (0U) +#define GPIO_INT_MASK_H_INT_MASK_HIGH_MASK (0xFFFFU << GPIO_INT_MASK_H_INT_MASK_HIGH_SHIFT) /* 0x0000FFFF */ +/* INT_TYPE_L */ +#define GPIO_INT_TYPE_L_OFFSET (0x20U) +#define GPIO_INT_TYPE_L_INT_TYPE_LOW_SHIFT (0U) +#define GPIO_INT_TYPE_L_INT_TYPE_LOW_MASK (0xFFFFU << GPIO_INT_TYPE_L_INT_TYPE_LOW_SHIFT) /* 0x0000FFFF */ +/* INT_TYPE_H */ +#define GPIO_INT_TYPE_H_OFFSET (0x24U) +#define GPIO_INT_TYPE_H_INT_TYPE_HIGH_SHIFT (0U) +#define GPIO_INT_TYPE_H_INT_TYPE_HIGH_MASK (0xFFFFU << GPIO_INT_TYPE_H_INT_TYPE_HIGH_SHIFT) /* 0x0000FFFF */ +/* INT_POLARITY_L */ +#define GPIO_INT_POLARITY_L_OFFSET (0x28U) +#define GPIO_INT_POLARITY_L_INT_POLARITY_LOW_SHIFT (0U) +#define GPIO_INT_POLARITY_L_INT_POLARITY_LOW_MASK (0xFFFFU << GPIO_INT_POLARITY_L_INT_POLARITY_LOW_SHIFT) /* 0x0000FFFF */ +/* INT_POLARITY_H */ +#define GPIO_INT_POLARITY_H_OFFSET (0x2CU) +#define GPIO_INT_POLARITY_H_INT_POLARITY_HIGH_SHIFT (0U) +#define GPIO_INT_POLARITY_H_INT_POLARITY_HIGH_MASK (0xFFFFU << GPIO_INT_POLARITY_H_INT_POLARITY_HIGH_SHIFT) /* 0x0000FFFF */ +/* INT_BOTHEDGE_L */ +#define GPIO_INT_BOTHEDGE_L_OFFSET (0x30U) +#define GPIO_INT_BOTHEDGE_L_INT_BOTHEDGE_LOW_SHIFT (0U) +#define GPIO_INT_BOTHEDGE_L_INT_BOTHEDGE_LOW_MASK (0xFFFFU << GPIO_INT_BOTHEDGE_L_INT_BOTHEDGE_LOW_SHIFT) /* 0x0000FFFF */ +/* INT_BOTHEDGE_H */ +#define GPIO_INT_BOTHEDGE_H_OFFSET (0x34U) +#define GPIO_INT_BOTHEDGE_H_INT_BOTHEDGE_HIGH_SHIFT (0U) +#define GPIO_INT_BOTHEDGE_H_INT_BOTHEDGE_HIGH_MASK (0xFFFFU << GPIO_INT_BOTHEDGE_H_INT_BOTHEDGE_HIGH_SHIFT) /* 0x0000FFFF */ +/* DEBOUNCE_L */ +#define GPIO_DEBOUNCE_L_OFFSET (0x38U) +#define GPIO_DEBOUNCE_L_DEBOUNCE_LOW_SHIFT (0U) +#define GPIO_DEBOUNCE_L_DEBOUNCE_LOW_MASK (0xFFFFU << GPIO_DEBOUNCE_L_DEBOUNCE_LOW_SHIFT) /* 0x0000FFFF */ +/* DEBOUNCE_H */ +#define GPIO_DEBOUNCE_H_OFFSET (0x3CU) +#define GPIO_DEBOUNCE_H_DEBOUNCE_HIGH_SHIFT (0U) +#define GPIO_DEBOUNCE_H_DEBOUNCE_HIGH_MASK (0xFFFFU << GPIO_DEBOUNCE_H_DEBOUNCE_HIGH_SHIFT) /* 0x0000FFFF */ +/* DBCLK_DIV_EN_L */ +#define GPIO_DBCLK_DIV_EN_L_OFFSET (0x40U) +#define GPIO_DBCLK_DIV_EN_L_DBCLK_DIV_EN_LOW_SHIFT (0U) +#define GPIO_DBCLK_DIV_EN_L_DBCLK_DIV_EN_LOW_MASK (0xFFFFU << GPIO_DBCLK_DIV_EN_L_DBCLK_DIV_EN_LOW_SHIFT) /* 0x0000FFFF */ +/* DBCLK_DIV_EN_H */ +#define GPIO_DBCLK_DIV_EN_H_OFFSET (0x44U) +#define GPIO_DBCLK_DIV_EN_H_DBCLK_DIV_EN_HIGH_SHIFT (0U) +#define GPIO_DBCLK_DIV_EN_H_DBCLK_DIV_EN_HIGH_MASK (0xFFFFU << GPIO_DBCLK_DIV_EN_H_DBCLK_DIV_EN_HIGH_SHIFT) /* 0x0000FFFF */ +/* DBCLK_DIV_CON */ +#define GPIO_DBCLK_DIV_CON_OFFSET (0x48U) +#define GPIO_DBCLK_DIV_CON_DBCLK_DIV_CON_SHIFT (0U) +#define GPIO_DBCLK_DIV_CON_DBCLK_DIV_CON_MASK (0xFFFFFFU << GPIO_DBCLK_DIV_CON_DBCLK_DIV_CON_SHIFT) /* 0x00FFFFFF */ +/* INT_STATUS */ +#define GPIO_INT_STATUS_OFFSET (0x50U) +#define GPIO_INT_STATUS (0x0U) +#define GPIO_INT_STATUS_INT_STATUS_SHIFT (0U) +#define GPIO_INT_STATUS_INT_STATUS_MASK (0xFFFFFFFFU << GPIO_INT_STATUS_INT_STATUS_SHIFT) /* 0xFFFFFFFF */ +/* INT_RAWSTATUS */ +#define GPIO_INT_RAWSTATUS_OFFSET (0x58U) +#define GPIO_INT_RAWSTATUS (0x0U) +#define GPIO_INT_RAWSTATUS_INT_RAWSTATUS_SHIFT (0U) +#define GPIO_INT_RAWSTATUS_INT_RAWSTATUS_MASK (0xFFFFFFFFU << GPIO_INT_RAWSTATUS_INT_RAWSTATUS_SHIFT) /* 0xFFFFFFFF */ +/* PORT_EOI_L */ +#define GPIO_PORT_EOI_L_OFFSET (0x60U) +#define GPIO_PORT_EOI_L_PORT_EOI_LOW_SHIFT (0U) +#define GPIO_PORT_EOI_L_PORT_EOI_LOW_MASK (0xFFFFU << GPIO_PORT_EOI_L_PORT_EOI_LOW_SHIFT) /* 0x0000FFFF */ +/* PORT_EOI_H */ +#define GPIO_PORT_EOI_H_OFFSET (0x64U) +#define GPIO_PORT_EOI_H_PORT_EOI_HIGH_SHIFT (0U) +#define GPIO_PORT_EOI_H_PORT_EOI_HIGH_MASK (0xFFFFU << GPIO_PORT_EOI_H_PORT_EOI_HIGH_SHIFT) /* 0x0000FFFF */ +/* EXT_PORT */ +#define GPIO_EXT_PORT_OFFSET (0x70U) +#define GPIO_EXT_PORT (0x0U) +#define GPIO_EXT_PORT_EXT_PORT_SHIFT (0U) +#define GPIO_EXT_PORT_EXT_PORT_MASK (0xFFFFFFFFU << GPIO_EXT_PORT_EXT_PORT_SHIFT) /* 0xFFFFFFFF */ +/* VER_ID */ +#define GPIO_VER_ID_OFFSET (0x78U) +#define GPIO_VER_ID (0x101157CU) +#define GPIO_VER_ID_VER_ID_SHIFT (0U) +#define GPIO_VER_ID_VER_ID_MASK (0xFFFFFFFFU << GPIO_VER_ID_VER_ID_SHIFT) /* 0xFFFFFFFF */ +/******************************************PWM*******************************************/ +/* PWM0_CNT */ +#define PWM_PWM0_CNT_OFFSET (0x0U) +#define PWM_PWM0_CNT (0x0U) +#define PWM_PWM0_CNT_CNT_SHIFT (0U) +#define PWM_PWM0_CNT_CNT_MASK (0xFFFFFFFFU << PWM_PWM0_CNT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PWM0_PERIOD_HPR */ +#define PWM_PWM0_PERIOD_HPR_OFFSET (0x4U) +#define PWM_PWM0_PERIOD_HPR_PERIOD_HPR_SHIFT (0U) +#define PWM_PWM0_PERIOD_HPR_PERIOD_HPR_MASK (0xFFFFFFFFU << PWM_PWM0_PERIOD_HPR_PERIOD_HPR_SHIFT) /* 0xFFFFFFFF */ +/* PWM0_DUTY_LPR */ +#define PWM_PWM0_DUTY_LPR_OFFSET (0x8U) +#define PWM_PWM0_DUTY_LPR_DUTY_LPR_SHIFT (0U) +#define PWM_PWM0_DUTY_LPR_DUTY_LPR_MASK (0xFFFFFFFFU << PWM_PWM0_DUTY_LPR_DUTY_LPR_SHIFT) /* 0xFFFFFFFF */ +/* PWM0_CTRL */ +#define PWM_PWM0_CTRL_OFFSET (0xCU) +#define PWM_PWM0_CTRL_PWM_EN_SHIFT (0U) +#define PWM_PWM0_CTRL_PWM_EN_MASK (0x1U << PWM_PWM0_CTRL_PWM_EN_SHIFT) /* 0x00000001 */ +#define PWM_PWM0_CTRL_PWM_MODE_SHIFT (1U) +#define PWM_PWM0_CTRL_PWM_MODE_MASK (0x3U << PWM_PWM0_CTRL_PWM_MODE_SHIFT) /* 0x00000006 */ +#define PWM_PWM0_CTRL_DUTY_POL_SHIFT (3U) +#define PWM_PWM0_CTRL_DUTY_POL_MASK (0x1U << PWM_PWM0_CTRL_DUTY_POL_SHIFT) /* 0x00000008 */ +#define PWM_PWM0_CTRL_INACTIVE_POL_SHIFT (4U) +#define PWM_PWM0_CTRL_INACTIVE_POL_MASK (0x1U << PWM_PWM0_CTRL_INACTIVE_POL_SHIFT) /* 0x00000010 */ +#define PWM_PWM0_CTRL_OUTPUT_MODE_SHIFT (5U) +#define PWM_PWM0_CTRL_OUTPUT_MODE_MASK (0x1U << PWM_PWM0_CTRL_OUTPUT_MODE_SHIFT) /* 0x00000020 */ +#define PWM_PWM0_CTRL_CONLOCK_SHIFT (6U) +#define PWM_PWM0_CTRL_CONLOCK_MASK (0x1U << PWM_PWM0_CTRL_CONLOCK_SHIFT) /* 0x00000040 */ +#define PWM_PWM0_CTRL_CH_CNT_EN_SHIFT (7U) +#define PWM_PWM0_CTRL_CH_CNT_EN_MASK (0x1U << PWM_PWM0_CTRL_CH_CNT_EN_SHIFT) /* 0x00000080 */ +#define PWM_PWM0_CTRL_FORCE_CLK_EN_SHIFT (8U) +#define PWM_PWM0_CTRL_FORCE_CLK_EN_MASK (0x1U << PWM_PWM0_CTRL_FORCE_CLK_EN_SHIFT) /* 0x00000100 */ +#define PWM_PWM0_CTRL_CLK_SEL_SHIFT (9U) +#define PWM_PWM0_CTRL_CLK_SEL_MASK (0x1U << PWM_PWM0_CTRL_CLK_SEL_SHIFT) /* 0x00000200 */ +#define PWM_PWM0_CTRL_CLK_SRC_SEL_SHIFT (10U) +#define PWM_PWM0_CTRL_CLK_SRC_SEL_MASK (0x1U << PWM_PWM0_CTRL_CLK_SRC_SEL_SHIFT) /* 0x00000400 */ +#define PWM_PWM0_CTRL_PRESCALE_SHIFT (12U) +#define PWM_PWM0_CTRL_PRESCALE_MASK (0x7U << PWM_PWM0_CTRL_PRESCALE_SHIFT) /* 0x00007000 */ +#define PWM_PWM0_CTRL_SCALE_SHIFT (16U) +#define PWM_PWM0_CTRL_SCALE_MASK (0xFFU << PWM_PWM0_CTRL_SCALE_SHIFT) /* 0x00FF0000 */ +#define PWM_PWM0_CTRL_RPT_SHIFT (24U) +#define PWM_PWM0_CTRL_RPT_MASK (0xFFU << PWM_PWM0_CTRL_RPT_SHIFT) /* 0xFF000000 */ +/* PWM1_CNT */ +#define PWM_PWM1_CNT_OFFSET (0x10U) +#define PWM_PWM1_CNT (0x0U) +#define PWM_PWM1_CNT_CNT_SHIFT (0U) +#define PWM_PWM1_CNT_CNT_MASK (0xFFFFFFFFU << PWM_PWM1_CNT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PWM1_PERIOD_HPR */ +#define PWM_PWM1_PERIOD_HPR_OFFSET (0x14U) +#define PWM_PWM1_PERIOD_HPR_PERIOD_HPR_SHIFT (0U) +#define PWM_PWM1_PERIOD_HPR_PERIOD_HPR_MASK (0xFFFFFFFFU << PWM_PWM1_PERIOD_HPR_PERIOD_HPR_SHIFT) /* 0xFFFFFFFF */ +/* PWM1_DUTY_LPR */ +#define PWM_PWM1_DUTY_LPR_OFFSET (0x18U) +#define PWM_PWM1_DUTY_LPR_DUTY_LPR_SHIFT (0U) +#define PWM_PWM1_DUTY_LPR_DUTY_LPR_MASK (0xFFFFFFFFU << PWM_PWM1_DUTY_LPR_DUTY_LPR_SHIFT) /* 0xFFFFFFFF */ +/* PWM1_CTRL */ +#define PWM_PWM1_CTRL_OFFSET (0x1CU) +#define PWM_PWM1_CTRL_PWM_EN_SHIFT (0U) +#define PWM_PWM1_CTRL_PWM_EN_MASK (0x1U << PWM_PWM1_CTRL_PWM_EN_SHIFT) /* 0x00000001 */ +#define PWM_PWM1_CTRL_PWM_MODE_SHIFT (1U) +#define PWM_PWM1_CTRL_PWM_MODE_MASK (0x3U << PWM_PWM1_CTRL_PWM_MODE_SHIFT) /* 0x00000006 */ +#define PWM_PWM1_CTRL_DUTY_POL_SHIFT (3U) +#define PWM_PWM1_CTRL_DUTY_POL_MASK (0x1U << PWM_PWM1_CTRL_DUTY_POL_SHIFT) /* 0x00000008 */ +#define PWM_PWM1_CTRL_INACTIVE_POL_SHIFT (4U) +#define PWM_PWM1_CTRL_INACTIVE_POL_MASK (0x1U << PWM_PWM1_CTRL_INACTIVE_POL_SHIFT) /* 0x00000010 */ +#define PWM_PWM1_CTRL_OUTPUT_MODE_SHIFT (5U) +#define PWM_PWM1_CTRL_OUTPUT_MODE_MASK (0x1U << PWM_PWM1_CTRL_OUTPUT_MODE_SHIFT) /* 0x00000020 */ +#define PWM_PWM1_CTRL_CONLOCK_SHIFT (6U) +#define PWM_PWM1_CTRL_CONLOCK_MASK (0x1U << PWM_PWM1_CTRL_CONLOCK_SHIFT) /* 0x00000040 */ +#define PWM_PWM1_CTRL_CH_CNT_EN_SHIFT (7U) +#define PWM_PWM1_CTRL_CH_CNT_EN_MASK (0x1U << PWM_PWM1_CTRL_CH_CNT_EN_SHIFT) /* 0x00000080 */ +#define PWM_PWM1_CTRL_FORCE_CLK_EN_SHIFT (8U) +#define PWM_PWM1_CTRL_FORCE_CLK_EN_MASK (0x1U << PWM_PWM1_CTRL_FORCE_CLK_EN_SHIFT) /* 0x00000100 */ +#define PWM_PWM1_CTRL_CLK_SEL_SHIFT (9U) +#define PWM_PWM1_CTRL_CLK_SEL_MASK (0x1U << PWM_PWM1_CTRL_CLK_SEL_SHIFT) /* 0x00000200 */ +#define PWM_PWM1_CTRL_CLK_SRC_SEL_SHIFT (10U) +#define PWM_PWM1_CTRL_CLK_SRC_SEL_MASK (0x1U << PWM_PWM1_CTRL_CLK_SRC_SEL_SHIFT) /* 0x00000400 */ +#define PWM_PWM1_CTRL_PRESCALE_SHIFT (12U) +#define PWM_PWM1_CTRL_PRESCALE_MASK (0x7U << PWM_PWM1_CTRL_PRESCALE_SHIFT) /* 0x00007000 */ +#define PWM_PWM1_CTRL_SCALE_SHIFT (16U) +#define PWM_PWM1_CTRL_SCALE_MASK (0xFFU << PWM_PWM1_CTRL_SCALE_SHIFT) /* 0x00FF0000 */ +#define PWM_PWM1_CTRL_RPT_SHIFT (24U) +#define PWM_PWM1_CTRL_RPT_MASK (0xFFU << PWM_PWM1_CTRL_RPT_SHIFT) /* 0xFF000000 */ +/* PWM2_CNT */ +#define PWM_PWM2_CNT_OFFSET (0x20U) +#define PWM_PWM2_CNT (0x0U) +#define PWM_PWM2_CNT_CNT_SHIFT (0U) +#define PWM_PWM2_CNT_CNT_MASK (0xFFFFFFFFU << PWM_PWM2_CNT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PWM2_PERIOD_HPR */ +#define PWM_PWM2_PERIOD_HPR_OFFSET (0x24U) +#define PWM_PWM2_PERIOD_HPR_PERIOD_HPR_SHIFT (0U) +#define PWM_PWM2_PERIOD_HPR_PERIOD_HPR_MASK (0xFFFFFFFFU << PWM_PWM2_PERIOD_HPR_PERIOD_HPR_SHIFT) /* 0xFFFFFFFF */ +/* PWM2_DUTY_LPR */ +#define PWM_PWM2_DUTY_LPR_OFFSET (0x28U) +#define PWM_PWM2_DUTY_LPR_DUTY_LPR_SHIFT (0U) +#define PWM_PWM2_DUTY_LPR_DUTY_LPR_MASK (0xFFFFFFFFU << PWM_PWM2_DUTY_LPR_DUTY_LPR_SHIFT) /* 0xFFFFFFFF */ +/* PWM2_CTRL */ +#define PWM_PWM2_CTRL_OFFSET (0x2CU) +#define PWM_PWM2_CTRL_PWM_EN_SHIFT (0U) +#define PWM_PWM2_CTRL_PWM_EN_MASK (0x1U << PWM_PWM2_CTRL_PWM_EN_SHIFT) /* 0x00000001 */ +#define PWM_PWM2_CTRL_PWM_MODE_SHIFT (1U) +#define PWM_PWM2_CTRL_PWM_MODE_MASK (0x3U << PWM_PWM2_CTRL_PWM_MODE_SHIFT) /* 0x00000006 */ +#define PWM_PWM2_CTRL_DUTY_POL_SHIFT (3U) +#define PWM_PWM2_CTRL_DUTY_POL_MASK (0x1U << PWM_PWM2_CTRL_DUTY_POL_SHIFT) /* 0x00000008 */ +#define PWM_PWM2_CTRL_INACTIVE_POL_SHIFT (4U) +#define PWM_PWM2_CTRL_INACTIVE_POL_MASK (0x1U << PWM_PWM2_CTRL_INACTIVE_POL_SHIFT) /* 0x00000010 */ +#define PWM_PWM2_CTRL_OUTPUT_MODE_SHIFT (5U) +#define PWM_PWM2_CTRL_OUTPUT_MODE_MASK (0x1U << PWM_PWM2_CTRL_OUTPUT_MODE_SHIFT) /* 0x00000020 */ +#define PWM_PWM2_CTRL_CONLOCK_SHIFT (6U) +#define PWM_PWM2_CTRL_CONLOCK_MASK (0x1U << PWM_PWM2_CTRL_CONLOCK_SHIFT) /* 0x00000040 */ +#define PWM_PWM2_CTRL_CH_CNT_EN_SHIFT (7U) +#define PWM_PWM2_CTRL_CH_CNT_EN_MASK (0x1U << PWM_PWM2_CTRL_CH_CNT_EN_SHIFT) /* 0x00000080 */ +#define PWM_PWM2_CTRL_FORCE_CLK_EN_SHIFT (8U) +#define PWM_PWM2_CTRL_FORCE_CLK_EN_MASK (0x1U << PWM_PWM2_CTRL_FORCE_CLK_EN_SHIFT) /* 0x00000100 */ +#define PWM_PWM2_CTRL_CLK_SEL_SHIFT (9U) +#define PWM_PWM2_CTRL_CLK_SEL_MASK (0x1U << PWM_PWM2_CTRL_CLK_SEL_SHIFT) /* 0x00000200 */ +#define PWM_PWM2_CTRL_CLK_SRC_SEL_SHIFT (10U) +#define PWM_PWM2_CTRL_CLK_SRC_SEL_MASK (0x1U << PWM_PWM2_CTRL_CLK_SRC_SEL_SHIFT) /* 0x00000400 */ +#define PWM_PWM2_CTRL_PRESCALE_SHIFT (12U) +#define PWM_PWM2_CTRL_PRESCALE_MASK (0x7U << PWM_PWM2_CTRL_PRESCALE_SHIFT) /* 0x00007000 */ +#define PWM_PWM2_CTRL_SCALE_SHIFT (16U) +#define PWM_PWM2_CTRL_SCALE_MASK (0xFFU << PWM_PWM2_CTRL_SCALE_SHIFT) /* 0x00FF0000 */ +#define PWM_PWM2_CTRL_RPT_SHIFT (24U) +#define PWM_PWM2_CTRL_RPT_MASK (0xFFU << PWM_PWM2_CTRL_RPT_SHIFT) /* 0xFF000000 */ +/* PWM3_CNT */ +#define PWM_PWM3_CNT_OFFSET (0x30U) +#define PWM_PWM3_CNT (0x0U) +#define PWM_PWM3_CNT_CNT_SHIFT (0U) +#define PWM_PWM3_CNT_CNT_MASK (0xFFFFFFFFU << PWM_PWM3_CNT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PWM3_PERIOD_HPR */ +#define PWM_PWM3_PERIOD_HPR_OFFSET (0x34U) +#define PWM_PWM3_PERIOD_HPR_PERIOD_HPR_SHIFT (0U) +#define PWM_PWM3_PERIOD_HPR_PERIOD_HPR_MASK (0xFFFFFFFFU << PWM_PWM3_PERIOD_HPR_PERIOD_HPR_SHIFT) /* 0xFFFFFFFF */ +/* PWM3_DUTY_LPR */ +#define PWM_PWM3_DUTY_LPR_OFFSET (0x38U) +#define PWM_PWM3_DUTY_LPR_DUTY_LPR_SHIFT (0U) +#define PWM_PWM3_DUTY_LPR_DUTY_LPR_MASK (0xFFFFFFFFU << PWM_PWM3_DUTY_LPR_DUTY_LPR_SHIFT) /* 0xFFFFFFFF */ +/* PWM3_CTRL */ +#define PWM_PWM3_CTRL_OFFSET (0x3CU) +#define PWM_PWM3_CTRL_PWM_EN_SHIFT (0U) +#define PWM_PWM3_CTRL_PWM_EN_MASK (0x1U << PWM_PWM3_CTRL_PWM_EN_SHIFT) /* 0x00000001 */ +#define PWM_PWM3_CTRL_PWM_MODE_SHIFT (1U) +#define PWM_PWM3_CTRL_PWM_MODE_MASK (0x3U << PWM_PWM3_CTRL_PWM_MODE_SHIFT) /* 0x00000006 */ +#define PWM_PWM3_CTRL_DUTY_POL_SHIFT (3U) +#define PWM_PWM3_CTRL_DUTY_POL_MASK (0x1U << PWM_PWM3_CTRL_DUTY_POL_SHIFT) /* 0x00000008 */ +#define PWM_PWM3_CTRL_INACTIVE_POL_SHIFT (4U) +#define PWM_PWM3_CTRL_INACTIVE_POL_MASK (0x1U << PWM_PWM3_CTRL_INACTIVE_POL_SHIFT) /* 0x00000010 */ +#define PWM_PWM3_CTRL_OUTPUT_MODE_SHIFT (5U) +#define PWM_PWM3_CTRL_OUTPUT_MODE_MASK (0x1U << PWM_PWM3_CTRL_OUTPUT_MODE_SHIFT) /* 0x00000020 */ +#define PWM_PWM3_CTRL_CONLOCK_SHIFT (6U) +#define PWM_PWM3_CTRL_CONLOCK_MASK (0x1U << PWM_PWM3_CTRL_CONLOCK_SHIFT) /* 0x00000040 */ +#define PWM_PWM3_CTRL_CH_CNT_EN_SHIFT (7U) +#define PWM_PWM3_CTRL_CH_CNT_EN_MASK (0x1U << PWM_PWM3_CTRL_CH_CNT_EN_SHIFT) /* 0x00000080 */ +#define PWM_PWM3_CTRL_FORCE_CLK_EN_SHIFT (8U) +#define PWM_PWM3_CTRL_FORCE_CLK_EN_MASK (0x1U << PWM_PWM3_CTRL_FORCE_CLK_EN_SHIFT) /* 0x00000100 */ +#define PWM_PWM3_CTRL_CLK_SEL_SHIFT (9U) +#define PWM_PWM3_CTRL_CLK_SEL_MASK (0x1U << PWM_PWM3_CTRL_CLK_SEL_SHIFT) /* 0x00000200 */ +#define PWM_PWM3_CTRL_CLK_SRC_SEL_SHIFT (10U) +#define PWM_PWM3_CTRL_CLK_SRC_SEL_MASK (0x1U << PWM_PWM3_CTRL_CLK_SRC_SEL_SHIFT) /* 0x00000400 */ +#define PWM_PWM3_CTRL_PRESCALE_SHIFT (12U) +#define PWM_PWM3_CTRL_PRESCALE_MASK (0x7U << PWM_PWM3_CTRL_PRESCALE_SHIFT) /* 0x00007000 */ +#define PWM_PWM3_CTRL_SCALE_SHIFT (16U) +#define PWM_PWM3_CTRL_SCALE_MASK (0xFFU << PWM_PWM3_CTRL_SCALE_SHIFT) /* 0x00FF0000 */ +#define PWM_PWM3_CTRL_RPT_SHIFT (24U) +#define PWM_PWM3_CTRL_RPT_MASK (0xFFU << PWM_PWM3_CTRL_RPT_SHIFT) /* 0xFF000000 */ +/* INTSTS */ +#define PWM_INTSTS_OFFSET (0x40U) +#define PWM_INTSTS_CH0_INTSTS_SHIFT (0U) +#define PWM_INTSTS_CH0_INTSTS_MASK (0x1U << PWM_INTSTS_CH0_INTSTS_SHIFT) /* 0x00000001 */ +#define PWM_INTSTS_CH1_INTSTS_SHIFT (1U) +#define PWM_INTSTS_CH1_INTSTS_MASK (0x1U << PWM_INTSTS_CH1_INTSTS_SHIFT) /* 0x00000002 */ +#define PWM_INTSTS_CH2_INTSTS_SHIFT (2U) +#define PWM_INTSTS_CH2_INTSTS_MASK (0x1U << PWM_INTSTS_CH2_INTSTS_SHIFT) /* 0x00000004 */ +#define PWM_INTSTS_CH3_INTSTS_SHIFT (3U) +#define PWM_INTSTS_CH3_INTSTS_MASK (0x1U << PWM_INTSTS_CH3_INTSTS_SHIFT) /* 0x00000008 */ +#define PWM_INTSTS_CH0_PWR_INTSTS_SHIFT (4U) +#define PWM_INTSTS_CH0_PWR_INTSTS_MASK (0x1U << PWM_INTSTS_CH0_PWR_INTSTS_SHIFT) /* 0x00000010 */ +#define PWM_INTSTS_CH1_PWR_INTSTS_SHIFT (5U) +#define PWM_INTSTS_CH1_PWR_INTSTS_MASK (0x1U << PWM_INTSTS_CH1_PWR_INTSTS_SHIFT) /* 0x00000020 */ +#define PWM_INTSTS_CH2_PWR_INTSTS_SHIFT (6U) +#define PWM_INTSTS_CH2_PWR_INTSTS_MASK (0x1U << PWM_INTSTS_CH2_PWR_INTSTS_SHIFT) /* 0x00000040 */ +#define PWM_INTSTS_CH3_PWR_INTSTS_SHIFT (7U) +#define PWM_INTSTS_CH3_PWR_INTSTS_MASK (0x1U << PWM_INTSTS_CH3_PWR_INTSTS_SHIFT) /* 0x00000080 */ +#define PWM_INTSTS_CH0_POL_SHIFT (8U) +#define PWM_INTSTS_CH0_POL_MASK (0x1U << PWM_INTSTS_CH0_POL_SHIFT) /* 0x00000100 */ +#define PWM_INTSTS_CH1_POL_SHIFT (9U) +#define PWM_INTSTS_CH1_POL_MASK (0x1U << PWM_INTSTS_CH1_POL_SHIFT) /* 0x00000200 */ +#define PWM_INTSTS_CH2_POL_SHIFT (10U) +#define PWM_INTSTS_CH2_POL_MASK (0x1U << PWM_INTSTS_CH2_POL_SHIFT) /* 0x00000400 */ +#define PWM_INTSTS_CH3_POL_SHIFT (11U) +#define PWM_INTSTS_CH3_POL_MASK (0x1U << PWM_INTSTS_CH3_POL_SHIFT) /* 0x00000800 */ +/* INT_EN */ +#define PWM_INT_EN_OFFSET (0x44U) +#define PWM_INT_EN_CH0_INT_EN_SHIFT (0U) +#define PWM_INT_EN_CH0_INT_EN_MASK (0x1U << PWM_INT_EN_CH0_INT_EN_SHIFT) /* 0x00000001 */ +#define PWM_INT_EN_CH1_INT_EN_SHIFT (1U) +#define PWM_INT_EN_CH1_INT_EN_MASK (0x1U << PWM_INT_EN_CH1_INT_EN_SHIFT) /* 0x00000002 */ +#define PWM_INT_EN_CH2_INT_EN_SHIFT (2U) +#define PWM_INT_EN_CH2_INT_EN_MASK (0x1U << PWM_INT_EN_CH2_INT_EN_SHIFT) /* 0x00000004 */ +#define PWM_INT_EN_CH3_INT_EN_SHIFT (3U) +#define PWM_INT_EN_CH3_INT_EN_MASK (0x1U << PWM_INT_EN_CH3_INT_EN_SHIFT) /* 0x00000008 */ +#define PWM_INT_EN_CH0_PWR_INT_EN_SHIFT (4U) +#define PWM_INT_EN_CH0_PWR_INT_EN_MASK (0x1U << PWM_INT_EN_CH0_PWR_INT_EN_SHIFT) /* 0x00000010 */ +#define PWM_INT_EN_CH1_PWR_INT_EN_SHIFT (5U) +#define PWM_INT_EN_CH1_PWR_INT_EN_MASK (0x1U << PWM_INT_EN_CH1_PWR_INT_EN_SHIFT) /* 0x00000020 */ +#define PWM_INT_EN_CH2_PWR_INT_EN_SHIFT (6U) +#define PWM_INT_EN_CH2_PWR_INT_EN_MASK (0x1U << PWM_INT_EN_CH2_PWR_INT_EN_SHIFT) /* 0x00000040 */ +#define PWM_INT_EN_CH3_PWR_INT_EN_SHIFT (7U) +#define PWM_INT_EN_CH3_PWR_INT_EN_MASK (0x1U << PWM_INT_EN_CH3_PWR_INT_EN_SHIFT) /* 0x00000080 */ +/* FIFO_CTRL */ +#define PWM_FIFO_CTRL_OFFSET (0x50U) +#define PWM_FIFO_CTRL_FIFO_MODE_SEL_SHIFT (0U) +#define PWM_FIFO_CTRL_FIFO_MODE_SEL_MASK (0x1U << PWM_FIFO_CTRL_FIFO_MODE_SEL_SHIFT) /* 0x00000001 */ +#define PWM_FIFO_CTRL_FULL_INT_EN_SHIFT (1U) +#define PWM_FIFO_CTRL_FULL_INT_EN_MASK (0x1U << PWM_FIFO_CTRL_FULL_INT_EN_SHIFT) /* 0x00000002 */ +#define PWM_FIFO_CTRL_OVERFLOW_INT_EN_SHIFT (2U) +#define PWM_FIFO_CTRL_OVERFLOW_INT_EN_MASK (0x1U << PWM_FIFO_CTRL_OVERFLOW_INT_EN_SHIFT) /* 0x00000004 */ +#define PWM_FIFO_CTRL_WATERMARK_INT_EN_SHIFT (3U) +#define PWM_FIFO_CTRL_WATERMARK_INT_EN_MASK (0x1U << PWM_FIFO_CTRL_WATERMARK_INT_EN_SHIFT) /* 0x00000008 */ +#define PWM_FIFO_CTRL_ALMOST_FULL_WATERMARK_SHIFT (4U) +#define PWM_FIFO_CTRL_ALMOST_FULL_WATERMARK_MASK (0x7U << PWM_FIFO_CTRL_ALMOST_FULL_WATERMARK_SHIFT) /* 0x00000070 */ +#define PWM_FIFO_CTRL_DMA_MODE_EN_SHIFT (8U) +#define PWM_FIFO_CTRL_DMA_MODE_EN_MASK (0x1U << PWM_FIFO_CTRL_DMA_MODE_EN_SHIFT) /* 0x00000100 */ +#define PWM_FIFO_CTRL_TIMEOUT_EN_SHIFT (9U) +#define PWM_FIFO_CTRL_TIMEOUT_EN_MASK (0x1U << PWM_FIFO_CTRL_TIMEOUT_EN_SHIFT) /* 0x00000200 */ +#define PWM_FIFO_CTRL_DMA_CH_SEL_EN_SHIFT (10U) +#define PWM_FIFO_CTRL_DMA_CH_SEL_EN_MASK (0x1U << PWM_FIFO_CTRL_DMA_CH_SEL_EN_SHIFT) /* 0x00000400 */ +#define PWM_FIFO_CTRL_DMA_CH_SEL_SHIFT (12U) +#define PWM_FIFO_CTRL_DMA_CH_SEL_MASK (0x3U << PWM_FIFO_CTRL_DMA_CH_SEL_SHIFT) /* 0x00003000 */ +/* FIFO_INTSTS */ +#define PWM_FIFO_INTSTS_OFFSET (0x54U) +#define PWM_FIFO_INTSTS_FIFO_FULL_INTSTS_SHIFT (0U) +#define PWM_FIFO_INTSTS_FIFO_FULL_INTSTS_MASK (0x1U << PWM_FIFO_INTSTS_FIFO_FULL_INTSTS_SHIFT) /* 0x00000001 */ +#define PWM_FIFO_INTSTS_FIFO_OVERFLOW_INTSTS_SHIFT (1U) +#define PWM_FIFO_INTSTS_FIFO_OVERFLOW_INTSTS_MASK (0x1U << PWM_FIFO_INTSTS_FIFO_OVERFLOW_INTSTS_SHIFT) /* 0x00000002 */ +#define PWM_FIFO_INTSTS_FIFO_WATERMARK_FULL_INTSTS_SHIFT (2U) +#define PWM_FIFO_INTSTS_FIFO_WATERMARK_FULL_INTSTS_MASK (0x1U << PWM_FIFO_INTSTS_FIFO_WATERMARK_FULL_INTSTS_SHIFT) /* 0x00000004 */ +#define PWM_FIFO_INTSTS_TIMIEOUT_INTSTS_SHIFT (3U) +#define PWM_FIFO_INTSTS_TIMIEOUT_INTSTS_MASK (0x1U << PWM_FIFO_INTSTS_TIMIEOUT_INTSTS_SHIFT) /* 0x00000008 */ +#define PWM_FIFO_INTSTS_FIFO_EMPTY_STATUS_SHIFT (4U) +#define PWM_FIFO_INTSTS_FIFO_EMPTY_STATUS_MASK (0x1U << PWM_FIFO_INTSTS_FIFO_EMPTY_STATUS_SHIFT) /* 0x00000010 */ +/* FIFO_TOUTTHR */ +#define PWM_FIFO_TOUTTHR_OFFSET (0x58U) +#define PWM_FIFO_TOUTTHR_TIMEOUT_THRESHOLD_SHIFT (0U) +#define PWM_FIFO_TOUTTHR_TIMEOUT_THRESHOLD_MASK (0xFFFFFU << PWM_FIFO_TOUTTHR_TIMEOUT_THRESHOLD_SHIFT) /* 0x000FFFFF */ +/* VERSION_ID */ +#define PWM_VERSION_ID_OFFSET (0x5CU) +#define PWM_VERSION_ID_SVN_VERSION_SHIFT (0U) +#define PWM_VERSION_ID_SVN_VERSION_MASK (0xFFFFU << PWM_VERSION_ID_SVN_VERSION_SHIFT) /* 0x0000FFFF */ +#define PWM_VERSION_ID_MINOR_VERSION_SHIFT (16U) +#define PWM_VERSION_ID_MINOR_VERSION_MASK (0xFFU << PWM_VERSION_ID_MINOR_VERSION_SHIFT) /* 0x00FF0000 */ +#define PWM_VERSION_ID_MAIN_VERSION_SHIFT (24U) +#define PWM_VERSION_ID_MAIN_VERSION_MASK (0xFFU << PWM_VERSION_ID_MAIN_VERSION_SHIFT) /* 0xFF000000 */ +/* FIFO */ +#define PWM_FIFO_OFFSET (0x60U) +#define PWM_FIFO (0x0U) +#define PWM_FIFO_CYCLE_CNT_SHIFT (0U) +#define PWM_FIFO_CYCLE_CNT_MASK (0x7FFFFFFFU << PWM_FIFO_CYCLE_CNT_SHIFT) /* 0x7FFFFFFF */ +#define PWM_FIFO_POL_SHIFT (31U) +#define PWM_FIFO_POL_MASK (0x1U << PWM_FIFO_POL_SHIFT) /* 0x80000000 */ +/* PWRMATCH_CTRL */ +#define PWM_PWRMATCH_CTRL_OFFSET (0x80U) +#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_ENABLE_SHIFT (3U) +#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_ENABLE_MASK (0x1U << PWM_PWRMATCH_CTRL_CH3_PWRKEY_ENABLE_SHIFT) /* 0x00000008 */ +#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_POLARITY_SHIFT (7U) +#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_POLARITY_MASK (0x1U << PWM_PWRMATCH_CTRL_CH3_PWRKEY_POLARITY_SHIFT) /* 0x00000080 */ +#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_CAPTURE_CTRL_SHIFT (11U) +#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_CAPTURE_CTRL_MASK (0x1U << PWM_PWRMATCH_CTRL_CH3_PWRKEY_CAPTURE_CTRL_SHIFT) /* 0x00000800 */ +#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_INT_CTRL_SHIFT (15U) +#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_INT_CTRL_MASK (0x1U << PWM_PWRMATCH_CTRL_CH3_PWRKEY_INT_CTRL_SHIFT) /* 0x00008000 */ +/* PWRMATCH_LPRE */ +#define PWM_PWRMATCH_LPRE_OFFSET (0x84U) +#define PWM_PWRMATCH_LPRE_CNT_MIN_SHIFT (0U) +#define PWM_PWRMATCH_LPRE_CNT_MIN_MASK (0xFFFFU << PWM_PWRMATCH_LPRE_CNT_MIN_SHIFT) /* 0x0000FFFF */ +#define PWM_PWRMATCH_LPRE_CNT_MAX_SHIFT (16U) +#define PWM_PWRMATCH_LPRE_CNT_MAX_MASK (0xFFFFU << PWM_PWRMATCH_LPRE_CNT_MAX_SHIFT) /* 0xFFFF0000 */ +/* PWRMATCH_HPRE */ +#define PWM_PWRMATCH_HPRE_OFFSET (0x88U) +#define PWM_PWRMATCH_HPRE_CNT_MIN_SHIFT (0U) +#define PWM_PWRMATCH_HPRE_CNT_MIN_MASK (0xFFFFU << PWM_PWRMATCH_HPRE_CNT_MIN_SHIFT) /* 0x0000FFFF */ +#define PWM_PWRMATCH_HPRE_CNT_MAX_SHIFT (16U) +#define PWM_PWRMATCH_HPRE_CNT_MAX_MASK (0xFFFFU << PWM_PWRMATCH_HPRE_CNT_MAX_SHIFT) /* 0xFFFF0000 */ +/* PWRMATCH_LD */ +#define PWM_PWRMATCH_LD_OFFSET (0x8CU) +#define PWM_PWRMATCH_LD_CNT_MIN_SHIFT (0U) +#define PWM_PWRMATCH_LD_CNT_MIN_MASK (0xFFFFU << PWM_PWRMATCH_LD_CNT_MIN_SHIFT) /* 0x0000FFFF */ +#define PWM_PWRMATCH_LD_CNT_MAX_SHIFT (16U) +#define PWM_PWRMATCH_LD_CNT_MAX_MASK (0xFFFFU << PWM_PWRMATCH_LD_CNT_MAX_SHIFT) /* 0xFFFF0000 */ +/* PWRMATCH_HD_ZERO */ +#define PWM_PWRMATCH_HD_ZERO_OFFSET (0x90U) +#define PWM_PWRMATCH_HD_ZERO_CNT_MIN_SHIFT (0U) +#define PWM_PWRMATCH_HD_ZERO_CNT_MIN_MASK (0xFFFFU << PWM_PWRMATCH_HD_ZERO_CNT_MIN_SHIFT) /* 0x0000FFFF */ +#define PWM_PWRMATCH_HD_ZERO_CNT_MAX_SHIFT (16U) +#define PWM_PWRMATCH_HD_ZERO_CNT_MAX_MASK (0xFFFFU << PWM_PWRMATCH_HD_ZERO_CNT_MAX_SHIFT) /* 0xFFFF0000 */ +/* PWRMATCH_HD_ONE */ +#define PWM_PWRMATCH_HD_ONE_OFFSET (0x94U) +#define PWM_PWRMATCH_HD_ONE_CNT_MIN_SHIFT (0U) +#define PWM_PWRMATCH_HD_ONE_CNT_MIN_MASK (0xFFFFU << PWM_PWRMATCH_HD_ONE_CNT_MIN_SHIFT) /* 0x0000FFFF */ +#define PWM_PWRMATCH_HD_ONE_CNT_MAX_SHIFT (16U) +#define PWM_PWRMATCH_HD_ONE_CNT_MAX_MASK (0xFFFFU << PWM_PWRMATCH_HD_ONE_CNT_MAX_SHIFT) /* 0xFFFF0000 */ +/* PWRMATCH_VALUE0 */ +#define PWM_PWRMATCH_VALUE0_OFFSET (0x98U) +#define PWM_PWRMATCH_VALUE0_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE0_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE0_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE1 */ +#define PWM_PWRMATCH_VALUE1_OFFSET (0x9CU) +#define PWM_PWRMATCH_VALUE1_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE1_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE1_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE2 */ +#define PWM_PWRMATCH_VALUE2_OFFSET (0xA0U) +#define PWM_PWRMATCH_VALUE2_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE2_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE2_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE3 */ +#define PWM_PWRMATCH_VALUE3_OFFSET (0xA4U) +#define PWM_PWRMATCH_VALUE3_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE3_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE3_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE4 */ +#define PWM_PWRMATCH_VALUE4_OFFSET (0xA8U) +#define PWM_PWRMATCH_VALUE4_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE4_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE4_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE5 */ +#define PWM_PWRMATCH_VALUE5_OFFSET (0xACU) +#define PWM_PWRMATCH_VALUE5_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE5_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE5_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE6 */ +#define PWM_PWRMATCH_VALUE6_OFFSET (0xB0U) +#define PWM_PWRMATCH_VALUE6_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE6_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE6_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE7 */ +#define PWM_PWRMATCH_VALUE7_OFFSET (0xB4U) +#define PWM_PWRMATCH_VALUE7_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE7_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE7_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE8 */ +#define PWM_PWRMATCH_VALUE8_OFFSET (0xB8U) +#define PWM_PWRMATCH_VALUE8_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE8_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE8_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE9 */ +#define PWM_PWRMATCH_VALUE9_OFFSET (0xBCU) +#define PWM_PWRMATCH_VALUE9_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE9_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE9_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWM3_PWRCAPTURE_VALUE */ +#define PWM_PWM3_PWRCAPTURE_VALUE_OFFSET (0xCCU) +#define PWM_PWM3_PWRCAPTURE_VALUE (0x0U) +#define PWM_PWM3_PWRCAPTURE_VALUE_PWRKEY_CAPTURE_VALUE_SHIFT (0U) +#define PWM_PWM3_PWRCAPTURE_VALUE_PWRKEY_CAPTURE_VALUE_MASK (0xFFFFFFFFU << PWM_PWM3_PWRCAPTURE_VALUE_PWRKEY_CAPTURE_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* FILTER_CTRL */ +#define PWM_FILTER_CTRL_OFFSET (0xD0U) +#define PWM_FILTER_CTRL_CH0_INPUT_FILTER_ENABLE_SHIFT (0U) +#define PWM_FILTER_CTRL_CH0_INPUT_FILTER_ENABLE_MASK (0x1U << PWM_FILTER_CTRL_CH0_INPUT_FILTER_ENABLE_SHIFT) /* 0x00000001 */ +#define PWM_FILTER_CTRL_CH1_INPUT_FILTER_ENABLE_SHIFT (1U) +#define PWM_FILTER_CTRL_CH1_INPUT_FILTER_ENABLE_MASK (0x1U << PWM_FILTER_CTRL_CH1_INPUT_FILTER_ENABLE_SHIFT) /* 0x00000002 */ +#define PWM_FILTER_CTRL_CH2_INPUT_FILTER_ENABLE_SHIFT (2U) +#define PWM_FILTER_CTRL_CH2_INPUT_FILTER_ENABLE_MASK (0x1U << PWM_FILTER_CTRL_CH2_INPUT_FILTER_ENABLE_SHIFT) /* 0x00000004 */ +#define PWM_FILTER_CTRL_CH3_INPUT_FILTER_ENABLE_SHIFT (3U) +#define PWM_FILTER_CTRL_CH3_INPUT_FILTER_ENABLE_MASK (0x1U << PWM_FILTER_CTRL_CH3_INPUT_FILTER_ENABLE_SHIFT) /* 0x00000008 */ +#define PWM_FILTER_CTRL_FILTER_NUMBER_SHIFT (4U) +#define PWM_FILTER_CTRL_FILTER_NUMBER_MASK (0x1FFU << PWM_FILTER_CTRL_FILTER_NUMBER_SHIFT) /* 0x00001FF0 */ +#define PWM_FILTER_CTRL_CH0_AND_CH3_SWITCH_EN_SHIFT (16U) +#define PWM_FILTER_CTRL_CH0_AND_CH3_SWITCH_EN_MASK (0x1U << PWM_FILTER_CTRL_CH0_AND_CH3_SWITCH_EN_SHIFT) /* 0x00010000 */ +#define PWM_FILTER_CTRL_CH1_AND_CH3_SWITCH_EN_SHIFT (17U) +#define PWM_FILTER_CTRL_CH1_AND_CH3_SWITCH_EN_MASK (0x1U << PWM_FILTER_CTRL_CH1_AND_CH3_SWITCH_EN_SHIFT) /* 0x00020000 */ +#define PWM_FILTER_CTRL_CH2_AND_CH3_SWITCH_EN_SHIFT (18U) +#define PWM_FILTER_CTRL_CH2_AND_CH3_SWITCH_EN_MASK (0x1U << PWM_FILTER_CTRL_CH2_AND_CH3_SWITCH_EN_SHIFT) /* 0x00040000 */ +/******************************************PMU*******************************************/ +/* VERSION */ +#define PMU_VERSION_OFFSET (0x0U) +#define PMU_VERSION (0x3003566U) +#define PMU_VERSION_VERSION_SHIFT (0U) +#define PMU_VERSION_VERSION_MASK (0xFFFFFFFFU << PMU_VERSION_VERSION_SHIFT) /* 0xFFFFFFFF */ +/* PWR_CON */ +#define PMU_PWR_CON_OFFSET (0x4U) +#define PMU_PWR_CON_POWERMODE_EN_SHIFT (0U) +#define PMU_PWR_CON_POWERMODE_EN_MASK (0x1U << PMU_PWR_CON_POWERMODE_EN_SHIFT) /* 0x00000001 */ +#define PMU_PWR_CON_DSU_BYPASS_SHIFT (1U) +#define PMU_PWR_CON_DSU_BYPASS_MASK (0x1U << PMU_PWR_CON_DSU_BYPASS_SHIFT) /* 0x00000002 */ +#define PMU_PWR_CON_RESERVED_SHIFT (2U) +#define PMU_PWR_CON_RESERVED_MASK (0x3U << PMU_PWR_CON_RESERVED_SHIFT) /* 0x0000000C */ +#define PMU_PWR_CON_BUS_BYPASS_SHIFT (4U) +#define PMU_PWR_CON_BUS_BYPASS_MASK (0x1U << PMU_PWR_CON_BUS_BYPASS_SHIFT) /* 0x00000010 */ +#define PMU_PWR_CON_DDR_BYPASS_SHIFT (5U) +#define PMU_PWR_CON_DDR_BYPASS_MASK (0x1U << PMU_PWR_CON_DDR_BYPASS_SHIFT) /* 0x00000020 */ +#define PMU_PWR_CON_PWRDN_BYPASS_SHIFT (6U) +#define PMU_PWR_CON_PWRDN_BYPASS_MASK (0x1U << PMU_PWR_CON_PWRDN_BYPASS_SHIFT) /* 0x00000040 */ +#define PMU_PWR_CON_CRU_BYPASS_SHIFT (7U) +#define PMU_PWR_CON_CRU_BYPASS_MASK (0x1U << PMU_PWR_CON_CRU_BYPASS_SHIFT) /* 0x00000080 */ +#define PMU_PWR_CON_CPU_BYPASS_SHIFT (8U) +#define PMU_PWR_CON_CPU_BYPASS_MASK (0xFU << PMU_PWR_CON_CPU_BYPASS_SHIFT) /* 0x00000F00 */ +#define PMU_PWR_CON_PMU_SLEEP_POL_SHIFT (15U) +#define PMU_PWR_CON_PMU_SLEEP_POL_MASK (0x1U << PMU_PWR_CON_PMU_SLEEP_POL_SHIFT) /* 0x00008000 */ +/* MAIN_PWR_STATE */ +#define PMU_MAIN_PWR_STATE_OFFSET (0x8U) +#define PMU_MAIN_PWR_STATE (0x0U) +#define PMU_MAIN_PWR_STATE_PMU_POWER_STATE_SHIFT (0U) +#define PMU_MAIN_PWR_STATE_PMU_POWER_STATE_MASK (0xFU << PMU_MAIN_PWR_STATE_PMU_POWER_STATE_SHIFT) /* 0x0000000F */ +/* INT_MASK_CON */ +#define PMU_INT_MASK_CON_OFFSET (0xCU) +#define PMU_INT_MASK_CON_GLB_INT_DISABLE_SHIFT (0U) +#define PMU_INT_MASK_CON_GLB_INT_DISABLE_MASK (0x1U << PMU_INT_MASK_CON_GLB_INT_DISABLE_SHIFT) /* 0x00000001 */ +#define PMU_INT_MASK_CON_WAKEUP_MCU_SFT_SHIFT (15U) +#define PMU_INT_MASK_CON_WAKEUP_MCU_SFT_MASK (0x1U << PMU_INT_MASK_CON_WAKEUP_MCU_SFT_SHIFT) /* 0x00008000 */ +/* WAKEUP_INT_CON */ +#define PMU_WAKEUP_INT_CON_OFFSET (0x10U) +#define PMU_WAKEUP_INT_CON_WAKEUP_CPU0_INT_EN_SHIFT (0U) +#define PMU_WAKEUP_INT_CON_WAKEUP_CPU0_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_CPU0_INT_EN_SHIFT) /* 0x00000001 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_CPU1_INT_EN_SHIFT (1U) +#define PMU_WAKEUP_INT_CON_WAKEUP_CPU1_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_CPU1_INT_EN_SHIFT) /* 0x00000002 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_CPU2_INT_EN_SHIFT (2U) +#define PMU_WAKEUP_INT_CON_WAKEUP_CPU2_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_CPU2_INT_EN_SHIFT) /* 0x00000004 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_CPU3_INT_EN_SHIFT (3U) +#define PMU_WAKEUP_INT_CON_WAKEUP_CPU3_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_CPU3_INT_EN_SHIFT) /* 0x00000008 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_GPIO0_INT_EN_SHIFT (4U) +#define PMU_WAKEUP_INT_CON_WAKEUP_GPIO0_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_GPIO0_INT_EN_SHIFT) /* 0x00000010 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_UART0_EN_SHIFT (5U) +#define PMU_WAKEUP_INT_CON_WAKEUP_UART0_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_UART0_EN_SHIFT) /* 0x00000020 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_SDMMC0_EN_SHIFT (6U) +#define PMU_WAKEUP_INT_CON_WAKEUP_SDMMC0_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_SDMMC0_EN_SHIFT) /* 0x00000040 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_SDMMC1_EN_SHIFT (7U) +#define PMU_WAKEUP_INT_CON_WAKEUP_SDMMC1_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_SDMMC1_EN_SHIFT) /* 0x00000080 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_SDMMC2_EN_SHIFT (8U) +#define PMU_WAKEUP_INT_CON_WAKEUP_SDMMC2_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_SDMMC2_EN_SHIFT) /* 0x00000100 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_USB_EN_SHIFT (9U) +#define PMU_WAKEUP_INT_CON_WAKEUP_USB_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_USB_EN_SHIFT) /* 0x00000200 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_PCIE_EN_SHIFT (10U) +#define PMU_WAKEUP_INT_CON_WAKEUP_PCIE_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_PCIE_EN_SHIFT) /* 0x00000400 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_VAD_EN_SHIFT (11U) +#define PMU_WAKEUP_INT_CON_WAKEUP_VAD_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_VAD_EN_SHIFT) /* 0x00000800 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_TIMER_EN_SHIFT (12U) +#define PMU_WAKEUP_INT_CON_WAKEUP_TIMER_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_TIMER_EN_SHIFT) /* 0x00001000 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_PWM0_EN_SHIFT (13U) +#define PMU_WAKEUP_INT_CON_WAKEUP_PWM0_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_PWM0_EN_SHIFT) /* 0x00002000 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_TIMEOUT_EN_SHIFT (14U) +#define PMU_WAKEUP_INT_CON_WAKEUP_TIMEOUT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_TIMEOUT_EN_SHIFT) /* 0x00004000 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_MCU_SFT_EN_SHIFT (15U) +#define PMU_WAKEUP_INT_CON_WAKEUP_MCU_SFT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_MCU_SFT_EN_SHIFT) /* 0x00008000 */ +/* WAKEUP_INT_ST */ +#define PMU_WAKEUP_INT_ST_OFFSET (0x14U) +#define PMU_WAKEUP_INT_ST (0x0U) +#define PMU_WAKEUP_INT_ST_WAKEUP_CPU0_INT_ST_SHIFT (0U) +#define PMU_WAKEUP_INT_ST_WAKEUP_CPU0_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_CPU0_INT_ST_SHIFT) /* 0x00000001 */ +#define PMU_WAKEUP_INT_ST_WAKEUP_CPU1_INT_ST_SHIFT (1U) +#define PMU_WAKEUP_INT_ST_WAKEUP_CPU1_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_CPU1_INT_ST_SHIFT) /* 0x00000002 */ +#define PMU_WAKEUP_INT_ST_WAKEUP_CPU2_INT_ST_SHIFT (2U) +#define PMU_WAKEUP_INT_ST_WAKEUP_CPU2_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_CPU2_INT_ST_SHIFT) /* 0x00000004 */ +#define PMU_WAKEUP_INT_ST_WAKEUP_CPU3_INT_ST_SHIFT (3U) +#define PMU_WAKEUP_INT_ST_WAKEUP_CPU3_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_CPU3_INT_ST_SHIFT) /* 0x00000008 */ +#define PMU_WAKEUP_INT_ST_WAKEUP_GPIO0_INT_ST_SHIFT (4U) +#define PMU_WAKEUP_INT_ST_WAKEUP_GPIO0_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_GPIO0_INT_ST_SHIFT) /* 0x00000010 */ +#define PMU_WAKEUP_INT_ST_WAKEUP_UART0_INT_ST_SHIFT (5U) +#define PMU_WAKEUP_INT_ST_WAKEUP_UART0_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_UART0_INT_ST_SHIFT) /* 0x00000020 */ +#define PMU_WAKEUP_INT_ST_WAKEUP_SDMMC0_INT_ST_SHIFT (6U) +#define PMU_WAKEUP_INT_ST_WAKEUP_SDMMC0_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_SDMMC0_INT_ST_SHIFT) /* 0x00000040 */ +#define PMU_WAKEUP_INT_ST_WAKEUP_SDMMC1_INT_ST_SHIFT (7U) +#define PMU_WAKEUP_INT_ST_WAKEUP_SDMMC1_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_SDMMC1_INT_ST_SHIFT) /* 0x00000080 */ +#define PMU_WAKEUP_INT_ST_WAKEUP_SDMMC2_INT_ST_SHIFT (8U) +#define PMU_WAKEUP_INT_ST_WAKEUP_SDMMC2_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_SDMMC2_INT_ST_SHIFT) /* 0x00000100 */ +#define PMU_WAKEUP_INT_ST_WAKEUP_USB_INT_ST_SHIFT (9U) +#define PMU_WAKEUP_INT_ST_WAKEUP_USB_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_USB_INT_ST_SHIFT) /* 0x00000200 */ +#define PMU_WAKEUP_INT_ST_WAKEUP_PCIE_INT_ST_SHIFT (10U) +#define PMU_WAKEUP_INT_ST_WAKEUP_PCIE_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_PCIE_INT_ST_SHIFT) /* 0x00000400 */ +#define PMU_WAKEUP_INT_ST_WAKEUP_VAD_INT_ST_SHIFT (11U) +#define PMU_WAKEUP_INT_ST_WAKEUP_VAD_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_VAD_INT_ST_SHIFT) /* 0x00000800 */ +#define PMU_WAKEUP_INT_ST_WAKEUP_TIMER_INT_ST_SHIFT (12U) +#define PMU_WAKEUP_INT_ST_WAKEUP_TIMER_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_TIMER_INT_ST_SHIFT) /* 0x00001000 */ +#define PMU_WAKEUP_INT_ST_WAKEUP_PWM0_INT_ST_SHIFT (13U) +#define PMU_WAKEUP_INT_ST_WAKEUP_PWM0_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_PWM0_INT_ST_SHIFT) /* 0x00002000 */ +#define PMU_WAKEUP_INT_ST_WAKEUP_TIMEOUT_INT_ST_SHIFT (14U) +#define PMU_WAKEUP_INT_ST_WAKEUP_TIMEOUT_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_TIMEOUT_INT_ST_SHIFT) /* 0x00004000 */ +#define PMU_WAKEUP_INT_ST_WAKEUP_SYS_INT_ST_SHIFT (15U) +#define PMU_WAKEUP_INT_ST_WAKEUP_SYS_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_ST_WAKEUP_SYS_INT_ST_SHIFT) /* 0x00008000 */ +/* WAKEUP_EDGE_CON */ +#define PMU_WAKEUP_EDGE_CON_OFFSET (0x18U) +#define PMU_WAKEUP_EDGE_CON_EDGE_WAKEUP_EN_SHIFT (0U) +#define PMU_WAKEUP_EDGE_CON_EDGE_WAKEUP_EN_MASK (0xFFFFFFFFU << PMU_WAKEUP_EDGE_CON_EDGE_WAKEUP_EN_SHIFT) /* 0xFFFFFFFF */ +/* WAKEUP_EDGE_ST */ +#define PMU_WAKEUP_EDGE_ST_OFFSET (0x1CU) +#define PMU_WAKEUP_EDGE_ST_EDGE_STATUS_SHIFT (0U) +#define PMU_WAKEUP_EDGE_ST_EDGE_STATUS_MASK (0xFFFFFFFFU << PMU_WAKEUP_EDGE_ST_EDGE_STATUS_SHIFT) /* 0xFFFFFFFF */ +/* BUS_IDLE_CON0 */ +#define PMU_BUS_IDLE_CON0_OFFSET (0x40U) +#define PMU_BUS_IDLE_CON0_IDLE_REQ_MSCH_SHIFT (0U) +#define PMU_BUS_IDLE_CON0_IDLE_REQ_MSCH_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_MSCH_SHIFT) /* 0x00000001 */ +#define PMU_BUS_IDLE_CON0_IDLE_REQ_GPU_SHIFT (1U) +#define PMU_BUS_IDLE_CON0_IDLE_REQ_GPU_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_GPU_SHIFT) /* 0x00000002 */ +#define PMU_BUS_IDLE_CON0_IDLE_REQ_NPU_SHIFT (2U) +#define PMU_BUS_IDLE_CON0_IDLE_REQ_NPU_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_NPU_SHIFT) /* 0x00000004 */ +#define PMU_BUS_IDLE_CON0_IDLE_REQ_VI_SHIFT (3U) +#define PMU_BUS_IDLE_CON0_IDLE_REQ_VI_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_VI_SHIFT) /* 0x00000008 */ +#define PMU_BUS_IDLE_CON0_IDLE_REQ_VO_SHIFT (4U) +#define PMU_BUS_IDLE_CON0_IDLE_REQ_VO_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_VO_SHIFT) /* 0x00000010 */ +#define PMU_BUS_IDLE_CON0_IDLE_REQ_RGA_SHIFT (5U) +#define PMU_BUS_IDLE_CON0_IDLE_REQ_RGA_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_RGA_SHIFT) /* 0x00000020 */ +#define PMU_BUS_IDLE_CON0_IDLE_REQ_VPU_SHIFT (6U) +#define PMU_BUS_IDLE_CON0_IDLE_REQ_VPU_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_VPU_SHIFT) /* 0x00000040 */ +#define PMU_BUS_IDLE_CON0_IDLE_REQ_RKVENC_SHIFT (7U) +#define PMU_BUS_IDLE_CON0_IDLE_REQ_RKVENC_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_RKVENC_SHIFT) /* 0x00000080 */ +#define PMU_BUS_IDLE_CON0_IDLE_REQ_RKVDEC_SHIFT (8U) +#define PMU_BUS_IDLE_CON0_IDLE_REQ_RKVDEC_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_RKVDEC_SHIFT) /* 0x00000100 */ +#define PMU_BUS_IDLE_CON0_IDLE_REQ_GIC_AUDIO_SHIFT (9U) +#define PMU_BUS_IDLE_CON0_IDLE_REQ_GIC_AUDIO_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_GIC_AUDIO_SHIFT) /* 0x00000200 */ +#define PMU_BUS_IDLE_CON0_IDLE_REQ_PHP_SHIFT (10U) +#define PMU_BUS_IDLE_CON0_IDLE_REQ_PHP_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_PHP_SHIFT) /* 0x00000400 */ +#define PMU_BUS_IDLE_CON0_IDLE_REQ_PIPE_SHIFT (11U) +#define PMU_BUS_IDLE_CON0_IDLE_REQ_PIPE_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_PIPE_SHIFT) /* 0x00000800 */ +#define PMU_BUS_IDLE_CON0_IDLE_REQ_SECURE_FLASH_SHIFT (12U) +#define PMU_BUS_IDLE_CON0_IDLE_REQ_SECURE_FLASH_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_SECURE_FLASH_SHIFT) /* 0x00001000 */ +#define PMU_BUS_IDLE_CON0_IDLE_REQ_PERIMID_SHIFT (13U) +#define PMU_BUS_IDLE_CON0_IDLE_REQ_PERIMID_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_PERIMID_SHIFT) /* 0x00002000 */ +#define PMU_BUS_IDLE_CON0_IDLE_REQ_USB_SHIFT (14U) +#define PMU_BUS_IDLE_CON0_IDLE_REQ_USB_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_USB_SHIFT) /* 0x00004000 */ +#define PMU_BUS_IDLE_CON0_IDLE_REQ_BUS_SHIFT (15U) +#define PMU_BUS_IDLE_CON0_IDLE_REQ_BUS_MASK (0x1U << PMU_BUS_IDLE_CON0_IDLE_REQ_BUS_SHIFT) /* 0x00008000 */ +/* BUS_IDLE_CON1 */ +#define PMU_BUS_IDLE_CON1_OFFSET (0x44U) +#define PMU_BUS_IDLE_CON1_IDLE_REQ_TOP1_SHIFT (0U) +#define PMU_BUS_IDLE_CON1_IDLE_REQ_TOP1_MASK (0x1U << PMU_BUS_IDLE_CON1_IDLE_REQ_TOP1_SHIFT) /* 0x00000001 */ +#define PMU_BUS_IDLE_CON1_IDLE_REQ_TOP2_SHIFT (1U) +#define PMU_BUS_IDLE_CON1_IDLE_REQ_TOP2_MASK (0x1U << PMU_BUS_IDLE_CON1_IDLE_REQ_TOP2_SHIFT) /* 0x00000002 */ +#define PMU_BUS_IDLE_CON1_IDLE_REQ_PMU_SHIFT (2U) +#define PMU_BUS_IDLE_CON1_IDLE_REQ_PMU_MASK (0x1U << PMU_BUS_IDLE_CON1_IDLE_REQ_PMU_SHIFT) /* 0x00000004 */ +/* BUS_IDLE_SFTCON0 */ +#define PMU_BUS_IDLE_SFTCON0_OFFSET (0x50U) +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_MSCH_SHIFT (0U) +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_MSCH_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_MSCH_SHIFT) /* 0x00000001 */ +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_GPU_SHIFT (1U) +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_GPU_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_GPU_SHIFT) /* 0x00000002 */ +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_NPU_SHIFT (2U) +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_NPU_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_NPU_SHIFT) /* 0x00000004 */ +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_VI_SHIFT (3U) +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_VI_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_VI_SHIFT) /* 0x00000008 */ +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_VO_SHIFT (4U) +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_VO_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_VO_SHIFT) /* 0x00000010 */ +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_RGA_SHIFT (5U) +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_RGA_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_RGA_SHIFT) /* 0x00000020 */ +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_VPU_SHIFT (6U) +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_VPU_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_VPU_SHIFT) /* 0x00000040 */ +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_RKVENC_SHIFT (7U) +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_RKVENC_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_RKVENC_SHIFT) /* 0x00000080 */ +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_RKVDEC_SHIFT (8U) +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_RKVDEC_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_RKVDEC_SHIFT) /* 0x00000100 */ +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_GIC_AUDIO_SHIFT (9U) +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_GIC_AUDIO_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_GIC_AUDIO_SHIFT) /* 0x00000200 */ +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_PHP_SHIFT (10U) +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_PHP_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_PHP_SHIFT) /* 0x00000400 */ +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_PIPE_SHIFT (11U) +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_PIPE_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_PIPE_SHIFT) /* 0x00000800 */ +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_SECURE_FLASH_SHIFT (12U) +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_SECURE_FLASH_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_SECURE_FLASH_SHIFT) /* 0x00001000 */ +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_PERIMID_SHIFT (13U) +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_PERIMID_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_PERIMID_SHIFT) /* 0x00002000 */ +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_USB_SHIFT (14U) +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_USB_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_USB_SHIFT) /* 0x00004000 */ +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_BUS_SHIFT (15U) +#define PMU_BUS_IDLE_SFTCON0_IDLE_REQ_BUS_MASK (0x1U << PMU_BUS_IDLE_SFTCON0_IDLE_REQ_BUS_SHIFT) /* 0x00008000 */ +/* BUS_IDLE_SFTCON1 */ +#define PMU_BUS_IDLE_SFTCON1_OFFSET (0x54U) +#define PMU_BUS_IDLE_SFTCON1_IDLE_REQ_TOP1_SHIFT (0U) +#define PMU_BUS_IDLE_SFTCON1_IDLE_REQ_TOP1_MASK (0x1U << PMU_BUS_IDLE_SFTCON1_IDLE_REQ_TOP1_SHIFT) /* 0x00000001 */ +#define PMU_BUS_IDLE_SFTCON1_IDLE_REQ_TOP2_SHIFT (1U) +#define PMU_BUS_IDLE_SFTCON1_IDLE_REQ_TOP2_MASK (0x1U << PMU_BUS_IDLE_SFTCON1_IDLE_REQ_TOP2_SHIFT) /* 0x00000002 */ +#define PMU_BUS_IDLE_SFTCON1_IDLE_REQ_PMU_SHIFT (2U) +#define PMU_BUS_IDLE_SFTCON1_IDLE_REQ_PMU_MASK (0x1U << PMU_BUS_IDLE_SFTCON1_IDLE_REQ_PMU_SHIFT) /* 0x00000004 */ +/* BUS_IDLE_ACK */ +#define PMU_BUS_IDLE_ACK_OFFSET (0x60U) +#define PMU_BUS_IDLE_ACK (0x0U) +#define PMU_BUS_IDLE_ACK_IDLE_ACK_MSCH_SHIFT (0U) +#define PMU_BUS_IDLE_ACK_IDLE_ACK_MSCH_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_MSCH_SHIFT) /* 0x00000001 */ +#define PMU_BUS_IDLE_ACK_IDLE_ACK_GPU_SHIFT (1U) +#define PMU_BUS_IDLE_ACK_IDLE_ACK_GPU_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_GPU_SHIFT) /* 0x00000002 */ +#define PMU_BUS_IDLE_ACK_IDLE_ACK_NPU_SHIFT (2U) +#define PMU_BUS_IDLE_ACK_IDLE_ACK_NPU_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_NPU_SHIFT) /* 0x00000004 */ +#define PMU_BUS_IDLE_ACK_IDLE_ACK_VI_SHIFT (3U) +#define PMU_BUS_IDLE_ACK_IDLE_ACK_VI_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_VI_SHIFT) /* 0x00000008 */ +#define PMU_BUS_IDLE_ACK_IDLE_ACK_VO_SHIFT (4U) +#define PMU_BUS_IDLE_ACK_IDLE_ACK_VO_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_VO_SHIFT) /* 0x00000010 */ +#define PMU_BUS_IDLE_ACK_IDLE_ACK_RGA_SHIFT (5U) +#define PMU_BUS_IDLE_ACK_IDLE_ACK_RGA_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_RGA_SHIFT) /* 0x00000020 */ +#define PMU_BUS_IDLE_ACK_IDLE_ACK_VPU_SHIFT (6U) +#define PMU_BUS_IDLE_ACK_IDLE_ACK_VPU_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_VPU_SHIFT) /* 0x00000040 */ +#define PMU_BUS_IDLE_ACK_IDLE_ACK_RKVENC_SHIFT (7U) +#define PMU_BUS_IDLE_ACK_IDLE_ACK_RKVENC_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_RKVENC_SHIFT) /* 0x00000080 */ +#define PMU_BUS_IDLE_ACK_IDLE_ACK_RKVDEC_SHIFT (8U) +#define PMU_BUS_IDLE_ACK_IDLE_ACK_RKVDEC_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_RKVDEC_SHIFT) /* 0x00000100 */ +#define PMU_BUS_IDLE_ACK_IDLE_ACK_GIC_AUDIO_SHIFT (9U) +#define PMU_BUS_IDLE_ACK_IDLE_ACK_GIC_AUDIO_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_GIC_AUDIO_SHIFT) /* 0x00000200 */ +#define PMU_BUS_IDLE_ACK_IDLE_ACK_PHP_SHIFT (10U) +#define PMU_BUS_IDLE_ACK_IDLE_ACK_PHP_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_PHP_SHIFT) /* 0x00000400 */ +#define PMU_BUS_IDLE_ACK_IDLE_ACK_PIPE_SHIFT (11U) +#define PMU_BUS_IDLE_ACK_IDLE_ACK_PIPE_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_PIPE_SHIFT) /* 0x00000800 */ +#define PMU_BUS_IDLE_ACK_IDLE_ACK_SECURE_FLASH_SHIFT (12U) +#define PMU_BUS_IDLE_ACK_IDLE_ACK_SECURE_FLASH_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_SECURE_FLASH_SHIFT) /* 0x00001000 */ +#define PMU_BUS_IDLE_ACK_IDLE_ACK_PERIMID_SHIFT (13U) +#define PMU_BUS_IDLE_ACK_IDLE_ACK_PERIMID_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_PERIMID_SHIFT) /* 0x00002000 */ +#define PMU_BUS_IDLE_ACK_IDLE_ACK_USB_SHIFT (14U) +#define PMU_BUS_IDLE_ACK_IDLE_ACK_USB_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_USB_SHIFT) /* 0x00004000 */ +#define PMU_BUS_IDLE_ACK_IDLE_ACK_BUS_SHIFT (15U) +#define PMU_BUS_IDLE_ACK_IDLE_ACK_BUS_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_BUS_SHIFT) /* 0x00008000 */ +#define PMU_BUS_IDLE_ACK_IDLE_ACK_TOP1_SHIFT (16U) +#define PMU_BUS_IDLE_ACK_IDLE_ACK_TOP1_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_TOP1_SHIFT) /* 0x00010000 */ +#define PMU_BUS_IDLE_ACK_IDLE_ACK_TOP2_SHIFT (17U) +#define PMU_BUS_IDLE_ACK_IDLE_ACK_TOP2_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_TOP2_SHIFT) /* 0x00020000 */ +#define PMU_BUS_IDLE_ACK_IDLE_ACK_PMU_SHIFT (18U) +#define PMU_BUS_IDLE_ACK_IDLE_ACK_PMU_MASK (0x1U << PMU_BUS_IDLE_ACK_IDLE_ACK_PMU_SHIFT) /* 0x00040000 */ +/* BUS_IDLE_ST */ +#define PMU_BUS_IDLE_ST_OFFSET (0x68U) +#define PMU_BUS_IDLE_ST (0x0U) +#define PMU_BUS_IDLE_ST_IDLE_MSCH_SHIFT (0U) +#define PMU_BUS_IDLE_ST_IDLE_MSCH_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_MSCH_SHIFT) /* 0x00000001 */ +#define PMU_BUS_IDLE_ST_IDLE_GPU_SHIFT (1U) +#define PMU_BUS_IDLE_ST_IDLE_GPU_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_GPU_SHIFT) /* 0x00000002 */ +#define PMU_BUS_IDLE_ST_IDLE_NPU_SHIFT (2U) +#define PMU_BUS_IDLE_ST_IDLE_NPU_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_NPU_SHIFT) /* 0x00000004 */ +#define PMU_BUS_IDLE_ST_IDLE_VI_SHIFT (3U) +#define PMU_BUS_IDLE_ST_IDLE_VI_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_VI_SHIFT) /* 0x00000008 */ +#define PMU_BUS_IDLE_ST_IDLE_VO_SHIFT (4U) +#define PMU_BUS_IDLE_ST_IDLE_VO_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_VO_SHIFT) /* 0x00000010 */ +#define PMU_BUS_IDLE_ST_IDLE_RGA_SHIFT (5U) +#define PMU_BUS_IDLE_ST_IDLE_RGA_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_RGA_SHIFT) /* 0x00000020 */ +#define PMU_BUS_IDLE_ST_IDLE_VPU_SHIFT (6U) +#define PMU_BUS_IDLE_ST_IDLE_VPU_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_VPU_SHIFT) /* 0x00000040 */ +#define PMU_BUS_IDLE_ST_IDLE_RKVENC_SHIFT (7U) +#define PMU_BUS_IDLE_ST_IDLE_RKVENC_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_RKVENC_SHIFT) /* 0x00000080 */ +#define PMU_BUS_IDLE_ST_IDLE_RKVDEC_SHIFT (8U) +#define PMU_BUS_IDLE_ST_IDLE_RKVDEC_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_RKVDEC_SHIFT) /* 0x00000100 */ +#define PMU_BUS_IDLE_ST_IDLE_GIC_AUDIO_SHIFT (9U) +#define PMU_BUS_IDLE_ST_IDLE_GIC_AUDIO_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_GIC_AUDIO_SHIFT) /* 0x00000200 */ +#define PMU_BUS_IDLE_ST_IDLE_PHP_SHIFT (10U) +#define PMU_BUS_IDLE_ST_IDLE_PHP_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_PHP_SHIFT) /* 0x00000400 */ +#define PMU_BUS_IDLE_ST_IDLE_PIPE_SHIFT (11U) +#define PMU_BUS_IDLE_ST_IDLE_PIPE_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_PIPE_SHIFT) /* 0x00000800 */ +#define PMU_BUS_IDLE_ST_IDLE_SECURE_FLASH_SHIFT (12U) +#define PMU_BUS_IDLE_ST_IDLE_SECURE_FLASH_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_SECURE_FLASH_SHIFT) /* 0x00001000 */ +#define PMU_BUS_IDLE_ST_IDLE_PERIMID_SHIFT (13U) +#define PMU_BUS_IDLE_ST_IDLE_PERIMID_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_PERIMID_SHIFT) /* 0x00002000 */ +#define PMU_BUS_IDLE_ST_IDLE_USB_SHIFT (14U) +#define PMU_BUS_IDLE_ST_IDLE_USB_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_USB_SHIFT) /* 0x00004000 */ +#define PMU_BUS_IDLE_ST_IDLE_BUS_SHIFT (15U) +#define PMU_BUS_IDLE_ST_IDLE_BUS_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_BUS_SHIFT) /* 0x00008000 */ +#define PMU_BUS_IDLE_ST_IDLE_TOP1_SHIFT (16U) +#define PMU_BUS_IDLE_ST_IDLE_TOP1_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_TOP1_SHIFT) /* 0x00010000 */ +#define PMU_BUS_IDLE_ST_IDLE_TOP2_SHIFT (17U) +#define PMU_BUS_IDLE_ST_IDLE_TOP2_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_TOP2_SHIFT) /* 0x00020000 */ +#define PMU_BUS_IDLE_ST_IDLE_PMU_SHIFT (18U) +#define PMU_BUS_IDLE_ST_IDLE_PMU_MASK (0x1U << PMU_BUS_IDLE_ST_IDLE_PMU_SHIFT) /* 0x00040000 */ +/* NOC_AUTO_CON0 */ +#define PMU_NOC_AUTO_CON0_OFFSET (0x70U) +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_MSCH_SHIFT (0U) +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_MSCH_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_MSCH_SHIFT) /* 0x00000001 */ +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_GPU_SHIFT (1U) +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_GPU_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_GPU_SHIFT) /* 0x00000002 */ +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_NPU_SHIFT (2U) +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_NPU_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_NPU_SHIFT) /* 0x00000004 */ +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_VI_SHIFT (3U) +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_VI_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_VI_SHIFT) /* 0x00000008 */ +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_VO_SHIFT (4U) +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_VO_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_VO_SHIFT) /* 0x00000010 */ +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_RGA_SHIFT (5U) +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_RGA_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_RGA_SHIFT) /* 0x00000020 */ +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_VPU_SHIFT (6U) +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_VPU_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_VPU_SHIFT) /* 0x00000040 */ +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_RKVENC_SHIFT (7U) +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_RKVENC_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_RKVENC_SHIFT) /* 0x00000080 */ +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_RKVDEC_SHIFT (8U) +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_RKVDEC_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_RKVDEC_SHIFT) /* 0x00000100 */ +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_GIC_AUDIO_SHIFT (9U) +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_GIC_AUDIO_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_GIC_AUDIO_SHIFT) /* 0x00000200 */ +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_PHP_SHIFT (10U) +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_PHP_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_PHP_SHIFT) /* 0x00000400 */ +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_PIPE_SHIFT (11U) +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_PIPE_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_PIPE_SHIFT) /* 0x00000800 */ +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_SECURE_FLASH_SHIFT (12U) +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_SECURE_FLASH_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_SECURE_FLASH_SHIFT) /* 0x00001000 */ +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_PERIMID_SHIFT (13U) +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_PERIMID_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_PERIMID_SHIFT) /* 0x00002000 */ +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_USB_SHIFT (14U) +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_USB_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_USB_SHIFT) /* 0x00004000 */ +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_BUS_SHIFT (15U) +#define PMU_NOC_AUTO_CON0_AUTO_IDLE_BUS_MASK (0x1U << PMU_NOC_AUTO_CON0_AUTO_IDLE_BUS_SHIFT) /* 0x00008000 */ +/* NOC_AUTO_CON1 */ +#define PMU_NOC_AUTO_CON1_OFFSET (0x74U) +#define PMU_NOC_AUTO_CON1_AUTO_IDLE_TOP1_SHIFT (0U) +#define PMU_NOC_AUTO_CON1_AUTO_IDLE_TOP1_MASK (0x1U << PMU_NOC_AUTO_CON1_AUTO_IDLE_TOP1_SHIFT) /* 0x00000001 */ +#define PMU_NOC_AUTO_CON1_AUTO_IDLE_TOP2_SHIFT (1U) +#define PMU_NOC_AUTO_CON1_AUTO_IDLE_TOP2_MASK (0x1U << PMU_NOC_AUTO_CON1_AUTO_IDLE_TOP2_SHIFT) /* 0x00000002 */ +#define PMU_NOC_AUTO_CON1_AUTO_IDLE_PMU_SHIFT (2U) +#define PMU_NOC_AUTO_CON1_AUTO_IDLE_PMU_MASK (0x1U << PMU_NOC_AUTO_CON1_AUTO_IDLE_PMU_SHIFT) /* 0x00000004 */ +#define PMU_NOC_AUTO_CON1_AUTO_IDLE_CPU_SHIFT (3U) +#define PMU_NOC_AUTO_CON1_AUTO_IDLE_CPU_MASK (0x1U << PMU_NOC_AUTO_CON1_AUTO_IDLE_CPU_SHIFT) /* 0x00000008 */ +/* DDR_PWR_CON */ +#define PMU_DDR_PWR_CON_OFFSET (0x80U) +#define PMU_DDR_PWR_CON_DDR_SREF_ENA_SHIFT (0U) +#define PMU_DDR_PWR_CON_DDR_SREF_ENA_MASK (0x1U << PMU_DDR_PWR_CON_DDR_SREF_ENA_SHIFT) /* 0x00000001 */ +#define PMU_DDR_PWR_CON_DDRIO_RET_ENA_SHIFT (1U) +#define PMU_DDR_PWR_CON_DDRIO_RET_ENA_MASK (0x1U << PMU_DDR_PWR_CON_DDRIO_RET_ENA_SHIFT) /* 0x00000002 */ +#define PMU_DDR_PWR_CON_DDRPHY_AUTO_GATING_ENA_SHIFT (4U) +#define PMU_DDR_PWR_CON_DDRPHY_AUTO_GATING_ENA_MASK (0x1U << PMU_DDR_PWR_CON_DDRPHY_AUTO_GATING_ENA_SHIFT) /* 0x00000010 */ +/* DDR_PWR_SFTCON */ +#define PMU_DDR_PWR_SFTCON_OFFSET (0x84U) +#define PMU_DDR_PWR_SFTCON_SW_DDR_SREF_REQ_SHIFT (0U) +#define PMU_DDR_PWR_SFTCON_SW_DDR_SREF_REQ_MASK (0x1U << PMU_DDR_PWR_SFTCON_SW_DDR_SREF_REQ_SHIFT) /* 0x00000001 */ +#define PMU_DDR_PWR_SFTCON_SW_DDRIO_RET_REQ_SHIFT (1U) +#define PMU_DDR_PWR_SFTCON_SW_DDRIO_RET_REQ_MASK (0x1U << PMU_DDR_PWR_SFTCON_SW_DDRIO_RET_REQ_SHIFT) /* 0x00000002 */ +#define PMU_DDR_PWR_SFTCON_SW_DDRIO_RET_EXIT_SHIFT (2U) +#define PMU_DDR_PWR_SFTCON_SW_DDRIO_RET_EXIT_MASK (0x1U << PMU_DDR_PWR_SFTCON_SW_DDRIO_RET_EXIT_SHIFT) /* 0x00000004 */ +#define PMU_DDR_PWR_SFTCON_DDRCTL_ACTIVE_WAIT_SHIFT (3U) +#define PMU_DDR_PWR_SFTCON_DDRCTL_ACTIVE_WAIT_MASK (0x1U << PMU_DDR_PWR_SFTCON_DDRCTL_ACTIVE_WAIT_SHIFT) /* 0x00000008 */ +/* DDR_PWR_STATE */ +#define PMU_DDR_PWR_STATE_OFFSET (0x88U) +#define PMU_DDR_PWR_STATE (0x0U) +#define PMU_DDR_PWR_STATE_DDR_POWER_STATE_SHIFT (0U) +#define PMU_DDR_PWR_STATE_DDR_POWER_STATE_MASK (0x7U << PMU_DDR_PWR_STATE_DDR_POWER_STATE_SHIFT) /* 0x00000007 */ +/* DDR_PWR_ST */ +#define PMU_DDR_PWR_ST_OFFSET (0x8CU) +#define PMU_DDR_PWR_ST (0x2U) +#define PMU_DDR_PWR_ST_DDRCTL_C_SYSACK_SHIFT (0U) +#define PMU_DDR_PWR_ST_DDRCTL_C_SYSACK_MASK (0x1U << PMU_DDR_PWR_ST_DDRCTL_C_SYSACK_SHIFT) /* 0x00000001 */ +#define PMU_DDR_PWR_ST_DDRCTL_C_ACTIVE_SHIFT (1U) +#define PMU_DDR_PWR_ST_DDRCTL_C_ACTIVE_MASK (0x1U << PMU_DDR_PWR_ST_DDRCTL_C_ACTIVE_SHIFT) /* 0x00000002 */ +#define PMU_DDR_PWR_ST_DDRIO_RET_SHIFT (2U) +#define PMU_DDR_PWR_ST_DDRIO_RET_MASK (0x1U << PMU_DDR_PWR_ST_DDRIO_RET_SHIFT) /* 0x00000004 */ +/* PWR_GATE_CON */ +#define PMU_PWR_GATE_CON_OFFSET (0x90U) +#define PMU_PWR_GATE_CON_PD_GPU_DWN_ENA_SHIFT (0U) +#define PMU_PWR_GATE_CON_PD_GPU_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON_PD_GPU_DWN_ENA_SHIFT) /* 0x00000001 */ +#define PMU_PWR_GATE_CON_PD_NPU_DWN_ENA_SHIFT (1U) +#define PMU_PWR_GATE_CON_PD_NPU_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON_PD_NPU_DWN_ENA_SHIFT) /* 0x00000002 */ +#define PMU_PWR_GATE_CON_PD_VPU_DWN_ENA_SHIFT (2U) +#define PMU_PWR_GATE_CON_PD_VPU_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON_PD_VPU_DWN_ENA_SHIFT) /* 0x00000004 */ +#define PMU_PWR_GATE_CON_PD_RKVENC_DWN_ENA_SHIFT (3U) +#define PMU_PWR_GATE_CON_PD_RKVENC_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON_PD_RKVENC_DWN_ENA_SHIFT) /* 0x00000008 */ +#define PMU_PWR_GATE_CON_PD_RKVDEC_DWN_ENA_SHIFT (4U) +#define PMU_PWR_GATE_CON_PD_RKVDEC_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON_PD_RKVDEC_DWN_ENA_SHIFT) /* 0x00000010 */ +#define PMU_PWR_GATE_CON_PD_RGA_DWN_ENA_SHIFT (5U) +#define PMU_PWR_GATE_CON_PD_RGA_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON_PD_RGA_DWN_ENA_SHIFT) /* 0x00000020 */ +#define PMU_PWR_GATE_CON_PD_VI_DWN_ENA_SHIFT (6U) +#define PMU_PWR_GATE_CON_PD_VI_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON_PD_VI_DWN_ENA_SHIFT) /* 0x00000040 */ +#define PMU_PWR_GATE_CON_PD_VO_DWN_ENA_SHIFT (7U) +#define PMU_PWR_GATE_CON_PD_VO_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON_PD_VO_DWN_ENA_SHIFT) /* 0x00000080 */ +#define PMU_PWR_GATE_CON_PD_PIPE_DWN_ENA_SHIFT (8U) +#define PMU_PWR_GATE_CON_PD_PIPE_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON_PD_PIPE_DWN_ENA_SHIFT) /* 0x00000100 */ +#define PMU_PWR_GATE_CON_PD_DDR_DWN_ENA_SHIFT (9U) +#define PMU_PWR_GATE_CON_PD_DDR_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON_PD_DDR_DWN_ENA_SHIFT) /* 0x00000200 */ +/* PWR_GATE_STATE */ +#define PMU_PWR_GATE_STATE_OFFSET (0x94U) +#define PMU_PWR_GATE_STATE (0x0U) +#define PMU_PWR_GATE_STATE_POWER_GATE_STATE_SHIFT (0U) +#define PMU_PWR_GATE_STATE_POWER_GATE_STATE_MASK (0x7U << PMU_PWR_GATE_STATE_POWER_GATE_STATE_SHIFT) /* 0x00000007 */ +/* PWR_DWN_ST */ +#define PMU_PWR_DWN_ST_OFFSET (0x98U) +#define PMU_PWR_DWN_ST (0x0U) +#define PMU_PWR_DWN_ST_PD_GPU_DWN_STAT_SHIFT (0U) +#define PMU_PWR_DWN_ST_PD_GPU_DWN_STAT_MASK (0x1U << PMU_PWR_DWN_ST_PD_GPU_DWN_STAT_SHIFT) /* 0x00000001 */ +#define PMU_PWR_DWN_ST_PD_NPU_DWN_STAT_SHIFT (1U) +#define PMU_PWR_DWN_ST_PD_NPU_DWN_STAT_MASK (0x1U << PMU_PWR_DWN_ST_PD_NPU_DWN_STAT_SHIFT) /* 0x00000002 */ +#define PMU_PWR_DWN_ST_PD_VPU_DWN_STAT_SHIFT (2U) +#define PMU_PWR_DWN_ST_PD_VPU_DWN_STAT_MASK (0x1U << PMU_PWR_DWN_ST_PD_VPU_DWN_STAT_SHIFT) /* 0x00000004 */ +#define PMU_PWR_DWN_ST_PD_RKVENC_DWN_STAT_SHIFT (3U) +#define PMU_PWR_DWN_ST_PD_RKVENC_DWN_STAT_MASK (0x1U << PMU_PWR_DWN_ST_PD_RKVENC_DWN_STAT_SHIFT) /* 0x00000008 */ +#define PMU_PWR_DWN_ST_PD_RKVDEC_DWN_STAT_SHIFT (4U) +#define PMU_PWR_DWN_ST_PD_RKVDEC_DWN_STAT_MASK (0x1U << PMU_PWR_DWN_ST_PD_RKVDEC_DWN_STAT_SHIFT) /* 0x00000010 */ +#define PMU_PWR_DWN_ST_PD_RGA_DWN_STAT_SHIFT (5U) +#define PMU_PWR_DWN_ST_PD_RGA_DWN_STAT_MASK (0x1U << PMU_PWR_DWN_ST_PD_RGA_DWN_STAT_SHIFT) /* 0x00000020 */ +#define PMU_PWR_DWN_ST_PD_VI_DWN_STAT_SHIFT (6U) +#define PMU_PWR_DWN_ST_PD_VI_DWN_STAT_MASK (0x1U << PMU_PWR_DWN_ST_PD_VI_DWN_STAT_SHIFT) /* 0x00000040 */ +#define PMU_PWR_DWN_ST_PD_VO_DWN_STAT_SHIFT (7U) +#define PMU_PWR_DWN_ST_PD_VO_DWN_STAT_MASK (0x1U << PMU_PWR_DWN_ST_PD_VO_DWN_STAT_SHIFT) /* 0x00000080 */ +#define PMU_PWR_DWN_ST_PD_PIPE_DWN_STAT_SHIFT (8U) +#define PMU_PWR_DWN_ST_PD_PIPE_DWN_STAT_MASK (0x1U << PMU_PWR_DWN_ST_PD_PIPE_DWN_STAT_SHIFT) /* 0x00000100 */ +#define PMU_PWR_DWN_ST_PD_DDR_DWN_STAT_SHIFT (9U) +#define PMU_PWR_DWN_ST_PD_DDR_DWN_STAT_MASK (0x1U << PMU_PWR_DWN_ST_PD_DDR_DWN_STAT_SHIFT) /* 0x00000200 */ +/* PWR_GATE_SFTCON */ +#define PMU_PWR_GATE_SFTCON_OFFSET (0xA0U) +#define PMU_PWR_GATE_SFTCON_PD_GPU_DWN_ENA_SHIFT (0U) +#define PMU_PWR_GATE_SFTCON_PD_GPU_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_SFTCON_PD_GPU_DWN_ENA_SHIFT) /* 0x00000001 */ +#define PMU_PWR_GATE_SFTCON_PD_NPU_DWN_ENA_SHIFT (1U) +#define PMU_PWR_GATE_SFTCON_PD_NPU_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_SFTCON_PD_NPU_DWN_ENA_SHIFT) /* 0x00000002 */ +#define PMU_PWR_GATE_SFTCON_PD_VPU_DWN_ENA_SHIFT (2U) +#define PMU_PWR_GATE_SFTCON_PD_VPU_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_SFTCON_PD_VPU_DWN_ENA_SHIFT) /* 0x00000004 */ +#define PMU_PWR_GATE_SFTCON_PD_RKVENC_DWN_ENA_SHIFT (3U) +#define PMU_PWR_GATE_SFTCON_PD_RKVENC_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_SFTCON_PD_RKVENC_DWN_ENA_SHIFT) /* 0x00000008 */ +#define PMU_PWR_GATE_SFTCON_PD_RKVDEC_DWN_ENA_SHIFT (4U) +#define PMU_PWR_GATE_SFTCON_PD_RKVDEC_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_SFTCON_PD_RKVDEC_DWN_ENA_SHIFT) /* 0x00000010 */ +#define PMU_PWR_GATE_SFTCON_PD_RGA_DWN_ENA_SHIFT (5U) +#define PMU_PWR_GATE_SFTCON_PD_RGA_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_SFTCON_PD_RGA_DWN_ENA_SHIFT) /* 0x00000020 */ +#define PMU_PWR_GATE_SFTCON_PD_VI_DWN_ENA_SHIFT (6U) +#define PMU_PWR_GATE_SFTCON_PD_VI_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_SFTCON_PD_VI_DWN_ENA_SHIFT) /* 0x00000040 */ +#define PMU_PWR_GATE_SFTCON_PD_VO_DWN_ENA_SHIFT (7U) +#define PMU_PWR_GATE_SFTCON_PD_VO_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_SFTCON_PD_VO_DWN_ENA_SHIFT) /* 0x00000080 */ +#define PMU_PWR_GATE_SFTCON_PD_PIPE_DWN_ENA_SHIFT (8U) +#define PMU_PWR_GATE_SFTCON_PD_PIPE_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_SFTCON_PD_PIPE_DWN_ENA_SHIFT) /* 0x00000100 */ +#define PMU_PWR_GATE_SFTCON_PD_DDR_DWN_ENA_SHIFT (9U) +#define PMU_PWR_GATE_SFTCON_PD_DDR_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_SFTCON_PD_DDR_DWN_ENA_SHIFT) /* 0x00000200 */ +/* VOL_GATE_SFTCON */ +#define PMU_VOL_GATE_SFTCON_OFFSET (0xA8U) +#define PMU_VOL_GATE_SFTCON_VD_GPU_ENA_SHIFT (0U) +#define PMU_VOL_GATE_SFTCON_VD_GPU_ENA_MASK (0x1U << PMU_VOL_GATE_SFTCON_VD_GPU_ENA_SHIFT) /* 0x00000001 */ +#define PMU_VOL_GATE_SFTCON_VD_NPU_ENA_SHIFT (1U) +#define PMU_VOL_GATE_SFTCON_VD_NPU_ENA_MASK (0x1U << PMU_VOL_GATE_SFTCON_VD_NPU_ENA_SHIFT) /* 0x00000002 */ +/* CRU_PWR_CON */ +#define PMU_CRU_PWR_CON_OFFSET (0xB0U) +#define PMU_CRU_PWR_CON_ALIVE_32K_ENA_SHIFT (0U) +#define PMU_CRU_PWR_CON_ALIVE_32K_ENA_MASK (0x1U << PMU_CRU_PWR_CON_ALIVE_32K_ENA_SHIFT) /* 0x00000001 */ +#define PMU_CRU_PWR_CON_OSC_DIS_ENA_SHIFT (1U) +#define PMU_CRU_PWR_CON_OSC_DIS_ENA_MASK (0x1U << PMU_CRU_PWR_CON_OSC_DIS_ENA_SHIFT) /* 0x00000002 */ +#define PMU_CRU_PWR_CON_WAKEUP_RST_ENA_SHIFT (2U) +#define PMU_CRU_PWR_CON_WAKEUP_RST_ENA_MASK (0x1U << PMU_CRU_PWR_CON_WAKEUP_RST_ENA_SHIFT) /* 0x00000004 */ +#define PMU_CRU_PWR_CON_INPUT_CLAMP_ENA_SHIFT (3U) +#define PMU_CRU_PWR_CON_INPUT_CLAMP_ENA_MASK (0x1U << PMU_CRU_PWR_CON_INPUT_CLAMP_ENA_SHIFT) /* 0x00000008 */ +#define PMU_CRU_PWR_CON_ALIVE_OSC_ENA_SHIFT (4U) +#define PMU_CRU_PWR_CON_ALIVE_OSC_ENA_MASK (0x1U << PMU_CRU_PWR_CON_ALIVE_OSC_ENA_SHIFT) /* 0x00000010 */ +#define PMU_CRU_PWR_CON_POWER_OFF_ENA_SHIFT (5U) +#define PMU_CRU_PWR_CON_POWER_OFF_ENA_MASK (0x1U << PMU_CRU_PWR_CON_POWER_OFF_ENA_SHIFT) /* 0x00000020 */ +#define PMU_CRU_PWR_CON_PWM_SWITCH_ENA_SHIFT (6U) +#define PMU_CRU_PWR_CON_PWM_SWITCH_ENA_MASK (0x1U << PMU_CRU_PWR_CON_PWM_SWITCH_ENA_SHIFT) /* 0x00000040 */ +#define PMU_CRU_PWR_CON_PWM_GPIO_IOE_ENA_SHIFT (7U) +#define PMU_CRU_PWR_CON_PWM_GPIO_IOE_ENA_MASK (0x1U << PMU_CRU_PWR_CON_PWM_GPIO_IOE_ENA_SHIFT) /* 0x00000080 */ +#define PMU_CRU_PWR_CON_PWM_SWITCH_IOUT_SHIFT (8U) +#define PMU_CRU_PWR_CON_PWM_SWITCH_IOUT_MASK (0x1U << PMU_CRU_PWR_CON_PWM_SWITCH_IOUT_SHIFT) /* 0x00000100 */ +#define PMU_CRU_PWR_CON_PD_BUS_CLK_SRC_GATE_ENA_SHIFT (9U) +#define PMU_CRU_PWR_CON_PD_BUS_CLK_SRC_GATE_ENA_MASK (0x1U << PMU_CRU_PWR_CON_PD_BUS_CLK_SRC_GATE_ENA_SHIFT) /* 0x00000200 */ +#define PMU_CRU_PWR_CON_PD_PERI_CLK_SRC_GATE_ENA_SHIFT (10U) +#define PMU_CRU_PWR_CON_PD_PERI_CLK_SRC_GATE_ENA_MASK (0x1U << PMU_CRU_PWR_CON_PD_PERI_CLK_SRC_GATE_ENA_SHIFT) /* 0x00000400 */ +#define PMU_CRU_PWR_CON_PD_PMU_CLK_SRC_GATE_ENA_SHIFT (11U) +#define PMU_CRU_PWR_CON_PD_PMU_CLK_SRC_GATE_ENA_MASK (0x1U << PMU_CRU_PWR_CON_PD_PMU_CLK_SRC_GATE_ENA_SHIFT) /* 0x00000800 */ +#define PMU_CRU_PWR_CON_PMUMEM_CLK_SRC_GATE_ENA_SHIFT (12U) +#define PMU_CRU_PWR_CON_PMUMEM_CLK_SRC_GATE_ENA_MASK (0x1U << PMU_CRU_PWR_CON_PMUMEM_CLK_SRC_GATE_ENA_SHIFT) /* 0x00001000 */ +/* CRU_PWR_SFTCON */ +#define PMU_CRU_PWR_SFTCON_OFFSET (0xB4U) +#define PMU_CRU_PWR_SFTCON_ALIVE_32K_ENA_SHIFT (0U) +#define PMU_CRU_PWR_SFTCON_ALIVE_32K_ENA_MASK (0x1U << PMU_CRU_PWR_SFTCON_ALIVE_32K_ENA_SHIFT) /* 0x00000001 */ +#define PMU_CRU_PWR_SFTCON_OSC_DIS_ENA_SHIFT (1U) +#define PMU_CRU_PWR_SFTCON_OSC_DIS_ENA_MASK (0x1U << PMU_CRU_PWR_SFTCON_OSC_DIS_ENA_SHIFT) /* 0x00000002 */ +#define PMU_CRU_PWR_SFTCON_WAKEUP_RST_ENA_SHIFT (2U) +#define PMU_CRU_PWR_SFTCON_WAKEUP_RST_ENA_MASK (0x1U << PMU_CRU_PWR_SFTCON_WAKEUP_RST_ENA_SHIFT) /* 0x00000004 */ +#define PMU_CRU_PWR_SFTCON_INPUT_CLAMP_ENA_SHIFT (3U) +#define PMU_CRU_PWR_SFTCON_INPUT_CLAMP_ENA_MASK (0x1U << PMU_CRU_PWR_SFTCON_INPUT_CLAMP_ENA_SHIFT) /* 0x00000008 */ +#define PMU_CRU_PWR_SFTCON_ALIVE_OSC_ENA_SHIFT (4U) +#define PMU_CRU_PWR_SFTCON_ALIVE_OSC_ENA_MASK (0x1U << PMU_CRU_PWR_SFTCON_ALIVE_OSC_ENA_SHIFT) /* 0x00000010 */ +#define PMU_CRU_PWR_SFTCON_POWER_OFF_ENA_SHIFT (5U) +#define PMU_CRU_PWR_SFTCON_POWER_OFF_ENA_MASK (0x1U << PMU_CRU_PWR_SFTCON_POWER_OFF_ENA_SHIFT) /* 0x00000020 */ +/* CRU_PWR_STATE */ +#define PMU_CRU_PWR_STATE_OFFSET (0xB8U) +#define PMU_CRU_PWR_STATE (0x0U) +#define PMU_CRU_PWR_STATE_CRU_POWER_STATE_SHIFT (0U) +#define PMU_CRU_PWR_STATE_CRU_POWER_STATE_MASK (0xFU << PMU_CRU_PWR_STATE_CRU_POWER_STATE_SHIFT) /* 0x0000000F */ +/* PLLPD_CON */ +#define PMU_PLLPD_CON_OFFSET (0xC0U) +#define PMU_PLLPD_CON_APLL_PD_ENA_SHIFT (0U) +#define PMU_PLLPD_CON_APLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON_APLL_PD_ENA_SHIFT) /* 0x00000001 */ +#define PMU_PLLPD_CON_DPLL_PD_ENA_SHIFT (1U) +#define PMU_PLLPD_CON_DPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON_DPLL_PD_ENA_SHIFT) /* 0x00000002 */ +#define PMU_PLLPD_CON_CPLL_PD_ENA_SHIFT (2U) +#define PMU_PLLPD_CON_CPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON_CPLL_PD_ENA_SHIFT) /* 0x00000004 */ +#define PMU_PLLPD_CON_GPLL_PD_ENA_SHIFT (3U) +#define PMU_PLLPD_CON_GPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON_GPLL_PD_ENA_SHIFT) /* 0x00000008 */ +#define PMU_PLLPD_CON_MPLL_PD_ENA_SHIFT (4U) +#define PMU_PLLPD_CON_MPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON_MPLL_PD_ENA_SHIFT) /* 0x00000010 */ +#define PMU_PLLPD_CON_NPLL_PD_ENA_SHIFT (5U) +#define PMU_PLLPD_CON_NPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON_NPLL_PD_ENA_SHIFT) /* 0x00000020 */ +#define PMU_PLLPD_CON_HPLL_PD_ENA_SHIFT (6U) +#define PMU_PLLPD_CON_HPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON_HPLL_PD_ENA_SHIFT) /* 0x00000040 */ +#define PMU_PLLPD_CON_PPLL_PD_ENA_SHIFT (7U) +#define PMU_PLLPD_CON_PPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON_PPLL_PD_ENA_SHIFT) /* 0x00000080 */ +#define PMU_PLLPD_CON_VPLL_PD_ENA_SHIFT (8U) +#define PMU_PLLPD_CON_VPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON_VPLL_PD_ENA_SHIFT) /* 0x00000100 */ +/* PLLPD_SFTCON */ +#define PMU_PLLPD_SFTCON_OFFSET (0xC4U) +#define PMU_PLLPD_SFTCON_APLL_PD_ENA_SHIFT (0U) +#define PMU_PLLPD_SFTCON_APLL_PD_ENA_MASK (0x1U << PMU_PLLPD_SFTCON_APLL_PD_ENA_SHIFT) /* 0x00000001 */ +#define PMU_PLLPD_SFTCON_DPLL_PD_ENA_SHIFT (1U) +#define PMU_PLLPD_SFTCON_DPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_SFTCON_DPLL_PD_ENA_SHIFT) /* 0x00000002 */ +#define PMU_PLLPD_SFTCON_CPLL_PD_ENA_SHIFT (2U) +#define PMU_PLLPD_SFTCON_CPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_SFTCON_CPLL_PD_ENA_SHIFT) /* 0x00000004 */ +#define PMU_PLLPD_SFTCON_GPLL_PD_ENA_SHIFT (3U) +#define PMU_PLLPD_SFTCON_GPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_SFTCON_GPLL_PD_ENA_SHIFT) /* 0x00000008 */ +#define PMU_PLLPD_SFTCON_MPLL_PD_ENA_SHIFT (4U) +#define PMU_PLLPD_SFTCON_MPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_SFTCON_MPLL_PD_ENA_SHIFT) /* 0x00000010 */ +#define PMU_PLLPD_SFTCON_NPLL_PD_ENA_SHIFT (5U) +#define PMU_PLLPD_SFTCON_NPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_SFTCON_NPLL_PD_ENA_SHIFT) /* 0x00000020 */ +#define PMU_PLLPD_SFTCON_HPLL_PD_ENA_SHIFT (6U) +#define PMU_PLLPD_SFTCON_HPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_SFTCON_HPLL_PD_ENA_SHIFT) /* 0x00000040 */ +#define PMU_PLLPD_SFTCON_PPLL_PD_ENA_SHIFT (7U) +#define PMU_PLLPD_SFTCON_PPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_SFTCON_PPLL_PD_ENA_SHIFT) /* 0x00000080 */ +#define PMU_PLLPD_SFTCON_VPLL_PD_ENA_SHIFT (8U) +#define PMU_PLLPD_SFTCON_VPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_SFTCON_VPLL_PD_ENA_SHIFT) /* 0x00000100 */ +/* INFO_TX_CON */ +#define PMU_INFO_TX_CON_OFFSET (0xD0U) +#define PMU_INFO_TX_CON_INFO_TX_EN_SHIFT (0U) +#define PMU_INFO_TX_CON_INFO_TX_EN_MASK (0x1U << PMU_INFO_TX_CON_INFO_TX_EN_SHIFT) /* 0x00000001 */ +#define PMU_INFO_TX_CON_INFO_TX_CON_SHIFT (4U) +#define PMU_INFO_TX_CON_INFO_TX_CON_MASK (0xFU << PMU_INFO_TX_CON_INFO_TX_CON_SHIFT) /* 0x000000F0 */ +#define PMU_INFO_TX_CON_INFO_TX_INTV_TIME_SHIFT (8U) +#define PMU_INFO_TX_CON_INFO_TX_INTV_TIME_MASK (0xFFU << PMU_INFO_TX_CON_INFO_TX_INTV_TIME_SHIFT) /* 0x0000FF00 */ +/* DSU_STABLE_CNT */ +#define PMU_DSU_STABLE_CNT_OFFSET (0x100U) +#define PMU_DSU_STABLE_CNT_STABLE_CNT_SHIFT (0U) +#define PMU_DSU_STABLE_CNT_STABLE_CNT_MASK (0xFFFFFU << PMU_DSU_STABLE_CNT_STABLE_CNT_SHIFT) /* 0x000FFFFF */ +/* PMIC_STABLE_CNT */ +#define PMU_PMIC_STABLE_CNT_OFFSET (0x104U) +#define PMU_PMIC_STABLE_CNT_STABLE_CNT_SHIFT (0U) +#define PMU_PMIC_STABLE_CNT_STABLE_CNT_MASK (0xFFFFFU << PMU_PMIC_STABLE_CNT_STABLE_CNT_SHIFT) /* 0x000FFFFF */ +/* OSC_STABLE_CNT */ +#define PMU_OSC_STABLE_CNT_OFFSET (0x108U) +#define PMU_OSC_STABLE_CNT_STABLE_CNT_SHIFT (0U) +#define PMU_OSC_STABLE_CNT_STABLE_CNT_MASK (0xFFFFFU << PMU_OSC_STABLE_CNT_STABLE_CNT_SHIFT) /* 0x000FFFFF */ +/* WAKEUP_RSTCLR_CNT */ +#define PMU_WAKEUP_RSTCLR_CNT_OFFSET (0x10CU) +#define PMU_WAKEUP_RSTCLR_CNT_WAKEUP_RSTCLR_CNT_SHIFT (0U) +#define PMU_WAKEUP_RSTCLR_CNT_WAKEUP_RSTCLR_CNT_MASK (0xFFFFFU << PMU_WAKEUP_RSTCLR_CNT_WAKEUP_RSTCLR_CNT_SHIFT) /* 0x000FFFFF */ +/* PLL_LOCK_CNT */ +#define PMU_PLL_LOCK_CNT_OFFSET (0x110U) +#define PMU_PLL_LOCK_CNT_PLL_LOCK_CNT_SHIFT (0U) +#define PMU_PLL_LOCK_CNT_PLL_LOCK_CNT_MASK (0xFFFFFU << PMU_PLL_LOCK_CNT_PLL_LOCK_CNT_SHIFT) /* 0x000FFFFF */ +/* DSU_PWRUP_CNT */ +#define PMU_DSU_PWRUP_CNT_OFFSET (0x118U) +#define PMU_DSU_PWRUP_CNT_STABLE_CNT_SHIFT (0U) +#define PMU_DSU_PWRUP_CNT_STABLE_CNT_MASK (0xFFFFFU << PMU_DSU_PWRUP_CNT_STABLE_CNT_SHIFT) /* 0x000FFFFF */ +/* DSU_PWRDN_CNT */ +#define PMU_DSU_PWRDN_CNT_OFFSET (0x11CU) +#define PMU_DSU_PWRDN_CNT_STABLE_CNT_SHIFT (0U) +#define PMU_DSU_PWRDN_CNT_STABLE_CNT_MASK (0xFFFFFU << PMU_DSU_PWRDN_CNT_STABLE_CNT_SHIFT) /* 0x000FFFFF */ +/* GPU_VOLUP_CNT */ +#define PMU_GPU_VOLUP_CNT_OFFSET (0x120U) +#define PMU_GPU_VOLUP_CNT_STABLE_CNT_SHIFT (0U) +#define PMU_GPU_VOLUP_CNT_STABLE_CNT_MASK (0xFFFFFU << PMU_GPU_VOLUP_CNT_STABLE_CNT_SHIFT) /* 0x000FFFFF */ +/* GPU_VOLDN_CNT */ +#define PMU_GPU_VOLDN_CNT_OFFSET (0x124U) +#define PMU_GPU_VOLDN_CNT_STABLE_CNT_SHIFT (0U) +#define PMU_GPU_VOLDN_CNT_STABLE_CNT_MASK (0xFFFFFU << PMU_GPU_VOLDN_CNT_STABLE_CNT_SHIFT) /* 0x000FFFFF */ +/* WAKEUP_TIMEOUT_CNT */ +#define PMU_WAKEUP_TIMEOUT_CNT_OFFSET (0x128U) +#define PMU_WAKEUP_TIMEOUT_CNT_WAKEUP_TIMEOUT_CNT_SHIFT (0U) +#define PMU_WAKEUP_TIMEOUT_CNT_WAKEUP_TIMEOUT_CNT_MASK (0xFFFFFFFFU << PMU_WAKEUP_TIMEOUT_CNT_WAKEUP_TIMEOUT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PWM_SWITCH_CNT */ +#define PMU_PWM_SWITCH_CNT_OFFSET (0x12CU) +#define PMU_PWM_SWITCH_CNT_STABLE_CNT_SHIFT (0U) +#define PMU_PWM_SWITCH_CNT_STABLE_CNT_MASK (0xFFFFFFFFU << PMU_PWM_SWITCH_CNT_STABLE_CNT_SHIFT) /* 0xFFFFFFFF */ +/* DBG_RST_CNT */ +#define PMU_DBG_RST_CNT_OFFSET (0x130U) +#define PMU_DBG_RST_CNT_DBG_RST_CNT_SHIFT (0U) +#define PMU_DBG_RST_CNT_DBG_RST_CNT_MASK (0xFFFFFFFFU << PMU_DBG_RST_CNT_DBG_RST_CNT_SHIFT) /* 0xFFFFFFFF */ +/* SYS_REG0 */ +#define PMU_SYS_REG0_OFFSET (0x180U) +#define PMU_SYS_REG0_PMU_SYS_REG_SHIFT (0U) +#define PMU_SYS_REG0_PMU_SYS_REG_MASK (0xFFFFFFFFU << PMU_SYS_REG0_PMU_SYS_REG_SHIFT) /* 0xFFFFFFFF */ +/* SYS_REG1 */ +#define PMU_SYS_REG1_OFFSET (0x184U) +#define PMU_SYS_REG1_PMU_SYS_REG_SHIFT (0U) +#define PMU_SYS_REG1_PMU_SYS_REG_MASK (0xFFFFFFFFU << PMU_SYS_REG1_PMU_SYS_REG_SHIFT) /* 0xFFFFFFFF */ +/* SYS_REG2 */ +#define PMU_SYS_REG2_OFFSET (0x188U) +#define PMU_SYS_REG2_PMU_SYS_REG_SHIFT (0U) +#define PMU_SYS_REG2_PMU_SYS_REG_MASK (0xFFFFFFFFU << PMU_SYS_REG2_PMU_SYS_REG_SHIFT) /* 0xFFFFFFFF */ +/* SYS_REG3 */ +#define PMU_SYS_REG3_OFFSET (0x18CU) +#define PMU_SYS_REG3_PMU_SYS_REG_SHIFT (0U) +#define PMU_SYS_REG3_PMU_SYS_REG_MASK (0xFFFFFFFFU << PMU_SYS_REG3_PMU_SYS_REG_SHIFT) /* 0xFFFFFFFF */ +/* SYS_REG4 */ +#define PMU_SYS_REG4_OFFSET (0x190U) +#define PMU_SYS_REG4_PMU_SYS_REG_SHIFT (0U) +#define PMU_SYS_REG4_PMU_SYS_REG_MASK (0xFFFFFFFFU << PMU_SYS_REG4_PMU_SYS_REG_SHIFT) /* 0xFFFFFFFF */ +/* SYS_REG5 */ +#define PMU_SYS_REG5_OFFSET (0x194U) +#define PMU_SYS_REG5_PMU_SYS_REG_SHIFT (0U) +#define PMU_SYS_REG5_PMU_SYS_REG_MASK (0xFFFFFFFFU << PMU_SYS_REG5_PMU_SYS_REG_SHIFT) /* 0xFFFFFFFF */ +/* SYS_REG6 */ +#define PMU_SYS_REG6_OFFSET (0x198U) +#define PMU_SYS_REG6_PMU_SYS_REG_SHIFT (0U) +#define PMU_SYS_REG6_PMU_SYS_REG_MASK (0xFFFFFFFFU << PMU_SYS_REG6_PMU_SYS_REG_SHIFT) /* 0xFFFFFFFF */ +/* SYS_REG7 */ +#define PMU_SYS_REG7_OFFSET (0x19CU) +#define PMU_SYS_REG7_PMU_SYS_REG_SHIFT (0U) +#define PMU_SYS_REG7_PMU_SYS_REG_MASK (0xFFFFFFFFU << PMU_SYS_REG7_PMU_SYS_REG_SHIFT) /* 0xFFFFFFFF */ +/* DSU_PWR_CON */ +#define PMU_DSU_PWR_CON_OFFSET (0x300U) +#define PMU_DSU_PWR_CON_DSU_PWRDN_ENA_SHIFT (2U) +#define PMU_DSU_PWR_CON_DSU_PWRDN_ENA_MASK (0x1U << PMU_DSU_PWR_CON_DSU_PWRDN_ENA_SHIFT) /* 0x00000004 */ +#define PMU_DSU_PWR_CON_DSU_PWROFF_ENA_SHIFT (3U) +#define PMU_DSU_PWR_CON_DSU_PWROFF_ENA_MASK (0x1U << PMU_DSU_PWR_CON_DSU_PWROFF_ENA_SHIFT) /* 0x00000008 */ +#define PMU_DSU_PWR_CON_DSU_RET_ENA_SHIFT (6U) +#define PMU_DSU_PWR_CON_DSU_RET_ENA_MASK (0x1U << PMU_DSU_PWR_CON_DSU_RET_ENA_SHIFT) /* 0x00000040 */ +#define PMU_DSU_PWR_CON_CLUSTER_CLK_SRC_GATE_ENA_SHIFT (7U) +#define PMU_DSU_PWR_CON_CLUSTER_CLK_SRC_GATE_ENA_MASK (0x1U << PMU_DSU_PWR_CON_CLUSTER_CLK_SRC_GATE_ENA_SHIFT) /* 0x00000080 */ +/* DSU_PWR_SFTCON */ +#define PMU_DSU_PWR_SFTCON_OFFSET (0x304U) +#define PMU_DSU_PWR_SFTCON_DSU_PWRDN_ENA_SHIFT (0U) +#define PMU_DSU_PWR_SFTCON_DSU_PWRDN_ENA_MASK (0x1U << PMU_DSU_PWR_SFTCON_DSU_PWRDN_ENA_SHIFT) /* 0x00000001 */ +#define PMU_DSU_PWR_SFTCON_CLUSTER_CLK_SRC_GATE_CFG_SHIFT (7U) +#define PMU_DSU_PWR_SFTCON_CLUSTER_CLK_SRC_GATE_CFG_MASK (0x1U << PMU_DSU_PWR_SFTCON_CLUSTER_CLK_SRC_GATE_CFG_SHIFT) /* 0x00000080 */ +/* DSU_AUTO_CON */ +#define PMU_DSU_AUTO_CON_OFFSET (0x308U) +#define PMU_DSU_AUTO_CON_DSU_LP_ENA_SHIFT (0U) +#define PMU_DSU_AUTO_CON_DSU_LP_ENA_MASK (0x1U << PMU_DSU_AUTO_CON_DSU_LP_ENA_SHIFT) /* 0x00000001 */ +#define PMU_DSU_AUTO_CON_DSU_INT_WAKEUP_CLUSTER_ENA_SHIFT (1U) +#define PMU_DSU_AUTO_CON_DSU_INT_WAKEUP_CLUSTER_ENA_MASK (0x1U << PMU_DSU_AUTO_CON_DSU_INT_WAKEUP_CLUSTER_ENA_SHIFT) /* 0x00000002 */ +#define PMU_DSU_AUTO_CON_DSU_INT_MASK_ENA_SHIFT (2U) +#define PMU_DSU_AUTO_CON_DSU_INT_MASK_ENA_MASK (0x1U << PMU_DSU_AUTO_CON_DSU_INT_MASK_ENA_SHIFT) /* 0x00000004 */ +#define PMU_DSU_AUTO_CON_DSU_SFT_WAKEUP_CLUSTER_ENA_SHIFT (3U) +#define PMU_DSU_AUTO_CON_DSU_SFT_WAKEUP_CLUSTER_ENA_MASK (0x1U << PMU_DSU_AUTO_CON_DSU_SFT_WAKEUP_CLUSTER_ENA_SHIFT) /* 0x00000008 */ +#define PMU_DSU_AUTO_CON_DSU_AUTO_RET_ENA_SHIFT (4U) +#define PMU_DSU_AUTO_CON_DSU_AUTO_RET_ENA_MASK (0x1U << PMU_DSU_AUTO_CON_DSU_AUTO_RET_ENA_SHIFT) /* 0x00000010 */ +/* DSU_PWR_STATE */ +#define PMU_DSU_PWR_STATE_OFFSET (0x30CU) +#define PMU_DSU_PWR_STATE (0x0U) +#define PMU_DSU_PWR_STATE_CPU0_POWER_STATE_SHIFT (0U) +#define PMU_DSU_PWR_STATE_CPU0_POWER_STATE_MASK (0x7U << PMU_DSU_PWR_STATE_CPU0_POWER_STATE_SHIFT) /* 0x00000007 */ +#define PMU_DSU_PWR_STATE_CPU1_POWER_STATE_SHIFT (4U) +#define PMU_DSU_PWR_STATE_CPU1_POWER_STATE_MASK (0x7U << PMU_DSU_PWR_STATE_CPU1_POWER_STATE_SHIFT) /* 0x00000070 */ +#define PMU_DSU_PWR_STATE_CPU2_POWER_STATE_SHIFT (8U) +#define PMU_DSU_PWR_STATE_CPU2_POWER_STATE_MASK (0x7U << PMU_DSU_PWR_STATE_CPU2_POWER_STATE_SHIFT) /* 0x00000700 */ +#define PMU_DSU_PWR_STATE_CPU3_POWER_STATE_SHIFT (12U) +#define PMU_DSU_PWR_STATE_CPU3_POWER_STATE_MASK (0x7U << PMU_DSU_PWR_STATE_CPU3_POWER_STATE_SHIFT) /* 0x00007000 */ +#define PMU_DSU_PWR_STATE_DSU_POWER_STATE_SHIFT (16U) +#define PMU_DSU_PWR_STATE_DSU_POWER_STATE_MASK (0x7U << PMU_DSU_PWR_STATE_DSU_POWER_STATE_SHIFT) /* 0x00070000 */ +/* CPU_AUTO_PWR_CON0 */ +#define PMU_CPU_AUTO_PWR_CON0_OFFSET (0x310U) +#define PMU_CPU_AUTO_PWR_CON0_CPU0_AUTO_PWRDN_ENA_SHIFT (0U) +#define PMU_CPU_AUTO_PWR_CON0_CPU0_AUTO_PWRDN_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU0_AUTO_PWRDN_ENA_SHIFT) /* 0x00000001 */ +#define PMU_CPU_AUTO_PWR_CON0_CPU0_INT_WAKEUP_ENA_SHIFT (1U) +#define PMU_CPU_AUTO_PWR_CON0_CPU0_INT_WAKEUP_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU0_INT_WAKEUP_ENA_SHIFT) /* 0x00000002 */ +#define PMU_CPU_AUTO_PWR_CON0_CPU0_INT_MASK_ENA_SHIFT (2U) +#define PMU_CPU_AUTO_PWR_CON0_CPU0_INT_MASK_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU0_INT_MASK_ENA_SHIFT) /* 0x00000004 */ +#define PMU_CPU_AUTO_PWR_CON0_CPU0_SFT_WAKEUP_PWRDN_ENA_SHIFT (3U) +#define PMU_CPU_AUTO_PWR_CON0_CPU0_SFT_WAKEUP_PWRDN_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU0_SFT_WAKEUP_PWRDN_ENA_SHIFT) /* 0x00000008 */ +#define PMU_CPU_AUTO_PWR_CON0_CPU0_AUTO_RET_ENA_SHIFT (4U) +#define PMU_CPU_AUTO_PWR_CON0_CPU0_AUTO_RET_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU0_AUTO_RET_ENA_SHIFT) /* 0x00000010 */ +#define PMU_CPU_AUTO_PWR_CON0_CPU0_SFT_WAKEUP_RET_ENA_SHIFT (5U) +#define PMU_CPU_AUTO_PWR_CON0_CPU0_SFT_WAKEUP_RET_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU0_SFT_WAKEUP_RET_ENA_SHIFT) /* 0x00000020 */ +#define PMU_CPU_AUTO_PWR_CON0_CPU0_DBG_RECOV_ENA_SHIFT (6U) +#define PMU_CPU_AUTO_PWR_CON0_CPU0_DBG_RECOV_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU0_DBG_RECOV_ENA_SHIFT) /* 0x00000040 */ +#define PMU_CPU_AUTO_PWR_CON0_CPU0_DBG_RECOV_RSTSRC_SHIFT (7U) +#define PMU_CPU_AUTO_PWR_CON0_CPU0_DBG_RECOV_RSTSRC_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU0_DBG_RECOV_RSTSRC_SHIFT) /* 0x00000080 */ +#define PMU_CPU_AUTO_PWR_CON0_CPU1_AUTO_PWRDN_ENA_SHIFT (8U) +#define PMU_CPU_AUTO_PWR_CON0_CPU1_AUTO_PWRDN_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU1_AUTO_PWRDN_ENA_SHIFT) /* 0x00000100 */ +#define PMU_CPU_AUTO_PWR_CON0_CPU1_INT_WAKEUP_ENA_SHIFT (9U) +#define PMU_CPU_AUTO_PWR_CON0_CPU1_INT_WAKEUP_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU1_INT_WAKEUP_ENA_SHIFT) /* 0x00000200 */ +#define PMU_CPU_AUTO_PWR_CON0_CPU1_INT_MASK_ENA_SHIFT (10U) +#define PMU_CPU_AUTO_PWR_CON0_CPU1_INT_MASK_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU1_INT_MASK_ENA_SHIFT) /* 0x00000400 */ +#define PMU_CPU_AUTO_PWR_CON0_CPU1_SFT_WAKEUP_PWRDN_ENA_SHIFT (11U) +#define PMU_CPU_AUTO_PWR_CON0_CPU1_SFT_WAKEUP_PWRDN_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU1_SFT_WAKEUP_PWRDN_ENA_SHIFT) /* 0x00000800 */ +#define PMU_CPU_AUTO_PWR_CON0_CPU1_AUTO_RET_ENA_SHIFT (12U) +#define PMU_CPU_AUTO_PWR_CON0_CPU1_AUTO_RET_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU1_AUTO_RET_ENA_SHIFT) /* 0x00001000 */ +#define PMU_CPU_AUTO_PWR_CON0_CPU1_SFT_WAKEUP_RET_ENA_SHIFT (13U) +#define PMU_CPU_AUTO_PWR_CON0_CPU1_SFT_WAKEUP_RET_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU1_SFT_WAKEUP_RET_ENA_SHIFT) /* 0x00002000 */ +#define PMU_CPU_AUTO_PWR_CON0_CPU1_DBG_RECOV_ENA_SHIFT (14U) +#define PMU_CPU_AUTO_PWR_CON0_CPU1_DBG_RECOV_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU1_DBG_RECOV_ENA_SHIFT) /* 0x00004000 */ +#define PMU_CPU_AUTO_PWR_CON0_CPU1_DBG_RECOV_RSTSRC_SHIFT (15U) +#define PMU_CPU_AUTO_PWR_CON0_CPU1_DBG_RECOV_RSTSRC_MASK (0x1U << PMU_CPU_AUTO_PWR_CON0_CPU1_DBG_RECOV_RSTSRC_SHIFT) /* 0x00008000 */ +/* CPU_AUTO_PWR_CON1 */ +#define PMU_CPU_AUTO_PWR_CON1_OFFSET (0x314U) +#define PMU_CPU_AUTO_PWR_CON1_CPU2_AUTO_PWRDN_ENA_SHIFT (0U) +#define PMU_CPU_AUTO_PWR_CON1_CPU2_AUTO_PWRDN_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU2_AUTO_PWRDN_ENA_SHIFT) /* 0x00000001 */ +#define PMU_CPU_AUTO_PWR_CON1_CPU2_INT_WAKEUP_ENA_SHIFT (1U) +#define PMU_CPU_AUTO_PWR_CON1_CPU2_INT_WAKEUP_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU2_INT_WAKEUP_ENA_SHIFT) /* 0x00000002 */ +#define PMU_CPU_AUTO_PWR_CON1_CPU2_INT_MASK_ENA_SHIFT (2U) +#define PMU_CPU_AUTO_PWR_CON1_CPU2_INT_MASK_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU2_INT_MASK_ENA_SHIFT) /* 0x00000004 */ +#define PMU_CPU_AUTO_PWR_CON1_CPU2_SFT_WAKEUP_PWRDN_ENA_SHIFT (3U) +#define PMU_CPU_AUTO_PWR_CON1_CPU2_SFT_WAKEUP_PWRDN_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU2_SFT_WAKEUP_PWRDN_ENA_SHIFT) /* 0x00000008 */ +#define PMU_CPU_AUTO_PWR_CON1_CPU2_AUTO_RET_ENA_SHIFT (4U) +#define PMU_CPU_AUTO_PWR_CON1_CPU2_AUTO_RET_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU2_AUTO_RET_ENA_SHIFT) /* 0x00000010 */ +#define PMU_CPU_AUTO_PWR_CON1_CPU2_SFT_WAKEUP_RET_ENA_SHIFT (5U) +#define PMU_CPU_AUTO_PWR_CON1_CPU2_SFT_WAKEUP_RET_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU2_SFT_WAKEUP_RET_ENA_SHIFT) /* 0x00000020 */ +#define PMU_CPU_AUTO_PWR_CON1_CPU2_DBG_RECOV_ENA_SHIFT (6U) +#define PMU_CPU_AUTO_PWR_CON1_CPU2_DBG_RECOV_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU2_DBG_RECOV_ENA_SHIFT) /* 0x00000040 */ +#define PMU_CPU_AUTO_PWR_CON1_CPU2_DBG_RECOV_RSTSRC_SHIFT (7U) +#define PMU_CPU_AUTO_PWR_CON1_CPU2_DBG_RECOV_RSTSRC_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU2_DBG_RECOV_RSTSRC_SHIFT) /* 0x00000080 */ +#define PMU_CPU_AUTO_PWR_CON1_CPU3_AUTO_PWRDN_ENA_SHIFT (8U) +#define PMU_CPU_AUTO_PWR_CON1_CPU3_AUTO_PWRDN_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU3_AUTO_PWRDN_ENA_SHIFT) /* 0x00000100 */ +#define PMU_CPU_AUTO_PWR_CON1_CPU3_INT_WAKEUP_ENA_SHIFT (9U) +#define PMU_CPU_AUTO_PWR_CON1_CPU3_INT_WAKEUP_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU3_INT_WAKEUP_ENA_SHIFT) /* 0x00000200 */ +#define PMU_CPU_AUTO_PWR_CON1_CPU3_INT_MASK_ENA_SHIFT (10U) +#define PMU_CPU_AUTO_PWR_CON1_CPU3_INT_MASK_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU3_INT_MASK_ENA_SHIFT) /* 0x00000400 */ +#define PMU_CPU_AUTO_PWR_CON1_CPU3_SFT_WAKEUP_PWRDN_ENA_SHIFT (11U) +#define PMU_CPU_AUTO_PWR_CON1_CPU3_SFT_WAKEUP_PWRDN_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU3_SFT_WAKEUP_PWRDN_ENA_SHIFT) /* 0x00000800 */ +#define PMU_CPU_AUTO_PWR_CON1_CPU3_AUTO_RET_ENA_SHIFT (12U) +#define PMU_CPU_AUTO_PWR_CON1_CPU3_AUTO_RET_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU3_AUTO_RET_ENA_SHIFT) /* 0x00001000 */ +#define PMU_CPU_AUTO_PWR_CON1_CPU3_SFT_WAKEUP_RET_ENA_SHIFT (13U) +#define PMU_CPU_AUTO_PWR_CON1_CPU3_SFT_WAKEUP_RET_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU3_SFT_WAKEUP_RET_ENA_SHIFT) /* 0x00002000 */ +#define PMU_CPU_AUTO_PWR_CON1_CPU3_DBG_RECOV_ENA_SHIFT (14U) +#define PMU_CPU_AUTO_PWR_CON1_CPU3_DBG_RECOV_ENA_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU3_DBG_RECOV_ENA_SHIFT) /* 0x00004000 */ +#define PMU_CPU_AUTO_PWR_CON1_CPU3_DBG_RECOV_RSTSRC_SHIFT (15U) +#define PMU_CPU_AUTO_PWR_CON1_CPU3_DBG_RECOV_RSTSRC_MASK (0x1U << PMU_CPU_AUTO_PWR_CON1_CPU3_DBG_RECOV_RSTSRC_SHIFT) /* 0x00008000 */ +/* CPU_PWR_SFTCON */ +#define PMU_CPU_PWR_SFTCON_OFFSET (0x318U) +#define PMU_CPU_PWR_SFTCON_CPU0_SFT_PWRDN_ENA_SHIFT (0U) +#define PMU_CPU_PWR_SFTCON_CPU0_SFT_PWRDN_ENA_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU0_SFT_PWRDN_ENA_SHIFT) /* 0x00000001 */ +#define PMU_CPU_PWR_SFTCON_CPU0_SFT_PREQ_OFF_SHIFT (1U) +#define PMU_CPU_PWR_SFTCON_CPU0_SFT_PREQ_OFF_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU0_SFT_PREQ_OFF_SHIFT) /* 0x00000002 */ +#define PMU_CPU_PWR_SFTCON_CPU0_SFT_PREQ_ON_SHIFT (2U) +#define PMU_CPU_PWR_SFTCON_CPU0_SFT_PREQ_ON_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU0_SFT_PREQ_ON_SHIFT) /* 0x00000004 */ +#define PMU_CPU_PWR_SFTCON_CPU0_SFT_PREQ_RET_SHIFT (3U) +#define PMU_CPU_PWR_SFTCON_CPU0_SFT_PREQ_RET_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU0_SFT_PREQ_RET_SHIFT) /* 0x00000008 */ +#define PMU_CPU_PWR_SFTCON_CPU1_SFT_PWRDN_ENA_SHIFT (4U) +#define PMU_CPU_PWR_SFTCON_CPU1_SFT_PWRDN_ENA_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU1_SFT_PWRDN_ENA_SHIFT) /* 0x00000010 */ +#define PMU_CPU_PWR_SFTCON_CPU1_SFT_PREQ_OFF_SHIFT (5U) +#define PMU_CPU_PWR_SFTCON_CPU1_SFT_PREQ_OFF_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU1_SFT_PREQ_OFF_SHIFT) /* 0x00000020 */ +#define PMU_CPU_PWR_SFTCON_CPU1_SFT_PREQ_ON_SHIFT (6U) +#define PMU_CPU_PWR_SFTCON_CPU1_SFT_PREQ_ON_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU1_SFT_PREQ_ON_SHIFT) /* 0x00000040 */ +#define PMU_CPU_PWR_SFTCON_CPU1_SFT_PREQ_RET_SHIFT (7U) +#define PMU_CPU_PWR_SFTCON_CPU1_SFT_PREQ_RET_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU1_SFT_PREQ_RET_SHIFT) /* 0x00000080 */ +#define PMU_CPU_PWR_SFTCON_CPU2_SFT_PWRDN_ENA_SHIFT (8U) +#define PMU_CPU_PWR_SFTCON_CPU2_SFT_PWRDN_ENA_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU2_SFT_PWRDN_ENA_SHIFT) /* 0x00000100 */ +#define PMU_CPU_PWR_SFTCON_CPU2_SFT_PREQ_OFF_SHIFT (9U) +#define PMU_CPU_PWR_SFTCON_CPU2_SFT_PREQ_OFF_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU2_SFT_PREQ_OFF_SHIFT) /* 0x00000200 */ +#define PMU_CPU_PWR_SFTCON_CPU2_SFT_PREQ_ON_SHIFT (10U) +#define PMU_CPU_PWR_SFTCON_CPU2_SFT_PREQ_ON_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU2_SFT_PREQ_ON_SHIFT) /* 0x00000400 */ +#define PMU_CPU_PWR_SFTCON_CPU2_SFT_PREQ_RET_SHIFT (11U) +#define PMU_CPU_PWR_SFTCON_CPU2_SFT_PREQ_RET_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU2_SFT_PREQ_RET_SHIFT) /* 0x00000800 */ +#define PMU_CPU_PWR_SFTCON_CPU3_SFT_PWRDN_ENA_SHIFT (12U) +#define PMU_CPU_PWR_SFTCON_CPU3_SFT_PWRDN_ENA_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU3_SFT_PWRDN_ENA_SHIFT) /* 0x00001000 */ +#define PMU_CPU_PWR_SFTCON_CPU3_SFT_PREQ_OFF_SHIFT (13U) +#define PMU_CPU_PWR_SFTCON_CPU3_SFT_PREQ_OFF_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU3_SFT_PREQ_OFF_SHIFT) /* 0x00002000 */ +#define PMU_CPU_PWR_SFTCON_CPU3_SFT_PREQ_ON_SHIFT (14U) +#define PMU_CPU_PWR_SFTCON_CPU3_SFT_PREQ_ON_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU3_SFT_PREQ_ON_SHIFT) /* 0x00004000 */ +#define PMU_CPU_PWR_SFTCON_CPU3_SFT_PREQ_RET_SHIFT (15U) +#define PMU_CPU_PWR_SFTCON_CPU3_SFT_PREQ_RET_MASK (0x1U << PMU_CPU_PWR_SFTCON_CPU3_SFT_PREQ_RET_SHIFT) /* 0x00008000 */ +/* CLUSTER_PWR_ST */ +#define PMU_CLUSTER_PWR_ST_OFFSET (0x31CU) +#define PMU_CLUSTER_PWR_ST (0x0U) +#define PMU_CLUSTER_PWR_ST_CPU0_DWN_STATE_SHIFT (0U) +#define PMU_CLUSTER_PWR_ST_CPU0_DWN_STATE_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU0_DWN_STATE_SHIFT) /* 0x00000001 */ +#define PMU_CLUSTER_PWR_ST_CPU1_DWN_STATE_SHIFT (1U) +#define PMU_CLUSTER_PWR_ST_CPU1_DWN_STATE_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU1_DWN_STATE_SHIFT) /* 0x00000002 */ +#define PMU_CLUSTER_PWR_ST_CPU2_DWN_STATE_SHIFT (2U) +#define PMU_CLUSTER_PWR_ST_CPU2_DWN_STATE_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU2_DWN_STATE_SHIFT) /* 0x00000004 */ +#define PMU_CLUSTER_PWR_ST_CPU3_DWN_STATE_SHIFT (3U) +#define PMU_CLUSTER_PWR_ST_CPU3_DWN_STATE_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU3_DWN_STATE_SHIFT) /* 0x00000008 */ +#define PMU_CLUSTER_PWR_ST_DSU_DWN_STATE_SHIFT (4U) +#define PMU_CLUSTER_PWR_ST_DSU_DWN_STATE_MASK (0x1U << PMU_CLUSTER_PWR_ST_DSU_DWN_STATE_SHIFT) /* 0x00000010 */ +#define PMU_CLUSTER_PWR_ST_CLUSTER_PREQ_ACCEPED_SHIFT (7U) +#define PMU_CLUSTER_PWR_ST_CLUSTER_PREQ_ACCEPED_MASK (0x1U << PMU_CLUSTER_PWR_ST_CLUSTER_PREQ_ACCEPED_SHIFT) /* 0x00000080 */ +#define PMU_CLUSTER_PWR_ST_CLUSTERPACTIVE_BIT_MEMRET_SHIFT (8U) +#define PMU_CLUSTER_PWR_ST_CLUSTERPACTIVE_BIT_MEMRET_MASK (0x1U << PMU_CLUSTER_PWR_ST_CLUSTERPACTIVE_BIT_MEMRET_SHIFT) /* 0x00000100 */ +#define PMU_CLUSTER_PWR_ST_CLUSTERPACTIVE_BIT_FUNCRET_SHIFT (9U) +#define PMU_CLUSTER_PWR_ST_CLUSTERPACTIVE_BIT_FUNCRET_MASK (0x1U << PMU_CLUSTER_PWR_ST_CLUSTERPACTIVE_BIT_FUNCRET_SHIFT) /* 0x00000200 */ +#define PMU_CLUSTER_PWR_ST_CLUSTERPACTIVE_BIT_ON_SHIFT (10U) +#define PMU_CLUSTER_PWR_ST_CLUSTERPACTIVE_BIT_ON_MASK (0x1U << PMU_CLUSTER_PWR_ST_CLUSTERPACTIVE_BIT_ON_SHIFT) /* 0x00000400 */ +#define PMU_CLUSTER_PWR_ST_CLUSTERPACTIVE_BIT_FULL_SHIFT (11U) +#define PMU_CLUSTER_PWR_ST_CLUSTERPACTIVE_BIT_FULL_MASK (0x1U << PMU_CLUSTER_PWR_ST_CLUSTERPACTIVE_BIT_FULL_SHIFT) /* 0x00000800 */ +#define PMU_CLUSTER_PWR_ST_CPU0_PREQ_ACCEPED_SHIFT (12U) +#define PMU_CLUSTER_PWR_ST_CPU0_PREQ_ACCEPED_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU0_PREQ_ACCEPED_SHIFT) /* 0x00001000 */ +#define PMU_CLUSTER_PWR_ST_CPU1_PREQ_ACCEPED_SHIFT (13U) +#define PMU_CLUSTER_PWR_ST_CPU1_PREQ_ACCEPED_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU1_PREQ_ACCEPED_SHIFT) /* 0x00002000 */ +#define PMU_CLUSTER_PWR_ST_CPU2_PREQ_ACCEPED_SHIFT (14U) +#define PMU_CLUSTER_PWR_ST_CPU2_PREQ_ACCEPED_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU2_PREQ_ACCEPED_SHIFT) /* 0x00004000 */ +#define PMU_CLUSTER_PWR_ST_CPU3_PREQ_ACCEPED_SHIFT (15U) +#define PMU_CLUSTER_PWR_ST_CPU3_PREQ_ACCEPED_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU3_PREQ_ACCEPED_SHIFT) /* 0x00008000 */ +#define PMU_CLUSTER_PWR_ST_CPU0_BIT_EMUOFF_SHIFT (16U) +#define PMU_CLUSTER_PWR_ST_CPU0_BIT_EMUOFF_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU0_BIT_EMUOFF_SHIFT) /* 0x00010000 */ +#define PMU_CLUSTER_PWR_ST_CPU0_BIT_FULLRET_SHIFT (17U) +#define PMU_CLUSTER_PWR_ST_CPU0_BIT_FULLRET_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU0_BIT_FULLRET_SHIFT) /* 0x00020000 */ +#define PMU_CLUSTER_PWR_ST_CPU0_BIT_FUNCRET_SHIFT (18U) +#define PMU_CLUSTER_PWR_ST_CPU0_BIT_FUNCRET_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU0_BIT_FUNCRET_SHIFT) /* 0x00040000 */ +#define PMU_CLUSTER_PWR_ST_CPU0_BIT_ON_SHIFT (19U) +#define PMU_CLUSTER_PWR_ST_CPU0_BIT_ON_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU0_BIT_ON_SHIFT) /* 0x00080000 */ +#define PMU_CLUSTER_PWR_ST_CPU1_BIT_EMUOFF_SHIFT (20U) +#define PMU_CLUSTER_PWR_ST_CPU1_BIT_EMUOFF_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU1_BIT_EMUOFF_SHIFT) /* 0x00100000 */ +#define PMU_CLUSTER_PWR_ST_CPU1_BIT_FULLRET_SHIFT (21U) +#define PMU_CLUSTER_PWR_ST_CPU1_BIT_FULLRET_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU1_BIT_FULLRET_SHIFT) /* 0x00200000 */ +#define PMU_CLUSTER_PWR_ST_CPU1_BIT_FUNCRET_SHIFT (22U) +#define PMU_CLUSTER_PWR_ST_CPU1_BIT_FUNCRET_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU1_BIT_FUNCRET_SHIFT) /* 0x00400000 */ +#define PMU_CLUSTER_PWR_ST_CPU1_BIT_ON_SHIFT (23U) +#define PMU_CLUSTER_PWR_ST_CPU1_BIT_ON_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU1_BIT_ON_SHIFT) /* 0x00800000 */ +#define PMU_CLUSTER_PWR_ST_CPU2_BIT_EMUOFF_SHIFT (24U) +#define PMU_CLUSTER_PWR_ST_CPU2_BIT_EMUOFF_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU2_BIT_EMUOFF_SHIFT) /* 0x01000000 */ +#define PMU_CLUSTER_PWR_ST_CPU2_BIT_FULLRET_SHIFT (25U) +#define PMU_CLUSTER_PWR_ST_CPU2_BIT_FULLRET_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU2_BIT_FULLRET_SHIFT) /* 0x02000000 */ +#define PMU_CLUSTER_PWR_ST_CPU2_BIT_FUNCRET_SHIFT (26U) +#define PMU_CLUSTER_PWR_ST_CPU2_BIT_FUNCRET_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU2_BIT_FUNCRET_SHIFT) /* 0x04000000 */ +#define PMU_CLUSTER_PWR_ST_CPU2_BIT_ON_SHIFT (27U) +#define PMU_CLUSTER_PWR_ST_CPU2_BIT_ON_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU2_BIT_ON_SHIFT) /* 0x08000000 */ +#define PMU_CLUSTER_PWR_ST_CPU3_BIT_EMUOFF_SHIFT (28U) +#define PMU_CLUSTER_PWR_ST_CPU3_BIT_EMUOFF_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU3_BIT_EMUOFF_SHIFT) /* 0x10000000 */ +#define PMU_CLUSTER_PWR_ST_CPU3_BIT_FULLRET_SHIFT (29U) +#define PMU_CLUSTER_PWR_ST_CPU3_BIT_FULLRET_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU3_BIT_FULLRET_SHIFT) /* 0x20000000 */ +#define PMU_CLUSTER_PWR_ST_CPU3_BIT_FUNCRET_SHIFT (30U) +#define PMU_CLUSTER_PWR_ST_CPU3_BIT_FUNCRET_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU3_BIT_FUNCRET_SHIFT) /* 0x40000000 */ +#define PMU_CLUSTER_PWR_ST_CPU3_BIT_ON_SHIFT (31U) +#define PMU_CLUSTER_PWR_ST_CPU3_BIT_ON_MASK (0x1U << PMU_CLUSTER_PWR_ST_CPU3_BIT_ON_SHIFT) /* 0x80000000 */ +/* CLUSTER_IDLE_CON */ +#define PMU_CLUSTER_IDLE_CON_OFFSET (0x320U) +#define PMU_CLUSTER_IDLE_CON_IDLE_REQ_CPU_SHIFT (0U) +#define PMU_CLUSTER_IDLE_CON_IDLE_REQ_CPU_MASK (0x1U << PMU_CLUSTER_IDLE_CON_IDLE_REQ_CPU_SHIFT) /* 0x00000001 */ +#define PMU_CLUSTER_IDLE_CON_DBG_PWRQ_REQ_SHIFT (1U) +#define PMU_CLUSTER_IDLE_CON_DBG_PWRQ_REQ_MASK (0x1U << PMU_CLUSTER_IDLE_CON_DBG_PWRQ_REQ_SHIFT) /* 0x00000002 */ +#define PMU_CLUSTER_IDLE_CON_CORE2GIC_PWRQ_REQ_SHIFT (2U) +#define PMU_CLUSTER_IDLE_CON_CORE2GIC_PWRQ_REQ_MASK (0x1U << PMU_CLUSTER_IDLE_CON_CORE2GIC_PWRQ_REQ_SHIFT) /* 0x00000004 */ +#define PMU_CLUSTER_IDLE_CON_GIC2CORE_PWRQ_REQ_SHIFT (3U) +#define PMU_CLUSTER_IDLE_CON_GIC2CORE_PWRQ_REQ_MASK (0x1U << PMU_CLUSTER_IDLE_CON_GIC2CORE_PWRQ_REQ_SHIFT) /* 0x00000008 */ +/* CLUSTER_IDLE_SFTCON */ +#define PMU_CLUSTER_IDLE_SFTCON_OFFSET (0x324U) +#define PMU_CLUSTER_IDLE_SFTCON_IDLE_REQ_CPU_SHIFT (0U) +#define PMU_CLUSTER_IDLE_SFTCON_IDLE_REQ_CPU_MASK (0x1U << PMU_CLUSTER_IDLE_SFTCON_IDLE_REQ_CPU_SHIFT) /* 0x00000001 */ +#define PMU_CLUSTER_IDLE_SFTCON_DBG_PWRQ_REQ_SHIFT (1U) +#define PMU_CLUSTER_IDLE_SFTCON_DBG_PWRQ_REQ_MASK (0x1U << PMU_CLUSTER_IDLE_SFTCON_DBG_PWRQ_REQ_SHIFT) /* 0x00000002 */ +#define PMU_CLUSTER_IDLE_SFTCON_CORE2GIC_PWRQ_REQ_SHIFT (2U) +#define PMU_CLUSTER_IDLE_SFTCON_CORE2GIC_PWRQ_REQ_MASK (0x1U << PMU_CLUSTER_IDLE_SFTCON_CORE2GIC_PWRQ_REQ_SHIFT) /* 0x00000004 */ +#define PMU_CLUSTER_IDLE_SFTCON_GIC2CORE_PWRQ_REQ_SHIFT (3U) +#define PMU_CLUSTER_IDLE_SFTCON_GIC2CORE_PWRQ_REQ_MASK (0x1U << PMU_CLUSTER_IDLE_SFTCON_GIC2CORE_PWRQ_REQ_SHIFT) /* 0x00000008 */ +/* CLUSTER_IDLE_ACK */ +#define PMU_CLUSTER_IDLE_ACK_OFFSET (0x328U) +#define PMU_CLUSTER_IDLE_ACK (0x0U) +#define PMU_CLUSTER_IDLE_ACK_IDLE_ACK_CPU_SHIFT (0U) +#define PMU_CLUSTER_IDLE_ACK_IDLE_ACK_CPU_MASK (0x1U << PMU_CLUSTER_IDLE_ACK_IDLE_ACK_CPU_SHIFT) /* 0x00000001 */ +#define PMU_CLUSTER_IDLE_ACK_DBG_PWRQ_ACCEPT_SHIFT (1U) +#define PMU_CLUSTER_IDLE_ACK_DBG_PWRQ_ACCEPT_MASK (0x1U << PMU_CLUSTER_IDLE_ACK_DBG_PWRQ_ACCEPT_SHIFT) /* 0x00000002 */ +#define PMU_CLUSTER_IDLE_ACK_CORE2GIC_PWRQ_ACCEPT_SHIFT (2U) +#define PMU_CLUSTER_IDLE_ACK_CORE2GIC_PWRQ_ACCEPT_MASK (0x1U << PMU_CLUSTER_IDLE_ACK_CORE2GIC_PWRQ_ACCEPT_SHIFT) /* 0x00000004 */ +#define PMU_CLUSTER_IDLE_ACK_GIC2CORE_PWRQ_ACCEPT_SHIFT (3U) +#define PMU_CLUSTER_IDLE_ACK_GIC2CORE_PWRQ_ACCEPT_MASK (0x1U << PMU_CLUSTER_IDLE_ACK_GIC2CORE_PWRQ_ACCEPT_SHIFT) /* 0x00000008 */ +/* CLUSTER_IDLE_ST */ +#define PMU_CLUSTER_IDLE_ST_OFFSET (0x32CU) +#define PMU_CLUSTER_IDLE_ST (0x0U) +#define PMU_CLUSTER_IDLE_ST_IDLE_CPU_SHIFT (0U) +#define PMU_CLUSTER_IDLE_ST_IDLE_CPU_MASK (0x1U << PMU_CLUSTER_IDLE_ST_IDLE_CPU_SHIFT) /* 0x00000001 */ +#define PMU_CLUSTER_IDLE_ST_DBG_PWRQ_ACTIVE_SHIFT (1U) +#define PMU_CLUSTER_IDLE_ST_DBG_PWRQ_ACTIVE_MASK (0x1U << PMU_CLUSTER_IDLE_ST_DBG_PWRQ_ACTIVE_SHIFT) /* 0x00000002 */ +#define PMU_CLUSTER_IDLE_ST_CORE2GIC_PWRQ_ACTIVE_SHIFT (2U) +#define PMU_CLUSTER_IDLE_ST_CORE2GIC_PWRQ_ACTIVE_MASK (0x1U << PMU_CLUSTER_IDLE_ST_CORE2GIC_PWRQ_ACTIVE_SHIFT) /* 0x00000004 */ +#define PMU_CLUSTER_IDLE_ST_GIC2CORE_PWRQ_ACTIVE_SHIFT (3U) +#define PMU_CLUSTER_IDLE_ST_GIC2CORE_PWRQ_ACTIVE_MASK (0x1U << PMU_CLUSTER_IDLE_ST_GIC2CORE_PWRQ_ACTIVE_SHIFT) /* 0x00000008 */ +/* DBG_PWR_CON */ +#define PMU_DBG_PWR_CON_OFFSET (0x330U) +#define PMU_DBG_PWR_CON_CPU0_DBG_PWRUP_REQ_ENA_SHIFT (0U) +#define PMU_DBG_PWR_CON_CPU0_DBG_PWRUP_REQ_ENA_MASK (0x1U << PMU_DBG_PWR_CON_CPU0_DBG_PWRUP_REQ_ENA_SHIFT) /* 0x00000001 */ +#define PMU_DBG_PWR_CON_CPU1_DBG_PWRUP_REQ_ENA_SHIFT (1U) +#define PMU_DBG_PWR_CON_CPU1_DBG_PWRUP_REQ_ENA_MASK (0x1U << PMU_DBG_PWR_CON_CPU1_DBG_PWRUP_REQ_ENA_SHIFT) /* 0x00000002 */ +#define PMU_DBG_PWR_CON_CPU2_DBG_PWRUP_REQ_ENA_SHIFT (2U) +#define PMU_DBG_PWR_CON_CPU2_DBG_PWRUP_REQ_ENA_MASK (0x1U << PMU_DBG_PWR_CON_CPU2_DBG_PWRUP_REQ_ENA_SHIFT) /* 0x00000004 */ +#define PMU_DBG_PWR_CON_CPU3_DBG_PWRUP_REQ_ENA_SHIFT (3U) +#define PMU_DBG_PWR_CON_CPU3_DBG_PWRUP_REQ_ENA_MASK (0x1U << PMU_DBG_PWR_CON_CPU3_DBG_PWRUP_REQ_ENA_SHIFT) /* 0x00000008 */ +#define PMU_DBG_PWR_CON_CLUSTER_DBG_PWRUP_REQ_ENA_SHIFT (4U) +#define PMU_DBG_PWR_CON_CLUSTER_DBG_PWRUP_REQ_ENA_MASK (0x1U << PMU_DBG_PWR_CON_CLUSTER_DBG_PWRUP_REQ_ENA_SHIFT) /* 0x00000010 */ +/****************************************SPINLOCK****************************************/ +/* STATUS_0 */ +#define SPINLOCK_STATUS_0_OFFSET (0x0U) +#define SPINLOCK_STATUS_0_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_0_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_0_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_1 */ +#define SPINLOCK_STATUS_1_OFFSET (0x4U) +#define SPINLOCK_STATUS_1_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_1_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_1_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_2 */ +#define SPINLOCK_STATUS_2_OFFSET (0x8U) +#define SPINLOCK_STATUS_2_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_2_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_2_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_3 */ +#define SPINLOCK_STATUS_3_OFFSET (0xCU) +#define SPINLOCK_STATUS_3_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_3_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_3_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_4 */ +#define SPINLOCK_STATUS_4_OFFSET (0x10U) +#define SPINLOCK_STATUS_4_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_4_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_4_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_5 */ +#define SPINLOCK_STATUS_5_OFFSET (0x14U) +#define SPINLOCK_STATUS_5_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_5_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_5_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_6 */ +#define SPINLOCK_STATUS_6_OFFSET (0x18U) +#define SPINLOCK_STATUS_6_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_6_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_6_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_7 */ +#define SPINLOCK_STATUS_7_OFFSET (0x1CU) +#define SPINLOCK_STATUS_7_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_7_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_7_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_8 */ +#define SPINLOCK_STATUS_8_OFFSET (0x20U) +#define SPINLOCK_STATUS_8_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_8_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_8_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_9 */ +#define SPINLOCK_STATUS_9_OFFSET (0x24U) +#define SPINLOCK_STATUS_9_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_9_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_9_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_10 */ +#define SPINLOCK_STATUS_10_OFFSET (0x28U) +#define SPINLOCK_STATUS_10_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_10_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_10_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_11 */ +#define SPINLOCK_STATUS_11_OFFSET (0x2CU) +#define SPINLOCK_STATUS_11_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_11_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_11_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_12 */ +#define SPINLOCK_STATUS_12_OFFSET (0x30U) +#define SPINLOCK_STATUS_12_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_12_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_12_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_13 */ +#define SPINLOCK_STATUS_13_OFFSET (0x34U) +#define SPINLOCK_STATUS_13_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_13_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_13_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_14 */ +#define SPINLOCK_STATUS_14_OFFSET (0x38U) +#define SPINLOCK_STATUS_14_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_14_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_14_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_15 */ +#define SPINLOCK_STATUS_15_OFFSET (0x3CU) +#define SPINLOCK_STATUS_15_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_15_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_15_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_16 */ +#define SPINLOCK_STATUS_16_OFFSET (0x40U) +#define SPINLOCK_STATUS_16_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_16_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_16_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_17 */ +#define SPINLOCK_STATUS_17_OFFSET (0x44U) +#define SPINLOCK_STATUS_17_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_17_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_17_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_18 */ +#define SPINLOCK_STATUS_18_OFFSET (0x48U) +#define SPINLOCK_STATUS_18_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_18_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_18_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_19 */ +#define SPINLOCK_STATUS_19_OFFSET (0x4CU) +#define SPINLOCK_STATUS_19_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_19_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_19_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_20 */ +#define SPINLOCK_STATUS_20_OFFSET (0x50U) +#define SPINLOCK_STATUS_20_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_20_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_20_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_21 */ +#define SPINLOCK_STATUS_21_OFFSET (0x54U) +#define SPINLOCK_STATUS_21_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_21_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_21_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_22 */ +#define SPINLOCK_STATUS_22_OFFSET (0x58U) +#define SPINLOCK_STATUS_22_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_22_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_22_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_23 */ +#define SPINLOCK_STATUS_23_OFFSET (0x5CU) +#define SPINLOCK_STATUS_23_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_23_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_23_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_24 */ +#define SPINLOCK_STATUS_24_OFFSET (0x60U) +#define SPINLOCK_STATUS_24_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_24_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_24_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_25 */ +#define SPINLOCK_STATUS_25_OFFSET (0x64U) +#define SPINLOCK_STATUS_25_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_25_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_25_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_26 */ +#define SPINLOCK_STATUS_26_OFFSET (0x68U) +#define SPINLOCK_STATUS_26_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_26_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_26_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_27 */ +#define SPINLOCK_STATUS_27_OFFSET (0x6CU) +#define SPINLOCK_STATUS_27_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_27_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_27_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_28 */ +#define SPINLOCK_STATUS_28_OFFSET (0x70U) +#define SPINLOCK_STATUS_28_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_28_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_28_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_29 */ +#define SPINLOCK_STATUS_29_OFFSET (0x74U) +#define SPINLOCK_STATUS_29_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_29_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_29_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_30 */ +#define SPINLOCK_STATUS_30_OFFSET (0x78U) +#define SPINLOCK_STATUS_30_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_30_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_30_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_31 */ +#define SPINLOCK_STATUS_31_OFFSET (0x7CU) +#define SPINLOCK_STATUS_31_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_31_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_31_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_32 */ +#define SPINLOCK_STATUS_32_OFFSET (0x80U) +#define SPINLOCK_STATUS_32_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_32_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_32_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_33 */ +#define SPINLOCK_STATUS_33_OFFSET (0x84U) +#define SPINLOCK_STATUS_33_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_33_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_33_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_34 */ +#define SPINLOCK_STATUS_34_OFFSET (0x88U) +#define SPINLOCK_STATUS_34_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_34_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_34_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_35 */ +#define SPINLOCK_STATUS_35_OFFSET (0x8CU) +#define SPINLOCK_STATUS_35_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_35_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_35_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_36 */ +#define SPINLOCK_STATUS_36_OFFSET (0x90U) +#define SPINLOCK_STATUS_36_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_36_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_36_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_37 */ +#define SPINLOCK_STATUS_37_OFFSET (0x94U) +#define SPINLOCK_STATUS_37_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_37_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_37_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_38 */ +#define SPINLOCK_STATUS_38_OFFSET (0x98U) +#define SPINLOCK_STATUS_38_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_38_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_38_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_39 */ +#define SPINLOCK_STATUS_39_OFFSET (0x9CU) +#define SPINLOCK_STATUS_39_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_39_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_39_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_40 */ +#define SPINLOCK_STATUS_40_OFFSET (0xA0U) +#define SPINLOCK_STATUS_40_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_40_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_40_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_41 */ +#define SPINLOCK_STATUS_41_OFFSET (0xA4U) +#define SPINLOCK_STATUS_41_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_41_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_41_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_42 */ +#define SPINLOCK_STATUS_42_OFFSET (0xA8U) +#define SPINLOCK_STATUS_42_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_42_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_42_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_43 */ +#define SPINLOCK_STATUS_43_OFFSET (0xACU) +#define SPINLOCK_STATUS_43_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_43_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_43_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_44 */ +#define SPINLOCK_STATUS_44_OFFSET (0xB0U) +#define SPINLOCK_STATUS_44_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_44_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_44_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_45 */ +#define SPINLOCK_STATUS_45_OFFSET (0xB4U) +#define SPINLOCK_STATUS_45_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_45_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_45_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_46 */ +#define SPINLOCK_STATUS_46_OFFSET (0xB8U) +#define SPINLOCK_STATUS_46_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_46_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_46_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_47 */ +#define SPINLOCK_STATUS_47_OFFSET (0xBCU) +#define SPINLOCK_STATUS_47_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_47_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_47_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_48 */ +#define SPINLOCK_STATUS_48_OFFSET (0xC0U) +#define SPINLOCK_STATUS_48_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_48_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_48_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_49 */ +#define SPINLOCK_STATUS_49_OFFSET (0xC4U) +#define SPINLOCK_STATUS_49_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_49_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_49_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_50 */ +#define SPINLOCK_STATUS_50_OFFSET (0xC8U) +#define SPINLOCK_STATUS_50_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_50_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_50_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_51 */ +#define SPINLOCK_STATUS_51_OFFSET (0xCCU) +#define SPINLOCK_STATUS_51_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_51_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_51_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_52 */ +#define SPINLOCK_STATUS_52_OFFSET (0xD0U) +#define SPINLOCK_STATUS_52_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_52_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_52_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_53 */ +#define SPINLOCK_STATUS_53_OFFSET (0xD4U) +#define SPINLOCK_STATUS_53_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_53_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_53_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_54 */ +#define SPINLOCK_STATUS_54_OFFSET (0xD8U) +#define SPINLOCK_STATUS_54_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_54_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_54_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_55 */ +#define SPINLOCK_STATUS_55_OFFSET (0xDCU) +#define SPINLOCK_STATUS_55_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_55_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_55_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_56 */ +#define SPINLOCK_STATUS_56_OFFSET (0xE0U) +#define SPINLOCK_STATUS_56_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_56_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_56_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_57 */ +#define SPINLOCK_STATUS_57_OFFSET (0xE4U) +#define SPINLOCK_STATUS_57_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_57_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_57_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_58 */ +#define SPINLOCK_STATUS_58_OFFSET (0xE8U) +#define SPINLOCK_STATUS_58_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_58_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_58_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_59 */ +#define SPINLOCK_STATUS_59_OFFSET (0xECU) +#define SPINLOCK_STATUS_59_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_59_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_59_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_60 */ +#define SPINLOCK_STATUS_60_OFFSET (0xF0U) +#define SPINLOCK_STATUS_60_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_60_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_60_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_61 */ +#define SPINLOCK_STATUS_61_OFFSET (0xF4U) +#define SPINLOCK_STATUS_61_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_61_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_61_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_62 */ +#define SPINLOCK_STATUS_62_OFFSET (0xF8U) +#define SPINLOCK_STATUS_62_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_62_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_62_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/* STATUS_63 */ +#define SPINLOCK_STATUS_63_OFFSET (0xFCU) +#define SPINLOCK_STATUS_63_SPINLOCK_STATUS_SHIFT (0U) +#define SPINLOCK_STATUS_63_SPINLOCK_STATUS_MASK (0xFU << SPINLOCK_STATUS_63_SPINLOCK_STATUS_SHIFT) /* 0x0000000F */ +/******************************************GMAC******************************************/ +/* MAC_CONFIGURATION */ +#define GMAC_MAC_CONFIGURATION_OFFSET (0x0U) +#define GMAC_MAC_CONFIGURATION_RE_SHIFT (0U) +#define GMAC_MAC_CONFIGURATION_RE_MASK (0x1U << GMAC_MAC_CONFIGURATION_RE_SHIFT) /* 0x00000001 */ +#define GMAC_MAC_CONFIGURATION_TE_SHIFT (1U) +#define GMAC_MAC_CONFIGURATION_TE_MASK (0x1U << GMAC_MAC_CONFIGURATION_TE_SHIFT) /* 0x00000002 */ +#define GMAC_MAC_CONFIGURATION_PRELEN_SHIFT (2U) +#define GMAC_MAC_CONFIGURATION_PRELEN_MASK (0x3U << GMAC_MAC_CONFIGURATION_PRELEN_SHIFT) /* 0x0000000C */ +#define GMAC_MAC_CONFIGURATION_DC_SHIFT (4U) +#define GMAC_MAC_CONFIGURATION_DC_MASK (0x1U << GMAC_MAC_CONFIGURATION_DC_SHIFT) /* 0x00000010 */ +#define GMAC_MAC_CONFIGURATION_BL_SHIFT (5U) +#define GMAC_MAC_CONFIGURATION_BL_MASK (0x3U << GMAC_MAC_CONFIGURATION_BL_SHIFT) /* 0x00000060 */ +#define GMAC_MAC_CONFIGURATION_DR_SHIFT (8U) +#define GMAC_MAC_CONFIGURATION_DR_MASK (0x1U << GMAC_MAC_CONFIGURATION_DR_SHIFT) /* 0x00000100 */ +#define GMAC_MAC_CONFIGURATION_DCRS_SHIFT (9U) +#define GMAC_MAC_CONFIGURATION_DCRS_MASK (0x1U << GMAC_MAC_CONFIGURATION_DCRS_SHIFT) /* 0x00000200 */ +#define GMAC_MAC_CONFIGURATION_DO_SHIFT (10U) +#define GMAC_MAC_CONFIGURATION_DO_MASK (0x1U << GMAC_MAC_CONFIGURATION_DO_SHIFT) /* 0x00000400 */ +#define GMAC_MAC_CONFIGURATION_ECRSFD_SHIFT (11U) +#define GMAC_MAC_CONFIGURATION_ECRSFD_MASK (0x1U << GMAC_MAC_CONFIGURATION_ECRSFD_SHIFT) /* 0x00000800 */ +#define GMAC_MAC_CONFIGURATION_LM_SHIFT (12U) +#define GMAC_MAC_CONFIGURATION_LM_MASK (0x1U << GMAC_MAC_CONFIGURATION_LM_SHIFT) /* 0x00001000 */ +#define GMAC_MAC_CONFIGURATION_DM_SHIFT (13U) +#define GMAC_MAC_CONFIGURATION_DM_MASK (0x1U << GMAC_MAC_CONFIGURATION_DM_SHIFT) /* 0x00002000 */ +#define GMAC_MAC_CONFIGURATION_FES_SHIFT (14U) +#define GMAC_MAC_CONFIGURATION_FES_MASK (0x1U << GMAC_MAC_CONFIGURATION_FES_SHIFT) /* 0x00004000 */ +#define GMAC_MAC_CONFIGURATION_PS_SHIFT (15U) +#define GMAC_MAC_CONFIGURATION_PS_MASK (0x1U << GMAC_MAC_CONFIGURATION_PS_SHIFT) /* 0x00008000 */ +#define GMAC_MAC_CONFIGURATION_JE_SHIFT (16U) +#define GMAC_MAC_CONFIGURATION_JE_MASK (0x1U << GMAC_MAC_CONFIGURATION_JE_SHIFT) /* 0x00010000 */ +#define GMAC_MAC_CONFIGURATION_JD_SHIFT (17U) +#define GMAC_MAC_CONFIGURATION_JD_MASK (0x1U << GMAC_MAC_CONFIGURATION_JD_SHIFT) /* 0x00020000 */ +#define GMAC_MAC_CONFIGURATION_BE_SHIFT (18U) +#define GMAC_MAC_CONFIGURATION_BE_MASK (0x1U << GMAC_MAC_CONFIGURATION_BE_SHIFT) /* 0x00040000 */ +#define GMAC_MAC_CONFIGURATION_WD_SHIFT (19U) +#define GMAC_MAC_CONFIGURATION_WD_MASK (0x1U << GMAC_MAC_CONFIGURATION_WD_SHIFT) /* 0x00080000 */ +#define GMAC_MAC_CONFIGURATION_ACS_SHIFT (20U) +#define GMAC_MAC_CONFIGURATION_ACS_MASK (0x1U << GMAC_MAC_CONFIGURATION_ACS_SHIFT) /* 0x00100000 */ +#define GMAC_MAC_CONFIGURATION_CST_SHIFT (21U) +#define GMAC_MAC_CONFIGURATION_CST_MASK (0x1U << GMAC_MAC_CONFIGURATION_CST_SHIFT) /* 0x00200000 */ +#define GMAC_MAC_CONFIGURATION_S2KP_SHIFT (22U) +#define GMAC_MAC_CONFIGURATION_S2KP_MASK (0x1U << GMAC_MAC_CONFIGURATION_S2KP_SHIFT) /* 0x00400000 */ +#define GMAC_MAC_CONFIGURATION_GPSLCE_SHIFT (23U) +#define GMAC_MAC_CONFIGURATION_GPSLCE_MASK (0x1U << GMAC_MAC_CONFIGURATION_GPSLCE_SHIFT) /* 0x00800000 */ +#define GMAC_MAC_CONFIGURATION_IPG_SHIFT (24U) +#define GMAC_MAC_CONFIGURATION_IPG_MASK (0x7U << GMAC_MAC_CONFIGURATION_IPG_SHIFT) /* 0x07000000 */ +#define GMAC_MAC_CONFIGURATION_IPC_SHIFT (27U) +#define GMAC_MAC_CONFIGURATION_IPC_MASK (0x1U << GMAC_MAC_CONFIGURATION_IPC_SHIFT) /* 0x08000000 */ +#define GMAC_MAC_CONFIGURATION_ARPEN_SHIFT (31U) +#define GMAC_MAC_CONFIGURATION_ARPEN_MASK (0x1U << GMAC_MAC_CONFIGURATION_ARPEN_SHIFT) /* 0x80000000 */ +/* MAC_EXT_CONFIGURATION */ +#define GMAC_MAC_EXT_CONFIGURATION_OFFSET (0x4U) +#define GMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT (0U) +#define GMAC_MAC_EXT_CONFIGURATION_GPSL_MASK (0x3FFFU << GMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT) /* 0x00003FFF */ +#define GMAC_MAC_EXT_CONFIGURATION_DCRCC_SHIFT (16U) +#define GMAC_MAC_EXT_CONFIGURATION_DCRCC_MASK (0x1U << GMAC_MAC_EXT_CONFIGURATION_DCRCC_SHIFT) /* 0x00010000 */ +#define GMAC_MAC_EXT_CONFIGURATION_SPEN_SHIFT (17U) +#define GMAC_MAC_EXT_CONFIGURATION_SPEN_MASK (0x1U << GMAC_MAC_EXT_CONFIGURATION_SPEN_SHIFT) /* 0x00020000 */ +#define GMAC_MAC_EXT_CONFIGURATION_USP_SHIFT (18U) +#define GMAC_MAC_EXT_CONFIGURATION_USP_MASK (0x1U << GMAC_MAC_EXT_CONFIGURATION_USP_SHIFT) /* 0x00040000 */ +#define GMAC_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT (24U) +#define GMAC_MAC_EXT_CONFIGURATION_EIPGEN_MASK (0x1U << GMAC_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT) /* 0x01000000 */ +#define GMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT (25U) +#define GMAC_MAC_EXT_CONFIGURATION_EIPG_MASK (0x1FU << GMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT) /* 0x3E000000 */ +/* MAC_PACKET_FILTER */ +#define GMAC_MAC_PACKET_FILTER_OFFSET (0x8U) +#define GMAC_MAC_PACKET_FILTER_PR_SHIFT (0U) +#define GMAC_MAC_PACKET_FILTER_PR_MASK (0x1U << GMAC_MAC_PACKET_FILTER_PR_SHIFT) /* 0x00000001 */ +#define GMAC_MAC_PACKET_FILTER_HUC_SHIFT (1U) +#define GMAC_MAC_PACKET_FILTER_HUC_MASK (0x1U << GMAC_MAC_PACKET_FILTER_HUC_SHIFT) /* 0x00000002 */ +#define GMAC_MAC_PACKET_FILTER_HMC_SHIFT (2U) +#define GMAC_MAC_PACKET_FILTER_HMC_MASK (0x1U << GMAC_MAC_PACKET_FILTER_HMC_SHIFT) /* 0x00000004 */ +#define GMAC_MAC_PACKET_FILTER_DAIF_SHIFT (3U) +#define GMAC_MAC_PACKET_FILTER_DAIF_MASK (0x1U << GMAC_MAC_PACKET_FILTER_DAIF_SHIFT) /* 0x00000008 */ +#define GMAC_MAC_PACKET_FILTER_PM_SHIFT (4U) +#define GMAC_MAC_PACKET_FILTER_PM_MASK (0x1U << GMAC_MAC_PACKET_FILTER_PM_SHIFT) /* 0x00000010 */ +#define GMAC_MAC_PACKET_FILTER_DBF_SHIFT (5U) +#define GMAC_MAC_PACKET_FILTER_DBF_MASK (0x1U << GMAC_MAC_PACKET_FILTER_DBF_SHIFT) /* 0x00000020 */ +#define GMAC_MAC_PACKET_FILTER_PCF_SHIFT (6U) +#define GMAC_MAC_PACKET_FILTER_PCF_MASK (0x3U << GMAC_MAC_PACKET_FILTER_PCF_SHIFT) /* 0x000000C0 */ +#define GMAC_MAC_PACKET_FILTER_HPF_SHIFT (10U) +#define GMAC_MAC_PACKET_FILTER_HPF_MASK (0x1U << GMAC_MAC_PACKET_FILTER_HPF_SHIFT) /* 0x00000400 */ +#define GMAC_MAC_PACKET_FILTER_VTFE_SHIFT (16U) +#define GMAC_MAC_PACKET_FILTER_VTFE_MASK (0x1U << GMAC_MAC_PACKET_FILTER_VTFE_SHIFT) /* 0x00010000 */ +/* MAC_WATCHDOG_TIMEOUT */ +#define GMAC_MAC_WATCHDOG_TIMEOUT_OFFSET (0xCU) +#define GMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT (0U) +#define GMAC_MAC_WATCHDOG_TIMEOUT_WTO_MASK (0xFU << GMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT) /* 0x0000000F */ +#define GMAC_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT (8U) +#define GMAC_MAC_WATCHDOG_TIMEOUT_PWE_MASK (0x1U << GMAC_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT) /* 0x00000100 */ +/* MAC_HASH_TABLE_REG0 */ +#define GMAC_MAC_HASH_TABLE_REG0_OFFSET (0x10U) +#define GMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT (0U) +#define GMAC_MAC_HASH_TABLE_REG0_HT31T0_MASK (0xFFFFFFFFU << GMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT) /* 0xFFFFFFFF */ +/* MAC_HASH_TABLE_REG1 */ +#define GMAC_MAC_HASH_TABLE_REG1_OFFSET (0x14U) +#define GMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT (0U) +#define GMAC_MAC_HASH_TABLE_REG1_HT63T32_MASK (0xFFFFFFFFU << GMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT) /* 0xFFFFFFFF */ +/* MAC_VLAN_TAG */ +#define GMAC_MAC_VLAN_TAG_OFFSET (0x50U) +#define GMAC_MAC_VLAN_TAG_VL_SHIFT (0U) +#define GMAC_MAC_VLAN_TAG_VL_MASK (0xFFFFU << GMAC_MAC_VLAN_TAG_VL_SHIFT) /* 0x0000FFFF */ +#define GMAC_MAC_VLAN_TAG_ETV_SHIFT (16U) +#define GMAC_MAC_VLAN_TAG_ETV_MASK (0x1U << GMAC_MAC_VLAN_TAG_ETV_SHIFT) /* 0x00010000 */ +#define GMAC_MAC_VLAN_TAG_VTIM_SHIFT (17U) +#define GMAC_MAC_VLAN_TAG_VTIM_MASK (0x1U << GMAC_MAC_VLAN_TAG_VTIM_SHIFT) /* 0x00020000 */ +#define GMAC_MAC_VLAN_TAG_ESVL_SHIFT (18U) +#define GMAC_MAC_VLAN_TAG_ESVL_MASK (0x1U << GMAC_MAC_VLAN_TAG_ESVL_SHIFT) /* 0x00040000 */ +#define GMAC_MAC_VLAN_TAG_ERSVLM_SHIFT (19U) +#define GMAC_MAC_VLAN_TAG_ERSVLM_MASK (0x1U << GMAC_MAC_VLAN_TAG_ERSVLM_SHIFT) /* 0x00080000 */ +#define GMAC_MAC_VLAN_TAG_DOVLTC_SHIFT (20U) +#define GMAC_MAC_VLAN_TAG_DOVLTC_MASK (0x1U << GMAC_MAC_VLAN_TAG_DOVLTC_SHIFT) /* 0x00100000 */ +#define GMAC_MAC_VLAN_TAG_EVLS_SHIFT (21U) +#define GMAC_MAC_VLAN_TAG_EVLS_MASK (0x3U << GMAC_MAC_VLAN_TAG_EVLS_SHIFT) /* 0x00600000 */ +#define GMAC_MAC_VLAN_TAG_EVLRXS_SHIFT (24U) +#define GMAC_MAC_VLAN_TAG_EVLRXS_MASK (0x1U << GMAC_MAC_VLAN_TAG_EVLRXS_SHIFT) /* 0x01000000 */ +/* MAC_Q0_TX_FLOW_CTRL */ +#define GMAC_MAC_Q0_TX_FLOW_CTRL_OFFSET (0x70U) +#define GMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_SHIFT (0U) +#define GMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_MASK (0x1U << GMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_SHIFT) /* 0x00000001 */ +#define GMAC_MAC_Q0_TX_FLOW_CTRL_TFE_SHIFT (1U) +#define GMAC_MAC_Q0_TX_FLOW_CTRL_TFE_MASK (0x1U << GMAC_MAC_Q0_TX_FLOW_CTRL_TFE_SHIFT) /* 0x00000002 */ +#define GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT (4U) +#define GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_MASK (0x7U << GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT) /* 0x00000070 */ +#define GMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_SHIFT (7U) +#define GMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_MASK (0x1U << GMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_SHIFT) /* 0x00000080 */ +#define GMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT (16U) +#define GMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK (0xFFFFU << GMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT) /* 0xFFFF0000 */ +/* MAC_RX_FLOW_CTRL */ +#define GMAC_MAC_RX_FLOW_CTRL_OFFSET (0x90U) +#define GMAC_MAC_RX_FLOW_CTRL_RFE_SHIFT (0U) +#define GMAC_MAC_RX_FLOW_CTRL_RFE_MASK (0x1U << GMAC_MAC_RX_FLOW_CTRL_RFE_SHIFT) /* 0x00000001 */ +#define GMAC_MAC_RX_FLOW_CTRL_UP_SHIFT (1U) +#define GMAC_MAC_RX_FLOW_CTRL_UP_MASK (0x1U << GMAC_MAC_RX_FLOW_CTRL_UP_SHIFT) /* 0x00000002 */ +/* MAC_INTERRUPT_STATUS */ +#define GMAC_MAC_INTERRUPT_STATUS_OFFSET (0xB0U) +#define GMAC_MAC_INTERRUPT_STATUS (0x0U) +#define GMAC_MAC_INTERRUPT_STATUS_RGSMIIIS_SHIFT (0U) +#define GMAC_MAC_INTERRUPT_STATUS_RGSMIIIS_MASK (0x1U << GMAC_MAC_INTERRUPT_STATUS_RGSMIIIS_SHIFT) /* 0x00000001 */ +#define GMAC_MAC_INTERRUPT_STATUS_PHYIS_SHIFT (3U) +#define GMAC_MAC_INTERRUPT_STATUS_PHYIS_MASK (0x1U << GMAC_MAC_INTERRUPT_STATUS_PHYIS_SHIFT) /* 0x00000008 */ +#define GMAC_MAC_INTERRUPT_STATUS_PMTIS_SHIFT (4U) +#define GMAC_MAC_INTERRUPT_STATUS_PMTIS_MASK (0x1U << GMAC_MAC_INTERRUPT_STATUS_PMTIS_SHIFT) /* 0x00000010 */ +#define GMAC_MAC_INTERRUPT_STATUS_LPIIS_SHIFT (5U) +#define GMAC_MAC_INTERRUPT_STATUS_LPIIS_MASK (0x1U << GMAC_MAC_INTERRUPT_STATUS_LPIIS_SHIFT) /* 0x00000020 */ +#define GMAC_MAC_INTERRUPT_STATUS_MMCIS_SHIFT (8U) +#define GMAC_MAC_INTERRUPT_STATUS_MMCIS_MASK (0x1U << GMAC_MAC_INTERRUPT_STATUS_MMCIS_SHIFT) /* 0x00000100 */ +#define GMAC_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT (9U) +#define GMAC_MAC_INTERRUPT_STATUS_MMCRXIS_MASK (0x1U << GMAC_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT) /* 0x00000200 */ +#define GMAC_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT (10U) +#define GMAC_MAC_INTERRUPT_STATUS_MMCTXIS_MASK (0x1U << GMAC_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT) /* 0x00000400 */ +#define GMAC_MAC_INTERRUPT_STATUS_MMCRXIPIS_SHIFT (11U) +#define GMAC_MAC_INTERRUPT_STATUS_MMCRXIPIS_MASK (0x1U << GMAC_MAC_INTERRUPT_STATUS_MMCRXIPIS_SHIFT) /* 0x00000800 */ +#define GMAC_MAC_INTERRUPT_STATUS_TSIS_SHIFT (12U) +#define GMAC_MAC_INTERRUPT_STATUS_TSIS_MASK (0x1U << GMAC_MAC_INTERRUPT_STATUS_TSIS_SHIFT) /* 0x00001000 */ +#define GMAC_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT (13U) +#define GMAC_MAC_INTERRUPT_STATUS_TXSTSIS_MASK (0x1U << GMAC_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT) /* 0x00002000 */ +#define GMAC_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT (14U) +#define GMAC_MAC_INTERRUPT_STATUS_RXSTSIS_MASK (0x1U << GMAC_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT) /* 0x00004000 */ +#define GMAC_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT (18U) +#define GMAC_MAC_INTERRUPT_STATUS_MDIOIS_MASK (0x1U << GMAC_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT) /* 0x00040000 */ +/* MAC_INTERRUPT_ENABLE */ +#define GMAC_MAC_INTERRUPT_ENABLE_OFFSET (0xB4U) +#define GMAC_MAC_INTERRUPT_ENABLE_RGSMIIIE_SHIFT (0U) +#define GMAC_MAC_INTERRUPT_ENABLE_RGSMIIIE_MASK (0x1U << GMAC_MAC_INTERRUPT_ENABLE_RGSMIIIE_SHIFT) /* 0x00000001 */ +#define GMAC_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT (3U) +#define GMAC_MAC_INTERRUPT_ENABLE_PHYIE_MASK (0x1U << GMAC_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT) /* 0x00000008 */ +#define GMAC_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT (4U) +#define GMAC_MAC_INTERRUPT_ENABLE_PMTIE_MASK (0x1U << GMAC_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT) /* 0x00000010 */ +#define GMAC_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT (5U) +#define GMAC_MAC_INTERRUPT_ENABLE_LPIIE_MASK (0x1U << GMAC_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT) /* 0x00000020 */ +#define GMAC_MAC_INTERRUPT_ENABLE_TSIE_SHIFT (12U) +#define GMAC_MAC_INTERRUPT_ENABLE_TSIE_MASK (0x1U << GMAC_MAC_INTERRUPT_ENABLE_TSIE_SHIFT) /* 0x00001000 */ +#define GMAC_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT (13U) +#define GMAC_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK (0x1U << GMAC_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT) /* 0x00002000 */ +#define GMAC_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT (14U) +#define GMAC_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK (0x1U << GMAC_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT) /* 0x00004000 */ +#define GMAC_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT (18U) +#define GMAC_MAC_INTERRUPT_ENABLE_MDIOIE_MASK (0x1U << GMAC_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT) /* 0x00040000 */ +/* MAC_RX_TX_STATUS */ +#define GMAC_MAC_RX_TX_STATUS_OFFSET (0xB8U) +#define GMAC_MAC_RX_TX_STATUS (0x0U) +#define GMAC_MAC_RX_TX_STATUS_TJT_SHIFT (0U) +#define GMAC_MAC_RX_TX_STATUS_TJT_MASK (0x1U << GMAC_MAC_RX_TX_STATUS_TJT_SHIFT) /* 0x00000001 */ +#define GMAC_MAC_RX_TX_STATUS_NCARR_SHIFT (1U) +#define GMAC_MAC_RX_TX_STATUS_NCARR_MASK (0x1U << GMAC_MAC_RX_TX_STATUS_NCARR_SHIFT) /* 0x00000002 */ +#define GMAC_MAC_RX_TX_STATUS_LCARR_SHIFT (2U) +#define GMAC_MAC_RX_TX_STATUS_LCARR_MASK (0x1U << GMAC_MAC_RX_TX_STATUS_LCARR_SHIFT) /* 0x00000004 */ +#define GMAC_MAC_RX_TX_STATUS_EXDEF_SHIFT (3U) +#define GMAC_MAC_RX_TX_STATUS_EXDEF_MASK (0x1U << GMAC_MAC_RX_TX_STATUS_EXDEF_SHIFT) /* 0x00000008 */ +#define GMAC_MAC_RX_TX_STATUS_LCOL_SHIFT (4U) +#define GMAC_MAC_RX_TX_STATUS_LCOL_MASK (0x1U << GMAC_MAC_RX_TX_STATUS_LCOL_SHIFT) /* 0x00000010 */ +#define GMAC_MAC_RX_TX_STATUS_EXCOL_SHIFT (5U) +#define GMAC_MAC_RX_TX_STATUS_EXCOL_MASK (0x1U << GMAC_MAC_RX_TX_STATUS_EXCOL_SHIFT) /* 0x00000020 */ +#define GMAC_MAC_RX_TX_STATUS_RWT_SHIFT (8U) +#define GMAC_MAC_RX_TX_STATUS_RWT_MASK (0x1U << GMAC_MAC_RX_TX_STATUS_RWT_SHIFT) /* 0x00000100 */ +/* MAC_PMT_CONTROL_STATUS */ +#define GMAC_MAC_PMT_CONTROL_STATUS_OFFSET (0xC0U) +#define GMAC_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT (0U) +#define GMAC_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK (0x1U << GMAC_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT) /* 0x00000001 */ +#define GMAC_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT (1U) +#define GMAC_MAC_PMT_CONTROL_STATUS_MGKPKTEN_MASK (0x1U << GMAC_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT) /* 0x00000002 */ +#define GMAC_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT (2U) +#define GMAC_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MASK (0x1U << GMAC_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT) /* 0x00000004 */ +#define GMAC_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT (5U) +#define GMAC_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MASK (0x1U << GMAC_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT) /* 0x00000020 */ +#define GMAC_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT (6U) +#define GMAC_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MASK (0x1U << GMAC_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT) /* 0x00000040 */ +#define GMAC_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT (9U) +#define GMAC_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MASK (0x1U << GMAC_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT) /* 0x00000200 */ +#define GMAC_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT (10U) +#define GMAC_MAC_PMT_CONTROL_STATUS_RWKPFE_MASK (0x1U << GMAC_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT) /* 0x00000400 */ +#define GMAC_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT (24U) +#define GMAC_MAC_PMT_CONTROL_STATUS_RWKPTR_MASK (0x1FU << GMAC_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT) /* 0x1F000000 */ +#define GMAC_MAC_PMT_CONTROL_STATUS_RWKFILTRST_SHIFT (31U) +#define GMAC_MAC_PMT_CONTROL_STATUS_RWKFILTRST_MASK (0x1U << GMAC_MAC_PMT_CONTROL_STATUS_RWKFILTRST_SHIFT) /* 0x80000000 */ +/* RWK_FILTER0_BYTE_MASK */ +#define GMAC_RWK_FILTER0_BYTE_MASK_OFFSET (0xC4U) +#define GMAC_RWK_FILTER0_BYTE_MASK_FILTER0_BYTE_MASK_SHIFT (0U) +#define GMAC_RWK_FILTER0_BYTE_MASK_FILTER0_BYTE_MASK_MASK (0xFFFFFFFFU << GMAC_RWK_FILTER0_BYTE_MASK_FILTER0_BYTE_MASK_SHIFT) /* 0xFFFFFFFF */ +/* RWK_FILTER1_BYTE_MASK */ +#define GMAC_RWK_FILTER1_BYTE_MASK_OFFSET (0xC8U) +#define GMAC_RWK_FILTER1_BYTE_MASK_FILTER1_BYTE_MASK_SHIFT (0U) +#define GMAC_RWK_FILTER1_BYTE_MASK_FILTER1_BYTE_MASK_MASK (0xFFFFFFFFU << GMAC_RWK_FILTER1_BYTE_MASK_FILTER1_BYTE_MASK_SHIFT) /* 0xFFFFFFFF */ +/* RWK_FILTER2_BYTE_MASK */ +#define GMAC_RWK_FILTER2_BYTE_MASK_OFFSET (0xCCU) +#define GMAC_RWK_FILTER2_BYTE_MASK_FILTER2_BYTE_MASK_SHIFT (0U) +#define GMAC_RWK_FILTER2_BYTE_MASK_FILTER2_BYTE_MASK_MASK (0xFFFFFFFFU << GMAC_RWK_FILTER2_BYTE_MASK_FILTER2_BYTE_MASK_SHIFT) /* 0xFFFFFFFF */ +/* RWK_FILTER3_BYTE_MASK */ +#define GMAC_RWK_FILTER3_BYTE_MASK_OFFSET (0xCCU) +#define GMAC_RWK_FILTER3_BYTE_MASK_FILTER3_BYTE_MASK_SHIFT (0U) +#define GMAC_RWK_FILTER3_BYTE_MASK_FILTER3_BYTE_MASK_MASK (0xFFFFFFFFU << GMAC_RWK_FILTER3_BYTE_MASK_FILTER3_BYTE_MASK_SHIFT) /* 0xFFFFFFFF */ +/* RWK_FILTER01_CRC */ +#define GMAC_RWK_FILTER01_CRC_OFFSET (0xD0U) +#define GMAC_RWK_FILTER01_CRC_FILTER0_CRC_SHIFT (0U) +#define GMAC_RWK_FILTER01_CRC_FILTER0_CRC_MASK (0xFFFFU << GMAC_RWK_FILTER01_CRC_FILTER0_CRC_SHIFT) /* 0x0000FFFF */ +#define GMAC_RWK_FILTER01_CRC_FILTER1_CRC_SHIFT (16U) +#define GMAC_RWK_FILTER01_CRC_FILTER1_CRC_MASK (0xFFFFU << GMAC_RWK_FILTER01_CRC_FILTER1_CRC_SHIFT) /* 0xFFFF0000 */ +/* RWK_FILTER23_CRC */ +#define GMAC_RWK_FILTER23_CRC_OFFSET (0xD4U) +#define GMAC_RWK_FILTER23_CRC_FILTER2_CRC_SHIFT (0U) +#define GMAC_RWK_FILTER23_CRC_FILTER2_CRC_MASK (0xFFFFU << GMAC_RWK_FILTER23_CRC_FILTER2_CRC_SHIFT) /* 0x0000FFFF */ +#define GMAC_RWK_FILTER23_CRC_FILTER3_CRC_SHIFT (16U) +#define GMAC_RWK_FILTER23_CRC_FILTER3_CRC_MASK (0xFFFFU << GMAC_RWK_FILTER23_CRC_FILTER3_CRC_SHIFT) /* 0xFFFF0000 */ +/* RWK_FILTER_OFFSET */ +#define GMAC_RWK_FILTER_OFFSET_OFFSET (0xD8U) +#define GMAC_RWK_FILTER_OFFSET_FILTER0_OFFSET_SHIFT (0U) +#define GMAC_RWK_FILTER_OFFSET_FILTER0_OFFSET_MASK (0xFFU << GMAC_RWK_FILTER_OFFSET_FILTER0_OFFSET_SHIFT) /* 0x000000FF */ +#define GMAC_RWK_FILTER_OFFSET_FILTER1_OFFSET_SHIFT (8U) +#define GMAC_RWK_FILTER_OFFSET_FILTER1_OFFSET_MASK (0xFFU << GMAC_RWK_FILTER_OFFSET_FILTER1_OFFSET_SHIFT) /* 0x0000FF00 */ +#define GMAC_RWK_FILTER_OFFSET_FILTER2_OFFSET_SHIFT (16U) +#define GMAC_RWK_FILTER_OFFSET_FILTER2_OFFSET_MASK (0xFFU << GMAC_RWK_FILTER_OFFSET_FILTER2_OFFSET_SHIFT) /* 0x00FF0000 */ +#define GMAC_RWK_FILTER_OFFSET_FILTER3_OFFSET_SHIFT (24U) +#define GMAC_RWK_FILTER_OFFSET_FILTER3_OFFSET_MASK (0xFFU << GMAC_RWK_FILTER_OFFSET_FILTER3_OFFSET_SHIFT) /* 0xFF000000 */ +/* RWK_FILTER_COMMAND */ +#define GMAC_RWK_FILTER_COMMAND_OFFSET (0xDCU) +#define GMAC_RWK_FILTER_COMMAND_FILTER0_COMMAND_SHIFT (0U) +#define GMAC_RWK_FILTER_COMMAND_FILTER0_COMMAND_MASK (0xFU << GMAC_RWK_FILTER_COMMAND_FILTER0_COMMAND_SHIFT) /* 0x0000000F */ +#define GMAC_RWK_FILTER_COMMAND_FILTER1_COMMAND_SHIFT (8U) +#define GMAC_RWK_FILTER_COMMAND_FILTER1_COMMAND_MASK (0xFU << GMAC_RWK_FILTER_COMMAND_FILTER1_COMMAND_SHIFT) /* 0x00000F00 */ +#define GMAC_RWK_FILTER_COMMAND_FILTER2_COMMAND_SHIFT (16U) +#define GMAC_RWK_FILTER_COMMAND_FILTER2_COMMAND_MASK (0xFU << GMAC_RWK_FILTER_COMMAND_FILTER2_COMMAND_SHIFT) /* 0x000F0000 */ +#define GMAC_RWK_FILTER_COMMAND_FILTER3_COMMAND_SHIFT (24U) +#define GMAC_RWK_FILTER_COMMAND_FILTER3_COMMAND_MASK (0xFU << GMAC_RWK_FILTER_COMMAND_FILTER3_COMMAND_SHIFT) /* 0x0F000000 */ +/* MAC_LPI_CONTROL_STATUS */ +#define GMAC_MAC_LPI_CONTROL_STATUS_OFFSET (0xD0U) +#define GMAC_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT (0U) +#define GMAC_MAC_LPI_CONTROL_STATUS_TLPIEN_MASK (0x1U << GMAC_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT) /* 0x00000001 */ +#define GMAC_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT (1U) +#define GMAC_MAC_LPI_CONTROL_STATUS_TLPIEX_MASK (0x1U << GMAC_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT) /* 0x00000002 */ +#define GMAC_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT (2U) +#define GMAC_MAC_LPI_CONTROL_STATUS_RLPIEN_MASK (0x1U << GMAC_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT) /* 0x00000004 */ +#define GMAC_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT (3U) +#define GMAC_MAC_LPI_CONTROL_STATUS_RLPIEX_MASK (0x1U << GMAC_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT) /* 0x00000008 */ +#define GMAC_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT (8U) +#define GMAC_MAC_LPI_CONTROL_STATUS_TLPIST_MASK (0x1U << GMAC_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT) /* 0x00000100 */ +#define GMAC_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT (9U) +#define GMAC_MAC_LPI_CONTROL_STATUS_RLPIST_MASK (0x1U << GMAC_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT) /* 0x00000200 */ +#define GMAC_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT (16U) +#define GMAC_MAC_LPI_CONTROL_STATUS_LPIEN_MASK (0x1U << GMAC_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT) /* 0x00010000 */ +#define GMAC_MAC_LPI_CONTROL_STATUS_PLS_SHIFT (17U) +#define GMAC_MAC_LPI_CONTROL_STATUS_PLS_MASK (0x1U << GMAC_MAC_LPI_CONTROL_STATUS_PLS_SHIFT) /* 0x00020000 */ +#define GMAC_MAC_LPI_CONTROL_STATUS_PLSEN_SHIFT (18U) +#define GMAC_MAC_LPI_CONTROL_STATUS_PLSEN_MASK (0x1U << GMAC_MAC_LPI_CONTROL_STATUS_PLSEN_SHIFT) /* 0x00040000 */ +#define GMAC_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT (19U) +#define GMAC_MAC_LPI_CONTROL_STATUS_LPITXA_MASK (0x1U << GMAC_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT) /* 0x00080000 */ +#define GMAC_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT (20U) +#define GMAC_MAC_LPI_CONTROL_STATUS_LPIATE_MASK (0x1U << GMAC_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT) /* 0x00100000 */ +#define GMAC_MAC_LPI_CONTROL_STATUS_LPITCSE_SHIFT (21U) +#define GMAC_MAC_LPI_CONTROL_STATUS_LPITCSE_MASK (0x1U << GMAC_MAC_LPI_CONTROL_STATUS_LPITCSE_SHIFT) /* 0x00200000 */ +/* MAC_LPI_TIMERS_CONTROL */ +#define GMAC_MAC_LPI_TIMERS_CONTROL_OFFSET (0xD4U) +#define GMAC_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT (0U) +#define GMAC_MAC_LPI_TIMERS_CONTROL_TWT_MASK (0xFFFFU << GMAC_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT) /* 0x0000FFFF */ +#define GMAC_MAC_LPI_TIMERS_CONTROL_LST_SHIFT (16U) +#define GMAC_MAC_LPI_TIMERS_CONTROL_LST_MASK (0x3FFU << GMAC_MAC_LPI_TIMERS_CONTROL_LST_SHIFT) /* 0x03FF0000 */ +/* MAC_LPI_ENTRY_TIMER */ +#define GMAC_MAC_LPI_ENTRY_TIMER_OFFSET (0xD8U) +#define GMAC_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT (3U) +#define GMAC_MAC_LPI_ENTRY_TIMER_LPIET_MASK (0x1FFFFU << GMAC_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT) /* 0x000FFFF8 */ +/* MAC_1US_TIC_COUNTER */ +#define GMAC_MAC_1US_TIC_COUNTER_OFFSET (0xDCU) +#define GMAC_MAC_1US_TIC_COUNTER_TIC_1US_CNTR_SHIFT (0U) +#define GMAC_MAC_1US_TIC_COUNTER_TIC_1US_CNTR_MASK (0xFFFU << GMAC_MAC_1US_TIC_COUNTER_TIC_1US_CNTR_SHIFT) /* 0x00000FFF */ +/* MAC_PHYIF_CONTROL_STATUS */ +#define GMAC_MAC_PHYIF_CONTROL_STATUS_OFFSET (0xF8U) +#define GMAC_MAC_PHYIF_CONTROL_STATUS_TC_SHIFT (0U) +#define GMAC_MAC_PHYIF_CONTROL_STATUS_TC_MASK (0x1U << GMAC_MAC_PHYIF_CONTROL_STATUS_TC_SHIFT) /* 0x00000001 */ +#define GMAC_MAC_PHYIF_CONTROL_STATUS_LUD_SHIFT (1U) +#define GMAC_MAC_PHYIF_CONTROL_STATUS_LUD_MASK (0x1U << GMAC_MAC_PHYIF_CONTROL_STATUS_LUD_SHIFT) /* 0x00000002 */ +#define GMAC_MAC_PHYIF_CONTROL_STATUS_LNKMOD_SHIFT (16U) +#define GMAC_MAC_PHYIF_CONTROL_STATUS_LNKMOD_MASK (0x1U << GMAC_MAC_PHYIF_CONTROL_STATUS_LNKMOD_SHIFT) /* 0x00010000 */ +#define GMAC_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT (17U) +#define GMAC_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_MASK (0x3U << GMAC_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT) /* 0x00060000 */ +#define GMAC_MAC_PHYIF_CONTROL_STATUS_LNKSTS_SHIFT (19U) +#define GMAC_MAC_PHYIF_CONTROL_STATUS_LNKSTS_MASK (0x1U << GMAC_MAC_PHYIF_CONTROL_STATUS_LNKSTS_SHIFT) /* 0x00080000 */ +/* MAC_VERSION */ +#define GMAC_MAC_VERSION_OFFSET (0x110U) +#define GMAC_MAC_VERSION_SNPSVER_SHIFT (0U) +#define GMAC_MAC_VERSION_SNPSVER_MASK (0xFFU << GMAC_MAC_VERSION_SNPSVER_SHIFT) /* 0x000000FF */ +#define GMAC_MAC_VERSION_USERVER_SHIFT (8U) +#define GMAC_MAC_VERSION_USERVER_MASK (0xFFU << GMAC_MAC_VERSION_USERVER_SHIFT) /* 0x0000FF00 */ +/* MAC_DEBUG */ +#define GMAC_MAC_DEBUG_OFFSET (0x114U) +#define GMAC_MAC_DEBUG (0x0U) +#define GMAC_MAC_DEBUG_RPESTS_SHIFT (0U) +#define GMAC_MAC_DEBUG_RPESTS_MASK (0x1U << GMAC_MAC_DEBUG_RPESTS_SHIFT) /* 0x00000001 */ +#define GMAC_MAC_DEBUG_RFCFCSTS_SHIFT (1U) +#define GMAC_MAC_DEBUG_RFCFCSTS_MASK (0x3U << GMAC_MAC_DEBUG_RFCFCSTS_SHIFT) /* 0x00000006 */ +#define GMAC_MAC_DEBUG_TPESTS_SHIFT (16U) +#define GMAC_MAC_DEBUG_TPESTS_MASK (0x1U << GMAC_MAC_DEBUG_TPESTS_SHIFT) /* 0x00010000 */ +#define GMAC_MAC_DEBUG_TFCSTS_SHIFT (17U) +#define GMAC_MAC_DEBUG_TFCSTS_MASK (0x3U << GMAC_MAC_DEBUG_TFCSTS_SHIFT) /* 0x00060000 */ +/* MAC_HW_FEATURE0 */ +#define GMAC_MAC_HW_FEATURE0_OFFSET (0x11CU) +#define GMAC_MAC_HW_FEATURE0 (0x160171E3U) +#define GMAC_MAC_HW_FEATURE0_MIISEL_SHIFT (0U) +#define GMAC_MAC_HW_FEATURE0_MIISEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_MIISEL_SHIFT) /* 0x00000001 */ +#define GMAC_MAC_HW_FEATURE0_GMIISEL_SHIFT (1U) +#define GMAC_MAC_HW_FEATURE0_GMIISEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_GMIISEL_SHIFT) /* 0x00000002 */ +#define GMAC_MAC_HW_FEATURE0_HDSEL_SHIFT (2U) +#define GMAC_MAC_HW_FEATURE0_HDSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_HDSEL_SHIFT) /* 0x00000004 */ +#define GMAC_MAC_HW_FEATURE0_PCSSEL_SHIFT (3U) +#define GMAC_MAC_HW_FEATURE0_PCSSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_PCSSEL_SHIFT) /* 0x00000008 */ +#define GMAC_MAC_HW_FEATURE0_VLHASH_SHIFT (4U) +#define GMAC_MAC_HW_FEATURE0_VLHASH_MASK (0x1U << GMAC_MAC_HW_FEATURE0_VLHASH_SHIFT) /* 0x00000010 */ +#define GMAC_MAC_HW_FEATURE0_SMASEL_SHIFT (5U) +#define GMAC_MAC_HW_FEATURE0_SMASEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_SMASEL_SHIFT) /* 0x00000020 */ +#define GMAC_MAC_HW_FEATURE0_RWKSEL_SHIFT (6U) +#define GMAC_MAC_HW_FEATURE0_RWKSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_RWKSEL_SHIFT) /* 0x00000040 */ +#define GMAC_MAC_HW_FEATURE0_MGKSEL_SHIFT (7U) +#define GMAC_MAC_HW_FEATURE0_MGKSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_MGKSEL_SHIFT) /* 0x00000080 */ +#define GMAC_MAC_HW_FEATURE0_MMCSEL_SHIFT (8U) +#define GMAC_MAC_HW_FEATURE0_MMCSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_MMCSEL_SHIFT) /* 0x00000100 */ +#define GMAC_MAC_HW_FEATURE0_ARPOFFSEL_SHIFT (9U) +#define GMAC_MAC_HW_FEATURE0_ARPOFFSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_ARPOFFSEL_SHIFT) /* 0x00000200 */ +#define GMAC_MAC_HW_FEATURE0_TSSEL_SHIFT (12U) +#define GMAC_MAC_HW_FEATURE0_TSSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_TSSEL_SHIFT) /* 0x00001000 */ +#define GMAC_MAC_HW_FEATURE0_EEESEL_SHIFT (13U) +#define GMAC_MAC_HW_FEATURE0_EEESEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_EEESEL_SHIFT) /* 0x00002000 */ +#define GMAC_MAC_HW_FEATURE0_TXCOESEL_SHIFT (14U) +#define GMAC_MAC_HW_FEATURE0_TXCOESEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_TXCOESEL_SHIFT) /* 0x00004000 */ +#define GMAC_MAC_HW_FEATURE0_RXCOESEL_SHIFT (16U) +#define GMAC_MAC_HW_FEATURE0_RXCOESEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_RXCOESEL_SHIFT) /* 0x00010000 */ +#define GMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT (18U) +#define GMAC_MAC_HW_FEATURE0_ADDMACADRSEL_MASK (0x1FU << GMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT) /* 0x007C0000 */ +#define GMAC_MAC_HW_FEATURE0_MACADR32SEL_SHIFT (23U) +#define GMAC_MAC_HW_FEATURE0_MACADR32SEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_MACADR32SEL_SHIFT) /* 0x00800000 */ +#define GMAC_MAC_HW_FEATURE0_MACADR64SEL_SHIFT (24U) +#define GMAC_MAC_HW_FEATURE0_MACADR64SEL_MASK (0x1U << GMAC_MAC_HW_FEATURE0_MACADR64SEL_SHIFT) /* 0x01000000 */ +#define GMAC_MAC_HW_FEATURE0_TSSTSSEL_SHIFT (25U) +#define GMAC_MAC_HW_FEATURE0_TSSTSSEL_MASK (0x3U << GMAC_MAC_HW_FEATURE0_TSSTSSEL_SHIFT) /* 0x06000000 */ +#define GMAC_MAC_HW_FEATURE0_SAVLANINS_SHIFT (27U) +#define GMAC_MAC_HW_FEATURE0_SAVLANINS_MASK (0x1U << GMAC_MAC_HW_FEATURE0_SAVLANINS_SHIFT) /* 0x08000000 */ +#define GMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT (28U) +#define GMAC_MAC_HW_FEATURE0_ACTPHYSEL_MASK (0xFU << GMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT) /* 0xF0000000 */ +/* MAC_HW_FEATURE1 */ +#define GMAC_MAC_HW_FEATURE1_OFFSET (0x120U) +#define GMAC_MAC_HW_FEATURE1 (0x10C01C8U) +#define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT (0U) +#define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK (0x1FU << GMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) /* 0x0000001F */ +#define GMAC_MAC_HW_FEATURE1_SPRAM_SHIFT (5U) +#define GMAC_MAC_HW_FEATURE1_SPRAM_MASK (0x1U << GMAC_MAC_HW_FEATURE1_SPRAM_SHIFT) /* 0x00000020 */ +#define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT (6U) +#define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK (0x1FU << GMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) /* 0x000007C0 */ +#define GMAC_MAC_HW_FEATURE1_OSTEN_SHIFT (11U) +#define GMAC_MAC_HW_FEATURE1_OSTEN_MASK (0x1U << GMAC_MAC_HW_FEATURE1_OSTEN_SHIFT) /* 0x00000800 */ +#define GMAC_MAC_HW_FEATURE1_PTOEN_SHIFT (12U) +#define GMAC_MAC_HW_FEATURE1_PTOEN_MASK (0x1U << GMAC_MAC_HW_FEATURE1_PTOEN_SHIFT) /* 0x00001000 */ +#define GMAC_MAC_HW_FEATURE1_ADVTHWORD_SHIFT (13U) +#define GMAC_MAC_HW_FEATURE1_ADVTHWORD_MASK (0x1U << GMAC_MAC_HW_FEATURE1_ADVTHWORD_SHIFT) /* 0x00002000 */ +#define GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT (14U) +#define GMAC_MAC_HW_FEATURE1_ADDR64_MASK (0x3U << GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT) /* 0x0000C000 */ +#define GMAC_MAC_HW_FEATURE1_DCBEN_SHIFT (16U) +#define GMAC_MAC_HW_FEATURE1_DCBEN_MASK (0x1U << GMAC_MAC_HW_FEATURE1_DCBEN_SHIFT) /* 0x00010000 */ +#define GMAC_MAC_HW_FEATURE1_SPHEN_SHIFT (17U) +#define GMAC_MAC_HW_FEATURE1_SPHEN_MASK (0x1U << GMAC_MAC_HW_FEATURE1_SPHEN_SHIFT) /* 0x00020000 */ +#define GMAC_MAC_HW_FEATURE1_TSOEN_SHIFT (18U) +#define GMAC_MAC_HW_FEATURE1_TSOEN_MASK (0x1U << GMAC_MAC_HW_FEATURE1_TSOEN_SHIFT) /* 0x00040000 */ +#define GMAC_MAC_HW_FEATURE1_DBGMEMA_SHIFT (19U) +#define GMAC_MAC_HW_FEATURE1_DBGMEMA_MASK (0x1U << GMAC_MAC_HW_FEATURE1_DBGMEMA_SHIFT) /* 0x00080000 */ +#define GMAC_MAC_HW_FEATURE1_AVSEL_SHIFT (20U) +#define GMAC_MAC_HW_FEATURE1_AVSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE1_AVSEL_SHIFT) /* 0x00100000 */ +#define GMAC_MAC_HW_FEATURE1_RAVSEL_SHIFT (21U) +#define GMAC_MAC_HW_FEATURE1_RAVSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE1_RAVSEL_SHIFT) /* 0x00200000 */ +#define GMAC_MAC_HW_FEATURE1_POUOST_SHIFT (23U) +#define GMAC_MAC_HW_FEATURE1_POUOST_MASK (0x1U << GMAC_MAC_HW_FEATURE1_POUOST_SHIFT) /* 0x00800000 */ +#define GMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT (24U) +#define GMAC_MAC_HW_FEATURE1_HASHTBLSZ_MASK (0x3U << GMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT) /* 0x03000000 */ +#define GMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT (27U) +#define GMAC_MAC_HW_FEATURE1_L3L4FNUM_MASK (0xFU << GMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT) /* 0x78000000 */ +/* MAC_HW_FEATURE2 */ +#define GMAC_MAC_HW_FEATURE2_OFFSET (0x124U) +#define GMAC_MAC_HW_FEATURE2 (0x10000000U) +#define GMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT (0U) +#define GMAC_MAC_HW_FEATURE2_RXQCNT_MASK (0xFU << GMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT) /* 0x0000000F */ +#define GMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT (6U) +#define GMAC_MAC_HW_FEATURE2_TXQCNT_MASK (0xFU << GMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT) /* 0x000003C0 */ +#define GMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT (12U) +#define GMAC_MAC_HW_FEATURE2_RXCHCNT_MASK (0xFU << GMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT) /* 0x0000F000 */ +#define GMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT (18U) +#define GMAC_MAC_HW_FEATURE2_TXCHCNT_MASK (0xFU << GMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT) /* 0x003C0000 */ +#define GMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT (24U) +#define GMAC_MAC_HW_FEATURE2_PPSOUTNUM_MASK (0x7U << GMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT) /* 0x07000000 */ +#define GMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT (28U) +#define GMAC_MAC_HW_FEATURE2_AUXSNAPNUM_MASK (0x7U << GMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT) /* 0x70000000 */ +/* MAC_HW_FEATURE3 */ +#define GMAC_MAC_HW_FEATURE3_OFFSET (0x128U) +#define GMAC_MAC_HW_FEATURE3_NRVF_SHIFT (0U) +#define GMAC_MAC_HW_FEATURE3_NRVF_MASK (0x7U << GMAC_MAC_HW_FEATURE3_NRVF_SHIFT) /* 0x00000007 */ +#define GMAC_MAC_HW_FEATURE3_CBTISEL_SHIFT (4U) +#define GMAC_MAC_HW_FEATURE3_CBTISEL_MASK (0x1U << GMAC_MAC_HW_FEATURE3_CBTISEL_SHIFT) /* 0x00000010 */ +#define GMAC_MAC_HW_FEATURE3_DVLAN_SHIFT (5U) +#define GMAC_MAC_HW_FEATURE3_DVLAN_MASK (0x1U << GMAC_MAC_HW_FEATURE3_DVLAN_SHIFT) /* 0x00000020 */ +#define GMAC_MAC_HW_FEATURE3_PDUPSEL_SHIFT (9U) +#define GMAC_MAC_HW_FEATURE3_PDUPSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE3_PDUPSEL_SHIFT) /* 0x00000200 */ +#define GMAC_MAC_HW_FEATURE3_FRPSEL_SHIFT (10U) +#define GMAC_MAC_HW_FEATURE3_FRPSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE3_FRPSEL_SHIFT) /* 0x00000400 */ +#define GMAC_MAC_HW_FEATURE3_FRPBS_SHIFT (11U) +#define GMAC_MAC_HW_FEATURE3_FRPBS_MASK (0x3U << GMAC_MAC_HW_FEATURE3_FRPBS_SHIFT) /* 0x00001800 */ +#define GMAC_MAC_HW_FEATURE3_FRPES_SHIFT (13U) +#define GMAC_MAC_HW_FEATURE3_FRPES_MASK (0x3U << GMAC_MAC_HW_FEATURE3_FRPES_SHIFT) /* 0x00006000 */ +#define GMAC_MAC_HW_FEATURE3_ESTSEL_SHIFT (16U) +#define GMAC_MAC_HW_FEATURE3_ESTSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE3_ESTSEL_SHIFT) /* 0x00010000 */ +#define GMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT (17U) +#define GMAC_MAC_HW_FEATURE3_ESTDEP_MASK (0x7U << GMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT) /* 0x000E0000 */ +#define GMAC_MAC_HW_FEATURE3_ESTWID_SHIFT (20U) +#define GMAC_MAC_HW_FEATURE3_ESTWID_MASK (0x3U << GMAC_MAC_HW_FEATURE3_ESTWID_SHIFT) /* 0x00300000 */ +#define GMAC_MAC_HW_FEATURE3_FPESEL_SHIFT (26U) +#define GMAC_MAC_HW_FEATURE3_FPESEL_MASK (0x1U << GMAC_MAC_HW_FEATURE3_FPESEL_SHIFT) /* 0x04000000 */ +#define GMAC_MAC_HW_FEATURE3_TBSSEL_SHIFT (27U) +#define GMAC_MAC_HW_FEATURE3_TBSSEL_MASK (0x1U << GMAC_MAC_HW_FEATURE3_TBSSEL_SHIFT) /* 0x08000000 */ +#define GMAC_MAC_HW_FEATURE3_ASP_SHIFT (28U) +#define GMAC_MAC_HW_FEATURE3_ASP_MASK (0x3U << GMAC_MAC_HW_FEATURE3_ASP_SHIFT) /* 0x30000000 */ +/* MAC_MDIO_ADDRESS */ +#define GMAC_MAC_MDIO_ADDRESS_OFFSET (0x200U) +#define GMAC_MAC_MDIO_ADDRESS_GB_SHIFT (0U) +#define GMAC_MAC_MDIO_ADDRESS_GB_MASK (0x1U << GMAC_MAC_MDIO_ADDRESS_GB_SHIFT) /* 0x00000001 */ +#define GMAC_MAC_MDIO_ADDRESS_C45E_SHIFT (1U) +#define GMAC_MAC_MDIO_ADDRESS_C45E_MASK (0x1U << GMAC_MAC_MDIO_ADDRESS_C45E_SHIFT) /* 0x00000002 */ +#define GMAC_MAC_MDIO_ADDRESS_GOC_0_SHIFT (2U) +#define GMAC_MAC_MDIO_ADDRESS_GOC_0_MASK (0x1U << GMAC_MAC_MDIO_ADDRESS_GOC_0_SHIFT) /* 0x00000004 */ +#define GMAC_MAC_MDIO_ADDRESS_GOC_1_SHIFT (3U) +#define GMAC_MAC_MDIO_ADDRESS_GOC_1_MASK (0x1U << GMAC_MAC_MDIO_ADDRESS_GOC_1_SHIFT) /* 0x00000008 */ +#define GMAC_MAC_MDIO_ADDRESS_SKAP_SHIFT (4U) +#define GMAC_MAC_MDIO_ADDRESS_SKAP_MASK (0x1U << GMAC_MAC_MDIO_ADDRESS_SKAP_SHIFT) /* 0x00000010 */ +#define GMAC_MAC_MDIO_ADDRESS_CR_SHIFT (8U) +#define GMAC_MAC_MDIO_ADDRESS_CR_MASK (0xFU << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) /* 0x00000F00 */ +#define GMAC_MAC_MDIO_ADDRESS_NTC_SHIFT (12U) +#define GMAC_MAC_MDIO_ADDRESS_NTC_MASK (0x7U << GMAC_MAC_MDIO_ADDRESS_NTC_SHIFT) /* 0x00007000 */ +#define GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT (16U) +#define GMAC_MAC_MDIO_ADDRESS_RDA_MASK (0x1FU << GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) /* 0x001F0000 */ +#define GMAC_MAC_MDIO_ADDRESS_PA_SHIFT (21U) +#define GMAC_MAC_MDIO_ADDRESS_PA_MASK (0x1FU << GMAC_MAC_MDIO_ADDRESS_PA_SHIFT) /* 0x03E00000 */ +#define GMAC_MAC_MDIO_ADDRESS_BTB_SHIFT (26U) +#define GMAC_MAC_MDIO_ADDRESS_BTB_MASK (0x1U << GMAC_MAC_MDIO_ADDRESS_BTB_SHIFT) /* 0x04000000 */ +#define GMAC_MAC_MDIO_ADDRESS_PSE_SHIFT (27U) +#define GMAC_MAC_MDIO_ADDRESS_PSE_MASK (0x1U << GMAC_MAC_MDIO_ADDRESS_PSE_SHIFT) /* 0x08000000 */ +/* MAC_MDIO_DATA */ +#define GMAC_MAC_MDIO_DATA_OFFSET (0x204U) +#define GMAC_MAC_MDIO_DATA_GD_SHIFT (0U) +#define GMAC_MAC_MDIO_DATA_GD_MASK (0xFFFFU << GMAC_MAC_MDIO_DATA_GD_SHIFT) /* 0x0000FFFF */ +#define GMAC_MAC_MDIO_DATA_RA_SHIFT (16U) +#define GMAC_MAC_MDIO_DATA_RA_MASK (0x1U << GMAC_MAC_MDIO_DATA_RA_SHIFT) /* 0x00010000 */ +/* MAC_CSR_SW_CTRL */ +#define GMAC_MAC_CSR_SW_CTRL_OFFSET (0x230U) +#define GMAC_MAC_CSR_SW_CTRL_RCWE_SHIFT (0U) +#define GMAC_MAC_CSR_SW_CTRL_RCWE_MASK (0x1U << GMAC_MAC_CSR_SW_CTRL_RCWE_SHIFT) /* 0x00000001 */ +/* MAC_ADDRESS0_HIGH */ +#define GMAC_MAC_ADDRESS0_HIGH_OFFSET (0x300U) +#define GMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT (0U) +#define GMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK (0xFFFFU << GMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT) /* 0x0000FFFF */ +#define GMAC_MAC_ADDRESS0_HIGH_AE_SHIFT (31U) +#define GMAC_MAC_ADDRESS0_HIGH_AE_MASK (0x1U << GMAC_MAC_ADDRESS0_HIGH_AE_SHIFT) /* 0x80000000 */ +/* MAC_ADDRESS0_LOW */ +#define GMAC_MAC_ADDRESS0_LOW_OFFSET (0x304U) +#define GMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT (0U) +#define GMAC_MAC_ADDRESS0_LOW_ADDRLO_MASK (0xFFFFFFFFU << GMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT) /* 0xFFFFFFFF */ +/* MMC_CONTROL */ +#define GMAC_MMC_CONTROL_OFFSET (0x700U) +#define GMAC_MMC_CONTROL_CNTRST_SHIFT (0U) +#define GMAC_MMC_CONTROL_CNTRST_MASK (0x1U << GMAC_MMC_CONTROL_CNTRST_SHIFT) /* 0x00000001 */ +#define GMAC_MMC_CONTROL_CNTSTOPRO_SHIFT (1U) +#define GMAC_MMC_CONTROL_CNTSTOPRO_MASK (0x1U << GMAC_MMC_CONTROL_CNTSTOPRO_SHIFT) /* 0x00000002 */ +#define GMAC_MMC_CONTROL_RSTONRD_SHIFT (2U) +#define GMAC_MMC_CONTROL_RSTONRD_MASK (0x1U << GMAC_MMC_CONTROL_RSTONRD_SHIFT) /* 0x00000004 */ +#define GMAC_MMC_CONTROL_CNTFREEZ_SHIFT (3U) +#define GMAC_MMC_CONTROL_CNTFREEZ_MASK (0x1U << GMAC_MMC_CONTROL_CNTFREEZ_SHIFT) /* 0x00000008 */ +#define GMAC_MMC_CONTROL_CNTPRST_SHIFT (4U) +#define GMAC_MMC_CONTROL_CNTPRST_MASK (0x1U << GMAC_MMC_CONTROL_CNTPRST_SHIFT) /* 0x00000010 */ +#define GMAC_MMC_CONTROL_CNTPRSTLVL_SHIFT (5U) +#define GMAC_MMC_CONTROL_CNTPRSTLVL_MASK (0x1U << GMAC_MMC_CONTROL_CNTPRSTLVL_SHIFT) /* 0x00000020 */ +#define GMAC_MMC_CONTROL_UCDBC_SHIFT (8U) +#define GMAC_MMC_CONTROL_UCDBC_MASK (0x1U << GMAC_MMC_CONTROL_UCDBC_SHIFT) /* 0x00000100 */ +/* MMC_RX_INTERRUPT */ +#define GMAC_MMC_RX_INTERRUPT_OFFSET (0x704U) +#define GMAC_MMC_RX_INTERRUPT (0x0U) +#define GMAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT (0U) +#define GMAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT) /* 0x00000001 */ +#define GMAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT (1U) +#define GMAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT) /* 0x00000002 */ +#define GMAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT (2U) +#define GMAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT) /* 0x00000004 */ +#define GMAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT (4U) +#define GMAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT) /* 0x00000010 */ +#define GMAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT (5U) +#define GMAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT) /* 0x00000020 */ +#define GMAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT (18U) +#define GMAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT) /* 0x00040000 */ +#define GMAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT (21U) +#define GMAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT) /* 0x00200000 */ +/* MMC_TX_INTERRUPT */ +#define GMAC_MMC_TX_INTERRUPT_OFFSET (0x708U) +#define GMAC_MMC_TX_INTERRUPT (0x0U) +#define GMAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT (0U) +#define GMAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK (0x1U << GMAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT) /* 0x00000001 */ +#define GMAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT (1U) +#define GMAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK (0x1U << GMAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT) /* 0x00000002 */ +#define GMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT (13U) +#define GMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK (0x1U << GMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT) /* 0x00002000 */ +#define GMAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT (19U) +#define GMAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK (0x1U << GMAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT) /* 0x00080000 */ +#define GMAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT (20U) +#define GMAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK (0x1U << GMAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT) /* 0x00100000 */ +#define GMAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT (21U) +#define GMAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK (0x1U << GMAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT) /* 0x00200000 */ +/* MMC_RX_INTERRUPT_MASK */ +#define GMAC_MMC_RX_INTERRUPT_MASK_OFFSET (0x70CU) +#define GMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT (0U) +#define GMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT) /* 0x00000001 */ +#define GMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT (1U) +#define GMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT) /* 0x00000002 */ +#define GMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT (2U) +#define GMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT) /* 0x00000004 */ +#define GMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT (4U) +#define GMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT) /* 0x00000010 */ +#define GMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT (5U) +#define GMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT) /* 0x00000020 */ +#define GMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT (18U) +#define GMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT) /* 0x00040000 */ +#define GMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT (21U) +#define GMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK (0x1U << GMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT) /* 0x00200000 */ +/* MMC_TX_INTERRUPT_MASK */ +#define GMAC_MMC_TX_INTERRUPT_MASK_OFFSET (0x710U) +#define GMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT (0U) +#define GMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK (0x1U << GMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT) /* 0x00000001 */ +#define GMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT (1U) +#define GMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK (0x1U << GMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT) /* 0x00000002 */ +#define GMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT (13U) +#define GMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK (0x1U << GMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT) /* 0x00002000 */ +#define GMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT (19U) +#define GMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK (0x1U << GMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT) /* 0x00080000 */ +#define GMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT (20U) +#define GMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK (0x1U << GMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT) /* 0x00100000 */ +#define GMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT (21U) +#define GMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK (0x1U << GMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT) /* 0x00200000 */ +/* TX_OCTET_COUNT_GOOD_BAD */ +#define GMAC_TX_OCTET_COUNT_GOOD_BAD_OFFSET (0x714U) +#define GMAC_TX_OCTET_COUNT_GOOD_BAD (0x0U) +#define GMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT (0U) +#define GMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK (0xFFFFFFFFU << GMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT) /* 0xFFFFFFFF */ +/* TX_PACKET_COUNT_GOOD_BAD */ +#define GMAC_TX_PACKET_COUNT_GOOD_BAD_OFFSET (0x718U) +#define GMAC_TX_PACKET_COUNT_GOOD_BAD (0x0U) +#define GMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT (0U) +#define GMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK (0xFFFFFFFFU << GMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT) /* 0xFFFFFFFF */ +/* TX_UNDERFLOW_ERROR_PACKETS */ +#define GMAC_TX_UNDERFLOW_ERROR_PACKETS_OFFSET (0x748U) +#define GMAC_TX_UNDERFLOW_ERROR_PACKETS (0x0U) +#define GMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT (0U) +#define GMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK (0xFFFFFFFFU << GMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT) /* 0xFFFFFFFF */ +/* TX_CARRIER_ERROR_PACKETS */ +#define GMAC_TX_CARRIER_ERROR_PACKETS_OFFSET (0x760U) +#define GMAC_TX_CARRIER_ERROR_PACKETS (0x0U) +#define GMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT (0U) +#define GMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK (0xFFFFFFFFU << GMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT) /* 0xFFFFFFFF */ +/* TX_OCTET_COUNT_GOOD */ +#define GMAC_TX_OCTET_COUNT_GOOD_OFFSET (0x764U) +#define GMAC_TX_OCTET_COUNT_GOOD (0x0U) +#define GMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT (0U) +#define GMAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK (0xFFFFFFFFU << GMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT) /* 0xFFFFFFFF */ +/* TX_PACKET_COUNT_GOOD */ +#define GMAC_TX_PACKET_COUNT_GOOD_OFFSET (0x768U) +#define GMAC_TX_PACKET_COUNT_GOOD (0x0U) +#define GMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT (0U) +#define GMAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK (0xFFFFFFFFU << GMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT) /* 0xFFFFFFFF */ +/* RX_PACKETS_COUNT_GOOD_BAD */ +#define GMAC_RX_PACKETS_COUNT_GOOD_BAD_OFFSET (0x780U) +#define GMAC_RX_PACKETS_COUNT_GOOD_BAD (0x0U) +#define GMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT (0U) +#define GMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK (0xFFFFFFFFU << GMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT) /* 0xFFFFFFFF */ +/* RX_OCTET_COUNT_GOOD_BAD */ +#define GMAC_RX_OCTET_COUNT_GOOD_BAD_OFFSET (0x784U) +#define GMAC_RX_OCTET_COUNT_GOOD_BAD (0x0U) +#define GMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT (0U) +#define GMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK (0xFFFFFFFFU << GMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT) /* 0xFFFFFFFF */ +/* RX_OCTET_COUNT_GOOD */ +#define GMAC_RX_OCTET_COUNT_GOOD_OFFSET (0x788U) +#define GMAC_RX_OCTET_COUNT_GOOD (0x0U) +#define GMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT (0U) +#define GMAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK (0xFFFFFFFFU << GMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT) /* 0xFFFFFFFF */ +/* RX_MULTICAST_PACKETS_GOOD */ +#define GMAC_RX_MULTICAST_PACKETS_GOOD_OFFSET (0x790U) +#define GMAC_RX_MULTICAST_PACKETS_GOOD (0x0U) +#define GMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT (0U) +#define GMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK (0xFFFFFFFFU << GMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT) /* 0xFFFFFFFF */ +/* RX_CRC_ERROR_PACKETS */ +#define GMAC_RX_CRC_ERROR_PACKETS_OFFSET (0x794U) +#define GMAC_RX_CRC_ERROR_PACKETS (0x0U) +#define GMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT (0U) +#define GMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK (0xFFFFFFFFU << GMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT) /* 0xFFFFFFFF */ +/* RX_LENGTH_ERROR_PACKETS */ +#define GMAC_RX_LENGTH_ERROR_PACKETS_OFFSET (0x7C8U) +#define GMAC_RX_LENGTH_ERROR_PACKETS (0x0U) +#define GMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT (0U) +#define GMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK (0xFFFFFFFFU << GMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT) /* 0xFFFFFFFF */ +/* RX_FIFO_OVERFLOW_PACKETS */ +#define GMAC_RX_FIFO_OVERFLOW_PACKETS_OFFSET (0x7D4U) +#define GMAC_RX_FIFO_OVERFLOW_PACKETS (0x0U) +#define GMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT (0U) +#define GMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK (0xFFFFFFFFU << GMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT) /* 0xFFFFFFFF */ +/* MMC_IPC_RX_INTERRUPT_MASK */ +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_OFFSET (0x800U) +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_SHIFT (0U) +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_SHIFT) /* 0x00000001 */ +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_SHIFT (1U) +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_SHIFT) /* 0x00000002 */ +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_SHIFT (5U) +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_SHIFT) /* 0x00000020 */ +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_SHIFT (6U) +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_SHIFT) /* 0x00000040 */ +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_SHIFT (9U) +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_SHIFT) /* 0x00000200 */ +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_SHIFT (11U) +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_SHIFT) /* 0x00000800 */ +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_SHIFT (13U) +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_SHIFT) /* 0x00002000 */ +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_SHIFT (17U) +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_SHIFT) /* 0x00020000 */ +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_SHIFT (22U) +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_SHIFT) /* 0x00400000 */ +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_SHIFT (25U) +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_SHIFT) /* 0x02000000 */ +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_SHIFT (27U) +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_SHIFT) /* 0x08000000 */ +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_SHIFT (29U) +#define GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_SHIFT) /* 0x20000000 */ +/* MMC_IPC_RX_INTERRUPT */ +#define GMAC_MMC_IPC_RX_INTERRUPT_OFFSET (0x808U) +#define GMAC_MMC_IPC_RX_INTERRUPT (0x0U) +#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_SHIFT (0U) +#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_SHIFT) /* 0x00000001 */ +#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_SHIFT (1U) +#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_SHIFT) /* 0x00000002 */ +#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_SHIFT (5U) +#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_SHIFT) /* 0x00000020 */ +#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_SHIFT (6U) +#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_SHIFT) /* 0x00000040 */ +#define GMAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_SHIFT (9U) +#define GMAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_SHIFT) /* 0x00000200 */ +#define GMAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_SHIFT (11U) +#define GMAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_SHIFT) /* 0x00000800 */ +#define GMAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_SHIFT (13U) +#define GMAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_SHIFT) /* 0x00002000 */ +#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_SHIFT (17U) +#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_SHIFT) /* 0x00020000 */ +#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_SHIFT (22U) +#define GMAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_SHIFT) /* 0x00400000 */ +#define GMAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_SHIFT (25U) +#define GMAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_SHIFT) /* 0x02000000 */ +#define GMAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_SHIFT (27U) +#define GMAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_SHIFT) /* 0x08000000 */ +#define GMAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_SHIFT (29U) +#define GMAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_MASK (0x1U << GMAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_SHIFT) /* 0x20000000 */ +/* RXIPV4_GOOD_PACKETS */ +#define GMAC_RXIPV4_GOOD_PACKETS_OFFSET (0x810U) +#define GMAC_RXIPV4_GOOD_PACKETS (0x0U) +#define GMAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_SHIFT (0U) +#define GMAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_MASK (0xFFFFFFFFU << GMAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_SHIFT) /* 0xFFFFFFFF */ +/* RXIPV4_HEADER_ERROR_PACKETS */ +#define GMAC_RXIPV4_HEADER_ERROR_PACKETS_OFFSET (0x814U) +#define GMAC_RXIPV4_HEADER_ERROR_PACKETS (0x0U) +#define GMAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_SHIFT (0U) +#define GMAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_MASK (0xFFFFFFFFU << GMAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_SHIFT) /* 0xFFFFFFFF */ +/* RXIPV6_GOOD_PACKETS */ +#define GMAC_RXIPV6_GOOD_PACKETS_OFFSET (0x824U) +#define GMAC_RXIPV6_GOOD_PACKETS (0x0U) +#define GMAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_SHIFT (0U) +#define GMAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_MASK (0xFFFFFFFFU << GMAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_SHIFT) /* 0xFFFFFFFF */ +/* RXIPV6_HEADER_ERROR_PACKETS */ +#define GMAC_RXIPV6_HEADER_ERROR_PACKETS_OFFSET (0x828U) +#define GMAC_RXIPV6_HEADER_ERROR_PACKETS (0x0U) +#define GMAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_SHIFT (0U) +#define GMAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_MASK (0xFFFFFFFFU << GMAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_SHIFT) /* 0xFFFFFFFF */ +/* RXUDP_ERROR_PACKETS */ +#define GMAC_RXUDP_ERROR_PACKETS_OFFSET (0x834U) +#define GMAC_RXUDP_ERROR_PACKETS (0x0U) +#define GMAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_SHIFT (0U) +#define GMAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_MASK (0xFFFFFFFFU << GMAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_SHIFT) /* 0xFFFFFFFF */ +/* RXTCP_ERROR_PACKETS */ +#define GMAC_RXTCP_ERROR_PACKETS_OFFSET (0x83CU) +#define GMAC_RXTCP_ERROR_PACKETS (0x0U) +#define GMAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_SHIFT (0U) +#define GMAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_MASK (0xFFFFFFFFU << GMAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_SHIFT) /* 0xFFFFFFFF */ +/* RXICMP_ERROR_PACKETS */ +#define GMAC_RXICMP_ERROR_PACKETS_OFFSET (0x844U) +#define GMAC_RXICMP_ERROR_PACKETS (0x0U) +#define GMAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_SHIFT (0U) +#define GMAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_MASK (0xFFFFFFFFU << GMAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_SHIFT) /* 0xFFFFFFFF */ +/* RXIPV4_HEADER_ERROR_OCTETS */ +#define GMAC_RXIPV4_HEADER_ERROR_OCTETS_OFFSET (0x854U) +#define GMAC_RXIPV4_HEADER_ERROR_OCTETS (0x0U) +#define GMAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_SHIFT (0U) +#define GMAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_MASK (0xFFFFFFFFU << GMAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_SHIFT) /* 0xFFFFFFFF */ +/* RXIPV6_HEADER_ERROR_OCTETS */ +#define GMAC_RXIPV6_HEADER_ERROR_OCTETS_OFFSET (0x868U) +#define GMAC_RXIPV6_HEADER_ERROR_OCTETS (0x0U) +#define GMAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_SHIFT (0U) +#define GMAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_MASK (0xFFFFFFFFU << GMAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_SHIFT) /* 0xFFFFFFFF */ +/* RXUDP_ERROR_OCTETS */ +#define GMAC_RXUDP_ERROR_OCTETS_OFFSET (0x874U) +#define GMAC_RXUDP_ERROR_OCTETS (0x0U) +#define GMAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_SHIFT (0U) +#define GMAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_MASK (0xFFFFFFFFU << GMAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_SHIFT) /* 0xFFFFFFFF */ +/* RXTCP_ERROR_OCTETS */ +#define GMAC_RXTCP_ERROR_OCTETS_OFFSET (0x87CU) +#define GMAC_RXTCP_ERROR_OCTETS (0x0U) +#define GMAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_SHIFT (0U) +#define GMAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_MASK (0xFFFFFFFFU << GMAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_SHIFT) /* 0xFFFFFFFF */ +/* RXICMP_ERROR_OCTETS */ +#define GMAC_RXICMP_ERROR_OCTETS_OFFSET (0x884U) +#define GMAC_RXICMP_ERROR_OCTETS (0x0U) +#define GMAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_SHIFT (0U) +#define GMAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_MASK (0xFFFFFFFFU << GMAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_SHIFT) /* 0xFFFFFFFF */ +/* MAC_TIMESTAMP_CONTROL */ +#define GMAC_MAC_TIMESTAMP_CONTROL_OFFSET (0xB00U) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT (0U) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSENA_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT) /* 0x00000001 */ +#define GMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT (1U) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT) /* 0x00000002 */ +#define GMAC_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT (2U) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSINIT_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT) /* 0x00000004 */ +#define GMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT (3U) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT) /* 0x00000008 */ +#define GMAC_MAC_TIMESTAMP_CONTROL_TSTRIG_SHIFT (4U) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSTRIG_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSTRIG_SHIFT) /* 0x00000010 */ +#define GMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT (5U) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT) /* 0x00000020 */ +#define GMAC_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT (8U) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSENALL_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT) /* 0x00000100 */ +#define GMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT (9U) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT) /* 0x00000200 */ +#define GMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT (10U) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT) /* 0x00000400 */ +#define GMAC_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT (11U) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT) /* 0x00000800 */ +#define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT (12U) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT) /* 0x00001000 */ +#define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT (13U) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT) /* 0x00002000 */ +#define GMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT (14U) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT) /* 0x00004000 */ +#define GMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT (15U) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT) /* 0x00008000 */ +#define GMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT (16U) +#define GMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK (0x3U << GMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT) /* 0x00030000 */ +#define GMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT (18U) +#define GMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT) /* 0x00040000 */ +#define GMAC_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT (20U) +#define GMAC_MAC_TIMESTAMP_CONTROL_ESTI_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT) /* 0x00100000 */ +#define GMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT (24U) +#define GMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT) /* 0x01000000 */ +#define GMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT (28U) +#define GMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK (0x1U << GMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT) /* 0x10000000 */ +/* MAC_SUB_SECOND_INCREMENT */ +#define GMAC_MAC_SUB_SECOND_INCREMENT_OFFSET (0xB04U) +#define GMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT (16U) +#define GMAC_MAC_SUB_SECOND_INCREMENT_SSINC_MASK (0xFFU << GMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT) /* 0x00FF0000 */ +/* MAC_SYSTEM_TIME_SECS */ +#define GMAC_MAC_SYSTEM_TIME_SECS_OFFSET (0xB08U) +#define GMAC_MAC_SYSTEM_TIME_SECS_TSS_SHIFT (0U) +#define GMAC_MAC_SYSTEM_TIME_SECS_TSS_MASK (0xFFFFFFFFU << GMAC_MAC_SYSTEM_TIME_SECS_TSS_SHIFT) /* 0xFFFFFFFF */ +/* MAC_SYSTEM_TIME_NS */ +#define GMAC_MAC_SYSTEM_TIME_NS_OFFSET (0xB0CU) +#define GMAC_MAC_SYSTEM_TIME_NS_TSSS_SHIFT (0U) +#define GMAC_MAC_SYSTEM_TIME_NS_TSSS_MASK (0x7FFFFFFFU << GMAC_MAC_SYSTEM_TIME_NS_TSSS_SHIFT) /* 0x7FFFFFFF */ +/* MAC_SYS_TIME_SECS_UPDATE */ +#define GMAC_MAC_SYS_TIME_SECS_UPDATE_OFFSET (0xB10U) +#define GMAC_MAC_SYS_TIME_SECS_UPDATE_TSS_SHIFT (0U) +#define GMAC_MAC_SYS_TIME_SECS_UPDATE_TSS_MASK (0xFFFFFFFFU << GMAC_MAC_SYS_TIME_SECS_UPDATE_TSS_SHIFT) /* 0xFFFFFFFF */ +/* MAC_SYS_TIME_NS_UPDATE */ +#define GMAC_MAC_SYS_TIME_NS_UPDATE_OFFSET (0xB14U) +#define GMAC_MAC_SYS_TIME_NS_UPDATE_TSSS_SHIFT (0U) +#define GMAC_MAC_SYS_TIME_NS_UPDATE_TSSS_MASK (0x7FFFFFFFU << GMAC_MAC_SYS_TIME_NS_UPDATE_TSSS_SHIFT) /* 0x7FFFFFFF */ +#define GMAC_MAC_SYS_TIME_NS_UPDATE_ADDSUB_SHIFT (31U) +#define GMAC_MAC_SYS_TIME_NS_UPDATE_ADDSUB_MASK (0x1U << GMAC_MAC_SYS_TIME_NS_UPDATE_ADDSUB_SHIFT) /* 0x80000000 */ +/* MAC_TIMESTAMP_ADDEND */ +#define GMAC_MAC_TIMESTAMP_ADDEND_OFFSET (0xB18U) +#define GMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT (0U) +#define GMAC_MAC_TIMESTAMP_ADDEND_TSAR_MASK (0xFFFFFFFFU << GMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT) /* 0xFFFFFFFF */ +/* MAC_TIMESTAMP_STATUS */ +#define GMAC_MAC_TIMESTAMP_STATUS_OFFSET (0xB20U) +#define GMAC_MAC_TIMESTAMP_STATUS (0x0U) +#define GMAC_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT (0U) +#define GMAC_MAC_TIMESTAMP_STATUS_TSSOVF_MASK (0x1U << GMAC_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT) /* 0x00000001 */ +#define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT (1U) +#define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK (0x1U << GMAC_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT) /* 0x00000002 */ +#define GMAC_MAC_TIMESTAMP_STATUS_AUXTSTRIG_SHIFT (2U) +#define GMAC_MAC_TIMESTAMP_STATUS_AUXTSTRIG_MASK (0x1U << GMAC_MAC_TIMESTAMP_STATUS_AUXTSTRIG_SHIFT) /* 0x00000004 */ +#define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT (3U) +#define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK (0x1U << GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT) /* 0x00000008 */ +#define GMAC_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT (15U) +#define GMAC_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK (0x1U << GMAC_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT) /* 0x00008000 */ +#define GMAC_MAC_TIMESTAMP_STATUS_ATSSTM_SHIFT (24U) +#define GMAC_MAC_TIMESTAMP_STATUS_ATSSTM_MASK (0x1U << GMAC_MAC_TIMESTAMP_STATUS_ATSSTM_SHIFT) /* 0x01000000 */ +#define GMAC_MAC_TIMESTAMP_STATUS_ATSNS_SHIFT (25U) +#define GMAC_MAC_TIMESTAMP_STATUS_ATSNS_MASK (0x1FU << GMAC_MAC_TIMESTAMP_STATUS_ATSNS_SHIFT) /* 0x3E000000 */ +/* MAC_TX_TS_STATUS_NS */ +#define GMAC_MAC_TX_TS_STATUS_NS_OFFSET (0xB30U) +#define GMAC_MAC_TX_TS_STATUS_NS (0x0U) +#define GMAC_MAC_TX_TS_STATUS_NS_TXTSSLO_SHIFT (0U) +#define GMAC_MAC_TX_TS_STATUS_NS_TXTSSLO_MASK (0x7FFFFFFFU << GMAC_MAC_TX_TS_STATUS_NS_TXTSSLO_SHIFT) /* 0x7FFFFFFF */ +#define GMAC_MAC_TX_TS_STATUS_NS_TXTSSMIS_SHIFT (31U) +#define GMAC_MAC_TX_TS_STATUS_NS_TXTSSMIS_MASK (0x1U << GMAC_MAC_TX_TS_STATUS_NS_TXTSSMIS_SHIFT) /* 0x80000000 */ +/* MAC_TX_TS_STATUS_SECS */ +#define GMAC_MAC_TX_TS_STATUS_SECS_OFFSET (0xB34U) +#define GMAC_MAC_TX_TS_STATUS_SECS (0x0U) +#define GMAC_MAC_TX_TS_STATUS_SECS_TXTSSHI_SHIFT (0U) +#define GMAC_MAC_TX_TS_STATUS_SECS_TXTSSHI_MASK (0xFFFFFFFFU << GMAC_MAC_TX_TS_STATUS_SECS_TXTSSHI_SHIFT) /* 0xFFFFFFFF */ +/* MAC_AUXILIARY_CONTROL */ +#define GMAC_MAC_AUXILIARY_CONTROL_OFFSET (0xB40U) +#define GMAC_MAC_AUXILIARY_CONTROL_ATSFC_SHIFT (0U) +#define GMAC_MAC_AUXILIARY_CONTROL_ATSFC_MASK (0x1U << GMAC_MAC_AUXILIARY_CONTROL_ATSFC_SHIFT) /* 0x00000001 */ +/* MAC_AUXILIARY_TS_NS */ +#define GMAC_MAC_AUXILIARY_TS_NS_OFFSET (0xB48U) +#define GMAC_MAC_AUXILIARY_TS_NS (0x0U) +#define GMAC_MAC_AUXILIARY_TS_NS_AUXTSLO_SHIFT (0U) +#define GMAC_MAC_AUXILIARY_TS_NS_AUXTSLO_MASK (0x7FFFFFFFU << GMAC_MAC_AUXILIARY_TS_NS_AUXTSLO_SHIFT) /* 0x7FFFFFFF */ +/* MAC_AUXILIARY_TS_SECS */ +#define GMAC_MAC_AUXILIARY_TS_SECS_OFFSET (0xB4CU) +#define GMAC_MAC_AUXILIARY_TS_SECS_AUXTSHI_SHIFT (0U) +#define GMAC_MAC_AUXILIARY_TS_SECS_AUXTSHI_MASK (0xFFFFFFFFU << GMAC_MAC_AUXILIARY_TS_SECS_AUXTSHI_SHIFT) /* 0xFFFFFFFF */ +/* MAC_TS_INGRESS_CORR_NS */ +#define GMAC_MAC_TS_INGRESS_CORR_NS_OFFSET (0xB58U) +#define GMAC_MAC_TS_INGRESS_CORR_NS_TSIC_SHIFT (0U) +#define GMAC_MAC_TS_INGRESS_CORR_NS_TSIC_MASK (0xFFFFFFFFU << GMAC_MAC_TS_INGRESS_CORR_NS_TSIC_SHIFT) /* 0xFFFFFFFF */ +/* MAC_TS_EGRESS_CORR_NS */ +#define GMAC_MAC_TS_EGRESS_CORR_NS_OFFSET (0xB5CU) +#define GMAC_MAC_TS_EGRESS_CORR_NS_TSEC_SHIFT (0U) +#define GMAC_MAC_TS_EGRESS_CORR_NS_TSEC_MASK (0xFFFFFFFFU << GMAC_MAC_TS_EGRESS_CORR_NS_TSEC_SHIFT) /* 0xFFFFFFFF */ +/* MAC_TS_INGRESS_LATENCY */ +#define GMAC_MAC_TS_INGRESS_LATENCY_OFFSET (0xB68U) +#define GMAC_MAC_TS_INGRESS_LATENCY (0x0U) +#define GMAC_MAC_TS_INGRESS_LATENCY_ITLSNS_SHIFT (8U) +#define GMAC_MAC_TS_INGRESS_LATENCY_ITLSNS_MASK (0xFFU << GMAC_MAC_TS_INGRESS_LATENCY_ITLSNS_SHIFT) /* 0x0000FF00 */ +#define GMAC_MAC_TS_INGRESS_LATENCY_ITLNS_SHIFT (16U) +#define GMAC_MAC_TS_INGRESS_LATENCY_ITLNS_MASK (0xFFU << GMAC_MAC_TS_INGRESS_LATENCY_ITLNS_SHIFT) /* 0x00FF0000 */ +/* MAC_TS_EGRESS_LATENCY */ +#define GMAC_MAC_TS_EGRESS_LATENCY_OFFSET (0xB6CU) +#define GMAC_MAC_TS_EGRESS_LATENCY (0x0U) +#define GMAC_MAC_TS_EGRESS_LATENCY_ETLSNS_SHIFT (8U) +#define GMAC_MAC_TS_EGRESS_LATENCY_ETLSNS_MASK (0xFFU << GMAC_MAC_TS_EGRESS_LATENCY_ETLSNS_SHIFT) /* 0x0000FF00 */ +#define GMAC_MAC_TS_EGRESS_LATENCY_ETLNS_SHIFT (16U) +#define GMAC_MAC_TS_EGRESS_LATENCY_ETLNS_MASK (0xFFU << GMAC_MAC_TS_EGRESS_LATENCY_ETLNS_SHIFT) /* 0x00FF0000 */ +/* MAC_PPS_CONTROL */ +#define GMAC_MAC_PPS_CONTROL_OFFSET (0xB70U) +#define GMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT (0U) +#define GMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK (0xFU << GMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT) /* 0x0000000F */ +/* MTL_DBG_CTL */ +#define GMAC_MTL_DBG_CTL_OFFSET (0xC08U) +#define GMAC_MTL_DBG_CTL_FDBGEN_SHIFT (0U) +#define GMAC_MTL_DBG_CTL_FDBGEN_MASK (0x1U << GMAC_MTL_DBG_CTL_FDBGEN_SHIFT) /* 0x00000001 */ +#define GMAC_MTL_DBG_CTL_DBGMOD_SHIFT (1U) +#define GMAC_MTL_DBG_CTL_DBGMOD_MASK (0x1U << GMAC_MTL_DBG_CTL_DBGMOD_SHIFT) /* 0x00000002 */ +#define GMAC_MTL_DBG_CTL_BYTEEN_SHIFT (2U) +#define GMAC_MTL_DBG_CTL_BYTEEN_MASK (0x3U << GMAC_MTL_DBG_CTL_BYTEEN_SHIFT) /* 0x0000000C */ +#define GMAC_MTL_DBG_CTL_PKTSTATE_SHIFT (5U) +#define GMAC_MTL_DBG_CTL_PKTSTATE_MASK (0x3U << GMAC_MTL_DBG_CTL_PKTSTATE_SHIFT) /* 0x00000060 */ +#define GMAC_MTL_DBG_CTL_RSTALL_SHIFT (8U) +#define GMAC_MTL_DBG_CTL_RSTALL_MASK (0x1U << GMAC_MTL_DBG_CTL_RSTALL_SHIFT) /* 0x00000100 */ +#define GMAC_MTL_DBG_CTL_RSTSEL_SHIFT (9U) +#define GMAC_MTL_DBG_CTL_RSTSEL_MASK (0x1U << GMAC_MTL_DBG_CTL_RSTSEL_SHIFT) /* 0x00000200 */ +#define GMAC_MTL_DBG_CTL_FIFORDEN_SHIFT (10U) +#define GMAC_MTL_DBG_CTL_FIFORDEN_MASK (0x1U << GMAC_MTL_DBG_CTL_FIFORDEN_SHIFT) /* 0x00000400 */ +#define GMAC_MTL_DBG_CTL_FIFOWREN_SHIFT (11U) +#define GMAC_MTL_DBG_CTL_FIFOWREN_MASK (0x1U << GMAC_MTL_DBG_CTL_FIFOWREN_SHIFT) /* 0x00000800 */ +#define GMAC_MTL_DBG_CTL_FIFOSEL_SHIFT (12U) +#define GMAC_MTL_DBG_CTL_FIFOSEL_MASK (0x3U << GMAC_MTL_DBG_CTL_FIFOSEL_SHIFT) /* 0x00003000 */ +#define GMAC_MTL_DBG_CTL_PKTIE_SHIFT (14U) +#define GMAC_MTL_DBG_CTL_PKTIE_MASK (0x1U << GMAC_MTL_DBG_CTL_PKTIE_SHIFT) /* 0x00004000 */ +#define GMAC_MTL_DBG_CTL_STSIE_SHIFT (15U) +#define GMAC_MTL_DBG_CTL_STSIE_MASK (0x1U << GMAC_MTL_DBG_CTL_STSIE_SHIFT) /* 0x00008000 */ +/* MTL_DBG_STS */ +#define GMAC_MTL_DBG_STS_OFFSET (0xC0CU) +#define GMAC_MTL_DBG_STS_FIFOBUSY_SHIFT (0U) +#define GMAC_MTL_DBG_STS_FIFOBUSY_MASK (0x1U << GMAC_MTL_DBG_STS_FIFOBUSY_SHIFT) /* 0x00000001 */ +#define GMAC_MTL_DBG_STS_PKTSTATE_SHIFT (1U) +#define GMAC_MTL_DBG_STS_PKTSTATE_MASK (0x3U << GMAC_MTL_DBG_STS_PKTSTATE_SHIFT) /* 0x00000006 */ +#define GMAC_MTL_DBG_STS_BYTEEN_SHIFT (3U) +#define GMAC_MTL_DBG_STS_BYTEEN_MASK (0x3U << GMAC_MTL_DBG_STS_BYTEEN_SHIFT) /* 0x00000018 */ +#define GMAC_MTL_DBG_STS_PKTI_SHIFT (8U) +#define GMAC_MTL_DBG_STS_PKTI_MASK (0x1U << GMAC_MTL_DBG_STS_PKTI_SHIFT) /* 0x00000100 */ +#define GMAC_MTL_DBG_STS_STSI_SHIFT (9U) +#define GMAC_MTL_DBG_STS_STSI_MASK (0x1U << GMAC_MTL_DBG_STS_STSI_SHIFT) /* 0x00000200 */ +#define GMAC_MTL_DBG_STS_LOCR_SHIFT (15U) +#define GMAC_MTL_DBG_STS_LOCR_MASK (0x1U << GMAC_MTL_DBG_STS_LOCR_SHIFT) /* 0x00008000 */ +/* MTL_FIFO_DEBUG_DATA */ +#define GMAC_MTL_FIFO_DEBUG_DATA_OFFSET (0xC10U) +#define GMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT (0U) +#define GMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK (0xFFFFFFFFU << GMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT) /* 0xFFFFFFFF */ +/* MTL_INTERRUPT_STATUS */ +#define GMAC_MTL_INTERRUPT_STATUS_OFFSET (0xC20U) +#define GMAC_MTL_INTERRUPT_STATUS (0x0U) +#define GMAC_MTL_INTERRUPT_STATUS_Q0IS_SHIFT (0U) +#define GMAC_MTL_INTERRUPT_STATUS_Q0IS_MASK (0x1U << GMAC_MTL_INTERRUPT_STATUS_Q0IS_SHIFT) /* 0x00000001 */ +#define GMAC_MTL_INTERRUPT_STATUS_DBGIS_SHIFT (17U) +#define GMAC_MTL_INTERRUPT_STATUS_DBGIS_MASK (0x1U << GMAC_MTL_INTERRUPT_STATUS_DBGIS_SHIFT) /* 0x00020000 */ +/* MTL_TXQ0_OPERATION_MODE */ +#define GMAC_MTL_TXQ0_OPERATION_MODE_OFFSET (0xD00U) +#define GMAC_MTL_TXQ0_OPERATION_MODE_FTQ_SHIFT (0U) +#define GMAC_MTL_TXQ0_OPERATION_MODE_FTQ_MASK (0x1U << GMAC_MTL_TXQ0_OPERATION_MODE_FTQ_SHIFT) /* 0x00000001 */ +#define GMAC_MTL_TXQ0_OPERATION_MODE_TSF_SHIFT (1U) +#define GMAC_MTL_TXQ0_OPERATION_MODE_TSF_MASK (0x1U << GMAC_MTL_TXQ0_OPERATION_MODE_TSF_SHIFT) /* 0x00000002 */ +#define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT (4U) +#define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_MASK (0x7U << GMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT) /* 0x00000070 */ +/* MTL_TXQ0_UNDERFLOW */ +#define GMAC_MTL_TXQ0_UNDERFLOW_OFFSET (0xD04U) +#define GMAC_MTL_TXQ0_UNDERFLOW (0x0U) +#define GMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT (0U) +#define GMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_MASK (0x7FFU << GMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT) /* 0x000007FF */ +#define GMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_SHIFT (11U) +#define GMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_MASK (0x1U << GMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_SHIFT) /* 0x00000800 */ +/* MTL_TXQ0_DEBUG */ +#define GMAC_MTL_TXQ0_DEBUG_OFFSET (0xD08U) +#define GMAC_MTL_TXQ0_DEBUG (0x0U) +#define GMAC_MTL_TXQ0_DEBUG_TXQPAUSED_SHIFT (0U) +#define GMAC_MTL_TXQ0_DEBUG_TXQPAUSED_MASK (0x1U << GMAC_MTL_TXQ0_DEBUG_TXQPAUSED_SHIFT) /* 0x00000001 */ +#define GMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT (1U) +#define GMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK (0x3U << GMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) /* 0x00000006 */ +#define GMAC_MTL_TXQ0_DEBUG_TWCSTS_SHIFT (3U) +#define GMAC_MTL_TXQ0_DEBUG_TWCSTS_MASK (0x1U << GMAC_MTL_TXQ0_DEBUG_TWCSTS_SHIFT) /* 0x00000008 */ +#define GMAC_MTL_TXQ0_DEBUG_TXQSTS_SHIFT (4U) +#define GMAC_MTL_TXQ0_DEBUG_TXQSTS_MASK (0x1U << GMAC_MTL_TXQ0_DEBUG_TXQSTS_SHIFT) /* 0x00000010 */ +#define GMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_SHIFT (5U) +#define GMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_MASK (0x1U << GMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_SHIFT) /* 0x00000020 */ +#define GMAC_MTL_TXQ0_DEBUG_PTXQ_SHIFT (16U) +#define GMAC_MTL_TXQ0_DEBUG_PTXQ_MASK (0x7U << GMAC_MTL_TXQ0_DEBUG_PTXQ_SHIFT) /* 0x00070000 */ +#define GMAC_MTL_TXQ0_DEBUG_STXSTSF_SHIFT (20U) +#define GMAC_MTL_TXQ0_DEBUG_STXSTSF_MASK (0x7U << GMAC_MTL_TXQ0_DEBUG_STXSTSF_SHIFT) /* 0x00700000 */ +/* MTL_Q0_INTERRUPT_CTRL_STATUS */ +#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_OFFSET (0xD2CU) +#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS_SHIFT (0U) +#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS_MASK (0x1U << GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS_SHIFT) /* 0x00000001 */ +#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUIE_SHIFT (8U) +#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUIE_MASK (0x1U << GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUIE_SHIFT) /* 0x00000100 */ +#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOVFIS_SHIFT (16U) +#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOVFIS_MASK (0x1U << GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOVFIS_SHIFT) /* 0x00010000 */ +#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOIE_SHIFT (24U) +#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOIE_MASK (0x1U << GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOIE_SHIFT) /* 0x01000000 */ +/* MTL_RXQ0_OPERATION_MODE */ +#define GMAC_MTL_RXQ0_OPERATION_MODE_OFFSET (0xD30U) +#define GMAC_MTL_RXQ0_OPERATION_MODE_RTC_SHIFT (0U) +#define GMAC_MTL_RXQ0_OPERATION_MODE_RTC_MASK (0x3U << GMAC_MTL_RXQ0_OPERATION_MODE_RTC_SHIFT) /* 0x00000003 */ +#define GMAC_MTL_RXQ0_OPERATION_MODE_FUP_SHIFT (3U) +#define GMAC_MTL_RXQ0_OPERATION_MODE_FUP_MASK (0x1U << GMAC_MTL_RXQ0_OPERATION_MODE_FUP_SHIFT) /* 0x00000008 */ +#define GMAC_MTL_RXQ0_OPERATION_MODE_FEP_SHIFT (4U) +#define GMAC_MTL_RXQ0_OPERATION_MODE_FEP_MASK (0x1U << GMAC_MTL_RXQ0_OPERATION_MODE_FEP_SHIFT) /* 0x00000010 */ +#define GMAC_MTL_RXQ0_OPERATION_MODE_RSF_SHIFT (5U) +#define GMAC_MTL_RXQ0_OPERATION_MODE_RSF_MASK (0x1U << GMAC_MTL_RXQ0_OPERATION_MODE_RSF_SHIFT) /* 0x00000020 */ +#define GMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_SHIFT (6U) +#define GMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_MASK (0x1U << GMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_SHIFT) /* 0x00000040 */ +#define GMAC_MTL_RXQ0_OPERATION_MODE_EHFC_SHIFT (7U) +#define GMAC_MTL_RXQ0_OPERATION_MODE_EHFC_MASK (0x1U << GMAC_MTL_RXQ0_OPERATION_MODE_EHFC_SHIFT) /* 0x00000080 */ +#define GMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT (8U) +#define GMAC_MTL_RXQ0_OPERATION_MODE_RFA_MASK (0x3FU << GMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT) /* 0x00003F00 */ +#define GMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT (14U) +#define GMAC_MTL_RXQ0_OPERATION_MODE_RFD_MASK (0x3FU << GMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) /* 0x000FC000 */ +/* MTL_RXQ0_MISS_PKT_OVF_CNT */ +#define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_OFFSET (0xD34U) +#define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT (0x0U) +#define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_OVFPKTCNT_SHIFT (0U) +#define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_OVFPKTCNT_MASK (0x7FFU << GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_OVFPKTCNT_SHIFT) /* 0x000007FF */ +#define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_OVFCNTOVF_SHIFT (11U) +#define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_OVFCNTOVF_MASK (0x1U << GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_OVFCNTOVF_SHIFT) /* 0x00000800 */ +#define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_MISPKTCNT_SHIFT (16U) +#define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_MISPKTCNT_MASK (0x7FFU << GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_MISPKTCNT_SHIFT) /* 0x07FF0000 */ +#define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_MISCNTOVF_SHIFT (27U) +#define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_MISCNTOVF_MASK (0x1U << GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT_MISCNTOVF_SHIFT) /* 0x08000000 */ +/* MTL_RXQ0_DEBUG */ +#define GMAC_MTL_RXQ0_DEBUG_OFFSET (0xD38U) +#define GMAC_MTL_RXQ0_DEBUG (0x0U) +#define GMAC_MTL_RXQ0_DEBUG_RWCSTS_SHIFT (0U) +#define GMAC_MTL_RXQ0_DEBUG_RWCSTS_MASK (0x1U << GMAC_MTL_RXQ0_DEBUG_RWCSTS_SHIFT) /* 0x00000001 */ +#define GMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT (1U) +#define GMAC_MTL_RXQ0_DEBUG_RRCSTS_MASK (0x3U << GMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT) /* 0x00000006 */ +#define GMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT (4U) +#define GMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK (0x3U << GMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) /* 0x00000030 */ +#define GMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT (16U) +#define GMAC_MTL_RXQ0_DEBUG_PRXQ_MASK (0xFU << GMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT) /* 0x000F0000 */ +/* DMA_MODE */ +#define GMAC_DMA_MODE_OFFSET (0x1000U) +#define GMAC_DMA_MODE_SWR_SHIFT (0U) +#define GMAC_DMA_MODE_SWR_MASK (0x1U << GMAC_DMA_MODE_SWR_SHIFT) /* 0x00000001 */ +#define GMAC_DMA_MODE_DSPW_SHIFT (8U) +#define GMAC_DMA_MODE_DSPW_MASK (0x1U << GMAC_DMA_MODE_DSPW_SHIFT) /* 0x00000100 */ +#define GMAC_DMA_MODE_INTM_SHIFT (16U) +#define GMAC_DMA_MODE_INTM_MASK (0x3U << GMAC_DMA_MODE_INTM_SHIFT) /* 0x00030000 */ +/* DMA_SYSBUS_MODE */ +#define GMAC_DMA_SYSBUS_MODE_OFFSET (0x1004U) +#define GMAC_DMA_SYSBUS_MODE_FB_SHIFT (0U) +#define GMAC_DMA_SYSBUS_MODE_FB_MASK (0x1U << GMAC_DMA_SYSBUS_MODE_FB_SHIFT) /* 0x00000001 */ +#define GMAC_DMA_SYSBUS_MODE_BLEN4_SHIFT (1U) +#define GMAC_DMA_SYSBUS_MODE_BLEN4_MASK (0x1U << GMAC_DMA_SYSBUS_MODE_BLEN4_SHIFT) /* 0x00000002 */ +#define GMAC_DMA_SYSBUS_MODE_BLEN8_SHIFT (2U) +#define GMAC_DMA_SYSBUS_MODE_BLEN8_MASK (0x1U << GMAC_DMA_SYSBUS_MODE_BLEN8_SHIFT) /* 0x00000004 */ +#define GMAC_DMA_SYSBUS_MODE_BLEN16_SHIFT (3U) +#define GMAC_DMA_SYSBUS_MODE_BLEN16_MASK (0x1U << GMAC_DMA_SYSBUS_MODE_BLEN16_SHIFT) /* 0x00000008 */ +#define GMAC_DMA_SYSBUS_MODE_AALE_SHIFT (10U) +#define GMAC_DMA_SYSBUS_MODE_AALE_MASK (0x1U << GMAC_DMA_SYSBUS_MODE_AALE_SHIFT) /* 0x00000400 */ +#define GMAC_DMA_SYSBUS_MODE_AAL_SHIFT (12U) +#define GMAC_DMA_SYSBUS_MODE_AAL_MASK (0x1U << GMAC_DMA_SYSBUS_MODE_AAL_SHIFT) /* 0x00001000 */ +#define GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT (16U) +#define GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK (0x7U << GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) /* 0x00070000 */ +#define GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT (24U) +#define GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK (0x3U << GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT) /* 0x03000000 */ +#define GMAC_DMA_SYSBUS_MODE_LPI_XIT_PKT_SHIFT (30U) +#define GMAC_DMA_SYSBUS_MODE_LPI_XIT_PKT_MASK (0x1U << GMAC_DMA_SYSBUS_MODE_LPI_XIT_PKT_SHIFT) /* 0x40000000 */ +#define GMAC_DMA_SYSBUS_MODE_EN_LPI_SHIFT (31U) +#define GMAC_DMA_SYSBUS_MODE_EN_LPI_MASK (0x1U << GMAC_DMA_SYSBUS_MODE_EN_LPI_SHIFT) /* 0x80000000 */ +/* DMA_INTERRUPT_STATUS */ +#define GMAC_DMA_INTERRUPT_STATUS_OFFSET (0x1008U) +#define GMAC_DMA_INTERRUPT_STATUS (0x0U) +#define GMAC_DMA_INTERRUPT_STATUS_DC0IS_SHIFT (0U) +#define GMAC_DMA_INTERRUPT_STATUS_DC0IS_MASK (0x1U << GMAC_DMA_INTERRUPT_STATUS_DC0IS_SHIFT) /* 0x00000001 */ +#define GMAC_DMA_INTERRUPT_STATUS_MTLIS_SHIFT (16U) +#define GMAC_DMA_INTERRUPT_STATUS_MTLIS_MASK (0x1U << GMAC_DMA_INTERRUPT_STATUS_MTLIS_SHIFT) /* 0x00010000 */ +#define GMAC_DMA_INTERRUPT_STATUS_MACIS_SHIFT (17U) +#define GMAC_DMA_INTERRUPT_STATUS_MACIS_MASK (0x1U << GMAC_DMA_INTERRUPT_STATUS_MACIS_SHIFT) /* 0x00020000 */ +/* DMA_DEBUG_STATUS0 */ +#define GMAC_DMA_DEBUG_STATUS0_OFFSET (0x100CU) +#define GMAC_DMA_DEBUG_STATUS0 (0x0U) +#define GMAC_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT (0U) +#define GMAC_DMA_DEBUG_STATUS0_AXWHSTS_MASK (0x1U << GMAC_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT) /* 0x00000001 */ +#define GMAC_DMA_DEBUG_STATUS0_AXRHSTS_SHIFT (1U) +#define GMAC_DMA_DEBUG_STATUS0_AXRHSTS_MASK (0x1U << GMAC_DMA_DEBUG_STATUS0_AXRHSTS_SHIFT) /* 0x00000002 */ +#define GMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT (8U) +#define GMAC_DMA_DEBUG_STATUS0_RPS0_MASK (0xFU << GMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT) /* 0x00000F00 */ +#define GMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT (12U) +#define GMAC_DMA_DEBUG_STATUS0_TPS0_MASK (0xFU << GMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT) /* 0x0000F000 */ +/* AXI_LPI_ENTRY_INTERVAL */ +#define GMAC_AXI_LPI_ENTRY_INTERVAL_OFFSET (0x1040U) +#define GMAC_AXI_LPI_ENTRY_INTERVAL_LPIEI_SHIFT (0U) +#define GMAC_AXI_LPI_ENTRY_INTERVAL_LPIEI_MASK (0xFU << GMAC_AXI_LPI_ENTRY_INTERVAL_LPIEI_SHIFT) /* 0x0000000F */ +/* DMA_CH0_CONTROL */ +#define GMAC_DMA_CH0_CONTROL_OFFSET (0x1100U) +#define GMAC_DMA_CH0_CONTROL_MSS_SHIFT (0U) +#define GMAC_DMA_CH0_CONTROL_MSS_MASK (0x3FFFU << GMAC_DMA_CH0_CONTROL_MSS_SHIFT) /* 0x00003FFF */ +#define GMAC_DMA_CH0_CONTROL_PBLX8_SHIFT (16U) +#define GMAC_DMA_CH0_CONTROL_PBLX8_MASK (0x1U << GMAC_DMA_CH0_CONTROL_PBLX8_SHIFT) /* 0x00010000 */ +#define GMAC_DMA_CH0_CONTROL_DSL_SHIFT (18U) +#define GMAC_DMA_CH0_CONTROL_DSL_MASK (0x7U << GMAC_DMA_CH0_CONTROL_DSL_SHIFT) /* 0x001C0000 */ +/* DMA_CH0_TX_CONTROL */ +#define GMAC_DMA_CH0_TX_CONTROL_OFFSET (0x1104U) +#define GMAC_DMA_CH0_TX_CONTROL_ST_SHIFT (0U) +#define GMAC_DMA_CH0_TX_CONTROL_ST_MASK (0x1U << GMAC_DMA_CH0_TX_CONTROL_ST_SHIFT) /* 0x00000001 */ +#define GMAC_DMA_CH0_TX_CONTROL_OSF_SHIFT (4U) +#define GMAC_DMA_CH0_TX_CONTROL_OSF_MASK (0x1U << GMAC_DMA_CH0_TX_CONTROL_OSF_SHIFT) /* 0x00000010 */ +#define GMAC_DMA_CH0_TX_CONTROL_TSE_SHIFT (12U) +#define GMAC_DMA_CH0_TX_CONTROL_TSE_MASK (0x1U << GMAC_DMA_CH0_TX_CONTROL_TSE_SHIFT) /* 0x00001000 */ +#define GMAC_DMA_CH0_TX_CONTROL_TSE_MODE_SHIFT (13U) +#define GMAC_DMA_CH0_TX_CONTROL_TSE_MODE_MASK (0x3U << GMAC_DMA_CH0_TX_CONTROL_TSE_MODE_SHIFT) /* 0x00006000 */ +#define GMAC_DMA_CH0_TX_CONTROL_IPBL_SHIFT (15U) +#define GMAC_DMA_CH0_TX_CONTROL_IPBL_MASK (0x1U << GMAC_DMA_CH0_TX_CONTROL_IPBL_SHIFT) /* 0x00008000 */ +#define GMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT (16U) +#define GMAC_DMA_CH0_TX_CONTROL_TXPBL_MASK (0x3FU << GMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT) /* 0x003F0000 */ +/* DMA_CH0_RX_CONTROL */ +#define GMAC_DMA_CH0_RX_CONTROL_OFFSET (0x1108U) +#define GMAC_DMA_CH0_RX_CONTROL_SR_SHIFT (0U) +#define GMAC_DMA_CH0_RX_CONTROL_SR_MASK (0x1U << GMAC_DMA_CH0_RX_CONTROL_SR_SHIFT) /* 0x00000001 */ +#define GMAC_DMA_CH0_RX_CONTROL_RBSZ_3_0_SHIFT (1U) +#define GMAC_DMA_CH0_RX_CONTROL_RBSZ_3_0_MASK (0x7U << GMAC_DMA_CH0_RX_CONTROL_RBSZ_3_0_SHIFT) /* 0x0000000E */ +#define GMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_SHIFT (4U) +#define GMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_MASK (0x7FFU << GMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_SHIFT) /* 0x00007FF0 */ +#define GMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT (16U) +#define GMAC_DMA_CH0_RX_CONTROL_RXPBL_MASK (0x3FU << GMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT) /* 0x003F0000 */ +#define GMAC_DMA_CH0_RX_CONTROL_RPF_SHIFT (31U) +#define GMAC_DMA_CH0_RX_CONTROL_RPF_MASK (0x1U << GMAC_DMA_CH0_RX_CONTROL_RPF_SHIFT) /* 0x80000000 */ +/* DMA_CH0_TXDESC_LIST_ADDRESS */ +#define GMAC_DMA_CH0_TXDESC_LIST_ADDRESS_OFFSET (0x1114U) +#define GMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT (3U) +#define GMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_MASK (0x1FFFFFFFU << GMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT) /* 0xFFFFFFF8 */ +/* DMA_CH0_RXDESC_LIST_ADDRESS */ +#define GMAC_DMA_CH0_RXDESC_LIST_ADDRESS_OFFSET (0x111CU) +#define GMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT (3U) +#define GMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_MASK (0x1FFFFFFFU << GMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT) /* 0xFFFFFFF8 */ +/* DMA_CH0_TXDESC_TAIL_POINTER */ +#define GMAC_DMA_CH0_TXDESC_TAIL_POINTER_OFFSET (0x1120U) +#define GMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT (3U) +#define GMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_MASK (0x1FFFFFFFU << GMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT) /* 0xFFFFFFF8 */ +/* DMA_CH0_RXDESC_TAIL_POINTER */ +#define GMAC_DMA_CH0_RXDESC_TAIL_POINTER_OFFSET (0x1128U) +#define GMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDRT_SHIFT (3U) +#define GMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDRT_MASK (0x1FFFFFFFU << GMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDRT_SHIFT) /* 0xFFFFFFF8 */ +/* DMA_CH0_TXDESC_RING_LENGTH */ +#define GMAC_DMA_CH0_TXDESC_RING_LENGTH_OFFSET (0x112CU) +#define GMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT (0U) +#define GMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU << GMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT) /* 0x000003FF */ +/* DMA_CH0_RXDESC_RING_LENGTH */ +#define GMAC_DMA_CH0_RXDESC_RING_LENGTH_OFFSET (0x1130U) +#define GMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT (0U) +#define GMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU << GMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT) /* 0x000003FF */ +/* DMA_CH0_INTERRUPT_ENABLE */ +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_OFFSET (0x1134U) +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_SHIFT (0U) +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_SHIFT) /* 0x00000001 */ +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_SHIFT (1U) +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_SHIFT) /* 0x00000002 */ +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_SHIFT (2U) +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_SHIFT) /* 0x00000004 */ +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_SHIFT (6U) +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_SHIFT) /* 0x00000040 */ +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_SHIFT (7U) +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_SHIFT) /* 0x00000080 */ +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_SHIFT (8U) +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_SHIFT) /* 0x00000100 */ +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_SHIFT (9U) +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_SHIFT) /* 0x00000200 */ +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_SHIFT (10U) +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_SHIFT) /* 0x00000400 */ +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_SHIFT (11U) +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_SHIFT) /* 0x00000800 */ +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_SHIFT (12U) +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_SHIFT) /* 0x00001000 */ +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_SHIFT (13U) +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_SHIFT) /* 0x00002000 */ +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_SHIFT (14U) +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_SHIFT) /* 0x00004000 */ +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_SHIFT (15U) +#define GMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_MASK (0x1U << GMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_SHIFT) /* 0x00008000 */ +/* DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER */ +#define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_OFFSET (0x1138U) +#define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT (0U) +#define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK (0xFFU << GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT) /* 0x000000FF */ +#define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT (16U) +#define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK (0x3U << GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT) /* 0x00030000 */ +/* DMA_CH0_CURRENT_APP_TXDESC */ +#define GMAC_DMA_CH0_CURRENT_APP_TXDESC_OFFSET (0x1144U) +#define GMAC_DMA_CH0_CURRENT_APP_TXDESC (0x0U) +#define GMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT (0U) +#define GMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFFU << GMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT) /* 0xFFFFFFFF */ +/* DMA_CH0_CURRENT_APP_RXDESC */ +#define GMAC_DMA_CH0_CURRENT_APP_RXDESC_OFFSET (0x114CU) +#define GMAC_DMA_CH0_CURRENT_APP_RXDESC (0x0U) +#define GMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT (0U) +#define GMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFFU << GMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT) /* 0xFFFFFFFF */ +/* DMA_CH0_CURRENT_APP_TXBUFFER */ +#define GMAC_DMA_CH0_CURRENT_APP_TXBUFFER_OFFSET (0x1154U) +#define GMAC_DMA_CH0_CURRENT_APP_TXBUFFER (0x0U) +#define GMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT (0U) +#define GMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK (0xFFFFFFFFU << GMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT) /* 0xFFFFFFFF */ +/* DMA_CH0_CURRENT_APP_RXBUFFER */ +#define GMAC_DMA_CH0_CURRENT_APP_RXBUFFER_OFFSET (0x115CU) +#define GMAC_DMA_CH0_CURRENT_APP_RXBUFFER (0x0U) +#define GMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT (0U) +#define GMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK (0xFFFFFFFFU << GMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT) /* 0xFFFFFFFF */ +/* DMA_CH0_STATUS */ +#define GMAC_DMA_CH0_STATUS_OFFSET (0x1160U) +#define GMAC_DMA_CH0_STATUS_TI_SHIFT (0U) +#define GMAC_DMA_CH0_STATUS_TI_MASK (0x1U << GMAC_DMA_CH0_STATUS_TI_SHIFT) /* 0x00000001 */ +#define GMAC_DMA_CH0_STATUS_TPS_SHIFT (1U) +#define GMAC_DMA_CH0_STATUS_TPS_MASK (0x1U << GMAC_DMA_CH0_STATUS_TPS_SHIFT) /* 0x00000002 */ +#define GMAC_DMA_CH0_STATUS_TBU_SHIFT (2U) +#define GMAC_DMA_CH0_STATUS_TBU_MASK (0x1U << GMAC_DMA_CH0_STATUS_TBU_SHIFT) /* 0x00000004 */ +#define GMAC_DMA_CH0_STATUS_RI_SHIFT (6U) +#define GMAC_DMA_CH0_STATUS_RI_MASK (0x1U << GMAC_DMA_CH0_STATUS_RI_SHIFT) /* 0x00000040 */ +#define GMAC_DMA_CH0_STATUS_RBU_SHIFT (7U) +#define GMAC_DMA_CH0_STATUS_RBU_MASK (0x1U << GMAC_DMA_CH0_STATUS_RBU_SHIFT) /* 0x00000080 */ +#define GMAC_DMA_CH0_STATUS_RPS_SHIFT (8U) +#define GMAC_DMA_CH0_STATUS_RPS_MASK (0x1U << GMAC_DMA_CH0_STATUS_RPS_SHIFT) /* 0x00000100 */ +#define GMAC_DMA_CH0_STATUS_RWT_SHIFT (9U) +#define GMAC_DMA_CH0_STATUS_RWT_MASK (0x1U << GMAC_DMA_CH0_STATUS_RWT_SHIFT) /* 0x00000200 */ +#define GMAC_DMA_CH0_STATUS_ETI_SHIFT (10U) +#define GMAC_DMA_CH0_STATUS_ETI_MASK (0x1U << GMAC_DMA_CH0_STATUS_ETI_SHIFT) /* 0x00000400 */ +#define GMAC_DMA_CH0_STATUS_ERI_SHIFT (11U) +#define GMAC_DMA_CH0_STATUS_ERI_MASK (0x1U << GMAC_DMA_CH0_STATUS_ERI_SHIFT) /* 0x00000800 */ +#define GMAC_DMA_CH0_STATUS_FBE_SHIFT (12U) +#define GMAC_DMA_CH0_STATUS_FBE_MASK (0x1U << GMAC_DMA_CH0_STATUS_FBE_SHIFT) /* 0x00001000 */ +#define GMAC_DMA_CH0_STATUS_CDE_SHIFT (13U) +#define GMAC_DMA_CH0_STATUS_CDE_MASK (0x1U << GMAC_DMA_CH0_STATUS_CDE_SHIFT) /* 0x00002000 */ +#define GMAC_DMA_CH0_STATUS_AIS_SHIFT (14U) +#define GMAC_DMA_CH0_STATUS_AIS_MASK (0x1U << GMAC_DMA_CH0_STATUS_AIS_SHIFT) /* 0x00004000 */ +#define GMAC_DMA_CH0_STATUS_NIS_SHIFT (15U) +#define GMAC_DMA_CH0_STATUS_NIS_MASK (0x1U << GMAC_DMA_CH0_STATUS_NIS_SHIFT) /* 0x00008000 */ +#define GMAC_DMA_CH0_STATUS_TEB_SHIFT (16U) +#define GMAC_DMA_CH0_STATUS_TEB_MASK (0x7U << GMAC_DMA_CH0_STATUS_TEB_SHIFT) /* 0x00070000 */ +#define GMAC_DMA_CH0_STATUS_REB_SHIFT (19U) +#define GMAC_DMA_CH0_STATUS_REB_MASK (0x7U << GMAC_DMA_CH0_STATUS_REB_SHIFT) /* 0x00380000 */ +/* DMA_CH0_MISS_FRAME_CNT */ +#define GMAC_DMA_CH0_MISS_FRAME_CNT_OFFSET (0x1164U) +#define GMAC_DMA_CH0_MISS_FRAME_CNT (0x0U) +#define GMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT (0U) +#define GMAC_DMA_CH0_MISS_FRAME_CNT_MFC_MASK (0x7FFU << GMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT) /* 0x000007FF */ +#define GMAC_DMA_CH0_MISS_FRAME_CNT_MFC0_SHIFT (15U) +#define GMAC_DMA_CH0_MISS_FRAME_CNT_MFC0_MASK (0x1U << GMAC_DMA_CH0_MISS_FRAME_CNT_MFC0_SHIFT) /* 0x00008000 */ +/* DMA_CH0_RX_ERI_CNT */ +#define GMAC_DMA_CH0_RX_ERI_CNT_OFFSET (0x1168U) +#define GMAC_DMA_CH0_RX_ERI_CNT (0x0U) +#define GMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT (0U) +#define GMAC_DMA_CH0_RX_ERI_CNT_ECNT_MASK (0x1U << GMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT) /* 0x00000001 */ +/******************************************MMC*******************************************/ +/* CTRL */ +#define MMC_CTRL_OFFSET (0x0U) +#define MMC_CTRL_CONTROLLER_RESET_SHIFT (0U) +#define MMC_CTRL_CONTROLLER_RESET_MASK (0x1U << MMC_CTRL_CONTROLLER_RESET_SHIFT) /* 0x00000001 */ +#define MMC_CTRL_FIFO_RESET_SHIFT (1U) +#define MMC_CTRL_FIFO_RESET_MASK (0x1U << MMC_CTRL_FIFO_RESET_SHIFT) /* 0x00000002 */ +#define MMC_CTRL_DMA_RESET_SHIFT (2U) +#define MMC_CTRL_DMA_RESET_MASK (0x1U << MMC_CTRL_DMA_RESET_SHIFT) /* 0x00000004 */ +#define MMC_CTRL_INT_ENABLE_SHIFT (4U) +#define MMC_CTRL_INT_ENABLE_MASK (0x1U << MMC_CTRL_INT_ENABLE_SHIFT) /* 0x00000010 */ +#define MMC_CTRL_DMA_ENABLE_SHIFT (5U) +#define MMC_CTRL_DMA_ENABLE_MASK (0x1U << MMC_CTRL_DMA_ENABLE_SHIFT) /* 0x00000020 */ +#define MMC_CTRL_READ_WAIT_SHIFT (6U) +#define MMC_CTRL_READ_WAIT_MASK (0x1U << MMC_CTRL_READ_WAIT_SHIFT) /* 0x00000040 */ +#define MMC_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U) +#define MMC_CTRL_SEND_IRQ_RESPONSE_MASK (0x1U << MMC_CTRL_SEND_IRQ_RESPONSE_SHIFT) /* 0x00000080 */ +#define MMC_CTRL_ABORT_READ_DATA_SHIFT (8U) +#define MMC_CTRL_ABORT_READ_DATA_MASK (0x1U << MMC_CTRL_ABORT_READ_DATA_SHIFT) /* 0x00000100 */ +#define MMC_CTRL_SEND_CCSD_SHIFT (9U) +#define MMC_CTRL_SEND_CCSD_MASK (0x1U << MMC_CTRL_SEND_CCSD_SHIFT) /* 0x00000200 */ +#define MMC_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U) +#define MMC_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x1U << MMC_CTRL_SEND_AUTO_STOP_CCSD_SHIFT) /* 0x00000400 */ +#define MMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U) +#define MMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x1U << MMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT) /* 0x00000800 */ +#define MMC_CTRL_USE_INTERNAL_DMAC_SHIFT (25U) +#define MMC_CTRL_USE_INTERNAL_DMAC_MASK (0x1U << MMC_CTRL_USE_INTERNAL_DMAC_SHIFT) /* 0x02000000 */ +/* PWREN */ +#define MMC_PWREN_OFFSET (0x4U) +#define MMC_PWREN_POWER_ENABLE_SHIFT (0U) +#define MMC_PWREN_POWER_ENABLE_MASK (0x1U << MMC_PWREN_POWER_ENABLE_SHIFT) /* 0x00000001 */ +/* CLKDIV */ +#define MMC_CLKDIV_OFFSET (0x8U) +#define MMC_CLKDIV_CLK_DIVIDER0_SHIFT (0U) +#define MMC_CLKDIV_CLK_DIVIDER0_MASK (0xFFU << MMC_CLKDIV_CLK_DIVIDER0_SHIFT) /* 0x000000FF */ +/* CLKSRC */ +#define MMC_CLKSRC_OFFSET (0xCU) +#define MMC_CLKSRC_CLK_SOURCE_SHIFT (0U) +#define MMC_CLKSRC_CLK_SOURCE_MASK (0x3U << MMC_CLKSRC_CLK_SOURCE_SHIFT) /* 0x00000003 */ +/* CLKENA */ +#define MMC_CLKENA_OFFSET (0x10U) +#define MMC_CLKENA_CCLK_ENABLE_SHIFT (0U) +#define MMC_CLKENA_CCLK_ENABLE_MASK (0x1U << MMC_CLKENA_CCLK_ENABLE_SHIFT) /* 0x00000001 */ +#define MMC_CLKENA_CCLK_LOW_POWER_SHIFT (16U) +#define MMC_CLKENA_CCLK_LOW_POWER_MASK (0x1U << MMC_CLKENA_CCLK_LOW_POWER_SHIFT) /* 0x00010000 */ +/* TMOUT */ +#define MMC_TMOUT_OFFSET (0x14U) +#define MMC_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U) +#define MMC_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU << MMC_TMOUT_RESPONSE_TIMEOUT_SHIFT) /* 0x000000FF */ +#define MMC_TMOUT_DATA_TIMEOUT_SHIFT (8U) +#define MMC_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFFU << MMC_TMOUT_DATA_TIMEOUT_SHIFT) /* 0xFFFFFF00 */ +/* CTYPE */ +#define MMC_CTYPE_OFFSET (0x18U) +#define MMC_CTYPE_CARD_WIDTH_SHIFT (0U) +#define MMC_CTYPE_CARD_WIDTH_MASK (0x1U << MMC_CTYPE_CARD_WIDTH_SHIFT) /* 0x00000001 */ +#define MMC_CTYPE_CARD_WIDTH_8_SHIFT (16U) +#define MMC_CTYPE_CARD_WIDTH_8_MASK (0x1U << MMC_CTYPE_CARD_WIDTH_8_SHIFT) /* 0x00010000 */ +/* BLKSIZ */ +#define MMC_BLKSIZ_OFFSET (0x1CU) +#define MMC_BLKSIZ_BLOCK_SIZE_SHIFT (0U) +#define MMC_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU << MMC_BLKSIZ_BLOCK_SIZE_SHIFT) /* 0x0000FFFF */ +/* BYTCNT */ +#define MMC_BYTCNT_OFFSET (0x20U) +#define MMC_BYTCNT_BYTE_COUNT_SHIFT (0U) +#define MMC_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU << MMC_BYTCNT_BYTE_COUNT_SHIFT) /* 0xFFFFFFFF */ +/* INTMASK */ +#define MMC_INTMASK_OFFSET (0x24U) +#define MMC_INTMASK_INT_MASK_SHIFT (0U) +#define MMC_INTMASK_INT_MASK_MASK (0xFFFFU << MMC_INTMASK_INT_MASK_SHIFT) /* 0x0000FFFF */ +#define MMC_INTMASK_DATA_NOBUSY_INT_MASK_SHIFT (16U) +#define MMC_INTMASK_DATA_NOBUSY_INT_MASK_MASK (0x1U << MMC_INTMASK_DATA_NOBUSY_INT_MASK_SHIFT) /* 0x00010000 */ +#define MMC_INTMASK_SDIO_INT_MASK_SHIFT (24U) +#define MMC_INTMASK_SDIO_INT_MASK_MASK (0x1U << MMC_INTMASK_SDIO_INT_MASK_SHIFT) /* 0x01000000 */ +/* CMDARG */ +#define MMC_CMDARG_OFFSET (0x28U) +#define MMC_CMDARG_CMD_ARG_SHIFT (0U) +#define MMC_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU << MMC_CMDARG_CMD_ARG_SHIFT) /* 0xFFFFFFFF */ +/* CMD */ +#define MMC_CMD_OFFSET (0x2CU) +#define MMC_CMD_CMD_INDEX_SHIFT (0U) +#define MMC_CMD_CMD_INDEX_MASK (0x3FU << MMC_CMD_CMD_INDEX_SHIFT) /* 0x0000003F */ +#define MMC_CMD_RESPONSE_EXPECT_SHIFT (6U) +#define MMC_CMD_RESPONSE_EXPECT_MASK (0x1U << MMC_CMD_RESPONSE_EXPECT_SHIFT) /* 0x00000040 */ +#define MMC_CMD_RESPONSE_LENGTH_SHIFT (7U) +#define MMC_CMD_RESPONSE_LENGTH_MASK (0x1U << MMC_CMD_RESPONSE_LENGTH_SHIFT) /* 0x00000080 */ +#define MMC_CMD_CHECK_RESPONSE_CRC_SHIFT (8U) +#define MMC_CMD_CHECK_RESPONSE_CRC_MASK (0x1U << MMC_CMD_CHECK_RESPONSE_CRC_SHIFT) /* 0x00000100 */ +#define MMC_CMD_DATA_EXPECTED_SHIFT (9U) +#define MMC_CMD_DATA_EXPECTED_MASK (0x1U << MMC_CMD_DATA_EXPECTED_SHIFT) /* 0x00000200 */ +#define MMC_CMD_WR_SHIFT (10U) +#define MMC_CMD_WR_MASK (0x1U << MMC_CMD_WR_SHIFT) /* 0x00000400 */ +#define MMC_CMD_TRANSFER_MODE_SHIFT (11U) +#define MMC_CMD_TRANSFER_MODE_MASK (0x1U << MMC_CMD_TRANSFER_MODE_SHIFT) /* 0x00000800 */ +#define MMC_CMD_SEND_AUTO_STOP_SHIFT (12U) +#define MMC_CMD_SEND_AUTO_STOP_MASK (0x1U << MMC_CMD_SEND_AUTO_STOP_SHIFT) /* 0x00001000 */ +#define MMC_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U) +#define MMC_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x1U << MMC_CMD_WAIT_PRVDATA_COMPLETE_SHIFT) /* 0x00002000 */ +#define MMC_CMD_STOP_ABORT_CMD_SHIFT (14U) +#define MMC_CMD_STOP_ABORT_CMD_MASK (0x1U << MMC_CMD_STOP_ABORT_CMD_SHIFT) /* 0x00004000 */ +#define MMC_CMD_SEND_INITIALIZATION_SHIFT (15U) +#define MMC_CMD_SEND_INITIALIZATION_MASK (0x1U << MMC_CMD_SEND_INITIALIZATION_SHIFT) /* 0x00008000 */ +#define MMC_CMD_UPDATE_CLOCK_REGS_ONLY_SHIFT (21U) +#define MMC_CMD_UPDATE_CLOCK_REGS_ONLY_MASK (0x1U << MMC_CMD_UPDATE_CLOCK_REGS_ONLY_SHIFT) /* 0x00200000 */ +#define MMC_CMD_READ_CEATA_DEVICE_SHIFT (22U) +#define MMC_CMD_READ_CEATA_DEVICE_MASK (0x1U << MMC_CMD_READ_CEATA_DEVICE_SHIFT) /* 0x00400000 */ +#define MMC_CMD_CCS_EXPECTED_SHIFT (23U) +#define MMC_CMD_CCS_EXPECTED_MASK (0x1U << MMC_CMD_CCS_EXPECTED_SHIFT) /* 0x00800000 */ +#define MMC_CMD_ENABLE_BOOT_SHIFT (24U) +#define MMC_CMD_ENABLE_BOOT_MASK (0x1U << MMC_CMD_ENABLE_BOOT_SHIFT) /* 0x01000000 */ +#define MMC_CMD_EXPECT_BOOT_ACK_SHIFT (25U) +#define MMC_CMD_EXPECT_BOOT_ACK_MASK (0x1U << MMC_CMD_EXPECT_BOOT_ACK_SHIFT) /* 0x02000000 */ +#define MMC_CMD_DISABLE_BOOT_SHIFT (26U) +#define MMC_CMD_DISABLE_BOOT_MASK (0x1U << MMC_CMD_DISABLE_BOOT_SHIFT) /* 0x04000000 */ +#define MMC_CMD_BOOT_MODE_SHIFT (27U) +#define MMC_CMD_BOOT_MODE_MASK (0x1U << MMC_CMD_BOOT_MODE_SHIFT) /* 0x08000000 */ +#define MMC_CMD_VOLT_SWITCH_SHIFT (28U) +#define MMC_CMD_VOLT_SWITCH_MASK (0x1U << MMC_CMD_VOLT_SWITCH_SHIFT) /* 0x10000000 */ +#define MMC_CMD_USE_HOLD_REG_SHIFT (29U) +#define MMC_CMD_USE_HOLD_REG_MASK (0x1U << MMC_CMD_USE_HOLD_REG_SHIFT) /* 0x20000000 */ +#define MMC_CMD_START_CMD_SHIFT (31U) +#define MMC_CMD_START_CMD_MASK (0x1U << MMC_CMD_START_CMD_SHIFT) /* 0x80000000 */ +/* RESP0 */ +#define MMC_RESP0_OFFSET (0x30U) +#define MMC_RESP0 (0x0U) +#define MMC_RESP0_RESPONSE0_SHIFT (0U) +#define MMC_RESP0_RESPONSE0_MASK (0xFFFFFFFFU << MMC_RESP0_RESPONSE0_SHIFT) /* 0xFFFFFFFF */ +/* RESP1 */ +#define MMC_RESP1_OFFSET (0x34U) +#define MMC_RESP1 (0x0U) +#define MMC_RESP1_RESPONSE1_SHIFT (0U) +#define MMC_RESP1_RESPONSE1_MASK (0xFFFFFFFFU << MMC_RESP1_RESPONSE1_SHIFT) /* 0xFFFFFFFF */ +/* RESP2 */ +#define MMC_RESP2_OFFSET (0x38U) +#define MMC_RESP2 (0x0U) +#define MMC_RESP2_RESPONSE2_SHIFT (0U) +#define MMC_RESP2_RESPONSE2_MASK (0xFFFFFFFFU << MMC_RESP2_RESPONSE2_SHIFT) /* 0xFFFFFFFF */ +/* RESP3 */ +#define MMC_RESP3_OFFSET (0x3CU) +#define MMC_RESP3 (0x0U) +#define MMC_RESP3_RESPONSE3_SHIFT (0U) +#define MMC_RESP3_RESPONSE3_MASK (0xFFFFFFFFU << MMC_RESP3_RESPONSE3_SHIFT) /* 0xFFFFFFFF */ +/* MINTSTS */ +#define MMC_MINTSTS_OFFSET (0x40U) +#define MMC_MINTSTS_INT_STATUS_SHIFT (0U) +#define MMC_MINTSTS_INT_STATUS_MASK (0xFFFFU << MMC_MINTSTS_INT_STATUS_SHIFT) /* 0x0000FFFF */ +#define MMC_MINTSTS_DATA_NOBUSY_INT_STATUS_SHIFT (16U) +#define MMC_MINTSTS_DATA_NOBUSY_INT_STATUS_MASK (0x1U << MMC_MINTSTS_DATA_NOBUSY_INT_STATUS_SHIFT) /* 0x00010000 */ +#define MMC_MINTSTS_SDIO_INTERRUPT_SHIFT (24U) +#define MMC_MINTSTS_SDIO_INTERRUPT_MASK (0x1U << MMC_MINTSTS_SDIO_INTERRUPT_SHIFT) /* 0x01000000 */ +/* RINTSTS */ +#define MMC_RINTSTS_OFFSET (0x44U) +#define MMC_RINTSTS_INT_STATUS_SHIFT (0U) +#define MMC_RINTSTS_INT_STATUS_MASK (0xFFFFU << MMC_RINTSTS_INT_STATUS_SHIFT) /* 0x0000FFFF */ +#define MMC_RINTSTS_DATA_NOBUSY_INT_STATUS_SHIFT (16U) +#define MMC_RINTSTS_DATA_NOBUSY_INT_STATUS_MASK (0x1U << MMC_RINTSTS_DATA_NOBUSY_INT_STATUS_SHIFT) /* 0x00010000 */ +#define MMC_RINTSTS_SDIO_INTERRUPT_SHIFT (24U) +#define MMC_RINTSTS_SDIO_INTERRUPT_MASK (0x1U << MMC_RINTSTS_SDIO_INTERRUPT_SHIFT) /* 0x01000000 */ +/* STATUS */ +#define MMC_STATUS_OFFSET (0x48U) +#define MMC_STATUS (0x106U) +#define MMC_STATUS_FIFO_RX_WATERMARK_SHIFT (0U) +#define MMC_STATUS_FIFO_RX_WATERMARK_MASK (0x1U << MMC_STATUS_FIFO_RX_WATERMARK_SHIFT) /* 0x00000001 */ +#define MMC_STATUS_FIFO_TX_WATERMARK_SHIFT (1U) +#define MMC_STATUS_FIFO_TX_WATERMARK_MASK (0x1U << MMC_STATUS_FIFO_TX_WATERMARK_SHIFT) /* 0x00000002 */ +#define MMC_STATUS_FIFO_EMPTY_SHIFT (2U) +#define MMC_STATUS_FIFO_EMPTY_MASK (0x1U << MMC_STATUS_FIFO_EMPTY_SHIFT) /* 0x00000004 */ +#define MMC_STATUS_FIFO_FULL_SHIFT (3U) +#define MMC_STATUS_FIFO_FULL_MASK (0x1U << MMC_STATUS_FIFO_FULL_SHIFT) /* 0x00000008 */ +#define MMC_STATUS_COMMAND_FSM_STATES_SHIFT (4U) +#define MMC_STATUS_COMMAND_FSM_STATES_MASK (0xFU << MMC_STATUS_COMMAND_FSM_STATES_SHIFT) /* 0x000000F0 */ +#define MMC_STATUS_DATA_3_STATUS_SHIFT (8U) +#define MMC_STATUS_DATA_3_STATUS_MASK (0x1U << MMC_STATUS_DATA_3_STATUS_SHIFT) /* 0x00000100 */ +#define MMC_STATUS_DATA_BUSY_SHIFT (9U) +#define MMC_STATUS_DATA_BUSY_MASK (0x1U << MMC_STATUS_DATA_BUSY_SHIFT) /* 0x00000200 */ +#define MMC_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U) +#define MMC_STATUS_DATA_STATE_MC_BUSY_MASK (0x1U << MMC_STATUS_DATA_STATE_MC_BUSY_SHIFT) /* 0x00000400 */ +#define MMC_STATUS_RESPONSE_INDEX_SHIFT (11U) +#define MMC_STATUS_RESPONSE_INDEX_MASK (0x3FU << MMC_STATUS_RESPONSE_INDEX_SHIFT) /* 0x0001F800 */ +#define MMC_STATUS_FIFO_COUNT_SHIFT (17U) +#define MMC_STATUS_FIFO_COUNT_MASK (0x1FFFU << MMC_STATUS_FIFO_COUNT_SHIFT) /* 0x3FFE0000 */ +#define MMC_STATUS_DMA_ACK_SHIFT (30U) +#define MMC_STATUS_DMA_ACK_MASK (0x1U << MMC_STATUS_DMA_ACK_SHIFT) /* 0x40000000 */ +#define MMC_STATUS_DMA_REQ_SHIFT (31U) +#define MMC_STATUS_DMA_REQ_MASK (0x1U << MMC_STATUS_DMA_REQ_SHIFT) /* 0x80000000 */ +/* FIFOTH */ +#define MMC_FIFOTH_OFFSET (0x4CU) +#define MMC_FIFOTH_TX_WMARK_SHIFT (0U) +#define MMC_FIFOTH_TX_WMARK_MASK (0xFFFU << MMC_FIFOTH_TX_WMARK_SHIFT) /* 0x00000FFF */ +#define MMC_FIFOTH_RX_WMARK_SHIFT (16U) +#define MMC_FIFOTH_RX_WMARK_MASK (0xFFFU << MMC_FIFOTH_RX_WMARK_SHIFT) /* 0x0FFF0000 */ +#define MMC_FIFOTH_DMA_MUTIPLE_TRANSACTION_SIZE_SHIFT (28U) +#define MMC_FIFOTH_DMA_MUTIPLE_TRANSACTION_SIZE_MASK (0x7U << MMC_FIFOTH_DMA_MUTIPLE_TRANSACTION_SIZE_SHIFT) /* 0x70000000 */ +/* CDETECT */ +#define MMC_CDETECT_OFFSET (0x50U) +#define MMC_CDETECT (0x1U) +#define MMC_CDETECT_CARD_DETECT_N_SHIFT (0U) +#define MMC_CDETECT_CARD_DETECT_N_MASK (0x1U << MMC_CDETECT_CARD_DETECT_N_SHIFT) /* 0x00000001 */ +/* WRTPRT */ +#define MMC_WRTPRT_OFFSET (0x54U) +#define MMC_WRTPRT_WRITE_PROTECT_SHIFT (0U) +#define MMC_WRTPRT_WRITE_PROTECT_MASK (0x1U << MMC_WRTPRT_WRITE_PROTECT_SHIFT) /* 0x00000001 */ +/* TCBCNT */ +#define MMC_TCBCNT_OFFSET (0x5CU) +#define MMC_TCBCNT (0x0U) +#define MMC_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U) +#define MMC_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU << MMC_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT) /* 0xFFFFFFFF */ +/* TBBCNT */ +#define MMC_TBBCNT_OFFSET (0x60U) +#define MMC_TBBCNT (0x0U) +#define MMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U) +#define MMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU << MMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT) /* 0xFFFFFFFF */ +/* DEBNCE */ +#define MMC_DEBNCE_OFFSET (0x64U) +#define MMC_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U) +#define MMC_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU << MMC_DEBNCE_DEBOUNCE_COUNT_SHIFT) /* 0x00FFFFFF */ +/* USRID */ +#define MMC_USRID_OFFSET (0x68U) +#define MMC_USRID_USRID_SHIFT (0U) +#define MMC_USRID_USRID_MASK (0xFFFFFFFFU << MMC_USRID_USRID_SHIFT) /* 0xFFFFFFFF */ +/* VERID */ +#define MMC_VERID_OFFSET (0x6CU) +#define MMC_VERID (0x5342270AU) +#define MMC_VERID_VERID_SHIFT (0U) +#define MMC_VERID_VERID_MASK (0xFFFFFFFFU << MMC_VERID_VERID_SHIFT) /* 0xFFFFFFFF */ +/* HCON */ +#define MMC_HCON_OFFSET (0x70U) +#define MMC_HCON (0x4C434C1U) +#define MMC_HCON_CARD_TYPE_SHIFT (0U) +#define MMC_HCON_CARD_TYPE_MASK (0x1U << MMC_HCON_CARD_TYPE_SHIFT) /* 0x00000001 */ +#define MMC_HCON_CARD_NUM_SHIFT (1U) +#define MMC_HCON_CARD_NUM_MASK (0x1FU << MMC_HCON_CARD_NUM_SHIFT) /* 0x0000003E */ +#define MMC_HCON_H_BUS_TYPE_SHIFT (6U) +#define MMC_HCON_H_BUS_TYPE_MASK (0x1U << MMC_HCON_H_BUS_TYPE_SHIFT) /* 0x00000040 */ +#define MMC_HCON_H_DATA_WIDTH_SHIFT (7U) +#define MMC_HCON_H_DATA_WIDTH_MASK (0x7U << MMC_HCON_H_DATA_WIDTH_SHIFT) /* 0x00000380 */ +#define MMC_HCON_H_ADDR_WIDTH_SHIFT (10U) +#define MMC_HCON_H_ADDR_WIDTH_MASK (0x3FU << MMC_HCON_H_ADDR_WIDTH_SHIFT) /* 0x0000FC00 */ +#define MMC_HCON_DMA_INTERFACE_SHIFT (16U) +#define MMC_HCON_DMA_INTERFACE_MASK (0x3U << MMC_HCON_DMA_INTERFACE_SHIFT) /* 0x00030000 */ +#define MMC_HCON_GE_DMA_DATA_WIDTH_SHIFT (18U) +#define MMC_HCON_GE_DMA_DATA_WIDTH_MASK (0x7U << MMC_HCON_GE_DMA_DATA_WIDTH_SHIFT) /* 0x001C0000 */ +#define MMC_HCON_FIFO_RAM_INSIDE_SHIFT (21U) +#define MMC_HCON_FIFO_RAM_INSIDE_MASK (0x1U << MMC_HCON_FIFO_RAM_INSIDE_SHIFT) /* 0x00200000 */ +#define MMC_HCON_IMPL_HOLD_REG_SHIFT (22U) +#define MMC_HCON_IMPL_HOLD_REG_MASK (0x1U << MMC_HCON_IMPL_HOLD_REG_SHIFT) /* 0x00400000 */ +#define MMC_HCON_SET_CLK_FALSE_PATH_SHIFT (23U) +#define MMC_HCON_SET_CLK_FALSE_PATH_MASK (0x1U << MMC_HCON_SET_CLK_FALSE_PATH_SHIFT) /* 0x00800000 */ +#define MMC_HCON_NUM_CLK_DIV_SHIFT (24U) +#define MMC_HCON_NUM_CLK_DIV_MASK (0x3U << MMC_HCON_NUM_CLK_DIV_SHIFT) /* 0x03000000 */ +#define MMC_HCON_AREA_OPTIMIZED_SHIFT (26U) +#define MMC_HCON_AREA_OPTIMIZED_MASK (0x1U << MMC_HCON_AREA_OPTIMIZED_SHIFT) /* 0x04000000 */ +/* UHSREG */ +#define MMC_UHSREG_OFFSET (0x74U) +#define MMC_UHSREG_DDR_REG_SHIFT (16U) +#define MMC_UHSREG_DDR_REG_MASK (0x1U << MMC_UHSREG_DDR_REG_SHIFT) /* 0x00010000 */ +/* RSTN */ +#define MMC_RSTN_OFFSET (0x78U) +#define MMC_RSTN_CARD_RESET_SHIFT (0U) +#define MMC_RSTN_CARD_RESET_MASK (0x1U << MMC_RSTN_CARD_RESET_SHIFT) /* 0x00000001 */ +/* BMOD */ +#define MMC_BMOD_OFFSET (0x80U) +#define MMC_BMOD_SWR_SHIFT (0U) +#define MMC_BMOD_SWR_MASK (0x1U << MMC_BMOD_SWR_SHIFT) /* 0x00000001 */ +#define MMC_BMOD_FB_SHIFT (1U) +#define MMC_BMOD_FB_MASK (0x1U << MMC_BMOD_FB_SHIFT) /* 0x00000002 */ +#define MMC_BMOD_DSL_SHIFT (2U) +#define MMC_BMOD_DSL_MASK (0x1FU << MMC_BMOD_DSL_SHIFT) /* 0x0000007C */ +#define MMC_BMOD_DE_SHIFT (7U) +#define MMC_BMOD_DE_MASK (0x1U << MMC_BMOD_DE_SHIFT) /* 0x00000080 */ +#define MMC_BMOD_PBL_SHIFT (8U) +#define MMC_BMOD_PBL_MASK (0x7U << MMC_BMOD_PBL_SHIFT) /* 0x00000700 */ +/* PLDMND */ +#define MMC_PLDMND_OFFSET (0x84U) +#define MMC_PLDMND_PD_SHIFT (0U) +#define MMC_PLDMND_PD_MASK (0xFFFFFFFFU << MMC_PLDMND_PD_SHIFT) /* 0xFFFFFFFF */ +/* DBADDR */ +#define MMC_DBADDR_OFFSET (0x88U) +#define MMC_DBADDR_SBL_SHIFT (0U) +#define MMC_DBADDR_SBL_MASK (0xFFFFFFFFU << MMC_DBADDR_SBL_SHIFT) /* 0xFFFFFFFF */ +/* IDSTS */ +#define MMC_IDSTS_OFFSET (0x8CU) +#define MMC_IDSTS_TI_SHIFT (0U) +#define MMC_IDSTS_TI_MASK (0x1U << MMC_IDSTS_TI_SHIFT) /* 0x00000001 */ +#define MMC_IDSTS_RI_SHIFT (1U) +#define MMC_IDSTS_RI_MASK (0x1U << MMC_IDSTS_RI_SHIFT) /* 0x00000002 */ +#define MMC_IDSTS_FBE_SHIFT (2U) +#define MMC_IDSTS_FBE_MASK (0x1U << MMC_IDSTS_FBE_SHIFT) /* 0x00000004 */ +#define MMC_IDSTS_DUI_SHIFT (4U) +#define MMC_IDSTS_DUI_MASK (0x1U << MMC_IDSTS_DUI_SHIFT) /* 0x00000010 */ +#define MMC_IDSTS_CES_SHIFT (5U) +#define MMC_IDSTS_CES_MASK (0x1U << MMC_IDSTS_CES_SHIFT) /* 0x00000020 */ +#define MMC_IDSTS_NIS_SHIFT (8U) +#define MMC_IDSTS_NIS_MASK (0x1U << MMC_IDSTS_NIS_SHIFT) /* 0x00000100 */ +#define MMC_IDSTS_AIS_SHIFT (9U) +#define MMC_IDSTS_AIS_MASK (0x1U << MMC_IDSTS_AIS_SHIFT) /* 0x00000200 */ +#define MMC_IDSTS_EB_SHIFT (10U) +#define MMC_IDSTS_EB_MASK (0x7U << MMC_IDSTS_EB_SHIFT) /* 0x00001C00 */ +#define MMC_IDSTS_FSM_SHIFT (13U) +#define MMC_IDSTS_FSM_MASK (0xFU << MMC_IDSTS_FSM_SHIFT) /* 0x0001E000 */ +/* IDINTEN */ +#define MMC_IDINTEN_OFFSET (0x90U) +#define MMC_IDINTEN_TI_SHIFT (0U) +#define MMC_IDINTEN_TI_MASK (0x1U << MMC_IDINTEN_TI_SHIFT) /* 0x00000001 */ +#define MMC_IDINTEN_RI_SHIFT (1U) +#define MMC_IDINTEN_RI_MASK (0x1U << MMC_IDINTEN_RI_SHIFT) /* 0x00000002 */ +#define MMC_IDINTEN_FBE_SHIFT (2U) +#define MMC_IDINTEN_FBE_MASK (0x1U << MMC_IDINTEN_FBE_SHIFT) /* 0x00000004 */ +#define MMC_IDINTEN_DU_SHIFT (4U) +#define MMC_IDINTEN_DU_MASK (0x1U << MMC_IDINTEN_DU_SHIFT) /* 0x00000010 */ +#define MMC_IDINTEN_CES_SHIFT (5U) +#define MMC_IDINTEN_CES_MASK (0x1U << MMC_IDINTEN_CES_SHIFT) /* 0x00000020 */ +#define MMC_IDINTEN_NI_SHIFT (8U) +#define MMC_IDINTEN_NI_MASK (0x1U << MMC_IDINTEN_NI_SHIFT) /* 0x00000100 */ +#define MMC_IDINTEN_AI_SHIFT (9U) +#define MMC_IDINTEN_AI_MASK (0x1U << MMC_IDINTEN_AI_SHIFT) /* 0x00000200 */ +/* DSCADDR */ +#define MMC_DSCADDR_OFFSET (0x94U) +#define MMC_DSCADDR_HDA_SHIFT (0U) +#define MMC_DSCADDR_HDA_MASK (0xFFFFFFFFU << MMC_DSCADDR_HDA_SHIFT) /* 0xFFFFFFFF */ +/* BUFADDR */ +#define MMC_BUFADDR_OFFSET (0x98U) +#define MMC_BUFADDR_HBA_SHIFT (0U) +#define MMC_BUFADDR_HBA_MASK (0xFFFFFFFFU << MMC_BUFADDR_HBA_SHIFT) /* 0xFFFFFFFF */ +/* CARDTHRCTL */ +#define MMC_CARDTHRCTL_OFFSET (0x100U) +#define MMC_CARDTHRCTL_CARD_RD_THRES_EN_SHIFT (0U) +#define MMC_CARDTHRCTL_CARD_RD_THRES_EN_MASK (0x1U << MMC_CARDTHRCTL_CARD_RD_THRES_EN_SHIFT) /* 0x00000001 */ +#define MMC_CARDTHRCTL_BUSY_CLR_INT_EN_SHIFT (1U) +#define MMC_CARDTHRCTL_BUSY_CLR_INT_EN_MASK (0x1U << MMC_CARDTHRCTL_BUSY_CLR_INT_EN_SHIFT) /* 0x00000002 */ +#define MMC_CARDTHRCTL_CARD_RD_THRES_SHIFT (16U) +#define MMC_CARDTHRCTL_CARD_RD_THRES_MASK (0xFFFU << MMC_CARDTHRCTL_CARD_RD_THRES_SHIFT) /* 0x0FFF0000 */ +/* BACKEND_POWER */ +#define MMC_BACKEND_POWER_OFFSET (0x104U) +#define MMC_BACKEND_POWER_BACK_END_POWER_SHIFT (0U) +#define MMC_BACKEND_POWER_BACK_END_POWER_MASK (0x1U << MMC_BACKEND_POWER_BACK_END_POWER_SHIFT) /* 0x00000001 */ +/* EMMCDDR_REG */ +#define MMC_EMMCDDR_REG_OFFSET (0x10CU) +#define MMC_EMMCDDR_REG_HALF_START_BIT_SHIFT (0U) +#define MMC_EMMCDDR_REG_HALF_START_BIT_MASK (0x1U << MMC_EMMCDDR_REG_HALF_START_BIT_SHIFT) /* 0x00000001 */ +/* RDYINT_GEN */ +#define MMC_RDYINT_GEN_OFFSET (0x120U) +#define MMC_RDYINT_GEN_RDYINT_GEN_MAXVAL_SHIFT (0U) +#define MMC_RDYINT_GEN_RDYINT_GEN_MAXVAL_MASK (0xFFU << MMC_RDYINT_GEN_RDYINT_GEN_MAXVAL_SHIFT) /* 0x000000FF */ +#define MMC_RDYINT_GEN_RDYINT_GEN_WORKING_SHIFT (8U) +#define MMC_RDYINT_GEN_RDYINT_GEN_WORKING_MASK (0x1U << MMC_RDYINT_GEN_RDYINT_GEN_WORKING_SHIFT) /* 0x00000100 */ +#define MMC_RDYINT_GEN_RDYINT_CNT_STATUS_SHIFT (16U) +#define MMC_RDYINT_GEN_RDYINT_CNT_STATUS_MASK (0xFFU << MMC_RDYINT_GEN_RDYINT_CNT_STATUS_SHIFT) /* 0x00FF0000 */ +#define MMC_RDYINT_GEN_RDYINT_CNT_FINISH_SHIFT (24U) +#define MMC_RDYINT_GEN_RDYINT_CNT_FINISH_MASK (0x1U << MMC_RDYINT_GEN_RDYINT_CNT_FINISH_SHIFT) /* 0x01000000 */ +/* FIFO_BASE */ +#define MMC_FIFO_BASE_OFFSET (0x200U) +#define MMC_FIFO_BASE_FIFO_BASE_ADDR_SHIFT (0U) +#define MMC_FIFO_BASE_FIFO_BASE_ADDR_MASK (0xFFFFFFFFU << MMC_FIFO_BASE_FIFO_BASE_ADDR_SHIFT) /* 0xFFFFFFFF */ +/******************************************FSPI******************************************/ +/* CTRL0 */ +#define FSPI_CTRL0_OFFSET (0x0U) +#define FSPI_CTRL0_SPIM_SHIFT (0U) +#define FSPI_CTRL0_SPIM_MASK (0x1U << FSPI_CTRL0_SPIM_SHIFT) /* 0x00000001 */ +#define FSPI_CTRL0_SHIFTPHASE_SHIFT (1U) +#define FSPI_CTRL0_SHIFTPHASE_MASK (0x1U << FSPI_CTRL0_SHIFTPHASE_SHIFT) /* 0x00000002 */ +#define FSPI_CTRL0_IDLE_CYCLE_SHIFT (4U) +#define FSPI_CTRL0_IDLE_CYCLE_MASK (0xFU << FSPI_CTRL0_IDLE_CYCLE_SHIFT) /* 0x000000F0 */ +#define FSPI_CTRL0_CMDB_SHIFT (8U) +#define FSPI_CTRL0_CMDB_MASK (0x3U << FSPI_CTRL0_CMDB_SHIFT) /* 0x00000300 */ +#define FSPI_CTRL0_ADRB_SHIFT (10U) +#define FSPI_CTRL0_ADRB_MASK (0x3U << FSPI_CTRL0_ADRB_SHIFT) /* 0x00000C00 */ +#define FSPI_CTRL0_DATB_SHIFT (12U) +#define FSPI_CTRL0_DATB_MASK (0x3U << FSPI_CTRL0_DATB_SHIFT) /* 0x00003000 */ +/* IMR */ +#define FSPI_IMR_OFFSET (0x4U) +#define FSPI_IMR_RXFM_SHIFT (0U) +#define FSPI_IMR_RXFM_MASK (0x1U << FSPI_IMR_RXFM_SHIFT) /* 0x00000001 */ +#define FSPI_IMR_RXUM_SHIFT (1U) +#define FSPI_IMR_RXUM_MASK (0x1U << FSPI_IMR_RXUM_SHIFT) /* 0x00000002 */ +#define FSPI_IMR_TXOM_SHIFT (2U) +#define FSPI_IMR_TXOM_MASK (0x1U << FSPI_IMR_TXOM_SHIFT) /* 0x00000004 */ +#define FSPI_IMR_TXEM_SHIFT (3U) +#define FSPI_IMR_TXEM_MASK (0x1U << FSPI_IMR_TXEM_SHIFT) /* 0x00000008 */ +#define FSPI_IMR_TRANSM_SHIFT (4U) +#define FSPI_IMR_TRANSM_MASK (0x1U << FSPI_IMR_TRANSM_SHIFT) /* 0x00000010 */ +#define FSPI_IMR_AHBM_SHIFT (5U) +#define FSPI_IMR_AHBM_MASK (0x1U << FSPI_IMR_AHBM_SHIFT) /* 0x00000020 */ +#define FSPI_IMR_NSPIM_SHIFT (6U) +#define FSPI_IMR_NSPIM_MASK (0x1U << FSPI_IMR_NSPIM_SHIFT) /* 0x00000040 */ +#define FSPI_IMR_DMAM_SHIFT (7U) +#define FSPI_IMR_DMAM_MASK (0x1U << FSPI_IMR_DMAM_SHIFT) /* 0x00000080 */ +/* ICLR */ +#define FSPI_ICLR_OFFSET (0x8U) +#define FSPI_ICLR_RXFC_SHIFT (0U) +#define FSPI_ICLR_RXFC_MASK (0x1U << FSPI_ICLR_RXFC_SHIFT) /* 0x00000001 */ +#define FSPI_ICLR_RXUC_SHIFT (1U) +#define FSPI_ICLR_RXUC_MASK (0x1U << FSPI_ICLR_RXUC_SHIFT) /* 0x00000002 */ +#define FSPI_ICLR_TXOC_SHIFT (2U) +#define FSPI_ICLR_TXOC_MASK (0x1U << FSPI_ICLR_TXOC_SHIFT) /* 0x00000004 */ +#define FSPI_ICLR_TXEC_SHIFT (3U) +#define FSPI_ICLR_TXEC_MASK (0x1U << FSPI_ICLR_TXEC_SHIFT) /* 0x00000008 */ +#define FSPI_ICLR_TRANSC_SHIFT (4U) +#define FSPI_ICLR_TRANSC_MASK (0x1U << FSPI_ICLR_TRANSC_SHIFT) /* 0x00000010 */ +#define FSPI_ICLR_AHBC_SHIFT (5U) +#define FSPI_ICLR_AHBC_MASK (0x1U << FSPI_ICLR_AHBC_SHIFT) /* 0x00000020 */ +#define FSPI_ICLR_NSPIC_SHIFT (6U) +#define FSPI_ICLR_NSPIC_MASK (0x1U << FSPI_ICLR_NSPIC_SHIFT) /* 0x00000040 */ +#define FSPI_ICLR_DMAC_SHIFT (7U) +#define FSPI_ICLR_DMAC_MASK (0x1U << FSPI_ICLR_DMAC_SHIFT) /* 0x00000080 */ +/* FTLR */ +#define FSPI_FTLR_OFFSET (0xCU) +#define FSPI_FTLR_TXFTLR_SHIFT (0U) +#define FSPI_FTLR_TXFTLR_MASK (0xFFU << FSPI_FTLR_TXFTLR_SHIFT) /* 0x000000FF */ +#define FSPI_FTLR_RXFTLR_SHIFT (8U) +#define FSPI_FTLR_RXFTLR_MASK (0xFFU << FSPI_FTLR_RXFTLR_SHIFT) /* 0x0000FF00 */ +/* RCVR */ +#define FSPI_RCVR_OFFSET (0x10U) +#define FSPI_RCVR_RCVR_SHIFT (0U) +#define FSPI_RCVR_RCVR_MASK (0x1U << FSPI_RCVR_RCVR_SHIFT) /* 0x00000001 */ +/* AX0 */ +#define FSPI_AX0_OFFSET (0x14U) +#define FSPI_AX0_AX_SHIFT (0U) +#define FSPI_AX0_AX_MASK (0xFFU << FSPI_AX0_AX_SHIFT) /* 0x000000FF */ +/* ABIT0 */ +#define FSPI_ABIT0_OFFSET (0x18U) +#define FSPI_ABIT0_ABIT_SHIFT (0U) +#define FSPI_ABIT0_ABIT_MASK (0x1FU << FSPI_ABIT0_ABIT_SHIFT) /* 0x0000001F */ +/* ISR */ +#define FSPI_ISR_OFFSET (0x1CU) +#define FSPI_ISR_RXFS_SHIFT (0U) +#define FSPI_ISR_RXFS_MASK (0x1U << FSPI_ISR_RXFS_SHIFT) /* 0x00000001 */ +#define FSPI_ISR_RXUS_SHIFT (1U) +#define FSPI_ISR_RXUS_MASK (0x1U << FSPI_ISR_RXUS_SHIFT) /* 0x00000002 */ +#define FSPI_ISR_TXOS_SHIFT (2U) +#define FSPI_ISR_TXOS_MASK (0x1U << FSPI_ISR_TXOS_SHIFT) /* 0x00000004 */ +#define FSPI_ISR_TXES_SHIFT (3U) +#define FSPI_ISR_TXES_MASK (0x1U << FSPI_ISR_TXES_SHIFT) /* 0x00000008 */ +#define FSPI_ISR_TRANSS_SHIFT (4U) +#define FSPI_ISR_TRANSS_MASK (0x1U << FSPI_ISR_TRANSS_SHIFT) /* 0x00000010 */ +#define FSPI_ISR_AHBS_SHIFT (5U) +#define FSPI_ISR_AHBS_MASK (0x1U << FSPI_ISR_AHBS_SHIFT) /* 0x00000020 */ +#define FSPI_ISR_NSPIS_SHIFT (6U) +#define FSPI_ISR_NSPIS_MASK (0x1U << FSPI_ISR_NSPIS_SHIFT) /* 0x00000040 */ +#define FSPI_ISR_DMAS_SHIFT (7U) +#define FSPI_ISR_DMAS_MASK (0x1U << FSPI_ISR_DMAS_SHIFT) /* 0x00000080 */ +/* FSR */ +#define FSPI_FSR_OFFSET (0x20U) +#define FSPI_FSR_TXFS_SHIFT (0U) +#define FSPI_FSR_TXFS_MASK (0x1U << FSPI_FSR_TXFS_SHIFT) /* 0x00000001 */ +#define FSPI_FSR_TXES_SHIFT (1U) +#define FSPI_FSR_TXES_MASK (0x1U << FSPI_FSR_TXES_SHIFT) /* 0x00000002 */ +#define FSPI_FSR_RXES_SHIFT (2U) +#define FSPI_FSR_RXES_MASK (0x1U << FSPI_FSR_RXES_SHIFT) /* 0x00000004 */ +#define FSPI_FSR_RXFS_SHIFT (3U) +#define FSPI_FSR_RXFS_MASK (0x1U << FSPI_FSR_RXFS_SHIFT) /* 0x00000008 */ +#define FSPI_FSR_TXWLVL_SHIFT (8U) +#define FSPI_FSR_TXWLVL_MASK (0x1FU << FSPI_FSR_TXWLVL_SHIFT) /* 0x00001F00 */ +#define FSPI_FSR_RXWLVL_SHIFT (16U) +#define FSPI_FSR_RXWLVL_MASK (0x1FU << FSPI_FSR_RXWLVL_SHIFT) /* 0x001F0000 */ +/* SR */ +#define FSPI_SR_OFFSET (0x24U) +#define FSPI_SR (0x0U) +#define FSPI_SR_SR_SHIFT (0U) +#define FSPI_SR_SR_MASK (0x1U << FSPI_SR_SR_SHIFT) /* 0x00000001 */ +/* RISR */ +#define FSPI_RISR_OFFSET (0x28U) +#define FSPI_RISR (0x0U) +#define FSPI_RISR_RXFS_SHIFT (0U) +#define FSPI_RISR_RXFS_MASK (0x1U << FSPI_RISR_RXFS_SHIFT) /* 0x00000001 */ +#define FSPI_RISR_RXUS_SHIFT (1U) +#define FSPI_RISR_RXUS_MASK (0x1U << FSPI_RISR_RXUS_SHIFT) /* 0x00000002 */ +#define FSPI_RISR_TXOS_SHIFT (2U) +#define FSPI_RISR_TXOS_MASK (0x1U << FSPI_RISR_TXOS_SHIFT) /* 0x00000004 */ +#define FSPI_RISR_TXES_SHIFT (3U) +#define FSPI_RISR_TXES_MASK (0x1U << FSPI_RISR_TXES_SHIFT) /* 0x00000008 */ +#define FSPI_RISR_TRANSS_SHIFT (4U) +#define FSPI_RISR_TRANSS_MASK (0x1U << FSPI_RISR_TRANSS_SHIFT) /* 0x00000010 */ +#define FSPI_RISR_AHBS_SHIFT (5U) +#define FSPI_RISR_AHBS_MASK (0x1U << FSPI_RISR_AHBS_SHIFT) /* 0x00000020 */ +#define FSPI_RISR_NSPIS_SHIFT (6U) +#define FSPI_RISR_NSPIS_MASK (0x1U << FSPI_RISR_NSPIS_SHIFT) /* 0x00000040 */ +#define FSPI_RISR_DMAS_SHIFT (7U) +#define FSPI_RISR_DMAS_MASK (0x1U << FSPI_RISR_DMAS_SHIFT) /* 0x00000080 */ +/* VER */ +#define FSPI_VER_OFFSET (0x2CU) +#define FSPI_VER (0x5U) +#define FSPI_VER_VER_SHIFT (0U) +#define FSPI_VER_VER_MASK (0xFFFFU << FSPI_VER_VER_SHIFT) /* 0x0000FFFF */ +/* QOP */ +#define FSPI_QOP_OFFSET (0x30U) +#define FSPI_QOP_SO123_SHIFT (0U) +#define FSPI_QOP_SO123_MASK (0x1U << FSPI_QOP_SO123_SHIFT) /* 0x00000001 */ +#define FSPI_QOP_SO123BP_SHIFT (1U) +#define FSPI_QOP_SO123BP_MASK (0x1U << FSPI_QOP_SO123BP_SHIFT) /* 0x00000002 */ +/* EXT_CTRL */ +#define FSPI_EXT_CTRL_OFFSET (0x34U) +#define FSPI_EXT_CTRL_CS_DESEL_CTRL_SHIFT (0U) +#define FSPI_EXT_CTRL_CS_DESEL_CTRL_MASK (0xFU << FSPI_EXT_CTRL_CS_DESEL_CTRL_SHIFT) /* 0x0000000F */ +#define FSPI_EXT_CTRL_SWITCH_IO_DUMM_CNT_SHIFT (4U) +#define FSPI_EXT_CTRL_SWITCH_IO_DUMM_CNT_MASK (0xFU << FSPI_EXT_CTRL_SWITCH_IO_DUMM_CNT_SHIFT) /* 0x000000F0 */ +#define FSPI_EXT_CTRL_SWITCH_IO_O2I_CNT_SHIFT (8U) +#define FSPI_EXT_CTRL_SWITCH_IO_O2I_CNT_MASK (0xFU << FSPI_EXT_CTRL_SWITCH_IO_O2I_CNT_SHIFT) /* 0x00000F00 */ +#define FSPI_EXT_CTRL_TRANS_INT_MODE_SHIFT (13U) +#define FSPI_EXT_CTRL_TRANS_INT_MODE_MASK (0x1U << FSPI_EXT_CTRL_TRANS_INT_MODE_SHIFT) /* 0x00002000 */ +#define FSPI_EXT_CTRL_SR_GEN_MODE_SHIFT (14U) +#define FSPI_EXT_CTRL_SR_GEN_MODE_MASK (0x1U << FSPI_EXT_CTRL_SR_GEN_MODE_SHIFT) /* 0x00004000 */ +/* DLL_CTRL0 */ +#define FSPI_DLL_CTRL0_OFFSET (0x3CU) +#define FSPI_DLL_CTRL0_SMP_DLL_CFG_SHIFT (0U) +#define FSPI_DLL_CTRL0_SMP_DLL_CFG_MASK (0x1FFU << FSPI_DLL_CTRL0_SMP_DLL_CFG_SHIFT) /* 0x000001FF */ +#define FSPI_DLL_CTRL0_SCLK_SMP_SEL_SHIFT (15U) +#define FSPI_DLL_CTRL0_SCLK_SMP_SEL_MASK (0x1U << FSPI_DLL_CTRL0_SCLK_SMP_SEL_SHIFT) /* 0x00008000 */ +/* EXT_AX */ +#define FSPI_EXT_AX_OFFSET (0x44U) +#define FSPI_EXT_AX_AX_CANCEL_PAT_SHIFT (0U) +#define FSPI_EXT_AX_AX_CANCEL_PAT_MASK (0xFFU << FSPI_EXT_AX_AX_CANCEL_PAT_SHIFT) /* 0x000000FF */ +#define FSPI_EXT_AX_AX_SETUP_PAT_SHIFT (8U) +#define FSPI_EXT_AX_AX_SETUP_PAT_MASK (0xFFU << FSPI_EXT_AX_AX_SETUP_PAT_SHIFT) /* 0x0000FF00 */ +/* SCLK_INATM_CNT */ +#define FSPI_SCLK_INATM_CNT_OFFSET (0x48U) +#define FSPI_SCLK_INATM_CNT_SCLK_INATM_CNT_SHIFT (0U) +#define FSPI_SCLK_INATM_CNT_SCLK_INATM_CNT_MASK (0xFFFFFFFFU << FSPI_SCLK_INATM_CNT_SCLK_INATM_CNT_SHIFT) /* 0xFFFFFFFF */ +/* XMMC_WCMD0 */ +#define FSPI_XMMC_WCMD0_OFFSET (0x50U) +#define FSPI_XMMC_WCMD0_CMD_SHIFT (0U) +#define FSPI_XMMC_WCMD0_CMD_MASK (0xFFU << FSPI_XMMC_WCMD0_CMD_SHIFT) /* 0x000000FF */ +#define FSPI_XMMC_WCMD0_DUMM_SHIFT (8U) +#define FSPI_XMMC_WCMD0_DUMM_MASK (0xFU << FSPI_XMMC_WCMD0_DUMM_SHIFT) /* 0x00000F00 */ +#define FSPI_XMMC_WCMD0_CONT_SHIFT (13U) +#define FSPI_XMMC_WCMD0_CONT_MASK (0x1U << FSPI_XMMC_WCMD0_CONT_SHIFT) /* 0x00002000 */ +#define FSPI_XMMC_WCMD0_ADDRB_SHIFT (14U) +#define FSPI_XMMC_WCMD0_ADDRB_MASK (0x3U << FSPI_XMMC_WCMD0_ADDRB_SHIFT) /* 0x0000C000 */ +/* XMMC_RCMD0 */ +#define FSPI_XMMC_RCMD0_OFFSET (0x54U) +#define FSPI_XMMC_RCMD0_CMD_SHIFT (0U) +#define FSPI_XMMC_RCMD0_CMD_MASK (0xFFU << FSPI_XMMC_RCMD0_CMD_SHIFT) /* 0x000000FF */ +#define FSPI_XMMC_RCMD0_DUMM_SHIFT (8U) +#define FSPI_XMMC_RCMD0_DUMM_MASK (0xFU << FSPI_XMMC_RCMD0_DUMM_SHIFT) /* 0x00000F00 */ +#define FSPI_XMMC_RCMD0_CONT_SHIFT (13U) +#define FSPI_XMMC_RCMD0_CONT_MASK (0x1U << FSPI_XMMC_RCMD0_CONT_SHIFT) /* 0x00002000 */ +#define FSPI_XMMC_RCMD0_ADDRB_SHIFT (14U) +#define FSPI_XMMC_RCMD0_ADDRB_MASK (0x3U << FSPI_XMMC_RCMD0_ADDRB_SHIFT) /* 0x0000C000 */ +/* XMMC_CTRL */ +#define FSPI_XMMC_CTRL_OFFSET (0x58U) +#define FSPI_XMMC_CTRL_DEV_HWEN_SHIFT (5U) +#define FSPI_XMMC_CTRL_DEV_HWEN_MASK (0x1U << FSPI_XMMC_CTRL_DEV_HWEN_SHIFT) /* 0x00000020 */ +#define FSPI_XMMC_CTRL_PFT_EN_SHIFT (6U) +#define FSPI_XMMC_CTRL_PFT_EN_MASK (0x1U << FSPI_XMMC_CTRL_PFT_EN_SHIFT) /* 0x00000040 */ +/* MODE */ +#define FSPI_MODE_OFFSET (0x5CU) +#define FSPI_MODE_XMMC_MODE_EN_SHIFT (0U) +#define FSPI_MODE_XMMC_MODE_EN_MASK (0x1U << FSPI_MODE_XMMC_MODE_EN_SHIFT) /* 0x00000001 */ +/* DEVRGN */ +#define FSPI_DEVRGN_OFFSET (0x60U) +#define FSPI_DEVRGN_RSIZE_SHIFT (0U) +#define FSPI_DEVRGN_RSIZE_MASK (0x1FU << FSPI_DEVRGN_RSIZE_SHIFT) /* 0x0000001F */ +#define FSPI_DEVRGN_DEC_CTRL_SHIFT (8U) +#define FSPI_DEVRGN_DEC_CTRL_MASK (0x3U << FSPI_DEVRGN_DEC_CTRL_SHIFT) /* 0x00000300 */ +/* DEVSIZE0 */ +#define FSPI_DEVSIZE0_OFFSET (0x64U) +#define FSPI_DEVSIZE0_DSIZE_SHIFT (0U) +#define FSPI_DEVSIZE0_DSIZE_MASK (0x1FU << FSPI_DEVSIZE0_DSIZE_SHIFT) /* 0x0000001F */ +/* TME0 */ +#define FSPI_TME0_OFFSET (0x68U) +#define FSPI_TME0_SCLK_INATM_EN_SHIFT (1U) +#define FSPI_TME0_SCLK_INATM_EN_MASK (0x1U << FSPI_TME0_SCLK_INATM_EN_SHIFT) /* 0x00000002 */ +/* XMMC_RX_WTMRK */ +#define FSPI_XMMC_RX_WTMRK_OFFSET (0x70U) +#define FSPI_XMMC_RX_WTMRK_RX_FULL_WTMRK_SHIFT (0U) +#define FSPI_XMMC_RX_WTMRK_RX_FULL_WTMRK_MASK (0xFFU << FSPI_XMMC_RX_WTMRK_RX_FULL_WTMRK_SHIFT) /* 0x000000FF */ +/* DMATR */ +#define FSPI_DMATR_OFFSET (0x80U) +#define FSPI_DMATR_DMATR_SHIFT (0U) +#define FSPI_DMATR_DMATR_MASK (0x1U << FSPI_DMATR_DMATR_SHIFT) /* 0x00000001 */ +/* DMAADDR */ +#define FSPI_DMAADDR_OFFSET (0x84U) +#define FSPI_DMAADDR_DMAADDR_SHIFT (0U) +#define FSPI_DMAADDR_DMAADDR_MASK (0xFFFFFFFFU << FSPI_DMAADDR_DMAADDR_SHIFT) /* 0xFFFFFFFF */ +/* LEN_CTRL */ +#define FSPI_LEN_CTRL_OFFSET (0x88U) +#define FSPI_LEN_CTRL_TRB_SEL_SHIFT (0U) +#define FSPI_LEN_CTRL_TRB_SEL_MASK (0x1U << FSPI_LEN_CTRL_TRB_SEL_SHIFT) /* 0x00000001 */ +/* LEN_EXT */ +#define FSPI_LEN_EXT_OFFSET (0x8CU) +#define FSPI_LEN_EXT_TRB_EXT_SHIFT (0U) +#define FSPI_LEN_EXT_TRB_EXT_MASK (0xFFFFFFFFU << FSPI_LEN_EXT_TRB_EXT_SHIFT) /* 0xFFFFFFFF */ +/* XMMCSR */ +#define FSPI_XMMCSR_OFFSET (0x94U) +#define FSPI_XMMCSR_SLOPOVER0_SHIFT (0U) +#define FSPI_XMMCSR_SLOPOVER0_MASK (0x1U << FSPI_XMMCSR_SLOPOVER0_SHIFT) /* 0x00000001 */ +#define FSPI_XMMCSR_SLOPOVER1_SHIFT (1U) +#define FSPI_XMMCSR_SLOPOVER1_MASK (0x1U << FSPI_XMMCSR_SLOPOVER1_SHIFT) /* 0x00000002 */ +/* CMD */ +#define FSPI_CMD_OFFSET (0x100U) +#define FSPI_CMD_CMD_SHIFT (0U) +#define FSPI_CMD_CMD_MASK (0xFFU << FSPI_CMD_CMD_SHIFT) /* 0x000000FF */ +#define FSPI_CMD_DUMM_SHIFT (8U) +#define FSPI_CMD_DUMM_MASK (0xFU << FSPI_CMD_DUMM_SHIFT) /* 0x00000F00 */ +#define FSPI_CMD_WR_SHIFT (12U) +#define FSPI_CMD_WR_MASK (0x1U << FSPI_CMD_WR_SHIFT) /* 0x00001000 */ +#define FSPI_CMD_CONT_SHIFT (13U) +#define FSPI_CMD_CONT_MASK (0x1U << FSPI_CMD_CONT_SHIFT) /* 0x00002000 */ +#define FSPI_CMD_ADDRB_SHIFT (14U) +#define FSPI_CMD_ADDRB_MASK (0x3U << FSPI_CMD_ADDRB_SHIFT) /* 0x0000C000 */ +#define FSPI_CMD_TRB_SHIFT (16U) +#define FSPI_CMD_TRB_MASK (0x3FFFU << FSPI_CMD_TRB_SHIFT) /* 0x3FFF0000 */ +#define FSPI_CMD_CS_SHIFT (30U) +#define FSPI_CMD_CS_MASK (0x3U << FSPI_CMD_CS_SHIFT) /* 0xC0000000 */ +/* ADDR */ +#define FSPI_ADDR_OFFSET (0x104U) +#define FSPI_ADDR_ADDR_SHIFT (0U) +#define FSPI_ADDR_ADDR_MASK (0xFFFFFFFFU << FSPI_ADDR_ADDR_SHIFT) /* 0xFFFFFFFF */ +/* DATA */ +#define FSPI_DATA_OFFSET (0x108U) +#define FSPI_DATA_DATA_SHIFT (0U) +#define FSPI_DATA_DATA_MASK (0xFFFFFFFFU << FSPI_DATA_DATA_SHIFT) /* 0xFFFFFFFF */ +/* CTRL1 */ +#define FSPI_CTRL1_OFFSET (0x200U) +#define FSPI_CTRL1_SPIM_SHIFT (0U) +#define FSPI_CTRL1_SPIM_MASK (0x1U << FSPI_CTRL1_SPIM_SHIFT) /* 0x00000001 */ +#define FSPI_CTRL1_SHIFTPHASE_SHIFT (1U) +#define FSPI_CTRL1_SHIFTPHASE_MASK (0x1U << FSPI_CTRL1_SHIFTPHASE_SHIFT) /* 0x00000002 */ +#define FSPI_CTRL1_IDLE_CYCLE_SHIFT (4U) +#define FSPI_CTRL1_IDLE_CYCLE_MASK (0xFU << FSPI_CTRL1_IDLE_CYCLE_SHIFT) /* 0x000000F0 */ +#define FSPI_CTRL1_CMDB_SHIFT (8U) +#define FSPI_CTRL1_CMDB_MASK (0x3U << FSPI_CTRL1_CMDB_SHIFT) /* 0x00000300 */ +#define FSPI_CTRL1_ADRB_SHIFT (10U) +#define FSPI_CTRL1_ADRB_MASK (0x3U << FSPI_CTRL1_ADRB_SHIFT) /* 0x00000C00 */ +#define FSPI_CTRL1_DATB_SHIFT (12U) +#define FSPI_CTRL1_DATB_MASK (0x3U << FSPI_CTRL1_DATB_SHIFT) /* 0x00003000 */ +/* AX1 */ +#define FSPI_AX1_OFFSET (0x214U) +#define FSPI_AX1_AX_SHIFT (0U) +#define FSPI_AX1_AX_MASK (0xFFU << FSPI_AX1_AX_SHIFT) /* 0x000000FF */ +/* ABIT1 */ +#define FSPI_ABIT1_OFFSET (0x218U) +#define FSPI_ABIT1_ABIT_SHIFT (0U) +#define FSPI_ABIT1_ABIT_MASK (0x1FU << FSPI_ABIT1_ABIT_SHIFT) /* 0x0000001F */ +/* DLL_CTRL1 */ +#define FSPI_DLL_CTRL1_OFFSET (0x23CU) +#define FSPI_DLL_CTRL1_SMP_DLL_CFG_SHIFT (0U) +#define FSPI_DLL_CTRL1_SMP_DLL_CFG_MASK (0x1FFU << FSPI_DLL_CTRL1_SMP_DLL_CFG_SHIFT) /* 0x000001FF */ +#define FSPI_DLL_CTRL1_SCLK_SMP_SEL_SHIFT (15U) +#define FSPI_DLL_CTRL1_SCLK_SMP_SEL_MASK (0x1U << FSPI_DLL_CTRL1_SCLK_SMP_SEL_SHIFT) /* 0x00008000 */ +/* XMMC_WCMD1 */ +#define FSPI_XMMC_WCMD1_OFFSET (0x250U) +#define FSPI_XMMC_WCMD1_CMD_SHIFT (0U) +#define FSPI_XMMC_WCMD1_CMD_MASK (0xFFU << FSPI_XMMC_WCMD1_CMD_SHIFT) /* 0x000000FF */ +#define FSPI_XMMC_WCMD1_DUMM_SHIFT (8U) +#define FSPI_XMMC_WCMD1_DUMM_MASK (0xFU << FSPI_XMMC_WCMD1_DUMM_SHIFT) /* 0x00000F00 */ +#define FSPI_XMMC_WCMD1_CONT_SHIFT (13U) +#define FSPI_XMMC_WCMD1_CONT_MASK (0x1U << FSPI_XMMC_WCMD1_CONT_SHIFT) /* 0x00002000 */ +#define FSPI_XMMC_WCMD1_ADDRB_SHIFT (14U) +#define FSPI_XMMC_WCMD1_ADDRB_MASK (0x3U << FSPI_XMMC_WCMD1_ADDRB_SHIFT) /* 0x0000C000 */ +/* XMMC_RCMD1 */ +#define FSPI_XMMC_RCMD1_OFFSET (0x254U) +#define FSPI_XMMC_RCMD1_CMD_SHIFT (0U) +#define FSPI_XMMC_RCMD1_CMD_MASK (0xFFU << FSPI_XMMC_RCMD1_CMD_SHIFT) /* 0x000000FF */ +#define FSPI_XMMC_RCMD1_DUMM_SHIFT (8U) +#define FSPI_XMMC_RCMD1_DUMM_MASK (0xFU << FSPI_XMMC_RCMD1_DUMM_SHIFT) /* 0x00000F00 */ +#define FSPI_XMMC_RCMD1_CONT_SHIFT (13U) +#define FSPI_XMMC_RCMD1_CONT_MASK (0x1U << FSPI_XMMC_RCMD1_CONT_SHIFT) /* 0x00002000 */ +#define FSPI_XMMC_RCMD1_ADDRB_SHIFT (14U) +#define FSPI_XMMC_RCMD1_ADDRB_MASK (0x3U << FSPI_XMMC_RCMD1_ADDRB_SHIFT) /* 0x0000C000 */ +/* DEVSIZE1 */ +#define FSPI_DEVSIZE1_OFFSET (0x264U) +#define FSPI_DEVSIZE1_DSIZE_SHIFT (0U) +#define FSPI_DEVSIZE1_DSIZE_MASK (0x1FU << FSPI_DEVSIZE1_DSIZE_SHIFT) /* 0x0000001F */ +/* TME1 */ +#define FSPI_TME1_OFFSET (0x268U) +#define FSPI_TME1_SCLK_INATM_EN_SHIFT (1U) +#define FSPI_TME1_SCLK_INATM_EN_MASK (0x1U << FSPI_TME1_SCLK_INATM_EN_SHIFT) /* 0x00000002 */ +/******************************************DMA*******************************************/ +/* DSR */ +#define DMA_DSR_OFFSET (0x0U) +#define DMA_DSR (0x0U) +#define DMA_DSR_FIELD0000_SHIFT (0U) +#define DMA_DSR_FIELD0000_MASK (0xFU << DMA_DSR_FIELD0000_SHIFT) /* 0x0000000F */ +#define DMA_DSR_FIELD0002_SHIFT (4U) +#define DMA_DSR_FIELD0002_MASK (0x1FU << DMA_DSR_FIELD0002_SHIFT) /* 0x000001F0 */ +#define DMA_DSR_FIELD0001_SHIFT (9U) +#define DMA_DSR_FIELD0001_MASK (0x1U << DMA_DSR_FIELD0001_SHIFT) /* 0x00000200 */ +/* DPC */ +#define DMA_DPC_OFFSET (0x4U) +#define DMA_DPC (0x0U) +#define DMA_DPC_FIELD0000_SHIFT (0U) +#define DMA_DPC_FIELD0000_MASK (0xFFFFFFFFU << DMA_DPC_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* INTEN */ +#define DMA_INTEN_OFFSET (0x20U) +#define DMA_INTEN_FIELD0000_SHIFT (0U) +#define DMA_INTEN_FIELD0000_MASK (0xFFFFFFFFU << DMA_INTEN_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* EVENT_RIS */ +#define DMA_EVENT_RIS_OFFSET (0x24U) +#define DMA_EVENT_RIS (0x0U) +#define DMA_EVENT_RIS_FIELD0000_SHIFT (0U) +#define DMA_EVENT_RIS_FIELD0000_MASK (0xFFFFFFFFU << DMA_EVENT_RIS_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* INTMIS */ +#define DMA_INTMIS_OFFSET (0x28U) +#define DMA_INTMIS (0x0U) +#define DMA_INTMIS_FIELD0000_SHIFT (0U) +#define DMA_INTMIS_FIELD0000_MASK (0xFFFFFFFFU << DMA_INTMIS_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* INTCLR */ +#define DMA_INTCLR_OFFSET (0x2CU) +#define DMA_INTCLR_FIELD0000_SHIFT (0U) +#define DMA_INTCLR_FIELD0000_MASK (0xFFFFFFFFU << DMA_INTCLR_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* FSRD */ +#define DMA_FSRD_OFFSET (0x30U) +#define DMA_FSRD (0x0U) +#define DMA_FSRD_FIELD0000_SHIFT (0U) +#define DMA_FSRD_FIELD0000_MASK (0xFFFFFFFFU << DMA_FSRD_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* FSRC */ +#define DMA_FSRC_OFFSET (0x34U) +#define DMA_FSRC (0x0U) +#define DMA_FSRC_FIELD0000_SHIFT (0U) +#define DMA_FSRC_FIELD0000_MASK (0xFFFFFFFFU << DMA_FSRC_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* FTRD */ +#define DMA_FTRD_OFFSET (0x38U) +#define DMA_FTRD_FIELD0000_SHIFT (0U) +#define DMA_FTRD_FIELD0000_MASK (0x1U << DMA_FTRD_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_FTRD_FIELD0005_SHIFT (1U) +#define DMA_FTRD_FIELD0005_MASK (0x1U << DMA_FTRD_FIELD0005_SHIFT) /* 0x00000002 */ +#define DMA_FTRD_FIELD0004_SHIFT (4U) +#define DMA_FTRD_FIELD0004_MASK (0x1U << DMA_FTRD_FIELD0004_SHIFT) /* 0x00000010 */ +#define DMA_FTRD_FIELD0003_SHIFT (5U) +#define DMA_FTRD_FIELD0003_MASK (0x1U << DMA_FTRD_FIELD0003_SHIFT) /* 0x00000020 */ +#define DMA_FTRD_FIELD0002_SHIFT (16U) +#define DMA_FTRD_FIELD0002_MASK (0x1U << DMA_FTRD_FIELD0002_SHIFT) /* 0x00010000 */ +#define DMA_FTRD_FIELD0001_SHIFT (30U) +#define DMA_FTRD_FIELD0001_MASK (0x1U << DMA_FTRD_FIELD0001_SHIFT) /* 0x40000000 */ +/* FTR0 */ +#define DMA_FTR0_OFFSET (0x40U) +#define DMA_FTR0 (0x0U) +#define DMA_FTR0_FIELD0000_SHIFT (0U) +#define DMA_FTR0_FIELD0000_MASK (0x1U << DMA_FTR0_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_FTR0_FIELD0011_SHIFT (1U) +#define DMA_FTR0_FIELD0011_MASK (0x1U << DMA_FTR0_FIELD0011_SHIFT) /* 0x00000002 */ +#define DMA_FTR0_FIELD0010_SHIFT (5U) +#define DMA_FTR0_FIELD0010_MASK (0x1U << DMA_FTR0_FIELD0010_SHIFT) /* 0x00000020 */ +#define DMA_FTR0_FIELD0009_SHIFT (6U) +#define DMA_FTR0_FIELD0009_MASK (0x1U << DMA_FTR0_FIELD0009_SHIFT) /* 0x00000040 */ +#define DMA_FTR0_FIELD0008_SHIFT (7U) +#define DMA_FTR0_FIELD0008_MASK (0x1U << DMA_FTR0_FIELD0008_SHIFT) /* 0x00000080 */ +#define DMA_FTR0_FIELD0007_SHIFT (12U) +#define DMA_FTR0_FIELD0007_MASK (0x1U << DMA_FTR0_FIELD0007_SHIFT) /* 0x00001000 */ +#define DMA_FTR0_FIELD0006_SHIFT (13U) +#define DMA_FTR0_FIELD0006_MASK (0x1U << DMA_FTR0_FIELD0006_SHIFT) /* 0x00002000 */ +#define DMA_FTR0_FIELD0005_SHIFT (16U) +#define DMA_FTR0_FIELD0005_MASK (0x1U << DMA_FTR0_FIELD0005_SHIFT) /* 0x00010000 */ +#define DMA_FTR0_FIELD0004_SHIFT (17U) +#define DMA_FTR0_FIELD0004_MASK (0x1U << DMA_FTR0_FIELD0004_SHIFT) /* 0x00020000 */ +#define DMA_FTR0_FIELD0003_SHIFT (18U) +#define DMA_FTR0_FIELD0003_MASK (0x1U << DMA_FTR0_FIELD0003_SHIFT) /* 0x00040000 */ +#define DMA_FTR0_FIELD0002_SHIFT (30U) +#define DMA_FTR0_FIELD0002_MASK (0x1U << DMA_FTR0_FIELD0002_SHIFT) /* 0x40000000 */ +#define DMA_FTR0_FIELD0001_SHIFT (31U) +#define DMA_FTR0_FIELD0001_MASK (0x1U << DMA_FTR0_FIELD0001_SHIFT) /* 0x80000000 */ +/* FTR1 */ +#define DMA_FTR1_OFFSET (0x44U) +#define DMA_FTR1 (0x0U) +#define DMA_FTR1_FIELD0000_SHIFT (0U) +#define DMA_FTR1_FIELD0000_MASK (0x1U << DMA_FTR1_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_FTR1_FIELD0011_SHIFT (1U) +#define DMA_FTR1_FIELD0011_MASK (0x1U << DMA_FTR1_FIELD0011_SHIFT) /* 0x00000002 */ +#define DMA_FTR1_FIELD0010_SHIFT (5U) +#define DMA_FTR1_FIELD0010_MASK (0x1U << DMA_FTR1_FIELD0010_SHIFT) /* 0x00000020 */ +#define DMA_FTR1_FIELD0009_SHIFT (6U) +#define DMA_FTR1_FIELD0009_MASK (0x1U << DMA_FTR1_FIELD0009_SHIFT) /* 0x00000040 */ +#define DMA_FTR1_FIELD0008_SHIFT (7U) +#define DMA_FTR1_FIELD0008_MASK (0x1U << DMA_FTR1_FIELD0008_SHIFT) /* 0x00000080 */ +#define DMA_FTR1_FIELD0007_SHIFT (12U) +#define DMA_FTR1_FIELD0007_MASK (0x1U << DMA_FTR1_FIELD0007_SHIFT) /* 0x00001000 */ +#define DMA_FTR1_FIELD0006_SHIFT (13U) +#define DMA_FTR1_FIELD0006_MASK (0x1U << DMA_FTR1_FIELD0006_SHIFT) /* 0x00002000 */ +#define DMA_FTR1_FIELD0005_SHIFT (16U) +#define DMA_FTR1_FIELD0005_MASK (0x1U << DMA_FTR1_FIELD0005_SHIFT) /* 0x00010000 */ +#define DMA_FTR1_FIELD0004_SHIFT (17U) +#define DMA_FTR1_FIELD0004_MASK (0x1U << DMA_FTR1_FIELD0004_SHIFT) /* 0x00020000 */ +#define DMA_FTR1_FIELD0003_SHIFT (18U) +#define DMA_FTR1_FIELD0003_MASK (0x1U << DMA_FTR1_FIELD0003_SHIFT) /* 0x00040000 */ +#define DMA_FTR1_FIELD0002_SHIFT (30U) +#define DMA_FTR1_FIELD0002_MASK (0x1U << DMA_FTR1_FIELD0002_SHIFT) /* 0x40000000 */ +#define DMA_FTR1_FIELD0001_SHIFT (31U) +#define DMA_FTR1_FIELD0001_MASK (0x1U << DMA_FTR1_FIELD0001_SHIFT) /* 0x80000000 */ +/* FTR2 */ +#define DMA_FTR2_OFFSET (0x48U) +#define DMA_FTR2 (0x0U) +#define DMA_FTR2_FIELD0000_SHIFT (0U) +#define DMA_FTR2_FIELD0000_MASK (0x1U << DMA_FTR2_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_FTR2_FIELD0011_SHIFT (1U) +#define DMA_FTR2_FIELD0011_MASK (0x1U << DMA_FTR2_FIELD0011_SHIFT) /* 0x00000002 */ +#define DMA_FTR2_FIELD0010_SHIFT (5U) +#define DMA_FTR2_FIELD0010_MASK (0x1U << DMA_FTR2_FIELD0010_SHIFT) /* 0x00000020 */ +#define DMA_FTR2_FIELD0009_SHIFT (6U) +#define DMA_FTR2_FIELD0009_MASK (0x1U << DMA_FTR2_FIELD0009_SHIFT) /* 0x00000040 */ +#define DMA_FTR2_FIELD0008_SHIFT (7U) +#define DMA_FTR2_FIELD0008_MASK (0x1U << DMA_FTR2_FIELD0008_SHIFT) /* 0x00000080 */ +#define DMA_FTR2_FIELD0007_SHIFT (12U) +#define DMA_FTR2_FIELD0007_MASK (0x1U << DMA_FTR2_FIELD0007_SHIFT) /* 0x00001000 */ +#define DMA_FTR2_FIELD0006_SHIFT (13U) +#define DMA_FTR2_FIELD0006_MASK (0x1U << DMA_FTR2_FIELD0006_SHIFT) /* 0x00002000 */ +#define DMA_FTR2_FIELD0005_SHIFT (16U) +#define DMA_FTR2_FIELD0005_MASK (0x1U << DMA_FTR2_FIELD0005_SHIFT) /* 0x00010000 */ +#define DMA_FTR2_FIELD0004_SHIFT (17U) +#define DMA_FTR2_FIELD0004_MASK (0x1U << DMA_FTR2_FIELD0004_SHIFT) /* 0x00020000 */ +#define DMA_FTR2_FIELD0003_SHIFT (18U) +#define DMA_FTR2_FIELD0003_MASK (0x1U << DMA_FTR2_FIELD0003_SHIFT) /* 0x00040000 */ +#define DMA_FTR2_FIELD0002_SHIFT (30U) +#define DMA_FTR2_FIELD0002_MASK (0x1U << DMA_FTR2_FIELD0002_SHIFT) /* 0x40000000 */ +#define DMA_FTR2_FIELD0001_SHIFT (31U) +#define DMA_FTR2_FIELD0001_MASK (0x1U << DMA_FTR2_FIELD0001_SHIFT) /* 0x80000000 */ +/* FTR3 */ +#define DMA_FTR3_OFFSET (0x4CU) +#define DMA_FTR3 (0x0U) +#define DMA_FTR3_FIELD0000_SHIFT (0U) +#define DMA_FTR3_FIELD0000_MASK (0x1U << DMA_FTR3_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_FTR3_FIELD0011_SHIFT (1U) +#define DMA_FTR3_FIELD0011_MASK (0x1U << DMA_FTR3_FIELD0011_SHIFT) /* 0x00000002 */ +#define DMA_FTR3_FIELD0010_SHIFT (5U) +#define DMA_FTR3_FIELD0010_MASK (0x1U << DMA_FTR3_FIELD0010_SHIFT) /* 0x00000020 */ +#define DMA_FTR3_FIELD0009_SHIFT (6U) +#define DMA_FTR3_FIELD0009_MASK (0x1U << DMA_FTR3_FIELD0009_SHIFT) /* 0x00000040 */ +#define DMA_FTR3_FIELD0008_SHIFT (7U) +#define DMA_FTR3_FIELD0008_MASK (0x1U << DMA_FTR3_FIELD0008_SHIFT) /* 0x00000080 */ +#define DMA_FTR3_FIELD0007_SHIFT (12U) +#define DMA_FTR3_FIELD0007_MASK (0x1U << DMA_FTR3_FIELD0007_SHIFT) /* 0x00001000 */ +#define DMA_FTR3_FIELD0006_SHIFT (13U) +#define DMA_FTR3_FIELD0006_MASK (0x1U << DMA_FTR3_FIELD0006_SHIFT) /* 0x00002000 */ +#define DMA_FTR3_FIELD0005_SHIFT (16U) +#define DMA_FTR3_FIELD0005_MASK (0x1U << DMA_FTR3_FIELD0005_SHIFT) /* 0x00010000 */ +#define DMA_FTR3_FIELD0004_SHIFT (17U) +#define DMA_FTR3_FIELD0004_MASK (0x1U << DMA_FTR3_FIELD0004_SHIFT) /* 0x00020000 */ +#define DMA_FTR3_FIELD0003_SHIFT (18U) +#define DMA_FTR3_FIELD0003_MASK (0x1U << DMA_FTR3_FIELD0003_SHIFT) /* 0x00040000 */ +#define DMA_FTR3_FIELD0002_SHIFT (30U) +#define DMA_FTR3_FIELD0002_MASK (0x1U << DMA_FTR3_FIELD0002_SHIFT) /* 0x40000000 */ +#define DMA_FTR3_FIELD0001_SHIFT (31U) +#define DMA_FTR3_FIELD0001_MASK (0x1U << DMA_FTR3_FIELD0001_SHIFT) /* 0x80000000 */ +/* FTR4 */ +#define DMA_FTR4_OFFSET (0x50U) +#define DMA_FTR4 (0x0U) +#define DMA_FTR4_FIELD0000_SHIFT (0U) +#define DMA_FTR4_FIELD0000_MASK (0x1U << DMA_FTR4_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_FTR4_FIELD0011_SHIFT (1U) +#define DMA_FTR4_FIELD0011_MASK (0x1U << DMA_FTR4_FIELD0011_SHIFT) /* 0x00000002 */ +#define DMA_FTR4_FIELD0010_SHIFT (5U) +#define DMA_FTR4_FIELD0010_MASK (0x1U << DMA_FTR4_FIELD0010_SHIFT) /* 0x00000020 */ +#define DMA_FTR4_FIELD0009_SHIFT (6U) +#define DMA_FTR4_FIELD0009_MASK (0x1U << DMA_FTR4_FIELD0009_SHIFT) /* 0x00000040 */ +#define DMA_FTR4_FIELD0008_SHIFT (7U) +#define DMA_FTR4_FIELD0008_MASK (0x1U << DMA_FTR4_FIELD0008_SHIFT) /* 0x00000080 */ +#define DMA_FTR4_FIELD0007_SHIFT (12U) +#define DMA_FTR4_FIELD0007_MASK (0x1U << DMA_FTR4_FIELD0007_SHIFT) /* 0x00001000 */ +#define DMA_FTR4_FIELD0006_SHIFT (13U) +#define DMA_FTR4_FIELD0006_MASK (0x1U << DMA_FTR4_FIELD0006_SHIFT) /* 0x00002000 */ +#define DMA_FTR4_FIELD0005_SHIFT (16U) +#define DMA_FTR4_FIELD0005_MASK (0x1U << DMA_FTR4_FIELD0005_SHIFT) /* 0x00010000 */ +#define DMA_FTR4_FIELD0004_SHIFT (17U) +#define DMA_FTR4_FIELD0004_MASK (0x1U << DMA_FTR4_FIELD0004_SHIFT) /* 0x00020000 */ +#define DMA_FTR4_FIELD0003_SHIFT (18U) +#define DMA_FTR4_FIELD0003_MASK (0x1U << DMA_FTR4_FIELD0003_SHIFT) /* 0x00040000 */ +#define DMA_FTR4_FIELD0002_SHIFT (30U) +#define DMA_FTR4_FIELD0002_MASK (0x1U << DMA_FTR4_FIELD0002_SHIFT) /* 0x40000000 */ +#define DMA_FTR4_FIELD0001_SHIFT (31U) +#define DMA_FTR4_FIELD0001_MASK (0x1U << DMA_FTR4_FIELD0001_SHIFT) /* 0x80000000 */ +/* FTR5 */ +#define DMA_FTR5_OFFSET (0x54U) +#define DMA_FTR5 (0x0U) +#define DMA_FTR5_FIELD0000_SHIFT (0U) +#define DMA_FTR5_FIELD0000_MASK (0x1U << DMA_FTR5_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_FTR5_FIELD0011_SHIFT (1U) +#define DMA_FTR5_FIELD0011_MASK (0x1U << DMA_FTR5_FIELD0011_SHIFT) /* 0x00000002 */ +#define DMA_FTR5_FIELD0010_SHIFT (5U) +#define DMA_FTR5_FIELD0010_MASK (0x1U << DMA_FTR5_FIELD0010_SHIFT) /* 0x00000020 */ +#define DMA_FTR5_FIELD0009_SHIFT (6U) +#define DMA_FTR5_FIELD0009_MASK (0x1U << DMA_FTR5_FIELD0009_SHIFT) /* 0x00000040 */ +#define DMA_FTR5_FIELD0008_SHIFT (7U) +#define DMA_FTR5_FIELD0008_MASK (0x1U << DMA_FTR5_FIELD0008_SHIFT) /* 0x00000080 */ +#define DMA_FTR5_FIELD0007_SHIFT (12U) +#define DMA_FTR5_FIELD0007_MASK (0x1U << DMA_FTR5_FIELD0007_SHIFT) /* 0x00001000 */ +#define DMA_FTR5_FIELD0006_SHIFT (13U) +#define DMA_FTR5_FIELD0006_MASK (0x1U << DMA_FTR5_FIELD0006_SHIFT) /* 0x00002000 */ +#define DMA_FTR5_FIELD0005_SHIFT (16U) +#define DMA_FTR5_FIELD0005_MASK (0x1U << DMA_FTR5_FIELD0005_SHIFT) /* 0x00010000 */ +#define DMA_FTR5_FIELD0004_SHIFT (17U) +#define DMA_FTR5_FIELD0004_MASK (0x1U << DMA_FTR5_FIELD0004_SHIFT) /* 0x00020000 */ +#define DMA_FTR5_FIELD0003_SHIFT (18U) +#define DMA_FTR5_FIELD0003_MASK (0x1U << DMA_FTR5_FIELD0003_SHIFT) /* 0x00040000 */ +#define DMA_FTR5_FIELD0002_SHIFT (30U) +#define DMA_FTR5_FIELD0002_MASK (0x1U << DMA_FTR5_FIELD0002_SHIFT) /* 0x40000000 */ +#define DMA_FTR5_FIELD0001_SHIFT (31U) +#define DMA_FTR5_FIELD0001_MASK (0x1U << DMA_FTR5_FIELD0001_SHIFT) /* 0x80000000 */ +/* CSR0 */ +#define DMA_CSR0_OFFSET (0x100U) +#define DMA_CSR0 (0x0U) +#define DMA_CSR0_FIELD0000_SHIFT (0U) +#define DMA_CSR0_FIELD0000_MASK (0xFU << DMA_CSR0_FIELD0000_SHIFT) /* 0x0000000F */ +#define DMA_CSR0_FIELD0004_SHIFT (4U) +#define DMA_CSR0_FIELD0004_MASK (0x1FU << DMA_CSR0_FIELD0004_SHIFT) /* 0x000001F0 */ +#define DMA_CSR0_FIELD0003_SHIFT (14U) +#define DMA_CSR0_FIELD0003_MASK (0x1U << DMA_CSR0_FIELD0003_SHIFT) /* 0x00004000 */ +#define DMA_CSR0_FIELD0002_SHIFT (15U) +#define DMA_CSR0_FIELD0002_MASK (0x1U << DMA_CSR0_FIELD0002_SHIFT) /* 0x00008000 */ +#define DMA_CSR0_FIELD0001_SHIFT (21U) +#define DMA_CSR0_FIELD0001_MASK (0x1U << DMA_CSR0_FIELD0001_SHIFT) /* 0x00200000 */ +/* CPC0 */ +#define DMA_CPC0_OFFSET (0x104U) +#define DMA_CPC0 (0x0U) +#define DMA_CPC0_FIELD0000_SHIFT (0U) +#define DMA_CPC0_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC0_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CSR1 */ +#define DMA_CSR1_OFFSET (0x108U) +#define DMA_CSR1 (0x0U) +#define DMA_CSR1_FIELD0000_SHIFT (0U) +#define DMA_CSR1_FIELD0000_MASK (0xFU << DMA_CSR1_FIELD0000_SHIFT) /* 0x0000000F */ +#define DMA_CSR1_FIELD0004_SHIFT (4U) +#define DMA_CSR1_FIELD0004_MASK (0x1FU << DMA_CSR1_FIELD0004_SHIFT) /* 0x000001F0 */ +#define DMA_CSR1_FIELD0003_SHIFT (14U) +#define DMA_CSR1_FIELD0003_MASK (0x1U << DMA_CSR1_FIELD0003_SHIFT) /* 0x00004000 */ +#define DMA_CSR1_FIELD0002_SHIFT (15U) +#define DMA_CSR1_FIELD0002_MASK (0x1U << DMA_CSR1_FIELD0002_SHIFT) /* 0x00008000 */ +#define DMA_CSR1_FIELD0001_SHIFT (21U) +#define DMA_CSR1_FIELD0001_MASK (0x1U << DMA_CSR1_FIELD0001_SHIFT) /* 0x00200000 */ +/* CPC1 */ +#define DMA_CPC1_OFFSET (0x10CU) +#define DMA_CPC1 (0x0U) +#define DMA_CPC1_FIELD0000_SHIFT (0U) +#define DMA_CPC1_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC1_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CSR2 */ +#define DMA_CSR2_OFFSET (0x110U) +#define DMA_CSR2 (0x0U) +#define DMA_CSR2_FIELD0000_SHIFT (0U) +#define DMA_CSR2_FIELD0000_MASK (0xFU << DMA_CSR2_FIELD0000_SHIFT) /* 0x0000000F */ +#define DMA_CSR2_FIELD0004_SHIFT (4U) +#define DMA_CSR2_FIELD0004_MASK (0x1FU << DMA_CSR2_FIELD0004_SHIFT) /* 0x000001F0 */ +#define DMA_CSR2_FIELD0003_SHIFT (14U) +#define DMA_CSR2_FIELD0003_MASK (0x1U << DMA_CSR2_FIELD0003_SHIFT) /* 0x00004000 */ +#define DMA_CSR2_FIELD0002_SHIFT (15U) +#define DMA_CSR2_FIELD0002_MASK (0x1U << DMA_CSR2_FIELD0002_SHIFT) /* 0x00008000 */ +#define DMA_CSR2_FIELD0001_SHIFT (21U) +#define DMA_CSR2_FIELD0001_MASK (0x1U << DMA_CSR2_FIELD0001_SHIFT) /* 0x00200000 */ +/* CPC2 */ +#define DMA_CPC2_OFFSET (0x114U) +#define DMA_CPC2 (0x0U) +#define DMA_CPC2_FIELD0000_SHIFT (0U) +#define DMA_CPC2_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC2_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CSR3 */ +#define DMA_CSR3_OFFSET (0x118U) +#define DMA_CSR3 (0x0U) +#define DMA_CSR3_FIELD0000_SHIFT (0U) +#define DMA_CSR3_FIELD0000_MASK (0xFU << DMA_CSR3_FIELD0000_SHIFT) /* 0x0000000F */ +#define DMA_CSR3_FIELD0004_SHIFT (4U) +#define DMA_CSR3_FIELD0004_MASK (0x1FU << DMA_CSR3_FIELD0004_SHIFT) /* 0x000001F0 */ +#define DMA_CSR3_FIELD0003_SHIFT (14U) +#define DMA_CSR3_FIELD0003_MASK (0x1U << DMA_CSR3_FIELD0003_SHIFT) /* 0x00004000 */ +#define DMA_CSR3_FIELD0002_SHIFT (15U) +#define DMA_CSR3_FIELD0002_MASK (0x1U << DMA_CSR3_FIELD0002_SHIFT) /* 0x00008000 */ +#define DMA_CSR3_FIELD0001_SHIFT (21U) +#define DMA_CSR3_FIELD0001_MASK (0x1U << DMA_CSR3_FIELD0001_SHIFT) /* 0x00200000 */ +/* CPC3 */ +#define DMA_CPC3_OFFSET (0x11CU) +#define DMA_CPC3 (0x0U) +#define DMA_CPC3_FIELD0000_SHIFT (0U) +#define DMA_CPC3_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC3_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CSR4 */ +#define DMA_CSR4_OFFSET (0x120U) +#define DMA_CSR4 (0x0U) +#define DMA_CSR4_FIELD0000_SHIFT (0U) +#define DMA_CSR4_FIELD0000_MASK (0xFU << DMA_CSR4_FIELD0000_SHIFT) /* 0x0000000F */ +#define DMA_CSR4_FIELD0004_SHIFT (4U) +#define DMA_CSR4_FIELD0004_MASK (0x1FU << DMA_CSR4_FIELD0004_SHIFT) /* 0x000001F0 */ +#define DMA_CSR4_FIELD0003_SHIFT (14U) +#define DMA_CSR4_FIELD0003_MASK (0x1U << DMA_CSR4_FIELD0003_SHIFT) /* 0x00004000 */ +#define DMA_CSR4_FIELD0002_SHIFT (15U) +#define DMA_CSR4_FIELD0002_MASK (0x1U << DMA_CSR4_FIELD0002_SHIFT) /* 0x00008000 */ +#define DMA_CSR4_FIELD0001_SHIFT (21U) +#define DMA_CSR4_FIELD0001_MASK (0x1U << DMA_CSR4_FIELD0001_SHIFT) /* 0x00200000 */ +/* CPC4 */ +#define DMA_CPC4_OFFSET (0x124U) +#define DMA_CPC4 (0x0U) +#define DMA_CPC4_FIELD0000_SHIFT (0U) +#define DMA_CPC4_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC4_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CSR5 */ +#define DMA_CSR5_OFFSET (0x128U) +#define DMA_CSR5 (0x0U) +#define DMA_CSR5_FIELD0000_SHIFT (0U) +#define DMA_CSR5_FIELD0000_MASK (0xFU << DMA_CSR5_FIELD0000_SHIFT) /* 0x0000000F */ +#define DMA_CSR5_FIELD0004_SHIFT (4U) +#define DMA_CSR5_FIELD0004_MASK (0x1FU << DMA_CSR5_FIELD0004_SHIFT) /* 0x000001F0 */ +#define DMA_CSR5_FIELD0003_SHIFT (14U) +#define DMA_CSR5_FIELD0003_MASK (0x1U << DMA_CSR5_FIELD0003_SHIFT) /* 0x00004000 */ +#define DMA_CSR5_FIELD0002_SHIFT (15U) +#define DMA_CSR5_FIELD0002_MASK (0x1U << DMA_CSR5_FIELD0002_SHIFT) /* 0x00008000 */ +#define DMA_CSR5_FIELD0001_SHIFT (21U) +#define DMA_CSR5_FIELD0001_MASK (0x1U << DMA_CSR5_FIELD0001_SHIFT) /* 0x00200000 */ +/* CPC5 */ +#define DMA_CPC5_OFFSET (0x12CU) +#define DMA_CPC5 (0x0U) +#define DMA_CPC5_FIELD0000_SHIFT (0U) +#define DMA_CPC5_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC5_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CSR6 */ +#define DMA_CSR6_OFFSET (0x130U) +#define DMA_CSR6 (0x0U) +#define DMA_CSR6_FIELD0000_SHIFT (0U) +#define DMA_CSR6_FIELD0000_MASK (0xFU << DMA_CSR6_FIELD0000_SHIFT) /* 0x0000000F */ +#define DMA_CSR6_FIELD0004_SHIFT (4U) +#define DMA_CSR6_FIELD0004_MASK (0x1FU << DMA_CSR6_FIELD0004_SHIFT) /* 0x000001F0 */ +#define DMA_CSR6_FIELD0003_SHIFT (14U) +#define DMA_CSR6_FIELD0003_MASK (0x1U << DMA_CSR6_FIELD0003_SHIFT) /* 0x00004000 */ +#define DMA_CSR6_FIELD0002_SHIFT (15U) +#define DMA_CSR6_FIELD0002_MASK (0x1U << DMA_CSR6_FIELD0002_SHIFT) /* 0x00008000 */ +#define DMA_CSR6_FIELD0001_SHIFT (21U) +#define DMA_CSR6_FIELD0001_MASK (0x1U << DMA_CSR6_FIELD0001_SHIFT) /* 0x00200000 */ +/* CPC6 */ +#define DMA_CPC6_OFFSET (0x134U) +#define DMA_CPC6 (0x0U) +#define DMA_CPC6_FIELD0000_SHIFT (0U) +#define DMA_CPC6_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC6_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CSR7 */ +#define DMA_CSR7_OFFSET (0x138U) +#define DMA_CSR7 (0x0U) +#define DMA_CSR7_FIELD0000_SHIFT (0U) +#define DMA_CSR7_FIELD0000_MASK (0xFU << DMA_CSR7_FIELD0000_SHIFT) /* 0x0000000F */ +#define DMA_CSR7_FIELD0004_SHIFT (4U) +#define DMA_CSR7_FIELD0004_MASK (0x1FU << DMA_CSR7_FIELD0004_SHIFT) /* 0x000001F0 */ +#define DMA_CSR7_FIELD0003_SHIFT (14U) +#define DMA_CSR7_FIELD0003_MASK (0x1U << DMA_CSR7_FIELD0003_SHIFT) /* 0x00004000 */ +#define DMA_CSR7_FIELD0002_SHIFT (15U) +#define DMA_CSR7_FIELD0002_MASK (0x1U << DMA_CSR7_FIELD0002_SHIFT) /* 0x00008000 */ +#define DMA_CSR7_FIELD0001_SHIFT (21U) +#define DMA_CSR7_FIELD0001_MASK (0x1U << DMA_CSR7_FIELD0001_SHIFT) /* 0x00200000 */ +/* CPC7 */ +#define DMA_CPC7_OFFSET (0x13CU) +#define DMA_CPC7 (0x0U) +#define DMA_CPC7_FIELD0000_SHIFT (0U) +#define DMA_CPC7_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC7_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* SAR0 */ +#define DMA_SAR0_OFFSET (0x400U) +#define DMA_SAR0 (0x0U) +#define DMA_SAR0_FIELD0000_SHIFT (0U) +#define DMA_SAR0_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR0_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* DAR0 */ +#define DMA_DAR0_OFFSET (0x404U) +#define DMA_DAR0 (0x0U) +#define DMA_DAR0_FIELD0000_SHIFT (0U) +#define DMA_DAR0_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR0_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CCR0 */ +#define DMA_CCR0_OFFSET (0x408U) +#define DMA_CCR0 (0x0U) +#define DMA_CCR0_FIELD0000_SHIFT (0U) +#define DMA_CCR0_FIELD0000_MASK (0x1U << DMA_CCR0_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_CCR0_FIELD0009_SHIFT (1U) +#define DMA_CCR0_FIELD0009_MASK (0x7U << DMA_CCR0_FIELD0009_SHIFT) /* 0x0000000E */ +#define DMA_CCR0_FIELD0008_SHIFT (4U) +#define DMA_CCR0_FIELD0008_MASK (0xFU << DMA_CCR0_FIELD0008_SHIFT) /* 0x000000F0 */ +#define DMA_CCR0_FIELD0007_SHIFT (8U) +#define DMA_CCR0_FIELD0007_MASK (0x7U << DMA_CCR0_FIELD0007_SHIFT) /* 0x00000700 */ +#define DMA_CCR0_FIELD0006_SHIFT (11U) +#define DMA_CCR0_FIELD0006_MASK (0x7U << DMA_CCR0_FIELD0006_SHIFT) /* 0x00003800 */ +#define DMA_CCR0_FIELD0005_SHIFT (14U) +#define DMA_CCR0_FIELD0005_MASK (0x1U << DMA_CCR0_FIELD0005_SHIFT) /* 0x00004000 */ +#define DMA_CCR0_FIELD0004_SHIFT (15U) +#define DMA_CCR0_FIELD0004_MASK (0x7U << DMA_CCR0_FIELD0004_SHIFT) /* 0x00038000 */ +#define DMA_CCR0_FIELD0003_SHIFT (18U) +#define DMA_CCR0_FIELD0003_MASK (0xFU << DMA_CCR0_FIELD0003_SHIFT) /* 0x003C0000 */ +#define DMA_CCR0_FIELD0002_SHIFT (22U) +#define DMA_CCR0_FIELD0002_MASK (0x7U << DMA_CCR0_FIELD0002_SHIFT) /* 0x01C00000 */ +#define DMA_CCR0_FIELD0001_SHIFT (25U) +#define DMA_CCR0_FIELD0001_MASK (0x7U << DMA_CCR0_FIELD0001_SHIFT) /* 0x0E000000 */ +/* LC0_0 */ +#define DMA_LC0_0_OFFSET (0x40CU) +#define DMA_LC0_0 (0x0U) +#define DMA_LC0_0_FIELD0000_SHIFT (0U) +#define DMA_LC0_0_FIELD0000_MASK (0xFFU << DMA_LC0_0_FIELD0000_SHIFT) /* 0x000000FF */ +/* LC1_0 */ +#define DMA_LC1_0_OFFSET (0x410U) +#define DMA_LC1_0 (0x0U) +#define DMA_LC1_0_FIELD0000_SHIFT (0U) +#define DMA_LC1_0_FIELD0000_MASK (0xFFU << DMA_LC1_0_FIELD0000_SHIFT) /* 0x000000FF */ +/* PADDING0_0 */ +#define DMA_PADDING0_0_OFFSET (0x414U) +/* PADDING0_1 */ +#define DMA_PADDING0_1_OFFSET (0x418U) +/* PADDING0_2 */ +#define DMA_PADDING0_2_OFFSET (0x41CU) +/* SAR1 */ +#define DMA_SAR1_OFFSET (0x420U) +#define DMA_SAR1 (0x0U) +#define DMA_SAR1_FIELD0000_SHIFT (0U) +#define DMA_SAR1_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR1_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* DAR1 */ +#define DMA_DAR1_OFFSET (0x424U) +#define DMA_DAR1 (0x0U) +#define DMA_DAR1_FIELD0000_SHIFT (0U) +#define DMA_DAR1_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR1_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CCR1 */ +#define DMA_CCR1_OFFSET (0x428U) +#define DMA_CCR1 (0x0U) +#define DMA_CCR1_FIELD0000_SHIFT (0U) +#define DMA_CCR1_FIELD0000_MASK (0x1U << DMA_CCR1_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_CCR1_FIELD0009_SHIFT (1U) +#define DMA_CCR1_FIELD0009_MASK (0x7U << DMA_CCR1_FIELD0009_SHIFT) /* 0x0000000E */ +#define DMA_CCR1_FIELD0008_SHIFT (4U) +#define DMA_CCR1_FIELD0008_MASK (0xFU << DMA_CCR1_FIELD0008_SHIFT) /* 0x000000F0 */ +#define DMA_CCR1_FIELD0007_SHIFT (8U) +#define DMA_CCR1_FIELD0007_MASK (0x7U << DMA_CCR1_FIELD0007_SHIFT) /* 0x00000700 */ +#define DMA_CCR1_FIELD0006_SHIFT (11U) +#define DMA_CCR1_FIELD0006_MASK (0x7U << DMA_CCR1_FIELD0006_SHIFT) /* 0x00003800 */ +#define DMA_CCR1_FIELD0005_SHIFT (14U) +#define DMA_CCR1_FIELD0005_MASK (0x1U << DMA_CCR1_FIELD0005_SHIFT) /* 0x00004000 */ +#define DMA_CCR1_FIELD0004_SHIFT (15U) +#define DMA_CCR1_FIELD0004_MASK (0x7U << DMA_CCR1_FIELD0004_SHIFT) /* 0x00038000 */ +#define DMA_CCR1_FIELD0003_SHIFT (18U) +#define DMA_CCR1_FIELD0003_MASK (0xFU << DMA_CCR1_FIELD0003_SHIFT) /* 0x003C0000 */ +#define DMA_CCR1_FIELD0002_SHIFT (22U) +#define DMA_CCR1_FIELD0002_MASK (0x7U << DMA_CCR1_FIELD0002_SHIFT) /* 0x01C00000 */ +#define DMA_CCR1_FIELD0001_SHIFT (25U) +#define DMA_CCR1_FIELD0001_MASK (0x7U << DMA_CCR1_FIELD0001_SHIFT) /* 0x0E000000 */ +/* LC0_1 */ +#define DMA_LC0_1_OFFSET (0x42CU) +#define DMA_LC0_1 (0x0U) +#define DMA_LC0_1_FIELD0000_SHIFT (0U) +#define DMA_LC0_1_FIELD0000_MASK (0xFFU << DMA_LC0_1_FIELD0000_SHIFT) /* 0x000000FF */ +/* LC1_1 */ +#define DMA_LC1_1_OFFSET (0x430U) +#define DMA_LC1_1 (0x0U) +#define DMA_LC1_1_FIELD0000_SHIFT (0U) +#define DMA_LC1_1_FIELD0000_MASK (0xFFU << DMA_LC1_1_FIELD0000_SHIFT) /* 0x000000FF */ +/* PADDING1_0 */ +#define DMA_PADDING1_0_OFFSET (0x434U) +/* PADDING1_1 */ +#define DMA_PADDING1_1_OFFSET (0x438U) +/* PADDING1_2 */ +#define DMA_PADDING1_2_OFFSET (0x43CU) +/* SAR2 */ +#define DMA_SAR2_OFFSET (0x440U) +#define DMA_SAR2 (0x0U) +#define DMA_SAR2_FIELD0000_SHIFT (0U) +#define DMA_SAR2_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR2_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* DAR2 */ +#define DMA_DAR2_OFFSET (0x444U) +#define DMA_DAR2 (0x0U) +#define DMA_DAR2_FIELD0000_SHIFT (0U) +#define DMA_DAR2_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR2_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CCR2 */ +#define DMA_CCR2_OFFSET (0x448U) +#define DMA_CCR2 (0x0U) +#define DMA_CCR2_FIELD0000_SHIFT (0U) +#define DMA_CCR2_FIELD0000_MASK (0x1U << DMA_CCR2_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_CCR2_FIELD0009_SHIFT (1U) +#define DMA_CCR2_FIELD0009_MASK (0x7U << DMA_CCR2_FIELD0009_SHIFT) /* 0x0000000E */ +#define DMA_CCR2_FIELD0008_SHIFT (4U) +#define DMA_CCR2_FIELD0008_MASK (0xFU << DMA_CCR2_FIELD0008_SHIFT) /* 0x000000F0 */ +#define DMA_CCR2_FIELD0007_SHIFT (8U) +#define DMA_CCR2_FIELD0007_MASK (0x7U << DMA_CCR2_FIELD0007_SHIFT) /* 0x00000700 */ +#define DMA_CCR2_FIELD0006_SHIFT (11U) +#define DMA_CCR2_FIELD0006_MASK (0x7U << DMA_CCR2_FIELD0006_SHIFT) /* 0x00003800 */ +#define DMA_CCR2_FIELD0005_SHIFT (14U) +#define DMA_CCR2_FIELD0005_MASK (0x1U << DMA_CCR2_FIELD0005_SHIFT) /* 0x00004000 */ +#define DMA_CCR2_FIELD0004_SHIFT (15U) +#define DMA_CCR2_FIELD0004_MASK (0x7U << DMA_CCR2_FIELD0004_SHIFT) /* 0x00038000 */ +#define DMA_CCR2_FIELD0003_SHIFT (18U) +#define DMA_CCR2_FIELD0003_MASK (0xFU << DMA_CCR2_FIELD0003_SHIFT) /* 0x003C0000 */ +#define DMA_CCR2_FIELD0002_SHIFT (22U) +#define DMA_CCR2_FIELD0002_MASK (0x7U << DMA_CCR2_FIELD0002_SHIFT) /* 0x01C00000 */ +#define DMA_CCR2_FIELD0001_SHIFT (25U) +#define DMA_CCR2_FIELD0001_MASK (0x7U << DMA_CCR2_FIELD0001_SHIFT) /* 0x0E000000 */ +/* LC0_2 */ +#define DMA_LC0_2_OFFSET (0x44CU) +#define DMA_LC0_2 (0x0U) +#define DMA_LC0_2_FIELD0000_SHIFT (0U) +#define DMA_LC0_2_FIELD0000_MASK (0xFFU << DMA_LC0_2_FIELD0000_SHIFT) /* 0x000000FF */ +/* LC1_2 */ +#define DMA_LC1_2_OFFSET (0x450U) +#define DMA_LC1_2 (0x0U) +#define DMA_LC1_2_FIELD0000_SHIFT (0U) +#define DMA_LC1_2_FIELD0000_MASK (0xFFU << DMA_LC1_2_FIELD0000_SHIFT) /* 0x000000FF */ +/* PADDING2_0 */ +#define DMA_PADDING2_0_OFFSET (0x454U) +/* PADDING2_1 */ +#define DMA_PADDING2_1_OFFSET (0x458U) +/* PADDING2_2 */ +#define DMA_PADDING2_2_OFFSET (0x45CU) +/* SAR3 */ +#define DMA_SAR3_OFFSET (0x460U) +#define DMA_SAR3 (0x0U) +#define DMA_SAR3_FIELD0000_SHIFT (0U) +#define DMA_SAR3_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR3_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* DAR3 */ +#define DMA_DAR3_OFFSET (0x464U) +#define DMA_DAR3 (0x0U) +#define DMA_DAR3_FIELD0000_SHIFT (0U) +#define DMA_DAR3_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR3_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CCR3 */ +#define DMA_CCR3_OFFSET (0x468U) +#define DMA_CCR3 (0x0U) +#define DMA_CCR3_FIELD0000_SHIFT (0U) +#define DMA_CCR3_FIELD0000_MASK (0x1U << DMA_CCR3_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_CCR3_FIELD0009_SHIFT (1U) +#define DMA_CCR3_FIELD0009_MASK (0x7U << DMA_CCR3_FIELD0009_SHIFT) /* 0x0000000E */ +#define DMA_CCR3_FIELD0008_SHIFT (4U) +#define DMA_CCR3_FIELD0008_MASK (0xFU << DMA_CCR3_FIELD0008_SHIFT) /* 0x000000F0 */ +#define DMA_CCR3_FIELD0007_SHIFT (8U) +#define DMA_CCR3_FIELD0007_MASK (0x7U << DMA_CCR3_FIELD0007_SHIFT) /* 0x00000700 */ +#define DMA_CCR3_FIELD0006_SHIFT (11U) +#define DMA_CCR3_FIELD0006_MASK (0x7U << DMA_CCR3_FIELD0006_SHIFT) /* 0x00003800 */ +#define DMA_CCR3_FIELD0005_SHIFT (14U) +#define DMA_CCR3_FIELD0005_MASK (0x1U << DMA_CCR3_FIELD0005_SHIFT) /* 0x00004000 */ +#define DMA_CCR3_FIELD0004_SHIFT (15U) +#define DMA_CCR3_FIELD0004_MASK (0x7U << DMA_CCR3_FIELD0004_SHIFT) /* 0x00038000 */ +#define DMA_CCR3_FIELD0003_SHIFT (18U) +#define DMA_CCR3_FIELD0003_MASK (0xFU << DMA_CCR3_FIELD0003_SHIFT) /* 0x003C0000 */ +#define DMA_CCR3_FIELD0002_SHIFT (22U) +#define DMA_CCR3_FIELD0002_MASK (0x7U << DMA_CCR3_FIELD0002_SHIFT) /* 0x01C00000 */ +#define DMA_CCR3_FIELD0001_SHIFT (25U) +#define DMA_CCR3_FIELD0001_MASK (0x7U << DMA_CCR3_FIELD0001_SHIFT) /* 0x0E000000 */ +/* LC0_3 */ +#define DMA_LC0_3_OFFSET (0x46CU) +#define DMA_LC0_3 (0x0U) +#define DMA_LC0_3_FIELD0000_SHIFT (0U) +#define DMA_LC0_3_FIELD0000_MASK (0xFFU << DMA_LC0_3_FIELD0000_SHIFT) /* 0x000000FF */ +/* LC1_3 */ +#define DMA_LC1_3_OFFSET (0x470U) +#define DMA_LC1_3 (0x0U) +#define DMA_LC1_3_FIELD0000_SHIFT (0U) +#define DMA_LC1_3_FIELD0000_MASK (0xFFU << DMA_LC1_3_FIELD0000_SHIFT) /* 0x000000FF */ +/* PADDING3_0 */ +#define DMA_PADDING3_0_OFFSET (0x474U) +/* PADDING3_1 */ +#define DMA_PADDING3_1_OFFSET (0x478U) +/* PADDING3_2 */ +#define DMA_PADDING3_2_OFFSET (0x47CU) +/* SAR4 */ +#define DMA_SAR4_OFFSET (0x480U) +#define DMA_SAR4 (0x0U) +#define DMA_SAR4_FIELD0000_SHIFT (0U) +#define DMA_SAR4_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR4_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* DAR4 */ +#define DMA_DAR4_OFFSET (0x484U) +#define DMA_DAR4 (0x0U) +#define DMA_DAR4_FIELD0000_SHIFT (0U) +#define DMA_DAR4_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR4_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CCR4 */ +#define DMA_CCR4_OFFSET (0x488U) +#define DMA_CCR4 (0x0U) +#define DMA_CCR4_FIELD0000_SHIFT (0U) +#define DMA_CCR4_FIELD0000_MASK (0x1U << DMA_CCR4_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_CCR4_FIELD0009_SHIFT (1U) +#define DMA_CCR4_FIELD0009_MASK (0x7U << DMA_CCR4_FIELD0009_SHIFT) /* 0x0000000E */ +#define DMA_CCR4_FIELD0008_SHIFT (4U) +#define DMA_CCR4_FIELD0008_MASK (0xFU << DMA_CCR4_FIELD0008_SHIFT) /* 0x000000F0 */ +#define DMA_CCR4_FIELD0007_SHIFT (8U) +#define DMA_CCR4_FIELD0007_MASK (0x7U << DMA_CCR4_FIELD0007_SHIFT) /* 0x00000700 */ +#define DMA_CCR4_FIELD0006_SHIFT (11U) +#define DMA_CCR4_FIELD0006_MASK (0x7U << DMA_CCR4_FIELD0006_SHIFT) /* 0x00003800 */ +#define DMA_CCR4_FIELD0005_SHIFT (14U) +#define DMA_CCR4_FIELD0005_MASK (0x1U << DMA_CCR4_FIELD0005_SHIFT) /* 0x00004000 */ +#define DMA_CCR4_FIELD0004_SHIFT (15U) +#define DMA_CCR4_FIELD0004_MASK (0x7U << DMA_CCR4_FIELD0004_SHIFT) /* 0x00038000 */ +#define DMA_CCR4_FIELD0003_SHIFT (18U) +#define DMA_CCR4_FIELD0003_MASK (0xFU << DMA_CCR4_FIELD0003_SHIFT) /* 0x003C0000 */ +#define DMA_CCR4_FIELD0002_SHIFT (22U) +#define DMA_CCR4_FIELD0002_MASK (0x7U << DMA_CCR4_FIELD0002_SHIFT) /* 0x01C00000 */ +#define DMA_CCR4_FIELD0001_SHIFT (25U) +#define DMA_CCR4_FIELD0001_MASK (0x7U << DMA_CCR4_FIELD0001_SHIFT) /* 0x0E000000 */ +/* LC0_4 */ +#define DMA_LC0_4_OFFSET (0x48CU) +#define DMA_LC0_4 (0x0U) +#define DMA_LC0_4_FIELD0000_SHIFT (0U) +#define DMA_LC0_4_FIELD0000_MASK (0xFFU << DMA_LC0_4_FIELD0000_SHIFT) /* 0x000000FF */ +/* LC1_4 */ +#define DMA_LC1_4_OFFSET (0x490U) +#define DMA_LC1_4 (0x0U) +#define DMA_LC1_4_FIELD0000_SHIFT (0U) +#define DMA_LC1_4_FIELD0000_MASK (0xFFU << DMA_LC1_4_FIELD0000_SHIFT) /* 0x000000FF */ +/* PADDING4_0 */ +#define DMA_PADDING4_0_OFFSET (0x494U) +/* PADDING4_1 */ +#define DMA_PADDING4_1_OFFSET (0x498U) +/* PADDING4_2 */ +#define DMA_PADDING4_2_OFFSET (0x49CU) +/* SAR5 */ +#define DMA_SAR5_OFFSET (0x4A0U) +#define DMA_SAR5 (0x0U) +#define DMA_SAR5_FIELD0000_SHIFT (0U) +#define DMA_SAR5_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR5_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* DAR5 */ +#define DMA_DAR5_OFFSET (0x4A4U) +#define DMA_DAR5 (0x0U) +#define DMA_DAR5_FIELD0000_SHIFT (0U) +#define DMA_DAR5_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR5_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CCR5 */ +#define DMA_CCR5_OFFSET (0x4A8U) +#define DMA_CCR5 (0x0U) +#define DMA_CCR5_FIELD0000_SHIFT (0U) +#define DMA_CCR5_FIELD0000_MASK (0x1U << DMA_CCR5_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_CCR5_FIELD0009_SHIFT (1U) +#define DMA_CCR5_FIELD0009_MASK (0x7U << DMA_CCR5_FIELD0009_SHIFT) /* 0x0000000E */ +#define DMA_CCR5_FIELD0008_SHIFT (4U) +#define DMA_CCR5_FIELD0008_MASK (0xFU << DMA_CCR5_FIELD0008_SHIFT) /* 0x000000F0 */ +#define DMA_CCR5_FIELD0007_SHIFT (8U) +#define DMA_CCR5_FIELD0007_MASK (0x7U << DMA_CCR5_FIELD0007_SHIFT) /* 0x00000700 */ +#define DMA_CCR5_FIELD0006_SHIFT (11U) +#define DMA_CCR5_FIELD0006_MASK (0x7U << DMA_CCR5_FIELD0006_SHIFT) /* 0x00003800 */ +#define DMA_CCR5_FIELD0005_SHIFT (14U) +#define DMA_CCR5_FIELD0005_MASK (0x1U << DMA_CCR5_FIELD0005_SHIFT) /* 0x00004000 */ +#define DMA_CCR5_FIELD0004_SHIFT (15U) +#define DMA_CCR5_FIELD0004_MASK (0x7U << DMA_CCR5_FIELD0004_SHIFT) /* 0x00038000 */ +#define DMA_CCR5_FIELD0003_SHIFT (18U) +#define DMA_CCR5_FIELD0003_MASK (0xFU << DMA_CCR5_FIELD0003_SHIFT) /* 0x003C0000 */ +#define DMA_CCR5_FIELD0002_SHIFT (22U) +#define DMA_CCR5_FIELD0002_MASK (0x7U << DMA_CCR5_FIELD0002_SHIFT) /* 0x01C00000 */ +#define DMA_CCR5_FIELD0001_SHIFT (25U) +#define DMA_CCR5_FIELD0001_MASK (0x7U << DMA_CCR5_FIELD0001_SHIFT) /* 0x0E000000 */ +/* LC0_5 */ +#define DMA_LC0_5_OFFSET (0x4ACU) +#define DMA_LC0_5 (0x0U) +#define DMA_LC0_5_FIELD0000_SHIFT (0U) +#define DMA_LC0_5_FIELD0000_MASK (0xFFU << DMA_LC0_5_FIELD0000_SHIFT) /* 0x000000FF */ +/* LC1_5 */ +#define DMA_LC1_5_OFFSET (0x4B0U) +#define DMA_LC1_5 (0x0U) +#define DMA_LC1_5_FIELD0000_SHIFT (0U) +#define DMA_LC1_5_FIELD0000_MASK (0xFFU << DMA_LC1_5_FIELD0000_SHIFT) /* 0x000000FF */ +/* PADDING5_0 */ +#define DMA_PADDING5_0_OFFSET (0x4B4U) +/* PADDING5_1 */ +#define DMA_PADDING5_1_OFFSET (0x4B8U) +/* PADDING5_2 */ +#define DMA_PADDING5_2_OFFSET (0x4BCU) +/* SAR6 */ +#define DMA_SAR6_OFFSET (0x4C0U) +#define DMA_SAR6 (0x0U) +#define DMA_SAR6_FIELD0000_SHIFT (0U) +#define DMA_SAR6_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR6_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* DAR6 */ +#define DMA_DAR6_OFFSET (0x4C4U) +#define DMA_DAR6 (0x0U) +#define DMA_DAR6_FIELD0000_SHIFT (0U) +#define DMA_DAR6_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR6_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CCR6 */ +#define DMA_CCR6_OFFSET (0x4C8U) +#define DMA_CCR6 (0x0U) +#define DMA_CCR6_FIELD0000_SHIFT (0U) +#define DMA_CCR6_FIELD0000_MASK (0x1U << DMA_CCR6_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_CCR6_FIELD0009_SHIFT (1U) +#define DMA_CCR6_FIELD0009_MASK (0x7U << DMA_CCR6_FIELD0009_SHIFT) /* 0x0000000E */ +#define DMA_CCR6_FIELD0008_SHIFT (4U) +#define DMA_CCR6_FIELD0008_MASK (0xFU << DMA_CCR6_FIELD0008_SHIFT) /* 0x000000F0 */ +#define DMA_CCR6_FIELD0007_SHIFT (8U) +#define DMA_CCR6_FIELD0007_MASK (0x7U << DMA_CCR6_FIELD0007_SHIFT) /* 0x00000700 */ +#define DMA_CCR6_FIELD0006_SHIFT (11U) +#define DMA_CCR6_FIELD0006_MASK (0x7U << DMA_CCR6_FIELD0006_SHIFT) /* 0x00003800 */ +#define DMA_CCR6_FIELD0005_SHIFT (14U) +#define DMA_CCR6_FIELD0005_MASK (0x1U << DMA_CCR6_FIELD0005_SHIFT) /* 0x00004000 */ +#define DMA_CCR6_FIELD0004_SHIFT (15U) +#define DMA_CCR6_FIELD0004_MASK (0x7U << DMA_CCR6_FIELD0004_SHIFT) /* 0x00038000 */ +#define DMA_CCR6_FIELD0003_SHIFT (18U) +#define DMA_CCR6_FIELD0003_MASK (0xFU << DMA_CCR6_FIELD0003_SHIFT) /* 0x003C0000 */ +#define DMA_CCR6_FIELD0002_SHIFT (22U) +#define DMA_CCR6_FIELD0002_MASK (0x7U << DMA_CCR6_FIELD0002_SHIFT) /* 0x01C00000 */ +#define DMA_CCR6_FIELD0001_SHIFT (25U) +#define DMA_CCR6_FIELD0001_MASK (0x7U << DMA_CCR6_FIELD0001_SHIFT) /* 0x0E000000 */ +/* LC0_6 */ +#define DMA_LC0_6_OFFSET (0x4CCU) +#define DMA_LC0_6 (0x0U) +#define DMA_LC0_6_FIELD0000_SHIFT (0U) +#define DMA_LC0_6_FIELD0000_MASK (0xFFU << DMA_LC0_6_FIELD0000_SHIFT) /* 0x000000FF */ +/* LC1_6 */ +#define DMA_LC1_6_OFFSET (0x4D0U) +#define DMA_LC1_6 (0x0U) +#define DMA_LC1_6_FIELD0000_SHIFT (0U) +#define DMA_LC1_6_FIELD0000_MASK (0xFFU << DMA_LC1_6_FIELD0000_SHIFT) /* 0x000000FF */ +/* PADDING6_0 */ +#define DMA_PADDING6_0_OFFSET (0x4D4U) +/* PADDING6_1 */ +#define DMA_PADDING6_1_OFFSET (0x4D8U) +/* PADDING6_2 */ +#define DMA_PADDING6_2_OFFSET (0x4DCU) +/* SAR7 */ +#define DMA_SAR7_OFFSET (0x4E0U) +#define DMA_SAR7 (0x0U) +#define DMA_SAR7_FIELD0000_SHIFT (0U) +#define DMA_SAR7_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR7_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* DAR7 */ +#define DMA_DAR7_OFFSET (0x4E4U) +#define DMA_DAR7 (0x0U) +#define DMA_DAR7_FIELD0000_SHIFT (0U) +#define DMA_DAR7_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR7_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CCR7 */ +#define DMA_CCR7_OFFSET (0x4E8U) +#define DMA_CCR7 (0x0U) +#define DMA_CCR7_FIELD0000_SHIFT (0U) +#define DMA_CCR7_FIELD0000_MASK (0x1U << DMA_CCR7_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_CCR7_FIELD0009_SHIFT (1U) +#define DMA_CCR7_FIELD0009_MASK (0x7U << DMA_CCR7_FIELD0009_SHIFT) /* 0x0000000E */ +#define DMA_CCR7_FIELD0008_SHIFT (4U) +#define DMA_CCR7_FIELD0008_MASK (0xFU << DMA_CCR7_FIELD0008_SHIFT) /* 0x000000F0 */ +#define DMA_CCR7_FIELD0007_SHIFT (8U) +#define DMA_CCR7_FIELD0007_MASK (0x7U << DMA_CCR7_FIELD0007_SHIFT) /* 0x00000700 */ +#define DMA_CCR7_FIELD0006_SHIFT (11U) +#define DMA_CCR7_FIELD0006_MASK (0x7U << DMA_CCR7_FIELD0006_SHIFT) /* 0x00003800 */ +#define DMA_CCR7_FIELD0005_SHIFT (14U) +#define DMA_CCR7_FIELD0005_MASK (0x1U << DMA_CCR7_FIELD0005_SHIFT) /* 0x00004000 */ +#define DMA_CCR7_FIELD0004_SHIFT (15U) +#define DMA_CCR7_FIELD0004_MASK (0x7U << DMA_CCR7_FIELD0004_SHIFT) /* 0x00038000 */ +#define DMA_CCR7_FIELD0003_SHIFT (18U) +#define DMA_CCR7_FIELD0003_MASK (0xFU << DMA_CCR7_FIELD0003_SHIFT) /* 0x003C0000 */ +#define DMA_CCR7_FIELD0002_SHIFT (22U) +#define DMA_CCR7_FIELD0002_MASK (0x7U << DMA_CCR7_FIELD0002_SHIFT) /* 0x01C00000 */ +#define DMA_CCR7_FIELD0001_SHIFT (25U) +#define DMA_CCR7_FIELD0001_MASK (0x7U << DMA_CCR7_FIELD0001_SHIFT) /* 0x0E000000 */ +/* LC0_7 */ +#define DMA_LC0_7_OFFSET (0x4ECU) +#define DMA_LC0_7 (0x0U) +#define DMA_LC0_7_FIELD0000_SHIFT (0U) +#define DMA_LC0_7_FIELD0000_MASK (0xFFU << DMA_LC0_7_FIELD0000_SHIFT) /* 0x000000FF */ +/* LC1_7 */ +#define DMA_LC1_7_OFFSET (0x4F0U) +#define DMA_LC1_7 (0x0U) +#define DMA_LC1_7_FIELD0000_SHIFT (0U) +#define DMA_LC1_7_FIELD0000_MASK (0xFFU << DMA_LC1_7_FIELD0000_SHIFT) /* 0x000000FF */ +/* PADDING7_0 */ +#define DMA_PADDING7_0_OFFSET (0x4F4U) +/* PADDING7_1 */ +#define DMA_PADDING7_1_OFFSET (0x4F8U) +/* PADDING7_2 */ +#define DMA_PADDING7_2_OFFSET (0x4FCU) +/* DBGSTATUS */ +#define DMA_DBGSTATUS_OFFSET (0xD00U) +#define DMA_DBGSTATUS (0x0U) +#define DMA_DBGSTATUS_FIELD0000_SHIFT (0U) +#define DMA_DBGSTATUS_FIELD0000_MASK (0x3U << DMA_DBGSTATUS_FIELD0000_SHIFT) /* 0x00000003 */ +/* DBGCMD */ +#define DMA_DBGCMD_OFFSET (0xD04U) +#define DMA_DBGCMD_FIELD0000_SHIFT (0U) +#define DMA_DBGCMD_FIELD0000_MASK (0x3U << DMA_DBGCMD_FIELD0000_SHIFT) /* 0x00000003 */ +/* DBGINST0 */ +#define DMA_DBGINST0_OFFSET (0xD08U) +#define DMA_DBGINST0_FIELD0000_SHIFT (0U) +#define DMA_DBGINST0_FIELD0000_MASK (0x1U << DMA_DBGINST0_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_DBGINST0_FIELD0003_SHIFT (8U) +#define DMA_DBGINST0_FIELD0003_MASK (0x7U << DMA_DBGINST0_FIELD0003_SHIFT) /* 0x00000700 */ +#define DMA_DBGINST0_FIELD0002_SHIFT (16U) +#define DMA_DBGINST0_FIELD0002_MASK (0xFFU << DMA_DBGINST0_FIELD0002_SHIFT) /* 0x00FF0000 */ +#define DMA_DBGINST0_FIELD0001_SHIFT (24U) +#define DMA_DBGINST0_FIELD0001_MASK (0xFFU << DMA_DBGINST0_FIELD0001_SHIFT) /* 0xFF000000 */ +/* DBGINST1 */ +#define DMA_DBGINST1_OFFSET (0xD0CU) +#define DMA_DBGINST1_FIELD0000_SHIFT (0U) +#define DMA_DBGINST1_FIELD0000_MASK (0xFFU << DMA_DBGINST1_FIELD0000_SHIFT) /* 0x000000FF */ +#define DMA_DBGINST1_FIELD0003_SHIFT (8U) +#define DMA_DBGINST1_FIELD0003_MASK (0xFFU << DMA_DBGINST1_FIELD0003_SHIFT) /* 0x0000FF00 */ +#define DMA_DBGINST1_FIELD0002_SHIFT (16U) +#define DMA_DBGINST1_FIELD0002_MASK (0xFFU << DMA_DBGINST1_FIELD0002_SHIFT) /* 0x00FF0000 */ +#define DMA_DBGINST1_FIELD0001_SHIFT (24U) +#define DMA_DBGINST1_FIELD0001_MASK (0xFFU << DMA_DBGINST1_FIELD0001_SHIFT) /* 0xFF000000 */ +/* CR0 */ +#define DMA_CR0_OFFSET (0xE00U) +#define DMA_CR0 (0x47051U) +#define DMA_CR0_FIELD0000_SHIFT (0U) +#define DMA_CR0_FIELD0000_MASK (0x1U << DMA_CR0_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_CR0_FIELD0005_SHIFT (1U) +#define DMA_CR0_FIELD0005_MASK (0x1U << DMA_CR0_FIELD0005_SHIFT) /* 0x00000002 */ +#define DMA_CR0_FIELD0004_SHIFT (2U) +#define DMA_CR0_FIELD0004_MASK (0x1U << DMA_CR0_FIELD0004_SHIFT) /* 0x00000004 */ +#define DMA_CR0_FIELD0003_SHIFT (4U) +#define DMA_CR0_FIELD0003_MASK (0x7U << DMA_CR0_FIELD0003_SHIFT) /* 0x00000070 */ +#define DMA_CR0_FIELD0002_SHIFT (12U) +#define DMA_CR0_FIELD0002_MASK (0x1FU << DMA_CR0_FIELD0002_SHIFT) /* 0x0001F000 */ +#define DMA_CR0_FIELD0001_SHIFT (17U) +#define DMA_CR0_FIELD0001_MASK (0x1FU << DMA_CR0_FIELD0001_SHIFT) /* 0x003E0000 */ +/* CR1 */ +#define DMA_CR1_OFFSET (0xE04U) +#define DMA_CR1 (0x57U) +#define DMA_CR1_FIELD0000_SHIFT (0U) +#define DMA_CR1_FIELD0000_MASK (0x7U << DMA_CR1_FIELD0000_SHIFT) /* 0x00000007 */ +#define DMA_CR1_FIELD0001_SHIFT (4U) +#define DMA_CR1_FIELD0001_MASK (0xFU << DMA_CR1_FIELD0001_SHIFT) /* 0x000000F0 */ +/* CR2 */ +#define DMA_CR2_OFFSET (0xE08U) +#define DMA_CR2 (0x0U) +#define DMA_CR2_FIELD0000_SHIFT (0U) +#define DMA_CR2_FIELD0000_MASK (0xFFFFFFFFU << DMA_CR2_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CR3 */ +#define DMA_CR3_OFFSET (0xE0CU) +#define DMA_CR3 (0x0U) +#define DMA_CR3_FIELD0000_SHIFT (0U) +#define DMA_CR3_FIELD0000_MASK (0xFFFFFFFFU << DMA_CR3_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CR4 */ +#define DMA_CR4_OFFSET (0xE10U) +#define DMA_CR4 (0x6U) +#define DMA_CR4_FIELD0000_SHIFT (0U) +#define DMA_CR4_FIELD0000_MASK (0xFFFFFFFFU << DMA_CR4_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CRDN */ +#define DMA_CRDN_OFFSET (0xE14U) +#define DMA_CRDN (0x2094733U) +#define DMA_CRDN_FIELD0000_SHIFT (0U) +#define DMA_CRDN_FIELD0000_MASK (0x7U << DMA_CRDN_FIELD0000_SHIFT) /* 0x00000007 */ +#define DMA_CRDN_FIELD0005_SHIFT (4U) +#define DMA_CRDN_FIELD0005_MASK (0x7U << DMA_CRDN_FIELD0005_SHIFT) /* 0x00000070 */ +#define DMA_CRDN_FIELD0004_SHIFT (8U) +#define DMA_CRDN_FIELD0004_MASK (0xFU << DMA_CRDN_FIELD0004_SHIFT) /* 0x00000F00 */ +#define DMA_CRDN_FIELD0003_SHIFT (12U) +#define DMA_CRDN_FIELD0003_MASK (0x7U << DMA_CRDN_FIELD0003_SHIFT) /* 0x00007000 */ +#define DMA_CRDN_FIELD0002_SHIFT (16U) +#define DMA_CRDN_FIELD0002_MASK (0xFU << DMA_CRDN_FIELD0002_SHIFT) /* 0x000F0000 */ +#define DMA_CRDN_FIELD0001_SHIFT (20U) +#define DMA_CRDN_FIELD0001_MASK (0x3FFU << DMA_CRDN_FIELD0001_SHIFT) /* 0x3FF00000 */ +/* WD */ +#define DMA_WD_OFFSET (0xE80U) +#define DMA_WD_FIELD0000_SHIFT (0U) +#define DMA_WD_FIELD0000_MASK (0x1U << DMA_WD_FIELD0000_SHIFT) /* 0x00000001 */ +/******************************************CAN*******************************************/ +/* MODE */ +#define CAN_MODE_OFFSET (0x0U) +#define CAN_MODE_WORK_MODE_SHIFT (0U) +#define CAN_MODE_WORK_MODE_MASK (0x1U << CAN_MODE_WORK_MODE_SHIFT) /* 0x00000001 */ +#define CAN_MODE_SLEEP_MODE_SHIFT (1U) +#define CAN_MODE_SLEEP_MODE_MASK (0x1U << CAN_MODE_SLEEP_MODE_SHIFT) /* 0x00000002 */ +#define CAN_MODE_SELF_TEST_SHIFT (2U) +#define CAN_MODE_SELF_TEST_MASK (0x1U << CAN_MODE_SELF_TEST_SHIFT) /* 0x00000004 */ +#define CAN_MODE_SILENT_MODE_SHIFT (3U) +#define CAN_MODE_SILENT_MODE_MASK (0x1U << CAN_MODE_SILENT_MODE_SHIFT) /* 0x00000008 */ +#define CAN_MODE_LBACK_MODE_SHIFT (4U) +#define CAN_MODE_LBACK_MODE_MASK (0x1U << CAN_MODE_LBACK_MODE_SHIFT) /* 0x00000010 */ +#define CAN_MODE_RXSTX_MODE_SHIFT (5U) +#define CAN_MODE_RXSTX_MODE_MASK (0x1U << CAN_MODE_RXSTX_MODE_SHIFT) /* 0x00000020 */ +#define CAN_MODE_TXORDER_MODE_SHIFT (6U) +#define CAN_MODE_TXORDER_MODE_MASK (0x1U << CAN_MODE_TXORDER_MODE_SHIFT) /* 0x00000040 */ +#define CAN_MODE_RXSORT_MODE_SHIFT (7U) +#define CAN_MODE_RXSORT_MODE_MASK (0x1U << CAN_MODE_RXSORT_MODE_SHIFT) /* 0x00000080 */ +#define CAN_MODE_COVER_MODE_SHIFT (8U) +#define CAN_MODE_COVER_MODE_MASK (0x1U << CAN_MODE_COVER_MODE_SHIFT) /* 0x00000100 */ +#define CAN_MODE_OVLD_MODE_SHIFT (9U) +#define CAN_MODE_OVLD_MODE_MASK (0x1U << CAN_MODE_OVLD_MODE_SHIFT) /* 0x00000200 */ +#define CAN_MODE_AUTO_RETX_MODE_SHIFT (10U) +#define CAN_MODE_AUTO_RETX_MODE_MASK (0x1U << CAN_MODE_AUTO_RETX_MODE_SHIFT) /* 0x00000400 */ +#define CAN_MODE_AUTO_BUS_ON_SHIFT (11U) +#define CAN_MODE_AUTO_BUS_ON_MASK (0x1U << CAN_MODE_AUTO_BUS_ON_SHIFT) /* 0x00000800 */ +#define CAN_MODE_SPACE_RX_MODE_SHIFT (12U) +#define CAN_MODE_SPACE_RX_MODE_MASK (0x1U << CAN_MODE_SPACE_RX_MODE_SHIFT) /* 0x00001000 */ +#define CAN_MODE_BRSD_SHIFT (13U) +#define CAN_MODE_BRSD_MASK (0x1U << CAN_MODE_BRSD_SHIFT) /* 0x00002000 */ +#define CAN_MODE_DPEE_SHIFT (14U) +#define CAN_MODE_DPEE_MASK (0x1U << CAN_MODE_DPEE_SHIFT) /* 0x00004000 */ +#define CAN_MODE_CAN_FD_MODE_ENABLE_SHIFT (15U) +#define CAN_MODE_CAN_FD_MODE_ENABLE_MASK (0x1U << CAN_MODE_CAN_FD_MODE_ENABLE_SHIFT) /* 0x00008000 */ +/* CMD */ +#define CAN_CMD_OFFSET (0x4U) +#define CAN_CMD_TX0_REQ_SHIFT (0U) +#define CAN_CMD_TX0_REQ_MASK (0x1U << CAN_CMD_TX0_REQ_SHIFT) /* 0x00000001 */ +#define CAN_CMD_TX1_REQ_SHIFT (1U) +#define CAN_CMD_TX1_REQ_MASK (0x1U << CAN_CMD_TX1_REQ_SHIFT) /* 0x00000002 */ +/* STATE */ +#define CAN_STATE_OFFSET (0x8U) +#define CAN_STATE (0x0U) +#define CAN_STATE_RX_BUFFER_FULL_SHIFT (0U) +#define CAN_STATE_RX_BUFFER_FULL_MASK (0x1U << CAN_STATE_RX_BUFFER_FULL_SHIFT) /* 0x00000001 */ +#define CAN_STATE_TX_BUFFER_FULL_SHIFT (1U) +#define CAN_STATE_TX_BUFFER_FULL_MASK (0x1U << CAN_STATE_TX_BUFFER_FULL_SHIFT) /* 0x00000002 */ +#define CAN_STATE_RX_PERIOD_SHIFT (2U) +#define CAN_STATE_RX_PERIOD_MASK (0x1U << CAN_STATE_RX_PERIOD_SHIFT) /* 0x00000004 */ +#define CAN_STATE_TX_PERIOD_SHIFT (3U) +#define CAN_STATE_TX_PERIOD_MASK (0x1U << CAN_STATE_TX_PERIOD_SHIFT) /* 0x00000008 */ +#define CAN_STATE_ERROR_WARNING_STATE_SHIFT (4U) +#define CAN_STATE_ERROR_WARNING_STATE_MASK (0x1U << CAN_STATE_ERROR_WARNING_STATE_SHIFT) /* 0x00000010 */ +#define CAN_STATE_BUS_OFF_STATE_SHIFT (5U) +#define CAN_STATE_BUS_OFF_STATE_MASK (0x1U << CAN_STATE_BUS_OFF_STATE_SHIFT) /* 0x00000020 */ +#define CAN_STATE_SLEEP_STATE_SHIFT (6U) +#define CAN_STATE_SLEEP_STATE_MASK (0x1U << CAN_STATE_SLEEP_STATE_SHIFT) /* 0x00000040 */ +/* INT */ +#define CAN_INT_OFFSET (0xCU) +#define CAN_INT_RX_FINISH_INT_SHIFT (0U) +#define CAN_INT_RX_FINISH_INT_MASK (0x1U << CAN_INT_RX_FINISH_INT_SHIFT) /* 0x00000001 */ +#define CAN_INT_TX_FINISH_INT_SHIFT (1U) +#define CAN_INT_TX_FINISH_INT_MASK (0x1U << CAN_INT_TX_FINISH_INT_SHIFT) /* 0x00000002 */ +#define CAN_INT_ERROR_WARNING_INT_SHIFT (2U) +#define CAN_INT_ERROR_WARNING_INT_MASK (0x1U << CAN_INT_ERROR_WARNING_INT_SHIFT) /* 0x00000004 */ +#define CAN_INT_OVERLOAD_INT_SHIFT (3U) +#define CAN_INT_OVERLOAD_INT_MASK (0x1U << CAN_INT_OVERLOAD_INT_SHIFT) /* 0x00000008 */ +#define CAN_INT_PASSIVE_ERROR_INT_SHIFT (4U) +#define CAN_INT_PASSIVE_ERROR_INT_MASK (0x1U << CAN_INT_PASSIVE_ERROR_INT_SHIFT) /* 0x00000010 */ +#define CAN_INT_TX_ARBIT_FAIL_INT_SHIFT (5U) +#define CAN_INT_TX_ARBIT_FAIL_INT_MASK (0x1U << CAN_INT_TX_ARBIT_FAIL_INT_SHIFT) /* 0x00000020 */ +#define CAN_INT_ERROR_INT_SHIFT (6U) +#define CAN_INT_ERROR_INT_MASK (0x1U << CAN_INT_ERROR_INT_SHIFT) /* 0x00000040 */ +#define CAN_INT_RX_FIFO_FULL_INT_SHIFT (7U) +#define CAN_INT_RX_FIFO_FULL_INT_MASK (0x1U << CAN_INT_RX_FIFO_FULL_INT_SHIFT) /* 0x00000080 */ +#define CAN_INT_RX_FIFO_OVERFLOW_INT_SHIFT (8U) +#define CAN_INT_RX_FIFO_OVERFLOW_INT_MASK (0x1U << CAN_INT_RX_FIFO_OVERFLOW_INT_SHIFT) /* 0x00000100 */ +#define CAN_INT_BUS_OFF_INT_SHIFT (9U) +#define CAN_INT_BUS_OFF_INT_MASK (0x1U << CAN_INT_BUS_OFF_INT_SHIFT) /* 0x00000200 */ +#define CAN_INT_BUS_OFF_RECOVERY_INT_SHIFT (10U) +#define CAN_INT_BUS_OFF_RECOVERY_INT_MASK (0x1U << CAN_INT_BUS_OFF_RECOVERY_INT_SHIFT) /* 0x00000400 */ +#define CAN_INT_TIMESTAMP_COUNTER_OVERFLOW_INT_SHIFT (11U) +#define CAN_INT_TIMESTAMP_COUNTER_OVERFLOW_INT_MASK (0x1U << CAN_INT_TIMESTAMP_COUNTER_OVERFLOW_INT_SHIFT) /* 0x00000800 */ +#define CAN_INT_TX_EVENT_FIFO_OVERFLOW_INT_SHIFT (12U) +#define CAN_INT_TX_EVENT_FIFO_OVERFLOW_INT_MASK (0x1U << CAN_INT_TX_EVENT_FIFO_OVERFLOW_INT_SHIFT) /* 0x00001000 */ +#define CAN_INT_TX_EVENT_FIFO_FULL_INT_SHIFT (13U) +#define CAN_INT_TX_EVENT_FIFO_FULL_INT_MASK (0x1U << CAN_INT_TX_EVENT_FIFO_FULL_INT_SHIFT) /* 0x00002000 */ +#define CAN_INT_WAKEUP_INT_SHIFT (14U) +#define CAN_INT_WAKEUP_INT_MASK (0x1U << CAN_INT_WAKEUP_INT_SHIFT) /* 0x00004000 */ +/* INT_MASK */ +#define CAN_INT_MASK_OFFSET (0x10U) +#define CAN_INT_MASK_RX_FINISH_INT_MASK_SHIFT (0U) +#define CAN_INT_MASK_RX_FINISH_INT_MASK_MASK (0x1U << CAN_INT_MASK_RX_FINISH_INT_MASK_SHIFT) /* 0x00000001 */ +#define CAN_INT_MASK_TX_FINISH_INT_MASK_SHIFT (1U) +#define CAN_INT_MASK_TX_FINISH_INT_MASK_MASK (0x1U << CAN_INT_MASK_TX_FINISH_INT_MASK_SHIFT) /* 0x00000002 */ +#define CAN_INT_MASK_ERROR_WARNING_INT_MASK_SHIFT (2U) +#define CAN_INT_MASK_ERROR_WARNING_INT_MASK_MASK (0x1U << CAN_INT_MASK_ERROR_WARNING_INT_MASK_SHIFT) /* 0x00000004 */ +#define CAN_INT_MASK_RX_BUFFER_OVERFLOW_INT_MASK_SHIFT (3U) +#define CAN_INT_MASK_RX_BUFFER_OVERFLOW_INT_MASK_MASK (0x1U << CAN_INT_MASK_RX_BUFFER_OVERFLOW_INT_MASK_SHIFT) /* 0x00000008 */ +#define CAN_INT_MASK_PASSIVE_ERROR_INT_MASK_SHIFT (4U) +#define CAN_INT_MASK_PASSIVE_ERROR_INT_MASK_MASK (0x1U << CAN_INT_MASK_PASSIVE_ERROR_INT_MASK_SHIFT) /* 0x00000010 */ +#define CAN_INT_MASK_TX_ARBIT_FAIL_INT_MASK_SHIFT (5U) +#define CAN_INT_MASK_TX_ARBIT_FAIL_INT_MASK_MASK (0x1U << CAN_INT_MASK_TX_ARBIT_FAIL_INT_MASK_SHIFT) /* 0x00000020 */ +#define CAN_INT_MASK_ERROR_INT_MASK_SHIFT (6U) +#define CAN_INT_MASK_ERROR_INT_MASK_MASK (0x1U << CAN_INT_MASK_ERROR_INT_MASK_SHIFT) /* 0x00000040 */ +#define CAN_INT_MASK_RX_FIFO_FULL_INT_MASK_SHIFT (7U) +#define CAN_INT_MASK_RX_FIFO_FULL_INT_MASK_MASK (0x1U << CAN_INT_MASK_RX_FIFO_FULL_INT_MASK_SHIFT) /* 0x00000080 */ +#define CAN_INT_MASK_RX_FIFO_OVERFLOW_INT_MASK_SHIFT (8U) +#define CAN_INT_MASK_RX_FIFO_OVERFLOW_INT_MASK_MASK (0x1U << CAN_INT_MASK_RX_FIFO_OVERFLOW_INT_MASK_SHIFT) /* 0x00000100 */ +#define CAN_INT_MASK_BUS_OFF_INT_MASK_SHIFT (9U) +#define CAN_INT_MASK_BUS_OFF_INT_MASK_MASK (0x1U << CAN_INT_MASK_BUS_OFF_INT_MASK_SHIFT) /* 0x00000200 */ +#define CAN_INT_MASK_BUS_OFF_RECOVERY_INT_MASK_SHIFT (10U) +#define CAN_INT_MASK_BUS_OFF_RECOVERY_INT_MASK_MASK (0x1U << CAN_INT_MASK_BUS_OFF_RECOVERY_INT_MASK_SHIFT) /* 0x00000400 */ +#define CAN_INT_MASK_TIMESTAMP_COUNTER_OVERFLOW_INT_MASK_SHIFT (11U) +#define CAN_INT_MASK_TIMESTAMP_COUNTER_OVERFLOW_INT_MASK_MASK (0x1U << CAN_INT_MASK_TIMESTAMP_COUNTER_OVERFLOW_INT_MASK_SHIFT) /* 0x00000800 */ +#define CAN_INT_MASK_TX_EVENT_FIFO_OVERFLOW_INT_MASK_SHIFT (12U) +#define CAN_INT_MASK_TX_EVENT_FIFO_OVERFLOW_INT_MASK_MASK (0x1U << CAN_INT_MASK_TX_EVENT_FIFO_OVERFLOW_INT_MASK_SHIFT) /* 0x00001000 */ +#define CAN_INT_MASK_TX_EVENT_FIFO_FULL_INT_MASK_SHIFT (13U) +#define CAN_INT_MASK_TX_EVENT_FIFO_FULL_INT_MASK_MASK (0x1U << CAN_INT_MASK_TX_EVENT_FIFO_FULL_INT_MASK_SHIFT) /* 0x00002000 */ +#define CAN_INT_MASK_WAKEUP_INT_MASK_SHIFT (14U) +#define CAN_INT_MASK_WAKEUP_INT_MASK_MASK (0x1U << CAN_INT_MASK_WAKEUP_INT_MASK_SHIFT) /* 0x00004000 */ +/* DMA_CTRL */ +#define CAN_DMA_CTRL_OFFSET (0x14U) +#define CAN_DMA_CTRL_DMA_TX_MODE_SHIFT (0U) +#define CAN_DMA_CTRL_DMA_TX_MODE_MASK (0x1U << CAN_DMA_CTRL_DMA_TX_MODE_SHIFT) /* 0x00000001 */ +#define CAN_DMA_CTRL_DMA_RX_MODE_SHIFT (1U) +#define CAN_DMA_CTRL_DMA_RX_MODE_MASK (0x1U << CAN_DMA_CTRL_DMA_RX_MODE_SHIFT) /* 0x00000002 */ +/* BITTIMING */ +#define CAN_BITTIMING_OFFSET (0x18U) +#define CAN_BITTIMING_TSEG1_SHIFT (0U) +#define CAN_BITTIMING_TSEG1_MASK (0xFU << CAN_BITTIMING_TSEG1_SHIFT) /* 0x0000000F */ +#define CAN_BITTIMING_TSEG2_SHIFT (4U) +#define CAN_BITTIMING_TSEG2_MASK (0x7U << CAN_BITTIMING_TSEG2_SHIFT) /* 0x00000070 */ +#define CAN_BITTIMING_BRP_SHIFT (8U) +#define CAN_BITTIMING_BRP_MASK (0x3FU << CAN_BITTIMING_BRP_SHIFT) /* 0x00003F00 */ +#define CAN_BITTIMING_SJW_SHIFT (14U) +#define CAN_BITTIMING_SJW_MASK (0x3U << CAN_BITTIMING_SJW_SHIFT) /* 0x0000C000 */ +#define CAN_BITTIMING_SAMPLE_MODE_SHIFT (16U) +#define CAN_BITTIMING_SAMPLE_MODE_MASK (0x1U << CAN_BITTIMING_SAMPLE_MODE_SHIFT) /* 0x00010000 */ +/* ARBITFAIL */ +#define CAN_ARBITFAIL_OFFSET (0x28U) +#define CAN_ARBITFAIL (0x0U) +#define CAN_ARBITFAIL_ARBIT_FAIL_CODE_SHIFT (0U) +#define CAN_ARBITFAIL_ARBIT_FAIL_CODE_MASK (0x7FU << CAN_ARBITFAIL_ARBIT_FAIL_CODE_SHIFT) /* 0x0000007F */ +/* ERROR_CODE */ +#define CAN_ERROR_CODE_OFFSET (0x2CU) +#define CAN_ERROR_CODE_RX_ERROR_POSITION_SHIFT (0U) +#define CAN_ERROR_CODE_RX_ERROR_POSITION_MASK (0xFFFFU << CAN_ERROR_CODE_RX_ERROR_POSITION_SHIFT) /* 0x0000FFFF */ +#define CAN_ERROR_CODE_TX_ERROR_POSITION_SHIFT (16U) +#define CAN_ERROR_CODE_TX_ERROR_POSITION_MASK (0x1FFU << CAN_ERROR_CODE_TX_ERROR_POSITION_SHIFT) /* 0x01FF0000 */ +#define CAN_ERROR_CODE_ERROR_DIRECTION_SHIFT (25U) +#define CAN_ERROR_CODE_ERROR_DIRECTION_MASK (0x1U << CAN_ERROR_CODE_ERROR_DIRECTION_SHIFT) /* 0x02000000 */ +#define CAN_ERROR_CODE_ERROR_TYPE_SHIFT (26U) +#define CAN_ERROR_CODE_ERROR_TYPE_MASK (0x7U << CAN_ERROR_CODE_ERROR_TYPE_SHIFT) /* 0x1C000000 */ +#define CAN_ERROR_CODE_ERROR_PHASE_SHIFT (29U) +#define CAN_ERROR_CODE_ERROR_PHASE_MASK (0x1U << CAN_ERROR_CODE_ERROR_PHASE_SHIFT) /* 0x20000000 */ +/* RXERRORCNT */ +#define CAN_RXERRORCNT_OFFSET (0x34U) +#define CAN_RXERRORCNT (0x0U) +#define CAN_RXERRORCNT_RX_ERR_CNT_SHIFT (0U) +#define CAN_RXERRORCNT_RX_ERR_CNT_MASK (0xFFU << CAN_RXERRORCNT_RX_ERR_CNT_SHIFT) /* 0x000000FF */ +/* TXERRORCNT */ +#define CAN_TXERRORCNT_OFFSET (0x38U) +#define CAN_TXERRORCNT (0x0U) +#define CAN_TXERRORCNT_TX_ERR_CNT_SHIFT (0U) +#define CAN_TXERRORCNT_TX_ERR_CNT_MASK (0x1FFU << CAN_TXERRORCNT_TX_ERR_CNT_SHIFT) /* 0x000001FF */ +/* IDCODE */ +#define CAN_IDCODE_OFFSET (0x3CU) +#define CAN_IDCODE_ID_CODE_SHIFT (0U) +#define CAN_IDCODE_ID_CODE_MASK (0x1FFFFFFFU << CAN_IDCODE_ID_CODE_SHIFT) /* 0x1FFFFFFF */ +/* IDMASK */ +#define CAN_IDMASK_OFFSET (0x40U) +#define CAN_IDMASK_ID_MASK_SHIFT (0U) +#define CAN_IDMASK_ID_MASK_MASK (0x1FFFFFFFU << CAN_IDMASK_ID_MASK_SHIFT) /* 0x1FFFFFFF */ +/* TXFRAMEINFO */ +#define CAN_TXFRAMEINFO_OFFSET (0x50U) +#define CAN_TXFRAMEINFO_TXDATA_LENGTH_SHIFT (0U) +#define CAN_TXFRAMEINFO_TXDATA_LENGTH_MASK (0xFU << CAN_TXFRAMEINFO_TXDATA_LENGTH_SHIFT) /* 0x0000000F */ +#define CAN_TXFRAMEINFO_TX_RTR_SHIFT (6U) +#define CAN_TXFRAMEINFO_TX_RTR_MASK (0x1U << CAN_TXFRAMEINFO_TX_RTR_SHIFT) /* 0x00000040 */ +#define CAN_TXFRAMEINFO_TXFRAME_FORMAT_SHIFT (7U) +#define CAN_TXFRAMEINFO_TXFRAME_FORMAT_MASK (0x1U << CAN_TXFRAMEINFO_TXFRAME_FORMAT_SHIFT) /* 0x00000080 */ +/* TXID */ +#define CAN_TXID_OFFSET (0x54U) +#define CAN_TXID_TX_ID_SHIFT (0U) +#define CAN_TXID_TX_ID_MASK (0x1FFFFFFFU << CAN_TXID_TX_ID_SHIFT) /* 0x1FFFFFFF */ +/* TXDATA0 */ +#define CAN_TXDATA0_OFFSET (0x58U) +#define CAN_TXDATA0_TX_DATA0_SHIFT (0U) +#define CAN_TXDATA0_TX_DATA0_MASK (0xFFFFFFFFU << CAN_TXDATA0_TX_DATA0_SHIFT) /* 0xFFFFFFFF */ +/* TXDATA1 */ +#define CAN_TXDATA1_OFFSET (0x5CU) +#define CAN_TXDATA1_TX_DATA1_SHIFT (0U) +#define CAN_TXDATA1_TX_DATA1_MASK (0xFFFFFFFFU << CAN_TXDATA1_TX_DATA1_SHIFT) /* 0xFFFFFFFF */ +/* RXFRAMEINFO */ +#define CAN_RXFRAMEINFO_OFFSET (0x60U) +#define CAN_RXFRAMEINFO (0x0U) +#define CAN_RXFRAMEINFO_RXDATA_LENGTH_SHIFT (0U) +#define CAN_RXFRAMEINFO_RXDATA_LENGTH_MASK (0xFU << CAN_RXFRAMEINFO_RXDATA_LENGTH_SHIFT) /* 0x0000000F */ +#define CAN_RXFRAMEINFO_RX_RTR_SHIFT (6U) +#define CAN_RXFRAMEINFO_RX_RTR_MASK (0x1U << CAN_RXFRAMEINFO_RX_RTR_SHIFT) /* 0x00000040 */ +#define CAN_RXFRAMEINFO_RXFRAME_FORMAT_SHIFT (7U) +#define CAN_RXFRAMEINFO_RXFRAME_FORMAT_MASK (0x1U << CAN_RXFRAMEINFO_RXFRAME_FORMAT_SHIFT) /* 0x00000080 */ +/* RXID */ +#define CAN_RXID_OFFSET (0x64U) +#define CAN_RXID (0x0U) +#define CAN_RXID_RX_ID_SHIFT (0U) +#define CAN_RXID_RX_ID_MASK (0x1FFFFFFFU << CAN_RXID_RX_ID_SHIFT) /* 0x1FFFFFFF */ +/* RXDATA0 */ +#define CAN_RXDATA0_OFFSET (0x68U) +#define CAN_RXDATA0 (0x0U) +#define CAN_RXDATA0_RX_DATA0_SHIFT (0U) +#define CAN_RXDATA0_RX_DATA0_MASK (0xFFFFFFFFU << CAN_RXDATA0_RX_DATA0_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA1 */ +#define CAN_RXDATA1_OFFSET (0x6CU) +#define CAN_RXDATA1 (0x0U) +#define CAN_RXDATA1_RX_DATA1_SHIFT (0U) +#define CAN_RXDATA1_RX_DATA1_MASK (0xFFFFFFFFU << CAN_RXDATA1_RX_DATA1_SHIFT) /* 0xFFFFFFFF */ +/* RTL_VERSION */ +#define CAN_RTL_VERSION_OFFSET (0x70U) +#define CAN_RTL_VERSION (0x21U) +#define CAN_RTL_VERSION_VERSION_SHIFT (0U) +#define CAN_RTL_VERSION_VERSION_MASK (0xFFFFFFFFU << CAN_RTL_VERSION_VERSION_SHIFT) /* 0xFFFFFFFF */ +/* FD_NOMINAL_BITTIMING */ +#define CAN_FD_NOMINAL_BITTIMING_OFFSET (0x100U) +#define CAN_FD_NOMINAL_BITTIMING_TSEG1_SHIFT (0U) +#define CAN_FD_NOMINAL_BITTIMING_TSEG1_MASK (0xFFU << CAN_FD_NOMINAL_BITTIMING_TSEG1_SHIFT) /* 0x000000FF */ +#define CAN_FD_NOMINAL_BITTIMING_TSEG2_SHIFT (8U) +#define CAN_FD_NOMINAL_BITTIMING_TSEG2_MASK (0x7FU << CAN_FD_NOMINAL_BITTIMING_TSEG2_SHIFT) /* 0x00007F00 */ +#define CAN_FD_NOMINAL_BITTIMING_BRQ_SHIFT (16U) +#define CAN_FD_NOMINAL_BITTIMING_BRQ_MASK (0xFFU << CAN_FD_NOMINAL_BITTIMING_BRQ_SHIFT) /* 0x00FF0000 */ +#define CAN_FD_NOMINAL_BITTIMING_SJW_SHIFT (24U) +#define CAN_FD_NOMINAL_BITTIMING_SJW_MASK (0x7FU << CAN_FD_NOMINAL_BITTIMING_SJW_SHIFT) /* 0x7F000000 */ +#define CAN_FD_NOMINAL_BITTIMING_SAMPLE_MODE_SHIFT (31U) +#define CAN_FD_NOMINAL_BITTIMING_SAMPLE_MODE_MASK (0x1U << CAN_FD_NOMINAL_BITTIMING_SAMPLE_MODE_SHIFT) /* 0x80000000 */ +/* FD_DATA_BITTIMING */ +#define CAN_FD_DATA_BITTIMING_OFFSET (0x104U) +#define CAN_FD_DATA_BITTIMING_TSEG1_SHIFT (0U) +#define CAN_FD_DATA_BITTIMING_TSEG1_MASK (0x1FU << CAN_FD_DATA_BITTIMING_TSEG1_SHIFT) /* 0x0000001F */ +#define CAN_FD_DATA_BITTIMING_TSEG2_SHIFT (5U) +#define CAN_FD_DATA_BITTIMING_TSEG2_MASK (0xFU << CAN_FD_DATA_BITTIMING_TSEG2_SHIFT) /* 0x000001E0 */ +#define CAN_FD_DATA_BITTIMING_BRQ_SHIFT (9U) +#define CAN_FD_DATA_BITTIMING_BRQ_MASK (0xFFU << CAN_FD_DATA_BITTIMING_BRQ_SHIFT) /* 0x0001FE00 */ +#define CAN_FD_DATA_BITTIMING_SJW_SHIFT (17U) +#define CAN_FD_DATA_BITTIMING_SJW_MASK (0xFU << CAN_FD_DATA_BITTIMING_SJW_SHIFT) /* 0x001E0000 */ +#define CAN_FD_DATA_BITTIMING_SAMPLE_MODE_SHIFT (21U) +#define CAN_FD_DATA_BITTIMING_SAMPLE_MODE_MASK (0x1U << CAN_FD_DATA_BITTIMING_SAMPLE_MODE_SHIFT) /* 0x00200000 */ +/* TRANSMIT_DELAY_COMPENSATION */ +#define CAN_TRANSMIT_DELAY_COMPENSATION_OFFSET (0x108U) +#define CAN_TRANSMIT_DELAY_COMPENSATION_TDC_ENABLE_SHIFT (0U) +#define CAN_TRANSMIT_DELAY_COMPENSATION_TDC_ENABLE_MASK (0x1U << CAN_TRANSMIT_DELAY_COMPENSATION_TDC_ENABLE_SHIFT) /* 0x00000001 */ +#define CAN_TRANSMIT_DELAY_COMPENSATION_TDC_OFFSET_SHIFT (1U) +#define CAN_TRANSMIT_DELAY_COMPENSATION_TDC_OFFSET_MASK (0x3FU << CAN_TRANSMIT_DELAY_COMPENSATION_TDC_OFFSET_SHIFT) /* 0x0000007E */ +/* TIMESTAMP_CTRL */ +#define CAN_TIMESTAMP_CTRL_OFFSET (0x10CU) +#define CAN_TIMESTAMP_CTRL_TIME_BASE_COUNTER_ENABLE_SHIFT (0U) +#define CAN_TIMESTAMP_CTRL_TIME_BASE_COUNTER_ENABLE_MASK (0x1U << CAN_TIMESTAMP_CTRL_TIME_BASE_COUNTER_ENABLE_SHIFT) /* 0x00000001 */ +#define CAN_TIMESTAMP_CTRL_TIME_BASE_COUNTER_PRESCALE_SHIFT (1U) +#define CAN_TIMESTAMP_CTRL_TIME_BASE_COUNTER_PRESCALE_MASK (0x3FU << CAN_TIMESTAMP_CTRL_TIME_BASE_COUNTER_PRESCALE_SHIFT) /* 0x0000007E */ +/* TIMESTAMP */ +#define CAN_TIMESTAMP_OFFSET (0x110U) +#define CAN_TIMESTAMP_TIME_BASE_COUNTER_SHIFT (0U) +#define CAN_TIMESTAMP_TIME_BASE_COUNTER_MASK (0xFFFFFFFFU << CAN_TIMESTAMP_TIME_BASE_COUNTER_SHIFT) /* 0xFFFFFFFF */ +/* TXEVENT_FIFO_CTRL */ +#define CAN_TXEVENT_FIFO_CTRL_OFFSET (0x114U) +#define CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_ENABLE_SHIFT (0U) +#define CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_ENABLE_MASK (0x1U << CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_ENABLE_SHIFT) /* 0x00000001 */ +#define CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_WATERMARK_SHIFT (1U) +#define CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_WATERMARK_MASK (0xFU << CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_WATERMARK_SHIFT) /* 0x0000001E */ +#define CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_CNT_SHIFT (5U) +#define CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_CNT_MASK (0xFU << CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_CNT_SHIFT) /* 0x000001E0 */ +/* RX_FIFO_CTRL */ +#define CAN_RX_FIFO_CTRL_OFFSET (0x118U) +#define CAN_RX_FIFO_CTRL_RX_FIFO_ENABLE_SHIFT (0U) +#define CAN_RX_FIFO_CTRL_RX_FIFO_ENABLE_MASK (0x1U << CAN_RX_FIFO_CTRL_RX_FIFO_ENABLE_SHIFT) /* 0x00000001 */ +#define CAN_RX_FIFO_CTRL_RX_FIFO_FULL_WATERMARK_SHIFT (1U) +#define CAN_RX_FIFO_CTRL_RX_FIFO_FULL_WATERMARK_MASK (0x7U << CAN_RX_FIFO_CTRL_RX_FIFO_FULL_WATERMARK_SHIFT) /* 0x0000000E */ +#define CAN_RX_FIFO_CTRL_RX_FIFO_CNT_SHIFT (4U) +#define CAN_RX_FIFO_CTRL_RX_FIFO_CNT_MASK (0x7U << CAN_RX_FIFO_CTRL_RX_FIFO_CNT_SHIFT) /* 0x00000070 */ +/* AFR_CTRL */ +#define CAN_AFR_CTRL_OFFSET (0x11CU) +#define CAN_AFR_CTRL_UAF1_SHIFT (0U) +#define CAN_AFR_CTRL_UAF1_MASK (0x1U << CAN_AFR_CTRL_UAF1_SHIFT) /* 0x00000001 */ +#define CAN_AFR_CTRL_UAF2_SHIFT (1U) +#define CAN_AFR_CTRL_UAF2_MASK (0x1U << CAN_AFR_CTRL_UAF2_SHIFT) /* 0x00000002 */ +#define CAN_AFR_CTRL_UAF3_SHIFT (2U) +#define CAN_AFR_CTRL_UAF3_MASK (0x1U << CAN_AFR_CTRL_UAF3_SHIFT) /* 0x00000004 */ +#define CAN_AFR_CTRL_UAF4_SHIFT (3U) +#define CAN_AFR_CTRL_UAF4_MASK (0x1U << CAN_AFR_CTRL_UAF4_SHIFT) /* 0x00000008 */ +#define CAN_AFR_CTRL_UAF5_SHIFT (4U) +#define CAN_AFR_CTRL_UAF5_MASK (0x1U << CAN_AFR_CTRL_UAF5_SHIFT) /* 0x00000010 */ +/* IDCODE0 */ +#define CAN_IDCODE0_OFFSET (0x120U) +#define CAN_IDCODE0_ID_CODE_SHIFT (0U) +#define CAN_IDCODE0_ID_CODE_MASK (0x1FFFFFFFU << CAN_IDCODE0_ID_CODE_SHIFT) /* 0x1FFFFFFF */ +/* IDMASK0 */ +#define CAN_IDMASK0_OFFSET (0x124U) +#define CAN_IDMASK0_ID_MASK_SHIFT (0U) +#define CAN_IDMASK0_ID_MASK_MASK (0x1FFFFFFFU << CAN_IDMASK0_ID_MASK_SHIFT) /* 0x1FFFFFFF */ +/* IDCODE1 */ +#define CAN_IDCODE1_OFFSET (0x128U) +#define CAN_IDCODE1_ID_CODE_SHIFT (0U) +#define CAN_IDCODE1_ID_CODE_MASK (0x1FFFFFFFU << CAN_IDCODE1_ID_CODE_SHIFT) /* 0x1FFFFFFF */ +/* IDMASK1 */ +#define CAN_IDMASK1_OFFSET (0x12CU) +#define CAN_IDMASK1_ID_MASK_SHIFT (0U) +#define CAN_IDMASK1_ID_MASK_MASK (0x1FFFFFFFU << CAN_IDMASK1_ID_MASK_SHIFT) /* 0x1FFFFFFF */ +/* IDCODE2 */ +#define CAN_IDCODE2_OFFSET (0x130U) +#define CAN_IDCODE2_ID_CODE_SHIFT (0U) +#define CAN_IDCODE2_ID_CODE_MASK (0x1FFFFFFFU << CAN_IDCODE2_ID_CODE_SHIFT) /* 0x1FFFFFFF */ +/* IDMASK2 */ +#define CAN_IDMASK2_OFFSET (0x134U) +#define CAN_IDMASK2_ID_MASK_SHIFT (0U) +#define CAN_IDMASK2_ID_MASK_MASK (0x1FFFFFFFU << CAN_IDMASK2_ID_MASK_SHIFT) /* 0x1FFFFFFF */ +/* IDCODE3 */ +#define CAN_IDCODE3_OFFSET (0x138U) +#define CAN_IDCODE3_ID_CODE_SHIFT (0U) +#define CAN_IDCODE3_ID_CODE_MASK (0x1FFFFFFFU << CAN_IDCODE3_ID_CODE_SHIFT) /* 0x1FFFFFFF */ +/* IDMASK3 */ +#define CAN_IDMASK3_OFFSET (0x13CU) +#define CAN_IDMASK3_ID_MASK_SHIFT (0U) +#define CAN_IDMASK3_ID_MASK_MASK (0x1FFFFFFFU << CAN_IDMASK3_ID_MASK_SHIFT) /* 0x1FFFFFFF */ +/* IDCODE4 */ +#define CAN_IDCODE4_OFFSET (0x140U) +#define CAN_IDCODE4_ID_CODE_SHIFT (0U) +#define CAN_IDCODE4_ID_CODE_MASK (0x1FFFFFFFU << CAN_IDCODE4_ID_CODE_SHIFT) /* 0x1FFFFFFF */ +/* IDMASK4 */ +#define CAN_IDMASK4_OFFSET (0x144U) +#define CAN_IDMASK4_ID_MASK_SHIFT (0U) +#define CAN_IDMASK4_ID_MASK_MASK (0x1FFFFFFFU << CAN_IDMASK4_ID_MASK_SHIFT) /* 0x1FFFFFFF */ +/* FD_TXFRAMEINFO */ +#define CAN_FD_TXFRAMEINFO_OFFSET (0x200U) +#define CAN_FD_TXFRAMEINFO_TXDATA_LENGTH_SHIFT (0U) +#define CAN_FD_TXFRAMEINFO_TXDATA_LENGTH_MASK (0xFU << CAN_FD_TXFRAMEINFO_TXDATA_LENGTH_SHIFT) /* 0x0000000F */ +#define CAN_FD_TXFRAMEINFO_TX_BRS_SHIFT (4U) +#define CAN_FD_TXFRAMEINFO_TX_BRS_MASK (0x1U << CAN_FD_TXFRAMEINFO_TX_BRS_SHIFT) /* 0x00000010 */ +#define CAN_FD_TXFRAMEINFO_TX_FDF_SHIFT (5U) +#define CAN_FD_TXFRAMEINFO_TX_FDF_MASK (0x1U << CAN_FD_TXFRAMEINFO_TX_FDF_SHIFT) /* 0x00000020 */ +#define CAN_FD_TXFRAMEINFO_TX_RTR_SHIFT (6U) +#define CAN_FD_TXFRAMEINFO_TX_RTR_MASK (0x1U << CAN_FD_TXFRAMEINFO_TX_RTR_SHIFT) /* 0x00000040 */ +#define CAN_FD_TXFRAMEINFO_TXFRAME_FORMAT_SHIFT (7U) +#define CAN_FD_TXFRAMEINFO_TXFRAME_FORMAT_MASK (0x1U << CAN_FD_TXFRAMEINFO_TXFRAME_FORMAT_SHIFT) /* 0x00000080 */ +/* FD_TXID */ +#define CAN_FD_TXID_OFFSET (0x204U) +#define CAN_FD_TXID_TX_ID_SHIFT (0U) +#define CAN_FD_TXID_TX_ID_MASK (0x1FFFFFFFU << CAN_FD_TXID_TX_ID_SHIFT) /* 0x1FFFFFFF */ +/* FD_TXDATA0 */ +#define CAN_FD_TXDATA0_OFFSET (0x208U) +#define CAN_FD_TXDATA0_TX_DATA0_SHIFT (0U) +#define CAN_FD_TXDATA0_TX_DATA0_MASK (0xFFFFFFFFU << CAN_FD_TXDATA0_TX_DATA0_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA1 */ +#define CAN_FD_TXDATA1_OFFSET (0x20CU) +#define CAN_FD_TXDATA1_TX_DATA1_SHIFT (0U) +#define CAN_FD_TXDATA1_TX_DATA1_MASK (0xFFFFFFFFU << CAN_FD_TXDATA1_TX_DATA1_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA2 */ +#define CAN_FD_TXDATA2_OFFSET (0x210U) +#define CAN_FD_TXDATA2_TX_DATA2_SHIFT (0U) +#define CAN_FD_TXDATA2_TX_DATA2_MASK (0xFFFFFFFFU << CAN_FD_TXDATA2_TX_DATA2_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA3 */ +#define CAN_FD_TXDATA3_OFFSET (0x214U) +#define CAN_FD_TXDATA3_TX_DATA3_SHIFT (0U) +#define CAN_FD_TXDATA3_TX_DATA3_MASK (0xFFFFFFFFU << CAN_FD_TXDATA3_TX_DATA3_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA4 */ +#define CAN_FD_TXDATA4_OFFSET (0x218U) +#define CAN_FD_TXDATA4_TX_DATA4_SHIFT (0U) +#define CAN_FD_TXDATA4_TX_DATA4_MASK (0xFFFFFFFFU << CAN_FD_TXDATA4_TX_DATA4_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA5 */ +#define CAN_FD_TXDATA5_OFFSET (0x21CU) +#define CAN_FD_TXDATA5_TX_DATA5_SHIFT (0U) +#define CAN_FD_TXDATA5_TX_DATA5_MASK (0xFFFFFFFFU << CAN_FD_TXDATA5_TX_DATA5_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA6 */ +#define CAN_FD_TXDATA6_OFFSET (0x220U) +#define CAN_FD_TXDATA6_TX_DATA6_SHIFT (0U) +#define CAN_FD_TXDATA6_TX_DATA6_MASK (0xFFFFFFFFU << CAN_FD_TXDATA6_TX_DATA6_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA7 */ +#define CAN_FD_TXDATA7_OFFSET (0x224U) +#define CAN_FD_TXDATA7_TX_DATA7_SHIFT (0U) +#define CAN_FD_TXDATA7_TX_DATA7_MASK (0xFFFFFFFFU << CAN_FD_TXDATA7_TX_DATA7_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA8 */ +#define CAN_FD_TXDATA8_OFFSET (0x228U) +#define CAN_FD_TXDATA8_TX_DATA8_SHIFT (0U) +#define CAN_FD_TXDATA8_TX_DATA8_MASK (0xFFFFFFFFU << CAN_FD_TXDATA8_TX_DATA8_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA9 */ +#define CAN_FD_TXDATA9_OFFSET (0x22CU) +#define CAN_FD_TXDATA9_TX_DATA9_SHIFT (0U) +#define CAN_FD_TXDATA9_TX_DATA9_MASK (0xFFFFFFFFU << CAN_FD_TXDATA9_TX_DATA9_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA10 */ +#define CAN_FD_TXDATA10_OFFSET (0x230U) +#define CAN_FD_TXDATA10_TX_DATA10_SHIFT (0U) +#define CAN_FD_TXDATA10_TX_DATA10_MASK (0xFFFFFFFFU << CAN_FD_TXDATA10_TX_DATA10_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA11 */ +#define CAN_FD_TXDATA11_OFFSET (0x234U) +#define CAN_FD_TXDATA11_TX_DATA11_SHIFT (0U) +#define CAN_FD_TXDATA11_TX_DATA11_MASK (0xFFFFFFFFU << CAN_FD_TXDATA11_TX_DATA11_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA12 */ +#define CAN_FD_TXDATA12_OFFSET (0x238U) +#define CAN_FD_TXDATA12_TX_DATA12_SHIFT (0U) +#define CAN_FD_TXDATA12_TX_DATA12_MASK (0xFFFFFFFFU << CAN_FD_TXDATA12_TX_DATA12_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA13 */ +#define CAN_FD_TXDATA13_OFFSET (0x23CU) +#define CAN_FD_TXDATA13_TX_DATA13_SHIFT (0U) +#define CAN_FD_TXDATA13_TX_DATA13_MASK (0xFFFFFFFFU << CAN_FD_TXDATA13_TX_DATA13_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA14 */ +#define CAN_FD_TXDATA14_OFFSET (0x240U) +#define CAN_FD_TXDATA14_TX_DATA14_SHIFT (0U) +#define CAN_FD_TXDATA14_TX_DATA14_MASK (0xFFFFFFFFU << CAN_FD_TXDATA14_TX_DATA14_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA15 */ +#define CAN_FD_TXDATA15_OFFSET (0x244U) +#define CAN_FD_TXDATA15_TX_DATA15_SHIFT (0U) +#define CAN_FD_TXDATA15_TX_DATA15_MASK (0xFFFFFFFFU << CAN_FD_TXDATA15_TX_DATA15_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXFRAMEINFO */ +#define CAN_FD_RXFRAMEINFO_OFFSET (0x300U) +#define CAN_FD_RXFRAMEINFO_RXDATA_LENGTH_SHIFT (0U) +#define CAN_FD_RXFRAMEINFO_RXDATA_LENGTH_MASK (0xFU << CAN_FD_RXFRAMEINFO_RXDATA_LENGTH_SHIFT) /* 0x0000000F */ +#define CAN_FD_RXFRAMEINFO_RX_BRS_SHIFT (4U) +#define CAN_FD_RXFRAMEINFO_RX_BRS_MASK (0x1U << CAN_FD_RXFRAMEINFO_RX_BRS_SHIFT) /* 0x00000010 */ +#define CAN_FD_RXFRAMEINFO_RX_FDF_SHIFT (5U) +#define CAN_FD_RXFRAMEINFO_RX_FDF_MASK (0x1U << CAN_FD_RXFRAMEINFO_RX_FDF_SHIFT) /* 0x00000020 */ +#define CAN_FD_RXFRAMEINFO_RX_RTR_SHIFT (6U) +#define CAN_FD_RXFRAMEINFO_RX_RTR_MASK (0x1U << CAN_FD_RXFRAMEINFO_RX_RTR_SHIFT) /* 0x00000040 */ +#define CAN_FD_RXFRAMEINFO_RXFRAME_FORMAT_SHIFT (7U) +#define CAN_FD_RXFRAMEINFO_RXFRAME_FORMAT_MASK (0x1U << CAN_FD_RXFRAMEINFO_RXFRAME_FORMAT_SHIFT) /* 0x00000080 */ +/* FD_RXID */ +#define CAN_FD_RXID_OFFSET (0x304U) +#define CAN_FD_RXID (0x0U) +#define CAN_FD_RXID_RX_ID_SHIFT (0U) +#define CAN_FD_RXID_RX_ID_MASK (0x1FFFFFFFU << CAN_FD_RXID_RX_ID_SHIFT) /* 0x1FFFFFFF */ +/* FD_RXTIMESTAMP */ +#define CAN_FD_RXTIMESTAMP_OFFSET (0x308U) +#define CAN_FD_RXTIMESTAMP (0x0U) +#define CAN_FD_RXTIMESTAMP_TIMESTAMP_SHIFT (0U) +#define CAN_FD_RXTIMESTAMP_TIMESTAMP_MASK (0xFFFFFFFFU << CAN_FD_RXTIMESTAMP_TIMESTAMP_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA0 */ +#define CAN_FD_RXDATA0_OFFSET (0x30CU) +#define CAN_FD_RXDATA0 (0x0U) +#define CAN_FD_RXDATA0_RX_DATA0_SHIFT (0U) +#define CAN_FD_RXDATA0_RX_DATA0_MASK (0xFFFFFFFFU << CAN_FD_RXDATA0_RX_DATA0_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA1 */ +#define CAN_FD_RXDATA1_OFFSET (0x310U) +#define CAN_FD_RXDATA1 (0x0U) +#define CAN_FD_RXDATA1_RX_DATA1_SHIFT (0U) +#define CAN_FD_RXDATA1_RX_DATA1_MASK (0xFFFFFFFFU << CAN_FD_RXDATA1_RX_DATA1_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA2 */ +#define CAN_FD_RXDATA2_OFFSET (0x314U) +#define CAN_FD_RXDATA2 (0x0U) +#define CAN_FD_RXDATA2_RX_DATA2_SHIFT (0U) +#define CAN_FD_RXDATA2_RX_DATA2_MASK (0xFFFFFFFFU << CAN_FD_RXDATA2_RX_DATA2_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA3 */ +#define CAN_FD_RXDATA3_OFFSET (0x318U) +#define CAN_FD_RXDATA3 (0x0U) +#define CAN_FD_RXDATA3_RX_DATA3_SHIFT (0U) +#define CAN_FD_RXDATA3_RX_DATA3_MASK (0xFFFFFFFFU << CAN_FD_RXDATA3_RX_DATA3_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA4 */ +#define CAN_FD_RXDATA4_OFFSET (0x31CU) +#define CAN_FD_RXDATA4 (0x0U) +#define CAN_FD_RXDATA4_RX_DATA4_SHIFT (0U) +#define CAN_FD_RXDATA4_RX_DATA4_MASK (0xFFFFFFFFU << CAN_FD_RXDATA4_RX_DATA4_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA5 */ +#define CAN_FD_RXDATA5_OFFSET (0x320U) +#define CAN_FD_RXDATA5 (0x0U) +#define CAN_FD_RXDATA5_RX_DATA5_SHIFT (0U) +#define CAN_FD_RXDATA5_RX_DATA5_MASK (0xFFFFFFFFU << CAN_FD_RXDATA5_RX_DATA5_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA6 */ +#define CAN_FD_RXDATA6_OFFSET (0x324U) +#define CAN_FD_RXDATA6 (0x0U) +#define CAN_FD_RXDATA6_RX_DATA6_SHIFT (0U) +#define CAN_FD_RXDATA6_RX_DATA6_MASK (0xFFFFFFFFU << CAN_FD_RXDATA6_RX_DATA6_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA7 */ +#define CAN_FD_RXDATA7_OFFSET (0x328U) +#define CAN_FD_RXDATA7 (0x0U) +#define CAN_FD_RXDATA7_RX_DATA7_SHIFT (0U) +#define CAN_FD_RXDATA7_RX_DATA7_MASK (0xFFFFFFFFU << CAN_FD_RXDATA7_RX_DATA7_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA8 */ +#define CAN_FD_RXDATA8_OFFSET (0x32CU) +#define CAN_FD_RXDATA8 (0x0U) +#define CAN_FD_RXDATA8_RX_DATA8_SHIFT (0U) +#define CAN_FD_RXDATA8_RX_DATA8_MASK (0xFFFFFFFFU << CAN_FD_RXDATA8_RX_DATA8_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA9 */ +#define CAN_FD_RXDATA9_OFFSET (0x330U) +#define CAN_FD_RXDATA9 (0x0U) +#define CAN_FD_RXDATA9_RX_DATA9_SHIFT (0U) +#define CAN_FD_RXDATA9_RX_DATA9_MASK (0xFFFFFFFFU << CAN_FD_RXDATA9_RX_DATA9_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA10 */ +#define CAN_FD_RXDATA10_OFFSET (0x334U) +#define CAN_FD_RXDATA10 (0x0U) +#define CAN_FD_RXDATA10_RX_DATA10_SHIFT (0U) +#define CAN_FD_RXDATA10_RX_DATA10_MASK (0xFFFFFFFFU << CAN_FD_RXDATA10_RX_DATA10_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA11 */ +#define CAN_FD_RXDATA11_OFFSET (0x338U) +#define CAN_FD_RXDATA11 (0x0U) +#define CAN_FD_RXDATA11_RX_DATA11_SHIFT (0U) +#define CAN_FD_RXDATA11_RX_DATA11_MASK (0xFFFFFFFFU << CAN_FD_RXDATA11_RX_DATA11_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA12 */ +#define CAN_FD_RXDATA12_OFFSET (0x33CU) +#define CAN_FD_RXDATA12 (0x0U) +#define CAN_FD_RXDATA12_RX_DATA12_SHIFT (0U) +#define CAN_FD_RXDATA12_RX_DATA12_MASK (0xFFFFFFFFU << CAN_FD_RXDATA12_RX_DATA12_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA13 */ +#define CAN_FD_RXDATA13_OFFSET (0x340U) +#define CAN_FD_RXDATA13 (0x0U) +#define CAN_FD_RXDATA13_RX_DATA13_SHIFT (0U) +#define CAN_FD_RXDATA13_RX_DATA13_MASK (0xFFFFFFFFU << CAN_FD_RXDATA13_RX_DATA13_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA14 */ +#define CAN_FD_RXDATA14_OFFSET (0x344U) +#define CAN_FD_RXDATA14 (0x0U) +#define CAN_FD_RXDATA14_RX_DATA14_SHIFT (0U) +#define CAN_FD_RXDATA14_RX_DATA14_MASK (0xFFFFFFFFU << CAN_FD_RXDATA14_RX_DATA14_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA15 */ +#define CAN_FD_RXDATA15_OFFSET (0x348U) +#define CAN_FD_RXDATA15 (0x0U) +#define CAN_FD_RXDATA15_RX_DATA15_SHIFT (0U) +#define CAN_FD_RXDATA15_RX_DATA15_MASK (0xFFFFFFFFU << CAN_FD_RXDATA15_RX_DATA15_SHIFT) /* 0xFFFFFFFF */ +/* RX_FIFO_RDATA */ +#define CAN_RX_FIFO_RDATA_OFFSET (0x400U) +#define CAN_RX_FIFO_RDATA (0x0U) +#define CAN_RX_FIFO_RDATA_RX_FIFO_RDATA_SHIFT (0U) +#define CAN_RX_FIFO_RDATA_RX_FIFO_RDATA_MASK (0xFFFFFFFFU << CAN_RX_FIFO_RDATA_RX_FIFO_RDATA_SHIFT) /* 0xFFFFFFFF */ +/* TXE_FIFO_RDATA */ +#define CAN_TXE_FIFO_RDATA_OFFSET (0x500U) +#define CAN_TXE_FIFO_RDATA (0x0U) +#define CAN_TXE_FIFO_RDATA_TXE_FIFO_RDATA_SHIFT (0U) +#define CAN_TXE_FIFO_RDATA_TXE_FIFO_RDATA_MASK (0xFFFFFFFFU << CAN_TXE_FIFO_RDATA_TXE_FIFO_RDATA_SHIFT) /* 0xFFFFFFFF */ +/******************************************WDT*******************************************/ +/* CR */ +#define WDT_CR_OFFSET (0x0U) +#define WDT_CR_WDT_EN_SHIFT (0U) +#define WDT_CR_WDT_EN_MASK (0x1U << WDT_CR_WDT_EN_SHIFT) /* 0x00000001 */ +#define WDT_CR_RESP_MODE_SHIFT (1U) +#define WDT_CR_RESP_MODE_MASK (0x1U << WDT_CR_RESP_MODE_SHIFT) /* 0x00000002 */ +#define WDT_CR_RST_PLUSE_LENGTH_SHIFT (2U) +#define WDT_CR_RST_PLUSE_LENGTH_MASK (0x7U << WDT_CR_RST_PLUSE_LENGTH_SHIFT) /* 0x0000001C */ +/* TORR */ +#define WDT_TORR_OFFSET (0x4U) +#define WDT_TORR_TIMEOUT_PERIOD_SHIFT (0U) +#define WDT_TORR_TIMEOUT_PERIOD_MASK (0xFU << WDT_TORR_TIMEOUT_PERIOD_SHIFT) /* 0x0000000F */ +/* CCVR */ +#define WDT_CCVR_OFFSET (0x8U) +#define WDT_CCVR (0xFFFFU) +#define WDT_CCVR_CUR_CNT_SHIFT (0U) +#define WDT_CCVR_CUR_CNT_MASK (0xFFFFFFFFU << WDT_CCVR_CUR_CNT_SHIFT) /* 0xFFFFFFFF */ +/* CRR */ +#define WDT_CRR_OFFSET (0xCU) +#define WDT_CRR_CNT_RESTART_SHIFT (0U) +#define WDT_CRR_CNT_RESTART_MASK (0xFFU << WDT_CRR_CNT_RESTART_SHIFT) /* 0x000000FF */ +/* STAT */ +#define WDT_STAT_OFFSET (0x10U) +#define WDT_STAT (0x0U) +#define WDT_STAT_WDT_STATUS_SHIFT (0U) +#define WDT_STAT_WDT_STATUS_MASK (0x1U << WDT_STAT_WDT_STATUS_SHIFT) /* 0x00000001 */ +/* EOI */ +#define WDT_EOI_OFFSET (0x14U) +#define WDT_EOI (0x0U) +#define WDT_EOI_WDT_INT_CLR_SHIFT (0U) +#define WDT_EOI_WDT_INT_CLR_MASK (0x1U << WDT_EOI_WDT_INT_CLR_SHIFT) /* 0x00000001 */ +/******************************************SPI*******************************************/ +/* CTRLR0 */ +#define SPI_CTRLR0_OFFSET (0x0U) +#define SPI_CTRLR0_DFS_SHIFT (0U) +#define SPI_CTRLR0_DFS_MASK (0x3U << SPI_CTRLR0_DFS_SHIFT) /* 0x00000003 */ +#define SPI_CTRLR0_CFS_SHIFT (2U) +#define SPI_CTRLR0_CFS_MASK (0xFU << SPI_CTRLR0_CFS_SHIFT) /* 0x0000003C */ +#define SPI_CTRLR0_SCPH_SHIFT (6U) +#define SPI_CTRLR0_SCPH_MASK (0x1U << SPI_CTRLR0_SCPH_SHIFT) /* 0x00000040 */ +#define SPI_CTRLR0_SCPOL_SHIFT (7U) +#define SPI_CTRLR0_SCPOL_MASK (0x1U << SPI_CTRLR0_SCPOL_SHIFT) /* 0x00000080 */ +#define SPI_CTRLR0_CSM_SHIFT (8U) +#define SPI_CTRLR0_CSM_MASK (0x3U << SPI_CTRLR0_CSM_SHIFT) /* 0x00000300 */ +#define SPI_CTRLR0_SSD_SHIFT (10U) +#define SPI_CTRLR0_SSD_MASK (0x1U << SPI_CTRLR0_SSD_SHIFT) /* 0x00000400 */ +#define SPI_CTRLR0_EM_SHIFT (11U) +#define SPI_CTRLR0_EM_MASK (0x1U << SPI_CTRLR0_EM_SHIFT) /* 0x00000800 */ +#define SPI_CTRLR0_FBM_SHIFT (12U) +#define SPI_CTRLR0_FBM_MASK (0x1U << SPI_CTRLR0_FBM_SHIFT) /* 0x00001000 */ +#define SPI_CTRLR0_BHT_SHIFT (13U) +#define SPI_CTRLR0_BHT_MASK (0x1U << SPI_CTRLR0_BHT_SHIFT) /* 0x00002000 */ +#define SPI_CTRLR0_RSD_SHIFT (14U) +#define SPI_CTRLR0_RSD_MASK (0x3U << SPI_CTRLR0_RSD_SHIFT) /* 0x0000C000 */ +#define SPI_CTRLR0_FRF_SHIFT (16U) +#define SPI_CTRLR0_FRF_MASK (0x3U << SPI_CTRLR0_FRF_SHIFT) /* 0x00030000 */ +#define SPI_CTRLR0_XFM_SHIFT (18U) +#define SPI_CTRLR0_XFM_MASK (0x3U << SPI_CTRLR0_XFM_SHIFT) /* 0x000C0000 */ +#define SPI_CTRLR0_OPM_SHIFT (20U) +#define SPI_CTRLR0_OPM_MASK (0x1U << SPI_CTRLR0_OPM_SHIFT) /* 0x00100000 */ +#define SPI_CTRLR0_MTM_SHIFT (21U) +#define SPI_CTRLR0_MTM_MASK (0x1U << SPI_CTRLR0_MTM_SHIFT) /* 0x00200000 */ +#define SPI_CTRLR0_SM_SHIFT (22U) +#define SPI_CTRLR0_SM_MASK (0x1U << SPI_CTRLR0_SM_SHIFT) /* 0x00400000 */ +#define SPI_CTRLR0_SOI_SHIFT (23U) +#define SPI_CTRLR0_SOI_MASK (0x3U << SPI_CTRLR0_SOI_SHIFT) /* 0x01800000 */ +#define SPI_CTRLR0_LBK_SHIFT (25U) +#define SPI_CTRLR0_LBK_MASK (0x1U << SPI_CTRLR0_LBK_SHIFT) /* 0x02000000 */ +/* CTRLR1 */ +#define SPI_CTRLR1_OFFSET (0x4U) +#define SPI_CTRLR1_NDM_SHIFT (0U) +#define SPI_CTRLR1_NDM_MASK (0xFFFFFFFFU << SPI_CTRLR1_NDM_SHIFT) /* 0xFFFFFFFF */ +/* ENR */ +#define SPI_ENR_OFFSET (0x8U) +#define SPI_ENR_ENR_SHIFT (0U) +#define SPI_ENR_ENR_MASK (0x1U << SPI_ENR_ENR_SHIFT) /* 0x00000001 */ +/* SER */ +#define SPI_SER_OFFSET (0xCU) +#define SPI_SER_SER_SHIFT (0U) +#define SPI_SER_SER_MASK (0x3U << SPI_SER_SER_SHIFT) /* 0x00000003 */ +/* BAUDR */ +#define SPI_BAUDR_OFFSET (0x10U) +#define SPI_BAUDR_BAUDR_SHIFT (0U) +#define SPI_BAUDR_BAUDR_MASK (0xFFFFU << SPI_BAUDR_BAUDR_SHIFT) /* 0x0000FFFF */ +/* TXFTLR */ +#define SPI_TXFTLR_OFFSET (0x14U) +#define SPI_TXFTLR_XFTLR_SHIFT (0U) +#define SPI_TXFTLR_XFTLR_MASK (0x3FU << SPI_TXFTLR_XFTLR_SHIFT) /* 0x0000003F */ +/* RXFTLR */ +#define SPI_RXFTLR_OFFSET (0x18U) +#define SPI_RXFTLR_RXFTLR_SHIFT (0U) +#define SPI_RXFTLR_RXFTLR_MASK (0x3FU << SPI_RXFTLR_RXFTLR_SHIFT) /* 0x0000003F */ +/* TXFLR */ +#define SPI_TXFLR_OFFSET (0x1CU) +#define SPI_TXFLR (0x0U) +#define SPI_TXFLR_TXFLR_SHIFT (0U) +#define SPI_TXFLR_TXFLR_MASK (0x7FU << SPI_TXFLR_TXFLR_SHIFT) /* 0x0000007F */ +/* RXFLR */ +#define SPI_RXFLR_OFFSET (0x20U) +#define SPI_RXFLR (0x0U) +#define SPI_RXFLR_RXFLR_SHIFT (0U) +#define SPI_RXFLR_RXFLR_MASK (0x7FU << SPI_RXFLR_RXFLR_SHIFT) /* 0x0000007F */ +/* SR */ +#define SPI_SR_OFFSET (0x24U) +#define SPI_SR (0x4CU) +#define SPI_SR_BSF_SHIFT (0U) +#define SPI_SR_BSF_MASK (0x1U << SPI_SR_BSF_SHIFT) /* 0x00000001 */ +#define SPI_SR_TFF_SHIFT (1U) +#define SPI_SR_TFF_MASK (0x1U << SPI_SR_TFF_SHIFT) /* 0x00000002 */ +#define SPI_SR_TFE_SHIFT (2U) +#define SPI_SR_TFE_MASK (0x1U << SPI_SR_TFE_SHIFT) /* 0x00000004 */ +#define SPI_SR_RFE_SHIFT (3U) +#define SPI_SR_RFE_MASK (0x1U << SPI_SR_RFE_SHIFT) /* 0x00000008 */ +#define SPI_SR_RFF_SHIFT (4U) +#define SPI_SR_RFF_MASK (0x1U << SPI_SR_RFF_SHIFT) /* 0x00000010 */ +#define SPI_SR_STB_SHIFT (5U) +#define SPI_SR_STB_MASK (0x1U << SPI_SR_STB_SHIFT) /* 0x00000020 */ +#define SPI_SR_SSI_SHIFT (6U) +#define SPI_SR_SSI_MASK (0x1U << SPI_SR_SSI_SHIFT) /* 0x00000040 */ +/* IPR */ +#define SPI_IPR_OFFSET (0x28U) +#define SPI_IPR_IPR_SHIFT (0U) +#define SPI_IPR_IPR_MASK (0x1U << SPI_IPR_IPR_SHIFT) /* 0x00000001 */ +/* IMR */ +#define SPI_IMR_OFFSET (0x2CU) +#define SPI_IMR_TFEIM_SHIFT (0U) +#define SPI_IMR_TFEIM_MASK (0x1U << SPI_IMR_TFEIM_SHIFT) /* 0x00000001 */ +#define SPI_IMR_TFOIM_SHIFT (1U) +#define SPI_IMR_TFOIM_MASK (0x1U << SPI_IMR_TFOIM_SHIFT) /* 0x00000002 */ +#define SPI_IMR_RFUIM_SHIFT (2U) +#define SPI_IMR_RFUIM_MASK (0x1U << SPI_IMR_RFUIM_SHIFT) /* 0x00000004 */ +#define SPI_IMR_RFOIM_SHIFT (3U) +#define SPI_IMR_RFOIM_MASK (0x1U << SPI_IMR_RFOIM_SHIFT) /* 0x00000008 */ +#define SPI_IMR_RFFIM_SHIFT (4U) +#define SPI_IMR_RFFIM_MASK (0x1U << SPI_IMR_RFFIM_SHIFT) /* 0x00000010 */ +#define SPI_IMR_TOIM_SHIFT (5U) +#define SPI_IMR_TOIM_MASK (0x1U << SPI_IMR_TOIM_SHIFT) /* 0x00000020 */ +#define SPI_IMR_SSPIM_SHIFT (6U) +#define SPI_IMR_SSPIM_MASK (0x1U << SPI_IMR_SSPIM_SHIFT) /* 0x00000040 */ +#define SPI_IMR_TXFIM_SHIFT (7U) +#define SPI_IMR_TXFIM_MASK (0x1U << SPI_IMR_TXFIM_SHIFT) /* 0x00000080 */ +/* ISR */ +#define SPI_ISR_OFFSET (0x30U) +#define SPI_ISR_TFEIS_SHIFT (0U) +#define SPI_ISR_TFEIS_MASK (0x1U << SPI_ISR_TFEIS_SHIFT) /* 0x00000001 */ +#define SPI_ISR_TFOIS_SHIFT (1U) +#define SPI_ISR_TFOIS_MASK (0x1U << SPI_ISR_TFOIS_SHIFT) /* 0x00000002 */ +#define SPI_ISR_RFUIS_SHIFT (2U) +#define SPI_ISR_RFUIS_MASK (0x1U << SPI_ISR_RFUIS_SHIFT) /* 0x00000004 */ +#define SPI_ISR_RFOIS_SHIFT (3U) +#define SPI_ISR_RFOIS_MASK (0x1U << SPI_ISR_RFOIS_SHIFT) /* 0x00000008 */ +#define SPI_ISR_RFFIS_SHIFT (4U) +#define SPI_ISR_RFFIS_MASK (0x1U << SPI_ISR_RFFIS_SHIFT) /* 0x00000010 */ +#define SPI_ISR_TOIS_SHIFT (5U) +#define SPI_ISR_TOIS_MASK (0x1U << SPI_ISR_TOIS_SHIFT) /* 0x00000020 */ +#define SPI_ISR_SSPIS_SHIFT (6U) +#define SPI_ISR_SSPIS_MASK (0x1U << SPI_ISR_SSPIS_SHIFT) /* 0x00000040 */ +#define SPI_ISR_TXFIS_SHIFT (7U) +#define SPI_ISR_TXFIS_MASK (0x1U << SPI_ISR_TXFIS_SHIFT) /* 0x00000080 */ +/* RISR */ +#define SPI_RISR_OFFSET (0x34U) +#define SPI_RISR_TFERIS_SHIFT (0U) +#define SPI_RISR_TFERIS_MASK (0x1U << SPI_RISR_TFERIS_SHIFT) /* 0x00000001 */ +#define SPI_RISR_TFORIS_SHIFT (1U) +#define SPI_RISR_TFORIS_MASK (0x1U << SPI_RISR_TFORIS_SHIFT) /* 0x00000002 */ +#define SPI_RISR_RFURIS_SHIFT (2U) +#define SPI_RISR_RFURIS_MASK (0x1U << SPI_RISR_RFURIS_SHIFT) /* 0x00000004 */ +#define SPI_RISR_RFORIS_SHIFT (3U) +#define SPI_RISR_RFORIS_MASK (0x1U << SPI_RISR_RFORIS_SHIFT) /* 0x00000008 */ +#define SPI_RISR_RFFRIS_SHIFT (4U) +#define SPI_RISR_RFFRIS_MASK (0x1U << SPI_RISR_RFFRIS_SHIFT) /* 0x00000010 */ +#define SPI_RISR_TORIS_SHIFT (5U) +#define SPI_RISR_TORIS_MASK (0x1U << SPI_RISR_TORIS_SHIFT) /* 0x00000020 */ +#define SPI_RISR_SSPRIS_SHIFT (6U) +#define SPI_RISR_SSPRIS_MASK (0x1U << SPI_RISR_SSPRIS_SHIFT) /* 0x00000040 */ +#define SPI_RISR_TXFRIS_SHIFT (7U) +#define SPI_RISR_TXFRIS_MASK (0x1U << SPI_RISR_TXFRIS_SHIFT) /* 0x00000080 */ +/* ICR */ +#define SPI_ICR_OFFSET (0x38U) +#define SPI_ICR_CCI_SHIFT (0U) +#define SPI_ICR_CCI_MASK (0x1U << SPI_ICR_CCI_SHIFT) /* 0x00000001 */ +#define SPI_ICR_CRFUI_SHIFT (1U) +#define SPI_ICR_CRFUI_MASK (0x1U << SPI_ICR_CRFUI_SHIFT) /* 0x00000002 */ +#define SPI_ICR_CRFOI_SHIFT (2U) +#define SPI_ICR_CRFOI_MASK (0x1U << SPI_ICR_CRFOI_SHIFT) /* 0x00000004 */ +#define SPI_ICR_CTFOI_SHIFT (3U) +#define SPI_ICR_CTFOI_MASK (0x1U << SPI_ICR_CTFOI_SHIFT) /* 0x00000008 */ +#define SPI_ICR_CTOI_SHIFT (4U) +#define SPI_ICR_CTOI_MASK (0x1U << SPI_ICR_CTOI_SHIFT) /* 0x00000010 */ +#define SPI_ICR_CSSPI_SHIFT (5U) +#define SPI_ICR_CSSPI_MASK (0x1U << SPI_ICR_CSSPI_SHIFT) /* 0x00000020 */ +#define SPI_ICR_CTXFI_SHIFT (6U) +#define SPI_ICR_CTXFI_MASK (0x1U << SPI_ICR_CTXFI_SHIFT) /* 0x00000040 */ +/* DMACR */ +#define SPI_DMACR_OFFSET (0x3CU) +#define SPI_DMACR_RDE_SHIFT (0U) +#define SPI_DMACR_RDE_MASK (0x1U << SPI_DMACR_RDE_SHIFT) /* 0x00000001 */ +#define SPI_DMACR_TDE_SHIFT (1U) +#define SPI_DMACR_TDE_MASK (0x1U << SPI_DMACR_TDE_SHIFT) /* 0x00000002 */ +/* DMATDLR */ +#define SPI_DMATDLR_OFFSET (0x40U) +#define SPI_DMATDLR_TDL_SHIFT (0U) +#define SPI_DMATDLR_TDL_MASK (0x3FU << SPI_DMATDLR_TDL_SHIFT) /* 0x0000003F */ +/* DMARDLR */ +#define SPI_DMARDLR_OFFSET (0x44U) +#define SPI_DMARDLR_RDL_SHIFT (0U) +#define SPI_DMARDLR_RDL_MASK (0x3FU << SPI_DMARDLR_RDL_SHIFT) /* 0x0000003F */ +/* TIMEOUT */ +#define SPI_TIMEOUT_OFFSET (0x4CU) +#define SPI_TIMEOUT_TOV_SHIFT (0U) +#define SPI_TIMEOUT_TOV_MASK (0xFFFFU << SPI_TIMEOUT_TOV_SHIFT) /* 0x0000FFFF */ +#define SPI_TIMEOUT_TOE_SHIFT (16U) +#define SPI_TIMEOUT_TOE_MASK (0x1U << SPI_TIMEOUT_TOE_SHIFT) /* 0x00010000 */ +/* BYPASS */ +#define SPI_BYPASS_OFFSET (0x50U) +#define SPI_BYPASS_BYEN_SHIFT (0U) +#define SPI_BYPASS_BYEN_MASK (0x1U << SPI_BYPASS_BYEN_SHIFT) /* 0x00000001 */ +#define SPI_BYPASS_FBM_SHIFT (1U) +#define SPI_BYPASS_FBM_MASK (0x1U << SPI_BYPASS_FBM_SHIFT) /* 0x00000002 */ +#define SPI_BYPASS_END_SHIFT (2U) +#define SPI_BYPASS_END_MASK (0x1U << SPI_BYPASS_END_SHIFT) /* 0x00000004 */ +#define SPI_BYPASS_RXCP_SHIFT (3U) +#define SPI_BYPASS_RXCP_MASK (0x1U << SPI_BYPASS_RXCP_SHIFT) /* 0x00000008 */ +#define SPI_BYPASS_TXCP_SHIFT (4U) +#define SPI_BYPASS_TXCP_MASK (0x1U << SPI_BYPASS_TXCP_SHIFT) /* 0x00000010 */ +/* TXDR */ +#define SPI_TXDR_OFFSET (0x400U) +#define SPI_TXDR_TXDR_SHIFT (0U) +#define SPI_TXDR_TXDR_MASK (0xFFFFU << SPI_TXDR_TXDR_SHIFT) /* 0x0000FFFF */ +/* RXDR */ +#define SPI_RXDR_OFFSET (0x800U) +#define SPI_RXDR (0x0U) +#define SPI_RXDR_RXDR_SHIFT (0U) +#define SPI_RXDR_RXDR_MASK (0xFFFFU << SPI_RXDR_RXDR_SHIFT) /* 0x0000FFFF */ +/*****************************************TSADC******************************************/ +/* USER_CON */ +#define TSADC_USER_CON_OFFSET (0x0U) +#define TSADC_USER_CON_ADC_INPUT_SRC_SEL_SHIFT (0U) +#define TSADC_USER_CON_ADC_INPUT_SRC_SEL_MASK (0x7U << TSADC_USER_CON_ADC_INPUT_SRC_SEL_SHIFT) /* 0x00000007 */ +#define TSADC_USER_CON_ADC_POWER_CTRL_SHIFT (3U) +#define TSADC_USER_CON_ADC_POWER_CTRL_MASK (0x1U << TSADC_USER_CON_ADC_POWER_CTRL_SHIFT) /* 0x00000008 */ +#define TSADC_USER_CON_START_MODE_SHIFT (4U) +#define TSADC_USER_CON_START_MODE_MASK (0x1U << TSADC_USER_CON_START_MODE_SHIFT) /* 0x00000010 */ +#define TSADC_USER_CON_START_SHIFT (5U) +#define TSADC_USER_CON_START_MASK (0x1U << TSADC_USER_CON_START_SHIFT) /* 0x00000020 */ +#define TSADC_USER_CON_INTER_PD_SOC_SHIFT (6U) +#define TSADC_USER_CON_INTER_PD_SOC_MASK (0x1FFU << TSADC_USER_CON_INTER_PD_SOC_SHIFT) /* 0x00007FC0 */ +#define TSADC_USER_CON_ADC_STATUS_SHIFT (15U) +#define TSADC_USER_CON_ADC_STATUS_MASK (0x1U << TSADC_USER_CON_ADC_STATUS_SHIFT) /* 0x00008000 */ +/* AUTO_CON */ +#define TSADC_AUTO_CON_OFFSET (0x4U) +#define TSADC_AUTO_CON_AUTO_EN_SHIFT (0U) +#define TSADC_AUTO_CON_AUTO_EN_MASK (0x1U << TSADC_AUTO_CON_AUTO_EN_SHIFT) /* 0x00000001 */ +#define TSADC_AUTO_CON_TSADC_Q_SEL_SHIFT (1U) +#define TSADC_AUTO_CON_TSADC_Q_SEL_MASK (0x1U << TSADC_AUTO_CON_TSADC_Q_SEL_SHIFT) /* 0x00000002 */ +#define TSADC_AUTO_CON_SRC0_EN_SHIFT (4U) +#define TSADC_AUTO_CON_SRC0_EN_MASK (0x1U << TSADC_AUTO_CON_SRC0_EN_SHIFT) /* 0x00000010 */ +#define TSADC_AUTO_CON_SRC1_EN_SHIFT (5U) +#define TSADC_AUTO_CON_SRC1_EN_MASK (0x1U << TSADC_AUTO_CON_SRC1_EN_SHIFT) /* 0x00000020 */ +#define TSADC_AUTO_CON_TSHUT_PROLARITY_SHIFT (8U) +#define TSADC_AUTO_CON_TSHUT_PROLARITY_MASK (0x1U << TSADC_AUTO_CON_TSHUT_PROLARITY_SHIFT) /* 0x00000100 */ +#define TSADC_AUTO_CON_SRC0_LT_EN_SHIFT (12U) +#define TSADC_AUTO_CON_SRC0_LT_EN_MASK (0x1U << TSADC_AUTO_CON_SRC0_LT_EN_SHIFT) /* 0x00001000 */ +#define TSADC_AUTO_CON_SRC1_LT_EN_SHIFT (13U) +#define TSADC_AUTO_CON_SRC1_LT_EN_MASK (0x1U << TSADC_AUTO_CON_SRC1_LT_EN_SHIFT) /* 0x00002000 */ +#define TSADC_AUTO_CON_AUTO_STATUS_SHIFT (16U) +#define TSADC_AUTO_CON_AUTO_STATUS_MASK (0x1U << TSADC_AUTO_CON_AUTO_STATUS_SHIFT) /* 0x00010000 */ +#define TSADC_AUTO_CON_SAMPLE_DLY_SEL_SHIFT (17U) +#define TSADC_AUTO_CON_SAMPLE_DLY_SEL_MASK (0x1U << TSADC_AUTO_CON_SAMPLE_DLY_SEL_SHIFT) /* 0x00020000 */ +#define TSADC_AUTO_CON_LAST_TSHUT_2GPIO_SHIFT (24U) +#define TSADC_AUTO_CON_LAST_TSHUT_2GPIO_MASK (0x1U << TSADC_AUTO_CON_LAST_TSHUT_2GPIO_SHIFT) /* 0x01000000 */ +#define TSADC_AUTO_CON_LAST_TSHUT_2CRU_SHIFT (25U) +#define TSADC_AUTO_CON_LAST_TSHUT_2CRU_MASK (0x1U << TSADC_AUTO_CON_LAST_TSHUT_2CRU_SHIFT) /* 0x02000000 */ +/* INT_EN */ +#define TSADC_INT_EN_OFFSET (0x8U) +#define TSADC_INT_EN_HT_INTEN_SRC0_SHIFT (0U) +#define TSADC_INT_EN_HT_INTEN_SRC0_MASK (0x1U << TSADC_INT_EN_HT_INTEN_SRC0_SHIFT) /* 0x00000001 */ +#define TSADC_INT_EN_HT_INTEN_SRC1_SHIFT (1U) +#define TSADC_INT_EN_HT_INTEN_SRC1_MASK (0x1U << TSADC_INT_EN_HT_INTEN_SRC1_SHIFT) /* 0x00000002 */ +#define TSADC_INT_EN_TSHUT_2GPIO_EN_SRC0_SHIFT (4U) +#define TSADC_INT_EN_TSHUT_2GPIO_EN_SRC0_MASK (0x1U << TSADC_INT_EN_TSHUT_2GPIO_EN_SRC0_SHIFT) /* 0x00000010 */ +#define TSADC_INT_EN_TSHUT_2GPIO_EN_SRC1_SHIFT (5U) +#define TSADC_INT_EN_TSHUT_2GPIO_EN_SRC1_MASK (0x1U << TSADC_INT_EN_TSHUT_2GPIO_EN_SRC1_SHIFT) /* 0x00000020 */ +#define TSADC_INT_EN_TSHUT_2CRU_EN_SRC0_SHIFT (8U) +#define TSADC_INT_EN_TSHUT_2CRU_EN_SRC0_MASK (0x1U << TSADC_INT_EN_TSHUT_2CRU_EN_SRC0_SHIFT) /* 0x00000100 */ +#define TSADC_INT_EN_TSHUT_2CRU_EN_SRC1_SHIFT (9U) +#define TSADC_INT_EN_TSHUT_2CRU_EN_SRC1_MASK (0x1U << TSADC_INT_EN_TSHUT_2CRU_EN_SRC1_SHIFT) /* 0x00000200 */ +#define TSADC_INT_EN_LT_INTEN_SRC0_SHIFT (12U) +#define TSADC_INT_EN_LT_INTEN_SRC0_MASK (0x1U << TSADC_INT_EN_LT_INTEN_SRC0_SHIFT) /* 0x00001000 */ +#define TSADC_INT_EN_LT_INTEN_SRC1_SHIFT (13U) +#define TSADC_INT_EN_LT_INTEN_SRC1_MASK (0x1U << TSADC_INT_EN_LT_INTEN_SRC1_SHIFT) /* 0x00002000 */ +#define TSADC_INT_EN_EOC_INT_EN_SHIFT (16U) +#define TSADC_INT_EN_EOC_INT_EN_MASK (0x1U << TSADC_INT_EN_EOC_INT_EN_SHIFT) /* 0x00010000 */ +/* INT_PD */ +#define TSADC_INT_PD_OFFSET (0xCU) +#define TSADC_INT_PD_HT_IRQ_SRC0_SHIFT (0U) +#define TSADC_INT_PD_HT_IRQ_SRC0_MASK (0x1U << TSADC_INT_PD_HT_IRQ_SRC0_SHIFT) /* 0x00000001 */ +#define TSADC_INT_PD_HT_IRQ_SRC1_SHIFT (1U) +#define TSADC_INT_PD_HT_IRQ_SRC1_MASK (0x1U << TSADC_INT_PD_HT_IRQ_SRC1_SHIFT) /* 0x00000002 */ +#define TSADC_INT_PD_TSHUT_O_SRC0_SHIFT (4U) +#define TSADC_INT_PD_TSHUT_O_SRC0_MASK (0x1U << TSADC_INT_PD_TSHUT_O_SRC0_SHIFT) /* 0x00000010 */ +#define TSADC_INT_PD_TSHUT_O_SRC1_SHIFT (5U) +#define TSADC_INT_PD_TSHUT_O_SRC1_MASK (0x1U << TSADC_INT_PD_TSHUT_O_SRC1_SHIFT) /* 0x00000020 */ +#define TSADC_INT_PD_LT_IRQ_SRC0_SHIFT (12U) +#define TSADC_INT_PD_LT_IRQ_SRC0_MASK (0x1U << TSADC_INT_PD_LT_IRQ_SRC0_SHIFT) /* 0x00001000 */ +#define TSADC_INT_PD_LT_IRQ_SRC1_SHIFT (13U) +#define TSADC_INT_PD_LT_IRQ_SRC1_MASK (0x1U << TSADC_INT_PD_LT_IRQ_SRC1_SHIFT) /* 0x00002000 */ +#define TSADC_INT_PD_EOC_INT_PD_SHIFT (16U) +#define TSADC_INT_PD_EOC_INT_PD_MASK (0x1U << TSADC_INT_PD_EOC_INT_PD_SHIFT) /* 0x00010000 */ +/* DATA0 */ +#define TSADC_DATA0_OFFSET (0x20U) +#define TSADC_DATA0 (0x0U) +#define TSADC_DATA0_ADC_DATA_SHIFT (0U) +#define TSADC_DATA0_ADC_DATA_MASK (0xFFFU << TSADC_DATA0_ADC_DATA_SHIFT) /* 0x00000FFF */ +/* DATA1 */ +#define TSADC_DATA1_OFFSET (0x24U) +#define TSADC_DATA1 (0x0U) +#define TSADC_DATA1_ADC_DATA_SHIFT (0U) +#define TSADC_DATA1_ADC_DATA_MASK (0xFFFU << TSADC_DATA1_ADC_DATA_SHIFT) /* 0x00000FFF */ +/* COMP0_INT */ +#define TSADC_COMP0_INT_OFFSET (0x30U) +#define TSADC_COMP0_INT_TSADC_COMP_SRC0_SHIFT (0U) +#define TSADC_COMP0_INT_TSADC_COMP_SRC0_MASK (0xFFFU << TSADC_COMP0_INT_TSADC_COMP_SRC0_SHIFT) /* 0x00000FFF */ +/* COMP1_INT */ +#define TSADC_COMP1_INT_OFFSET (0x34U) +#define TSADC_COMP1_INT_TSADC_COMP_SRC1_SHIFT (0U) +#define TSADC_COMP1_INT_TSADC_COMP_SRC1_MASK (0xFFFU << TSADC_COMP1_INT_TSADC_COMP_SRC1_SHIFT) /* 0x00000FFF */ +/* COMP0_SHUT */ +#define TSADC_COMP0_SHUT_OFFSET (0x40U) +#define TSADC_COMP0_SHUT_TSADC_COMP_SRC0_SHIFT (0U) +#define TSADC_COMP0_SHUT_TSADC_COMP_SRC0_MASK (0xFFFU << TSADC_COMP0_SHUT_TSADC_COMP_SRC0_SHIFT) /* 0x00000FFF */ +/* COMP1_SHUT */ +#define TSADC_COMP1_SHUT_OFFSET (0x44U) +#define TSADC_COMP1_SHUT_TSADC_COMP_SRC1_SHIFT (0U) +#define TSADC_COMP1_SHUT_TSADC_COMP_SRC1_MASK (0xFFFU << TSADC_COMP1_SHUT_TSADC_COMP_SRC1_SHIFT) /* 0x00000FFF */ +/* HIGHT_INT_DEBOUNCE */ +#define TSADC_HIGHT_INT_DEBOUNCE_OFFSET (0x60U) +#define TSADC_HIGHT_INT_DEBOUNCE_DEBOUNCE_SHIFT (0U) +#define TSADC_HIGHT_INT_DEBOUNCE_DEBOUNCE_MASK (0xFFU << TSADC_HIGHT_INT_DEBOUNCE_DEBOUNCE_SHIFT) /* 0x000000FF */ +/* HIGHT_TSHUT_DEBOUNCE */ +#define TSADC_HIGHT_TSHUT_DEBOUNCE_OFFSET (0x64U) +#define TSADC_HIGHT_TSHUT_DEBOUNCE_DEBOUNCE_SHIFT (0U) +#define TSADC_HIGHT_TSHUT_DEBOUNCE_DEBOUNCE_MASK (0xFFU << TSADC_HIGHT_TSHUT_DEBOUNCE_DEBOUNCE_SHIFT) /* 0x000000FF */ +/* AUTO_PERIOD */ +#define TSADC_AUTO_PERIOD_OFFSET (0x68U) +#define TSADC_AUTO_PERIOD_AUTO_PERIOD_SHIFT (0U) +#define TSADC_AUTO_PERIOD_AUTO_PERIOD_MASK (0xFFFFFFFFU << TSADC_AUTO_PERIOD_AUTO_PERIOD_SHIFT) /* 0xFFFFFFFF */ +/* AUTO_PERIOD_HT */ +#define TSADC_AUTO_PERIOD_HT_OFFSET (0x6CU) +#define TSADC_AUTO_PERIOD_HT_AUTO_PERIOD_SHIFT (0U) +#define TSADC_AUTO_PERIOD_HT_AUTO_PERIOD_MASK (0xFFFFFFFFU << TSADC_AUTO_PERIOD_HT_AUTO_PERIOD_SHIFT) /* 0xFFFFFFFF */ +/* COMP0_LOW_INT */ +#define TSADC_COMP0_LOW_INT_OFFSET (0x80U) +#define TSADC_COMP0_LOW_INT_TSADC_COMP_SRC0_SHIFT (0U) +#define TSADC_COMP0_LOW_INT_TSADC_COMP_SRC0_MASK (0xFFFU << TSADC_COMP0_LOW_INT_TSADC_COMP_SRC0_SHIFT) /* 0x00000FFF */ +/* COMP1_LOW_INT */ +#define TSADC_COMP1_LOW_INT_OFFSET (0x84U) +#define TSADC_COMP1_LOW_INT_TSADC_COMP_SRC1_SHIFT (0U) +#define TSADC_COMP1_LOW_INT_TSADC_COMP_SRC1_MASK (0xFFFU << TSADC_COMP1_LOW_INT_TSADC_COMP_SRC1_SHIFT) /* 0x00000FFF */ +/*****************************************SARADC*****************************************/ +/* DATA */ +#define SARADC_DATA_OFFSET (0x0U) +#define SARADC_DATA (0x0U) +#define SARADC_DATA_ADC_DATA_SHIFT (0U) +#define SARADC_DATA_ADC_DATA_MASK (0x3FFU << SARADC_DATA_ADC_DATA_SHIFT) /* 0x000003FF */ +/* STAS */ +#define SARADC_STAS_OFFSET (0x4U) +#define SARADC_STAS (0x0U) +#define SARADC_STAS_ADC_STATUS_SHIFT (0U) +#define SARADC_STAS_ADC_STATUS_MASK (0x1U << SARADC_STAS_ADC_STATUS_SHIFT) /* 0x00000001 */ +/* CTRL */ +#define SARADC_CTRL_OFFSET (0x8U) +#define SARADC_CTRL_ADC_INPUT_SRC_SEL_SHIFT (0U) +#define SARADC_CTRL_ADC_INPUT_SRC_SEL_MASK (0x7U << SARADC_CTRL_ADC_INPUT_SRC_SEL_SHIFT) /* 0x00000007 */ +#define SARADC_CTRL_ADC_POWER_CTRL_SHIFT (3U) +#define SARADC_CTRL_ADC_POWER_CTRL_MASK (0x1U << SARADC_CTRL_ADC_POWER_CTRL_SHIFT) /* 0x00000008 */ +#define SARADC_CTRL_INT_EN_SHIFT (5U) +#define SARADC_CTRL_INT_EN_MASK (0x1U << SARADC_CTRL_INT_EN_SHIFT) /* 0x00000020 */ +#define SARADC_CTRL_INT_STATUS_SHIFT (6U) +#define SARADC_CTRL_INT_STATUS_MASK (0x1U << SARADC_CTRL_INT_STATUS_SHIFT) /* 0x00000040 */ +/* DLY_PU_SOC */ +#define SARADC_DLY_PU_SOC_OFFSET (0xCU) +#define SARADC_DLY_PU_SOC_DLY_PU_SOC_SHIFT (0U) +#define SARADC_DLY_PU_SOC_DLY_PU_SOC_MASK (0x3FU << SARADC_DLY_PU_SOC_DLY_PU_SOC_SHIFT) /* 0x0000003F */ +/******************************************MBOX******************************************/ +/* A2B_INTEN */ +#define MBOX_A2B_INTEN_OFFSET (0x0U) +#define MBOX_A2B_INTEN_INT0_SHIFT (0U) +#define MBOX_A2B_INTEN_INT0_MASK (0x1U << MBOX_A2B_INTEN_INT0_SHIFT) /* 0x00000001 */ +#define MBOX_A2B_INTEN_INT1_SHIFT (1U) +#define MBOX_A2B_INTEN_INT1_MASK (0x1U << MBOX_A2B_INTEN_INT1_SHIFT) /* 0x00000002 */ +#define MBOX_A2B_INTEN_INT2_SHIFT (2U) +#define MBOX_A2B_INTEN_INT2_MASK (0x1U << MBOX_A2B_INTEN_INT2_SHIFT) /* 0x00000004 */ +#define MBOX_A2B_INTEN_INT3_SHIFT (3U) +#define MBOX_A2B_INTEN_INT3_MASK (0x1U << MBOX_A2B_INTEN_INT3_SHIFT) /* 0x00000008 */ +/* A2B_STATUS */ +#define MBOX_A2B_STATUS_OFFSET (0x4U) +#define MBOX_A2B_STATUS_INT0_SHIFT (0U) +#define MBOX_A2B_STATUS_INT0_MASK (0x1U << MBOX_A2B_STATUS_INT0_SHIFT) /* 0x00000001 */ +#define MBOX_A2B_STATUS_INT1_SHIFT (1U) +#define MBOX_A2B_STATUS_INT1_MASK (0x1U << MBOX_A2B_STATUS_INT1_SHIFT) /* 0x00000002 */ +#define MBOX_A2B_STATUS_INT2_SHIFT (2U) +#define MBOX_A2B_STATUS_INT2_MASK (0x1U << MBOX_A2B_STATUS_INT2_SHIFT) /* 0x00000004 */ +#define MBOX_A2B_STATUS_INT3_SHIFT (3U) +#define MBOX_A2B_STATUS_INT3_MASK (0x1U << MBOX_A2B_STATUS_INT3_SHIFT) /* 0x00000008 */ +/* A2B_CMD_0 */ +#define MBOX_A2B_CMD_0_OFFSET (0x8U) +#define MBOX_A2B_CMD_0_COMMAND_SHIFT (0U) +#define MBOX_A2B_CMD_0_COMMAND_MASK (0xFFFFFFFFU << MBOX_A2B_CMD_0_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* A2B_DAT_0 */ +#define MBOX_A2B_DAT_0_OFFSET (0xCU) +#define MBOX_A2B_DAT_0_DATA_SHIFT (0U) +#define MBOX_A2B_DAT_0_DATA_MASK (0xFFFFFFFFU << MBOX_A2B_DAT_0_DATA_SHIFT) /* 0xFFFFFFFF */ +/* A2B_CMD_1 */ +#define MBOX_A2B_CMD_1_OFFSET (0x10U) +#define MBOX_A2B_CMD_1_COMMAND_SHIFT (0U) +#define MBOX_A2B_CMD_1_COMMAND_MASK (0xFFFFFFFFU << MBOX_A2B_CMD_1_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* A2B_DAT_1 */ +#define MBOX_A2B_DAT_1_OFFSET (0x14U) +#define MBOX_A2B_DAT_1_DATA_SHIFT (0U) +#define MBOX_A2B_DAT_1_DATA_MASK (0xFFFFFFFFU << MBOX_A2B_DAT_1_DATA_SHIFT) /* 0xFFFFFFFF */ +/* A2B_CMD_2 */ +#define MBOX_A2B_CMD_2_OFFSET (0x18U) +#define MBOX_A2B_CMD_2_COMMAND_SHIFT (0U) +#define MBOX_A2B_CMD_2_COMMAND_MASK (0xFFFFFFFFU << MBOX_A2B_CMD_2_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* A2B_DAT_2 */ +#define MBOX_A2B_DAT_2_OFFSET (0x1CU) +#define MBOX_A2B_DAT_2_DATA_SHIFT (0U) +#define MBOX_A2B_DAT_2_DATA_MASK (0xFFFFFFFFU << MBOX_A2B_DAT_2_DATA_SHIFT) /* 0xFFFFFFFF */ +/* A2B_CMD_3 */ +#define MBOX_A2B_CMD_3_OFFSET (0x20U) +#define MBOX_A2B_CMD_3_COMMAND_SHIFT (0U) +#define MBOX_A2B_CMD_3_COMMAND_MASK (0xFFFFFFFFU << MBOX_A2B_CMD_3_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* A2B_DAT_3 */ +#define MBOX_A2B_DAT_3_OFFSET (0x24U) +#define MBOX_A2B_DAT_3_DATA_SHIFT (0U) +#define MBOX_A2B_DAT_3_DATA_MASK (0xFFFFFFFFU << MBOX_A2B_DAT_3_DATA_SHIFT) /* 0xFFFFFFFF */ +/* B2A_INTEN */ +#define MBOX_B2A_INTEN_OFFSET (0x28U) +#define MBOX_B2A_INTEN_INT0_SHIFT (0U) +#define MBOX_B2A_INTEN_INT0_MASK (0x1U << MBOX_B2A_INTEN_INT0_SHIFT) /* 0x00000001 */ +#define MBOX_B2A_INTEN_INT1_SHIFT (1U) +#define MBOX_B2A_INTEN_INT1_MASK (0x1U << MBOX_B2A_INTEN_INT1_SHIFT) /* 0x00000002 */ +#define MBOX_B2A_INTEN_INT2_SHIFT (2U) +#define MBOX_B2A_INTEN_INT2_MASK (0x1U << MBOX_B2A_INTEN_INT2_SHIFT) /* 0x00000004 */ +#define MBOX_B2A_INTEN_INT3_SHIFT (3U) +#define MBOX_B2A_INTEN_INT3_MASK (0x1U << MBOX_B2A_INTEN_INT3_SHIFT) /* 0x00000008 */ +/* B2A_STATUS */ +#define MBOX_B2A_STATUS_OFFSET (0x2CU) +#define MBOX_B2A_STATUS_INT0_SHIFT (0U) +#define MBOX_B2A_STATUS_INT0_MASK (0x1U << MBOX_B2A_STATUS_INT0_SHIFT) /* 0x00000001 */ +#define MBOX_B2A_STATUS_INT1_SHIFT (1U) +#define MBOX_B2A_STATUS_INT1_MASK (0x1U << MBOX_B2A_STATUS_INT1_SHIFT) /* 0x00000002 */ +#define MBOX_B2A_STATUS_INT2_SHIFT (2U) +#define MBOX_B2A_STATUS_INT2_MASK (0x1U << MBOX_B2A_STATUS_INT2_SHIFT) /* 0x00000004 */ +#define MBOX_B2A_STATUS_INT3_SHIFT (3U) +#define MBOX_B2A_STATUS_INT3_MASK (0x1U << MBOX_B2A_STATUS_INT3_SHIFT) /* 0x00000008 */ +/* B2A_CMD_0 */ +#define MBOX_B2A_CMD_0_OFFSET (0x30U) +#define MBOX_B2A_CMD_0_COMMAND_SHIFT (0U) +#define MBOX_B2A_CMD_0_COMMAND_MASK (0xFFFFFFFFU << MBOX_B2A_CMD_0_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* B2A_DAT_0 */ +#define MBOX_B2A_DAT_0_OFFSET (0x34U) +#define MBOX_B2A_DAT_0_DATA_SHIFT (0U) +#define MBOX_B2A_DAT_0_DATA_MASK (0xFFFFFFFFU << MBOX_B2A_DAT_0_DATA_SHIFT) /* 0xFFFFFFFF */ +/* B2A_CMD_1 */ +#define MBOX_B2A_CMD_1_OFFSET (0x38U) +#define MBOX_B2A_CMD_1_COMMAND_SHIFT (0U) +#define MBOX_B2A_CMD_1_COMMAND_MASK (0xFFFFFFFFU << MBOX_B2A_CMD_1_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* B2A_DAT_1 */ +#define MBOX_B2A_DAT_1_OFFSET (0x3CU) +#define MBOX_B2A_DAT_1_DATA_SHIFT (0U) +#define MBOX_B2A_DAT_1_DATA_MASK (0xFFFFFFFFU << MBOX_B2A_DAT_1_DATA_SHIFT) /* 0xFFFFFFFF */ +/* B2A_CMD_2 */ +#define MBOX_B2A_CMD_2_OFFSET (0x40U) +#define MBOX_B2A_CMD_2_COMMAND_SHIFT (0U) +#define MBOX_B2A_CMD_2_COMMAND_MASK (0xFFFFFFFFU << MBOX_B2A_CMD_2_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* B2A_DAT_2 */ +#define MBOX_B2A_DAT_2_OFFSET (0x44U) +#define MBOX_B2A_DAT_2_DATA_SHIFT (0U) +#define MBOX_B2A_DAT_2_DATA_MASK (0xFFFFFFFFU << MBOX_B2A_DAT_2_DATA_SHIFT) /* 0xFFFFFFFF */ +/* B2A_CMD_3 */ +#define MBOX_B2A_CMD_3_OFFSET (0x48U) +#define MBOX_B2A_CMD_3_COMMAND_SHIFT (0U) +#define MBOX_B2A_CMD_3_COMMAND_MASK (0xFFFFFFFFU << MBOX_B2A_CMD_3_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* B2A_DAT_3 */ +#define MBOX_B2A_DAT_3_OFFSET (0x4CU) +#define MBOX_B2A_DAT_3_DATA_SHIFT (0U) +#define MBOX_B2A_DAT_3_DATA_MASK (0xFFFFFFFFU << MBOX_B2A_DAT_3_DATA_SHIFT) /* 0xFFFFFFFF */ +/* ATOMIC_LOCK_00 */ +#define MBOX_ATOMIC_LOCK_00_OFFSET (0x100U) +#define MBOX_ATOMIC_LOCK_00_ATOMIC_LOCK_00_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_00_ATOMIC_LOCK_00_MASK (0x1U << MBOX_ATOMIC_LOCK_00_ATOMIC_LOCK_00_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_01 */ +#define MBOX_ATOMIC_LOCK_01_OFFSET (0x104U) +#define MBOX_ATOMIC_LOCK_01_ATOMIC_LOCK_01_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_01_ATOMIC_LOCK_01_MASK (0x1U << MBOX_ATOMIC_LOCK_01_ATOMIC_LOCK_01_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_02 */ +#define MBOX_ATOMIC_LOCK_02_OFFSET (0x108U) +#define MBOX_ATOMIC_LOCK_02_ATOMIC_LOCK_02_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_02_ATOMIC_LOCK_02_MASK (0x1U << MBOX_ATOMIC_LOCK_02_ATOMIC_LOCK_02_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_03 */ +#define MBOX_ATOMIC_LOCK_03_OFFSET (0x10CU) +#define MBOX_ATOMIC_LOCK_03_ATOMIC_LOCK_03_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_03_ATOMIC_LOCK_03_MASK (0x1U << MBOX_ATOMIC_LOCK_03_ATOMIC_LOCK_03_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_04 */ +#define MBOX_ATOMIC_LOCK_04_OFFSET (0x110U) +#define MBOX_ATOMIC_LOCK_04_ATOMIC_LOCK_04_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_04_ATOMIC_LOCK_04_MASK (0x1U << MBOX_ATOMIC_LOCK_04_ATOMIC_LOCK_04_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_05 */ +#define MBOX_ATOMIC_LOCK_05_OFFSET (0x114U) +#define MBOX_ATOMIC_LOCK_05_ATOMIC_LOCK_05_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_05_ATOMIC_LOCK_05_MASK (0x1U << MBOX_ATOMIC_LOCK_05_ATOMIC_LOCK_05_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_06 */ +#define MBOX_ATOMIC_LOCK_06_OFFSET (0x118U) +#define MBOX_ATOMIC_LOCK_06_ATOMIC_LOCK_06_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_06_ATOMIC_LOCK_06_MASK (0x1U << MBOX_ATOMIC_LOCK_06_ATOMIC_LOCK_06_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_07 */ +#define MBOX_ATOMIC_LOCK_07_OFFSET (0x11CU) +#define MBOX_ATOMIC_LOCK_07_ATOMIC_LOCK_07_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_07_ATOMIC_LOCK_07_MASK (0x1U << MBOX_ATOMIC_LOCK_07_ATOMIC_LOCK_07_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_08 */ +#define MBOX_ATOMIC_LOCK_08_OFFSET (0x120U) +#define MBOX_ATOMIC_LOCK_08_ATOMIC_LOCK_08_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_08_ATOMIC_LOCK_08_MASK (0x1U << MBOX_ATOMIC_LOCK_08_ATOMIC_LOCK_08_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_09 */ +#define MBOX_ATOMIC_LOCK_09_OFFSET (0x124U) +#define MBOX_ATOMIC_LOCK_09_ATOMIC_LOCK_09_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_09_ATOMIC_LOCK_09_MASK (0x1U << MBOX_ATOMIC_LOCK_09_ATOMIC_LOCK_09_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_10 */ +#define MBOX_ATOMIC_LOCK_10_OFFSET (0x128U) +#define MBOX_ATOMIC_LOCK_10_ATOMIC_LOCK_10_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_10_ATOMIC_LOCK_10_MASK (0x1U << MBOX_ATOMIC_LOCK_10_ATOMIC_LOCK_10_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_11 */ +#define MBOX_ATOMIC_LOCK_11_OFFSET (0x12CU) +#define MBOX_ATOMIC_LOCK_11_ATOMIC_LOCK_11_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_11_ATOMIC_LOCK_11_MASK (0x1U << MBOX_ATOMIC_LOCK_11_ATOMIC_LOCK_11_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_12 */ +#define MBOX_ATOMIC_LOCK_12_OFFSET (0x130U) +#define MBOX_ATOMIC_LOCK_12_ATOMIC_LOCK_12_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_12_ATOMIC_LOCK_12_MASK (0x1U << MBOX_ATOMIC_LOCK_12_ATOMIC_LOCK_12_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_13 */ +#define MBOX_ATOMIC_LOCK_13_OFFSET (0x134U) +#define MBOX_ATOMIC_LOCK_13_ATOMIC_LOCK_13_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_13_ATOMIC_LOCK_13_MASK (0x1U << MBOX_ATOMIC_LOCK_13_ATOMIC_LOCK_13_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_14 */ +#define MBOX_ATOMIC_LOCK_14_OFFSET (0x138U) +#define MBOX_ATOMIC_LOCK_14_ATOMIC_LOCK_14_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_14_ATOMIC_LOCK_14_MASK (0x1U << MBOX_ATOMIC_LOCK_14_ATOMIC_LOCK_14_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_15 */ +#define MBOX_ATOMIC_LOCK_15_OFFSET (0x13CU) +#define MBOX_ATOMIC_LOCK_15_ATOMIC_LOCK_15_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_15_ATOMIC_LOCK_15_MASK (0x1U << MBOX_ATOMIC_LOCK_15_ATOMIC_LOCK_15_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_16 */ +#define MBOX_ATOMIC_LOCK_16_OFFSET (0x140U) +#define MBOX_ATOMIC_LOCK_16_ATOMIC_LOCK_16_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_16_ATOMIC_LOCK_16_MASK (0x1U << MBOX_ATOMIC_LOCK_16_ATOMIC_LOCK_16_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_17 */ +#define MBOX_ATOMIC_LOCK_17_OFFSET (0x144U) +#define MBOX_ATOMIC_LOCK_17_ATOMIC_LOCK_17_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_17_ATOMIC_LOCK_17_MASK (0x1U << MBOX_ATOMIC_LOCK_17_ATOMIC_LOCK_17_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_18 */ +#define MBOX_ATOMIC_LOCK_18_OFFSET (0x148U) +#define MBOX_ATOMIC_LOCK_18_ATOMIC_LOCK_18_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_18_ATOMIC_LOCK_18_MASK (0x1U << MBOX_ATOMIC_LOCK_18_ATOMIC_LOCK_18_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_19 */ +#define MBOX_ATOMIC_LOCK_19_OFFSET (0x14CU) +#define MBOX_ATOMIC_LOCK_19_ATOMIC_LOCK_19_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_19_ATOMIC_LOCK_19_MASK (0x1U << MBOX_ATOMIC_LOCK_19_ATOMIC_LOCK_19_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_20 */ +#define MBOX_ATOMIC_LOCK_20_OFFSET (0x150U) +#define MBOX_ATOMIC_LOCK_20_ATOMIC_LOCK_20_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_20_ATOMIC_LOCK_20_MASK (0x1U << MBOX_ATOMIC_LOCK_20_ATOMIC_LOCK_20_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_21 */ +#define MBOX_ATOMIC_LOCK_21_OFFSET (0x154U) +#define MBOX_ATOMIC_LOCK_21_ATOMIC_LOCK_21_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_21_ATOMIC_LOCK_21_MASK (0x1U << MBOX_ATOMIC_LOCK_21_ATOMIC_LOCK_21_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_22 */ +#define MBOX_ATOMIC_LOCK_22_OFFSET (0x158U) +#define MBOX_ATOMIC_LOCK_22_ATOMIC_LOCK_22_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_22_ATOMIC_LOCK_22_MASK (0x1U << MBOX_ATOMIC_LOCK_22_ATOMIC_LOCK_22_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_23 */ +#define MBOX_ATOMIC_LOCK_23_OFFSET (0x15CU) +#define MBOX_ATOMIC_LOCK_23_ATOMIC_LOCK_23_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_23_ATOMIC_LOCK_23_MASK (0x1U << MBOX_ATOMIC_LOCK_23_ATOMIC_LOCK_23_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_24 */ +#define MBOX_ATOMIC_LOCK_24_OFFSET (0x160U) +#define MBOX_ATOMIC_LOCK_24_ATOMIC_LOCK_24_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_24_ATOMIC_LOCK_24_MASK (0x1U << MBOX_ATOMIC_LOCK_24_ATOMIC_LOCK_24_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_25 */ +#define MBOX_ATOMIC_LOCK_25_OFFSET (0x164U) +#define MBOX_ATOMIC_LOCK_25_ATOMIC_LOCK_25_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_25_ATOMIC_LOCK_25_MASK (0x1U << MBOX_ATOMIC_LOCK_25_ATOMIC_LOCK_25_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_26 */ +#define MBOX_ATOMIC_LOCK_26_OFFSET (0x168U) +#define MBOX_ATOMIC_LOCK_26_ATOMIC_LOCK_26_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_26_ATOMIC_LOCK_26_MASK (0x1U << MBOX_ATOMIC_LOCK_26_ATOMIC_LOCK_26_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_27 */ +#define MBOX_ATOMIC_LOCK_27_OFFSET (0x16CU) +#define MBOX_ATOMIC_LOCK_27_ATOMIC_LOCK_27_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_27_ATOMIC_LOCK_27_MASK (0x1U << MBOX_ATOMIC_LOCK_27_ATOMIC_LOCK_27_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_28 */ +#define MBOX_ATOMIC_LOCK_28_OFFSET (0x170U) +#define MBOX_ATOMIC_LOCK_28_ATOMIC_LOCK_28_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_28_ATOMIC_LOCK_28_MASK (0x1U << MBOX_ATOMIC_LOCK_28_ATOMIC_LOCK_28_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_29 */ +#define MBOX_ATOMIC_LOCK_29_OFFSET (0x174U) +#define MBOX_ATOMIC_LOCK_29_ATOMIC_LOCK_29_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_29_ATOMIC_LOCK_29_MASK (0x1U << MBOX_ATOMIC_LOCK_29_ATOMIC_LOCK_29_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_30 */ +#define MBOX_ATOMIC_LOCK_30_OFFSET (0x178U) +#define MBOX_ATOMIC_LOCK_30_ATOMIC_LOCK_30_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_30_ATOMIC_LOCK_30_MASK (0x1U << MBOX_ATOMIC_LOCK_30_ATOMIC_LOCK_30_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_31 */ +#define MBOX_ATOMIC_LOCK_31_OFFSET (0x17CU) +#define MBOX_ATOMIC_LOCK_31_ATOMIC_LOCK_31_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_31_ATOMIC_LOCK_31_MASK (0x1U << MBOX_ATOMIC_LOCK_31_ATOMIC_LOCK_31_SHIFT) /* 0x00000001 */ +/*****************************************INTMUX*****************************************/ +/* INT_ENABLE_GROUP0 */ +#define INTMUX_INT_ENABLE_GROUP0_OFFSET (0x0U) +#define INTMUX_INT_ENABLE_GROUP0_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP0_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP0_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP1 */ +#define INTMUX_INT_ENABLE_GROUP1_OFFSET (0x4U) +#define INTMUX_INT_ENABLE_GROUP1_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP1_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP1_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP2 */ +#define INTMUX_INT_ENABLE_GROUP2_OFFSET (0x8U) +#define INTMUX_INT_ENABLE_GROUP2_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP2_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP2_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP3 */ +#define INTMUX_INT_ENABLE_GROUP3_OFFSET (0xCU) +#define INTMUX_INT_ENABLE_GROUP3_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP3_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP3_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP4 */ +#define INTMUX_INT_ENABLE_GROUP4_OFFSET (0x10U) +#define INTMUX_INT_ENABLE_GROUP4_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP4_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP4_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP5 */ +#define INTMUX_INT_ENABLE_GROUP5_OFFSET (0x14U) +#define INTMUX_INT_ENABLE_GROUP5_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP5_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP5_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP6 */ +#define INTMUX_INT_ENABLE_GROUP6_OFFSET (0x18U) +#define INTMUX_INT_ENABLE_GROUP6_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP6_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP6_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP7 */ +#define INTMUX_INT_ENABLE_GROUP7_OFFSET (0x1CU) +#define INTMUX_INT_ENABLE_GROUP7_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP7_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP7_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP8 */ +#define INTMUX_INT_ENABLE_GROUP8_OFFSET (0x20U) +#define INTMUX_INT_ENABLE_GROUP8_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP8_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP8_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP9 */ +#define INTMUX_INT_ENABLE_GROUP9_OFFSET (0x24U) +#define INTMUX_INT_ENABLE_GROUP9_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP9_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP9_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP10 */ +#define INTMUX_INT_ENABLE_GROUP10_OFFSET (0x28U) +#define INTMUX_INT_ENABLE_GROUP10_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP10_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP10_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP11 */ +#define INTMUX_INT_ENABLE_GROUP11_OFFSET (0x2CU) +#define INTMUX_INT_ENABLE_GROUP11_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP11_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP11_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP12 */ +#define INTMUX_INT_ENABLE_GROUP12_OFFSET (0x30U) +#define INTMUX_INT_ENABLE_GROUP12_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP12_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP12_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP13 */ +#define INTMUX_INT_ENABLE_GROUP13_OFFSET (0x34U) +#define INTMUX_INT_ENABLE_GROUP13_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP13_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP13_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP14 */ +#define INTMUX_INT_ENABLE_GROUP14_OFFSET (0x38U) +#define INTMUX_INT_ENABLE_GROUP14_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP14_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP14_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP15 */ +#define INTMUX_INT_ENABLE_GROUP15_OFFSET (0x3CU) +#define INTMUX_INT_ENABLE_GROUP15_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP15_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP15_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP16 */ +#define INTMUX_INT_ENABLE_GROUP16_OFFSET (0x40U) +#define INTMUX_INT_ENABLE_GROUP16_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP16_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP16_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP17 */ +#define INTMUX_INT_ENABLE_GROUP17_OFFSET (0x44U) +#define INTMUX_INT_ENABLE_GROUP17_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP17_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP17_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP18 */ +#define INTMUX_INT_ENABLE_GROUP18_OFFSET (0x48U) +#define INTMUX_INT_ENABLE_GROUP18_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP18_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP18_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP19 */ +#define INTMUX_INT_ENABLE_GROUP19_OFFSET (0x4CU) +#define INTMUX_INT_ENABLE_GROUP19_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP19_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP19_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP20 */ +#define INTMUX_INT_ENABLE_GROUP20_OFFSET (0x50U) +#define INTMUX_INT_ENABLE_GROUP20_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP20_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP20_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP21 */ +#define INTMUX_INT_ENABLE_GROUP21_OFFSET (0x54U) +#define INTMUX_INT_ENABLE_GROUP21_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP21_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP21_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP22 */ +#define INTMUX_INT_ENABLE_GROUP22_OFFSET (0x58U) +#define INTMUX_INT_ENABLE_GROUP22_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP22_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP22_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP23 */ +#define INTMUX_INT_ENABLE_GROUP23_OFFSET (0x5CU) +#define INTMUX_INT_ENABLE_GROUP23_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP23_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP23_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP24 */ +#define INTMUX_INT_ENABLE_GROUP24_OFFSET (0x60U) +#define INTMUX_INT_ENABLE_GROUP24_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP24_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP24_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP25 */ +#define INTMUX_INT_ENABLE_GROUP25_OFFSET (0x64U) +#define INTMUX_INT_ENABLE_GROUP25_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP25_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP25_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP26 */ +#define INTMUX_INT_ENABLE_GROUP26_OFFSET (0x68U) +#define INTMUX_INT_ENABLE_GROUP26_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP26_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP26_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP27 */ +#define INTMUX_INT_ENABLE_GROUP27_OFFSET (0x6CU) +#define INTMUX_INT_ENABLE_GROUP27_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP27_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP27_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP28 */ +#define INTMUX_INT_ENABLE_GROUP28_OFFSET (0x70U) +#define INTMUX_INT_ENABLE_GROUP28_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP28_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP28_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP29 */ +#define INTMUX_INT_ENABLE_GROUP29_OFFSET (0x74U) +#define INTMUX_INT_ENABLE_GROUP29_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP29_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP29_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP30 */ +#define INTMUX_INT_ENABLE_GROUP30_OFFSET (0x78U) +#define INTMUX_INT_ENABLE_GROUP30_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP30_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP30_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_ENABLE_GROUP31 */ +#define INTMUX_INT_ENABLE_GROUP31_OFFSET (0x7CU) +#define INTMUX_INT_ENABLE_GROUP31_ENABLE_SHIFT (0U) +#define INTMUX_INT_ENABLE_GROUP31_ENABLE_MASK (0xFFU << INTMUX_INT_ENABLE_GROUP31_ENABLE_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP0 */ +#define INTMUX_INT_FLAG_GROUP0_OFFSET (0x80U) +#define INTMUX_INT_FLAG_GROUP0 (0x0U) +#define INTMUX_INT_FLAG_GROUP0_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP0_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP0_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP1 */ +#define INTMUX_INT_FLAG_GROUP1_OFFSET (0x84U) +#define INTMUX_INT_FLAG_GROUP1 (0x0U) +#define INTMUX_INT_FLAG_GROUP1_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP1_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP1_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP2 */ +#define INTMUX_INT_FLAG_GROUP2_OFFSET (0x88U) +#define INTMUX_INT_FLAG_GROUP2 (0x0U) +#define INTMUX_INT_FLAG_GROUP2_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP2_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP2_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP3 */ +#define INTMUX_INT_FLAG_GROUP3_OFFSET (0x8CU) +#define INTMUX_INT_FLAG_GROUP3 (0x0U) +#define INTMUX_INT_FLAG_GROUP3_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP3_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP3_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP4 */ +#define INTMUX_INT_FLAG_GROUP4_OFFSET (0x90U) +#define INTMUX_INT_FLAG_GROUP4 (0x0U) +#define INTMUX_INT_FLAG_GROUP4_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP4_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP4_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP5 */ +#define INTMUX_INT_FLAG_GROUP5_OFFSET (0x94U) +#define INTMUX_INT_FLAG_GROUP5 (0x0U) +#define INTMUX_INT_FLAG_GROUP5_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP5_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP5_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP6 */ +#define INTMUX_INT_FLAG_GROUP6_OFFSET (0x98U) +#define INTMUX_INT_FLAG_GROUP6 (0x0U) +#define INTMUX_INT_FLAG_GROUP6_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP6_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP6_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP7 */ +#define INTMUX_INT_FLAG_GROUP7_OFFSET (0x9CU) +#define INTMUX_INT_FLAG_GROUP7 (0x0U) +#define INTMUX_INT_FLAG_GROUP7_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP7_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP7_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP8 */ +#define INTMUX_INT_FLAG_GROUP8_OFFSET (0xA0U) +#define INTMUX_INT_FLAG_GROUP8 (0x0U) +#define INTMUX_INT_FLAG_GROUP8_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP8_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP8_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP9 */ +#define INTMUX_INT_FLAG_GROUP9_OFFSET (0xA4U) +#define INTMUX_INT_FLAG_GROUP9 (0x0U) +#define INTMUX_INT_FLAG_GROUP9_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP9_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP9_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP10 */ +#define INTMUX_INT_FLAG_GROUP10_OFFSET (0xA8U) +#define INTMUX_INT_FLAG_GROUP10 (0x0U) +#define INTMUX_INT_FLAG_GROUP10_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP10_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP10_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP11 */ +#define INTMUX_INT_FLAG_GROUP11_OFFSET (0xACU) +#define INTMUX_INT_FLAG_GROUP11 (0x0U) +#define INTMUX_INT_FLAG_GROUP11_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP11_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP11_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP12 */ +#define INTMUX_INT_FLAG_GROUP12_OFFSET (0xB0U) +#define INTMUX_INT_FLAG_GROUP12 (0x0U) +#define INTMUX_INT_FLAG_GROUP12_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP12_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP12_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP13 */ +#define INTMUX_INT_FLAG_GROUP13_OFFSET (0xB4U) +#define INTMUX_INT_FLAG_GROUP13 (0x0U) +#define INTMUX_INT_FLAG_GROUP13_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP13_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP13_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP14 */ +#define INTMUX_INT_FLAG_GROUP14_OFFSET (0xB8U) +#define INTMUX_INT_FLAG_GROUP14 (0x0U) +#define INTMUX_INT_FLAG_GROUP14_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP14_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP14_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP15 */ +#define INTMUX_INT_FLAG_GROUP15_OFFSET (0xBCU) +#define INTMUX_INT_FLAG_GROUP15 (0x0U) +#define INTMUX_INT_FLAG_GROUP15_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP15_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP15_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP16 */ +#define INTMUX_INT_FLAG_GROUP16_OFFSET (0xC0U) +#define INTMUX_INT_FLAG_GROUP16 (0x0U) +#define INTMUX_INT_FLAG_GROUP16_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP16_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP16_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP17 */ +#define INTMUX_INT_FLAG_GROUP17_OFFSET (0xC4U) +#define INTMUX_INT_FLAG_GROUP17 (0x0U) +#define INTMUX_INT_FLAG_GROUP17_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP17_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP17_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP18 */ +#define INTMUX_INT_FLAG_GROUP18_OFFSET (0xC8U) +#define INTMUX_INT_FLAG_GROUP18 (0x0U) +#define INTMUX_INT_FLAG_GROUP18_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP18_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP18_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP19 */ +#define INTMUX_INT_FLAG_GROUP19_OFFSET (0xCCU) +#define INTMUX_INT_FLAG_GROUP19 (0x0U) +#define INTMUX_INT_FLAG_GROUP19_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP19_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP19_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP20 */ +#define INTMUX_INT_FLAG_GROUP20_OFFSET (0xD0U) +#define INTMUX_INT_FLAG_GROUP20 (0x0U) +#define INTMUX_INT_FLAG_GROUP20_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP20_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP20_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP21 */ +#define INTMUX_INT_FLAG_GROUP21_OFFSET (0xD4U) +#define INTMUX_INT_FLAG_GROUP21 (0x0U) +#define INTMUX_INT_FLAG_GROUP21_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP21_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP21_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP22 */ +#define INTMUX_INT_FLAG_GROUP22_OFFSET (0xD8U) +#define INTMUX_INT_FLAG_GROUP22 (0x0U) +#define INTMUX_INT_FLAG_GROUP22_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP22_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP22_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP23 */ +#define INTMUX_INT_FLAG_GROUP23_OFFSET (0xDCU) +#define INTMUX_INT_FLAG_GROUP23 (0x0U) +#define INTMUX_INT_FLAG_GROUP23_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP23_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP23_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP24 */ +#define INTMUX_INT_FLAG_GROUP24_OFFSET (0xE0U) +#define INTMUX_INT_FLAG_GROUP24 (0x0U) +#define INTMUX_INT_FLAG_GROUP24_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP24_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP24_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP25 */ +#define INTMUX_INT_FLAG_GROUP25_OFFSET (0xE4U) +#define INTMUX_INT_FLAG_GROUP25 (0x0U) +#define INTMUX_INT_FLAG_GROUP25_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP25_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP25_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP26 */ +#define INTMUX_INT_FLAG_GROUP26_OFFSET (0xE8U) +#define INTMUX_INT_FLAG_GROUP26 (0x0U) +#define INTMUX_INT_FLAG_GROUP26_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP26_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP26_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP27 */ +#define INTMUX_INT_FLAG_GROUP27_OFFSET (0xECU) +#define INTMUX_INT_FLAG_GROUP27 (0x0U) +#define INTMUX_INT_FLAG_GROUP27_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP27_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP27_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP28 */ +#define INTMUX_INT_FLAG_GROUP28_OFFSET (0xF0U) +#define INTMUX_INT_FLAG_GROUP28 (0x0U) +#define INTMUX_INT_FLAG_GROUP28_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP28_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP28_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP29 */ +#define INTMUX_INT_FLAG_GROUP29_OFFSET (0xF4U) +#define INTMUX_INT_FLAG_GROUP29 (0x0U) +#define INTMUX_INT_FLAG_GROUP29_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP29_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP29_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP30 */ +#define INTMUX_INT_FLAG_GROUP30_OFFSET (0xF8U) +#define INTMUX_INT_FLAG_GROUP30 (0x0U) +#define INTMUX_INT_FLAG_GROUP30_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP30_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP30_FLAG_SHIFT) /* 0x000000FF */ +/* INT_FLAG_GROUP31 */ +#define INTMUX_INT_FLAG_GROUP31_OFFSET (0xFCU) +#define INTMUX_INT_FLAG_GROUP31 (0x0U) +#define INTMUX_INT_FLAG_GROUP31_FLAG_SHIFT (0U) +#define INTMUX_INT_FLAG_GROUP31_FLAG_MASK (0xFFU << INTMUX_INT_FLAG_GROUP31_FLAG_SHIFT) /* 0x000000FF */ + +/********Name=SOFTRST_CON00,Offset=0x400********/ +#define SRST_NCORERESET0 0U +#define SRST_NCORERESET1 1U +#define SRST_NCORERESET2 2U +#define SRST_NCORERESET3 3U +#define SRST_NCPUPORESET0 4U +#define SRST_NCPUPORESET1 5U +#define SRST_NCPUPORESET2 6U +#define SRST_NCPUPORESET3 7U +#define SRST_NSRESET 8U +#define SRST_NSPORESET 9U +#define SRST_NATRESET 10U +#define SRST_NGICRESET 11U +#define SRST_NPRESET 12U +#define SRST_NPERIPHRESET 13U +/********Name=SOFTRST_CON01,Offset=0x404********/ +#define SRST_A_CORE_NIU2DDR 16U +#define SRST_A_CORE_NIU2BUS 17U +#define SRST_P_DBG_NIU 18U +#define SRST_P_DBG 19U +#define SRST_P_DBG_DAPLITE 20U +#define SRST_DAP 21U +#define SRST_A_ADB400_CORE2GIC 22U +#define SRST_A_ADB400_GIC2CORE 23U +#define SRST_P_CORE_GRF 24U +#define SRST_P_CORE_PVTM 25U +#define SRST_CORE_PVTM 26U +#define SRST_CORE_PVTPLL 27U +/********Name=SOFTRST_CON02,Offset=0x408********/ +#define SRST_GPU 32U +#define SRST_A_GPU_NIU 33U +#define SRST_P_GPU_NIU 34U +#define SRST_P_GPU_PVTM 35U +#define SRST_GPU_PVTM 36U +#define SRST_GPU_PVTPLL 37U +#define SRST_A_NPU_NIU 40U +#define SRST_H_NPU_NIU 41U +#define SRST_P_NPU_NIU 42U +#define SRST_A_RKNN 43U +#define SRST_H_RKNN 44U +#define SRST_P_NPU_PVTM 45U +#define SRST_NPU_PVTM 46U +#define SRST_NPU_PVTPLL 47U +/********Name=SOFTRST_CON03,Offset=0x40C********/ +#define SRST_A_MSCH 51U +#define SRST_HWFFC_CTRL 52U +#define SRST_DDR_ALWAYSON 53U +#define SRST_A_DDRSPLIT 54U +#define SRST_DDRDFI_CTL 55U +#define SRST_A_DMA2DDR 57U +/********Name=SOFTRST_CON04,Offset=0x410********/ +#define SRST_A_PERIMID_NIU 64U +#define SRST_H_PERIMID_NIU 65U +#define SRST_A_GIC_AUDIO_NIU 66U +#define SRST_H_GIC_AUDIO_NIU 67U +#define SRST_A_GIC600 68U +#define SRST_A_GIC600_DEBUG 69U +#define SRST_A_GICADB_CORE2GIC 70U +#define SRST_A_GICADB_GIC2CORE 71U +#define SRST_A_SPINLOCK 72U +#define SRST_H_SDMMC_BUFFER 73U +#define SRST_D_SDMMC_BUFFER 74U +#define SRST_H_I2S0_8CH 75U +#define SRST_H_I2S1_8CH 76U +#define SRST_H_I2S2_2CH 77U +#define SRST_H_I2S3_2CH 78U +/********Name=SOFTRST_CON05,Offset=0x414********/ +#define SRST_M_I2S0_8CH_TX 80U +#define SRST_M_I2S0_8CH_RX 81U +#define SRST_M_I2S1_8CH_TX 82U +#define SRST_M_I2S1_8CH_RX 83U +#define SRST_M_I2S2_2CH 84U +#define SRST_M_I2S3_2CH_TX 85U +#define SRST_M_I2S3_2CH_RX 86U +#define SRST_H_PDM 87U +#define SRST_M_PDM 88U +#define SRST_H_VAD 89U +#define SRST_H_SPDIF_8CH 90U +#define SRST_M_SPDIF_8CH 91U +#define SRST_H_AUDPWM 92U +#define SRST_S_AUDPWM 93U +#define SRST_H_ACDCDIG 94U +#define SRST_ACDCDIG 95U +/********Name=SOFTRST_CON06,Offset=0x418********/ +#define SRST_A_SECURE_FLASH_NIU 96U +#define SRST_H_SECURE_FLASH_NIU 97U +#define SRST_A_CRYPTO_NS 103U +#define SRST_H_CRYPTO_NS 104U +#define SRST_CRYPTO_NS_CORE 105U +#define SRST_CRYPTO_NS_PKA 106U +#define SRST_CRYPTO_NS_RNG 107U +#define SRST_H_TRNG_NS 108U +#define SRST_TRNG_NS 109U +/********Name=SOFTRST_CON07,Offset=0x41C********/ +#define SRST_H_NANDC 112U +#define SRST_N_NANDC 113U +#define SRST_H_SFC 114U +#define SRST_H_SFC_XIP 115U +#define SRST_S_SFC 116U +#define SRST_A_EMMC 117U +#define SRST_H_EMMC 118U +#define SRST_B_EMMC 119U +#define SRST_C_EMMC 120U +#define SRST_T_EMMC 121U +/********Name=SOFTRST_CON08,Offset=0x420********/ +#define SRST_A_PIPE_NIU 128U +#define SRST_P_PIPE_NIU 130U +#define SRST_P_PIPE_GRF 133U +#define SRST_A_SATA0 134U +#define SRST_SATA0_PIPE 135U +#define SRST_SATA0_PMALIVE 136U +#define SRST_SATA0_RXOOB 137U +#define SRST_A_SATA1 138U +#define SRST_SATA1_PIPE 139U +#define SRST_SATA1_PMALIVE 140U +#define SRST_SATA1_RXOOB 141U +/********Name=SOFTRST_CON09,Offset=0x424********/ +#define SRST_A_SATA2 144U +#define SRST_SATA2_PIPE 145U +#define SRST_SATA2_PMALIVE 146U +#define SRST_SATA2_RXOOB 147U +#define SRST_USB3OTG0 148U +#define SRST_USB3OTG1 149U +#define SRST_XPCS 150U +#define SRST_XPCS_TX_DIV10 151U +#define SRST_XPCS_RX_DIV10 152U +#define SRST_XPCS_XGXS_RX 153U +/********Name=SOFTRST_CON10,Offset=0x428********/ +#define SRST_P_PCIE20 160U +#define SRST_PCIE20_POWERUP 161U +#define SRST_MSTR_ARESET_PCIE20 162U +#define SRST_SLV_ARESET_PCIE20 163U +#define SRST_DBI_ARESET_PCIE20 164U +#define SRST_BRESET_PCIE20 165U +#define SRST_PERST_PCIE20 166U +#define SRST_CORE_RST_PCIE20 167U +#define SRST_NSTICKY_RST_PCIE20 168U +#define SRST_STICKY_RST_PCIE20 169U +#define SRST_PWR_RST_PCIE20 170U +/********Name=SOFTRST_CON11,Offset=0x42C********/ +#define SRST_P_PCIE30X1 176U +#define SRST_PCIE30X1_POWERUP 177U +#define SRST_MSTR_ARESET_PCIE30X1 178U +#define SRST_SLV_ARESET_PCIE30X1 179U +#define SRST_DBI_ARESET_PCIE30X1 180U +#define SRST_BRESET_PCIE30X1 181U +#define SRST_PERST_PCIE30X1 182U +#define SRST_CORE_RST_PCIE30X1 183U +#define SRST_NSTICKY_RST_PCIE30X1 184U +#define SRST_STICKY_RST_PCIE30X1 185U +#define SRST_PWR_RST_PCIE30X1 186U +/********Name=SOFTRST_CON12,Offset=0x430********/ +#define SRST_P_PCIE30X2 192U +#define SRST_PCIE30X2_POWERUP 193U +#define SRST_MSTR_ARESET_PCIE30X2 194U +#define SRST_SLV_ARESET_PCIE30X2 195U +#define SRST_DBI_ARESET_PCIE30X2 196U +#define SRST_BRESET_PCIE30X2 197U +#define SRST_PERST_PCIE30X2 198U +#define SRST_CORE_RST_PCIE30X2 199U +#define SRST_NSTICKY_RST_PCIE30X2 200U +#define SRST_STICKY_RST_PCIE30X2 201U +#define SRST_PWR_RST_PCIE30X2 202U +/********Name=SOFTRST_CON13,Offset=0x434********/ +#define SRST_A_PHP_NIU 208U +#define SRST_H_PHP_NIU 209U +#define SRST_P_PHP_NIU 210U +#define SRST_H_SDMMC0 211U +#define SRST_SDMMC0 212U +#define SRST_H_SDMMC1 213U +#define SRST_SDMMC1 214U +#define SRST_A_GMAC0 215U +#define SRST_GMAC0_TIMESTAMP 216U +/********Name=SOFTRST_CON14,Offset=0x438********/ +#define SRST_A_USB_NIU 224U +#define SRST_H_USB_NIU 225U +#define SRST_P_USB_NIU 226U +#define SRST_P_USB_GRF 227U +#define SRST_H_USB2HOST0 228U +#define SRST_H_USB2HOST0_ARB 229U +#define SRST_USB2HOST0_UTMI 230U +#define SRST_H_USB2HOST1 231U +#define SRST_H_USB2HOST1_ARB 232U +#define SRST_USB2HOST1_UTMI 233U +#define SRST_H_SDMMC2 234U +#define SRST_SDMMC2 235U +#define SRST_A_GMAC1 236U +#define SRST_GMAC1_TIMESTAMP 237U +/********Name=SOFTRST_CON15,Offset=0x43C********/ +#define SRST_A_VI_NIU 240U +#define SRST_H_VI_NIU 241U +#define SRST_P_VI_NIU 242U +#define SRST_A_VICAP1 247U +#define SRST_H_VICAP1 248U +#define SRST_D_VICAP1 249U +#define SRST_I_VICAP1 250U +#define SRST_P_VICAP1 251U +#define SRST_H_ISP 252U +#define SRST_ISP 253U +#define SRST_P_CSI2HOST1 255U +/********Name=SOFTRST_CON16,Offset=0x440********/ +#define SRST_A_VO_NIU 256U +#define SRST_H_VO_NIU 257U +#define SRST_P_VO_NIU 258U +#define SRST_A_VOP_NIU 259U +#define SRST_A_VOP 260U +#define SRST_H_VOP 261U +#define SRST_D0_VOP 262U +#define SRST_D1_VOP 263U +#define SRST_D2_VOP 264U +#define SRST_VOP_PWM 265U +#define SRST_A_HDCP 266U +#define SRST_H_HDCP 267U +#define SRST_P_HDCP 268U +#define SRST_P_HDMI_HOST 270U +#define SRST_HDMI_HOST 271U +/********Name=SOFTRST_CON17,Offset=0x444********/ +#define SRST_P_DSITX_0 272U +#define SRST_P_DSITX_1 273U +#define SRST_P_EDP_CTRL 274U +#define SRST_EDP_24M 275U +#define SRST_A_VPU_NIU 280U +#define SRST_H_VPU_NIU 281U +#define SRST_A_VPU 282U +#define SRST_H_VPU 283U +#define SRST_H_EINK 286U +#define SRST_P_EINK 287U +/********Name=SOFTRST_CON18,Offset=0x448********/ +#define SRST_A_RGA_NIU 288U +#define SRST_H_RGA_NIU 289U +#define SRST_P_RGA_NIU 290U +#define SRST_A_RGA 292U +#define SRST_H_RGA 293U +#define SRST_RGA_CORE 294U +#define SRST_A_IEP 295U +#define SRST_H_IEP 296U +#define SRST_IEP_CORE 297U +#define SRST_H_EBC 298U +#define SRST_D_EBC 299U +#define SRST_A_JDEC 300U +#define SRST_H_JDEC 301U +#define SRST_A_JENC 302U +#define SRST_H_JENC 303U +/********Name=SOFTRST_CON19,Offset=0x44C********/ +#define SRST_A_VENC_NIU 304U +#define SRST_H_VENC_NIU 305U +#define SRST_A_RKVENC 307U +#define SRST_H_RKVENC 308U +#define SRST_RKVENC_CORE 309U +/********Name=SOFTRST_CON20,Offset=0x450********/ +#define SRST_A_RKVDEC_NIU 320U +#define SRST_H_RKVDEC_NIU 321U +#define SRST_A_RKVDEC 322U +#define SRST_H_RKVDEC 323U +#define SRST_RKVDEC_CA 324U +#define SRST_RKVDEC_CORE 325U +#define SRST_RKVDEC_HEVC_CA 326U +/********Name=SOFTRST_CON21,Offset=0x454********/ +#define SRST_A_BUS_NIU 336U +#define SRST_P_BUS_NIU 338U +#define SRST_P_CAN0 340U +#define SRST_CAN0 341U +#define SRST_P_CAN1 342U +#define SRST_CAN1 343U +#define SRST_P_CAN2 344U +#define SRST_CAN2 345U +#define SRST_P_GPIO1 346U +#define SRST_DB_GPIO1 347U +#define SRST_P_GPIO2 348U +#define SRST_DB_GPIO2 349U +#define SRST_P_GPIO3 350U +#define SRST_DB_GPIO3 351U +/********Name=SOFTRST_CON22,Offset=0x458********/ +#define SRST_P_GPIO4 352U +#define SRST_DB_GPIO4 353U +#define SRST_P_I2C1 354U +#define SRST_I2C1 355U +#define SRST_P_I2C2 356U +#define SRST_I2C2 357U +#define SRST_P_I2C3 358U +#define SRST_I2C3 359U +#define SRST_P_I2C4 360U +#define SRST_I2C4 361U +#define SRST_P_I2C5 362U +#define SRST_I2C5 363U +#define SRST_P_OTPC_NS 364U +#define SRST_OTPC_NS_SBPI 365U +#define SRST_OTPC_NS_USR 366U +/********Name=SOFTRST_CON23,Offset=0x45C********/ +#define SRST_P_PWM1 368U +#define SRST_PWM1 369U +#define SRST_P_PWM2 370U +#define SRST_PWM2 371U +#define SRST_P_PWM3 372U +#define SRST_PWM3 373U +#define SRST_P_SPI0 374U +#define SRST_SPI0 375U +#define SRST_P_SPI1 376U +#define SRST_SPI1 377U +#define SRST_P_SPI2 378U +#define SRST_SPI2 379U +#define SRST_P_SPI3 380U +#define SRST_SPI3 381U +/********Name=SOFTRST_CON24,Offset=0x460********/ +#define SRST_P_SARADC 384U +#define SRST_P_TSADC 385U +#define SRST_TSADC 386U +#define SRST_P_TIMER 387U +#define SRST_TIMER0 388U +#define SRST_TIMER1 389U +#define SRST_TIMER2 390U +#define SRST_TIMER3 391U +#define SRST_TIMER4 392U +#define SRST_TIMER5 393U +#define SRST_P_UART1 394U +#define SRST_S_UART1 395U +/********Name=SOFTRST_CON25,Offset=0x464********/ +#define SRST_P_UART2 400U +#define SRST_S_UART2 401U +#define SRST_P_UART3 402U +#define SRST_S_UART3 403U +#define SRST_P_UART4 404U +#define SRST_S_UART4 405U +#define SRST_P_UART5 406U +#define SRST_S_UART5 407U +#define SRST_P_UART6 408U +#define SRST_S_UART6 409U +#define SRST_P_UART7 410U +#define SRST_S_UART7 411U +#define SRST_P_UART8 412U +#define SRST_S_UART8 413U +#define SRST_P_UART9 414U +#define SRST_S_UART9 415U +/********Name=SOFTRST_CON26,Offset=0x468********/ +#define SRST_P_GRF 416U +#define SRST_P_GRF_VCCIO12 417U +#define SRST_P_GRF_VCCIO34 418U +#define SRST_P_GRF_VCCIO567 419U +#define SRST_P_SCR 420U +#define SRST_P_WDT_NS 421U +#define SRST_T_WDT_NS 422U +#define SRST_P_DFT2APB 423U +#define SRST_A_MCU 426U +#define SRST_P_INTMUX 427U +#define SRST_P_MAILBOX 428U +/********Name=SOFTRST_CON27,Offset=0x46C********/ +#define SRST_A_TOP_HIGH_NIU 432U +#define SRST_A_TOP_LOW_NIU 433U +#define SRST_H_TOP_NIU 434U +#define SRST_P_TOP_NIU 435U +#define SRST_P_TOP_CRU 438U +#define SRST_P_DDRPHY 439U +#define SRST_DDRPHY 440U +#define SRST_P_MIPICSIPHY 442U +#define SRST_P_MIPIDSIPHY0 443U +#define SRST_P_MIPIDSIPHY1 444U +#define SRST_P_PCIE30PHY 445U +#define SRST_PCIE30PHY 446U +#define SRST_P_PCIE30PHY_GRF 447U +/********Name=SOFTRST_CON28,Offset=0x470********/ +#define SRST_P_APB2ASB_CHIP_LEFT 448U +#define SRST_P_APB2ASB_CHIP_BOTTOM 449U +#define SRST_P_ASB2APB_CHIP_LEFT 450U +#define SRST_P_ASB2APB_CHIP_BOTTOM 451U +#define SRST_P_PIPEPHY0 452U +#define SRST_PIPEPHY0 453U +#define SRST_P_PIPEPHY1 454U +#define SRST_PIPEPHY1 455U +#define SRST_P_PIPEPHY2 456U +#define SRST_PIPEPHY2 457U +#define SRST_P_USB2PHY0_GRF 458U +#define SRST_P_USB2PHY1_GRF 459U +#define SRST_P_CPU_BOOST 460U +#define SRST_CPU_BOOST 461U +#define SRST_P_OTPPHY 462U +#define SRST_OTPPHY 463U +/********Name=SOFTRST_CON29,Offset=0x474********/ +#define SRST_USB2PHY0_POR 464U +#define SRST_USB2PHY0_USB3OTG0 465U +#define SRST_USB2PHY0_USB3OTG1 466U +#define SRST_USB2PHY1_POR 467U +#define SRST_USB2PHY1_USB2HOST0 468U +#define SRST_USB2PHY1_USB2HOST1 469U +#define SRST_P_EDPPHY_GRF 470U +#define SRST_TSADCPHY 471U +#define SRST_GMAC0_DELAYLINE 472U +#define SRST_GMAC1_DELAYLINE 473U +#define SRST_OTPC_ARB 474U +#define SRST_P_PIPEPHY0_GRF 475U +#define SRST_P_PIPEPHY1_GRF 476U +#define SRST_P_PIPEPHY2_GRF 477U +/********Name=PMUSOFTRST_CON00,Offset=0x200********/ +#define SRST_P_PDPMU_NIU 480U +#define SRST_P_PMUCRU 481U +#define SRST_P_PMUGRF 482U +#define SRST_P_I2C0 483U +#define SRST_I2C0 484U +#define SRST_P_UART0 485U +#define SRST_S_UART0 486U +#define SRST_P_PWM0 487U +#define SRST_PWM0 488U +#define SRST_P_GPIO0 489U +#define SRST_DB_GPIO0 490U +#define SRST_P_PMUPVTM 491U +#define SRST_PMUPVTM 492U + +/********Name=GATE_CON00,Offset=0x300********/ +#define CLK_CORE_GATE 0U +#define CLK_CORE0_GATE 1U +#define CLK_CORE1_GATE 2U +#define CLK_CORE2_GATE 3U +#define CLK_CORE3_GATE 4U +#define SCLK_CORE_SRC_GATE 5U +#define CLK_NPLL_CORE_GATE 6U +#define SCLK_CORE_GATE 7U +#define ATCLK_CORE_GATE 8U +#define GICCLK_CORE_GATE 9U +#define PCLK_CORE_PRE_GATE 10U +#define PERIPHCLK_CORE_PRE_GATE 11U +#define PCLK_CORE_GATE 12U +#define PERIPHCLK_CORE_GATE 13U +#define TSCLK_CORE_GATE 14U +#define CNTCLK_CORE_GATE 15U +/********Name=GATE_CON01,Offset=0x304********/ +#define ACLK_CORE_GATE 16U +#define ACLK_CORE_NIU2DDR_GATE 17U +#define ACLK_CORE_NIU2BUS_GATE 18U +#define PCLK_DBG_NIU_GATE 19U +#define PCLK_DBG_GATE 20U +#define PCLK_DBG_DAPLITE_GATE 21U +#define ACLK_ADB400_CORE2GIC_GATE 22U +#define ACLK_ADB400_GIC2CORE_GATE 23U +#define PCLK_CORE_GRF_GATE 24U +#define PCLK_CORE_PVTM_GATE 25U +#define CLK_CORE_PVTM_GATE 26U +#define CLK_CORE_PVTM_CORE_GATE 27U +#define CLK_CORE_PVTPLL_GATE 28U +#define CLK_CORE_DIV2_GATE 29U +#define CLK_APLL_CORE_GATE 30U +#define CLK_JTAG_GATE 31U +/********Name=GATE_CON02,Offset=0x308********/ +#define CLK_GPU_SRC_GATE 32U +#define PCLK_GPU_PRE_GATE 34U +#define ACLK_GPU_GATE 35U +#define ACLK_GPU_NIU_GATE 36U +#define PCLK_GPU_NIU_GATE 37U +#define PCLK_GPU_PVTM_GATE 38U +#define CLK_GPU_PVTM_GATE 39U +#define CLK_GPU_PVTM_CORE_GATE 40U +#define CLK_GPU_PVTPLL_GATE 41U +#define CLK_GPU_DIV2_GATE 42U +#define ACLK_GPU_PRE_GATE 43U +/********Name=GATE_CON03,Offset=0x30C********/ +#define CLK_NPU_SRC_GATE 48U +#define CLK_NPU_NP5_GATE 49U +#define HCLK_NPU_PRE_GATE 50U +#define PCLK_NPU_PRE_GATE 51U +#define ACLK_NPU_NIU_GATE 52U +#define HCLK_NPU_NIU_GATE 53U +#define PCLK_NPU_NIU_GATE 54U +#define ACLK_RKNN_GATE 55U +#define HCLK_RKNN_GATE 56U +#define PCLK_NPU_PVTM_GATE 57U +#define CLK_NPU_PVTM_GATE 58U +#define CLK_NPU_PVTM_CORE_GATE 59U +#define CLK_NPU_PVTPLL_GATE 60U +#define CLK_NPU_DIV2_GATE 61U +/********Name=GATE_CON04,Offset=0x310********/ +#define CLK_DDRPHY1X_GATE 64U +#define CLK_DPLL_DDR_GATE 65U +#define ACLK_MSCH_DIV2_GATE 66U +#define CLK_HWFFC_CTRL_GATE 67U +#define ACLK_DDRSCRAMBLE_GATE 68U +#define ACLK_MSCH_GATE 69U +#define CLK_DDR_ALWAYSON_GATE 70U +#define ACLK_DDRSPLIT_GATE 72U +#define CLK_DDRDFI_CTL_GATE 73U +#define ACLK_DMA2DDR_GATE 75U +#define CLK_DDRMON_GATE 77U +#define CLK24_DDRMON_GATE 79U +/********Name=GATE_CON05,Offset=0x314********/ +#define ACLK_GIC_AUDIO_GATE 80U +#define HCLK_GIC_AUDIO_GATE 81U +#define ACLK_GIC_AUDIO_NIU_GATE 82U +#define HCLK_GIC_AUDIO_NIU_GATE 83U +#define ACLK_GIC600_GATE 84U +#define ACLK_GICADB_CORE2GIC_GATE 85U +#define ACLK_GICADB_GIC2CORE_GATE 86U +#define ACLK_SPINLOCK_GATE 87U +#define HCLK_SDMMC_BUFFER_GATE 88U +#define DCLK_SDMMC_BUFFER_GATE 89U +#define HCLK_I2S0_8CH_GATE 90U +#define HCLK_I2S1_8CH_GATE 91U +#define HCLK_I2S2_2CH_GATE 92U +#define HCLK_I2S3_2CH_GATE 93U +#define HCLK_PDM_GATE 94U +#define MCLK_PDM_GATE 95U +/********Name=GATE_CON06,Offset=0x318********/ +#define CLK_I2S0_8CH_TX_SRC_GATE 96U +#define CLK_I2S0_8CH_TX_FRAC_GATE 97U +#define MCLK_I2S0_8CH_TX_GATE 98U +#define I2S0_MCLKOUT_TX_GATE 99U +#define CLK_I2S0_8CH_RX_SRC_GATE 100U +#define CLK_I2S0_8CH_RX_FRAC_GATE 101U +#define MCLK_I2S0_8CH_RX_GATE 102U +#define I2S0_MCLKOUT_RX_GATE 103U +#define CLK_I2S1_8CH_TX_SRC_GATE 104U +#define CLK_I2S1_8CH_TX_FRAC_GATE 105U +#define MCLK_I2S1_8CH_TX_GATE 106U +#define I2S1_MCLKOUT_TX_GATE 107U +#define CLK_I2S1_8CH_RX_SRC_GATE 108U +#define CLK_I2S1_8CH_RX_FRAC_GATE 109U +#define MCLK_I2S1_8CH_RX_GATE 110U +#define I2S1_MCLKOUT_RX_GATE 111U +/********Name=GATE_CON07,Offset=0x31C********/ +#define CLK_I2S2_2CH_SRC_GATE 112U +#define CLK_I2S2_2CH_FRAC_GATE 113U +#define MCLK_I2S2_2CH_GATE 114U +#define I2S2_MCLKOUT_GATE 115U +#define CLK_I2S3_2CH_TX_SRC_GATE 116U +#define CLK_I2S3_2CH_TX_FRAC_GATE 117U +#define MCLK_I2S3_2CH_TX_GATE 118U +#define I2S3_MCLKOUT_TX_GATE 119U +#define CLK_I2S3_2CH_RX_SRC_GATE 120U +#define CLK_I2S3_2CH_RX_FRAC_GATE 121U +#define MCLK_I2S3_2CH_RX_GATE 122U +#define I2S3_MCLKOUT_RX_GATE 123U +#define HCLK_VAD_GATE 124U +#define HCLK_SPDIF_8CH_GATE 125U +#define MCLK_SPDIF_8CH_SRC_GATE 126U +#define MCLK_SPDIF_8CH_FRAC_GATE 127U +/********Name=GATE_CON08,Offset=0x320********/ +#define HCLK_AUDPWM_GATE 128U +#define SCLK_AUDPWM_SRC_GATE 129U +#define SCLK_AUDPWM_FRAC_GATE 130U +#define HCLK_ACDCDIG_GATE 131U +#define CLK_ACDCDIG_I2C_GATE 132U +#define CLK_ACDCDIG_DAC_GATE 133U +#define CLK_ACDCDIG_ADC_GATE 134U +#define ACLK_SECURE_FLASH_GATE 135U +#define HCLK_SECURE_FLASH_GATE 136U +#define ACLK_SECURE_FLASH_NIU_GATE 137U +#define HCLK_SECURE_FLASH_NIU_GATE 138U +#define ACLK_CRYPTO_NS_GATE 139U +#define HCLK_CRYPTO_NS_GATE 140U +#define CLK_CRYPTO_NS_CORE_GATE 141U +#define CLK_CRYPTO_NS_PKA_GATE 142U +#define CLK_CRYPTO_NS_RNG_GATE 143U +/********Name=GATE_CON09,Offset=0x324********/ +#define HCLK_NANDC_GATE 144U +#define NCLK_NANDC_GATE 145U +#define HCLK_SFC_GATE 146U +#define HCLK_SFC_XIP_GATE 147U +#define SCLK_SFC_GATE 148U +#define ACLK_EMMC_GATE 149U +#define HCLK_EMMC_GATE 150U +#define BCLK_EMMC_GATE 151U +#define CCLK_EMMC_GATE 152U +#define TCLK_EMMC_GATE 153U +#define HCLK_TRNG_NS_GATE 154U +#define CLK_TRNG_NS_GATE 155U +/********Name=GATE_CON10,Offset=0x328********/ +#define ACLK_PIPE_GATE 160U +#define PCLK_PIPE_GATE 161U +#define ACLK_PIPE_NIU_GATE 162U +#define PCLK_PIPE_NIU_GATE 163U +#define CLK_XPCS_EEE_GATE 164U +#define CLK_XPCS_RX_DIV10_GATE 165U +#define CLK_XPCS_TX_DIV10_GATE 166U +#define PCLK_PIPE_GRF_GATE 167U +#define ACLK_USB3OTG0_GATE 168U +#define CLK_USB3OTG0_REF_GATE 169U +#define CLK_USB3OTG0_SUSPEND_GATE 170U +#define CLK_USB3OTG0_PIPE_GATE 171U +#define ACLK_USB3OTG1_GATE 172U +#define CLK_USB3OTG1_REF_GATE 173U +#define CLK_USB3OTG1_SUSPEND_GATE 174U +#define CLK_USB3OTG1_PIPE_GATE 175U +/********Name=GATE_CON11,Offset=0x32C********/ +#define ACLK_SATA0_GATE 176U +#define CLK_SATA0_PMALIVE_GATE 177U +#define CLK_SATA0_RXOOB_GATE 178U +#define CLK_SATA0_PIPE_GATE 179U +#define ACLK_SATA1_GATE 180U +#define CLK_SATA1_PMALIVE_GATE 181U +#define CLK_SATA1_RXOOB_GATE 182U +#define CLK_SATA1_PIPE_GATE 183U +#define ACLK_SATA2_GATE 184U +#define CLK_SATA2_PMALIVE_GATE 185U +#define CLK_SATA2_RXOOB_GATE 186U +#define CLK_SATA2_PIPE_GATE 187U +/********Name=GATE_CON12,Offset=0x330********/ +#define ACLK_PCIE20_MST_GATE 192U +#define ACLK_PCIE20_SLV_GATE 193U +#define ACLK_PCIE20_DBI_GATE 194U +#define PCLK_PCIE20_GATE 195U +#define CLK_PCIE20_AUX_GATE 196U +#define CLK_PCIE20_PIPE_GATE 197U +#define ACLK_PCIE30X1_MST_GATE 200U +#define ACLK_PCIE30X1_SLV_GATE 201U +#define ACLK_PCIE30X1_DBI_GATE 202U +#define PCLK_PCIE30X1_GATE 203U +#define CLK_PCIE30X1_AUX_GATE 204U +#define CLK_PCIE30X1_PIPE_GATE 205U +/********Name=GATE_CON13,Offset=0x334********/ +#define ACLK_PCIE30X2_MST_GATE 208U +#define ACLK_PCIE30X2_SLV_GATE 209U +#define ACLK_PCIE30X2_DBI_GATE 210U +#define PCLK_PCIE30X2_GATE 211U +#define CLK_PCIE30X2_AUX_GATE 212U +#define CLK_PCIE30X2_PIPE_GATE 213U +#define PCLK_XPCS_GATE 214U +#define CLK_XPCS_QSGMII_TX_GATE 215U +#define CLK_XPCS_QSGMII_RX_GATE 216U +#define CLK_XPCS_XGXS_TX_GATE 217U +#define CLK_XPCS_XGXS_RX_GATE 219U +#define CLK_XPCS_MII0_TX_GATE 220U +#define CLK_XPCS_MII0_RX_GATE 221U +#define CLK_XPCS_MII1_TX_GATE 222U +#define CLK_XPCS_MII1_RX_GATE 223U +/********Name=GATE_CON14,Offset=0x338********/ +#define ACLK_PERIMID_GATE 224U +#define HCLK_PERIMID_GATE 225U +#define ACLK_PERIMID_NIU_GATE 226U +#define HCLK_PERIMID_NIU_GATE 227U +#define ACLK_PHP_GATE 232U +#define HCLK_PHP_GATE 233U +#define PCLK_PHP_GATE 234U +#define ACLK_PHP_NIU_GATE 235U +#define HCLK_PHP_NIU_GATE 236U +#define PCLK_PHP_NIU_GATE 237U +/********Name=GATE_CON15,Offset=0x33C********/ +#define HCLK_SDMMC0_GATE 240U +#define CLK_SDMMC0_GATE 241U +#define HCLK_SDMMC1_GATE 242U +#define CLK_SDMMC1_GATE 243U +#define CLK_GMAC0_PTP_REF_GATE 244U +#define ACLK_GMAC0_GATE 245U +#define PCLK_GMAC0_GATE 246U +#define CLK_MAC0_2TOP_GATE 247U +#define CLK_MAC0_OUT_GATE 248U +#define CLK_MAC0_REFOUT_GATE 252U +/********Name=GATE_CON16,Offset=0x340********/ +#define ACLK_USB_GATE 256U +#define HCLK_USB_GATE 257U +#define PCLK_USB_GATE 258U +#define ACLK_USB_NIU_GATE 259U +#define HCLK_USB_NIU_GATE 260U +#define PCLK_USB_NIU_GATE 261U +#define PCLK_USB_GRF_GATE 262U +#define HCLK_USB2HOST0_GATE 268U +#define HCLK_USB2HOST0_ARB_GATE 269U +#define HCLK_USB2HOST1_GATE 270U +#define HCLK_USB2HOST1_ARB_GATE 271U +/********Name=GATE_CON17,Offset=0x344********/ +#define HCLK_SDMMC2_GATE 272U +#define CLK_SDMMC2_GATE 273U +#define CLK_GMAC1_PTP_REF_GATE 274U +#define ACLK_GMAC1_GATE 275U +#define PCLK_GMAC1_GATE 276U +#define CLK_MAC1_2TOP_GATE 277U +#define CLK_MAC1_OUT_GATE 278U +#define CLK_MAC1_REFOUT_GATE 282U +/********Name=GATE_CON18,Offset=0x348********/ +#define ACLK_VI_GATE 288U +#define HCLK_VI_GATE 289U +#define PCLK_VI_GATE 290U +#define ACLK_VI_NIU_GATE 291U +#define HCLK_VI_NIU_GATE 292U +#define PCLK_VI_NIU_GATE 293U +#define ACLK_VICAP1_GATE 297U +#define HCLK_VICAP1_GATE 298U +#define DCLK_VICAP1_GATE 299U +/********Name=GATE_CON19,Offset=0x34C********/ +#define ACLK_ISP_GATE 304U +#define HCLK_ISP_GATE 305U +#define CLK_ISP_GATE 306U +#define PCLK_CSI2HOST1_GATE 308U +#define CLK_CIF_OUT_GATE 312U +#define CLK_CAM0_OUT_GATE 313U +#define CLK_CAM1_OUT_GATE 314U +/********Name=GATE_CON20,Offset=0x350********/ +#define HCLK_VO_GATE 321U +#define PCLK_VO_GATE 322U +#define ACLK_VO_NIU_GATE 323U +#define HCLK_VO_NIU_GATE 324U +#define PCLK_VO_NIU_GATE 325U +#define ACLK_VOP_PRE_GATE 326U +#define ACLK_VOP_NIU_GATE 327U +#define ACLK_VOP_GATE 328U +#define HCLK_VOP_GATE 329U +#define DCLK0_VOP_GATE 330U +#define DCLK1_VOP_GATE 331U +#define DCLK2_VOP_GATE 332U +#define CLK_VOP_PWM_GATE 333U +/********Name=GATE_CON21,Offset=0x354********/ +#define ACLK_HDCP_GATE 336U +#define HCLK_HDCP_GATE 337U +#define PCLK_HDCP_GATE 338U +#define PCLK_HDMI_HOST_GATE 339U +#define CLK_HDMI_SFR_GATE 340U +#define CLK_HDMI_CEC_GATE 341U +#define PCLK_DSITX_0_GATE 342U +#define PCLK_DSITX_1_GATE 343U +#define PCLK_EDP_CTRL_GATE 344U +#define CLK_EDP_200M_GATE 345U +/********Name=GATE_CON22,Offset=0x358********/ +#define ACLK_VPU_PRE_GATE 352U +#define HCLK_VPU_PRE_GATE 353U +#define ACLK_VPU_NIU_GATE 354U +#define HCLK_VPU_NIU_GATE 355U +#define ACLK_VPU_GATE 356U +#define HCLK_VPU_GATE 357U +#define PCLK_RGA_PRE_GATE 364U +#define PCLK_RGA_NIU_GATE 365U +#define PCLK_EINK_GATE 366U +#define HCLK_EINK_GATE 367U +/********Name=GATE_CON23,Offset=0x35C********/ +#define ACLK_RGA_PRE_GATE 368U +#define HCLK_RGA_PRE_GATE 369U +#define ACLK_RGA_NIU_GATE 370U +#define HCLK_RGA_NIU_GATE 371U +#define ACLK_RGA_GATE 372U +#define HCLK_RGA_GATE 373U +#define CLK_RGA_CORE_GATE 374U +#define ACLK_IEP_GATE 375U +#define HCLK_IEP_GATE 376U +#define CLK_IEP_CORE_GATE 377U +#define HCLK_EBC_GATE 378U +#define DCLK_EBC_GATE 379U +#define ACLK_JDEC_GATE 380U +#define HCLK_JDEC_GATE 381U +#define ACLK_JENC_GATE 382U +#define HCLK_JENC_GATE 383U +/********Name=GATE_CON24,Offset=0x360********/ +#define ACLK_RKVENC_PRE_GATE 384U +#define HCLK_RKVENC_PRE_GATE 385U +#define ACLK_RKVENC_NIU_GATE 387U +#define HCLK_RKVENC_NIU_GATE 388U +#define ACLK_RKVENC_GATE 390U +#define HCLK_RKVENC_GATE 391U +#define CLK_RKVENC_CORE_GATE 392U +/********Name=GATE_CON25,Offset=0x364********/ +#define ACLK_RKVDEC_PRE_GATE 400U +#define HCLK_RKVDEC_PRE_GATE 401U +#define ACLK_RKVDEC_NIU_GATE 402U +#define HCLK_RKVDEC_NIU_GATE 403U +#define ACLK_RKVDEC_GATE 404U +#define HCLK_RKVDEC_GATE 405U +#define CLK_RKVDEC_CA_GATE 406U +#define CLK_RKVDEC_CORE_GATE 407U +#define CLK_RKVDEC_HEVC_CA_GATE 408U +/********Name=GATE_CON26,Offset=0x368********/ +#define ACLK_BUS_GATE 416U +#define PCLK_BUS_GATE 417U +#define ACLK_BUS_NIU_GATE 418U +#define PCLK_BUS_NIU_GATE 419U +#define PCLK_TSADC_GATE 420U +#define CLK_TSADC_TSEN_GATE 421U +#define CLK_TSADC_GATE 422U +#define PCLK_SARADC_GATE 423U +#define CLK_SARADC_GATE 424U +#define PCLK_OTPC_NS_GATE 425U +#define CLK_OTPC_NS_SBPI_GATE 426U +#define CLK_OTPC_NS_USR_GATE 427U +#define PCLK_SCR_GATE 428U +#define PCLK_WDT_NS_GATE 429U +#define TCLK_WDT_NS_GATE 430U +/********Name=GATE_CON27,Offset=0x36C********/ +#define PCLK_GRF_GATE 432U +#define PCLK_GRF_VCCIO12_GATE 433U +#define PCLK_GRF_VCCIO34_GATE 434U +#define PCLK_GRF_VCCIO567_GATE 435U +#define PCLK_DFT2APB_GATE 436U +#define PCLK_CAN0_GATE 437U +#define CLK_CAN0_GATE 438U +#define PCLK_CAN1_GATE 439U +#define CLK_CAN1_GATE 440U +#define PCLK_CAN2_GATE 441U +#define CLK_CAN2_GATE 442U +#define PCLK_UART1_GATE 444U +#define CLK_UART1_GATE 445U +#define CLK_UART1_FRAC_GATE 446U +#define SCLK_UART1_GATE 447U +/********Name=GATE_CON28,Offset=0x370********/ +#define PCLK_UART2_GATE 448U +#define CLK_UART2_GATE 449U +#define CLK_UART2_FRAC_GATE 450U +#define SCLK_UART2_GATE 451U +#define PCLK_UART3_GATE 452U +#define CLK_UART3_GATE 453U +#define CLK_UART3_FRAC_GATE 454U +#define SCLK_UART3_GATE 455U +#define PCLK_UART4_GATE 456U +#define CLK_UART4_GATE 457U +#define CLK_UART4_FRAC_GATE 458U +#define SCLK_UART4_GATE 459U +#define PCLK_UART5_GATE 460U +#define CLK_UART5_GATE 461U +#define CLK_UART5_FRAC_GATE 462U +#define SCLK_UART5_GATE 463U +/********Name=GATE_CON29,Offset=0x374********/ +#define PCLK_UART6_GATE 464U +#define CLK_UART6_GATE 465U +#define CLK_UART6_FRAC_GATE 466U +#define SCLK_UART6_GATE 467U +#define PCLK_UART7_GATE 468U +#define CLK_UART7_GATE 469U +#define CLK_UART7_FRAC_GATE 470U +#define SCLK_UART7_GATE 471U +#define PCLK_UART8_GATE 472U +#define CLK_UART8_GATE 473U +#define CLK_UART8_FRAC_GATE 474U +#define SCLK_UART8_GATE 475U +#define PCLK_UART9_GATE 476U +#define CLK_UART9_GATE 477U +#define CLK_UART9_FRAC_GATE 478U +#define SCLK_UART9_GATE 479U +/********Name=GATE_CON30,Offset=0x378********/ +#define PCLK_I2C1_GATE 480U +#define CLK_I2C1_GATE 481U +#define PCLK_I2C2_GATE 482U +#define CLK_I2C2_GATE 483U +#define PCLK_I2C3_GATE 484U +#define CLK_I2C3_GATE 485U +#define PCLK_I2C4_GATE 486U +#define CLK_I2C4_GATE 487U +#define PCLK_I2C5_GATE 488U +#define CLK_I2C5_GATE 489U +#define PCLK_SPI0_GATE 490U +#define CLK_SPI0_GATE 491U +#define PCLK_SPI1_GATE 492U +#define CLK_SPI1_GATE 493U +#define PCLK_SPI2_GATE 494U +#define CLK_SPI2_GATE 495U +/********Name=GATE_CON31,Offset=0x37C********/ +#define PCLK_SPI3_GATE 496U +#define CLK_SPI3_GATE 497U +#define PCLK_GPIO1_GATE 498U +#define DBCLK_GPIO1_GATE 499U +#define PCLK_GPIO2_GATE 500U +#define DBCLK_GPIO2_GATE 501U +#define PCLK_GPIO3_GATE 502U +#define DBCLK_GPIO3_GATE 503U +#define PCLK_GPIO4_GATE 504U +#define DBCLK_GPIO4_GATE 505U +#define PCLK_PWM1_GATE 506U +#define CLK_PWM1_GATE 507U +#define CLK_PWM1_CAPTURE_GATE 508U +#define PCLK_PWM2_GATE 509U +#define CLK_PWM2_GATE 510U +#define CLK_PWM2_CAPTURE_GATE 511U +/********Name=GATE_CON32,Offset=0x380********/ +#define PCLK_PWM3_GATE 512U +#define CLK_PWM3_GATE 513U +#define CLK_PWM3_CAPTURE_GATE 514U +#define PCLK_TIMER_GATE 515U +#define CLK_TIMER0_GATE 516U +#define CLK_TIMER1_GATE 517U +#define CLK_TIMER2_GATE 518U +#define CLK_TIMER3_GATE 519U +#define CLK_TIMER4_GATE 520U +#define CLK_TIMER5_GATE 521U +#define CLK_I2C_GATE 522U +#define DBCLK_GPIO_GATE 523U +#define CLK_TIMER_GATE 524U +#define ACLK_MCU_GATE 525U +#define PCLK_INTMUX_GATE 526U +#define PCLK_MAILBOX_GATE 527U +/********Name=GATE_CON33,Offset=0x384********/ +#define ACLK_TOP_HIGH_GATE 528U +#define ACLK_TOP_LOW_GATE 529U +#define HCLK_TOP_GATE 530U +#define PCLK_TOP_GATE 531U +#define ACLK_TOP_HIGH_NIU_GATE 532U +#define ACLK_TOP_LOW_NIU_GATE 533U +#define HCLK_TOP_NIU_GATE 534U +#define PCLK_TOP_NIU_GATE 535U +#define PCLK_PCIE30PHY_GATE 536U +#define CLK_OTPC_ARB_GATE 537U +#define PCLK_TOP_CRU_GATE 540U +#define PCLK_MIPICSIPHY_GATE 541U +#define PCLK_MIPIDSIPHY0_GATE 542U +#define PCLK_MIPIDSIPHY1_GATE 543U +/********Name=GATE_CON34,Offset=0x388********/ +#define PCLK_APB2ASB_CHIP_LEFT_GATE 544U +#define PCLK_APB2ASB_CHIP_BOTTOM_GATE 545U +#define PCLK_ASB2APB_CHIP_LEFT_GATE 546U +#define PCLK_ASB2APB_CHIP_BOTTOM_GATE 547U +#define PCLK_PIPEPHY0_GATE 548U +#define PCLK_PIPEPHY1_GATE 549U +#define PCLK_PIPEPHY2_GATE 550U +#define PCLK_USB2PHY0_GRF_GATE 551U +#define PCLK_USB2PHY1_GRF_GATE 552U +#define PCLK_DDRPHY_GATE 553U +#define CLK_DDRPHY_GATE 554U +#define PCLK_CPU_BOOST_GATE 555U +#define CLK_CPU_BOOST_GATE 556U +#define PCLK_OTPPHY_GATE 557U +#define PCLK_EDPPHY_GRF_GATE 558U +#define CLK_TESTOUT_GATE 559U +/********Name=GATE_CON35,Offset=0x38C********/ +#define CLK_GPLL_DIV_400M_GATE 560U +#define CLK_GPLL_DIV_300M_GATE 561U +#define CLK_GPLL_DIV_200M_GATE 562U +#define CLK_GPLL_DIV_150M_GATE 563U +#define CLK_GPLL_DIV_100M_GATE 564U +#define CLK_GPLL_DIV_75M_GATE 565U +#define CLK_GPLL_DIV_20M_GATE 566U +#define CLK_CPLL_DIV_500M_GATE 567U +#define CLK_CPLL_DIV_333M_GATE 568U +#define CLK_CPLL_DIV_250M_GATE 569U +#define CLK_CPLL_DIV_125M_GATE 570U +#define CLK_CPLL_DIV_100M_GATE 571U +#define CLK_CPLL_DIV_62P5_GATE 572U +#define CLK_CPLL_DIV_50M_GATE 573U +#define CLK_CPLL_DIV_25M_GATE 574U +#define CLK_OSC0_DIV_750K_GATE 575U +/********Name=PMUGATE_CON00,Offset=0x180********/ +#define XIN_OSC0_DIV_GATE 576U +#define CLK_OSC0_DIV32K_GATE 577U +#define PCLK_PDPMU_GATE 578U +#define PCLK_PDPMU_NIU_GATE 579U +#define PCLK_PMUCRU_GATE 580U +#define PCLK_PMUGRF_GATE 581U +#define PCLK_PMU_GATE 582U +#define CLK_PMU_GATE 583U +/********Name=PMUGATE_CON01,Offset=0x184********/ +#define PCLK_I2C0_GATE 592U +#define CLK_I2C0_GATE 593U +#define PCLK_UART0_GATE 594U +#define SCLK_UART0_DIV_GATE 595U +#define SCLK_UART0_FRACDIV_GATE 596U +#define SCLK_UART0_GATE 597U +#define PCLK_PWM0_GATE 598U +#define CLK_PWM0_GATE 599U +#define CLK_CAPTURE_PWM0_GATE 600U +#define PCLK_GPIO0_GATE 601U +#define DBCLK_GPIO0_GATE 602U +#define PCLK_PMUPVTM_GATE 603U +#define CLK_PMUPVTM_GATE 604U +#define CLK_CORE_PMUPVTM_GATE 605U +/********Name=PMUGATE_CON02,Offset=0x188********/ +#define CLK_REF24M_GATE 608U +#define XIN_OSC0_USBPHY0_GATE 609U +#define XIN_OSC0_USBPHY1_GATE 610U +#define XIN_OSC0_MIPIDSIPHY0_GATE 611U +#define XIN_OSC0_MIPIDSIPHY1_GATE 612U +#define CLK_WIFI_DIV_GATE 613U +#define CLK_WIFI_OSC0_GATE 614U +#define CLK_PCIEPHY0_DIV_GATE 615U +#define CLK_PCIEPHY0_OSC0_GATE 616U +#define CLK_PCIEPHY1_DIV_GATE 617U +#define CLK_PCIEPHY1_OSC0_GATE 618U +#define CLK_PCIEPHY2_DIV_GATE 619U +#define CLK_PCIEPHY2_OSC0_GATE 620U +#define CLK_PCIE30PHY_REF_M_GATE 621U +#define CLK_PCIE30PHY_REF_N_GATE 622U +#define XIN_OSC0_EDPPHY_GATE 623U + +/********Name=CLKSEL_CON00,Offset=0x100********/ +#define CLK_CORE0_DIV 0x05000000U +#define CLK_CORE1_DIV 0x05080000U +/********Name=CLKSEL_CON01,Offset=0x104********/ +#define CLK_CORE2_DIV 0x05000001U +#define CLK_CORE3_DIV 0x05080001U +/********Name=CLKSEL_CON02,Offset=0x108********/ +#define SCLK_CORE_SRC_DIV 0x04000002U +/********Name=CLKSEL_CON03,Offset=0x10C********/ +#define ATCLK_CORE_DIV 0x05000003U +#define GICCLK_CORE_DIV 0x05080003U +/********Name=CLKSEL_CON04,Offset=0x110********/ +#define PCLK_CORE_PRE_DIV 0x05000004U +#define PERIPHCLK_CORE_PRE_DIV 0x05080004U +/********Name=CLKSEL_CON05,Offset=0x114********/ +#define ACLK_CORE_NDFT_DIV 0x05080005U +/********Name=CLKSEL_CON06,Offset=0x118********/ +#define CLK_GPU_PRE_DIV 0x04000006U +#define ACLK_GPU_PRE_DIV 0x02080006U +#define PCLK_GPU_PRE_DIV 0x040C0006U +/********Name=CLKSEL_CON07,Offset=0x11C********/ +#define CLK_NPU_SRC_DIV 0x04000007U +#define CLK_NPU_NP5_DIV 0x02040007U +/********Name=CLKSEL_CON08,Offset=0x120********/ +#define HCLK_NPU_PRE_DIV 0x04000008U +#define PCLK_NPU_PRE_DIV 0x04040008U +/********Name=CLKSEL_CON09,Offset=0x124********/ +#define CLK_DDRPHY1X_SRC_DIV 0x05000009U +/********Name=CLKSEL_CON10,Offset=0x128********/ +#define CLK_MSCH_DIV 0x0200000AU +/********Name=CLKSEL_CON11,Offset=0x12C********/ +#define CLK_I2S0_8CH_TX_SRC_DIV 0x0700000BU +/********Name=CLKSEL_CON12,Offset=0x130********/ +#define CLK_I2S0_8CH_TX_FRAC_DIV 0x2000000CU +/********Name=CLKSEL_CON13,Offset=0x134********/ +#define CLK_I2S0_8CH_RX_SRC_DIV 0x0700000DU +/********Name=CLKSEL_CON14,Offset=0x138********/ +#define CLK_I2S0_8CH_RX_FRAC_DIV 0x2000000EU +/********Name=CLKSEL_CON15,Offset=0x13C********/ +#define CLK_I2S1_8CH_TX_SRC_DIV 0x0700000FU +/********Name=CLKSEL_CON16,Offset=0x140********/ +#define CLK_I2S1_8CH_TX_FRAC_DIV 0x20000010U +/********Name=CLKSEL_CON17,Offset=0x144********/ +#define CLK_I2S1_8CH_RX_SRC_DIV 0x07000011U +/********Name=CLKSEL_CON18,Offset=0x148********/ +#define CLK_I2S1_8CH_RX_FRAC_DIV 0x20000012U +/********Name=CLKSEL_CON19,Offset=0x14C********/ +#define CLK_I2S2_2CH_SRC_DIV 0x07000013U +/********Name=CLKSEL_CON20,Offset=0x150********/ +#define CLK_I2S2_2CH_FRAC_DIV 0x20000014U +/********Name=CLKSEL_CON21,Offset=0x154********/ +#define CLK_I2S3_2CH_TX_SRC_DIV 0x07000015U +/********Name=CLKSEL_CON22,Offset=0x158********/ +#define CLK_I2S3_2CH_TX_FRAC_DIV 0x20000016U +/********Name=CLKSEL_CON23,Offset=0x15C********/ +#define MCLK_SPDIF_8CH_SRC_DIV 0x07000017U +/********Name=CLKSEL_CON24,Offset=0x160********/ +#define MCLK_SPDIF_8CH_FRAC_DIV 0x20000018U +/********Name=CLKSEL_CON25,Offset=0x164********/ +#define SCLK_AUDPWM_SRC_DIV 0x06000019U +/********Name=CLKSEL_CON26,Offset=0x168********/ +#define SCLK_AUDPWM_FRAC_DIV 0x2000001AU +/********Name=CLKSEL_CON27,Offset=0x16C********/ +/********Name=CLKSEL_CON28,Offset=0x170********/ +/********Name=CLKSEL_CON29,Offset=0x174********/ +#define PCLK_PIPE_DIV 0x0404001DU +/********Name=CLKSEL_CON30,Offset=0x178********/ +#define PCLK_PHP_DIV 0x0404001EU +/********Name=CLKSEL_CON31,Offset=0x17C********/ +/********Name=CLKSEL_CON32,Offset=0x180********/ +#define PCLK_USB_DIV 0x04040020U +/********Name=CLKSEL_CON33,Offset=0x184********/ +/********Name=CLKSEL_CON34,Offset=0x188********/ +#define HCLK_VI_DIV 0x04040022U +#define PCLK_VI_DIV 0x04080022U +/********Name=CLKSEL_CON35,Offset=0x18C********/ +#define CLK_ISP_DIV 0x05000023U +#define CLK_CIF_OUT_DIV 0x06080023U +/********Name=CLKSEL_CON36,Offset=0x190********/ +#define CLK_CAM0_OUT_DIV 0x06000024U +#define CLK_CAM1_OUT_DIV 0x06080024U +/********Name=CLKSEL_CON37,Offset=0x194********/ +#define HCLK_VO_DIV 0x04080025U +#define PCLK_VO_DIV 0x040C0025U +/********Name=CLKSEL_CON38,Offset=0x198********/ +#define ACLK_VOP_PRE_DIV 0x05000026U +/********Name=CLKSEL_CON39,Offset=0x19C********/ +#define DCLK0_VOP_DIV 0x08000027U +/********Name=CLKSEL_CON40,Offset=0x1A0********/ +#define DCLK1_VOP_DIV 0x08000028U +/********Name=CLKSEL_CON41,Offset=0x1A4********/ +#define DCLK2_VOP_DIV 0x08000029U +/********Name=CLKSEL_CON42,Offset=0x1A8********/ +#define ACLK_VPU_PRE_DIV 0x0500002AU +#define HCLK_VPU_PRE_DIV 0x0408002AU +/********Name=CLKSEL_CON43,Offset=0x1AC********/ +#define HCLK_RGA_PRE_DIV 0x0408002BU +#define PCLK_RGA_PRE_DIV 0x040C002BU +/********Name=CLKSEL_CON44,Offset=0x1B0********/ +#define ACLK_RKVENC_PRE_DIV 0x0500002CU +#define HCLK_RKVENC_PRE_DIV 0x0408002CU +/********Name=CLKSEL_CON45,Offset=0x1B4********/ +#define CLK_RKVENC_CORE_DIV 0x0500002DU +/********Name=CLKSEL_CON47,Offset=0x1BC********/ +#define ACLK_RKVDEC_PRE_DIV 0x0500002FU +#define HCLK_RKVDEC_PRE_DIV 0x0408002FU +/********Name=CLKSEL_CON48,Offset=0x1C0********/ +#define CLK_RKVDEC_CA_DIV 0x05000030U +/********Name=CLKSEL_CON49,Offset=0x1C4********/ +#define CLK_RKVDEC_HEVC_CA_DIV 0x05000031U +#define CLK_RKVDEC_CORE_DIV 0x05080031U +/********Name=CLKSEL_CON50,Offset=0x1C8********/ +/********Name=CLKSEL_CON51,Offset=0x1CC********/ +#define CLK_TSADC_TSEN_DIV 0x03000033U +#define CLK_TSADC_DIV 0x07080033U +/********Name=CLKSEL_CON52,Offset=0x1D0********/ +#define CLK_UART1_SRC_DIV 0x07000034U +/********Name=CLKSEL_CON53,Offset=0x1D4********/ +#define CLK_UART1_FRAC_DIV 0x20000035U +/********Name=CLKSEL_CON54,Offset=0x1D8********/ +#define CLK_UART2_SRC_DIV 0x07000036U +/********Name=CLKSEL_CON55,Offset=0x1DC********/ +#define CLK_UART2_FRAC_DIV 0x20000037U +/********Name=CLKSEL_CON56,Offset=0x1E0********/ +#define CLK_UART3_SRC_DIV 0x07000038U +/********Name=CLKSEL_CON57,Offset=0x1E4********/ +#define CLK_UART3_FRAC_DIV 0x20000039U +/********Name=CLKSEL_CON58,Offset=0x1E8********/ +#define CLK_UART4_SRC_DIV 0x0700003AU +/********Name=CLKSEL_CON59,Offset=0x1EC********/ +#define CLK_UART4_FRAC_DIV 0x2000003BU +/********Name=CLKSEL_CON60,Offset=0x1F0********/ +#define CLK_UART5_SRC_DIV 0x0700003CU +/********Name=CLKSEL_CON61,Offset=0x1F4********/ +#define CLK_UART5_FRAC_DIV 0x2000003DU +/********Name=CLKSEL_CON62,Offset=0x1F8********/ +#define CLK_UART6_SRC_DIV 0x0700003EU +/********Name=CLKSEL_CON63,Offset=0x1FC********/ +#define CLK_UART6_FRAC_DIV 0x2000003FU +/********Name=CLKSEL_CON64,Offset=0x200********/ +#define CLK_UART7_SRC_DIV 0x07000040U +/********Name=CLKSEL_CON65,Offset=0x204********/ +#define CLK_UART7_FRAC_DIV 0x20000041U +/********Name=CLKSEL_CON66,Offset=0x208********/ +#define CLK_UART8_SRC_DIV 0x07000042U +/********Name=CLKSEL_CON67,Offset=0x20C********/ +#define CLK_UART8_FRAC_DIV 0x20000043U +/********Name=CLKSEL_CON68,Offset=0x210********/ +#define CLK_UART9_SRC_DIV 0x07000044U +/********Name=CLKSEL_CON69,Offset=0x214********/ +#define CLK_UART9_FRAC_DIV 0x20000045U +/********Name=CLKSEL_CON70,Offset=0x218********/ +#define CLK_CAN0_DIV 0x05000046U +#define CLK_CAN1_DIV 0x05080046U +/********Name=CLKSEL_CON71,Offset=0x21C********/ +#define CLK_CAN2_DIV 0x05000047U +/********Name=CLKSEL_CON72,Offset=0x220********/ +/********Name=CLKSEL_CON73,Offset=0x224********/ +/********Name=CLKSEL_CON74,Offset=0x228********/ +#define CLK_TESTOUT_DIV 0x0800004AU +/********Name=CLKSEL_CON75,Offset=0x22C********/ +#define CLK_GPLL_DIV_400M_DIV 0x0500004BU +#define CLK_GPLL_DIV_300M_DIV 0x0508004BU +/********Name=CLKSEL_CON76,Offset=0x230********/ +#define CLK_GPLL_DIV_200M_DIV 0x0500004CU +#define CLK_GPLL_DIV_150M_DIV 0x0508004CU +/********Name=CLKSEL_CON77,Offset=0x234********/ +#define CLK_GPLL_DIV_100M_DIV 0x0500004DU +#define CLK_GPLL_DIV_75M_DIV 0x0508004DU +/********Name=CLKSEL_CON78,Offset=0x238********/ +#define CLK_GPLL_DIV_20M_DIV 0x0600004EU +#define CLK_CPLL_DIV_500M_DIV 0x0508004EU +/********Name=CLKSEL_CON79,Offset=0x23C********/ +#define CLK_CPLL_DIV_333M_DIV 0x0500004FU +#define CLK_CPLL_DIV_250M_DIV 0x0508004FU +/********Name=CLKSEL_CON80,Offset=0x240********/ +#define CLK_CPLL_DIV_125M_DIV 0x05000050U +#define CLK_CPLL_DIV_62P5_DIV 0x05080050U +/********Name=CLKSEL_CON81,Offset=0x244********/ +#define CLK_CPLL_DIV_50M_DIV 0x05000051U +#define CLK_CPLL_DIV_25M_DIV 0x06080051U +/********Name=CLKSEL_CON82,Offset=0x248********/ +#define CLK_CPLL_DIV_100M_DIV 0x05000052U +#define CLK_OSC0_DIV_750K_DIV 0x06080052U +/********Name=CLKSEL_CON83,Offset=0x24C********/ +#define CLK_I2S3_2CH_RX_SRC_DIV 0x07000053U +/********Name=CLKSEL_CON84,Offset=0x250********/ +#define CLK_I2S3_2CH_RX_FRAC_DIV 0x20000054U + +/********Name=CLKSEL_CON00,Offset=0x100********/ +#define CLK_CORE_I_SEL 0x01060000U +#define CLK_CORE_I_SEL_CLK_GPLL_MUX 0U +#define CLK_CORE_NDFT_SEL 0x01070000U +#define CLK_CORE_NDFT_SEL_CLK_APLL_CORE 0U +#define CLK_CORE_NDFT_MUX_SEL 0x010F0000U +#define CLK_CORE_NDFT_MUX_SEL_CORE_PVTPLL_OUT 0U +/********Name=CLKSEL_CON01,Offset=0x104********/ +/********Name=CLKSEL_CON02,Offset=0x108********/ +#define SCLK_CORE_SRC_SEL 0x02080002U +#define SCLK_CORE_SRC_SEL_CLK_NPLL_MUX 0U +#define SCLK_CORE_PRE_SEL 0x010F0002U +#define SCLK_CORE_PRE_SEL_CLK_NPLL_CORE 0U +/********Name=CLKSEL_CON03,Offset=0x10C********/ +/********Name=CLKSEL_CON04,Offset=0x110********/ +/********Name=CLKSEL_CON05,Offset=0x114********/ +#define ACLK_CORE_NIU2BUS_SEL 0x020E0005U +#define ACLK_CORE_NIU2BUS_SEL_XIN_OSC0_FUNC_MUX 0U +/********Name=CLKSEL_CON06,Offset=0x118********/ +#define CLK_GPU_PRE_SEL 0x02060006U +#define CLK_GPU_PRE_SEL_CLK_NPLL_MUX 0U +#define CLK_GPU_PRE_MUX_SEL 0x010B0006U +#define CLK_GPU_PRE_MUX_SEL_GPU_PVTPLL_OUT 0U +/********Name=CLKSEL_CON07,Offset=0x11C********/ +#define CLK_NPU_SRC_SEL 0x01060007U +#define CLK_NPU_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_NPU_NP5_SEL 0x01070007U +#define CLK_NPU_NP5_SEL_CLK_GPLL_MUX 0U +#define CLK_NPU_PRE_NDFT_SEL 0x01080007U +#define CLK_NPU_PRE_NDFT_SEL_CLK_NPU_NP5 0U +#define CLK_NPU_PRE_MUX_SEL 0x010F0007U +#define CLK_NPU_PRE_MUX_SEL_NPU_PVTPLL_OUT 0U +/********Name=CLKSEL_CON08,Offset=0x120********/ +/********Name=CLKSEL_CON09,Offset=0x124********/ +#define CLK_DDRPHY1X_SRC_SEL 0x02060009U +#define CLK_DDRPHY1X_SRC_SEL_CLK_CPLL_MUX 0U +#define CLK_DDRPHY1X_SEL 0x010F0009U +#define CLK_DDRPHY1X_SEL_CLK_DPLL_DDR 0U +/********Name=CLKSEL_CON10,Offset=0x128********/ +#define ACLK_PERIMID_SEL 0x0204000AU +#define ACLK_PERIMID_SEL_XIN_OSC0_FUNC_MUX 0U +#define HCLK_PERIMID_SEL 0x0206000AU +#define HCLK_PERIMID_SEL_XIN_OSC0_FUNC_MUX 0U +#define ACLK_GIC_AUDIO_SEL 0x0208000AU +#define ACLK_GIC_AUDIO_SEL_XIN_OSC0_FUNC_MUX 0U +#define HCLK_GIC_AUDIO_SEL 0x020A000AU +#define HCLK_GIC_AUDIO_SEL_XIN_OSC0_FUNC_MUX 0U +#define DCLK_SDMMC_BUFFER_SEL 0x020C000AU +#define DCLK_SDMMC_BUFFER_SEL_CLK_CPLL_DIV_50M 0U +/********Name=CLKSEL_CON11,Offset=0x12C********/ +#define CLK_I2S0_8CH_TX_SRC_SEL 0x0208000BU +#define CLK_I2S0_8CH_TX_SRC_SEL_CLK_NPLL_MUX 0U +#define MCLK_I2S0_8CH_TX_SEL 0x020A000BU +#define MCLK_I2S0_8CH_TX_SEL_XIN_OSC0_HALF 0U +#define I2S0_MCLKOUT_TX_SEL 0x010F000BU +#define I2S0_MCLKOUT_TX_SEL_XIN_OSC0_HALF 0U +/********Name=CLKSEL_CON12,Offset=0x130********/ +/********Name=CLKSEL_CON13,Offset=0x134********/ +#define CLK_I2S0_8CH_RX_SRC_SEL 0x0208000DU +#define CLK_I2S0_8CH_RX_SRC_SEL_CLK_NPLL_MUX 0U +#define MCLK_I2S0_8CH_RX_SEL 0x020A000DU +#define MCLK_I2S0_8CH_RX_SEL_XIN_OSC0_HALF 0U +#define I2S0_MCLKOUT_RX_SEL 0x010F000DU +#define I2S0_MCLKOUT_RX_SEL_XIN_OSC0_HALF 0U +/********Name=CLKSEL_CON14,Offset=0x138********/ +/********Name=CLKSEL_CON15,Offset=0x13C********/ +#define CLK_I2S1_8CH_TX_SRC_SEL 0x0208000FU +#define CLK_I2S1_8CH_TX_SRC_SEL_CLK_NPLL_MUX 0U +#define MCLK_I2S1_8CH_TX_SEL 0x020A000FU +#define MCLK_I2S1_8CH_TX_SEL_XIN_OSC0_HALF 0U +#define I2S1_MCLKOUT_TX_SEL 0x010F000FU +#define I2S1_MCLKOUT_TX_SEL_XIN_OSC0_HALF 0U +/********Name=CLKSEL_CON16,Offset=0x140********/ +/********Name=CLKSEL_CON17,Offset=0x144********/ +#define CLK_I2S1_8CH_RX_SRC_SEL 0x02080011U +#define CLK_I2S1_8CH_RX_SRC_SEL_CLK_NPLL_MUX 0U +#define MCLK_I2S1_8CH_RX_SEL 0x020A0011U +#define MCLK_I2S1_8CH_RX_SEL_XIN_OSC0_HALF 0U +#define I2S1_MCLKOUT_RX_SEL 0x010F0011U +#define I2S1_MCLKOUT_RX_SEL_XIN_OSC0_HALF 0U +/********Name=CLKSEL_CON18,Offset=0x148********/ +/********Name=CLKSEL_CON19,Offset=0x14C********/ +#define CLK_I2S2_2CH_SRC_SEL 0x02080013U +#define CLK_I2S2_2CH_SRC_SEL_CLK_NPLL_MUX 0U +#define MCLK_I2S2_2CH_SEL 0x020A0013U +#define MCLK_I2S2_2CH_SEL_XIN_OSC0_HALF 0U +#define I2S2_MCLKOUT_SEL 0x010F0013U +#define I2S2_MCLKOUT_SEL_XIN_OSC0_HALF 0U +/********Name=CLKSEL_CON20,Offset=0x150********/ +/********Name=CLKSEL_CON21,Offset=0x154********/ +#define CLK_I2S3_2CH_TX_SRC_SEL 0x02080015U +#define CLK_I2S3_2CH_TX_SRC_SEL_CLK_NPLL_MUX 0U +#define MCLK_I2S3_2CH_TX_SEL 0x020A0015U +#define MCLK_I2S3_2CH_TX_SEL_XIN_OSC0_HALF 0U +#define I2S3_MCLKOUT_TX_SEL 0x010F0015U +#define I2S3_MCLKOUT_TX_SEL_XIN_OSC0_HALF 0U +/********Name=CLKSEL_CON22,Offset=0x158********/ +/********Name=CLKSEL_CON23,Offset=0x15C********/ +#define MCLK_PDM_SEL 0x02080017U +#define MCLK_PDM_SEL_CLK_GPLL_DIV_100M 0U +#define CLK_ACDCDIG_I2C_SEL 0x020A0017U +#define CLK_ACDCDIG_I2C_SEL_CLK_CPLL_DIV_100M 0U +#define MCLK_SPDIF_8CH_SRC_SEL 0x010E0017U +#define MCLK_SPDIF_8CH_SRC_SEL_CLK_GPLL_MUX 0U +#define MCLK_SPDIF_8CH_SEL 0x010F0017U +#define MCLK_SPDIF_8CH_SEL_MCLK_SPDIF_8CH_FRAC 0U +/********Name=CLKSEL_CON24,Offset=0x160********/ +/********Name=CLKSEL_CON25,Offset=0x164********/ +#define SCLK_AUDPWM_SRC_SEL 0x010E0019U +#define SCLK_AUDPWM_SRC_SEL_CLK_CPLL_MUX 0U +#define SCLK_AUDPWM_SEL 0x010F0019U +#define SCLK_AUDPWM_SEL_SCLK_AUDPWM_FRAC 0U +/********Name=CLKSEL_CON26,Offset=0x168********/ +/********Name=CLKSEL_CON27,Offset=0x16C********/ +#define ACLK_SECURE_FLASH_SEL 0x0200001BU +#define ACLK_SECURE_FLASH_SEL_XIN_OSC0_FUNC_MUX 0U +#define HCLK_SECURE_FLASH_SEL 0x0202001BU +#define HCLK_SECURE_FLASH_SEL_XIN_OSC0_FUNC_MUX 0U +#define CLK_CRYPTO_NS_CORE_SEL 0x0204001BU +#define CLK_CRYPTO_NS_CORE_SEL_CLK_GPLL_DIV_100M 0U +#define CLK_CRYPTO_NS_PKA_SEL 0x0206001BU +#define CLK_CRYPTO_NS_PKA_SEL_CLK_GPLL_DIV_100M 0U +/********Name=CLKSEL_CON28,Offset=0x170********/ +#define NCLK_NANDC_SEL 0x0200001CU +#define NCLK_NANDC_SEL_XIN_OSC0_FUNC_MUX 0U +#define SCLK_SFC_SEL 0x0304001CU +#define SCLK_SFC_SEL_CLK_GPLL_DIV_150M 0U +#define BCLK_EMMC_SEL 0x0208001CU +#define BCLK_EMMC_SEL_CLK_CPLL_DIV_125M 0U +#define CCLK_EMMC_SEL 0x030C001CU +#define CCLK_EMMC_SEL_CLK_OSC0_DIV_375K 0U +/********Name=CLKSEL_CON29,Offset=0x174********/ +#define ACLK_PIPE_SEL 0x0200001DU +#define ACLK_PIPE_SEL_XIN_OSC0_FUNC_MUX 0U +#define CLK_USB3OTG0_SUSPEND_SEL 0x0108001DU +#define CLK_USB3OTG0_SUSPEND_SEL_CLK_RTC_32K 0U +#define CLK_USB3OTG1_SUSPEND_SEL 0x0109001DU +#define CLK_USB3OTG1_SUSPEND_SEL_CLK_RTC_32K 0U +#define CLK_XPCS_EEE_SEL 0x010D001DU +#define CLK_XPCS_EEE_SEL_CLK_CPLL_DIV_125M 0U +/********Name=CLKSEL_CON30,Offset=0x178********/ +#define ACLK_PHP_SEL 0x0200001EU +#define ACLK_PHP_SEL_XIN_OSC0_FUNC_MUX 0U +#define HCLK_PHP_SEL 0x0202001EU +#define HCLK_PHP_SEL_XIN_OSC0_FUNC_MUX 0U +#define CLK_SDMMC0_SEL 0x0308001EU +#define CLK_SDMMC0_SEL_CLK_OSC0_DIV_750K 0U +#define CLK_SDMMC1_SEL 0x030C001EU +#define CLK_SDMMC1_SEL_CLK_OSC0_DIV_750K 0U +/********Name=CLKSEL_CON31,Offset=0x17C********/ +#define CLK_GMAC0_RX_TX_SEL 0x0200001FU +#define RMII0_EXTCLK_SEL 0x0102001FU +#define RMII0_EXTCLK_SEL_IO 0U +#define RMII0_CLK_SEL 0x0103001FU +#define RMII0_CLK_SEL_25M 0U +#define RGMII0_CLK_SEL 0x0204001FU +#define RGMII0_CLK_SEL_25M 0U +#define CLK_MAC0_2TOP_SEL 0x0208001FU +#define CLK_MAC0_2TOP_SEL_CLK_PPLL_MUX 0U +#define CLK_GMAC0_PTP_REF_SEL 0x020C001FU +#define CLK_GMAC0_PTP_REF_SEL_XIN_OSC0_FUNC_MUX 0U +#define CLK_MAC0_OUT_SEL 0x020E001FU +#define CLK_MAC0_OUT_SEL_XIN_OSC0_FUNC_MUX 0U +/********Name=CLKSEL_CON32,Offset=0x180********/ +#define ACLK_USB_SEL 0x02000020U +#define ACLK_USB_SEL_XIN_OSC0_FUNC_MUX 0U +#define HCLK_USB_SEL 0x02020020U +#define HCLK_USB_SEL_XIN_OSC0_FUNC_MUX 0U +#define CLK_SDMMC2_SEL 0x03080020U +#define CLK_SDMMC2_SEL_CLK_OSC0_DIV_750K 0U +/********Name=CLKSEL_CON33,Offset=0x184********/ +#define CLK_GMAC1_RX_TX_SEL 0x02000021U +#define RMII1_EXTCLK_SEL 0x01020021U +#define RMII1_EXTCLK_SEL_IO 0U +#define RMII1_CLK_SEL 0x01030021U +#define RMII1_CLK_SEL_25M 0U +#define RGMII1_CLK_SEL 0x02040021U +#define RGMII1_CLK_SEL_25M 0U +#define CLK_MAC1_2TOP_SEL 0x02080021U +#define CLK_MAC1_2TOP_SEL_CLK_PPLL_MUX 0U +#define CLK_GMAC1_PTP_REF_SEL 0x020C0021U +#define CLK_GMAC1_PTP_REF_SEL_XIN_OSC0_FUNC_MUX 0U +#define CLK_MAC1_OUT_SEL 0x020E0021U +#define CLK_MAC1_OUT_SEL_XIN_OSC0_FUNC_MUX 0U +/********Name=CLKSEL_CON34,Offset=0x188********/ +#define ACLK_VI_SEL 0x02000022U +#define ACLK_VI_SEL_XIN_OSC0_FUNC_MUX 0U +#define DCLK_VICAP1_SEL 0x020E0022U +#define DCLK_VICAP1_SEL_CLK_GPLL_DIV_200M 0U +/********Name=CLKSEL_CON35,Offset=0x18C********/ +#define CLK_ISP_SEL 0x02060023U +#define CLK_ISP_SEL_CLK_HPLL_MUX 0U +#define CLK_CIF_OUT_SEL 0x020E0023U +#define CLK_CIF_OUT_SEL_XIN_OSC0_FUNC_MUX 0U +/********Name=CLKSEL_CON36,Offset=0x190********/ +#define CLK_CAM0_OUT_SEL 0x02060024U +#define CLK_CAM0_OUT_SEL_XIN_OSC0_FUNC_MUX 0U +#define CLK_CAM1_OUT_SEL 0x020E0024U +#define CLK_CAM1_OUT_SEL_XIN_OSC0_FUNC_MUX 0U +/********Name=CLKSEL_CON37,Offset=0x194********/ +#define ACLK_VO_SEL 0x02000025U +#define ACLK_VO_SEL_XIN_OSC0_FUNC_MUX 0U +/********Name=CLKSEL_CON38,Offset=0x198********/ +#define ACLK_VOP_PRE_SEL 0x02060026U +#define ACLK_VOP_PRE_SEL_CLK_VPLL_MUX 0U +#define CLK_EDP_200M_SEL 0x02080026U +#define CLK_EDP_200M_SEL_CLK_CPLL_DIV_125M 0U +/********Name=CLKSEL_CON39,Offset=0x19C********/ +#define DCLK0_VOP_SEL 0x020A0027U +#define DCLK0_VOP_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON40,Offset=0x1A0********/ +#define DCLK1_VOP_SEL 0x020A0028U +#define DCLK1_VOP_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON41,Offset=0x1A4********/ +#define DCLK2_VOP_SEL 0x020A0029U +#define DCLK2_VOP_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON42,Offset=0x1A8********/ +#define ACLK_VPU_PRE_SEL 0x0107002AU +#define ACLK_VPU_PRE_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON43,Offset=0x1AC********/ +#define ACLK_RGA_PRE_SEL 0x0200002BU +#define ACLK_RGA_PRE_SEL_XIN_OSC0_FUNC_MUX 0U +#define CLK_RGA_CORE_SEL 0x0202002BU +#define CLK_RGA_CORE_SEL_CLK_CPLL_DIV_100M 0U +#define CLK_IEP_CORE_SEL 0x0204002BU +#define CLK_IEP_CORE_SEL_CLK_CPLL_DIV_100M 0U +#define DCLK_EBC_SEL 0x0206002BU +#define DCLK_EBC_SEL_CLK_GPLL_DIV_200M 0U +/********Name=CLKSEL_CON44,Offset=0x1B0********/ +#define ACLK_RKVENC_PRE_SEL 0x0206002CU +#define ACLK_RKVENC_PRE_SEL_CLK_NPLL_MUX 0U +/********Name=CLKSEL_CON45,Offset=0x1B4********/ +#define CLK_RKVENC_CORE_SEL 0x020E002DU +#define CLK_RKVENC_CORE_SEL_CLK_VPLL_MUX 0U +/********Name=CLKSEL_CON47,Offset=0x1BC********/ +#define ACLK_RKVDEC_PRE_SEL 0x0107002FU +#define ACLK_RKVDEC_PRE_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON48,Offset=0x1C0********/ +#define CLK_RKVDEC_CA_SEL 0x02060030U +#define CLK_RKVDEC_CA_SEL_CLK_VPLL_MUX 0U +/********Name=CLKSEL_CON49,Offset=0x1C4********/ +#define CLK_RKVDEC_HEVC_CA_SEL 0x02060031U +#define CLK_RKVDEC_HEVC_CA_SEL_CLK_VPLL_MUX 0U +#define CLK_RKVDEC_CORE_SEL 0x020E0031U +#define CLK_RKVDEC_CORE_SEL_CLK_VPLL_MUX 0U +/********Name=CLKSEL_CON50,Offset=0x1C8********/ +#define ACLK_BUS_SEL 0x02000032U +#define ACLK_BUS_SEL_XIN_OSC0_FUNC_MUX 0U +#define PCLK_BUS_SEL 0x02040032U +#define PCLK_BUS_SEL_XIN_OSC0_FUNC_MUX 0U +/********Name=CLKSEL_CON51,Offset=0x1CC********/ +#define CLK_TSADC_TSEN_SEL 0x02040033U +#define CLK_TSADC_TSEN_SEL_CLK_CPLL_DIV_100M 0U +/********Name=CLKSEL_CON52,Offset=0x1D0********/ +#define CLK_UART1_SRC_SEL 0x02080034U +#define CLK_UART1_SRC_SEL_USBPHY480M_MUX 0U +#define SCLK_UART1_SEL 0x020C0034U +#define SCLK_UART1_SEL_XIN_OSC0_FUNC_MUX 0U +/********Name=CLKSEL_CON53,Offset=0x1D4********/ +/********Name=CLKSEL_CON54,Offset=0x1D8********/ +#define CLK_UART2_SRC_SEL 0x02080036U +#define CLK_UART2_SRC_SEL_USBPHY480M_MUX 0U +#define SCLK_UART2_SEL 0x020C0036U +#define SCLK_UART2_SEL_XIN_OSC0_FUNC_MUX 0U +/********Name=CLKSEL_CON55,Offset=0x1DC********/ +/********Name=CLKSEL_CON56,Offset=0x1E0********/ +#define CLK_UART3_SRC_SEL 0x02080038U +#define CLK_UART3_SRC_SEL_USBPHY480M_MUX 0U +#define SCLK_UART3_SEL 0x020C0038U +#define SCLK_UART3_SEL_XIN_OSC0_FUNC_MUX 0U +/********Name=CLKSEL_CON57,Offset=0x1E4********/ +/********Name=CLKSEL_CON58,Offset=0x1E8********/ +#define CLK_UART4_SRC_SEL 0x0208003AU +#define CLK_UART4_SRC_SEL_USBPHY480M_MUX 0U +#define SCLK_UART4_SEL 0x020C003AU +#define SCLK_UART4_SEL_XIN_OSC0_FUNC_MUX 0U +/********Name=CLKSEL_CON59,Offset=0x1EC********/ +/********Name=CLKSEL_CON60,Offset=0x1F0********/ +#define CLK_UART5_SRC_SEL 0x0208003CU +#define CLK_UART5_SRC_SEL_USBPHY480M_MUX 0U +#define SCLK_UART5_SEL 0x020C003CU +#define SCLK_UART5_SEL_XIN_OSC0_FUNC_MUX 0U +/********Name=CLKSEL_CON61,Offset=0x1F4********/ +/********Name=CLKSEL_CON62,Offset=0x1F8********/ +#define CLK_UART6_SRC_SEL 0x0208003EU +#define CLK_UART6_SRC_SEL_USBPHY480M_MUX 0U +#define SCLK_UART6_SEL 0x020C003EU +#define SCLK_UART6_SEL_XIN_OSC0_FUNC_MUX 0U +/********Name=CLKSEL_CON63,Offset=0x1FC********/ +/********Name=CLKSEL_CON64,Offset=0x200********/ +#define CLK_UART7_SRC_SEL 0x02080040U +#define CLK_UART7_SRC_SEL_USBPHY480M_MUX 0U +#define SCLK_UART7_SEL 0x020C0040U +#define SCLK_UART7_SEL_XIN_OSC0_FUNC_MUX 0U +/********Name=CLKSEL_CON65,Offset=0x204********/ +/********Name=CLKSEL_CON66,Offset=0x208********/ +#define CLK_UART8_SRC_SEL 0x02080042U +#define CLK_UART8_SRC_SEL_USBPHY480M_MUX 0U +#define SCLK_UART8_SEL 0x020C0042U +#define SCLK_UART8_SEL_XIN_OSC0_FUNC_MUX 0U +/********Name=CLKSEL_CON67,Offset=0x20C********/ +/********Name=CLKSEL_CON68,Offset=0x210********/ +#define CLK_UART9_SRC_SEL 0x02080044U +#define CLK_UART9_SRC_SEL_USBPHY480M_MUX 0U +#define SCLK_UART9_SEL 0x020C0044U +#define SCLK_UART9_SEL_XIN_OSC0_FUNC_MUX 0U +/********Name=CLKSEL_CON69,Offset=0x214********/ +/********Name=CLKSEL_CON70,Offset=0x218********/ +#define CLK_CAN0_SEL 0x01070046U +#define CLK_CAN0_SEL_CLK_CPLL_MUX 0U +#define CLK_CAN1_SEL 0x010F0046U +#define CLK_CAN1_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON71,Offset=0x21C********/ +#define CLK_CAN2_SEL 0x01070047U +#define CLK_CAN2_SEL_CLK_CPLL_MUX 0U +#define CLK_I2C_SEL 0x02080047U +#define CLK_I2C_SEL_CLK_CPLL_DIV_100M 0U +/********Name=CLKSEL_CON72,Offset=0x220********/ +#define CLK_SPI0_SEL 0x02000048U +#define CLK_SPI0_SEL_CLK_CPLL_DIV_100M 0U +#define CLK_SPI1_SEL 0x02020048U +#define CLK_SPI1_SEL_CLK_CPLL_DIV_100M 0U +#define CLK_SPI2_SEL 0x02040048U +#define CLK_SPI2_SEL_CLK_CPLL_DIV_100M 0U +#define CLK_SPI3_SEL 0x02060048U +#define CLK_SPI3_SEL_CLK_CPLL_DIV_100M 0U +#define CLK_PWM1_SEL 0x02080048U +#define CLK_PWM1_SEL_CLK_CPLL_DIV_100M 0U +#define CLK_PWM2_SEL 0x020A0048U +#define CLK_PWM2_SEL_CLK_CPLL_DIV_100M 0U +#define CLK_PWM3_SEL 0x020C0048U +#define CLK_PWM3_SEL_CLK_CPLL_DIV_100M 0U +#define DBCLK_GPIO_SEL 0x010E0048U +#define DBCLK_GPIO_SEL_CLK_RTC_32K 0U +/********Name=CLKSEL_CON73,Offset=0x224********/ +#define ACLK_TOP_HIGH_SEL 0x02000049U +#define ACLK_TOP_HIGH_SEL_XIN_OSC0_FUNC_MUX 0U +#define ACLK_TOP_LOW_SEL 0x02040049U +#define ACLK_TOP_LOW_SEL_XIN_OSC0_FUNC_MUX 0U +#define HCLK_TOP_SEL 0x02080049U +#define HCLK_TOP_SEL_XIN_OSC0_FUNC_MUX 0U +#define PCLK_TOP_SEL 0x020C0049U +#define PCLK_TOP_SEL_XIN_OSC0_FUNC_MUX 0U +#define CLK_OTPC_ARB_SEL 0x010F0049U +#define CLK_OTPC_ARB_SEL_CLK_CPLL_DIV_100M 0U +/********Name=CLKSEL_CON74,Offset=0x228********/ +#define CLK_TESTOUT_SEL 0x0508004AU +#define CLK_TESTOUT_SEL_USBPHY480M_I 0U +/********Name=CLKSEL_CON75,Offset=0x22C********/ +/********Name=CLKSEL_CON76,Offset=0x230********/ +/********Name=CLKSEL_CON77,Offset=0x234********/ +/********Name=CLKSEL_CON78,Offset=0x238********/ +/********Name=CLKSEL_CON79,Offset=0x23C********/ +/********Name=CLKSEL_CON80,Offset=0x240********/ +/********Name=CLKSEL_CON81,Offset=0x244********/ +/********Name=CLKSEL_CON82,Offset=0x248********/ +/********Name=CLKSEL_CON83,Offset=0x24C********/ +#define CLK_I2S3_2CH_RX_SRC_SEL 0x02080053U +#define CLK_I2S3_2CH_RX_SRC_SEL_CLK_NPLL_MUX 0U +#define MCLK_I2S3_2CH_RX_SEL 0x020A0053U +#define MCLK_I2S3_2CH_RX_SEL_XIN_OSC0_HALF 0U +#define I2S3_MCLKOUT_RX_SEL 0x010F0053U +#define I2S3_MCLKOUT_RX_SEL_XIN_OSC0_HALF 0U +/********Name=CLKSEL_CON84,Offset=0x250********/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __RK3568_H */ \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/soc.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/soc.h new file mode 100644 index 000000000..8318bd75c --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/soc.h @@ -0,0 +1,449 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef __SOC_H +#define __SOC_H +#ifdef __cplusplus +extern "C" { +#endif + +#include "hal_conf.h" + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus +#define __I volatile /*!< brief Defines 'read only' permissions */ +#else +#define __I volatile const /*!< brief Defines 'read only' permissions */ +#endif +#define __O volatile /*!< brief Defines 'write only' permissions */ +#define __IO volatile /*!< brief Defines 'read / write' permissions */ + +/* ================================================================================ */ +/* ================ DMA REQ =============== */ +/* ================================================================================ */ +typedef enum { + DMA_REQ_UART0_TX = 0, + DMA_REQ_UART0_RX = 1, + DMA_REQ_UART1_TX = 2, + DMA_REQ_UART1_RX = 3, + DMA_REQ_UART2_TX = 4, + DMA_REQ_UART2_RX = 5, + DMA_REQ_UART3_TX = 6, + DMA_REQ_UART3_RX = 7, + DMA_REQ_UART4_TX = 8, + DMA_REQ_UART4_RX = 9, + DMA_REQ_UART5_TX = 10, + DMA_REQ_UART5_RX = 11, + DMA_REQ_UART6_TX = 12, + DMA_REQ_UART6_RX = 13, + DMA_REQ_UART7_TX = 14, + DMA_REQ_UART7_RX = 15, + DMA_REQ_UART8_TX = 16, + DMA_REQ_UART8_RX = 17, + DMA_REQ_UART9_TX = 18, + DMA_REQ_UART9_RX = 19, + DMA_REQ_SPI0_TX = 20, + DMA_REQ_SPI0_RX = 21, + DMA_REQ_SPI1_TX = 22, + DMA_REQ_SPI1_RX = 23, + DMA_REQ_SPI2_TX = 24, + DMA_REQ_SPI2_RX = 25, + DMA_REQ_SPI3_TX = 26, + DMA_REQ_SPI3_RX = 27, +} DMA_REQ_Type; + +/* ================================================================================ */ +/* ================ IRQ ================ */ +/* ================================================================================ */ +#ifdef HAL_MCU_CORE +#define INTMUX_IRQ_START_NUM 32 +#define INTMUX_OUT_IRQ_START_NUM 0 +#define INTMUX_NUM_INT_PER_OUT 64 +#define INTMUX_NUM_GROUP_PER_CON 8 +#define INTMUX_NUM_GROUP_PER_OUT 8 +#define INTMUX_NUM_INT_PER_GROUP 8 +#define NUM_EXT_INTERRUPTS 320 + +typedef enum +{ +/****** Platform Exceptions Numbers ***************************************************/ + NUM_INTERRUPTS = 0, + DMAC0_ABORT_IRQn = 45, /*!< DMAC0 Abort Interrupt */ + DMAC0_IRQn = 46, /*!< DMAC0 Interrupt */ + DMAC1_ABORT_IRQn = 47, /*!< DMAC1 Abort Interrupt */ + DMAC1_IRQn = 48, /*!< DMAC1 Interrupt */ + GPIO0_IRQn = 65, /*!< GPIO0 Interrupt */ + GPIO1_IRQn = 66, /*!< GPIO1 Interrupt */ + GPIO2_IRQn = 67, /*!< GPIO2 Interrupt */ + GPIO3_IRQn = 68, /*!< GPIO3 Interrupt */ + GPIO4_IRQn = 69, /*!< GPIO4 Interrupt */ + I2C0_IRQn = 78, /*!< I2C0 Interrupt */ + I2C1_IRQn = 79, /*!< I2C1 Interrupt */ + I2C2_IRQn = 80, /*!< I2C2 Interrupt */ + I2C3_IRQn = 81, /*!< I2C3 Interrupt */ + I2C4_IRQn = 82, /*!< I2C4 Interrupt */ + I2C5_IRQn = 83, /*!< I2C5 Interrupt */ + PWM_PMU_IRQn = 114, /*!< PWM_PMU Interrupt */ + PWM1_IRQn = 115, /*!< PWM1 Interrupt */ + PWM2_IRQn = 116, /*!< PWM2 Interrupt */ + PWM3_IRQn = 117, /*!< PWM3 Interrupt */ + PWM_PMU_PWR_IRQn = 118, /*!< PWM_PMU PWR Interrupt */ + PWM1_PWR_IRQn = 119, /*!< PWM1 PWR Interrupt */ + PWM2_PWR_IRQn = 120, /*!< PWM2 PWR Interrupt */ + PWM3_PWR_IRQn = 121, /*!< PWM3 PWR Interrupt */ + SARADC_IRQn = 125, /*!< SARADC Interrupt */ + FSPI0_IRQn = 133, /*!< FSPI Interrupt */ + SPI0_IRQn = 135, /*!< SPI0 Interrupt */ + SPI1_IRQn = 136, /*!< SPI1 Interrupt */ + SPI2_IRQn = 137, /*!< SPI2 Interrupt */ + SPI3_IRQn = 138, /*!< SPI3 Interrupt */ + TIMER0_IRQn = 141, /*!< TIMER0 Interrupt */ + TIMER1_IRQn = 142, /*!< TIMER1 Interrupt */ + TIMER2_IRQn = 143, /*!< TIMER2 Interrupt */ + TIMER3_IRQn = 144, /*!< TIMER3 Interrupt */ + TIMER4_IRQn = 145, /*!< TIMER4 Interrupt */ + TIMER5_IRQn = 146, /*!< TIMER5 Interrupt */ + UART0_IRQn = 148, /*!< UART0 Interrupt */ + UART1_IRQn = 149, /*!< UART1 Interrupt */ + UART2_IRQn = 150, /*!< UART2 Interrupt */ + UART3_IRQn = 151, /*!< UART3 Interrupt */ + UART4_IRQn = 152, /*!< UART4 Interrupt */ + UART5_IRQn = 153, /*!< UART5 Interrupt */ + UART6_IRQn = 154, /*!< UART6 Interrupt */ + UART7_IRQn = 155, /*!< UART7 Interrupt */ + UART8_IRQn = 156, /*!< UART8 Interrupt */ + UART9_IRQn = 157, /*!< UART9 Interrupt */ + WDT0_IRQn = 181, /*!< WDT0 Interrupt */ + MBOX0_CH0_B2A_IRQn = 215, /*!< MBOX0 CH0 B2A Interrupt */ + MBOX0_CH1_B2A_IRQn = 216, /*!< MBOX0 CH1 B2A Interrupt */ + MBOX0_CH2_B2A_IRQn = 217, /*!< MBOX0 CH2 B2A Interrupt */ + MBOX0_CH3_B2A_IRQn = 218, /*!< MBOX0 CH3 B2A Interrupt */ + MBOX0_CH0_A2B_IRQn = 219, /*!< MBOX0 CH0 A2B Interrupt */ + MBOX0_CH1_A2B_IRQn = 220, /*!< MBOX0 CH1 A2B Interrupt */ + MBOX0_CH2_A2B_IRQn = 221, /*!< MBOX0 CH2 A2B Interrupt */ + MBOX0_CH3_A2B_IRQn = 222, /*!< MBOX0 CH3 A2B Interrupt */ + TOTAL_INTERRUPTS = (INTMUX_IRQ_START_NUM + NUM_INTERRUPTS + NUM_EXT_INTERRUPTS), +} IRQn_Type; +#else +typedef enum +{ +/* When IPI_SGIs are used in AMP mode, you need to pay attention to whether it conflicts + * with SMP mode. Especially in the case of Linux OS as The Master Core. + * IPI_SGI 0~7 for non-secure and IPI_SGI 8~15 for secure. + */ + IPI_SGI0 = 0, + IPI_SGI1 = 1, + IPI_SGI2 = 2, + IPI_SGI3 = 3, + IPI_SGI4 = 4, + IPI_SGI5 = 5, + IPI_SGI6 = 6, + IPI_SGI7 = 7, + IPI_SGI8 = 8, + IPI_SGI9 = 9, + IPI_SGI10 = 10, + IPI_SGI11 = 11, + IPI_SGI12 = 12, + IPI_SGI13 = 13, + IPI_SGI14 = 14, + IPI_SGI15 = 15, + + CNTHP_IRQn = 26, + CNTV_IRQn = 27, + CNTPS_IRQn = 29, + CNTPNS_IRQn = 30, + +/****** Platform Exceptions Numbers ***************************************************/ + CAN0_IRQn = 33, /*!< CAN0 Interrupt */ + CAN1_IRQn = 34, /*!< CAN1 Interrupt */ + CAN2_IRQn = 35, /*!< CAN2 Interrupt */ + DMAC0_ABORT_IRQn = 45, /*!< DMAC0 Abort Interrupt */ + DMAC0_IRQn = 46, /*!< DMAC0 Interrupt */ + DMAC1_ABORT_IRQn = 47, /*!< DMAC1 Abort Interrupt */ + DMAC1_IRQn = 48, /*!< DMAC1 Interrupt */ + GMAC0_IRQn = 59, /*!< GMAC0 Interrupt */ + GMAC1_IRQn = 64, /*!< GMAC1 Interrupt */ + GPIO0_IRQn = 65, /*!< GPIO0 Interrupt */ + GPIO1_IRQn = 66, /*!< GPIO1 Interrupt */ + GPIO2_IRQn = 67, /*!< GPIO2 Interrupt */ + GPIO3_IRQn = 68, /*!< GPIO3 Interrupt */ + GPIO4_IRQn = 69, /*!< GPIO4 Interrupt */ + I2C0_IRQn = 78, /*!< I2C0 Interrupt */ + I2C1_IRQn = 79, /*!< I2C1 Interrupt */ + I2C2_IRQn = 80, /*!< I2C2 Interrupt */ + I2C3_IRQn = 81, /*!< I2C3 Interrupt */ + I2C4_IRQn = 82, /*!< I2C4 Interrupt */ + I2C5_IRQn = 83, /*!< I2C5 Interrupt */ + PWM_PMU_IRQn = 114, /*!< PWM_PMU Interrupt */ + PWM1_IRQn = 115, /*!< PWM1 Interrupt */ + PWM2_IRQn = 116, /*!< PWM2 Interrupt */ + PWM3_IRQn = 117, /*!< PWM3 Interrupt */ + PWM_PMU_PWR_IRQn = 118, /*!< PWM_PMU PWR Interrupt */ + PWM1_PWR_IRQn = 119, /*!< PWM1 PWR Interrupt */ + PWM2_PWR_IRQn = 120, /*!< PWM2 PWR Interrupt */ + PWM3_PWR_IRQn = 121, /*!< PWM3 PWR Interrupt */ + SARADC_IRQn = 125, /*!< SARADC Interrupt */ + FSPI0_IRQn = 133, /*!< FSPI Interrupt */ + SPI0_IRQn = 135, /*!< SPI0 Interrupt */ + SPI1_IRQn = 136, /*!< SPI1 Interrupt */ + SPI2_IRQn = 137, /*!< SPI2 Interrupt */ + SPI3_IRQn = 138, /*!< SPI3 Interrupt */ + TIMER0_IRQn = 141, /*!< TIMER0 Interrupt */ + TIMER1_IRQn = 142, /*!< TIMER1 Interrupt */ + TIMER2_IRQn = 143, /*!< TIMER2 Interrupt */ + TIMER3_IRQn = 144, /*!< TIMER3 Interrupt */ + TIMER4_IRQn = 145, /*!< TIMER4 Interrupt */ + TIMER5_IRQn = 146, /*!< TIMER5 Interrupt */ + UART0_IRQn = 148, /*!< UART0 Interrupt */ + UART1_IRQn = 149, /*!< UART1 Interrupt */ + UART2_IRQn = 150, /*!< UART2 Interrupt */ + UART3_IRQn = 151, /*!< UART3 Interrupt */ + UART4_IRQn = 152, /*!< UART4 Interrupt */ + UART5_IRQn = 153, /*!< UART5 Interrupt */ + UART6_IRQn = 154, /*!< UART6 Interrupt */ + UART7_IRQn = 155, /*!< UART7 Interrupt */ + UART8_IRQn = 156, /*!< UART8 Interrupt */ + UART9_IRQn = 157, /*!< UART9 Interrupt */ + WDT0_IRQn = 181, /*!< WDT0 Interrupt */ + PCIE30x2_LEGACY_IRQn = 194, /*!< PCIe3x2_legacy Interrupt */ + DDR_ECC_CE_IRQn = 205, /*!< DDR ECC correctable fault Interrupt */ + DDR_ECC_UE_IRQn = 207, /*!< DDR ECC uncorrectable fault Interrupt */ + MBOX0_CH0_B2A_IRQn = 215, /*!< MBOX0 CH0 B2A Interrupt */ + MBOX0_CH1_B2A_IRQn = 216, /*!< MBOX0 CH1 B2A Interrupt */ + MBOX0_CH2_B2A_IRQn = 217, /*!< MBOX0 CH2 B2A Interrupt */ + MBOX0_CH3_B2A_IRQn = 218, /*!< MBOX0 CH3 B2A Interrupt */ + MBOX0_CH0_A2B_IRQn = 219, /*!< MBOX0 CH0 A2B Interrupt */ + MBOX0_CH1_A2B_IRQn = 220, /*!< MBOX0 CH1 A2B Interrupt */ + MBOX0_CH2_A2B_IRQn = 221, /*!< MBOX0 CH2 A2B Interrupt */ + MBOX0_CH3_A2B_IRQn = 222, /*!< MBOX0 CH3 A2B Interrupt */ + NFAULT0_IRQn = 272, /*!< DSU L3 CACHE ECC FAULT Interrupt */ + NFAULT1_IRQn = 273, /*!< CPU0 L1-L2 CACHE ECC FAULT Interrupt */ + NFAULT2_IRQn = 274, /*!< CPU1 L1-L2 CACHE ECC FAULT Interrupt */ + NFAULT3_IRQn = 275, /*!< CPU2 L1-L2 CACHE ECC FAULT Interrupt */ + NFAULT4_IRQn = 276, /*!< CPU3 L1-L2 CACHE ECC FAULT Interrupt */ + NERR0_IRQn = 277, /*!< DSU L3 CACHE ECC ERROR Interrupt */ + NERR1_IRQn = 278, /*!< CPU0 L1-L2 CACHE ECC ERROR Interrupt */ + NERR2_IRQn = 279, /*!< CPU1 L1-L2 CACHE ECC ERROR Interrupt */ + NERR3_IRQn = 280, /*!< CPU2 L1-L2 CACHE ECC ERROR Interrupt */ + NERR4_IRQn = 281, /*!< CPU3 L1-L2 CACHE ECC ERROR Interrupt */ + RSVD0_IRQn = 283, /*!< RSVD0 Interrupt */ + RPMSG_01_IRQn = 285, /*!< RPMSG 0->1 Interrupt */ + RPMSG_02_IRQn = 286, /*!< RPMSG 0->2 Interrupt */ + RPMSG_03_IRQn = 287, /*!< RPMSG 0->3 Interrupt */ + RPMSG_10_IRQn = 288, /*!< RPMSG 1->0 Interrupt */ + RPMSG_12_IRQn = 289, /*!< RPMSG 1->2 Interrupt */ + RPMSG_13_IRQn = 290, /*!< RPMSG 1->3 Interrupt */ + RPMSG_20_IRQn = 291, /*!< RPMSG 2->0 Interrupt */ + RPMSG_21_IRQn = 292, /*!< RPMSG 2->1 Interrupt */ + RPMSG_23_IRQn = 293, /*!< RPMSG 2->3 Interrupt */ + RPMSG_30_IRQn = 294, /*!< RPMSG 3->0 Interrupt */ + RPMSG_31_IRQn = 295, /*!< RPMSG 3->1 Interrupt */ + RPMSG_32_IRQn = 296, /*!< RPMSG 3->2 Interrupt */ + NUM_INTERRUPTS = 352, +} IRQn_Type; +#endif + +#define RSVD_IRQn(_N) (RSVD0_IRQn + (_N)) + +#define AMP_CPUOFF_REQ_IRQ(cpu) RSVD_IRQn(11 + (cpu)) /* gic irq: 294 */ +#define GIC_TOUCH_REQ_IRQ(cpu) (AMP_CPUOFF_REQ_IRQ(4) + cpu) /* gic irq: 298 */ + +#define GPIO_IRQ_GROUP_DIRQ_BASE RSVD_IRQn(37) /* gic irq: 320 */ +#define GPIO_IRQ_GROUP_DIRQ_NUM (NUM_INTERRUPTS - GPIO_IRQ_GROUP_DIRQ_BASE) + +#define GPIO_IRQ_GROUP_GPIO0_HWIRQ GPIO0_IRQn +#define GPIO_IRQ_GROUP_GPION_HWIRQ GPIO4_IRQn + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +#if defined(HAL_AP_CORE) && defined(HAL_MCU_CORE) +#error "HAL_AP_CORE and HAL_MCU_CORE only one of them can be enabled" +#endif + +#if !defined(HAL_AP_CORE) && !defined(HAL_MCU_CORE) +#error "Please define HAL_AP_CORE or HAL_MCU_CORE on hal_conf.h" +#endif + +#ifdef HAL_AP_CORE +#define __CORTEX_A 55U /* Cortex-A55 Core */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __TIM_PRESENT 1U /* Generic Timer */ + +#define CACHE_LINE_SHIFT (6U) +#define CACHE_LINE_SIZE (0x1U << CACHE_LINE_SHIFT) + +#else +#define __RISC_V +#endif + +#ifndef __ASSEMBLY__ +// #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ +// #ifdef __CORTEX_A +// #include "core_ca.h" +// #endif +#include "system_rk3568.h" +#endif /* __ASSEMBLY__ */ +#include "rk3568.h" + +/****************************************************************************************/ +/* */ +/* Module Address Section */ +/* */ +/****************************************************************************************/ +/* Memory Base */ +#define PCIE3X2_DBI_BASE 0xF6000000 /* PCIe dbi base address */ +#define GIC_DISTRIBUTOR_BASE 0xFD400000 /* GICD base address */ +#define GIC_REDISTRIBUTOR_BASE 0xFD460000 /* GICR base address */ +#define PCIE3PHY_GRF_BASE 0xFDCB8000 /* S-PHY_GRF base address */ +#define PCIE3X2_APB_BASE 0xFE280000 /* PCIe apb base address */ + +/****************************************************************************************/ +/* */ +/* Register Bitmap Section */ +/* */ +/****************************************************************************************/ +/********************************** CPU Topology ****************************************/ +#define MPIDR_MT_MASK ((1U) << 24) +#define MPIDR_AFFLVL_MASK (0xFFU) +#define MPIDR_AFF0_SHIFT (0U) +#define MPIDR_AFF1_SHIFT (8U) +#define MPIDR_AFF2_SHIFT (16U) +#define MPIDR_AFF3_SHIFT (32U) +#define MPIDR_AFFINITY_MASK (0xFFFFFFU) +#define PLATFORM_CLUSTER0_CORE_COUNT (4) +#define PLATFORM_CLUSTER1_CORE_COUNT (0) +#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT +#define CPU_GET_AFFINITY(cpuId, clusterId) ((cpuId) << MPIDR_AFF1_SHIFT) + +/********************************** CACHE ECC ****************************************/ +#ifndef __ASSEMBLY__ +/** @addtogroup CACHE_ECC_Exported_Definition_Group1 + * @{ + */ +/** the fault value will be injected */ +typedef enum { + CACHE_ECC_INJECT_UC = 0x80000002, /**< Uncontainable Error generation */ + CACHE_ECC_INJECT_DE_UER = 0x8000000a, /**< for l1~l2, generate a exception */ +} eCACHE_ECC_InjectFault; +/** @} */ +#endif +/******************************************CRU*******************************************/ +#define PLL_INPUT_OSC_RATE (24 * 1000 * 1000) + +#define CRU_SRST_CON_CNT 29 +#define CRU_GATE_CON_CNT 35 +#define CRU_CLK_DIV_CON_CNT 84 +#define CRU_CLK_SEL_CON_CNT 84 + +#define CLK(mux, div) \ + (((mux) & 0x0F0F00FFU) | (((div) & 0xFFU) << 8) | (((div) & 0x0F0F0000U) << 4)) + +#ifndef __ASSEMBLY__ +typedef enum CLOCK_Name { + CLK_INVALID = 0U, + PLL_APLL, + PLL_CPLL, + PLL_GPLL, + PLL_NPLL, + PLL_VPLL, + PLL_PPLL, + PLL_HPLL, + CLK_WDT, + CLK_UART0, + CLK_I2C = CLK(CLK_I2C_SEL, 0U), + CLK_PWM1 = CLK(CLK_PWM1_SEL, 0U), + CLK_PWM2 = CLK(CLK_PWM2_SEL, 0U), + CLK_PWM3 = CLK(CLK_PWM3_SEL, 0U), + CLK_SPI0 = CLK(CLK_SPI0_SEL, 0U), + CLK_SPI1 = CLK(CLK_SPI1_SEL, 0U), + CLK_SPI2 = CLK(CLK_SPI2_SEL, 0U), + CLK_SPI3 = CLK(CLK_SPI3_SEL, 0U), + CLK_UART1_SRC = CLK(CLK_UART1_SRC_SEL, CLK_UART1_SRC_DIV), + CLK_UART1_FRAC = CLK(0U, CLK_UART1_FRAC_DIV), + CLK_UART1 = CLK(SCLK_UART1_SEL, 0U), + CLK_UART2_SRC = CLK(CLK_UART2_SRC_SEL, CLK_UART2_SRC_DIV), + CLK_UART2_FRAC = CLK(0U, CLK_UART2_FRAC_DIV), + CLK_UART2 = CLK(SCLK_UART2_SEL, 0U), + CLK_UART3_SRC = CLK(CLK_UART3_SRC_SEL, CLK_UART3_SRC_DIV), + CLK_UART3_FRAC = CLK(0U, CLK_UART3_FRAC_DIV), + CLK_UART3 = CLK(SCLK_UART3_SEL, 0U), + CLK_UART4_SRC = CLK(CLK_UART4_SRC_SEL, CLK_UART4_SRC_DIV), + CLK_UART4_FRAC = CLK(0U, CLK_UART4_FRAC_DIV), + CLK_UART4 = CLK(SCLK_UART4_SEL, 0U), + CLK_UART5_SRC = CLK(CLK_UART5_SRC_SEL, CLK_UART5_SRC_DIV), + CLK_UART5_FRAC = CLK(0U, CLK_UART5_FRAC_DIV), + CLK_UART5 = CLK(SCLK_UART5_SEL, 0U), + CLK_UART6_SRC = CLK(CLK_UART6_SRC_SEL, CLK_UART6_SRC_DIV), + CLK_UART6_FRAC = CLK(0U, CLK_UART6_FRAC_DIV), + CLK_UART6 = CLK(SCLK_UART6_SEL, 0U), + CLK_UART7_SRC = CLK(CLK_UART7_SRC_SEL, CLK_UART7_SRC_DIV), + CLK_UART7_FRAC = CLK(0U, CLK_UART7_FRAC_DIV), + CLK_UART7 = CLK(SCLK_UART7_SEL, 0U), + CLK_UART8_SRC = CLK(CLK_UART8_SRC_SEL, CLK_UART8_SRC_DIV), + CLK_UART8_FRAC = CLK(0U, CLK_UART8_FRAC_DIV), + CLK_UART8 = CLK(SCLK_UART8_SEL, 0U), + CLK_UART9_SRC = CLK(CLK_UART9_SRC_SEL, CLK_UART9_SRC_DIV), + CLK_UART9_FRAC = CLK(0U, CLK_UART9_FRAC_DIV), + CLK_UART9 = CLK(SCLK_UART9_SEL, 0U), + CLK_CAN0 = CLK(CLK_CAN0_SEL, CLK_CAN0_DIV), + CLK_CAN1 = CLK(CLK_CAN1_SEL, CLK_CAN1_DIV), + CLK_CAN2 = CLK(CLK_CAN2_SEL, CLK_CAN2_DIV), + CLK_TSADC_TSEN = CLK(CLK_TSADC_TSEN_SEL, CLK_TSADC_TSEN_DIV), + CLK_TSADC = CLK(0, CLK_TSADC_DIV), + SCLK_SFC = CLK(SCLK_SFC_SEL, 0U), + CLK_MAC0_2TOP = CLK(CLK_MAC0_2TOP_SEL, 0U), + CLK_MAC1_2TOP = CLK(CLK_MAC1_2TOP_SEL, 0U), + CLK_MAC0_OUT = CLK(CLK_MAC0_OUT_SEL, 0U), + CLK_MAC1_OUT = CLK(CLK_MAC1_OUT_SEL, 0U), + CLK_GMAC0_PTP_REF = CLK(CLK_GMAC0_PTP_REF_SEL, 0U), + CLK_GMAC1_PTP_REF = CLK(CLK_GMAC1_PTP_REF_SEL, 0U), + SCLK_GMAC0 = CLK(RMII0_EXTCLK_SEL, 0U), + SCLK_GMAC1 = CLK(RMII1_EXTCLK_SEL, 0U), + SCLK_GMAC0_RGMII_SPEED = CLK(RGMII0_CLK_SEL, 0U), + SCLK_GMAC1_RGMII_SPEED = CLK(RGMII1_CLK_SEL, 0U), + SCLK_GMAC0_RMII_SPEED = CLK(RMII0_CLK_SEL, 0U), + SCLK_GMAC1_RMII_SPEED = CLK(RMII1_CLK_SEL, 0U), + SCLK_GMAC0_RX_TX = CLK(CLK_GMAC0_RX_TX_SEL, 0U), + SCLK_GMAC1_RX_TX = CLK(CLK_GMAC1_RX_TX_SEL, 0U), + ACLK_PHP = CLK(ACLK_PHP_SEL, 0U), + HCLK_PHP = CLK(HCLK_PHP_SEL, 0U), + PCLK_PHP = CLK(0U, PCLK_PHP_DIV), + ACLK_USB = CLK(ACLK_USB_SEL, 0U), + HCLK_USB = CLK(HCLK_USB_SEL, 0U), + PCLK_USB = CLK(0U, PCLK_USB_DIV), + CLK_SDMMC0 = CLK(CLK_SDMMC0_SEL, 0U), +} eCLOCK_Name; +#endif +/****************************************MBOX********************************************/ +#define MBOX_CNT 2 +#define MBOX_CHAN_CNT 4 +/****************************************GRF*********************************************/ +#define GRF_IOMUX_BIT_PER_PIN (4) +#define GRF_DS_BIT_PER_PIN (8) +#define GRF_PULL_BIT_PER_PIN (2) +/****************************************GPIO********************************************/ +// #ifdef GPIO_VER_ID +// #undef GPIO_VER_ID +// #define GPIO_VER_ID (0x01000C2BU) +// #endif +/****************************************PMU*********************************************/ +#ifndef __ASSEMBLY__ +typedef enum PD_Id { + PD_INVALID = 0U, +} ePD_Id; +#endif +/****************************************FSPI********************************************/ +#define FSPI_CHIP_CNT (2) + +/****************************************WDT*********************************************/ +#define GLB_RST_SND_WDT GLB_RST_SND_WDT0 +#define GLB_RST_FST_WDT GLB_RST_FST_WDT0 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __SOC_H */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/system_rk3568.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/system_rk3568.h new file mode 100644 index 000000000..211b2f411 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/system_rk3568.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef __SYSTEM_RK3568_H_ +#define __SYSTEM_RK3568_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_RK3568_H_ */ From 93ad360a1a2da3dbb77ccf603e7ad84dbf11d4a3 Mon Sep 17 00:00:00 2001 From: xj Date: Sun, 25 Aug 2024 20:10:52 -0700 Subject: [PATCH 145/198] merge codes --- .../XiZi_AIoT/services/lib/usyscall/usyscall.c | 5 +++++ .../XiZi_AIoT/services/lib/usyscall/usyscall.h | 5 ++++- Ubiquitous/XiZi_AIoT/softkernel/include/syscall.h | 2 ++ Ubiquitous/XiZi_AIoT/softkernel/include/task.h | 8 ++++++++ Ubiquitous/XiZi_AIoT/softkernel/syscall/Makefile | 1 + .../XiZi_AIoT/softkernel/syscall/sys_state.c | 6 ++++++ Ubiquitous/XiZi_AIoT/softkernel/syscall/syscall.c | 3 +++ Ubiquitous/XiZi_AIoT/softkernel/task/task.c | 5 ++++- .../XiZi_AIoT/softkernel/trap/clock_irq_handler.c | 14 ++++++++++++++ 9 files changed, 47 insertions(+), 2 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.c b/Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.c index 8bdf03709..403d16e61 100644 --- a/Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.c +++ b/Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.c @@ -153,4 +153,9 @@ bool semaphore_wait(int sem_id) bool semaphore_signal(int sem_id) { return syscall(SYSCALL_SEMAPHORE, (intptr_t)SYS_SEM_SIGNAL, (intptr_t)sem_id, 0, 0); +} + +int sleep(intptr_t ms) +{ + return syscall(SYSCALL_SLEEP, (intptr_t)ms, 0, 0, 0); } \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.h b/Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.h index e76f684a1..de683f9cd 100644 --- a/Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.h +++ b/Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.h @@ -34,6 +34,7 @@ #define SYSCALL_KILL 12 // kill the task by id #define SYSCALL_SEMAPHORE 13 // semaphore related operations +#define SYSCALL_SLEEP 14 // sleep // clang-format on typedef enum { @@ -105,4 +106,6 @@ uintptr_t get_tick(); int semaphore_new(int val); bool semaphore_free(int sem_id); bool semaphore_wait(int sem_id); -bool semaphore_signal(int sem_id); \ No newline at end of file +bool semaphore_signal(int sem_id); + +int sleep(intptr_t ms); \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/softkernel/include/syscall.h b/Ubiquitous/XiZi_AIoT/softkernel/include/syscall.h index 14e2ddc7e..f2c0265d4 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/include/syscall.h +++ b/Ubiquitous/XiZi_AIoT/softkernel/include/syscall.h @@ -48,6 +48,7 @@ Modification: #define SYSCALL_KILL 12 // kill the task by id #define SYSCALL_SEMAPHORE 13 // semaphore related operations +#define SYSCALL_SLEEP 14 // sleep // clang-format on #ifndef __ASSEMBLER__ @@ -113,4 +114,5 @@ int sys_unbind_irq_all(struct Thread* task); int sys_unbind_irq(struct Thread* task, int irq_num); int sys_semaphore(sys_sem_option op, int sem_id); +int sys_sleep(intptr_t ms); #endif diff --git a/Ubiquitous/XiZi_AIoT/softkernel/include/task.h b/Ubiquitous/XiZi_AIoT/softkernel/include/task.h index accfb513a..096a0613e 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/include/task.h +++ b/Ubiquitous/XiZi_AIoT/softkernel/include/task.h @@ -44,6 +44,7 @@ Modification: #define TASK_MAX_PRIORITY 32 #define TASK_DEFAULT_PRIORITY 2 #define TASK_NAME_MAX_LEN 16 +#define SLEEP_MONITOR_CORE 0 enum ProcState { INIT = 0, @@ -51,6 +52,7 @@ enum ProcState { RUNNING, DEAD, BLOCKED, + SLEEPING, NEVER_RUN, }; @@ -72,6 +74,10 @@ struct ThreadContext { struct trapframe* trapframe; }; +struct TaskSleepContext { + int64_t remain_ms; +}; + /* Process Control Block */ struct Thread { /* task name */ @@ -97,6 +103,7 @@ struct Thread { /* task schedule attributes */ struct double_list_node node; + struct TaskSleepContext sleep_context; enum ProcState state; int priority; // priority int remain_tick; @@ -114,6 +121,7 @@ struct XiziTaskManager { struct double_list_node task_list_head[TASK_MAX_PRIORITY]; /* list of task control blocks that are allocated */ struct double_list_node task_running_list_head; struct double_list_node task_blocked_list_head; + struct double_list_node task_sleep_list_head; struct XiziSemaphorePool semaphore_pool; /* mem allocator */ diff --git a/Ubiquitous/XiZi_AIoT/softkernel/syscall/Makefile b/Ubiquitous/XiZi_AIoT/softkernel/syscall/Makefile index 4adbb947d..6a144502d 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/syscall/Makefile +++ b/Ubiquitous/XiZi_AIoT/softkernel/syscall/Makefile @@ -1,6 +1,7 @@ SRC_FILES := syscall.c \ sys_spawn.c \ sys_thread.c \ + sys_sleep.c \ sys_yield.c \ sys_register_as_server.c \ sys_connect_session.c \ diff --git a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_state.c b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_state.c index 67aea6b05..53406e3e2 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_state.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_state.c @@ -91,6 +91,12 @@ void show_tasks(void) SHOWTASK_TASK_BASE_INFO(task); } + DOUBLE_LIST_FOR_EACH_ENTRY(task, &xizi_task_manager.task_sleep_list_head, node) + { + LOG_PRINTF("%-8s", "SLEEP"); + SHOWTASK_TASK_BASE_INFO(task); + } + struct ksemaphore* sem = NULL; DOUBLE_LIST_FOR_EACH_ENTRY(sem, &xizi_task_manager.semaphore_pool.sem_list_guard, sem_list_node) { diff --git a/Ubiquitous/XiZi_AIoT/softkernel/syscall/syscall.c b/Ubiquitous/XiZi_AIoT/softkernel/syscall/syscall.c index d3ae51f67..c6985c194 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/syscall/syscall.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/syscall/syscall.c @@ -80,6 +80,9 @@ int syscall(int sys_num, uintptr_t param1, uintptr_t param2, uintptr_t param3, u case SYSCALL_SEMAPHORE: ret = sys_semaphore((sys_sem_option)param1, (int)param2); break; + case SYSCALL_SLEEP: + ret = sys_sleep((intptr_t)param1); + break; default: ERROR("Unsurport syscall(%d) right now\n", sys_num); ret = -1; diff --git a/Ubiquitous/XiZi_AIoT/softkernel/task/task.c b/Ubiquitous/XiZi_AIoT/softkernel/task/task.c index 27df0e16e..9b9a90ede 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/task/task.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/task/task.c @@ -38,6 +38,7 @@ Modification: #include "scheduler.h" #include "syscall.h" #include "task.h" +#include "trap_common.h" struct CPU global_cpus[NR_CPU]; uint32_t ready_task_priority; @@ -70,6 +71,7 @@ static void _task_manager_init() } doubleListNodeInit(&xizi_task_manager.task_blocked_list_head); doubleListNodeInit(&xizi_task_manager.task_running_list_head); + doubleListNodeInit(&xizi_task_manager.task_sleep_list_head); // init task (slab) allocator slab_init(&xizi_task_manager.memspace_allocator, sizeof(struct MemSpace)); slab_init(&xizi_task_manager.task_allocator, sizeof(struct Thread)); @@ -286,6 +288,7 @@ extern void context_switch(struct context**, struct context*); static void _scheduler(struct SchedulerRightGroup right_group) { struct MmuCommonDone* p_mmu_driver = AchieveResource(&right_group.mmu_driver_tag); +// struct XiziTrapDriver* p_intr_driver = AchieveResource(&right_group.intr_driver_tag); struct Thread* next_task; struct CPU* cpu = cur_cpu(); @@ -347,7 +350,7 @@ static void _task_block(struct double_list_node* head, struct Thread* task) static void _task_unblock(struct Thread* task) { assert(task != NULL); - assert(task->state == BLOCKED); + assert(task->state == BLOCKED || task->state == SLEEPING); task_node_leave_list(task); task->state = READY; task_node_add_to_ready_list_back(task); diff --git a/Ubiquitous/XiZi_AIoT/softkernel/trap/clock_irq_handler.c b/Ubiquitous/XiZi_AIoT/softkernel/trap/clock_irq_handler.c index eba875e07..937e4b219 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/trap/clock_irq_handler.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/trap/clock_irq_handler.c @@ -69,6 +69,8 @@ int xizi_clock_handler(int irq, void* tf, void* arg) if (p_clock_driver->is_timer_expired()) { p_clock_driver->clear_clock_intr(); global_tick++; + + // handle current thread struct Thread* current_task = cur_cpu()->task; if (current_task) { current_task->remain_tick--; @@ -77,6 +79,18 @@ int xizi_clock_handler(int irq, void* tf, void* arg) xizi_task_manager.task_yield_noschedule(current_task, false); } } + + // todo: cpu 0 will handle sleeping thread + struct Thread* thread = NULL; + DOUBLE_LIST_FOR_EACH_ENTRY(thread, &xizi_task_manager.task_sleep_list_head, node) + { + assert(thread->state == SLEEPING); + thread->sleep_context.remain_ms--; + if (thread->sleep_context.remain_ms <= 0) { + xizi_task_manager.task_unblock(thread); + break; + } + } } return 0; } \ No newline at end of file From 8c2eb4598f011833f5afdf61fae007462a6a03ff Mon Sep 17 00:00:00 2001 From: xj Date: Sun, 25 Aug 2024 20:33:16 -0700 Subject: [PATCH 146/198] merge codes --- .../XiZi_AIoT/softkernel/syscall/sys_sleep.c | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_sleep.c diff --git a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_sleep.c b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_sleep.c new file mode 100644 index 000000000..bce382597 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_sleep.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file sys_sleep.c + * @brief task sleep + * @version 3.0 + * @author AIIT XUOS Lab + * @date 2023.08.25 + */ + +/************************************************* +File name: sys_sleep.c +Description: +Others: +History: +1. Date: 2023-08-28 +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#include "multicores.h" +#include "syscall.h" +#include "task.h" + +#include "assert.h" + +int sys_sleep(intptr_t ms) +{ + struct Thread* cur_task = cur_cpu()->task; + xizi_task_manager.task_yield_noschedule(cur_task, false); + xizi_task_manager.task_block(&xizi_task_manager.task_sleep_list_head, cur_task); + cur_task->state = SLEEPING; + cur_task->sleep_context.remain_ms = ms; + + return 0; +} \ No newline at end of file From eadaa44dd8f801b44232732eaa43694949d0bec1 Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 26 Aug 2024 00:10:38 -0700 Subject: [PATCH 147/198] modify sleep function --- .../XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c index ab3ae16f0..f261b6ee5 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c @@ -335,7 +335,7 @@ void usb_osal_leave_critical_section(size_t flag){ void usb_osal_msleep(uint32_t delay){ if(delay > 0){ - + sleep(delay); } } From 24b1b5ac56eaea0a9ac186c94bcaf87a6cab574a Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 27 Aug 2024 18:58:40 +0800 Subject: [PATCH 148/198] Add usb_check_phymode --- .../drivers/usb/usb_service/usb_host.c | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c index 14b2f8a76..e0b7cd6b9 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c @@ -77,6 +77,34 @@ void ipc_rndis_init(void){ } } +static void usb_check_phymode(int id) +{ +#define PIPE_PHY_GRF0 0xFDC70000 +#define PIPE_PHY_GRF1 0xFDC80000 +#define PIPE_PHY_GRF_PIPE_CON0 0x00 +#define PIPE_PHY_GRF_VIRADDR_BASE 0x0000002100000000ULL + void *base = (void *)PIPE_PHY_GRF0; + void *base_vir = (void *)PIPE_PHY_GRF_VIRADDR_BASE; + uint32_t pipe_phymode; + + if (USB3_0_ID == id) { + base = (void *)PIPE_PHY_GRF0; + } + if (USB3_1_ID == id) { + base = (void *)PIPE_PHY_GRF1; + } + + if(!mmap((uintptr_t)base_vir, (uintptr_t)base, 0xFF, true)){ + USB_LOG_ERR("usb_check_phy mmap fail\n"); + } + + pipe_phymode = readl ( base_vir + PIPE_PHY_GRF_PIPE_CON0 ); + USB_LOG_DBG("usbh_initialize PIPE_PHY_GRF_PIPE_CON0=%08X\n", pipe_phymode); + if ( (pipe_phymode & 0x000C) != 0x0004) { + USB_LOG_ERR("usbh_initialize PIPE_PHY_GRF_PIPE_CON0=%08X is not USB3 mode\n", pipe_phymode); + } +} + static void usb_init(int id) { if (0 == usbh_initialize(id, &usb[id])){ @@ -100,6 +128,8 @@ int main(int argc, char* argv[]) } } printf("main usb3 id=%d init.\r\n", id); + + usb_check_phymode(id); usb_init(id); ipc_rndis_init(); From e7a92d9417bf648d44643031ec4f41202331b5ef Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 27 Aug 2024 04:33:02 -0700 Subject: [PATCH 149/198] Modify osal functions --- .../drivers/usb/components/osal/usb_osal.c | 42 ++++++++++++++++++- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c index f261b6ee5..d2fed989a 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/osal/usb_osal.c @@ -93,6 +93,8 @@ usb_osal_mutex_t usb_osal_mutex_create(void){ mutex_id = semaphore_new(1); + printf("In %s, mutex_id = %d\n", __func__, mutex_id); + return (usb_osal_mutex_t)mutex_id; } @@ -129,6 +131,7 @@ int usb_osal_mutex_give(usb_osal_mutex_t mutex){ semaphore_signal(mutex_id); + return 0; } @@ -181,6 +184,8 @@ osal_msg_queue_t osal_mq_create(const char *name, mq->msg_size = msg_size; mq->max_msgs = max_msgs; + printf("In %s, msg_size = %d, max_msgs = %d\n", __func__, msg_size, max_msgs); + return mq; } @@ -227,8 +232,10 @@ int osal_mq_send(osal_msg_queue_t mq, tail = mq->tail; header = mq->header; + + printf("In %s, tail = %d, header = %d\n", __func__, tail, header); /* message queue is full. */ - tail_nxt = (tail + 1) > mq->max_msgs ? (tail + 1 -mq->max_msgs):(tail + 1); + tail_nxt = (tail + 1) > mq->max_msgs ? (tail + 1 - mq->max_msgs):(tail + 1); if(tail_nxt == header){ usb_osal_sem_give(mq->mutex); return 0; @@ -246,7 +253,7 @@ int osal_mq_send(osal_msg_queue_t mq, -int osal_mq_recv(osal_msg_queue_t mq, +int __osal_mq_recv(osal_msg_queue_t mq, void *msg, size_t msg_len, uint32_t timeout){ @@ -277,6 +284,8 @@ int osal_mq_recv(osal_msg_queue_t mq, return 0; } + printf("In %s, tail = %d, header = %d\n", __func__, tail, header); + msg_header = (osal_mq_msg_header_t)(mq->data + (sizeof(struct osal_mq_msg_header) + mq->msg_size) * header); msg_buf = (uint8_t *)(msg_header + 1); copy_len = (msg_header->len > msg_len ? msg_len : msg_header->len); @@ -290,6 +299,35 @@ int osal_mq_recv(osal_msg_queue_t mq, return copy_len; } +int osal_mq_recv(osal_msg_queue_t mq, + void *msg, + size_t msg_len, + uint32_t timeout){ + int ret = 0; + int sleep_time = timeout; + int for_ever = 0; + + if(sleep_time == 0) + for_ever = 1; + + do{ + ret = __osal_mq_recv(mq, msg, msg_len, timeout); + + if(ret == 0){ + if(sleep_time > 0 || for_ever == 1){ + usb_osal_msleep(10); + + if(for_ever == 0) + sleep_time -= 10; + }else{ + break; + } + } + + }while(ret == 0); + + return ret; +} usb_osal_mq_t usb_osal_mq_create(uint32_t max_msgs){ From 08e1fba9321dea663f65bdb91ac71eff8ea9b087 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 30 Aug 2024 10:00:46 +0800 Subject: [PATCH 150/198] Modify the xHCI register size --- .../services/drivers/usb/components/port/xhci/usb_hc_xhci.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h index 15a0a2ec1..8b38fdee8 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h @@ -59,7 +59,7 @@ extern "C" { #define USB3_1_ID 1 #define USB3_0_BASE_ADDR 0xFCC00000 #define USB3_1_BASE_ADDR 0xFD000000 -#define USB3_ADDR_OFFSET_UPPER_BOUND 0x07FFF +#define USB3_ADDR_OFFSET_UPPER_BOUND 0x08000 #define USB3_VIRADDR_BASE 0x0000002000000000ULL #define USB3_0_VIRADDR_BASE USB3_VIRADDR_BASE From 137247d9184bae4b7067c0e19745ac5406ac2c1d Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 30 Aug 2024 10:10:54 +0800 Subject: [PATCH 151/198] Obtain the interrupt number according to the usb id --- .../usb/components/port/xhci/usb_hc_xhci.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index 999c290d9..537472983 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -1080,8 +1080,19 @@ IPC_SERVER_INTERFACE(Ipc_xhci_intr, 1); IPC_SERVER_REGISTER_INTERFACES(IpcXhciIntrHandler, 1, Ipc_xhci_intr); int bind_xhci_intr(void *para){ + int irq_no = USB3_0_INTERRUPT_NO; + struct xhci_host *xhci = (struct xhci_host *)para; - if (register_irq(USB3_0_INTERRUPT_NO, Ipc_xhci_intr) < 0) { + USB_LOG_DBG("bind_xhci_intr xhci pointer=%08x\n", xhci); + if (USB3_0_ID == xhci->bus->id) { + irq_no = USB3_0_INTERRUPT_NO; + } + if (USB3_1_ID == xhci->bus->id) { + irq_no = USB3_1_INTERRUPT_NO; + } + USB_LOG_DBG("bind_xhci_intr irq_no=%d\n", irq_no); + + if (register_irq(irq_no, Ipc_xhci_intr) < 0) { printf("bind failed!\n"); exit(1); } @@ -1108,7 +1119,7 @@ int create_xhci_intr_service(void *para){ return -1; } - + USB_LOG_DBG("create_xhci_intr_service xhci pointer=%08x\n", xhci); tid = thread(bind_xhci_intr, "xhci_intr_procedure", para); /* Create thread error! */ From ab8ba67a839fef2e7c31be0faf531323ba63496e Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 30 Aug 2024 10:20:35 +0800 Subject: [PATCH 152/198] Fixed a bug in using usb_osal_mq_recv --- .../services/drivers/usb/components/class/hub/usbh_hub.c | 6 ++++-- .../XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c | 4 ++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c index b98c3b7f9..c948ac3db 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c @@ -689,11 +689,12 @@ static void usbh_hub_thread(void *argument) int ret = 0; struct usbh_bus *usb = (struct usbh_bus *)argument; + USB_LOG_DBG("usbh_hub_thread usb pointer=%08x\r\n", usb); usb_hc_init(usb->id); while (1) { USB_LOG_DBG("wait event of mq@%p \r\n", usb->hub_mq); - ret = usb_osal_mq_recv(usb->hub_mq, (void *)&hub, 0xffffffff); - if (ret < 0) { + ret = usb_osal_mq_recv(usb->hub_mq, (void *)&hub, 0x7fffffff); + if (ret <= 0) { continue; } USB_LOG_DBG("handle event of hub@%p \r\n", hub); @@ -763,6 +764,7 @@ int usbh_hub_initialize(struct usbh_bus *usb) return -1; } + USB_LOG_DBG("usbh_hub_initialize usb pointer=%08x\r\n", usb); char thread_name[12]; snprintf(thread_name, 12, "usb%d_hub", usb->id); usb->hub_thread = usb_osal_thread_create(thread_name, CONFIG_USBHOST_PSC_STACKSIZE, CONFIG_USBHOST_PSC_PRIO, usbh_hub_thread, usb); diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c index e0b7cd6b9..9939dcb78 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c @@ -99,9 +99,9 @@ static void usb_check_phymode(int id) } pipe_phymode = readl ( base_vir + PIPE_PHY_GRF_PIPE_CON0 ); - USB_LOG_DBG("usbh_initialize PIPE_PHY_GRF_PIPE_CON0=%08X\n", pipe_phymode); + USB_LOG_DBG("usb_check_phy PIPE_PHY_GRF_PIPE_CON0=%08X\n", pipe_phymode); if ( (pipe_phymode & 0x000C) != 0x0004) { - USB_LOG_ERR("usbh_initialize PIPE_PHY_GRF_PIPE_CON0=%08X is not USB3 mode\n", pipe_phymode); + USB_LOG_ERR("usb_check_phy PIPE_PHY_GRF_PIPE_CON0=%08X is not USB3 mode\n", pipe_phymode); } } From c9838c216160d8a102d49dfcdec08ecb988e266d Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 3 Sep 2024 16:26:48 +0800 Subject: [PATCH 153/198] Modify usb_check_phymode --- .../services/drivers/usb/usb_service/usb_host.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c index 9939dcb78..d4e28569d 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c @@ -82,10 +82,12 @@ static void usb_check_phymode(int id) #define PIPE_PHY_GRF0 0xFDC70000 #define PIPE_PHY_GRF1 0xFDC80000 #define PIPE_PHY_GRF_PIPE_CON0 0x00 +#define PIPE_PHY_GRF_PIPE_CON3 0x0C #define PIPE_PHY_GRF_VIRADDR_BASE 0x0000002100000000ULL void *base = (void *)PIPE_PHY_GRF0; void *base_vir = (void *)PIPE_PHY_GRF_VIRADDR_BASE; - uint32_t pipe_phymode; + uint32_t con0; + uint32_t con3; if (USB3_0_ID == id) { base = (void *)PIPE_PHY_GRF0; @@ -98,10 +100,11 @@ static void usb_check_phymode(int id) USB_LOG_ERR("usb_check_phy mmap fail\n"); } - pipe_phymode = readl ( base_vir + PIPE_PHY_GRF_PIPE_CON0 ); - USB_LOG_DBG("usb_check_phy PIPE_PHY_GRF_PIPE_CON0=%08X\n", pipe_phymode); - if ( (pipe_phymode & 0x000C) != 0x0004) { - USB_LOG_ERR("usb_check_phy PIPE_PHY_GRF_PIPE_CON0=%08X is not USB3 mode\n", pipe_phymode); + con0 = readl ( base_vir + PIPE_PHY_GRF_PIPE_CON0 ); + con3 = readl ( base_vir + PIPE_PHY_GRF_PIPE_CON3 ); + USB_LOG_DBG("usb_check_phy PIPE_PHY_GRF_PIPE_CON0=%08X PIPE_PHY_GRF_PIPE_CON3=%08X\n", con0, con3); + if ( !( (con0 & 0x000C) == 0x0004 && (con3 & 0x8000) == 0) ) { + USB_LOG_ERR("usb_check_phy PIPE_PHY_GRF_PIPE_CON0=%08X and CON3=%08X is not USB3 mode\n", con0, con3); } } From abee37bf3163d5f3c0daf0567163768c919cd2ee Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 3 Sep 2024 16:34:01 +0800 Subject: [PATCH 154/198] Not executing ipc_rndis_init to debug xhci --- .../XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c index d4e28569d..ada6da8bb 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/usb_host.c @@ -134,9 +134,9 @@ int main(int argc, char* argv[]) usb_check_phymode(id); usb_init(id); - +#if 0 //debug ipc_rndis_init(); - +#endif while (1){ usb_osal_msleep(1000); } From 35b70a666c83bc272d7d8b4f773e621e155bdede Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 3 Sep 2024 16:57:49 +0800 Subject: [PATCH 155/198] Debug: Replace the args of usb_osal_thread_create with global parameter --- .../drivers/usb/components/class/hub/usbh_hub.c | 8 +++++++- .../usb/components/port/xhci/usb_hc_xhci.c | 16 ++++++++++++---- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c index c948ac3db..b3edd9419 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c @@ -43,6 +43,7 @@ extern int usbh_enumerate(struct usbh_hubport *hport); static void usbh_hub_thread_wakeup(struct usbh_hub *hub); static const char *speed_table[] = { "error-speed", "low-speed", "full-speed", "high-speed", "wireless-speed", "super-speed", "superplus-speed" }; +struct usbh_bus *g_usb_debug; struct usbh_hubport *usbh_get_roothub_port (struct usbh_bus *bus, unsigned int address) { @@ -689,6 +690,8 @@ static void usbh_hub_thread(void *argument) int ret = 0; struct usbh_bus *usb = (struct usbh_bus *)argument; + USB_LOG_DBG("usbh_hub_thread usb pointer=%08x\r\n", usb); + usb = g_usb_debug; USB_LOG_DBG("usbh_hub_thread usb pointer=%08x\r\n", usb); usb_hc_init(usb->id); while (1) { @@ -763,7 +766,7 @@ int usbh_hub_initialize(struct usbh_bus *usb) if (usb->hub_mq == NULL) { return -1; } - + g_usb_debug = usb; USB_LOG_DBG("usbh_hub_initialize usb pointer=%08x\r\n", usb); char thread_name[12]; snprintf(thread_name, 12, "usb%d_hub", usb->id); @@ -771,6 +774,9 @@ int usbh_hub_initialize(struct usbh_bus *usb) if (usb->hub_thread == NULL) { return -1; } +#if 1 + usb_osal_msleep(10); //Avoid log character confusion after usb_osal_thread_create +#endif return 0; } diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c index 537472983..53ecae633 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.c @@ -52,6 +52,7 @@ Modification: Modify USB Device Initialization in xHCI code to apply to XiZi AIO /************************** Constant Definitions *****************************/ /************************** Variable Definitions *****************************/ +struct xhci_host *g_xhci_debug; /***************** Macros (Inline Functions) Definitions *********************/ @@ -1068,8 +1069,10 @@ int IPC_DO_SERVE_FUNC(Ipc_xhci_intr)(void* ignore) { printf("TEST_SW_HDLR: In %s()\n", __func__); intptr_t id; + struct xhci_host *xhci = g_xhci_debug; - id = 0; + id = xhci->bus->id; + USB_LOG_DBG("Ipc_xhci_intr id=%d\n", id); XHCI_USBH_IRQHandler((void *)id); return 0; @@ -1083,6 +1086,8 @@ int bind_xhci_intr(void *para){ int irq_no = USB3_0_INTERRUPT_NO; struct xhci_host *xhci = (struct xhci_host *)para; + USB_LOG_DBG("bind_xhci_intr xhci pointer=%08x\n", xhci); + xhci = g_xhci_debug; USB_LOG_DBG("bind_xhci_intr xhci pointer=%08x\n", xhci); if (USB3_0_ID == xhci->bus->id) { irq_no = USB3_0_INTERRUPT_NO; @@ -1111,7 +1116,7 @@ int bind_xhci_intr(void *para){ int create_xhci_intr_service(void *para){ struct xhci_host *xhci; int tid; - + char *task_param[] = { para, NULL }; xhci = (struct xhci_host *)para; @@ -1119,8 +1124,9 @@ int create_xhci_intr_service(void *para){ return -1; } + g_xhci_debug = xhci; USB_LOG_DBG("create_xhci_intr_service xhci pointer=%08x\n", xhci); - tid = thread(bind_xhci_intr, "xhci_intr_procedure", para); + tid = thread(bind_xhci_intr, "xhci_intr_procedure", task_param); /* Create thread error! */ if(tid < 0){ @@ -1130,7 +1136,9 @@ int create_xhci_intr_service(void *para){ }else{ /* Child thread. do nothing except for the interrupt processing function. */ } - +#if 1 + usb_osal_msleep(10); //Avoid log character confusion after usb_osal_thread_create +#endif return 0; } From df1a8fac3a14aea1399e21013aaad9954267751c Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 3 Sep 2024 17:20:16 +0800 Subject: [PATCH 156/198] Add function xhci_dump --- .../drivers/usb/components/port/xhci/xhci.c | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 00116df51..3ac56007c 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -666,6 +666,8 @@ int xhci_probe ( struct xhci_host *xhci, unsigned long baseaddr ) { port->protocol = xhci_port_protocol ( xhci, i ); } + xhci_dump(xhci); + return error; err_reset: @@ -2977,6 +2979,56 @@ void xhci_event_process(struct xhci_host *xhci) { } +/* Dump host controller registers */ +void xhci_dump(struct xhci_host *xhci){ + unsigned int offset; + unsigned int i; + unsigned int interrupter; + + for ( offset = 0 ; offset < 0x20 ; offset += 0x10 ) { + printf("%08lx: %08lx: ", xhci->cap_addr + offset, xhci->cap + offset ); + for ( i = 0 ; i < 0x10 ; i += 0x04 ) { + printf("%08x ", readl ( xhci->cap_addr + offset + i) ); + } + printf("\n"); + } + printf("\n"); + + for ( offset = 0 ; offset < 0x3c ; offset += 0x10 ) { + printf("%08lx: %08lx: ", xhci->op_addr + offset, xhci->op + offset ); + for ( i = 0 ; i < 0x10 ; i += 0x04 ) { + printf("%08x ", readl ( xhci->op_addr + offset + i) ); + } + printf("\n"); + } + for ( offset = XHCI_OP_PORTSC ( 1 ) ; offset <= XHCI_OP_PORTSC ( xhci->ports ) ; offset += 0x10 ) { + printf("%08lx: %08lx: ", xhci->op_addr + offset, xhci->op + offset ); + for ( i = 0 ; i < 0x10 ; i += 0x04 ) { + printf("%08x ", readl ( xhci->op_addr + offset + i) ); + } + printf("\n"); + } + printf("\n"); + + printf("%08lx: %08lx: ", xhci->run_addr, xhci->run); + printf("%08x ", readl ( xhci->run_addr) ); + printf("\n"); + interrupter = 1; + for ( offset = 0x20 ; offset < 0x20 + (32 * interrupter) ; offset += 0x10 ) { + printf("%08lx: %08lx: ", xhci->run_addr + offset, xhci->run + offset ); + for ( i = 0 ; i < 0x10 ; i += 0x04 ) { + printf("%08x ", readl ( xhci->run_addr + offset + i) ); + } + printf("\n"); + } + printf("\n"); + + printf("%08lx: %08lx: ", xhci->db_addr, xhci->db); + printf("%08x ", readl ( xhci->db_addr) ); + printf("\n"); + printf("\n"); +} + /* Dump Port status */ void xhci_dump_port_status(uint32_t port, uint32_t portsc) { } From 636d4bf8c8f8c9bcd53c0099a3d266292b2fc538 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 3 Sep 2024 17:42:44 +0800 Subject: [PATCH 157/198] Add function handshake to wait for the HCHalted Status bit to be 0 --- .../drivers/usb/components/port/xhci/xhci.c | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 3ac56007c..536e90929 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -1068,6 +1068,36 @@ static int xhci_event_alloc ( struct xhci_host *xhci ) { return rc; } +/** + * Waits for as per specified amount of time + * for the "result" to match with "done" + * + * @param ptr pointer to the register to be read + * @param mask mask for the value read + * @param done value to be campared with result + * @param msec time to wait till + * @return 0 if handshake is success else < 0 on failure + */ +static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int msec) +{ + uint32_t result; + + do { + result = readl(ptr); + if (result == ~(uint32_t)0) + return -ENODEV; + result &= mask; + if (result == done) { + USB_LOG_DBG("XHCI handshake success ptr=%p result=%08x\n", ptr, result ); + return 0; + } + msec--; + usb_osal_msleep(1); + } while (msec > 0); + USB_LOG_DBG("XHCI handshake timeout ptr=%p result=%08x\n", ptr, result ); + return -ETIMEDOUT; +} + /** * Start xHCI device * @@ -1077,6 +1107,8 @@ static void xhci_run ( struct xhci_host *xhci ) { uint32_t config; uint32_t usbcmd; uint32_t runtime; + int halt_msec; + int ret; /* Configure number of device slots */ // config = readl ( xhci->op + XHCI_OP_CONFIG ); @@ -1102,6 +1134,15 @@ static void xhci_run ( struct xhci_host *xhci ) { // writel ( usbcmd, xhci->op + XHCI_OP_USBCMD ); writel ( usbcmd, xhci->op_addr + XHCI_OP_USBCMD ); + /* + * Wait for the HCHalted Status bit to be 0 to indicate the host is + * running. + */ + halt_msec = 16; + ret = handshake(xhci->op_addr + XHCI_OP_USBSTS, XHCI_USBSTS_HCH, 0, halt_msec); + if (ret) + USB_LOG_WRN("Host took too long to start, waited %u microseconds.\n", halt_msec); + USB_LOG_DBG("XHCI %s start running\n", xhci->name ); } From 86e600ba5e3bfcc934b3bf402eb6906a91229831 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Wed, 4 Sep 2024 17:27:28 +0800 Subject: [PATCH 158/198] Add xhci_dump_port_status_debug --- .../drivers/usb/components/class/hub/usbh_hub.c | 4 +++- .../drivers/usb/components/port/xhci/xhci.c | 17 +++++++++++++++-- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c index b3edd9419..fb14a72ea 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/class/hub/usbh_hub.c @@ -23,6 +23,7 @@ Modification: rndis uses naive_mmap to assign virtual and physical addresses and #include "usb_def.h" #include "usyscall.h" +extern void xhci_dump_port_status_debug(int id); //Debugging function #define DEV_FORMAT "/usb%d/hub%d" @@ -696,8 +697,9 @@ static void usbh_hub_thread(void *argument) usb_hc_init(usb->id); while (1) { USB_LOG_DBG("wait event of mq@%p \r\n", usb->hub_mq); - ret = usb_osal_mq_recv(usb->hub_mq, (void *)&hub, 0x7fffffff); + ret = usb_osal_mq_recv(usb->hub_mq, (void *)&hub, 10000); if (ret <= 0) { + xhci_dump_port_status_debug(usb->id); continue; } USB_LOG_DBG("handle event of hub@%p \r\n", hub); diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 536e90929..45f5a9145 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -666,8 +666,6 @@ int xhci_probe ( struct xhci_host *xhci, unsigned long baseaddr ) { port->protocol = xhci_port_protocol ( xhci, i ); } - xhci_dump(xhci); - return error; err_reset: @@ -1271,6 +1269,8 @@ int xhci_open ( struct xhci_host *xhci ) { /* Start controller */ xhci_run ( xhci ); + xhci_dump(xhci); + return 0; xhci_stop ( xhci ); @@ -3072,6 +3072,19 @@ void xhci_dump(struct xhci_host *xhci){ /* Dump Port status */ void xhci_dump_port_status(uint32_t port, uint32_t portsc) { + USB_LOG_DBG("XHCI port %d portsc %08x\n", port, portsc ); +} +//Debugging function +void xhci_dump_port_status_debug(int id) { + uint32_t portsc; + struct usbh_bus *bus = usbh_get_bus_of_index(id); + struct xhci_host *xhci = (struct xhci_host *)bus->priv; + + USB_LOG_DBG("xhci_status_debug xhci->op_addr + port1 = %08lx\n", xhci->op_addr + XHCI_OP_PORTSC ( 1 )); + portsc = readl ( xhci->op_addr + XHCI_OP_PORTSC ( 1 ) ); + USB_LOG_DBG("xhci_status_debug port=1 portsc=%08x\n", portsc); + portsc = readl ( xhci->op_addr + XHCI_OP_PORTSC ( 2 ) ); + USB_LOG_DBG("xhci_status_debug port=2 portsc=%08x\n", portsc); } /* Dump input context */ From 6fd90067a0576dcc84ac2a600b397c99747665d5 Mon Sep 17 00:00:00 2001 From: xj Date: Sun, 8 Sep 2024 20:00:37 -0700 Subject: [PATCH 159/198] Adding files for RK3568 USB --- .../services/drivers/usb/components/dev/Makefile | 4 ++++ .../drivers/usb/components/dev/rk3568/Makefile | 11 +++++++++++ .../drivers/usb/components/dev/rk3568/rk3568_usb.c | 10 ++++++++++ .../drivers/usb/components/dev/rk3568/rk3568_usb.h | 6 ++++++ .../XiZi_AIoT/services/drivers/usb/components/usb.mk | 2 ++ 5 files changed, 33 insertions(+) create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.c create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.h diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/Makefile new file mode 100644 index 000000000..c778bcc85 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/Makefile @@ -0,0 +1,4 @@ +SRC_DIR := rk3568 + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/Makefile new file mode 100644 index 000000000..12cd004c6 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/Makefile @@ -0,0 +1,11 @@ +include $(KERNEL_ROOT)/services/drivers/usb/components/usb.mk + +objs += rk3568_usb.o + +all: ${objs} + @echo "generate $^" + @mv $^ $(KERNEL_ROOT)/services/drivers/usb/components + +%.o: %.c + @echo "cc $^" + @${cc} ${cflags} ${c_useropts} ${INC_DIR} -o $@ -c $^ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.c new file mode 100644 index 000000000..1a6761c42 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.c @@ -0,0 +1,10 @@ +#include "rk3568_usb.h" + + +int enable_dwc3_rk3568(){ + return 0; +}; + +int disable_dwc3_rk3568(){ + return 0; +}; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.h new file mode 100644 index 000000000..52eddeff1 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.h @@ -0,0 +1,6 @@ +#ifndef RK3568_USB_H_ +#define RK3568_USB_H_ + +int enable_rk3568_usb = 0; + +#endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk index 21d6d5b7b..c11893355 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk @@ -42,6 +42,8 @@ INC_DIR = -I$(KERNEL_ROOT)/services/drivers/usb/ \ -I$(KERNEL_ROOT)/services/drivers/usb/components/osal \ -I$(KERNEL_ROOT)/services/drivers/usb/components/port \ -I$(KERNEL_ROOT)/services/drivers/usb/components/port/xhci \ + -I$(KERNEL_ROOT)/services/drivers/usb/components/dev \ + -I$(KERNEL_ROOT)/services/drivers/usb/components/dev/rk3568 \ -I$(KERNEL_ROOT)/services/drivers/usb/usb_service \ -I$(KERNEL_ROOT)/services//semaphore \ -I$(KERNEL_ROOT)/services/lib/ipc \ From c500ecfe1098377f9b3b622e171576b28dd31a58 Mon Sep 17 00:00:00 2001 From: xj Date: Sun, 8 Sep 2024 20:01:27 -0700 Subject: [PATCH 160/198] Adding files for RK3568 USB --- Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk index c11893355..331859e78 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk @@ -38,12 +38,12 @@ INC_DIR = -I$(KERNEL_ROOT)/services/drivers/usb/ \ -I$(KERNEL_ROOT)/services/drivers/usb/components/class/wireless \ -I$(KERNEL_ROOT)/services/drivers/usb/components/common \ -I$(KERNEL_ROOT)/services/drivers/usb/components/core \ + -I$(KERNEL_ROOT)/services/drivers/usb/components/dev \ + -I$(KERNEL_ROOT)/services/drivers/usb/components/dev/rk3568 \ -I$(KERNEL_ROOT)/services/drivers/usb/components/mem \ -I$(KERNEL_ROOT)/services/drivers/usb/components/osal \ -I$(KERNEL_ROOT)/services/drivers/usb/components/port \ -I$(KERNEL_ROOT)/services/drivers/usb/components/port/xhci \ - -I$(KERNEL_ROOT)/services/drivers/usb/components/dev \ - -I$(KERNEL_ROOT)/services/drivers/usb/components/dev/rk3568 \ -I$(KERNEL_ROOT)/services/drivers/usb/usb_service \ -I$(KERNEL_ROOT)/services//semaphore \ -I$(KERNEL_ROOT)/services/lib/ipc \ From c3ab8a0b24f7a77a3ab374c3a432797dacd88f3a Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 9 Sep 2024 01:33:53 -0700 Subject: [PATCH 161/198] add DWC3 codes --- .../usb/components/dev/rk3568/rk3568_usb.c | 7 ----- .../usb/components/dev/rk3568/rk3568_usb.h | 4 ++- .../drivers/usb/components/port/Makefile | 4 +-- .../drivers/usb/components/port/dwc3/Makefile | 11 ++++++++ .../drivers/usb/components/port/dwc3/dwc3.c | 1 + .../drivers/usb/components/port/dwc3/dwc3.h | 16 +++++++++++ .../drivers/usb/components/port/dwc3/gadget.h | 28 +++++++++++++++++++ .../services/drivers/usb/components/usb.mk | 1 + 8 files changed, 62 insertions(+), 10 deletions(-) create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/gadget.h diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.c index 1a6761c42..e2ec728b0 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.c @@ -1,10 +1,3 @@ #include "rk3568_usb.h" -int enable_dwc3_rk3568(){ - return 0; -}; - -int disable_dwc3_rk3568(){ - return 0; -}; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.h index 52eddeff1..0b6b443ad 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.h @@ -1,6 +1,8 @@ #ifndef RK3568_USB_H_ #define RK3568_USB_H_ -int enable_rk3568_usb = 0; +#include "dwc3.h" + + #endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/Makefile index f2783839d..f79b6fc78 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/Makefile @@ -1,4 +1,4 @@ -SRC_DIR := xhci +SRC_DIR := xhci dwc3 -include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/Makefile new file mode 100644 index 000000000..02ff013b2 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/Makefile @@ -0,0 +1,11 @@ +include $(KERNEL_ROOT)/services/drivers/usb/components/usb.mk + +objs += dwc3.o + +all: ${objs} + @echo "generate $^" + @mv $^ $(KERNEL_ROOT)/services/drivers/usb/components + +%.o: %.c + @echo "cc $^" + @${cc} ${cflags} ${c_useropts} ${INC_DIR} -o $@ -c $^ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c new file mode 100644 index 000000000..22e6d852f --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c @@ -0,0 +1 @@ +#include "dwc3.h" diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h new file mode 100644 index 000000000..893db2789 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h @@ -0,0 +1,16 @@ +#ifndef DWC3_H_ +#define DWC3_H_ + + +#include "usbh_core.h" +#include "usbh_hub.h" +#include "xhci_reg.h" +#include "xhci.h" +#include "gadget.h" + + + + + + +#endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/gadget.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/gadget.h new file mode 100644 index 000000000..f3100e07e --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/gadget.h @@ -0,0 +1,28 @@ +#ifndef GADGET_H_ +#define GADGET_H_ + +#include +#include +#include "usbh_core.h" + +struct usb_gadget { + int speed; + int max_speed; + int state; + uint8_t is_dualspeed:1; + uint8_t is_otg:1; + uint8_t is_a_peripheral:1; + uint8_t b_hnp_enable:1; + uint8_t a_hnp_support:1; + uint8_t a_alt_hnp_support:1; + uint8_t quirk_ep_out_aligned_size:1; + const char *name; + void *dev; +}; + + + + + + +#endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk index 331859e78..b6f00e2a2 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk @@ -43,6 +43,7 @@ INC_DIR = -I$(KERNEL_ROOT)/services/drivers/usb/ \ -I$(KERNEL_ROOT)/services/drivers/usb/components/mem \ -I$(KERNEL_ROOT)/services/drivers/usb/components/osal \ -I$(KERNEL_ROOT)/services/drivers/usb/components/port \ + -I$(KERNEL_ROOT)/services/drivers/usb/components/port/dwc3 \ -I$(KERNEL_ROOT)/services/drivers/usb/components/port/xhci \ -I$(KERNEL_ROOT)/services/drivers/usb/usb_service \ -I$(KERNEL_ROOT)/services//semaphore \ From 36bd41322501763f23ad9cab6da52a104a14e1ec Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 9 Sep 2024 01:34:15 -0700 Subject: [PATCH 162/198] add DWC3 codes --- Ubiquitous/XiZi_AIoT/services/drivers/usb/components/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/Makefile index 62e1a8580..1f8bdb2e2 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/Makefile @@ -11,7 +11,7 @@ # libipc = $(KERNEL_ROOT)/services/app/libipc.o # libsem = $(KERNEL_ROOT)/services/app/libsemaphore.o -SRC_DIR := class core mem osal port +SRC_DIR := class core mem osal port dev include $(KERNEL_ROOT)/compiler.mk From 33ac3e904804b0f1af38c63f9d397f94fc2ce9a1 Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 9 Sep 2024 03:02:06 -0700 Subject: [PATCH 163/198] add DWC3 codes --- .../drivers/usb/components/port/dwc3/gadget.h | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/gadget.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/gadget.h index f3100e07e..ae90b7a53 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/gadget.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/gadget.h @@ -4,6 +4,87 @@ #include #include #include "usbh_core.h" +#include "usb_list.h" + + +struct usb_ctrlrequest; +struct usb_ep; +struct usb_ep_caps; +struct usb_ep_ops; +struct usb_gadget; +struct usb_gadget_driver; +struct usb_ss_ep_comp_descriptor; + + + +struct usb_ctrlrequest { + uint8_t bRequestType; + uint8_t bRequest; + uint8_t wValue; +/* wIndex and wLength should be little end. */ + uint16_t wIndex; + uint16_t wLength; +} __attribute__ ((packed)); + + +struct usb_ep_caps { + uint8_t type_control:1; + uint8_t type_iso:1; + uint8_t type_bulk:1; + uint8_t type_int:1; + uint8_t dir_in:1; + uint8_t dir_out:1; +}; + +struct usb_ep { + void *driver_data; + const char *name; + const struct usb_ep_ops *ops; + usb_slist_t ep_list; + struct usb_ep_caps caps; + uint32_t maxpacket:16; + uint32_t maxpacket_limit:16; + uint32_t max_streams:16; + uint32_t maxburst:5; +/* usb_endpoint_descriptor is included in usb_def.h header files*/ + const struct usb_endpoint_descriptor *desc; + const struct usb_ss_ep_comp_descriptor *comp_desc; +}; + + + +struct usb_gadget_ops { + int (*get_frame)(struct usb_gadget *); + int (*wakeup)(struct usb_gadget *); + int (*set_selfpowered) (struct usb_gadget *, int is_selfpowered); + int (*vbus_draw) (struct usb_gadget *, unsigned mA); + int (*pullup) (struct usb_gadget *, int is_on); + int (*ioctl)(struct usb_gadget *, + unsigned code, unsigned long param); + int (*udc_start)(struct usb_gadget *, + struct usb_gadget_driver *); + int (*udc_stop)(struct usb_gadget *); + struct usb_ep *(*match_ep)(struct usb_gadget *, + struct usb_endpoint_descriptor *, + struct usb_ss_ep_comp_descriptor *); + void (*udc_set_speed)(struct usb_gadget *gadget, + int usb_device_speed); +}; + +struct usb_gadget_driver { + char *function; + int speed; + int (*bind)(struct usb_gadget *); + void (*unbind)(struct usb_gadget *); + int (*setup)(struct usb_gadget *, + const struct usb_ctrlrequest *); + void (*disconnect)(struct usb_gadget *); + void (*suspend)(struct usb_gadget *); + void (*resume)(struct usb_gadget *); + void (*reset)(struct usb_gadget *); +}; + + struct usb_gadget { int speed; From 6229f7b1c8a8be363fad325036a6104b76e75643 Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 9 Sep 2024 04:58:55 -0700 Subject: [PATCH 164/198] add DWC3 codes --- .../drivers/usb/components/port/dwc3/dwc3.h | 849 ++++++++++++++++++ .../drivers/usb/components/port/dwc3/gadget.h | 17 + 2 files changed, 866 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h index 893db2789..4782ad101 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h @@ -8,9 +8,858 @@ #include "xhci.h" #include "gadget.h" +#define DWC3_MSG_MAX 500 + +/* Global constants */ +#define DWC3_EP0_BOUNCE_SIZE 512 +#define DWC3_ENDPOINTS_NUM 32 +#define DWC3_XHCI_RESOURCES_NUM 2 + +#define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ +#define DWC3_EVENT_SIZE 4 /* bytes */ +#define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */ +#define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM) +#define DWC3_EVENT_TYPE_MASK 0xfe + +#define DWC3_EVENT_TYPE_DEV 0 +#define DWC3_EVENT_TYPE_CARKIT 3 +#define DWC3_EVENT_TYPE_I2C 4 + +#define DWC3_DEVICE_EVENT_DISCONNECT 0 +#define DWC3_DEVICE_EVENT_RESET 1 +#define DWC3_DEVICE_EVENT_CONNECT_DONE 2 +#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 +#define DWC3_DEVICE_EVENT_WAKEUP 4 +#define DWC3_DEVICE_EVENT_HIBER_REQ 5 +#define DWC3_DEVICE_EVENT_EOPF 6 +#define DWC3_DEVICE_EVENT_SOF 7 +#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 +#define DWC3_DEVICE_EVENT_CMD_CMPL 10 +#define DWC3_DEVICE_EVENT_OVERFLOW 11 + +#define DWC3_GEVNTCOUNT_MASK 0xfffc +#define DWC3_GSNPSID_MASK 0xffff0000 +#define DWC3_GSNPSREV_MASK 0xffff + +/* DWC3 registers memory space boundries */ +#define DWC3_XHCI_REGS_START 0x0 +#define DWC3_XHCI_REGS_END 0x7fff +#define DWC3_GLOBALS_REGS_START 0xc100 +#define DWC3_GLOBALS_REGS_END 0xc6ff +#define DWC3_DEVICE_REGS_START 0xc700 +#define DWC3_DEVICE_REGS_END 0xcbff +#define DWC3_OTG_REGS_START 0xcc00 +#define DWC3_OTG_REGS_END 0xccff + +/* Global Registers */ +#define DWC3_GSBUSCFG0 0xc100 +#define DWC3_GSBUSCFG1 0xc104 +#define DWC3_GTXTHRCFG 0xc108 +#define DWC3_GRXTHRCFG 0xc10c +#define DWC3_GCTL 0xc110 +#define DWC3_GEVTEN 0xc114 +#define DWC3_GSTS 0xc118 +#define DWC3_GUCTL1 0xc11c +#define DWC3_GSNPSID 0xc120 +#define DWC3_GGPIO 0xc124 +#define DWC3_GUID 0xc128 +#define DWC3_GUCTL 0xc12c +#define DWC3_GBUSERRADDR0 0xc130 +#define DWC3_GBUSERRADDR1 0xc134 +#define DWC3_GPRTBIMAP0 0xc138 +#define DWC3_GPRTBIMAP1 0xc13c +#define DWC3_GHWPARAMS0 0xc140 +#define DWC3_GHWPARAMS1 0xc144 +#define DWC3_GHWPARAMS2 0xc148 +#define DWC3_GHWPARAMS3 0xc14c +#define DWC3_GHWPARAMS4 0xc150 +#define DWC3_GHWPARAMS5 0xc154 +#define DWC3_GHWPARAMS6 0xc158 +#define DWC3_GHWPARAMS7 0xc15c +#define DWC3_GDBGFIFOSPACE 0xc160 +#define DWC3_GDBGLTSSM 0xc164 +#define DWC3_GPRTBIMAP_HS0 0xc180 +#define DWC3_GPRTBIMAP_HS1 0xc184 +#define DWC3_GPRTBIMAP_FS0 0xc188 +#define DWC3_GPRTBIMAP_FS1 0xc18c + +#define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) +#define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) + +#define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) + +#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) + +#define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) +#define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) + +#define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) +#define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) +#define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) +#define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) + +#define DWC3_GHWPARAMS8 0xc600 + +/* Device Registers */ +#define DWC3_DCFG 0xc700 +#define DWC3_DCTL 0xc704 +#define DWC3_DEVTEN 0xc708 +#define DWC3_DSTS 0xc70c +#define DWC3_DGCMDPAR 0xc710 +#define DWC3_DGCMD 0xc714 +#define DWC3_DALEPENA 0xc720 +#define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) +#define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) +#define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) +#define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) + +/* OTG Registers */ +#define DWC3_OCFG 0xcc00 +#define DWC3_OCTL 0xcc04 +#define DWC3_OEVT 0xcc08 +#define DWC3_OEVTEN 0xcc0C +#define DWC3_OSTS 0xcc10 + +/* Bit fields */ + +/* Global Configuration Register */ +#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) +#define DWC3_GCTL_U2RSTECN (1 << 16) +#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) +#define DWC3_GCTL_CLK_BUS (0) +#define DWC3_GCTL_CLK_PIPE (1) +#define DWC3_GCTL_CLK_PIPEHALF (2) +#define DWC3_GCTL_CLK_MASK (3) + +#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) +#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) +#define DWC3_GCTL_PRTCAP_HOST 1 +#define DWC3_GCTL_PRTCAP_DEVICE 2 +#define DWC3_GCTL_PRTCAP_OTG 3 + +#define DWC3_GCTL_CORESOFTRESET (1 << 11) +#define DWC3_GCTL_SOFITPSYNC (1 << 10) +#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) +#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) +#define DWC3_GCTL_DISSCRAMBLE (1 << 3) +#define DWC3_GCTL_U2EXIT_LFPS (1 << 2) +#define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) +#define DWC3_GCTL_DSBLCLKGTNG (1 << 0) + +/* Global User Control 1 Register */ +#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26) + +/* Global USB2 PHY Configuration Register */ +#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) +#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30) +#define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) +#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) +#define DWC3_GUSB2PHYCFG_PHYIF_8BIT (0 << 3) +#define DWC3_GUSB2PHYCFG_PHYIF_16BIT (1 << 3) +#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3) +#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) +#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10) +#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) +#define USBTRDTIM_UTMI_8_BIT 9 +#define USBTRDTIM_UTMI_16_BIT 5 +#define UTMI_PHYIF_16_BIT 1 +#define UTMI_PHYIF_8_BIT 0 + +/* Global USB3 PIPE Control Register */ +#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) +#define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29) +#define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24) +#define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) +#define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) +#define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) +#define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18) +#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) +#define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9) +#define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8) +#define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) +#define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) + +/* Global TX Fifo Size Register */ +#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) +#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) + +/* Global Event Size Registers */ +#define DWC3_GEVNTSIZ_INTMASK (1 << 31) +#define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) + +/* Global HWPARAMS1 Register */ +#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) +#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 +#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 +#define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 +#define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) +#define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) + +/* Global HWPARAMS3 Register */ +#define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) +#define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 +#define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1 +#define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) +#define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 +#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 +#define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 +#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 +#define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) +#define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 +#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 + +/* Global HWPARAMS4 Register */ +#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) +#define DWC3_MAX_HIBER_SCRATCHBUFS 15 + +/* Global HWPARAMS6 Register */ +#define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) + +/* Device Configuration Register */ +#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) +#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) + +#define DWC3_DCFG_SPEED_MASK (7 << 0) +#define DWC3_DCFG_SUPERSPEED (4 << 0) +#define DWC3_DCFG_HIGHSPEED (0 << 0) +#define DWC3_DCFG_FULLSPEED2 (1 << 0) +#define DWC3_DCFG_LOWSPEED (2 << 0) +#define DWC3_DCFG_FULLSPEED1 (3 << 0) + +#define DWC3_DCFG_LPM_CAP (1 << 22) + +/* Device Control Register */ +#define DWC3_DCTL_RUN_STOP (1 << 31) +#define DWC3_DCTL_CSFTRST (1 << 30) +#define DWC3_DCTL_LSFTRST (1 << 29) + +#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) +#define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) + +#define DWC3_DCTL_APPL1RES (1 << 23) + +/* These apply for core versions 1.87a and earlier */ +#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) +#define DWC3_DCTL_TRGTULST(n) ((n) << 17) +#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) +#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) +#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) +#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) +#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) + +/* These apply for core versions 1.94a and later */ +#define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf) +#define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20) + +#define DWC3_DCTL_KEEP_CONNECT (1 << 19) +#define DWC3_DCTL_L1_HIBER_EN (1 << 18) +#define DWC3_DCTL_CRS (1 << 17) +#define DWC3_DCTL_CSS (1 << 16) + +#define DWC3_DCTL_INITU2ENA (1 << 12) +#define DWC3_DCTL_ACCEPTU2ENA (1 << 11) +#define DWC3_DCTL_INITU1ENA (1 << 10) +#define DWC3_DCTL_ACCEPTU1ENA (1 << 9) +#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) + +#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) +#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) + +#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) +#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) +#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) +#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) +#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) +#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) +#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) + +/* Device Event Enable Register */ +#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) +#define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) +#define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) +#define DWC3_DEVTEN_ERRTICERREN (1 << 9) +#define DWC3_DEVTEN_SOFEN (1 << 7) +#define DWC3_DEVTEN_EOPFEN (1 << 6) +#define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) +#define DWC3_DEVTEN_WKUPEVTEN (1 << 4) +#define DWC3_DEVTEN_ULSTCNGEN (1 << 3) +#define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) +#define DWC3_DEVTEN_USBRSTEN (1 << 1) +#define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) + +/* Device Status Register */ +#define DWC3_DSTS_DCNRD (1 << 29) + +/* This applies for core versions 1.87a and earlier */ +#define DWC3_DSTS_PWRUPREQ (1 << 24) + +/* These apply for core versions 1.94a and later */ +#define DWC3_DSTS_RSS (1 << 25) +#define DWC3_DSTS_SSS (1 << 24) + +#define DWC3_DSTS_COREIDLE (1 << 23) +#define DWC3_DSTS_DEVCTRLHLT (1 << 22) + +#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) +#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) + +#define DWC3_DSTS_RXFIFOEMPTY (1 << 17) + +#define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) +#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) + +#define DWC3_DSTS_CONNECTSPD (7 << 0) + +#define DWC3_DSTS_SUPERSPEED (4 << 0) +#define DWC3_DSTS_HIGHSPEED (0 << 0) +#define DWC3_DSTS_FULLSPEED2 (1 << 0) +#define DWC3_DSTS_LOWSPEED (2 << 0) +#define DWC3_DSTS_FULLSPEED1 (3 << 0) + +/* Device Generic Command Register */ +#define DWC3_DGCMD_SET_LMP 0x01 +#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 +#define DWC3_DGCMD_XMIT_FUNCTION 0x03 + +/* These apply for core versions 1.94a and later */ +#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 +#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 + +#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 +#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a +#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c +#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 + +#define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1) +#define DWC3_DGCMD_CMDACT (1 << 10) +#define DWC3_DGCMD_CMDIOC (1 << 8) + +/* Device Generic Command Parameter Register */ +#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) +#define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) +#define DWC3_DGCMDPAR_RX_FIFO (0 << 5) +#define DWC3_DGCMDPAR_TX_FIFO (1 << 5) +#define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) +#define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) + +/* Device Endpoint Command Register */ +#define DWC3_DEPCMD_PARAM_SHIFT 16 +#define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) +#define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) +#define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1) +#define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) +#define DWC3_DEPCMD_CMDACT (1 << 10) +#define DWC3_DEPCMD_CMDIOC (1 << 8) + +#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) +#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) +#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) +#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) +#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) +#define DWC3_DEPCMD_SETSTALL (0x04 << 0) +/* This applies for core versions 1.90a and earlier */ +#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) +/* This applies for core versions 1.94a and later */ +#define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) +#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) +#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) + +/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ +#define DWC3_DALEPENA_EP(n) (1 << n) + +#define DWC3_DEPCMD_TYPE_CONTROL 0 +#define DWC3_DEPCMD_TYPE_ISOC 1 +#define DWC3_DEPCMD_TYPE_BULK 2 +#define DWC3_DEPCMD_TYPE_INTR 3 + +struct dwc3_trb; +struct dwc3; + + +/** + * struct dwc3_event_buffer - Software event buffer representation + * @buf: _THE_ buffer + * @length: size of this buffer + * @lpos: event offset + * @count: cache of last read event count register + * @flags: flags related to this event buffer + * @dma: dma_addr_t + * @dwc: pointer to DWC controller + */ +struct dwc3_event_buffer { + void *buf; + uint16_t length; + unsigned int lpos; + unsigned int count; + unsigned int flags; + +#define DWC3_EVENT_PENDING (1UL << 0) + uintptr_t dma; + struct dwc3 *dwc; +}; + +#define DWC3_EP_FLAG_STALLED (1 << 0) +#define DWC3_EP_FLAG_WEDGED (1 << 1) + +#define DWC3_EP_DIRECTION_TX true +#define DWC3_EP_DIRECTION_RX false + +#define DWC3_TRB_NUM 32 +#define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) + +struct dwc3_ep { + struct usb_ep endpoint; + usb_slist_t request_list; + usb_slist_t req_queued; + + struct dwc3_trb *trb_pool; + uintptr_t trb_pool_dma; + uint32_t free_slot; + uint32_t busy_slot; + const struct usb_ss_ep_comp_descriptor *comp_desc; + struct dwc3 *dwc; + + uint32_t saved_state; + unsigned flags; +#define DWC3_EP_ENABLED (1 << 0) +#define DWC3_EP_STALL (1 << 1) +#define DWC3_EP_WEDGE (1 << 2) +#define DWC3_EP_BUSY (1 << 4) +#define DWC3_EP_PENDING_REQUEST (1 << 5) +#define DWC3_EP_MISSED_ISOC (1 << 6) + + /* This last one is specific to EP0 */ +#define DWC3_EP0_DIR_IN (1 << 31) + + unsigned current_trb; + + uint8_t number; + uint8_t type; + uint8_t resource_index; + uint32_t interval; + + char name[20]; + + unsigned direction:1; + unsigned stream_capable:1; +}; + + +enum usb_dr_mode { + USB_DR_MODE_UNKNOWN, + USB_DR_MODE_HOST, + USB_DR_MODE_PERIPHERAL, + USB_DR_MODE_OTG, +}; + +enum dwc3_phy { + DWC3_PHY_UNKNOWN = 0, + DWC3_PHY_USB3, + DWC3_PHY_USB2, +}; + + +enum usb_phy_interface { + USBPHY_INTERFACE_MODE_UNKNOWN, + USBPHY_INTERFACE_MODE_UTMI, + USBPHY_INTERFACE_MODE_UTMIW, +}; + +enum dwc3_ep0_next { + DWC3_EP0_UNKNOWN = 0, + DWC3_EP0_COMPLETE, + DWC3_EP0_NRDY_DATA, + DWC3_EP0_NRDY_STATUS, +}; + +enum dwc3_ep0_state { + EP0_UNCONNECTED = 0, + EP0_SETUP_PHASE, + EP0_DATA_PHASE, + EP0_STATUS_PHASE, +}; + +enum dwc3_link_state { + /* In SuperSpeed */ + DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ + DWC3_LINK_STATE_U1 = 0x01, + DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ + DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ + DWC3_LINK_STATE_SS_DIS = 0x04, + DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ + DWC3_LINK_STATE_SS_INACT = 0x06, + DWC3_LINK_STATE_POLL = 0x07, + DWC3_LINK_STATE_RECOV = 0x08, + DWC3_LINK_STATE_HRESET = 0x09, + DWC3_LINK_STATE_CMPLY = 0x0a, + DWC3_LINK_STATE_LPBK = 0x0b, + DWC3_LINK_STATE_RESET = 0x0e, + DWC3_LINK_STATE_RESUME = 0x0f, + DWC3_LINK_STATE_MASK = 0x0f, +}; + + +/* TRB Length, PCM and Status */ +#define DWC3_TRB_SIZE_MASK (0x00ffffff) +#define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) +#define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) +#define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) + +#define DWC3_TRBSTS_OK 0 +#define DWC3_TRBSTS_MISSED_ISOC 1 +#define DWC3_TRBSTS_SETUP_PENDING 2 +#define DWC3_TRB_STS_XFER_IN_PROG 4 + +/* TRB Control */ +#define DWC3_TRB_CTRL_HWO (1 << 0) +#define DWC3_TRB_CTRL_LST (1 << 1) +#define DWC3_TRB_CTRL_CHN (1 << 2) +#define DWC3_TRB_CTRL_CSP (1 << 3) +#define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) +#define DWC3_TRB_CTRL_ISP_IMI (1 << 10) +#define DWC3_TRB_CTRL_IOC (1 << 11) +#define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) + +#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) +#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) +#define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) +#define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) +#define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) +#define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) +#define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) +#define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) + + +struct dwc3_trb { + uint32_t bpl; + uint32_t bph; + uint32_t size; + uint32_t ctrl; +} __packed; + + +/** + * dwc3_hwparams - copy of HWPARAMS registers + * @hwparams0 - GHWPARAMS0 + * @hwparams1 - GHWPARAMS1 + * @hwparams2 - GHWPARAMS2 + * @hwparams3 - GHWPARAMS3 + * @hwparams4 - GHWPARAMS4 + * @hwparams5 - GHWPARAMS5 + * @hwparams6 - GHWPARAMS6 + * @hwparams7 - GHWPARAMS7 + * @hwparams8 - GHWPARAMS8 + */ +struct dwc3_hwparams { + uint32_t hwparams0; + uint32_t hwparams1; + uint32_t hwparams2; + uint32_t hwparams3; + uint32_t hwparams4; + uint32_t hwparams5; + uint32_t hwparams6; + uint32_t hwparams7; + uint32_t hwparams8; +}; +/* HWPARAMS0 */ +#define DWC3_MODE(n) ((n) & 0x7) + +#define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) + +/* HWPARAMS1 */ +#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) + +/* HWPARAMS3 */ +#define DWC3_NUM_IN_EPS_MASK (0x1f << 18) +#define DWC3_NUM_EPS_MASK (0x3f << 12) +#define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ + (DWC3_NUM_EPS_MASK)) >> 12) +#define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ + (DWC3_NUM_IN_EPS_MASK)) >> 18) + +/* HWPARAMS7 */ +#define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) + +struct dwc3_request { + struct usb_request request; + usb_slist_t list; + struct dwc3_ep *dep; + uint32_t start_slot; + + uint8_t epnum; + struct dwc3_trb *trb; + uintptr_t trb_dma; + + unsigned direction:1; + unsigned mapped:1; + unsigned queued:1; +}; + + +/* + * struct dwc3_scratchpad_array - hibernation scratchpad array + * (format defined by hw) + */ +struct dwc3_scratchpad_array { +/* dma_addr should be little end. */ + uintptr_t dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; +}; + + +struct dwc3 { + struct usb_ctrlrequest *ctrl_req; + struct dwc3_trb *ep0_trb; + void *ep0_bounce; + void *scratchbuf; + uint8_t *setup_buf; + uintptr_t ctrl_req_addr; + uintptr_t ep0_trb_addr; + uintptr_t ep0_bounce_addr; + uintptr_t scratch_addr; + struct dwc3_request ep0_usb_req; + + /* device lock */ + usb_osal_mutex_t lock; + + struct dwc3_event_buffer **ev_buffs; + struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; + + struct usb_gadget gadget; + struct usb_gadget_driver *gadget_driver; + uintptr_t regs; + uint32_t regs_size; + enum dwc3_phy dr_mode; + enum usb_phy_interface hsphy_mode; +/* used for suspend/resume */ + uint32_t dcfg; + uint32_t gctl; + + uint32_t nr_scratch; + uint32_t num_event_buffers; + uint32_t u1u2; + uint32_t maximum_speed; + uint32_t revision; +#define DWC3_REVISION_173A 0x5533173a +#define DWC3_REVISION_175A 0x5533175a +#define DWC3_REVISION_180A 0x5533180a +#define DWC3_REVISION_183A 0x5533183a +#define DWC3_REVISION_185A 0x5533185a +#define DWC3_REVISION_187A 0x5533187a +#define DWC3_REVISION_188A 0x5533188a +#define DWC3_REVISION_190A 0x5533190a +#define DWC3_REVISION_194A 0x5533194a +#define DWC3_REVISION_200A 0x5533200a +#define DWC3_REVISION_202A 0x5533202a +#define DWC3_REVISION_210A 0x5533210a +#define DWC3_REVISION_220A 0x5533220a +#define DWC3_REVISION_230A 0x5533230a +#define DWC3_REVISION_240A 0x5533240a +#define DWC3_REVISION_250A 0x5533250a +#define DWC3_REVISION_260A 0x5533260a +#define DWC3_REVISION_270A 0x5533270a + + enum dwc3_ep0_next ep0_next_event; + enum dwc3_ep0_state ep0state; + enum dwc3_link_state link_state; + uint16_t isoch_delay; + uint16_t u2sel; + uint16_t u2pel; + uint8_t u1sel; + uint8_t u1pel; + + uint8_t speed; + + uint8_t num_out_eps; + uint8_t num_in_eps; + + void *mem; + struct dwc3_hwparams hwparams; + uint8_t test_mode; + uint8_t test_mode_nr; + uint8_t lpm_nyet_threshold; + uint8_t hird_threshold; + + uint32_t delayed_status:1; + uint32_t ep0_bounced:1; + uint32_t ep0_expect_in:1; + uint32_t has_hibernation:1; + uint32_t has_lpm_erratum:1; + uint32_t is_utmi_l1_suspend:1; + uint32_t is_selfpowered:1; + uint32_t is_fpga:1; + uint32_t needs_fifo_resize:1; + uint32_t pullups_connected:1; + uint32_t resize_fifos:1; + uint32_t setup_packet_pending:1; + uint32_t start_config_issued:1; + uint32_t three_stage_setup:1; + + uint32_t disable_scramble_quirk:1; + uint32_t u2exit_lfps_quirk:1; + uint32_t u2ss_inp3_quirk:1; + uint32_t req_p1p2p3_quirk:1; + uint32_t del_p1p2p3_quirk:1; + uint32_t del_phy_power_chg_quirk:1; + uint32_t lfps_filter_quirk:1; + uint32_t rx_detect_poll_quirk:1; + uint32_t dis_u3_susphy_quirk:1; + uint32_t dis_u2_susphy_quirk:1; + uint32_t dis_u1u2_quirk:1; + uint32_t dis_enblslpm_quirk:1; + uint32_t dis_u2_freeclk_exists_quirk:1; + + uint32_t tx_de_emphasis_quirk:1; + uint32_t tx_de_emphasis:2; + uint32_t usb2_phyif_utmi_width:5; + int index; + usb_slist_t list; +}; + +struct dwc3_event_type { + uint32_t is_devspec:1; + uint32_t type:7; + uint32_t reserved8_31:24; +} __packed; + +#define DWC3_DEPEVT_XFERCOMPLETE 0x01 +#define DWC3_DEPEVT_XFERINPROGRESS 0x02 +#define DWC3_DEPEVT_XFERNOTREADY 0x03 +#define DWC3_DEPEVT_RXTXFIFOEVT 0x04 +#define DWC3_DEPEVT_STREAMEVT 0x06 +#define DWC3_DEPEVT_EPCMDCMPLT 0x07 + +static inline const char *dwc3_ep_event_string(uint8_t event) +{ + switch (event) { + case DWC3_DEPEVT_XFERCOMPLETE: + return "Transfer Complete"; + case DWC3_DEPEVT_XFERINPROGRESS: + return "Transfer In-Progress"; + case DWC3_DEPEVT_XFERNOTREADY: + return "Transfer Not Ready"; + case DWC3_DEPEVT_RXTXFIFOEVT: + return "FIFO"; + case DWC3_DEPEVT_STREAMEVT: + return "Stream"; + case DWC3_DEPEVT_EPCMDCMPLT: + return "Endpoint Command Complete"; + } + + return "UNKNOWN"; +} + +struct dwc3_event_depevt { + uint32_t one_bit:1; + uint32_t endpoint_number:5; + uint32_t endpoint_event:4; + uint32_t reserved11_10:2; + uint32_t status:4; + +/* Within XferNotReady */ +#define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) + +/* Within XferComplete */ +#define DEPEVT_STATUS_BUSERR (1 << 0) +#define DEPEVT_STATUS_SHORT (1 << 1) +#define DEPEVT_STATUS_IOC (1 << 2) +#define DEPEVT_STATUS_LST (1 << 3) + +/* Stream event only */ +#define DEPEVT_STREAMEVT_FOUND 1 +#define DEPEVT_STREAMEVT_NOTFOUND 2 + +/* Control-only Status */ +#define DEPEVT_STATUS_CONTROL_DATA 1 +#define DEPEVT_STATUS_CONTROL_STATUS 2 + + uint32_t parameters:16; +} __packed; + + +/** + * struct dwc3_event_devt - Device Events + * @one_bit: indicates this is a non-endpoint event (not used) + * @device_event: indicates it's a device event. Should read as 0x00 + * @type: indicates the type of device event. + * 0 - DisconnEvt + * 1 - USBRst + * 2 - ConnectDone + * 3 - ULStChng + * 4 - WkUpEvt + * 5 - Reserved + * 6 - EOPF + * 7 - SOF + * 8 - Reserved + * 9 - ErrticErr + * 10 - CmdCmplt + * 11 - EvntOverflow + * 12 - VndrDevTstRcved + * @reserved15_12: Reserved, not used + * @event_info: Information about this event + * @reserved31_25: Reserved, not used + */ +struct dwc3_event_devt { + uint32_t one_bit:1; + uint32_t device_event:7; + uint32_t type:4; + uint32_t reserved15_12:4; + uint32_t event_info:9; + uint32_t reserved31_25:7; +} __packed; + +/** + * struct dwc3_event_gevt - Other Core Events + * @one_bit: indicates this is a non-endpoint event (not used) + * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. + * @phy_port_number: self-explanatory + * @reserved31_12: Reserved, not used. + */ +struct dwc3_event_gevt { + uint32_t one_bit:1; + uint32_t device_event:7; + uint32_t phy_port_number:4; + uint32_t reserved31_12:20; +} __packed; + +/** + * union dwc3_event - representation of Event Buffer contents + * @raw: raw 32-bit event + * @type: the type of the event + * @depevt: Device Endpoint Event + * @devt: Device Event + * @gevt: Global Event + */ +union dwc3_event { + uint32_t raw; + struct dwc3_event_type type; + struct dwc3_event_depevt depevt; + struct dwc3_event_devt devt; + struct dwc3_event_gevt gevt; +}; + +/** + * struct dwc3_gadget_ep_cmd_params - representation of endpoint command + * parameters + * @param2: third parameter + * @param1: second parameter + * @param0: first parameter + */ +struct dwc3_gadget_ep_cmd_params { + uint32_t param2; + uint32_t param1; + uint32_t param0; +}; + +/* + * DWC3 Features to be used as Driver Data + */ + +#define DWC3_HAS_PERIPHERAL BIT(0) +#define DWC3_HAS_XHCI BIT(1) +#define DWC3_HAS_OTG BIT(3) #endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/gadget.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/gadget.h index ae90b7a53..f28f191db 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/gadget.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/gadget.h @@ -102,7 +102,24 @@ struct usb_gadget { }; +struct usb_request { + void *buf; + unsigned length; + uintptr_t dma; + unsigned stream_id:16; + unsigned no_interrupt:1; + unsigned zero:1; + unsigned short_not_ok:1; + + void (*complete)(struct usb_ep *ep, + struct usb_request *req); + void *context; + usb_slist_t list; + + int status; + unsigned actual; +}; From f6ae7d7b1350e1d9ae30820903b865c419be003a Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 9 Sep 2024 23:18:33 -0700 Subject: [PATCH 165/198] Add dwc3 codes --- .../drivers/usb/components/dev/rk3568/rk3568_usb.c | 11 +++++++++++ .../drivers/usb/components/dev/rk3568/rk3568_usb.h | 3 ++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.c index e2ec728b0..1fd288525 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.c @@ -1,3 +1,14 @@ #include "rk3568_usb.h" +struct dwc3 dwc3_rk3568[CONFIG_USBHOST_XHCI_NUM]; + + +int dwc3_generic_host_probe(uint32_t id){ + return 0; +} + + +int dwc3_generic_probe(uint32_t id){ + return 0; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.h index 0b6b443ad..21abd4a09 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.h @@ -3,6 +3,7 @@ #include "dwc3.h" - +int dwc3_generic_host_probe(uint32_t id); +int dwc3_generic_probe(uint32_t id); #endif From 2d3b8d0b9510c98f2a1d91db31ec70d69e1b6c5c Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 9 Sep 2024 23:19:01 -0700 Subject: [PATCH 166/198] Add dwc3 codes --- .../XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c | 1 + .../XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h | 1 + 2 files changed, 2 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c index 22e6d852f..be9300194 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c @@ -1 +1,2 @@ #include "dwc3.h" +#include "usb_config.h" \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h index 4782ad101..2323e2363 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h @@ -862,4 +862,5 @@ struct dwc3_gadget_ep_cmd_params { #define DWC3_HAS_OTG BIT(3) + #endif From 636d643a4b68b791e893ad0e3939d73015ec4eb7 Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 9 Sep 2024 23:52:40 -0700 Subject: [PATCH 167/198] add DWC3 codes --- .../services/drivers/usb/components/Makefile | 2 +- .../XiZi_AIoT/services/drivers/usb/components/usb.mk | 1 + .../services/drivers/usb/components/usb_phy/Makefile | 11 +++++++++++ .../services/drivers/usb/components/usb_phy/usb_phy.c | 1 + .../services/drivers/usb/components/usb_phy/usb_phy.h | 8 ++++++++ 5 files changed, 22 insertions(+), 1 deletion(-) create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb_phy/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb_phy/usb_phy.c create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb_phy/usb_phy.h diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/Makefile index 1f8bdb2e2..c8727a088 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/Makefile @@ -11,7 +11,7 @@ # libipc = $(KERNEL_ROOT)/services/app/libipc.o # libsem = $(KERNEL_ROOT)/services/app/libsemaphore.o -SRC_DIR := class core mem osal port dev +SRC_DIR := class core mem osal port dev usb_phy include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk index b6f00e2a2..f2dc2c015 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb.mk @@ -45,6 +45,7 @@ INC_DIR = -I$(KERNEL_ROOT)/services/drivers/usb/ \ -I$(KERNEL_ROOT)/services/drivers/usb/components/port \ -I$(KERNEL_ROOT)/services/drivers/usb/components/port/dwc3 \ -I$(KERNEL_ROOT)/services/drivers/usb/components/port/xhci \ + -I$(KERNEL_ROOT)/services/drivers/usb/components/usb_phy \ -I$(KERNEL_ROOT)/services/drivers/usb/usb_service \ -I$(KERNEL_ROOT)/services//semaphore \ -I$(KERNEL_ROOT)/services/lib/ipc \ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb_phy/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb_phy/Makefile new file mode 100644 index 000000000..e4fcf450d --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb_phy/Makefile @@ -0,0 +1,11 @@ +include $(KERNEL_ROOT)/services/drivers/usb/components/usb.mk + +objs += usb_phy.o + +all: ${objs} + @echo "generate $^" + @mv $^ $(KERNEL_ROOT)/services/drivers/usb/components + +%.o: %.c + @echo "cc $^" + @${cc} ${cflags} ${c_useropts} ${INC_DIR} -o $@ -c $^ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb_phy/usb_phy.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb_phy/usb_phy.c new file mode 100644 index 000000000..d8cd8b904 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb_phy/usb_phy.c @@ -0,0 +1 @@ +#include "usb_phy.h" diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb_phy/usb_phy.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb_phy/usb_phy.h new file mode 100644 index 000000000..2d5be425a --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb_phy/usb_phy.h @@ -0,0 +1,8 @@ +#ifndef USB_PHY_H_ +#define USB_PHY_H_ + + + + + +#endif From 65fbdd5c1ed87aa7f88fe0fbc0317d6c178db5d1 Mon Sep 17 00:00:00 2001 From: xj Date: Mon, 9 Sep 2024 23:53:03 -0700 Subject: [PATCH 168/198] add DWC3 codes --- .../drivers/usb/components/port/dwc3/dwc3.c | 22 ++++++++++++++++++- .../drivers/usb/components/port/dwc3/dwc3.h | 7 ++++++ 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c index be9300194..d835f94e8 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c @@ -1,2 +1,22 @@ #include "dwc3.h" -#include "usb_config.h" \ No newline at end of file +#include "usb_config.h" + + +void dwc3_of_parse(struct dwc3 *dwc){ + +} + + + +int dwc3_host_init(struct dwc3 *dwc){ + return 0; +} + + + +enum usb_phy_interface usb_get_phy_mode(uint32_t id){ + return USBPHY_INTERFACE_MODE_UTMIW; +} + + + diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h index 2323e2363..faf4cf6bb 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h @@ -861,6 +861,13 @@ struct dwc3_gadget_ep_cmd_params { #define DWC3_HAS_XHCI BIT(1) #define DWC3_HAS_OTG BIT(3) +void dwc3_of_parse(struct dwc3 *dwc); + + +int dwc3_host_init(struct dwc3 *dwc); + +enum usb_phy_interface usb_get_phy_mode(uint32_t id); + #endif From 43cf354e3dafe6ff7090a8bba5deb97c453d1072 Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 10 Sep 2024 05:37:47 -0700 Subject: [PATCH 169/198] add DWC3 codes --- .../drivers/usb/components/port/dwc3/dwc3.c | 39 ++ .../drivers/usb/components/port/dwc3/dwc3.h | 17 +- .../drivers/usb/components/usb_phy/usb_phy.c | 11 + .../drivers/usb/components/usb_phy/usb_phy.h | 507 ++++++++++++++++++ 4 files changed, 571 insertions(+), 3 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c index d835f94e8..7d2b7e445 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c @@ -20,3 +20,42 @@ enum usb_phy_interface usb_get_phy_mode(uint32_t id){ +int dwc3_setup_phy(void *dev, struct phy **array, int *num_phys){ + return 0; +} + + + +void dwc3_cache_hwparams(struct dwc3 *dwc){ + +} + + + +int dwc3_core_init(struct dwc3 *dwc){ + return 0; +} + + + +int dwc3_event_buffers_setup(struct dwc3 *dwc){ + return 0; +} + + + +int dwc3_core_init_mode(struct dwc3 *dwc){ + return 0; +} + + + +void dwc3_set_mode(struct dwc3 *dwc, uint32_t mode){ + +} + + + +int dwc3_init(struct dwc3 *dwc){ + return 0; +} diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h index faf4cf6bb..23be126ca 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h @@ -7,6 +7,7 @@ #include "xhci_reg.h" #include "xhci.h" #include "gadget.h" +#include "usb_phy.h" #define DWC3_MSG_MAX 500 @@ -863,11 +864,21 @@ struct dwc3_gadget_ep_cmd_params { void dwc3_of_parse(struct dwc3 *dwc); - -int dwc3_host_init(struct dwc3 *dwc); - enum usb_phy_interface usb_get_phy_mode(uint32_t id); +int dwc3_setup_phy(void *dev, struct phy **array, int *num_phys); +int dwc3_init(struct dwc3 *dwc); +void dwc3_cache_hwparams(struct dwc3 *dwc); + +int dwc3_core_init(struct dwc3 *dwc); + +int dwc3_event_buffers_setup(struct dwc3 *dwc); + +int dwc3_core_init_mode(struct dwc3 *dwc); + +void dwc3_set_mode(struct dwc3 *dwc, uint32_t mode); + +int dwc3_host_init(struct dwc3 *dwc); #endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb_phy/usb_phy.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb_phy/usb_phy.c index d8cd8b904..28443186e 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb_phy/usb_phy.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb_phy/usb_phy.c @@ -1 +1,12 @@ #include "usb_phy.h" + + +int generic_phy_init(struct phy *phy){ + return 0; +} + + + +int generic_phy_power_on(struct phy *phy){ + return 0; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb_phy/usb_phy.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb_phy/usb_phy.h index 2d5be425a..af5776eef 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb_phy/usb_phy.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb_phy/usb_phy.h @@ -1,8 +1,515 @@ #ifndef USB_PHY_H_ #define USB_PHY_H_ +#include +#include + + +enum phy_mode { + PHY_MODE_INVALID, + PHY_MODE_DP, +}; + + +struct phy_attrs { + uint32_t bus_width; + uint32_t max_link_rate; + enum phy_mode mode; +}; + + +struct phy { + void *dev; + uint32_t id; + struct phy_attrs attrs; +}; +struct phy_configure_opts_mipi_dphy { + /** + * @clk_miss: + * + * Timeout, in picoseconds, for receiver to detect absence of + * Clock transitions and disable the Clock Lane HS-RX. + * + * Maximum value: 60000 ps + */ + unsigned int clk_miss; + + /** + * @clk_post: + * + * Time, in picoseconds, that the transmitter continues to + * send HS clock after the last associated Data Lane has + * transitioned to LP Mode. Interval is defined as the period + * from the end of @hs_trail to the beginning of @clk_trail. + * + * Minimum value: 60000 ps + 52 * @hs_clk_rate period in ps + */ + unsigned int clk_post; + + /** + * @clk_pre: + * + * Time, in UI, that the HS clock shall be driven by + * the transmitter prior to any associated Data Lane beginning + * the transition from LP to HS mode. + * + * Minimum value: 8 UI + */ + unsigned int clk_pre; + + /** + * @clk_prepare: + * + * Time, in picoseconds, that the transmitter drives the Clock + * Lane LP-00 Line state immediately before the HS-0 Line + * state starting the HS transmission. + * + * Minimum value: 38000 ps + * Maximum value: 95000 ps + */ + unsigned int clk_prepare; + + /** + * @clk_settle: + * + * Time interval, in picoseconds, during which the HS receiver + * should ignore any Clock Lane HS transitions, starting from + * the beginning of @clk_prepare. + * + * Minimum value: 95000 ps + * Maximum value: 300000 ps + */ + unsigned int clk_settle; + + /** + * @clk_term_en: + * + * Time, in picoseconds, for the Clock Lane receiver to enable + * the HS line termination. + * + * Maximum value: 38000 ps + */ + unsigned int clk_term_en; + + /** + * @clk_trail: + * + * Time, in picoseconds, that the transmitter drives the HS-0 + * state after the last payload clock bit of a HS transmission + * burst. + * + * Minimum value: 60000 ps + */ + unsigned int clk_trail; + + /** + * @clk_zero: + * + * Time, in picoseconds, that the transmitter drives the HS-0 + * state prior to starting the Clock. + */ + unsigned int clk_zero; + + /** + * @d_term_en: + * + * Time, in picoseconds, for the Data Lane receiver to enable + * the HS line termination. + * + * Maximum value: 35000 ps + 4 * @hs_clk_rate period in ps + */ + unsigned int d_term_en; + + /** + * @eot: + * + * Transmitted time interval, in picoseconds, from the start + * of @hs_trail or @clk_trail, to the start of the LP- 11 + * state following a HS burst. + * + * Maximum value: 105000 ps + 12 * @hs_clk_rate period in ps + */ + unsigned int eot; + + /** + * @hs_exit: + * + * Time, in picoseconds, that the transmitter drives LP-11 + * following a HS burst. + * + * Minimum value: 100000 ps + */ + unsigned int hs_exit; + + /** + * @hs_prepare: + * + * Time, in picoseconds, that the transmitter drives the Data + * Lane LP-00 Line state immediately before the HS-0 Line + * state starting the HS transmission. + * + * Minimum value: 40000 ps + 4 * @hs_clk_rate period in ps + * Maximum value: 85000 ps + 6 * @hs_clk_rate period in ps + */ + unsigned int hs_prepare; + + /** + * @hs_settle: + * + * Time interval, in picoseconds, during which the HS receiver + * shall ignore any Data Lane HS transitions, starting from + * the beginning of @hs_prepare. + * + * Minimum value: 85000 ps + 6 * @hs_clk_rate period in ps + * Maximum value: 145000 ps + 10 * @hs_clk_rate period in ps + */ + unsigned int hs_settle; + + /** + * @hs_skip: + * + * Time interval, in picoseconds, during which the HS-RX + * should ignore any transitions on the Data Lane, following a + * HS burst. The end point of the interval is defined as the + * beginning of the LP-11 state following the HS burst. + * + * Minimum value: 40000 ps + * Maximum value: 55000 ps + 4 * @hs_clk_rate period in ps + */ + unsigned int hs_skip; + + /** + * @hs_trail: + * + * Time, in picoseconds, that the transmitter drives the + * flipped differential state after last payload data bit of a + * HS transmission burst + * + * Minimum value: max(8 * @hs_clk_rate period in ps, + * 60000 ps + 4 * @hs_clk_rate period in ps) + */ + unsigned int hs_trail; + + /** + * @hs_zero: + * + * Time, in picoseconds, that the transmitter drives the HS-0 + * state prior to transmitting the Sync sequence. + */ + unsigned int hs_zero; + + /** + * @init: + * + * Time, in picoseconds for the initialization period to + * complete. + * + * Minimum value: 100000000 ps + */ + unsigned int init; + + /** + * @lpx: + * + * Transmitted length, in picoseconds, of any Low-Power state + * period. + * + * Minimum value: 50000 ps + */ + unsigned int lpx; + + /** + * @ta_get: + * + * Time, in picoseconds, that the new transmitter drives the + * Bridge state (LP-00) after accepting control during a Link + * Turnaround. + * + * Value: 5 * @lpx + */ + unsigned int ta_get; + + /** + * @ta_go: + * + * Time, in picoseconds, that the transmitter drives the + * Bridge state (LP-00) before releasing control during a Link + * Turnaround. + * + * Value: 4 * @lpx + */ + unsigned int ta_go; + + /** + * @ta_sure: + * + * Time, in picoseconds, that the new transmitter waits after + * the LP-10 state before transmitting the Bridge state + * (LP-00) during a Link Turnaround. + * + * Minimum value: @lpx + * Maximum value: 2 * @lpx + */ + unsigned int ta_sure; + + /** + * @wakeup: + * + * Time, in picoseconds, that a transmitter drives a Mark-1 + * state prior to a Stop state in order to initiate an exit + * from ULPS. + * + * Minimum value: 1000000000 ps + */ + unsigned int wakeup; + + /** + * @hs_clk_rate: + * + * Clock rate, in Hertz, of the high-speed clock. + */ + unsigned long hs_clk_rate; + + /** + * @lp_clk_rate: + * + * Clock rate, in Hertz, of the low-power clock. + */ + unsigned long lp_clk_rate; + + /** + * @lanes: + * + * Number of active data lanes used for the transmissions. + */ + unsigned char lanes; +}; + + +struct phy_configure_opts_dp { + /** + * @link_rate: + * + * Link Rate, in Mb/s, of the main link. + * + * Allowed values: 1620, 2160, 2430, 2700, 3240, 4320, 5400, 8100 Mb/s + */ + unsigned int link_rate; + + /** + * @lanes: + * + * Number of active, consecutive, data lanes, starting from + * lane 0, used for the transmissions on main link. + * + * Allowed values: 1, 2, 4 + */ + unsigned int lanes; + + /** + * @voltage: + * + * Voltage swing levels, as specified by DisplayPort specification, + * to be used by particular lanes. One value per lane. + * voltage[0] is for lane 0, voltage[1] is for lane 1, etc. + * + * Maximum value: 3 + */ + unsigned int voltage[4]; + + /** + * @pre: + * + * Pre-emphasis levels, as specified by DisplayPort specification, to be + * used by particular lanes. One value per lane. + * + * Maximum value: 3 + */ + unsigned int pre[4]; + + /** + * @ssc: + * + * Flag indicating, whether or not to enable spread-spectrum clocking. + * + */ + uint8_t ssc : 1; + + /** + * @set_rate: + * + * Flag indicating, whether or not reconfigure link rate and SSC to + * requested values. + * + */ + uint8_t set_rate : 1; + + /** + * @set_lanes: + * + * Flag indicating, whether or not reconfigure lane count to + * requested value. + * + */ + uint8_t set_lanes : 1; + + /** + * @set_voltages: + * + * Flag indicating, whether or not reconfigure voltage swing + * and pre-emphasis to requested values. Only lanes specified + * by "lanes" parameter will be affected. + * + */ + uint8_t set_voltages : 1; +}; + + +struct phy_configure_opts_pcie { + bool is_bifurcation; /* Bifurcation mode support */ +}; + + +/** + * union phy_configure_opts - Opaque generic phy configuration + * + * @mipi_dphy: Configuration set applicable for phys supporting + * the MIPI_DPHY phy mode. + * @dp: Configuration set applicable for phys supporting + * the DisplayPort protocol. + */ +union phy_configure_opts { + struct phy_configure_opts_mipi_dphy mipi_dphy; + struct phy_configure_opts_dp dp; + struct phy_configure_opts_pcie pcie; +}; + + +struct phy_ops { + /** + * of_xlate - Translate a client's device-tree (OF) phy specifier. + * + * The PHY core calls this function as the first step in implementing + * a client's generic_phy_get_by_*() call. + * + * If this function pointer is set to NULL, the PHY core will use a + * default implementation, which assumes #phy-cells = <0> or + * #phy-cells = <1>, and in the later case that the DT cell + * contains a simple integer PHY port ID. + * + * @phy: The phy struct to hold the translation result. + * @args: The phy specifier values from device tree. + * @return 0 if OK, or a negative error code. + */ +// int (*of_xlate)(struct phy *phy, struct ofnode_phandle_args *args); + + /** + * init - initialize the hardware. + * + * Hardware intialization should not be done in during probe() but + * should be implemented in this init() function. It could be starting + * PLL, taking a controller out of reset, routing, etc. This function + * is typically called only once per PHY port. + * If power_on() is not implemented, it must power up the phy. + * + * @phy: the PHY port to initialize + * @return 0 if OK, or a negative error code. + */ + int (*init)(struct phy *phy); + + /** + * exit - de-initialize the PHY device + * + * Hardware de-intialization should be done here. Every step done in + * init() should be undone here. + * This could be used to suspend the phy to reduce power consumption or + * to put the phy in a known condition before booting the OS (though it + * is NOT called automatically before booting the OS) + * If power_off() is not implemented, it must power down the phy. + * + * @phy: PHY port to be de-initialized + * @return 0 if OK, or a negative error code + */ + int (*exit)(struct phy *phy); + + /** + * reset - resets a PHY device without shutting down + * + * @phy: PHY port to be reset + * + * During runtime, the PHY may need to be reset in order to + * re-establish connection etc without being shut down or exit. + * + * @return 0 if OK, or a negative error code + */ + int (*reset)(struct phy *phy); + + /** + * @configure: + * + * Optional. + * + * Used to change the PHY parameters. phy_init() must have + * been called on the phy. + * + * Returns: 0 if successful, an negative error code otherwise + */ + int (*configure)(struct phy *phy, union phy_configure_opts *opts); + + /** + * @validate: + * + * Optional. + * + * Used to check that the current set of parameters can be + * handled by the phy. Implementations are free to tune the + * parameters passed as arguments if needed by some + * implementation detail or constraints. It must not change + * any actual configuration of the PHY, so calling it as many + * times as deemed fit by the consumer must have no side + * effect. + * + * Returns: 0 if the configuration can be applied, an negative + * error code otherwise + */ + int (*validate)(struct phy *phy, enum phy_mode mode, int submode, + union phy_configure_opts *opts); + + /** + * power_on - power on a PHY device + * + * @phy: PHY port to be powered on + * + * During runtime, the PHY may need to be powered on or off several + * times. This function is used to power on the PHY. It relies on the + * setup done in init(). If init() is not implemented, it must take care + * of setting up the context (PLLs, ...) + * + * @return 0 if OK, or a negative error code + */ + int (*power_on)(struct phy *phy); + + /** + * power_off - power off a PHY device + * + * @phy: PHY port to be powered off + * + * During runtime, the PHY may need to be powered on or off several + * times. This function is used to power off the PHY. Except if + * init()/deinit() are not implemented, it must not de-initialize + * everything. + * + * @return 0 if OK, or a negative error code + */ + int (*power_off)(struct phy *phy); + + int (*set_mode)(struct phy *phy, enum phy_mode mode, int submode); +}; + +int generic_phy_init(struct phy *phy); +int generic_phy_power_on(struct phy *phy); #endif From 0cd2ad608006f763f5694885d7d72238ac3930fc Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 10 Sep 2024 20:26:24 -0700 Subject: [PATCH 170/198] Add DWC3 codes --- .../services/drivers/usb/components/port/dwc3/dwc3.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h index 23be126ca..5702a0f6d 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h @@ -9,6 +9,11 @@ #include "gadget.h" #include "usb_phy.h" +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE + + + #define DWC3_MSG_MAX 500 /* Global constants */ @@ -632,7 +637,7 @@ struct dwc3 { struct usb_gadget_driver *gadget_driver; uintptr_t regs; uint32_t regs_size; - enum dwc3_phy dr_mode; + enum usb_dr_mode dr_mode; enum usb_phy_interface hsphy_mode; /* used for suspend/resume */ uint32_t dcfg; @@ -881,4 +886,7 @@ int dwc3_core_init_mode(struct dwc3 *dwc); void dwc3_set_mode(struct dwc3 *dwc, uint32_t mode); int dwc3_host_init(struct dwc3 *dwc); + + + #endif From 69288eb2551527fd06a12d02f8d0c4c03f1ae60e Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 10 Sep 2024 23:01:44 -0700 Subject: [PATCH 171/198] Add DWC3 codes --- .../services/drivers/usb/components/port/dwc3/dwc3.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h index 5702a0f6d..2ebd36609 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h @@ -635,7 +635,12 @@ struct dwc3 { struct usb_gadget gadget; struct usb_gadget_driver *gadget_driver; +/* + * The regs stores the value of the DWC3 start physical address + * Conversely, the regs_vir stores the mapped value of the regs, which can be used in the xHCI driver. + */ uintptr_t regs; + uintptr_t regs_vir; uint32_t regs_size; enum usb_dr_mode dr_mode; enum usb_phy_interface hsphy_mode; From 068e61694de8e0151e35d26d13ed36dd0ac032a1 Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 10 Sep 2024 23:29:36 -0700 Subject: [PATCH 172/198] Add DWC3 codes --- .../services/drivers/usb/components/port/dwc3/dwc3.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h index 2ebd36609..f6a11c4d4 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h @@ -892,6 +892,16 @@ void dwc3_set_mode(struct dwc3 *dwc, uint32_t mode); int dwc3_host_init(struct dwc3 *dwc); +static inline uint32_t dwc3_readl(void *base, uint32_t offset){ + uintptr_t offs = offset - DWC3_GLOBALS_REGS_START; + uint32_t value; + value = readl(base + offs); + return value; +} +static inline void dwc3_writel(void *base, uint32_t offset, uint32_t value){ + unsigned long offs = offset - DWC3_GLOBALS_REGS_START; + writel(value, base + offs); +} #endif From d2e410b69b448af93651d004d3a09d7a4c309723 Mon Sep 17 00:00:00 2001 From: xj Date: Tue, 10 Sep 2024 23:45:35 -0700 Subject: [PATCH 173/198] Add DWC3 codes --- .../drivers/usb/components/port/dwc3/dwc3.c | 13 ++++++++++++- .../drivers/usb/components/port/dwc3/dwc3.h | 4 ++-- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c index 7d2b7e445..9bc28841c 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c @@ -26,8 +26,19 @@ int dwc3_setup_phy(void *dev, struct phy **array, int *num_phys){ -void dwc3_cache_hwparams(struct dwc3 *dwc){ +void dwc3_cache_hwparams(struct dwc3 *dwc) +{ + struct dwc3_hwparams *parms = &dwc->hwparams; + parms->hwparams0 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS0); + parms->hwparams1 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS1); + parms->hwparams2 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS2); + parms->hwparams3 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS3); + parms->hwparams4 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS4); + parms->hwparams5 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS5); + parms->hwparams6 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS6); + parms->hwparams7 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS7); + parms->hwparams8 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS8); } diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h index f6a11c4d4..b0b0eca31 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h @@ -639,8 +639,8 @@ struct dwc3 { * The regs stores the value of the DWC3 start physical address * Conversely, the regs_vir stores the mapped value of the regs, which can be used in the xHCI driver. */ - uintptr_t regs; - uintptr_t regs_vir; + void *regs; + void *regs_vir; uint32_t regs_size; enum usb_dr_mode dr_mode; enum usb_phy_interface hsphy_mode; From 6d834be99185e34e7eff238559f49bdf3167eeba Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Wed, 11 Sep 2024 19:11:45 +0800 Subject: [PATCH 174/198] Add dwc3 host probe --- .../drivers/usb/components/core/usbh_core.c | 9 ++- .../usb/components/dev/rk3568/rk3568_usb.c | 61 +++++++++++++++++-- .../usb/components/dev/rk3568/rk3568_usb.h | 2 +- .../drivers/usb/components/port/dwc3/dwc3.c | 46 +++++++++++++- .../drivers/usb/components/port/dwc3/dwc3.h | 7 ++- .../services/drivers/usb/usb_service/Makefile | 6 +- 6 files changed, 120 insertions(+), 11 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c index 9e038cdff..60aac05f5 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/core/usbh_core.c @@ -33,6 +33,7 @@ Modification: usb core uses naive_mmap to assign virtual and physical addresses #include "usbh_core.h" #include "usbh_hub.h" #include "usb_hc_xhci.h" +#include "rk3568_usb.h" #include "usyscall.h" #include "usbh_rndis.h" @@ -1020,10 +1021,14 @@ int usb_hc_init(uint32_t id) struct usbh_bus* usb = usbh_get_bus_of_index(id); if (USB_HC_XHCI == usb->usb_hc_type) { - ret = xhci_usb_hc_init(usb->id); + ret = dwc3_generic_host_probe(id); + if (ret) { + return ret; + } + ret = xhci_usb_hc_init(id); } else { - USB_LOG_WRN("invalid usb controller type %d \r\n", usb->usb_hc_type); + USB_LOG_WRN("usb_hc_init invalid usb controller type %d \r\n", usb->usb_hc_type); return -EINVAL; } diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.c index 1fd288525..8fec80135 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.c @@ -1,14 +1,67 @@ +/************************************************* +File name: rk3568_usb.c +Description: the dwc3 host probe function adapted to xiuos. +Others: take RK3568 codes uboot\drivers\usb\dwc3\dwc3-generic.c +*************************************************/ #include "rk3568_usb.h" +#include "usb_hc_xhci.h" struct dwc3 dwc3_rk3568[CONFIG_USBHOST_XHCI_NUM]; -int dwc3_generic_host_probe(uint32_t id){ - return 0; +static uint32_t usb_get_maximum_speed(uint32_t id) +{ + return USB_SPEED_SUPER; +} + +static enum usb_dr_mode usb_get_dr_mode(uint32_t id) +{ + return USB_DR_MODE_HOST; } -int dwc3_generic_probe(uint32_t id){ - return 0; +int dwc3_generic_host_probe(uint32_t id) +{ + struct dwc3 *dwc3; + + USB_ASSERT(id < CONFIG_USBHOST_XHCI_NUM); + dwc3 = &(dwc3_rk3568[id]); + memset(dwc3, 0, sizeof(*dwc3)); + dwc3->id = id; + + return dwc3_generic_probe(dwc3); +} + + +int dwc3_generic_probe(struct dwc3 *dwc3) +{ + int rc; + uintptr_t base; + uintptr_t base_vir; + int len; + + dwc3->maximum_speed = usb_get_maximum_speed(dwc3->id); + dwc3->dr_mode = usb_get_dr_mode(dwc3->id); + + dwc3_of_parse(dwc3); + + base = usb_hc_get_register_base(dwc3->id); + base_vir = usb_hc_get_register_vir_base(dwc3->id); + + dwc3->regs = (void *)base + DWC3_GLOBALS_REGS_START; + dwc3->regs_vir = (void *)base_vir + DWC3_GLOBALS_REGS_START; + len = DWC3_OTG_REGS_END - DWC3_GLOBALS_REGS_START + 1; + + if(!mmap((uintptr_t)dwc3->regs_vir, (uintptr_t)dwc3->regs, len, true)){ + USB_LOG_ERR("%s mmap fail\r\n", __func__); + return -ENOMEM; + } + + rc = dwc3_init(dwc3); + if (rc) { + return rc; + } + + return 0; } \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.h index 21abd4a09..73398a283 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.h @@ -4,6 +4,6 @@ #include "dwc3.h" int dwc3_generic_host_probe(uint32_t id); -int dwc3_generic_probe(uint32_t id); +int dwc3_generic_probe(struct dwc3 *dwc3); #endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c index 9bc28841c..a1803b307 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c @@ -2,8 +2,52 @@ #include "usb_config.h" -void dwc3_of_parse(struct dwc3 *dwc){ +void dwc3_of_parse(struct dwc3 *dwc) +{ + uint8_t lpm_nyet_threshold; + uint8_t tx_de_emphasis; + uint8_t hird_threshold; + + /* default to highest possible threshold */ + lpm_nyet_threshold = 0xff; + + /* default to -3.5dB de-emphasis */ + tx_de_emphasis = 1; + + /* + * default to assert utmi_sleep_n and use maximum allowed HIRD + * threshold value of 0b1100 + */ + hird_threshold = 12; + + dwc->hsphy_mode = usb_get_phy_mode(dwc->id); + + /* xiuos: The parameters are updated according to the dts of RK3568 */ + dwc->has_lpm_erratum = 0; + lpm_nyet_threshold = lpm_nyet_threshold; + dwc->is_utmi_l1_suspend = 0; + hird_threshold = hird_threshold; + dwc->disable_scramble_quirk = 0; + dwc->u2exit_lfps_quirk = 0; + dwc->u2ss_inp3_quirk = 0; + dwc->req_p1p2p3_quirk = 0; + dwc->del_p1p2p3_quirk = 0; + dwc->del_phy_power_chg_quirk = 0; + dwc->lfps_filter_quirk = 0; + dwc->rx_detect_poll_quirk = 0; + dwc->dis_u3_susphy_quirk = 0; + dwc->dis_u2_susphy_quirk = 0; + dwc->dis_enblslpm_quirk = 1; + dwc->dis_u2_freeclk_exists_quirk = 1; + dwc->tx_de_emphasis_quirk = 0; + tx_de_emphasis = tx_de_emphasis; + + dwc->lpm_nyet_threshold = lpm_nyet_threshold; + dwc->tx_de_emphasis = tx_de_emphasis; + + dwc->hird_threshold = hird_threshold + | (dwc->is_utmi_l1_suspend << 4); } diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h index b0b0eca31..eb49d2edf 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h @@ -627,9 +627,12 @@ struct dwc3 { uintptr_t scratch_addr; struct dwc3_request ep0_usb_req; - /* device lock */ + /* The id is USB3_0 or USB3_1 */ + uint32_t id; + + /* device lock */ usb_osal_mutex_t lock; - + struct dwc3_event_buffer **ev_buffs; struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/Makefile index ca7596a97..fc1425831 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/usb_service/Makefile @@ -12,10 +12,14 @@ session = $(KERNEL_ROOT)/services/app/session.o libipc = $(KERNEL_ROOT)/services/app/libipc.o libsem = $(KERNEL_ROOT)/services/app/libsemaphore.o -usb_components = $(KERNEL_ROOT)/services/drivers/usb/components/rndis_host.o \ +usb_components = \ + $(KERNEL_ROOT)/services/drivers/usb/components/dwc3.o \ + $(KERNEL_ROOT)/services/drivers/usb/components/rk3568_usb.o \ + $(KERNEL_ROOT)/services/drivers/usb/components/rndis_host.o \ $(KERNEL_ROOT)/services/drivers/usb/components/usb_hc_xhci.o \ $(KERNEL_ROOT)/services/drivers/usb/components/usb_mem.o \ $(KERNEL_ROOT)/services/drivers/usb/components/usb_osal.o \ + $(KERNEL_ROOT)/services/drivers/usb/components/usb_phy.o \ $(KERNEL_ROOT)/services/drivers/usb/components/usbh_core.o \ $(KERNEL_ROOT)/services/drivers/usb/components/usbh_hub.o \ $(KERNEL_ROOT)/services/drivers/usb/components/usbh_rndis.o \ From 506f37d00932835fe4996d154ee89a808e93fc83 Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 12 Sep 2024 01:25:32 -0700 Subject: [PATCH 175/198] Add DWC3 codes --- .../services/drivers/usb/components/common/usb_util.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_util.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_util.h index 0c46dbcb8..67f1f9c4c 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_util.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/common/usb_util.h @@ -204,4 +204,7 @@ 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 +#define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) +#define lower_32_bits(n) ((uint32_t)(n)) + #endif From 0e9625cf87e352570e5d06840e8da51c299541a2 Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 12 Sep 2024 02:38:41 -0700 Subject: [PATCH 176/198] Add DWC3 codes --- .../drivers/usb/components/port/dwc3/dwc3.c | 23 +++++++++++++++++++ .../drivers/usb/components/port/dwc3/dwc3.h | 12 ++++++++++ 2 files changed, 35 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c index a1803b307..0619008df 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c @@ -92,6 +92,23 @@ int dwc3_core_init(struct dwc3 *dwc){ } +int dwc3_alloc_scratch_buffers(struct dwc3 *dwc){ + return 0; +} + + + +int dwc3_setup_scratch_buffers(struct dwc3 *dwc){ + return 0; +} + + + +int dwc3_event_buffers_alloc(struct dwc3 *dwc){ + return 0; +} + + int dwc3_event_buffers_setup(struct dwc3 *dwc){ return 0; @@ -114,3 +131,9 @@ void dwc3_set_mode(struct dwc3 *dwc, uint32_t mode){ int dwc3_init(struct dwc3 *dwc){ return 0; } + + + +int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, uint32_t param){ + return 0; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h index eb49d2edf..352cf2e5f 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h @@ -4,6 +4,7 @@ #include "usbh_core.h" #include "usbh_hub.h" +#include "usb_util.h" #include "xhci_reg.h" #include "xhci.h" #include "gadget.h" @@ -887,6 +888,14 @@ void dwc3_cache_hwparams(struct dwc3 *dwc); int dwc3_core_init(struct dwc3 *dwc); +int dwc3_alloc_scratch_buffers(struct dwc3 *dwc); + +int dwc3_setup_scratch_buffers(struct dwc3 *dwc); + +int dwc3_alloc_event_buffers(struct dwc3 *dwc, uint32_t length); + +int dwc3_event_buffers_alloc(struct dwc3 *dwc); + int dwc3_event_buffers_setup(struct dwc3 *dwc); int dwc3_core_init_mode(struct dwc3 *dwc); @@ -895,6 +904,9 @@ void dwc3_set_mode(struct dwc3 *dwc, uint32_t mode); int dwc3_host_init(struct dwc3 *dwc); +int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, uint32_t param); + + static inline uint32_t dwc3_readl(void *base, uint32_t offset){ uintptr_t offs = offset - DWC3_GLOBALS_REGS_START; uint32_t value; From 43a771c15c4225f5f5ed22e95132e3e1f430400f Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 12 Sep 2024 02:59:09 -0700 Subject: [PATCH 177/198] Add DWC3 codes --- .../XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c index 0619008df..5c73eaf26 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c @@ -1,6 +1,6 @@ #include "dwc3.h" #include "usb_config.h" - +#include "usyscall.h" void dwc3_of_parse(struct dwc3 *dwc) From b51c9112527fdf634fbd23afd77f780a5dac2deb Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Thu, 12 Sep 2024 18:50:59 +0800 Subject: [PATCH 178/198] Modify dwc3_generic_probe --- .../services/drivers/usb/components/dev/rk3568/rk3568_usb.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.c index 8fec80135..d42038e74 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/dev/rk3568/rk3568_usb.c @@ -25,6 +25,7 @@ int dwc3_generic_host_probe(uint32_t id) { struct dwc3 *dwc3; + USB_LOG_DBG("%s usb3.0 id=%d\r\n", __func__, id); USB_ASSERT(id < CONFIG_USBHOST_XHCI_NUM); dwc3 = &(dwc3_rk3568[id]); memset(dwc3, 0, sizeof(*dwc3)); @@ -46,6 +47,11 @@ int dwc3_generic_probe(struct dwc3 *dwc3) dwc3_of_parse(dwc3); + /* TODO: */ + rc = dwc3_setup_phy(NULL, NULL, NULL); + if (rc) + return rc; + base = usb_hc_get_register_base(dwc3->id); base_vir = usb_hc_get_register_vir_base(dwc3->id); From 637408e1928579d5f6b502958cc4c54b25f7e47f Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 12 Sep 2024 04:02:59 -0700 Subject: [PATCH 179/198] Add DWC3 codes --- .../drivers/usb/components/port/dwc3/dwc3.c | 33 +++++++++++++++++-- .../drivers/usb/components/port/dwc3/dwc3.h | 2 -- 2 files changed, 31 insertions(+), 4 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c index 5c73eaf26..ca9dafdf7 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c @@ -93,6 +93,16 @@ int dwc3_core_init(struct dwc3 *dwc){ int dwc3_alloc_scratch_buffers(struct dwc3 *dwc){ + uint32_t length; + + if (!dwc->has_hibernation) + return 0; + + if (!dwc->nr_scratch) + return 0; + + + return 0; } @@ -104,12 +114,11 @@ int dwc3_setup_scratch_buffers(struct dwc3 *dwc){ -int dwc3_event_buffers_alloc(struct dwc3 *dwc){ +int dwc3_alloc_event_buffers(struct dwc3 *dwc, uint32_t length){ return 0; } - int dwc3_event_buffers_setup(struct dwc3 *dwc){ return 0; } @@ -135,5 +144,25 @@ int dwc3_init(struct dwc3 *dwc){ int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, uint32_t param){ + uint32_t timeout = 500; + uint32_t reg; + + dwc3_writel(dwc->regs_vir, DWC3_DGCMDPAR, param); + dwc3_writel(dwc->regs_vir, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); + + do { + reg = dwc3_readl(dwc->regs_vir, DWC3_DGCMD); + + if(!(reg & DWC3_DGCMD_CMDACT)){ + return 0; + } + + timeout--; + usb_osal_msleep(1); + + if(!timeout) + return -1; + }while(1); + return 0; } \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h index 352cf2e5f..86dec1910 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h @@ -894,8 +894,6 @@ int dwc3_setup_scratch_buffers(struct dwc3 *dwc); int dwc3_alloc_event_buffers(struct dwc3 *dwc, uint32_t length); -int dwc3_event_buffers_alloc(struct dwc3 *dwc); - int dwc3_event_buffers_setup(struct dwc3 *dwc); int dwc3_core_init_mode(struct dwc3 *dwc); From a509d162ec2c08893547faf1f7c9d97820f5b7e2 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Thu, 12 Sep 2024 19:32:27 +0800 Subject: [PATCH 180/198] Add dwc3_init --- .../drivers/usb/components/port/dwc3/dwc3.c | 56 ++++++++++++++++++- .../drivers/usb/components/port/dwc3/dwc3.h | 7 +++ 2 files changed, 61 insertions(+), 2 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c index ca9dafdf7..73b49f7a7 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c @@ -92,6 +92,10 @@ int dwc3_core_init(struct dwc3 *dwc){ } +void dwc3_core_exit(struct dwc3 *dwc){ +} + + int dwc3_alloc_scratch_buffers(struct dwc3 *dwc){ uint32_t length; @@ -119,11 +123,20 @@ int dwc3_alloc_event_buffers(struct dwc3 *dwc, uint32_t length){ } +void dwc3_free_event_buffers(struct dwc3 *dwc){ +} + + + int dwc3_event_buffers_setup(struct dwc3 *dwc){ return 0; } +void dwc3_event_buffers_cleanup(struct dwc3 *dwc){ +} + + int dwc3_core_init_mode(struct dwc3 *dwc){ return 0; @@ -137,12 +150,51 @@ void dwc3_set_mode(struct dwc3 *dwc, uint32_t mode){ -int dwc3_init(struct dwc3 *dwc){ - return 0; +int dwc3_init(struct dwc3 *dwc) +{ + int ret; + + dwc3_cache_hwparams(dwc); + + ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); + if (ret) { + USB_LOG_ERR("failed to allocate event buffers\n"); + return -ENOMEM; + } + + ret = dwc3_core_init(dwc); + if (ret) { + USB_LOG_ERR("failed to initialize core\n"); + goto core_fail; + } + + ret = dwc3_event_buffers_setup(dwc); + if (ret) { + USB_LOG_ERR("failed to setup event buffers\n"); + goto event_fail; + } + + ret = dwc3_core_init_mode(dwc); + if (ret) + goto mode_fail; + + return 0; + +mode_fail: + dwc3_event_buffers_cleanup(dwc); + +event_fail: + dwc3_core_exit(dwc); + +core_fail: + dwc3_free_event_buffers(dwc); + + return ret; } + int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, uint32_t param){ uint32_t timeout = 500; uint32_t reg; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h index 86dec1910..f047e94c3 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h @@ -888,14 +888,21 @@ void dwc3_cache_hwparams(struct dwc3 *dwc); int dwc3_core_init(struct dwc3 *dwc); +void dwc3_core_exit(struct dwc3 *dwc); + int dwc3_alloc_scratch_buffers(struct dwc3 *dwc); int dwc3_setup_scratch_buffers(struct dwc3 *dwc); int dwc3_alloc_event_buffers(struct dwc3 *dwc, uint32_t length); +void dwc3_free_event_buffers(struct dwc3 *dwc); + int dwc3_event_buffers_setup(struct dwc3 *dwc); +void dwc3_event_buffers_cleanup(struct dwc3 *dwc); + + int dwc3_core_init_mode(struct dwc3 *dwc); void dwc3_set_mode(struct dwc3 *dwc, uint32_t mode); From 5769e988449a0524be2aa84499d6ee30bd24a93b Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 12 Sep 2024 04:33:43 -0700 Subject: [PATCH 181/198] DWC3 scratch buffer functions --- .../drivers/usb/components/port/dwc3/dwc3.c | 45 +++++++++++++++++-- 1 file changed, 42 insertions(+), 3 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c index 73b49f7a7..e733ee7ab 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c @@ -97,7 +97,9 @@ void dwc3_core_exit(struct dwc3 *dwc){ int dwc3_alloc_scratch_buffers(struct dwc3 *dwc){ - uint32_t length; + uint32_t len; + uintptr_t phy_addr, vir_addr; + int ret; if (!dwc->has_hibernation) return 0; @@ -105,15 +107,52 @@ int dwc3_alloc_scratch_buffers(struct dwc3 *dwc){ if (!dwc->nr_scratch) return 0; + len = dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE; + ret = naive_mmap(&vir_addr, &phy_addr, len, true); + if(ret != 0){ + USB_LOG_ERR("could not allocate DWC3 scratch buffers!\n"); + ret = -ENOMEM; + } - return 0; + dwc->scratchbuf = (void *)vir_addr; + dwc->scratch_addr = phy_addr; + + return ret; } int dwc3_setup_scratch_buffers(struct dwc3 *dwc){ - return 0; + uint32_t param; + int ret; + + if (!dwc->has_hibernation) + return 0; + + if (!dwc->nr_scratch) + return 0; + + param = lower_32_bits(dwc->scratch_addr); + + ret = dwc3_send_gadget_generic_command(dwc, + DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); + + if(ret != 0) + goto err_cmd; + + param = upper_32_bits(dwc->scratch_addr); + + ret = dwc3_send_gadget_generic_command(dwc, + DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); + + if(ret != 0) + goto err_cmd; + + return ret; + +err_cmd: + return ret; } From e6f6d3e1dd09c5a038e5dd3eb31b4aa5975397ad Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 12 Sep 2024 04:45:05 -0700 Subject: [PATCH 182/198] DWC3 scratch buffer functions --- .../services/drivers/usb/components/port/dwc3/dwc3.c | 7 ++++++- .../services/drivers/usb/components/port/dwc3/dwc3.h | 2 ++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c index e733ee7ab..17c2c4fbd 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c @@ -108,6 +108,11 @@ int dwc3_alloc_scratch_buffers(struct dwc3 *dwc){ return 0; len = dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE; + + vir_addr = USB_MEM_VIRADDR_ALLOC; + phy_addr = 0; + dwc->scratchbuf = (void *)vir_addr; + ret = naive_mmap(&vir_addr, &phy_addr, len, true); if(ret != 0){ @@ -115,7 +120,7 @@ int dwc3_alloc_scratch_buffers(struct dwc3 *dwc){ ret = -ENOMEM; } - dwc->scratchbuf = (void *)vir_addr; + dwc->scratch_addr = phy_addr; return ret; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h index f047e94c3..b4e6b06cd 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h @@ -896,6 +896,8 @@ int dwc3_setup_scratch_buffers(struct dwc3 *dwc); int dwc3_alloc_event_buffers(struct dwc3 *dwc, uint32_t length); +struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length); + void dwc3_free_event_buffers(struct dwc3 *dwc); int dwc3_event_buffers_setup(struct dwc3 *dwc); From d41cdce316c0dd2c7693c9439f91aac3dfa134b7 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Thu, 12 Sep 2024 20:10:15 +0800 Subject: [PATCH 183/198] Add dwc3_core_init --- .../drivers/usb/components/port/dwc3/dwc3.c | 161 +++++++++++++++++- .../drivers/usb/components/port/dwc3/dwc3.h | 8 + 2 files changed, 168 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c index 17c2c4fbd..bd11f29af 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c @@ -87,8 +87,150 @@ void dwc3_cache_hwparams(struct dwc3 *dwc) -int dwc3_core_init(struct dwc3 *dwc){ +/** + * dwc3_core_init - Low-level initialization of DWC3 Core + * @dwc: Pointer to our controller context structure + * + * Returns 0 on success otherwise negative errno. + */ +int dwc3_core_init(struct dwc3 *dwc) +{ + unsigned long timeout; + uint32_t hwparams4 = dwc->hwparams.hwparams4; + uint32_t reg; + int ret; + + reg = dwc3_readl(dwc->regs_vir, DWC3_GSNPSID); + /* This should read as U3 followed by revision number */ + if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { + USB_LOG_ERR("this is not a DesignWare USB3 DRD Core\n"); + ret = -ENODEV; + goto err0; + } + dwc->revision = reg; + + /* Handle USB2.0-only core configuration */ + if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == + DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { + if (dwc->maximum_speed == USB_SPEED_SUPER) + dwc->maximum_speed = USB_SPEED_HIGH; + } + + /* issue device SoftReset too */ + timeout = 5000; + dwc3_writel(dwc->regs_vir, DWC3_DCTL, DWC3_DCTL_CSFTRST); + while (timeout--) { + reg = dwc3_readl(dwc->regs_vir, DWC3_DCTL); + if (!(reg & DWC3_DCTL_CSFTRST)) + break; + }; + + if (!timeout) { + USB_LOG_ERR("Reset Timed Out\n"); + ret = -ETIMEDOUT; + goto err0; + } + + ret = dwc3_core_soft_reset(dwc); + if (ret) + goto err0; + + if (dwc->revision >= DWC3_REVISION_250A) { + reg = dwc3_readl(dwc->regs_vir, DWC3_GUCTL1); + + if (dwc->maximum_speed == USB_SPEED_HIGH || + dwc->maximum_speed == USB_SPEED_FULL) + reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; + + dwc3_writel(dwc->regs_vir, DWC3_GUCTL1, reg); + } + + reg = dwc3_readl(dwc->regs_vir, DWC3_GCTL); + reg &= ~DWC3_GCTL_SCALEDOWN_MASK; + + switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { + case DWC3_GHWPARAMS1_EN_PWROPT_CLK: + /** + * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an + * issue which would cause xHCI compliance tests to fail. + * + * Because of that we cannot enable clock gating on such + * configurations. + * + * Refers to: + * + * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based + * SOF/ITP Mode Used + */ + if ((dwc->dr_mode == USB_DR_MODE_HOST || + dwc->dr_mode == USB_DR_MODE_OTG) && + (dwc->revision >= DWC3_REVISION_210A && + dwc->revision <= DWC3_REVISION_250A)) + reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; + else + reg &= ~DWC3_GCTL_DSBLCLKGTNG; + break; + case DWC3_GHWPARAMS1_EN_PWROPT_HIB: + /* enable hibernation here */ + dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); + + /* + * REVISIT Enabling this bit so that host-mode hibernation + * will work. Device-mode hibernation is not yet implemented. + */ + reg |= DWC3_GCTL_GBLHIBERNATIONEN; + break; + default: + USB_LOG_DBG("No power optimization available\n"); + } + + /* check if current dwc3 is on simulation board */ + if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { + USB_LOG_DBG("it is on FPGA board\n"); + dwc->is_fpga = true; + } + + if(dwc->disable_scramble_quirk && !dwc->is_fpga) + USB_LOG_WRN("disable_scramble cannot be used on non-FPGA builds\n"); + + if (dwc->disable_scramble_quirk && dwc->is_fpga) + reg |= DWC3_GCTL_DISSCRAMBLE; + else + reg &= ~DWC3_GCTL_DISSCRAMBLE; + + if (dwc->u2exit_lfps_quirk) + reg |= DWC3_GCTL_U2EXIT_LFPS; + + /* + * WORKAROUND: DWC3 revisions <1.90a have a bug + * where the device can fail to connect at SuperSpeed + * and falls back to high-speed mode which causes + * the device to enter a Connect/Disconnect loop + */ + if (dwc->revision < DWC3_REVISION_190A) + reg |= DWC3_GCTL_U2RSTECN; + + dwc3_core_num_eps(dwc); + + dwc3_writel(dwc->regs_vir, DWC3_GCTL, reg); + + dwc3_phy_setup(dwc); + + ret = dwc3_alloc_scratch_buffers(dwc); + if (ret) + goto err0; + + ret = dwc3_setup_scratch_buffers(dwc); + if (ret) + goto err1; + return 0; + +err1: + dwc3_free_scratch_buffers(dwc); + +err0: + return ret; } @@ -96,6 +238,20 @@ void dwc3_core_exit(struct dwc3 *dwc){ } + +int dwc3_core_soft_reset(struct dwc3 *dwc){ + return 0; +} + + +void dwc3_core_num_eps(struct dwc3 *dwc){ +} + + +void dwc3_phy_setup(struct dwc3 *dwc){ +} + + int dwc3_alloc_scratch_buffers(struct dwc3 *dwc){ uint32_t len; uintptr_t phy_addr, vir_addr; @@ -161,6 +317,9 @@ err_cmd: } +void dwc3_free_scratch_buffers(struct dwc3 *dwc){ +} + int dwc3_alloc_event_buffers(struct dwc3 *dwc, uint32_t length){ return 0; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h index b4e6b06cd..e01ea78bf 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h @@ -890,10 +890,18 @@ int dwc3_core_init(struct dwc3 *dwc); void dwc3_core_exit(struct dwc3 *dwc); +int dwc3_core_soft_reset(struct dwc3 *dwc); + +void dwc3_core_num_eps(struct dwc3 *dwc); + +void dwc3_phy_setup(struct dwc3 *dwc); + int dwc3_alloc_scratch_buffers(struct dwc3 *dwc); int dwc3_setup_scratch_buffers(struct dwc3 *dwc); +void dwc3_free_scratch_buffers(struct dwc3 *dwc); + int dwc3_alloc_event_buffers(struct dwc3 *dwc, uint32_t length); struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length); From 62c6017222aba5dedce4e71199acf423469570ea Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Thu, 12 Sep 2024 20:16:58 +0800 Subject: [PATCH 184/198] Tabs go space --- .../drivers/usb/components/port/dwc3/dwc3.c | 154 +++++++++--------- 1 file changed, 77 insertions(+), 77 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c index bd11f29af..8e65f940f 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c @@ -5,49 +5,49 @@ void dwc3_of_parse(struct dwc3 *dwc) { - uint8_t lpm_nyet_threshold; - uint8_t tx_de_emphasis; - uint8_t hird_threshold; + uint8_t lpm_nyet_threshold; + uint8_t tx_de_emphasis; + uint8_t hird_threshold; - /* default to highest possible threshold */ - lpm_nyet_threshold = 0xff; + /* default to highest possible threshold */ + lpm_nyet_threshold = 0xff; - /* default to -3.5dB de-emphasis */ - tx_de_emphasis = 1; + /* default to -3.5dB de-emphasis */ + tx_de_emphasis = 1; - /* - * default to assert utmi_sleep_n and use maximum allowed HIRD - * threshold value of 0b1100 - */ - hird_threshold = 12; + /* + * default to assert utmi_sleep_n and use maximum allowed HIRD + * threshold value of 0b1100 + */ + hird_threshold = 12; - dwc->hsphy_mode = usb_get_phy_mode(dwc->id); + dwc->hsphy_mode = usb_get_phy_mode(dwc->id); - /* xiuos: The parameters are updated according to the dts of RK3568 */ - dwc->has_lpm_erratum = 0; - lpm_nyet_threshold = lpm_nyet_threshold; - dwc->is_utmi_l1_suspend = 0; - hird_threshold = hird_threshold; - dwc->disable_scramble_quirk = 0; - dwc->u2exit_lfps_quirk = 0; - dwc->u2ss_inp3_quirk = 0; - dwc->req_p1p2p3_quirk = 0; - dwc->del_p1p2p3_quirk = 0; - dwc->del_phy_power_chg_quirk = 0; - dwc->lfps_filter_quirk = 0; - dwc->rx_detect_poll_quirk = 0; - dwc->dis_u3_susphy_quirk = 0; - dwc->dis_u2_susphy_quirk = 0; - dwc->dis_enblslpm_quirk = 1; - dwc->dis_u2_freeclk_exists_quirk = 1; - dwc->tx_de_emphasis_quirk = 0; - tx_de_emphasis = tx_de_emphasis; + /* xiuos: The parameters are updated according to the dts of RK3568 */ + dwc->has_lpm_erratum = 0; + lpm_nyet_threshold = lpm_nyet_threshold; + dwc->is_utmi_l1_suspend = 0; + hird_threshold = hird_threshold; + dwc->disable_scramble_quirk = 0; + dwc->u2exit_lfps_quirk = 0; + dwc->u2ss_inp3_quirk = 0; + dwc->req_p1p2p3_quirk = 0; + dwc->del_p1p2p3_quirk = 0; + dwc->del_phy_power_chg_quirk = 0; + dwc->lfps_filter_quirk = 0; + dwc->rx_detect_poll_quirk = 0; + dwc->dis_u3_susphy_quirk = 0; + dwc->dis_u2_susphy_quirk = 0; + dwc->dis_enblslpm_quirk = 1; + dwc->dis_u2_freeclk_exists_quirk = 1; + dwc->tx_de_emphasis_quirk = 0; + tx_de_emphasis = tx_de_emphasis; - dwc->lpm_nyet_threshold = lpm_nyet_threshold; - dwc->tx_de_emphasis = tx_de_emphasis; + dwc->lpm_nyet_threshold = lpm_nyet_threshold; + dwc->tx_de_emphasis = tx_de_emphasis; - dwc->hird_threshold = hird_threshold - | (dwc->is_utmi_l1_suspend << 4); + dwc->hird_threshold = hird_threshold + | (dwc->is_utmi_l1_suspend << 4); } @@ -72,17 +72,17 @@ int dwc3_setup_phy(void *dev, struct phy **array, int *num_phys){ void dwc3_cache_hwparams(struct dwc3 *dwc) { - struct dwc3_hwparams *parms = &dwc->hwparams; + struct dwc3_hwparams *parms = &dwc->hwparams; - parms->hwparams0 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS0); - parms->hwparams1 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS1); - parms->hwparams2 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS2); - parms->hwparams3 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS3); - parms->hwparams4 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS4); - parms->hwparams5 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS5); - parms->hwparams6 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS6); - parms->hwparams7 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS7); - parms->hwparams8 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS8); + parms->hwparams0 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS0); + parms->hwparams1 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS1); + parms->hwparams2 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS2); + parms->hwparams3 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS3); + parms->hwparams4 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS4); + parms->hwparams5 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS5); + parms->hwparams6 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS6); + parms->hwparams7 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS7); + parms->hwparams8 = dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS8); } @@ -265,9 +265,9 @@ int dwc3_alloc_scratch_buffers(struct dwc3 *dwc){ len = dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE; - vir_addr = USB_MEM_VIRADDR_ALLOC; + vir_addr = USB_MEM_VIRADDR_ALLOC; phy_addr = 0; - dwc->scratchbuf = (void *)vir_addr; + dwc->scratchbuf = (void *)vir_addr; ret = naive_mmap(&vir_addr, &phy_addr, len, true); @@ -355,52 +355,52 @@ void dwc3_set_mode(struct dwc3 *dwc, uint32_t mode){ int dwc3_init(struct dwc3 *dwc) { - int ret; + int ret; - dwc3_cache_hwparams(dwc); + dwc3_cache_hwparams(dwc); - ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); - if (ret) { - USB_LOG_ERR("failed to allocate event buffers\n"); - return -ENOMEM; - } + ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); + if (ret) { + USB_LOG_ERR("failed to allocate event buffers\n"); + return -ENOMEM; + } - ret = dwc3_core_init(dwc); - if (ret) { - USB_LOG_ERR("failed to initialize core\n"); - goto core_fail; - } + ret = dwc3_core_init(dwc); + if (ret) { + USB_LOG_ERR("failed to initialize core\n"); + goto core_fail; + } - ret = dwc3_event_buffers_setup(dwc); - if (ret) { - USB_LOG_ERR("failed to setup event buffers\n"); - goto event_fail; - } + ret = dwc3_event_buffers_setup(dwc); + if (ret) { + USB_LOG_ERR("failed to setup event buffers\n"); + goto event_fail; + } - ret = dwc3_core_init_mode(dwc); - if (ret) - goto mode_fail; + ret = dwc3_core_init_mode(dwc); + if (ret) + goto mode_fail; - return 0; + return 0; mode_fail: - dwc3_event_buffers_cleanup(dwc); + dwc3_event_buffers_cleanup(dwc); event_fail: - dwc3_core_exit(dwc); + dwc3_core_exit(dwc); core_fail: - dwc3_free_event_buffers(dwc); + dwc3_free_event_buffers(dwc); - return ret; + return ret; } int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, uint32_t param){ - uint32_t timeout = 500; - uint32_t reg; + uint32_t timeout = 500; + uint32_t reg; dwc3_writel(dwc->regs_vir, DWC3_DGCMDPAR, param); dwc3_writel(dwc->regs_vir, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); @@ -410,14 +410,14 @@ int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, uint32_t pa if(!(reg & DWC3_DGCMD_CMDACT)){ return 0; - } + } timeout--; usb_osal_msleep(1); if(!timeout) return -1; - }while(1); + }while(1); return 0; } \ No newline at end of file From 7d575c4ceafe666e570a3c6cd2d599b29a8f889b Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 12 Sep 2024 05:21:03 -0700 Subject: [PATCH 185/198] DWC3 event buffer functions --- .../drivers/usb/components/port/dwc3/dwc3.c | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c index 8e65f940f..e11ebdf38 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c @@ -322,7 +322,69 @@ void dwc3_free_scratch_buffers(struct dwc3 *dwc){ int dwc3_alloc_event_buffers(struct dwc3 *dwc, uint32_t length){ + int num; + int i; + + num = DWC3_NUM_INT(dwc->hwparams.hwparams1); + dwc->num_event_buffers = num; + + dwc->ev_buffs = usb_malloc(num * sizeof(*dwc->ev_buffs)); + + if (!dwc->ev_buffs) + return -ENOMEM; + + for (i = 0; i < num; i++) { + struct dwc3_event_buffer *evt; + evt = dwc3_alloc_one_event_buffer(dwc, length); + + if(evt == NULL){ + goto err_alloc_evt; + } + dwc->ev_buffs[i] = evt; + } + return 0; + +err_alloc_evt: + i = i - 1; + for(; i >= 0; i--){ + usb_free(dwc->ev_buffs[i]); + } + + return -ENOMEM; +} + + +struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length){ + struct dwc3_event_buffer *evt; + uintptr_t phy_addr, vir_addr; + int ret; + + evt = usb_malloc(sizeof(*evt)); + + if(evt == NULL){ + return NULL; + } + + evt->dwc = dwc; + evt->length = length; + + vir_addr = USB_MEM_VIRADDR_ALLOC; + phy_addr = 0; + evt->buf = (void *)vir_addr; + + ret = naive_mmap(&vir_addr, &phy_addr, length, true); + + if(ret != 0){ + USB_LOG_ERR("could not allocate DWC3 event buffers!\n"); + goto err_evt; + } + + evt->dma = phy_addr; + +err_evt: + usb_free(evt); + return NULL; } @@ -332,6 +394,23 @@ void dwc3_free_event_buffers(struct dwc3 *dwc){ int dwc3_event_buffers_setup(struct dwc3 *dwc){ + struct dwc3_event_buffer *evt; + int n; + + for (n = 0; n < dwc->num_event_buffers; n++) { + evt = dwc->ev_buffs[n]; + + evt->lpos = 0; + + dwc3_writel(dwc->regs_vir, DWC3_GEVNTADRLO(n), + lower_32_bits(evt->dma)); + dwc3_writel(dwc->regs_vir, DWC3_GEVNTADRHI(n), + upper_32_bits(evt->dma)); + dwc3_writel(dwc->regs_vir, DWC3_GEVNTSIZ(n), + DWC3_GEVNTSIZ_SIZE(evt->length)); + dwc3_writel(dwc->regs_vir, DWC3_GEVNTCOUNT(n), 0); + } + return 0; } From ee3bcc6f664c9222d39318b1768c648a6582b89e Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 13 Sep 2024 10:23:25 +0800 Subject: [PATCH 186/198] Add dwc3_core_soft_reset --- .../drivers/usb/components/port/dwc3/dwc3.c | 53 ++++++++++++++++++- 1 file changed, 51 insertions(+), 2 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c index e11ebdf38..ebcc8c518 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c @@ -239,12 +239,61 @@ void dwc3_core_exit(struct dwc3 *dwc){ -int dwc3_core_soft_reset(struct dwc3 *dwc){ +/** + * dwc3_core_soft_reset - Issues core soft reset and PHY reset + * @dwc: pointer to our context structure + */ +int dwc3_core_soft_reset(struct dwc3 *dwc) +{ + uint32_t reg; + + /* Before Resetting PHY, put Core in Reset */ + reg = dwc3_readl(dwc->regs_vir, DWC3_GCTL); + reg |= DWC3_GCTL_CORESOFTRESET; + dwc3_writel(dwc->regs_vir, DWC3_GCTL, reg); + + /* Assert USB3 PHY reset */ + reg = dwc3_readl(dwc->regs_vir, DWC3_GUSB3PIPECTL(0)); + reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; + dwc3_writel(dwc->regs_vir, DWC3_GUSB3PIPECTL(0), reg); + + /* Assert USB2 PHY reset */ + reg = dwc3_readl(dwc->regs_vir, DWC3_GUSB2PHYCFG(0)); + reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; + dwc3_writel(dwc->regs_vir, DWC3_GUSB2PHYCFG(0), reg); + + usb_osal_msleep(100); + + /* Clear USB3 PHY reset */ + reg = dwc3_readl(dwc->regs_vir, DWC3_GUSB3PIPECTL(0)); + reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; + dwc3_writel(dwc->regs_vir, DWC3_GUSB3PIPECTL(0), reg); + + /* Clear USB2 PHY reset */ + reg = dwc3_readl(dwc->regs_vir, DWC3_GUSB2PHYCFG(0)); + reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; + dwc3_writel(dwc->regs_vir, DWC3_GUSB2PHYCFG(0), reg); + + usb_osal_msleep(100); + + /* After PHYs are stable we can take Core out of reset state */ + reg = dwc3_readl(dwc->regs_vir, DWC3_GCTL); + reg &= ~DWC3_GCTL_CORESOFTRESET; + dwc3_writel(dwc->regs_vir, DWC3_GCTL, reg); + return 0; } -void dwc3_core_num_eps(struct dwc3 *dwc){ +void dwc3_core_num_eps(struct dwc3 *dwc) +{ + struct dwc3_hwparams *parms = &dwc->hwparams; + + dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); + dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; + + USB_LOG_DBG("found %d IN and %d OUT endpoints\n", + dwc->num_in_eps, dwc->num_out_eps); } From a854fc28ba6968d54a95ab5e207c3545df451b61 Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 12 Sep 2024 19:58:07 -0700 Subject: [PATCH 187/198] DWC3 event buffer functions --- .../XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c index ebcc8c518..c56c6cdd5 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c @@ -430,6 +430,8 @@ struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned } evt->dma = phy_addr; + + return evt; err_evt: usb_free(evt); From d3c7f1d5c147eabcaedfc739cb5faf4e564502de Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 13 Sep 2024 13:55:28 +0800 Subject: [PATCH 188/198] Add dwc3_phy_setup --- .../drivers/usb/components/port/dwc3/dwc3.c | 116 +++++++++++++++++- .../drivers/usb/components/port/dwc3/dwc3.h | 2 + 2 files changed, 117 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c index c56c6cdd5..1b89e99c6 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c @@ -108,6 +108,7 @@ int dwc3_core_init(struct dwc3 *dwc) goto err0; } dwc->revision = reg; + USB_LOG_DBG("%s dwc revision=%08x\n", __func__, dwc->revision); /* Handle USB2.0-only core configuration */ if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == @@ -297,7 +298,120 @@ void dwc3_core_num_eps(struct dwc3 *dwc) } -void dwc3_phy_setup(struct dwc3 *dwc){ +void dwc3_phy_setup(struct dwc3 *dwc) +{ + uint32_t reg; + + reg = dwc3_readl(dwc->regs_vir, DWC3_GUSB3PIPECTL(0)); + + /* + * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY + * to '0' during coreConsultant configuration. So default value + * will be '0' when the core is reset. Application needs to set it + * to '1' after the core initialization is completed. + */ + if (dwc->revision > DWC3_REVISION_194A) + reg |= DWC3_GUSB3PIPECTL_SUSPHY; + + if (dwc->u2ss_inp3_quirk) + reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; + + if (dwc->req_p1p2p3_quirk) + reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; + + if (dwc->del_p1p2p3_quirk) + reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; + + if (dwc->del_phy_power_chg_quirk) + reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; + + if (dwc->lfps_filter_quirk) + reg |= DWC3_GUSB3PIPECTL_LFPSFILT; + + if (dwc->rx_detect_poll_quirk) + reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; + + if (dwc->tx_de_emphasis_quirk) + reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); + + /* + * RK3568 uboot: For some Rokchip SoCs like RK3588, if the USB3 PHY is suspended + * in U-Boot would cause the PHY initialize abortively in Linux Kernel, + * so disable the DWC3_GUSB3PIPECTL_SUSPHY feature here to fix it. + */ + /*if (dwc->dis_u3_susphy_quirk || CONFIG_IS_ENABLED(ARCH_ROCKCHIP)) + reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;*/ + /* + * Linux: Similarly for DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be + * cleared after power-on reset, and it can be set after core + * initialization. + */ + reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; + + dwc3_writel(dwc->regs_vir, DWC3_GUSB3PIPECTL(0), reg); + + dwc3_hsphy_mode_setup(dwc); + + usb_osal_msleep(100); + + reg = dwc3_readl(dwc->regs_vir, DWC3_GUSB2PHYCFG(0)); + + /* + * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to + * '0' during coreConsultant configuration. So default value will + * be '0' when the core is reset. Application needs to set it to + * '1' after the core initialization is completed. + */ + if (dwc->revision > DWC3_REVISION_194A) + reg |= DWC3_GUSB2PHYCFG_SUSPHY; + + if (dwc->dis_u2_susphy_quirk) + reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; + + if (dwc->dis_enblslpm_quirk) + reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; + + if (dwc->dis_u2_freeclk_exists_quirk) + reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; + + if (dwc->usb2_phyif_utmi_width == 16) { + reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | + DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); + reg |= DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); + reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT); + } + dwc3_writel(dwc->regs_vir, DWC3_GUSB2PHYCFG(0), reg); + + usb_osal_msleep(100); +} + + +void dwc3_hsphy_mode_setup(struct dwc3 *dwc) +{ + enum usb_phy_interface hsphy_mode = dwc->hsphy_mode; + uint32_t reg; + + /* Set dwc3 usb2 phy config */ + reg = dwc3_readl(dwc->regs_vir, DWC3_GUSB2PHYCFG(0)); + + switch (hsphy_mode) { + case USBPHY_INTERFACE_MODE_UTMI: + reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | + DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); + reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | + DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); + break; + case USBPHY_INTERFACE_MODE_UTMIW: + reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | + DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); + reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | + DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); + break; + default: + break; + } + + dwc3_writel(dwc->regs_vir, DWC3_GUSB2PHYCFG(0), reg); } diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h index e01ea78bf..8d9d00c30 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h @@ -896,6 +896,8 @@ void dwc3_core_num_eps(struct dwc3 *dwc); void dwc3_phy_setup(struct dwc3 *dwc); +void dwc3_hsphy_mode_setup(struct dwc3 *dwc); + int dwc3_alloc_scratch_buffers(struct dwc3 *dwc); int dwc3_setup_scratch_buffers(struct dwc3 *dwc); From 014283451a0def97cb66e6ef9da0eeea43e154b6 Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 12 Sep 2024 23:57:41 -0700 Subject: [PATCH 189/198] DWC3 reg size --- .../services/drivers/usb/components/port/xhci/usb_hc_xhci.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h index 8b38fdee8..7f8d60c9c 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h @@ -60,10 +60,11 @@ extern "C" { #define USB3_0_BASE_ADDR 0xFCC00000 #define USB3_1_BASE_ADDR 0xFD000000 #define USB3_ADDR_OFFSET_UPPER_BOUND 0x08000 +#define USB3_DWC3_ADDR_GAP 0x0B00 #define USB3_VIRADDR_BASE 0x0000002000000000ULL #define USB3_0_VIRADDR_BASE USB3_VIRADDR_BASE -#define USB3_1_VIRADDR_BASE USB3_VIRADDR_BASE + USB3_ADDR_OFFSET_UPPER_BOUND +#define USB3_1_VIRADDR_BASE USB3_VIRADDR_BASE + USB3_ADDR_OFFSET_UPPER_BOUND + USB3_DWC3_ADDR_GAP #define USB3_0_INTERRUPT_NO 201 #define USB3_1_INTERRUPT_NO 202 From b9c3e22f5f7f194b4365a478e6477d029cfd947b Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 13 Sep 2024 15:05:40 +0800 Subject: [PATCH 190/198] Modify DWC3 reg size --- .../services/drivers/usb/components/port/xhci/usb_hc_xhci.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h index 7f8d60c9c..f91b3323f 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h @@ -60,7 +60,7 @@ extern "C" { #define USB3_0_BASE_ADDR 0xFCC00000 #define USB3_1_BASE_ADDR 0xFD000000 #define USB3_ADDR_OFFSET_UPPER_BOUND 0x08000 -#define USB3_DWC3_ADDR_GAP 0x0B00 +#define USB3_DWC3_ADDR_GAP 0x0C00 #define USB3_VIRADDR_BASE 0x0000002000000000ULL #define USB3_0_VIRADDR_BASE USB3_VIRADDR_BASE From 7b5369a1f3cd6f40276fa44165c460020ca26579 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 13 Sep 2024 15:31:22 +0800 Subject: [PATCH 191/198] Modify DWC3 reg size to aligned to 4096 --- .../services/drivers/usb/components/port/xhci/usb_hc_xhci.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h index f91b3323f..4dbd3fe10 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h @@ -60,7 +60,11 @@ extern "C" { #define USB3_0_BASE_ADDR 0xFCC00000 #define USB3_1_BASE_ADDR 0xFD000000 #define USB3_ADDR_OFFSET_UPPER_BOUND 0x08000 -#define USB3_DWC3_ADDR_GAP 0x0C00 +/* + * The size of all DWC3 registers (including OTG regs) is 0xC00. However, the XiZi AIOT requires the I/O memory size to be aligned to 4096. + * So we define USB3_DWC3_ADDR_GAP as 0x01000. + */ +#define USB3_DWC3_ADDR_GAP 0x01000 #define USB3_VIRADDR_BASE 0x0000002000000000ULL #define USB3_0_VIRADDR_BASE USB3_VIRADDR_BASE From 0027373c8652c8136ed3a2cac351ee29a700fa7b Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Sat, 14 Sep 2024 09:25:51 +0800 Subject: [PATCH 192/198] dwc3 init direction mode --- .../drivers/usb/components/port/dwc3/dwc3.c | 29 ++++++++++++++++--- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c index 1b89e99c6..d0283a172 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c @@ -585,18 +585,39 @@ void dwc3_event_buffers_cleanup(struct dwc3 *dwc){ -int dwc3_core_init_mode(struct dwc3 *dwc){ +int dwc3_core_init_mode(struct dwc3 *dwc) +{ + int ret; + + switch (dwc->dr_mode) { + case USB_DR_MODE_HOST: + dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); + ret = dwc3_host_init(dwc); + if (ret) { + USB_LOG_ERR("failed to initialize host\n"); + return ret; + } + break; + default: + USB_LOG_ERR("Unsupported mode of operation %d\n", dwc->dr_mode); + return -EINVAL; + } + return 0; } +void dwc3_set_mode(struct dwc3 *dwc, uint32_t mode) +{ + u32 reg; -void dwc3_set_mode(struct dwc3 *dwc, uint32_t mode){ - + reg = dwc3_readl(dwc->regs_vir, DWC3_GCTL); + reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); + reg |= DWC3_GCTL_PRTCAPDIR(mode); + dwc3_writel(dwc->regs_vir, DWC3_GCTL, reg); } - int dwc3_init(struct dwc3 *dwc) { int ret; From 7c9d76b6afcf5a8914b8b7b610b0a1df10f878cf Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Sat, 14 Sep 2024 10:22:19 +0800 Subject: [PATCH 193/198] Add dwc3_dump --- .../drivers/usb/components/port/dwc3/dwc3.c | 37 ++++++++++++++++++- 1 file changed, 35 insertions(+), 2 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c index d0283a172..f15235942 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c @@ -609,7 +609,7 @@ int dwc3_core_init_mode(struct dwc3 *dwc) void dwc3_set_mode(struct dwc3 *dwc, uint32_t mode) { - u32 reg; + uint32_t reg; reg = dwc3_readl(dwc->regs_vir, DWC3_GCTL); reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); @@ -646,6 +646,8 @@ int dwc3_init(struct dwc3 *dwc) if (ret) goto mode_fail; + dwc3_dump(dwc); + return 0; mode_fail: @@ -685,4 +687,35 @@ int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, uint32_t pa }while(1); return 0; -} \ No newline at end of file +} + +void dwc3_dump(struct dwc3 *dwc) +{ + USB_LOG_DBG("%s regs=%08lx regs_vir=%08lx\n", __func__, dwc->regs, dwc->regs_vir ); + + USB_LOG_DBG("%04x: %08x\n", DWC3_GSBUSCFG0, dwc3_readl(dwc->regs_vir, DWC3_GSBUSCFG0) ); + USB_LOG_DBG("%04x: %08x\n", DWC3_GCTL, dwc3_readl(dwc->regs_vir, DWC3_GCTL) ); + USB_LOG_DBG("%04x: %08x\n", DWC3_GUCTL1, dwc3_readl(dwc->regs_vir, DWC3_GUCTL1) ); + USB_LOG_DBG("%04x: %08x\n", DWC3_GSNPSID, dwc3_readl(dwc->regs_vir, DWC3_GSNPSID) ); + + USB_LOG_DBG("%04x: %08x\n", DWC3_GHWPARAMS0, dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS0) ); + USB_LOG_DBG("%04x: %08x\n", DWC3_GHWPARAMS1, dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS1) ); + USB_LOG_DBG("%04x: %08x\n", DWC3_GHWPARAMS2, dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS2) ); + USB_LOG_DBG("%04x: %08x\n", DWC3_GHWPARAMS3, dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS3) ); + USB_LOG_DBG("%04x: %08x\n", DWC3_GHWPARAMS4, dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS4) ); + USB_LOG_DBG("%04x: %08x\n", DWC3_GHWPARAMS5, dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS5) ); + USB_LOG_DBG("%04x: %08x\n", DWC3_GHWPARAMS6, dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS6) ); + USB_LOG_DBG("%04x: %08x\n", DWC3_GHWPARAMS7, dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS7) ); + + USB_LOG_DBG("%04x: %08x\n", DWC3_GUSB2PHYCFG(0), dwc3_readl(dwc->regs_vir, DWC3_GUSB2PHYCFG(0)) ); + USB_LOG_DBG("%04x: %08x\n", DWC3_GUSB3PIPECTL(0), dwc3_readl(dwc->regs_vir, DWC3_GUSB3PIPECTL(0)) ); + USB_LOG_DBG("%04x: %08x\n", DWC3_GEVNTADRLO(0), dwc3_readl(dwc->regs_vir, DWC3_GEVNTADRLO(0)) ); + USB_LOG_DBG("%04x: %08x\n", DWC3_GEVNTADRHI(0), dwc3_readl(dwc->regs_vir, DWC3_GEVNTADRHI(0)) ); + + USB_LOG_DBG("%04x: %08x\n", DWC3_GHWPARAMS8, dwc3_readl(dwc->regs_vir, DWC3_GHWPARAMS8) ); + + USB_LOG_DBG("%04x: %08x\n", DWC3_DCTL, dwc3_readl(dwc->regs_vir, DWC3_DCTL) ); + USB_LOG_DBG("%04x: %08x\n", DWC3_DGCMDPAR, dwc3_readl(dwc->regs_vir, DWC3_DGCMDPAR) ); + USB_LOG_DBG("%04x: %08x\n", DWC3_DGCMD, dwc3_readl(dwc->regs_vir, DWC3_DGCMD) ); +} + From 332bb5b870f2ed2aa4d0a19091b1f6d98f122921 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Sat, 14 Sep 2024 15:29:05 +0800 Subject: [PATCH 194/198] Modify dwc3_dump --- .../XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h | 1 + 1 file changed, 1 insertion(+) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h index 8d9d00c30..40a688b8c 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h @@ -923,6 +923,7 @@ int dwc3_host_init(struct dwc3 *dwc); int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, uint32_t param); +void dwc3_dump(struct dwc3 *dwc); static inline uint32_t dwc3_readl(void *base, uint32_t offset){ uintptr_t offs = offset - DWC3_GLOBALS_REGS_START; From 7000c5cd18918546a4996f39ba880fd02be0c296 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 20 Sep 2024 19:28:42 +0800 Subject: [PATCH 195/198] According to ARMv8 architecture, the IRQ should be enable by calling gic_setup_spi when the NO. is larger than 31. --- .../intr/arm/armv8-a/cortex-a55/3568/trap_common.c | 7 ++++++- Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_register_irq.c | 6 ++++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/trap_common.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/trap_common.c index 354e2d2ee..1c2ca1a1d 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/trap_common.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/trap_common.c @@ -70,7 +70,12 @@ static void _cpu_irq_disable(void) static void _single_irq_enable(int irq, int cpu, int prio) { - gic_setup_ppi((uint32_t)cpu, (uint32_t)irq); + if (irq < 32) { + gic_setup_ppi((uint32_t)cpu, (uint32_t)irq); + } + else { + gic_setup_spi((uint32_t)cpu, (uint32_t)irq); + } } static void _single_irq_disable(int irq, int cpu) diff --git a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_register_irq.c b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_register_irq.c index 38a19bcff..91c3ac6c8 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_register_irq.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_register_irq.c @@ -104,6 +104,8 @@ extern struct session_backend* create_session_inner(struct Thread* client, struc static struct XiziTrapDriver* p_intr_driver = NULL; int sys_register_irq(int irq_num, int irq_opcode) { + int cpu_id; + // init intr resource; if (p_intr_driver == NULL) { struct TraceTag intr_ac_tag; @@ -140,6 +142,10 @@ int sys_register_irq(int irq_num, int irq_opcode) p_intr_driver->bind_irq_handler(irq_num, user_irq_handler); cur_task->bind_irq = true; + // enable irq + cpu_id = p_intr_driver->cur_cpu_id(); + p_intr_driver->single_irq_enable(irq_num, cpu_id, 0); + return 0; } From da16c4f01ccacd5e95d4c49b9f5bee51a1ac9224 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 24 Sep 2024 17:16:34 +0800 Subject: [PATCH 196/198] Modify xhci debug log --- .../services/drivers/usb/components/port/xhci/xhci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c index 45f5a9145..fe7c96ebd 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/xhci.c @@ -776,7 +776,7 @@ static int xhci_scratchpad_alloc ( struct xhci_host *xhci ) { rc = -ENOMEM; goto err_alloc; } - USB_LOG_DBG("xhci_scratchpad_alloc vir_addr=%lx phy_addr=%08lx\n", vir_addr, phy_addr); + USB_LOG_DBG("xhci_scratchpad_alloc vir_addr=%lx phy_addr=%08lx\n", scratch->array_addr, phy_addr); memset(scratch->array_addr, 0, array_len); scratch->array_phy = phy_addr; @@ -907,7 +907,7 @@ static int xhci_command_alloc ( struct xhci_host *xhci ) { rc = -ENOMEM; goto err_ring_alloc; } - USB_LOG_DBG("xhci_command_alloc cmds_addr=%lx cmds_phy=%08lx\n", cmds_addr, cmds_phy); + USB_LOG_DBG("xhci_command_alloc cmds_addr=%lx cmds_phy=%08lx\n", xhci->cmds_addr, cmds_phy); xhci->cmds_phy = cmds_phy; From 2425a2a12eb0dc8c890fdb4c3bd34e480c49feae Mon Sep 17 00:00:00 2001 From: xj Date: Thu, 24 Oct 2024 23:13:37 -0700 Subject: [PATCH 197/198] codes for MAIR supporting --- .../cortex-a55/preboot_for_3568/boot.S | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/boot.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/boot.S index bf9535a90..ed4eedd2a 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/boot.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/boot.S @@ -15,10 +15,21 @@ #define SPSR_EL2_VALUE (7 << 6) | (5 << 0) #define SCTLR_EL1_VALUE (0x30D00800) +/* Macros for MAIR setting. */ +#define MAIR(attr, mt) ((attr) << ((mt) * 8)) +#define MT_DEVICE_nGnRnE 0 +#define MT_DEVICE_nGnRE 1 +#define MT_DEVICE_GRE 2 +#define MT_NORMAL_NC 3 +#define MT_NORMAL 4 +#define MT_NORMAL_WT 5 + .section ".text", "ax" .global _boot_start .global primary_cpu_init .global el2_setup +/* The function for setting memory types and MAIR registers. */ +.global __cpu_mair_setup _boot_start: bl el2_setup @@ -53,6 +64,7 @@ _boot_start: mov x5, x2 cmp x5, #0 beq primary_cpu_init + bl __cpu_mair_setup bl bootmain // for secondary cpus, jump to argument function pointer passed in by ROM bl . @@ -68,6 +80,7 @@ primary_cpu_init: stp x3, x3, [x1], #16 b.lt 1b + bl __cpu_mair_setup bl bootmain .func el2_setup @@ -117,4 +130,39 @@ el2_setup: eret .endfunc + .func __cpu_mair_setup +__cpu_mair_setup: + tlbi vmalle1 // Invalidate local TLB + dsb nsh + + mov x0, #3 << 20 + msr cpacr_el1, x0 // Enable FP/ASIMD + mov x0, #1 << 12 // Reset mdscr_el1 and disable + msr mdscr_el1, x0 // access to the DCC from EL0 + isb // Unmask debug exceptions now, +// enable_dbg // since this is per-cpu + /* + * Memory region attributes for LPAE: + * + * n = AttrIndx[2:0] + * n MAIR + * DEVICE_nGnRnE 000 00000000 + * DEVICE_nGnRE 001 00000100 + * DEVICE_GRE 010 00001100 + * NORMAL_NC 011 01000100 + * NORMAL 100 11111111 + * NORMAL_WT 101 10111011 + */ + ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \ + MAIR(0x04, MT_DEVICE_nGnRE) | \ + MAIR(0x0c, MT_DEVICE_GRE) | \ + MAIR(0x44, MT_NORMAL_NC) | \ + MAIR(0xff, MT_NORMAL) | \ + MAIR(0xbb, MT_NORMAL_WT) + msr mair_el1, x5 + + eret + .endfunc + + .end \ No newline at end of file From 8ad7409aae64e412910e98f09d977d85b25bda58 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 25 Oct 2024 15:33:06 +0800 Subject: [PATCH 198/198] Modify cpu mair setup --- .../arm/armv8-a/cortex-a55/preboot_for_3568/boot.S | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/boot.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/boot.S index ed4eedd2a..4509ddcbe 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/boot.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/boot.S @@ -135,10 +135,10 @@ __cpu_mair_setup: tlbi vmalle1 // Invalidate local TLB dsb nsh - mov x0, #3 << 20 - msr cpacr_el1, x0 // Enable FP/ASIMD - mov x0, #1 << 12 // Reset mdscr_el1 and disable - msr mdscr_el1, x0 // access to the DCC from EL0 +// mov x0, #3 << 20 +// msr cpacr_el1, x0 // Enable FP/ASIMD +// mov x0, #1 << 12 // Reset mdscr_el1 and disable +// msr mdscr_el1, x0 // access to the DCC from EL0 isb // Unmask debug exceptions now, // enable_dbg // since this is per-cpu /* @@ -161,7 +161,7 @@ __cpu_mair_setup: MAIR(0xbb, MT_NORMAL_WT) msr mair_el1, x5 - eret + ret .endfunc